182 lines
5.4 KiB
C
182 lines
5.4 KiB
C
#include "dev_profile.h"
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#include "spi.h"
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#include "../config/app_config.h"
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#include "../drivers/frequency/lmx2594/lmx2594.h"
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#include "../drivers/axi_core/spi_engine/spi_engine.h"
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#include "../drivers/platform/xilinx_gpio.h"
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static struct spi_engine_init_param spi_engine_param = {
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.ref_clk_hz = AD9653_SPI_ENGINE_REF_CLK,
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.type = SPI_ENGINE,
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.spi_engine_baseaddr = AD9653_SPI_ENGINE_BASEADDR,
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.cs_delay = AD9653_SPI_ENGINE_CS_DELAY,
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.data_width = AD9653_SPI_ENGINE_DATA_WIDTH
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};
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//static struct xil_gpio_init_param xil_gpio_param = {
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// .type = GPIO_PS,
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// .device_id = AD9653_GPIO_DEVICE_ID
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//};
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static struct spi_init_param lmx2594_adc_spi_init = {
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.device_id = LMX2594_ADC_SPI_DEVICE_ID,
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.max_speed_hz = LMX2594_ADC_SPI_ENGINE_MAX_SPEED,
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.mode = SPI_MODE_0,
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.chip_select = LMX2594_ADC_SPI_CS,
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.platform_ops = &spi_eng_platform_ops,
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.extra = &spi_engine_param
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};
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static struct spi_init_param lmx2594_dac_spi_init = {
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.device_id = LMX2594_DAC_SPI_DEVICE_ID,
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.max_speed_hz = LMX2594_DAC_SPI_ENGINE_MAX_SPEED,
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.mode = SPI_MODE_0,
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.chip_select = LMX2594_DAC_SPI_CS,
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.platform_ops = &spi_eng_platform_ops,
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.extra = &spi_engine_param
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};
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struct lmx2594_init_param lmx2594_adc_init_param = {
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/* SPI */
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.spi_init = &lmx2594_adc_spi_init
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};
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struct lmx2594_init_param lmx2594_dac_init_param = {
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/* SPI */
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.spi_init = &lmx2594_dac_spi_init
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};
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const uint32_t lmx2594_default_config_len = 110;
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const struct lmx2594_config lmx2594_default_config[] = {
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// 0 ~ 78: General configuration
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// 79 ~ 106: Ramping configuration
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// 107 ~ 112: Readback registers
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// Recommended Initial Power-Up Sequence
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// For the most reliable programming, TI recommends this procedure::
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// 1. Apply power to device.
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// 2. Program RESET = 1 to reset registers.
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// 3. Program RESET = 0 to remove reset.
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// 4. Program registers as shown in the register map in REVERSE order from highest to lowest.
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// 5. Wait 10 ms.
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// 6. Program register R0 one additional time with FCAL_EN = 1 to ensure that the VCO calibration runs from a stable state.
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// Reset
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{ 0, 0x0002},
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// Remove Reset
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{ 0, 0x0000},
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// Reverse order programming
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{106, 0x0000},
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{105, 0x0021},
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{104, 0x0000},
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{103, 0xD555},
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{102, 0x3F97},
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{101, 0x0011},
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{100, 0x0000},
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{ 99, 0x2AAB},
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{ 98, 0x01A0},
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{ 97, 0x0888},
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{ 96, 0x0000},
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{ 95, 0x0000}, // fixed
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{ 94, 0x0000}, // fixed
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{ 93, 0x0000}, // fixed
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{ 92, 0x0000}, // fixed
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{ 91, 0x0000}, // fixed
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{ 90, 0x0000}, // fixed
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{ 89, 0x0000}, // fixed
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{ 88, 0x0000}, // fixed
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{ 87, 0x0000}, // fixed
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{ 86, 0x5879},
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{ 85, 0xEC58},
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{ 84, 0x0001},
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{ 83, 0x54C9},
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{ 82, 0x2961},
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{ 81, 0x0000},
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{ 80, 0x4000},
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{ 79, 0x001F},
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{ 78, 0x0003}, // [8:1] VCO_CAPCTRL_STRT
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{ 77, 0x0000}, // fixed
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{ 76, 0x000C}, // fixed
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{ 75, 0x0800}, // [10:6] CHDIV
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{ 74, 0x0000}, // [11:6] JESD_DAC4_CTRL; [5:0] JESD_DAC3_CTRL
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{ 73, 0x003F}, // [11:6] JESD_DAC2_CTRL; [5:0] JESD_DAC1_CTRL
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{ 72, 0x0001}, // [10:0] SYSREF_DIV
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{ 71, 0x0081}, // [7:5] SYSREF_DIV_PRE; [4] SYSREF_PULSE; [3] SYSREF_EN; [2] SYSREF_REPEAT
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{ 70, 0xC350}, // [15:0] MASH_RST_COUNT
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{ 69, 0x0000}, // [15:0] MASH_RST_COUNT
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{ 68, 0x03E8}, // fixed
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{ 67, 0x0000}, // fixed
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{ 66, 0x01F4}, // fixed
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{ 65, 0x0000}, // fixed
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{ 64, 0x1388}, // fixed
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{ 63, 0x0000}, // fixed
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{ 62, 0x0322}, // fixed
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{ 61, 0x00A8}, // fixed
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{ 60, 0x0000}, // [15:0] LD_DLY
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{ 59, 0x0001}, // [0] LD_TYPE
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{ 58, 0x9001}, // [15] INPIN_IGNORE; [14] INPIN_HYST; [13:12] INPIN_LVL; [11:9] INPIN_FMT
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{ 57, 0x0020}, // fixed
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{ 56, 0x0000}, // fixed
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{ 55, 0x0000}, // fixed
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{ 54, 0x0000}, // fixed
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{ 53, 0x0000}, // fixed
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{ 52, 0x0820}, // fixed
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{ 51, 0x0080}, // fixed
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{ 50, 0x0000}, // fixed
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{ 49, 0x4180}, // fixed
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{ 48, 0x0300}, // fixed
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{ 47, 0x0300}, // fixed
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{ 46, 0x07FC}, // [1:0] OUTB_MUX
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{ 45, 0xC0DF}, // [12:11] OUTA_MUX; [10:9] OUT_ISET; [5:0] OUTB_PWR
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{ 44, 0x1AA3}, // [13:8] OUTA_PWR; [7] OUTB_PD; [6] OUTA_PD; [5] MASH_RESET_N; [2:0] MASH_ORDER
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{ 43, 0x0000}, // [15:0] PLL_NUM
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{ 42, 0x0000}, // [15:0] PLL_NUM
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{ 41, 0x0000}, // [15:0] MASH_SEE
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{ 40, 0x0000}, // [15:0] MASH_SEE
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{ 39, 0x03E8}, // [15:0] PLL_DEN
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{ 38, 0x0000}, // [15:0] PLL_DEN
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{ 37, 0x0304}, // [37] MASH_SEED_EN; [13:8] PFD_DLY_SEL
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{ 36, 0x0028}, // [15:0] PLL_N
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{ 35, 0x0004}, // fixed
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{ 34, 0x0000}, // [2:0] PLL_N
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{ 33, 0x1E21}, // fixed
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{ 32, 0x0393}, // fixed
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{ 31, 0x43EC}, // [14] SEG1_EN
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{ 30, 0x318C}, // fixed
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{ 29, 0x318C}, // fixed
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{ 28, 0x0488}, // fixed
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{ 27, 0x0002}, // fixed
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{ 26, 0x0DB0}, // fixed
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{ 25, 0x0C2B}, // fixed
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{ 24, 0x071A}, // fixed
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{ 23, 0x007C}, // fixed
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{ 22, 0x0001}, // fixed
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{ 21, 0x0401}, // fixed
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{ 20, 0xE048}, // [13:11] VCO_SEL. [10] VCO_SEL_FORCE
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{ 19, 0x27B7}, // [7:0] VCO_CAPCTRL
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{ 18, 0x0064}, // fixed
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{ 17, 0x012C}, // [8:0] VCO_DACISET_STRT
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{ 16, 0x0080}, // [8:0] VCO_DACISET
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{ 15, 0x064F}, // fixed
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{ 14, 0x1E70}, // [6:4] CPG
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{ 13, 0x4000}, // fixed
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{ 12, 0x5001}, // [11:0] PLL_R_PR
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{ 11, 0x0018}, // [11:4] PLL_R
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{ 10, 0x10D8}, // [11:7] MULT
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{ 9, 0x0604}, // [12] OSC_2X
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{ 8, 0x2000}, // [14] VCO_DACISET_FORCE; [11] VCO_CAPCTRL_FORCE
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{ 7, 0x40B2}, // [14] OUT_FORCE
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{ 6, 0xC802}, // fixed
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{ 5, 0x00C8}, // fixed
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{ 4, 0x0C43}, // [15:8] ACAL_CMP_DLY
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{ 3, 0x0642}, // fixed
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{ 2, 0x0500}, // fixed
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{ 1, 0x0809}, // [2:0] CAL_CLK_DIV
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{ 0, 0x2598}, // [15] RAMP_EN; [14] VCO_PHASE_SYNC; [9] OUT_MUTE; [8:7] FCAL_HPFD_ADJ; [6:5] FCAL_LPFD_ADJ; [3] FCAL_EN; [2] MUXOUT_LD_SEL; [1] RESET; [0] POWERDOWN
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// one more time
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{ 0, 0x2598}
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};
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