Gatsby Van
3470b6f6dc
* merge GE code * update fold structure * enable to build two types of projects separately
708 lines
39 KiB
C
708 lines
39 KiB
C
/**
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* \file mykonos_macros.h
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* \brief Contains address and miscellaneous macro definitions for Mykonos API
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*
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* Mykonos API version: 1.5.2.3566
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*/
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/**
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* \page Disclaimer Legal Disclaimer
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* Copyright 2015-2017 Analog Devices Inc.
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* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
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*
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*/
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#ifndef CLEMENTE_TDD_MACROS_H
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#define CLEMENTE_TDD_MACROS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MYKONOS_ADDR_CONFIGURATION_CONTROL_0 0x000
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#define MYKONOS_ADDR_SPI_CONFIGURATION_CONTROL_1 0x001
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#define MYKONOS_ADDR_PRODUCT_ID 0x004
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#define MYKONOS_GPIO_DRV_CTL_0 0x020
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#define MYKONOS_GPIO_DRV_CTL_1 0x021
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#define MYKONOS_GPIO_SLEW_CTL_0 0x022
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#define MYKONOS_GPIO_SLEW_CTL_1 0x023
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#define MYKONOS_GPIO_SLEW_CTL_2 0x024
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#define MYKONOS_GPIO_SLEW_CTL_3 0x025
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#define MYKONOS_ADDR_DIGITAL_IO_CONTROL 0x028
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#define MYKONOS_ADDR_SYSREF_PAD_CONFIG 0x040
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#define MYKONOS_ADDR_TX1_SYNC_PAD_CONFIG 0x041
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#define MYKONOS_ADDR_TX2_SYNC_PAD_CONFIG 0x042
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#define MYKONOS_ADDR_RX1_SYNC_CONFIG 0x043
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#define MYKONOS_ADDR_RX2_SYNC_CONFIG 0x044
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/* Mykonos Framer Registers */
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#define MYKONOS_ADDR_FRAMER_RESET 0x059
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#define MYKONOS_ADDR_FRAMER_CLK_EN 0x05A
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#define MYKONOS_ADDR_FRAMER_ADDR 0x05B
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#define MYKONOS_ADDR_FRAMER_DATA 0x05C
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#define MYKONOS_ADDR_FRAMER_WRITE_EN 0x05D
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#define MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN 0x05E
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#define MYKONOS_ADDR_FRAMER_CONFIG_F 0x05F
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#define MYKONOS_ADDR_FRAMER_LANE_CTL 0x060
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#define MYKONOS_ADDR_FRAMER_ADC_XBAR_SEL 0x061
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#define MYKONOS_ADDR_FRAMER_LANE_XBAR_SEL 0x062
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#define MYKONOS_ADDR_FRAMER_CONFIG_LOOPBACK_XBAR_REV 0x063
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#define MYKONOS_ADDR_FRAMER_SYNCN_FILT 0x064
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#define MYKONOS_ADDR_FRAMER_LMFC_F_OFFSET 0x065
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#define MYKONOS_ADDR_FRAMER_LMFC_K_OFFSET 0x066
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#define MYKONOS_ADDR_FRAMER_TEST_CNTR_CTL 0x067
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#define MYKONOS_ADDR_FRAMER_STATUS_STRB 0x068
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#define MYKONOS_ADDR_FRAMER_STATUS 0x069
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#define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_CNTR_STAT 0x06A
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#define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0x06B
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#define MYKONOS_ADDR_FRAMER_LANE_FIFO_STRB 0x06C
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#define MYKONOS_ADDR_FRAMER_LANE0_FIFO_RDWR_ADDR 0x06D
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#define MYKONOS_ADDR_FRAMER_LANE1_FIFO_RDWR_ADDR 0x06E
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#define MYKONOS_ADDR_FRAMER_LANE2_FIFO_RDWR_ADDR 0x06F
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#define MYKONOS_ADDR_FRAMER_LANE3_FIFO_RDWR_ADDR 0x070
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#define MYKONOS_ADDR_FRAMER_PRBS10_CTL 0x071
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#define MYKONOS_ADDR_FRAMER_PRBS20_CTL 0x072
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#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_EN 0x073
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#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_7_TO_0 0x074
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#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_15_TO_8 0x075
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#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_19_TO_16 0x076
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#define MYKONOS_ADDR_FRAMER_CONFIG_JTX_GEN 0x077
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#define MYKONOS_ADDR_FRAMER_LANE_DATA_CTL 0x078
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#define MYKONOS_ADDR_FRAMER_DATA_SAMPLE_CTL 0x079
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/* Mykonos Deframer Sub Address Map */
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#define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_RECVD 0x00
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#define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_CFG 0x50
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/* Mykonos Deframer Registers */
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#define MYKONOS_ADDR_DEFRAMER_RESET 0x07A
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#define MYKONOS_ADDR_DEFRAMER_CLK_EN 0x07B
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#define MYKONOS_ADDR_DEFRAMER_ADDR 0x07C
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#define MYKONOS_ADDR_DEFRAMER_DATA 0x07D
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#define MYKONOS_ADDR_DEFRAMER_WR_EN 0x07E
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#define MYKONOS_ADDR_DEFRAMER_SYSREF_FIFO_EN 0x07F
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#define MYKONOS_ADDR_DEFRAMER_CONFIG_F 0x080
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#define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_CTL 0x081
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#define MYKONOS_ADDR_DEFRAMER_DAC_XBAR_SEL 0x082
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#define MYKONOS_ADDR_DEFRAMER_LANE_XBAR_SEL 0x083
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#define MYKONOS_ADDR_DEFRAMER_LMFC_F_OFFSET 0x084
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#define MYKONOS_ADDR_DEFRAMER_LMFC_K_OFFSET 0x085
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#define MYKONOS_ADDR_DEFRAMER_CONFIG_SYNC_USER_DATA_CTL 0x086
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#define MYKONOS_ADDR_DEFRAMER_SYNC_REQ_RETIME 0x087
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#define MYKONOS_ADDR_DEFRAMER_TEST 0x088
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#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_STRT_DAC_XBAR_REV 0x089
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#define MYKONOS_ADDR_DEFRAMER_STAT_STRB 0x08A
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#define MYKONOS_ADDR_DEFRAMER_STAT 0x08B
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#define MYKONOS_ADDR_DEFRAMER_TEST_ERR_CNT_STAT 0x08C
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#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_RD_ADDR 0x08D
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#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_ADDR 0x08E
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#define MYKONOS_ADDR_DEFRAMER_QBLMFC_VS_EXTLMFC_CNTR_STAT 0x08F
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#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_STAT 0x090
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#define MYKONOS_ADDR_DEFRAMER_STRT_RD_DEL_STOP_WR 0x091
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#define MYKONOS_ADDR_DEFRAMER_FIFO_SAMPLE_SPI_ADDR_RD 0x092
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#define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_ADDR_RD 0x093
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#define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_DATA_RD 0x094
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#define MYKONOS_ADDR_DEFRAMER_SAMPLE0_7_TO_0 0x095
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#define MYKONOS_ADDR_DEFRAMER_SAMPLE0_15_TO_8 0x096
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#define MYKONOS_ADDR_DEFRAMER_SAMPLE1_7_TO_0 0x097
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#define MYKONOS_ADDR_DEFRAMER_SAMPLE1_15_TO_8 0x098
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#define MYKONOS_ADDR_DEFRAMER_SAMPLE2_7_TO_0 0x099
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#define MYKONOS_ADDR_DEFRAMER_SAMPLE2_15_TO_8 0x09A
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#define MYKONOS_ADDR_DEFRAMER_SAMPLE3_7_TO_0 0x09B
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#define MYKONOS_ADDR_DEFRAMER_SAMPLE3_15_TO_8 0x09C
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#define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_STRB 0x09D
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#define MYKONOS_ADDR_DEFRAMER_LANE0_FIFO_RDWR_ADDR 0x09E
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#define MYKONOS_ADDR_DEFRAMER_LANE1_FIFO_RDWR_ADDR 0x09F
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#define MYKONOS_ADDR_DEFRAMER_LANE2_FIFO_RDWR_ADDR 0x0A0
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#define MYKONOS_ADDR_DEFRAMER_LANE3_FIFO_RDWR_ADDR 0x0A1
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#define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_CNTR_STAT 0x0A2
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#define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0x0A3
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#define MYKONOS_ADDR_DEFRAMER_PRBS10_CTL 0x0A4
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#define MYKONOS_ADDR_DEFRAMER_PRBS20_CTL 0x0A5
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#define MYKONOS_ADDR_DEFRAMER_PRBS20_STRB_CHKSUM_TYPE 0x0A6
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#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_7_TO_0 0x0A7
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#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_15_TO_8 0x0A8
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#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_23_TO_16 0x0A9
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#define MYKONOS_ADDR_DEFRAMER_LANE_DATA_CTL 0x0AA
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#define MYKONOS_ADDR_DEFRAMER_STATUS_2 0x0AB
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#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_PHASE 0x0AC
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/* Mykonos Serializer Registers */
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#define MYKONOS_ADDR_SERIALIZER_CTL_0 0x0B0
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#define MYKONOS_ADDR_SERIALIZER_CTL_1 0x0B1
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#define MYKONOS_ADDR_SERIALIZER_CTL_2 0x0B2
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#define MYKONOS_ADDR_SERIALIZER_CTL_3 0x0B3
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#define MYKONOS_ADDR_SERIALIZER_HS_DIV_TXSER_CLK_EN 0x0B4
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#define MYKONOS_ADDR_SERIALIZER_SPECIAL 0x0B5
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/* Mykonos Deserializer Registers */
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#define MYKONOS_ADDR_DESERIALIZER_PDET_CTL 0x0BC
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#define MYKONOS_ADDR_DESERIALIZER_CTL_0 0x0BD
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#define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_0 0x0BE
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#define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_1 0x0BF
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#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_0 0x0C1
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#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1 0x0C2
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#define MYKONOS_ADDR_DESERIALIZER_MISC_CTL 0x0C3
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#define MYKONOS_ADDR_DESERIALIZER_EQ_HP_EN 0x0C4
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#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1_TO_0 0x0C5
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#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_3_TO_2 0x0C6
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#define MYKONOS_ADDR_DESERIALIZER_HS_DIV_RXCDR_CLK_EN 0x0CD
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#define MYKONOS_ADDR_DESERIALIZER_SPECIAL 0x0CE
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#define MYKONOS_ADDR_DESERIALIZER_CDR_CAL_CTL 0x0D0
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#define MYKONOS_ADDR_CONFIGURATION_CONTROL_1 0x100
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#define MYKONOS_ADDR_CONFIGURATION_CONTROL_2 0x101
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#define MYKONOS_ADDR_CONFIGURATION_CONTROL_4 0x102
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#define MYKONOS_ADDR_CONFIGURATION_CONTROL_5 0x103
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#define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_1 0x104
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#define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_2 0x105
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#define MYKONOS_ADDR_DPD_SNIFFER_GPIO_SELECT 0x106
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#define MYKONOS_ADDR_SNIFFER_CONFIGURATION_CONTROL 0x107
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#define MYKONOS_ADDR_DPD_CONFIGURATION_CONTROL 0x108
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#define MYKONOS_ADDR_LOOPBACK_CONFIGURATION_CONTROL 0x109
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#define MYKONOS_ADDR_CLOCK_CONTROL_0 0x117
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#define MYKONOS_ADDR_CLOCK_CONTROL_1 0x118
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#define MYKONOS_ADDR_CLOCK_CONTROL_2 0x119
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#define MYKONOS_ADDR_CLOCK_CONTROL_3 0x11A
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#define MYKONOS_ADDR_CLOCK_CONTROL_4 0x11B
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#define MYKONOS_ADDR_CLOCK_CONTROL_5 0x11C
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#define MYKONOS_ADDR_MCS_CONTROL 0x120
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#define MYKONOS_ADDR_MCS_STATUS 0x121
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/* CLK PLL Registers */
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#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE0 0x141
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#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE1 0x142
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#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE0 0x143
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#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE1 0x144
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#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE2 0x145
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#define MYKONOS_ADDR_CLK_SYNTH_F_VCOTN_BYTE1 0x148
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#define MYKONOS_ADDR_CLK_SYNTH_BYTE1 0x149
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#define MYKONOS_ADDR_CLK_SYNTH_BYTE2 0x14A
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#define MYKONOS_ADDR_CLK_SYNTH_BYTE3 0x14B
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#define MYKONOS_ADDR_CLK_SYNTH_BYTE5 0x14D
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#define MYKONOS_ADDR_CLK_SYNTH_BYTE6 0x14E
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#define MYKONOS_ADDR_CLK_SYNTH_BYTE7 0x14F
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#define MYKONOS_ADDR_CLK_SYNTH_LF_R3 0x150
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#define MYKONOS_ADDR_CLK_SYNTH_BYTE9 0x152
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#define MYKONOS_ADDR_CLK_SYNTH_CAL_STAT 0x154
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#define MYKONOS_ADDR_CLK_SYNTH_VCO_CAL_REF 0x155
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#define MYKONOS_ADDR_CLK_SYNTH_VCO_BAND_BYTE1 0x157
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#define MYKONOS_ADDR_CLK_SYNTH_CAL_CONTROL 0x159
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#define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL1 0x15E
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#define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL2 0x15F
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/* DPD Registers */
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#define MYKONOS_ADDR_TX1_DPD_MODEL_INDIRECT_PTR 0x178
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#define MYKONOS_ADDR_TX2_DPD_MODEL_INDIRECT_PTR 0x17C
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#define MYKONOS_ADDR_DPD_RMS_BUF_SIZE 0x180
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#define MYKONOS_ADDR_TX1_DPD_MODEL_WORKING_PTR 0x188
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#define MYKONOS_ADDR_TX2_DPD_MODEL_WORKING_PTR 0x18C
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/* Rx NCO Control registers */
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#define MYKONOS_ADDR_CALPLL_SDM_CONTROL 0x17F
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#define MYKONOS_ADDR_RX_NCO_CONTROL 0x190
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#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_3 0x191
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#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_2 0x192
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#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_1 0x193
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#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_3 0x194
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#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_2 0x195
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#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_1 0x196
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#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_3 0x197
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#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_2 0x198
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#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_1 0x199
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#define MYKONOS_ADDR_ENSM_CONFIG_7_0 0x1B0
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#define MYKONOS_ADDR_CALIBRATION_CONTROL 0x1B2
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#define MYKONOS_ADDR_ENSM_MANUAL_GAIN_LOCK_GPIO_SELECT 0x1B5
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#define MYKONOS_ADDR_REFERENCE_CLOCK_CYCLES 0x1C0
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#define MYKONOS_ADDR_TX_PD_OVERIDE_7_0 0x209
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#define MYKONOS_ADDR_RCAL_CONTROL 0x224
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#define MYKONOS_ADDR_REF_PAD_CONFIG1 0x230
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#define MYKONOS_ADDR_REF_PAD_CONFIG2 0x231
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#define MYKONOS_ADDR_RXSYNTH_CP_CAL_STAT 0x254
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#define MYKONOS_ADDR_RXSYNTH_VCO_BAND_BYTE1 0x257
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#define MYKONOS_ADDR_TXSYNTH_CP_CAL_STAT 0x2C4
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#define MYKONOS_ADDR_TXSYNTH_VCO_BAND_BYTE1 0x2C7
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#define MYKONOS_ADDR_SNIFF_RXSYNTH_CP_CAL_STAT 0x354
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#define MYKONOS_ADDR_SNIFF_RXSYNTH_VCO_BAND_BYTE1 0x357
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#define MYKONOS_ADDR_SNIFF_RXLOGEN_BYTE1 0x380
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#define MYKONOS_ADDR_RX_FILTER_CONFIGURATION 0x410
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#define MYKONOS_ADDR_RX_FILTER_GAIN 0x411
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#define MYKONOS_ADDR_DPD_SNIFFER_RX_FILTER_GAIN 0x412
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/* Mykonos Temperature Gain Compensation Registers */
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#define MYKONOS_ADDR_RX1_TEMP_GAIN_COMP 0x420
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#define MYKONOS_ADDR_RX2_TEMP_GAIN_COMP 0x421
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#define MYKONOS_ADDR_OBS_TEMP_GAIN_COMP 0x422
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/* Mykonos AGC General Registers */
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#define MYKONOS_ADDR_AGC_CFG_1 0x42E
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#define MYKONOS_ADDR_AGC_CFG_2 0x42F
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#define MYKONOS_ADDR_AGC_GAIN_CHANGE_GPIO_SEL 0x430
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#define MYKONOS_ADDR_AGC_RX1_MAX_GAIN_INDEX 0x431
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#define MYKONOS_ADDR_AGC_RX1_MIN_GAIN_INDEX 0x432
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#define MYKONOS_ADDR_AGC_MANUAL_GAIN_CFG 0x433
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#define MYKONOS_ADDR_AGC_MANUAL_GAIN_GPIO_SEL 0x434
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#define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_1 0x435
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#define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_2 0x436
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#define MYKONOS_ADDR_AGC_LOCK_LEVEL 0x437
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#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_1 0x438
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#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_2 0x439
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#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_3 0x43A
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#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_4 0x43B
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#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_5 0x43C
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#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_6 0x43D
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#define MYKONOS_ADDR_AGC_RX1_GAIN_LOCK_DELAY 0x43E
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#define MYKONOS_ADDR_AGC_RX2_GAIN_LOCK_DELAY 0x43F
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#define MYKONOS_ADDR_AGC_RX1_ATTACK_DELAY 0x440
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#define MYKONOS_ADDR_AGC_RX2_ATTACK_DELAY 0x441
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#define MYKONOS_ADDR_AGC_ULB_THRSH 0x442
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#define MYKONOS_ADDR_AGC_LLB_THRSH 0x443
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#define MYKONOS_ADDR_AGC_RX_BLOCK_DET_DECAY 0x444
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#define MYKONOS_ADDR_AGC_RESET_PD_HIGH_CNT 0x445
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#define MYKONOS_ADDR_AGC_RX2_MAX_GAIN_INDEX 0x446
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#define MYKONOS_ADDR_AGC_RX2_MIN_GAIN_INDEX 0x447
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#define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_1 0x448
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#define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_2 0x449
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#define MYKONOS_ADDR_AGC_ORX_SNRX_MAX_GAIN_INDEX 0x44A
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#define MYKONOS_ADDR_AGC_ORX_SNRX_MIN_GAIN_INDEX 0x44B
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#define MYKONOS_ADDR_AGC_ORX_SNRX_MANUAL_GAIN_CFG 0x44C
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#define MYKONOS_ADDR_AGC_ORX_SNRX_GPIO_SEL 0x44D
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#define MYKONOS_ADDR_AGC_ORX_SNRX_LOCK_LEVEL 0x44E
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#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_1 0x44F
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#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_2 0x450
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#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_3 0x451
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#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_4 0x452
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#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_5 0x453
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#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_6 0x454
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#define MYKONOS_ADDR_AGC_ORX_SNRX_GAIN_LOCK_DELAY 0x455
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#define MYKONOS_ADDR_AGC_ORX_SNRX_ATTACK_DELAY 0x456
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#define MYKONOS_ADDR_AGC_ORX_SNRX_ULB_THRSH 0x457
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#define MYKONOS_ADDR_AGC_ORX_SNRX_LLB_THRSH 0x458
|
|
#define MYKONOS_ADDR_AGC_ORX_SNRX_BLOCK_DET_DECAY 0x459
|
|
#define MYKONOS_ADDR_AGC_ORX_SNRX_RESET_PD_HIGH_CNT 0x45A
|
|
#define MYKONOS_ADDR_AGC_ORX1_MANUAL_GAIN_INDEX 0x45B
|
|
#define MYKONOS_ADDR_AGC_ORX2_MANUAL_GAIN_INDEX 0x45C
|
|
#define MYKONOS_ADDR_AGC_SNRX_MANUAL_GAIN_INDEX 0x45D
|
|
#define MYKONOS_ADDR_AGC_LOOPBACK1_MANUAL_GAIN_INDEX 0x45E
|
|
#define MYKONOS_ADDR_AGC_LOOPBACK2_MANUAL_GAIN_INDEX 0x45F
|
|
#define MYKONOS_ADDR_AGC_ORX_SNRX_ACTIVE 0x460
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|
|
|
/* Mykonos Fast Attack AGC Registers */
|
|
#define MYKONOS_ADDR_AGC_FAST_CFG_1 0x468
|
|
#define MYKONOS_ADDR_AGC_FAST_CFG_2 0x469
|
|
#define MYKONOS_ADDR_AGC_FAST_ENRGY_LOST_THRSH 0x46A
|
|
#define MYKONOS_ADDR_AGC_FAST_STRONG_SIG_THRSH 0x46B
|
|
#define MYKONOS_ADDR_AGC_FAST_SETTING_DELAY 0x46C
|
|
#define MYKONOS_ADDR_AGC_FAST_OPT_MAX_GAIN 0x46D
|
|
#define MYKONOS_ADDR_AGC_FAST_ENRGY_DET_CNT 0x46E
|
|
#define MYKONOS_ADDR_AGC_FAST_AGCLL_UPPER_LIMIT 0x46F
|
|
#define MYKONOS_ADDR_AGC_FAST_GAIN_LOCK_EXIT_CNT 0x470
|
|
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_1 0x471
|
|
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_2 0x472
|
|
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_LOST_THRSH 0x473
|
|
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_STRONG_SIG_THRSH 0x474
|
|
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_SET_DELAY 0x475
|
|
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_OPT_MAX_GAIN 0x476
|
|
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_DET_CNT 0x477
|
|
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_AGCLL_UPPER_LIMIT 0x478
|
|
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_GAIN_LOCK_EXIT_CNT 0x479
|
|
|
|
/* Mykonos Slow Loop - Hybrid AGC Registers */
|
|
#define MYKONOS_ADDR_AGC_SLOW_LOCK_LEV_THRSH 0x480
|
|
#define MYKONOS_ADDR_AGC_SLOW_ULB_CNT_THRSH 0x481
|
|
#define MYKONOS_ADDR_AGC_SLOW_LLB_CNT_THRSH 0x482
|
|
#define MYKONOS_ADDR_AGC_SLOW_HIGH_OVRG_CNT_THRSH 0x483
|
|
#define MYKONOS_ADDR_AGC_SLOW_LOW_OVRG_CNT_THRSH 0x484
|
|
#define MYKONOS_ADDR_AGC_SLOW_VERYLOW_OVRG_CNT_THRSH 0x485
|
|
#define MYKONOS_ADDR_AGC_SLOW_DIG_SAT_CNT_THRSH 0x486
|
|
#define MYKONOS_ADDR_AGC_SLOW_UPPER0_THRSH_GAIN_STEP 0x487
|
|
#define MYKONOS_ADDR_AGC_SLOW_LOWER0_THRSH_GAIN_STEP 0x488
|
|
#define MYKONOS_ADDR_AGC_SLOW_UPPER1_THRSH_GAIN_STEP 0x489
|
|
#define MYKONOS_ADDR_AGC_SLOW_LOWER1_THRSH_GAIN_STEP 0x48A
|
|
#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_1 0x48B
|
|
#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_2 0x48C
|
|
#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_3 0x48D
|
|
#define MYKONOS_ADDR_AGC_SLOW_LOOP_CFG 0x48E
|
|
#define MYKONOS_ADDR_AGC_SLOW_POWER_THRSH 0x48F
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOCK_LEV_THRSH 0x490
|
|
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ULB_CNT_THRSH 0x491
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LLB_CNT_THRSH 0x492
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_HIGH_OVRG_CNT_THRSH 0x493
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_LOW_OVRG_CNT_THRSH 0x494
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_VERYLOW_OVRG_CNT_THRSH 0x495
|
|
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_DIG_SAT_CNT_THRSH 0x496
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER0_THRSH_GAIN_STEP 0x497
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER0_THRSH_GAIN_STEP 0x498
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER1_THRSH_GAIN_STEP 0x499
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER1_THRSH_GAIN_STEP 0x49A
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_1 0x49B
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_2 0x49C
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_3 0x49D
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOOP_CFG 0x49E
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_POWER_THRSH 0x49F
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_1 0x4A0
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_2 0x4A1
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_1 0x4A2
|
|
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_2 0x4A3
|
|
|
|
/* Mykonos Gain Control Read Registers */
|
|
#define MYKONOS_ADDR_GAIN_CTL_CHANNEL_1 0x4B0
|
|
#define MYKONOS_ADDR_GAIN_CTL_FAST_ATTK_STATE 0x4B1
|
|
#define MYKONOS_ADDR_GAIN_CTL_SLOW_LOOP_STATE 0x4B2
|
|
#define MYKONOS_ADDR_GAIN_CTL_CHANNEL_2 0x4B3
|
|
#define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_1 0x4B4
|
|
#define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_2 0x4B5
|
|
#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_GAIN 0x4B6
|
|
#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_LOOP_STATE 0x4B7
|
|
#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_OVRG_SIGS 0x4B8
|
|
|
|
/* Mykonos Rx Data Path Overrange Registers */
|
|
#define MYKONOS_ADDR_RX_OVRG_DATAPATH_OVRFLW 0x4B9
|
|
#define MYKONOS_ADDR_RX_OVRG_ORX_SNRX_DATAPATH_OVRFLW 0x4BA
|
|
|
|
/* Mykonos RSSI Measurement Registers and Dec Power Measurement Registers*/
|
|
#define MYKONOS_ADDR_RSSI_MEAS_DURATION_0_1 0x4C0
|
|
#define MYKONOS_ADDR_RSSI_MEAS_DURATION_2_3 0x4C1
|
|
#define MYKONOS_ADDR_RSSI_CFG 0x4C6
|
|
#define MYKONOS_DEC_POWER_CONFIG_1 0x4C7
|
|
#define MYKONOS_DEC_POWER_CONFIG_2 0x4C8
|
|
#define MYKONOS_ADDR_DPD_SNF_RSSI_CFG 0x4CF
|
|
#define MYKONOS_ADDR_DPD_RSSI_CFG 0x4D6
|
|
#define MYKONOS_SNIFFER_DEC_POWER_CONFIG_1 0x4D7
|
|
#define MYKONOS_SNIFFER_DEC_POWER_CONFIG_2 0x4D8
|
|
#define MYKONOS_CH1_DECIMATED_PWR 0x4DE
|
|
#define MYKONOS_CH2_DECIMATED_PWR 0x4DF
|
|
#define MYKONOS_SNIFFER_DECIMATED_PWR 0x4E6
|
|
|
|
#define MYKONOS_ADDR_DIGITAL_GAIN_CONFIG 0x4F0
|
|
#define MYKONOS_ADDR_DPD_SNIFFER_DIGITAL_GAIN_CONFIG 0x4F1
|
|
#define MYKONOS_ADDR_GAIN_TABLE_ADDR 0x500
|
|
#define MYKONOS_ADDR_GAIN_TABLE_RX1_FE_GAIN 0x501
|
|
#define MYKONOS_ADDR_GAIN_TABLE_RX1_EXT_CTL 0x502
|
|
#define MYKONOS_ADDR_GAIN_TABLE_RX1_DIG_GAIN 0x503
|
|
#define MYKONOS_ADDR_GAIN_TABLE_RX2_FE_GAIN 0x504
|
|
#define MYKONOS_ADDR_GAIN_TABLE_RX2_EXT_CTL 0x505
|
|
#define MYKONOS_ADDR_GAIN_TABLE_RX2_DIG_GAIN 0x506
|
|
#define MYKONOS_ADDR_GAIN_TABLE_RX3_FE_GAIN 0x507
|
|
#define MYKONOS_ADDR_GAIN_TABLE_RX3_LNA_ENAB 0x508
|
|
#define MYKONOS_ADDR_GAIN_TABLE_RX3_DIG_GAIN 0x509
|
|
#define MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION 0x516
|
|
#define MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION 0x517
|
|
#define MYKONOS_ADDR_RXFE1_LOCM 0x520
|
|
#define MYKONOS_ADDR_RXFE2_LOCM 0x521
|
|
#define MYKONOS_ADDR_RXLOOPBACK1_CNTRL_1 0x540
|
|
#define MYKONOS_ADDR_RXLOOPBACK2_CNTRL_1 0x541
|
|
#define MYKONOS_ADDR_RX_LOOPBACK1_CNTRL_4 0x546
|
|
#define MYKONOS_ADDR_RX_LOOPBACK2_CNTRL_4 0x547
|
|
|
|
/* Mykonos Overload/Peak Detection Registers */
|
|
#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_CFG 0x580
|
|
#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_UPPER_THRSH 0x581
|
|
#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_LOWER_THRSH 0x582
|
|
|
|
#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_CFG 0x583
|
|
#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_UPPER_THRSH 0x584
|
|
#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_LOWER_THRSH 0x585
|
|
#define MYKONOS_ADDR_OVRLD_PD_DEC_VERYLOW_THRSH 0x586
|
|
#define MYKONOS_ADDR_ORX_SNRX_OVRLD_ADC_OVRLD_CFG 0x587
|
|
#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_CFG 0x58A
|
|
#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_UPPER_THRSH 0x58B
|
|
#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_LOWER_THRSH 0x58C
|
|
#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_VERYLOW_THRSH 0x58D
|
|
|
|
#define MYKONOS_ADDR_RX_ADC_FLASH_DELAY 0x5B6
|
|
#define MYKONOS_ADDR_RX_ADC_FLASH_CTRL 0x5B7
|
|
#define MYKONOS_ADDR_RX_ADC1_PRFL 0x5DD
|
|
#define MYKONOS_ADDR_RX_ADC2_PRFL 0x5DE
|
|
#define MYKONOS_ADDR_ORX_ADC_PRFL 0x5DF
|
|
|
|
#define MYKONOS_ADDR_RFDC_MEASURE_COUNT_1 0x631
|
|
#define MYKONOS_ADDR_RFDC_MEASURE_COUNT_2 0x632
|
|
#define MYKONOS_ADDR_RFDC_PROGRAM_SHIFT 0x635
|
|
#define MYKONOS_ADDR_RFDC_CONFIG2 0x636
|
|
#define MYKONOS_DPD_Sniffer_RFDC_CAL_TRACK_EN 0x642
|
|
#define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_1 0x644
|
|
#define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_2 0x645
|
|
#define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_1 0x650
|
|
#define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_2 0x651
|
|
#define MYKONOS_ADDR_DIGITAL_DC_MIN_CAL_IDX 0x63A
|
|
#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SHIFT 0x674
|
|
#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CONFIG 0x676
|
|
#define MYKONOS_DIGITAL_DC_OFFSET_CH3_TRACKING 0x67A
|
|
#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SNF 0x67C
|
|
#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CH3_DPD_M_SHIFT 0x67D
|
|
|
|
#define MYKONOS_ADDR_RX_GAIN_COMP_DELAY 0x710
|
|
#define MYKONOS_ADDR_RX1_GAIN_COMP_OFFSET 0x711
|
|
#define MYKONOS_ADDR_RX2_GAIN_COMP_OFFSET 0x712
|
|
#define MYKONOS_ADDR_RX_GAIN_COMP_CFG 0x713
|
|
#define MYKONOS_ADDR_RX_SLCR_PIN_CFG 0x714
|
|
#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_DELAY 0x715
|
|
#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_OFFSET 0x716
|
|
#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_CFG 0x717
|
|
#define MYKONOS_ADDR_DPD_SNF_RX_SLCR_PIN_CFG 0x718
|
|
|
|
#define MYKONOS_ADDR_FLOATING_POINT_CFG 0x750
|
|
#define MYKONOS_ADDR_FLOATING_POINT_RX_CTRL 0x751
|
|
#define MYKONOS_ADDR_FLOATING_POINT_ORX_CTRL 0x752
|
|
|
|
|
|
#define MYKONOS_ADDR_SNRX_LNA_BIAS_C 0x81B
|
|
|
|
|
|
#define MYKONOS_ADDR_ORX_ADC_FLASH_DELAY 0x846
|
|
#define MYKONOS_ADDR_ORX_ADC_FLASH_CTRL 0x847
|
|
|
|
#define MYKONOS_ADDR_TX_FILTER_CONFIGURATION 0x910
|
|
#define MYKONOS_ADDR_TX1_ATTENUATION_0_READBACK 0x940
|
|
#define MYKONOS_ADDR_TX1_ATTENUATION_1_READBACK 0x941
|
|
#define MYKONOS_ADDR_TX2_ATTENUATION_0_READBACK 0x942
|
|
#define MYKONOS_ADDR_TX2_ATTENUATION_1_READBACK 0x943
|
|
#define MYKONOS_ADDR_TX_FILTER_OVERFLOW 0x950
|
|
|
|
/* Mykonos PA Protection Block Registers */
|
|
#define MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION 0x955
|
|
#define MYKONOS_ADDR_PA_PROTECTION_ATTEN_CONTROL 0x956
|
|
#define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_LSB 0x957
|
|
#define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_MSB 0x958
|
|
#define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_LSB 0x959
|
|
#define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_MSB 0x95A
|
|
#define MYKONOS_ADDR_TX1_ATTENUATION_0 0x960
|
|
#define MYKONOS_ADDR_TX1_ATTENUATION_1 0x961
|
|
#define MYKONOS_ADDR_TX2_ATTENUATION_0 0x962
|
|
#define MYKONOS_ADDR_TX2_ATTENUATION_1 0x963
|
|
#define MYKONOS_ADDR_TX1_GAIN_0 0x967
|
|
#define MYKONOS_ADDR_TX1_GAIN_1 0x968
|
|
#define MYKONOS_ADDR_TX1_GAIN_2 0x969
|
|
#define MYKONOS_ADDR_TX2_GAIN_0 0x96A
|
|
#define MYKONOS_ADDR_TX2_GAIN_1 0x96B
|
|
#define MYKONOS_ADDR_TX2_GAIN_2 0x96C
|
|
#define MYKONOS_ADDR_TX_INCR_DECR_WORD 0x96D
|
|
#define MYKONOS_ADDR_TX_TPC_CONFIG 0x96E
|
|
#define MYKONOS_ADDR_TX_TPC_GPIO_CFG 0x96F
|
|
|
|
#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_MSB 0x9CB
|
|
#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_LSB 0x9CC
|
|
#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_MSB 0x9CD
|
|
#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_LSB 0x9CE
|
|
|
|
/* Mykonos GPIO Registers */
|
|
#define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_7_0 0xB00
|
|
#define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_15_8 0xB01
|
|
#define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_7_0 0xB02
|
|
#define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_15_8 0xB03
|
|
#define MYKONOS_ADDR_GPIO_3V3_SPI_READ_7_0 0xB04
|
|
#define MYKONOS_ADDR_GPIO_3V3_SPI_READ_15_8 0xB05
|
|
#define MYKONOS_ADDR_GPIO_3V3_LSB_SRC_CTL 0xB06
|
|
#define MYKONOS_ADDR_GPIO_3V3_MSB_SRC_CTL 0xB07
|
|
|
|
#define MYKONOS_ADDR_GPIO_DIR_CTL_7_0 0xB20
|
|
#define MYKONOS_ADDR_GPIO_DIR_CTL_15_8 0xB21
|
|
#define MYKONOS_ADDR_GPIO_DIR_CTL_18_16 0xB22
|
|
#define MYKONOS_ADDR_GPIO_SPI_SRC_7_0 0xB23
|
|
#define MYKONOS_ADDR_GPIO_SPI_SRC_15_8 0xB24
|
|
#define MYKONOS_ADDR_GPIO_SPI_SRC_18_16 0xB25
|
|
#define MYKONOS_ADDR_GPIO_SPI_READ_7_0 0xB26
|
|
#define MYKONOS_ADDR_GPIO_SPI_READ_15_8 0xB27
|
|
#define MYKONOS_ADDR_GPIO_SPI_READ_18_16 0xB28
|
|
#define MYKONOS_ADDR_SOURCE_CONTROL_LOWER_BYTE 0xB29
|
|
#define MYKONOS_ADDR_SOURCE_CONTROL_UPPER_BYTE 0xB2A
|
|
#define MYKONOS_ADDR_SOURCE_CONTROL_EXTRA_BITS 0xB2B
|
|
|
|
#define MYKONOS_ADDR_GPIO_MONITOR_INDEX 0xB40
|
|
#define MYKONOS_ADDR_GPIO_MONITOR_ENABLE 0xB41
|
|
|
|
#define MYKONOS_ADDR_GP_INTERRUPT_MASK_1 0xB42
|
|
#define MYKONOS_ADDR_GP_INTERRUPT_MASK_0 0xB43
|
|
#define MYKONOS_ADDR_GP_INTERRUPT_READ_1 0xB44
|
|
#define MYKONOS_ADDR_GP_INTERRUPT_READ_0 0xB45
|
|
|
|
#define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_5_0 0xB73
|
|
#define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_9_6 0xB74
|
|
#define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_5_0 0xB75
|
|
#define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_9_6 0xB76
|
|
#define MYKONOS_ADDR_AUX_DAC_LATCH_CONTROL 0xB9F
|
|
#define MYKONOS_ADDR_AUXDAC_0_WORD_MSB 0xBA0
|
|
|
|
#define MYKONOS_ADR_AUX_ADC_CLOCK_DIVIDE 0xBC0
|
|
#define MYKONOS_ADDR_AUX_ADC_CFG 0xBC1
|
|
#define MYKONOS_ADDR_AUX_ADC_READ_MSB 0xBC2
|
|
#define MYKONOS_ADDR_AUX_ADC_READ_LSB 0xBC3
|
|
#define MYKONOS_ADDR_AUX_ADC_SEL 0xBC4
|
|
#define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_0 0xBC5
|
|
#define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_1 0xBC6
|
|
|
|
#define MYKONOS_ADDR_TEMP_SENSOR_OFFSET 0xBE0
|
|
#define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB 0xBE1
|
|
#define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_MSB 0xBE2
|
|
#define MYKONOS_ADDR_TEMP_SENSOR_READ 0xBE3
|
|
#define MYKONOS_ADDR_TEMP_SENSOR_CONFIG 0xBE4
|
|
|
|
#define MYKONOS_ADDR_DIGITAL_TEST_BYTE_0 0xC40
|
|
|
|
/* ARM subsystem registers */
|
|
#define MYKONOS_ADDR_ARM_CTL_1 0xD00
|
|
#define MYKONOS_ADDR_ARM_CTL_2 0xD01
|
|
#define MYKONOS_ADDR_ARM_ADDR_BYTE_0 0xD02
|
|
#define MYKONOS_ADDR_ARM_ADDR_BYTE_1 0xD03
|
|
#define MYKONOS_ADDR_ARM_DATA_BYTE_0 0xD04
|
|
#define MYKONOS_ADDR_ARM_DATA_BYTE_1 0xD05
|
|
#define MYKONOS_ADDR_ARM_DATA_BYTE_2 0xD06
|
|
#define MYKONOS_ADDR_ARM_DATA_BYTE_3 0xD07
|
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#define MYKONOS_ADDR_ARM_CLK_CTL 0xD08
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#define MYKONOS_ADDR_AHB_SPI_BRIDGE 0xD09
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#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_0 0xD0A
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#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_1 0xD0B
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#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_2 0xD0C
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#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_3 0xD0D
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#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_0 0xD0E
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#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_1 0xD0F
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#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_2 0xD10
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#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_3 0xD11
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#define MYKONOS_ADDR_ARM_BRIDGE_CLK_CTL 0xD14
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/* ARM mailbox registers */
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#define MYKONOS_ADDR_ARM_CMD 0xD30
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#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_1 0xD31
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#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_2 0xD32
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#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_3 0xD33
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#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_4 0xD34
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#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_5 0xD35
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#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_6 0xD36
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#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_7 0xD37
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#define MYKONOS_ADDR_ARM_CMD_STATUS_0 0xD38
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#define MYKONOS_ADDR_ARM_CMD_STATUS_1 0xD39
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#define MYKONOS_ADDR_ARM_CMD_STATUS_2 0xD3A
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#define MYKONOS_ADDR_ARM_CMD_STATUS_3 0xD3B
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#define MYKONOS_ADDR_ARM_CMD_STATUS_4 0xD3C
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#define MYKONOS_ADDR_ARM_CMD_STATUS_5 0xD3D
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#define MYKONOS_ADDR_ARM_CMD_STATUS_6 0xD3E
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#define MYKONOS_ADDR_ARM_CMD_STATUS_7 0xD3F
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#define MYKONOS_ADDR_ARM_OPCODE_STATE_0 0xD40
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#define MYKONOS_ADDR_ARM_OPCODE_STATE_1 0xD41
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#define MYKONOS_ADDR_ARM_OPCODE_STATE_2 0xD42
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#define MYKONOS_ADDR_ARM_OPCODE_STATE_3 0xD43
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#define MYKONOS_ADDR_ARM_OPCODE_STATE_4 0xD44
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#define MYKONOS_ADDR_ARM_OPCODE_STATE_5 0xD45
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#define MYKONOS_ADDR_ARM_OPCODE_STATE_6 0xD46
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#define MYKONOS_ADDR_ARM_OPCODE_STATE_7 0xD47
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/* Mykonos Power-Down Override Control Registers */
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#define MYKONOS_ADDR_TX_PD_OVERRIDE_CONTROL_7_0 0xD89
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/* Mykonos Observation Framer Registers */
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#define MYKONOS_ADDR_OBS_FRAMER_RESET 0xDC0
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#define MYKONOS_ADDR_OBS_FRAMER_CLK_EN 0xDC1
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#define MYKONOS_ADDR_OBS_FRAMER_ADDR 0xDC2
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#define MYKONOS_ADDR_OBS_FRAMER_DATA 0xDC3
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#define MYKONOS_ADDR_OBS_FRAMER_WRITE_EN 0xDC4
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#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN 0xDC5
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#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_F 0xDC6
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#define MYKONOS_ADDR_OBS_FRAMER_LANE_CTL 0xDC7
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#define MYKONOS_ADDR_OBS_FRAMER_ADC_XBAR_SEL 0xDC8
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#define MYKONOS_ADDR_OBS_FRAMER_LANE_XBAR_SEL 0xDC9
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#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_LOOPBACK_XBAR_REV 0xDCA
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#define MYKONOS_ADDR_OBS_FRAMER_SYNCN_FILT 0xDCB
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#define MYKONOS_ADDR_OBS_FRAMER_LMFC_F_OFFSET 0xDCC
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#define MYKONOS_ADDR_OBS_FRAMER_LMFC_K_OFFSET 0xDCD
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#define MYKONOS_ADDR_OBS_FRAMER_TEST_CNTR_CTL 0xDCE
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#define MYKONOS_ADDR_OBS_FRAMER_STATUS_STRB 0xDCF
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#define MYKONOS_ADDR_OBS_FRAMER_STATUS 0xDD0
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#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_CNTR_STAT 0xDD1
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#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0xDD2
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#define MYKONOS_ADDR_OBS_FRAMER_LANE_FIFO_STRB 0xDD3
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#define MYKONOS_ADDR_OBS_FRAMER_LANE0_FIFO_RDWR_ADDR 0xDD4
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#define MYKONOS_ADDR_OBS_FRAMER_LANE1_FIFO_RDWR_ADDR 0xDD5
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#define MYKONOS_ADDR_OBS_FRAMER_LANE2_FIFO_RDWR_ADDR 0xDD6
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#define MYKONOS_ADDR_OBS_FRAMER_LANE3_FIFO_RDWR_ADDR 0xDD7
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#define MYKONOS_ADDR_OBS_FRAMER_PRBS10_CTL 0xDD8
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#define MYKONOS_ADDR_OBS_FRAMER_PRBS20_CTL 0xDD9
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#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_EN 0xDDA
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#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_7_TO_0 0xDDB
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#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_15_TO_8 0xDDC
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#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_19_TO_16 0xDDD
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#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_JTX_GEN 0xDDE
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#define MYKONOS_ADDR_OBS_FRAMER_LANE_DATA_CTL 0xDDF
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#define MYKONOS_ADDR_OBS_FRAMER_DATA_SAMPLE_CTL 0xDE0
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#define MYKONOS_ADDR_PFIR_COEFF_CTL 0xDFF
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#define MYKONOS_ADDR_PFIR_COEFF_DATA 0xE00
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#define MYKONOS_ADDR_PFIR_COEFF_ADDR 0xE01
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/* ARM memory */
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#define MYKONOS_ADDR_ARM_START_PROG_ADDR 0x01000000
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#define MYKONOS_ADDR_ARM_END_PROG_ADDR 0x01017FFF
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#define MYKONOS_ADDR_ARM_START_DATA_ADDR 0x20000000
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#define MYKONOS_ADDR_ARM_END_DATA_ADDR 0x2000FFFF
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#define MYKONOS_ADDR_ARM_BUILD_CHKSUM_ADDR 0x01017FE0
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#define MYKONOS_ADDR_ARM_CALC_CHKSUM_ADDR 0x01017FE4
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#define MYKONOS_ADDR_ARM_VERSION 0x01000128
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#define MYKONOS_ARM_ABORT_OPCODE 0x00
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#define MYKONOS_ARM_RUNINIT_OPCODE 0x02
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#define MYKONOS_ARM_RADIOON_OPCODE 0x04
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#define MYKONOS_ARM_WRITECFG_OPCODE 0x06
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#define MYKONOS_ARM_READCFG_OPCODE 0x08
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#define MYKONOS_ARM_SET_OPCODE 0x0A
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#define MYKONOS_ARM_GET_OPCODE 0x0C
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#define MYKONOS_ARM_OBJECTID_DPDINIT_CONFIG 0x0F
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#define MYKONOS_ARM_OBJECTID_CLGCINIT_CONFIG 0x10
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#define MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG 0x11
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#define MYKONOS_ARM_OBJECTID_DPDCONFIG 0x24
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#define MYKONOS_ARM_DPD_RESET 0x02
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#define MYKONOS_ARM_OBJECTID_GS_TRACKCALS 0x66
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#define MYKONOS_ARM_OBJECTID_RXQEC_TRACKING 0x20
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#define MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING 0x21
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#define MYKONOS_ARM_OBJECTID_TXLOL_TRACKING 0x22
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#define MYKONOS_ARM_OBJECTID_TXQEC_TRACKING 0x23
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#define MYKONOS_ARM_OBJECTID_CLGCCONFIG 0x25
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#define MYKONOS_ARM_OBJECTID_VSWRCONFIG 0x26
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#define MYKONOS_ARM_OBJECTID_CAL_STATUS 0x42
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#define MYKONOS_ARM_OBJECTID_INIT_CAL_DONE 0x43
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#define MYKONOS_ARM_OBJECTID_ORX_MODE 0x61
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#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_SUSPEND_RESUME 0x65
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#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_CONTROL 0x66
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#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_PENDING 0x67
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#define MYKONOS_ARM_OBJECTID_RADIO_CONTROL 0x81
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#define MYKONOS_ARM_OBJECTID_CALSCHEDULER 0x83
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#define MYKONOS_ARM_SYSTEMSTATE_POWERUP 0x00
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#define MYKONOS_ARM_SYSTEMSTATE_READY 0x01
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#define MYKONOS_ARM_SYSTEMSTATE_IDLE 0x02
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#define MYKONOS_ARM_SYSTEMSTATE_RADIO_ON 0x03
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#define ORX_TRIGGER_SIGNALID 0x00
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#define ORX_MODE_0_SIGNALID 0x01
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#define ORX_MODE_1_SIGNALID 0x02
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#define ORX_MODE_2_SIGNALID 0x03
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#define RX1_ENABLE_ACK_SIGNALID 0x04
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#define RX2_ENABLE_ACK_SIGNALID 0x05
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#define TX1_ENABLE_ACK_SIGNALID 0x06
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#define TX2_ENABLE_ACK_SIGNALID 0x07
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#define ORX1_ENABLE_ACK_SIGNALID 0x08
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#define ORX2_ENABLE_ACK_SIGNALID 0x09
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#define SRX_ENABLE_ACK_SIGNALID 0x0A
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#define TX_OBS_SELECT_SIGNALID 0x0B
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#define DISABLE_DPD_ACTUATOR 0x03
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#define ENABLE_DPD_ACTUATOR 0x04
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#define SET_CLGC_DESIRED_GAIN_1 0x05
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#define SET_CLGC_DESIRED_GAIN_2 0x06
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#define SET_PATH_DELAY 0x08
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#ifdef __cplusplus
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}
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#endif
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#endif
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