Initial version.

datalink814_ge/src/Xilinx.spec

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+*startfile:
+crti%O%s crtbegin%O%s

datalink814_ge/src/bit_array/bar.h

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+/*
+ bar.h
+ project: bit array C library
+ url: https://github.com/noporpoise/BitArray/
+ maintainer: Isaac Turner <[email protected]>
+ license: Public Domain, no warranty
+ date: Sept 2014
+*/
+
+// shorten the names of some of the bit_array functions to be more
+// like the str* function names.  The prefix "bar" is used to represent
+// bit_array and is analogous to "str".
+
+#ifndef BAR_HEADER_SEEN
+#define BAR_HEADER_SEEN
+
+#include "bit_array.h"
+
+#define bar BIT_ARRAY
+
+#define barcreate  bit_array_create
+#define bardestroy bit_array_free
+#define baralloc   bit_array_alloc
+#define barfree    bit_array_dealloc
+#define barlen     bit_array_length
+
+#define barsize    bit_array_resize
+#define barcap     bit_array_ensure_size
+
+// These five are MACROs
+#define barget     bit_array_get
+#define barset     bit_array_set
+#define barclr     bit_array_clear
+#define barflip    bit_array_toggle
+#define barmake    bit_array_assign
+
+/* Functions instead of macros bars* => s for safe */
+#define barsget    bit_array_get_bit
+#define barsset    bit_array_set_bit
+#define barsclr    bit_array_clear_bit
+#define barsflip   bit_array_toggle_bit
+#define barsmake   bit_array_assign_bit
+
+/* "resize" functions barr*: automatically enlarge array if needed */
+#define barrget    bit_array_rget
+#define barrset    bit_array_rset
+#define barrclr    bit_array_rclear
+#define barrflip   bit_array_rtoggle
+#define barrmake   bit_array_rassign
+
+#define barsetn    bit_array_set_bits
+#define barclrn    bit_array_clear_bits
+#define barflipn   bit_array_toggle_bits
+
+#define barsetr    bit_array_set_region
+#define barclrr    bit_array_clear_region
+#define barflipr   bit_array_toggle_region
+
+#define barfill    bit_array_set_all
+#define barzero    bit_array_clear_all
+#define bartogl    bit_array_toggle_all
+
+/* gw "get word" */
+#define bargw64    bit_array_get_word64
+#define bargw32    bit_array_get_word32
+#define bargw16    bit_array_get_word16
+#define bargw8     bit_array_get_word8
+#define bargwn     bit_array_get_wordn
+
+/* sw "set word" */
+#define barsw64    bit_array_set_word64
+#define barsw32    bit_array_set_word32
+#define barsw16    bit_array_set_word16
+#define barswn     bit_array_set_wordn
+
+#define barncpy    bit_array_copy
+#define barcpy     bit_array_copy_all
+#define bardup     bit_array_clone
+
+#define barpopc    bit_array_num_bits_set
+#define barzeros   bit_array_num_bits_cleared
+#define bardist    bit_array_hamming_distance
+#define barparity  bit_array_parity
+
+#define barfns     bit_array_find_next_set_bit
+#define barfps     bit_array_find_prev_set_bit
+#define barffs     bit_array_find_first_set_bit
+#define barfls     bit_array_find_last_set_bit
+
+#define barfnz     bit_array_find_next_clear_bit
+#define barfpz     bit_array_find_prev_clear_bit
+#define barffz     bit_array_find_first_clear_bit
+#define barflz     bit_array_find_last_clear_bit
+
+#define barsort    bit_array_sort_bits
+#define barsortr   bit_array_sort_bits_rev
+
+#define barand     bit_array_and
+#define baror      bit_array_or
+#define barxor     bit_array_xor
+#define barnot     bit_array_not
+
+#define barcmp     bit_array_cmp
+#define barcmpbe   bit_array_cmp_big_endian
+#define barcmpw    bit_array_cmp_words
+#define barcmp64   bit_array_cmp_uint64
+
+#define barshr     bit_array_shift_right
+#define barshl     bit_array_shift_left
+#define bareshl    bit_array_shift_left_extend
+
+#define barcycr    bit_array_cycle_right
+#define barcycl    bit_array_cycle_left
+
+#define barmix     bit_array_interleave
+
+#define barrev     bit_array_reverse
+#define barrevr    bit_array_reverse_region
+
+#define bar2num    bit_array_as_num
+
+/* Add/sub/mult/div a bit array with: */
+/*   _i unsigned integer, _si shifted integer, _sb shifted bitarray */
+#define baraddi    bit_array_add_uint64
+#define baraddsi   bit_array_add_word
+#define baraddsb   bit_array_add_words
+#define barsubi    bit_array_sub_uint64
+#define barsubsi   bit_array_sub_word
+#define barsubsb   bit_array_sub_words
+#define barmuli    bit_array_mul_uint64
+#define bardivi    bit_array_div_uint64
+
+/* arguments are both bit arrays */
+#define baradd     bit_array_add
+#define barsub     bit_array_subtract
+#define barmul     bit_array_multiply
+#define bardiv     bit_array_divide
+
+#define barsave    bit_array_save
+#define barload    bit_array_load
+
+#define barhash    bit_array_hash
+
+#define barrand    bit_array_random
+#define barshfl    bit_array_shuffle
+#define barperm    bit_array_next_permutation
+
+#endif /* BAR_HEADER_SEEN */

datalink814_ge/src/bit_array/bit_array.h

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+/*
+ bit_array.h
+ project: bit array C library
+ url: https://github.com/noporpoise/BitArray/
+ maintainer: Isaac Turner <[email protected]>
+ license: Public Domain, no warranty
+ date: Sep 2014
+*/
+
+#ifndef BIT_ARRAY_HEADER_SEEN
+#define BIT_ARRAY_HEADER_SEEN
+
+#include <stdio.h>
+#include <inttypes.h>
+
+#include "bit_macros.h"
+
+typedef struct BIT_ARRAY BIT_ARRAY;
+
+// 64 bit words
+typedef uint64_t word_t, word_addr_t, bit_index_t;
+typedef uint8_t word_offset_t; // Offset within a 64 bit word
+
+#define BIT_INDEX_MIN 0
+#define BIT_INDEX_MAX (~(bit_index_t)0)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Structs
+//
+
+struct BIT_ARRAY
+{
+  word_t* words;
+  bit_index_t num_of_bits;
+  // Number of words used -- this is just round_up(num_of_bits / 64)
+  // if num_of_bits == 0, this is 0
+  word_addr_t num_of_words;
+  // For more efficient allocation we use realloc only to double size --
+  // not for adding every word.  Initial size is INIT_CAPACITY_WORDS.
+  word_addr_t capacity_in_words;
+};
+
+//
+// Basics: Constructor, destructor, get length, resize
+//
+
+// Constructor - create a new bit array of length nbits
+BIT_ARRAY* bit_array_create(bit_index_t nbits);
+
+// Destructor - free the memory used for a bit array
+void bit_array_free(BIT_ARRAY* bitarray);
+
+// Allocate using existing struct
+BIT_ARRAY* bit_array_alloc(BIT_ARRAY* bitarr, bit_index_t nbits);
+void bit_array_dealloc(BIT_ARRAY* bitarr);
+
+// Get length of bit array
+bit_index_t bit_array_length(const BIT_ARRAY* bit_arr);
+
+// Change the size of a bit array. Enlarging an array will add zeros
+// to the end of it. Returns 1 on success, 0 on failure (e.g. not enough memory)
+char bit_array_resize(BIT_ARRAY* bitarr, bit_index_t new_num_of_bits);
+
+// If bitarr length < num_bits, resizes to num_bits
+char bit_array_ensure_size(BIT_ARRAY* bitarr, bit_index_t ensure_num_of_bits);
+
+// Same as above but exit with an error message if out of memory
+void bit_array_resize_critical(BIT_ARRAY* bitarr, bit_index_t num_of_bits);
+void bit_array_ensure_size_critical(BIT_ARRAY* bitarr, bit_index_t num_of_bits);
+
+
+//
+// Macros
+//
+
+//
+// Get, set, clear, assign and toggle individual bits
+// Macros for fast access -- beware: no bounds checking
+//
+
+#define bit_array_get(arr,i)      bitset_get((arr)->words, i)
+#define bit_array_set(arr,i)      bitset_set((arr)->words, i)
+#define bit_array_clear(arr,i)    bitset_del((arr)->words, i)
+#define bit_array_toggle(arr,i)   bitset_tgl((arr)->words, i)
+// c must be 0 or 1
+#define bit_array_assign(arr,i,c) bitset_cpy((arr)->words,i,c)
+
+//
+// Get, set, clear, assign and toggle individual bits
+// "Safe": use assert() to check bounds
+//
+
+// Get the value of a bit (returns 0 or 1)
+char bit_array_get_bit(const BIT_ARRAY* bitarr, bit_index_t b);
+void bit_array_set_bit(BIT_ARRAY* bitarr, bit_index_t b);
+void bit_array_clear_bit(BIT_ARRAY* bitarr, bit_index_t b);
+void bit_array_toggle_bit(BIT_ARRAY* bitarr, bit_index_t b);
+// If char c != 0, set bit; otherwise clear bit
+void bit_array_assign_bit(BIT_ARRAY* bitarr, bit_index_t b, char c);
+
+//
+// "Resizing": enlarge array if needed
+//
+
+char bit_array_rget(BIT_ARRAY* bitarr, bit_index_t b);
+void bit_array_rset(BIT_ARRAY* bitarr, bit_index_t b);
+void bit_array_rclear(BIT_ARRAY* bitarr, bit_index_t b);
+void bit_array_rtoggle(BIT_ARRAY* bitarr, bit_index_t b);
+void bit_array_rassign(BIT_ARRAY* bitarr, bit_index_t b, char c);
+
+//
+// Set, clear and toggle several bits at once
+//
+
+// Set multiple bits at once.
+// e.g. set bits 1, 20 & 31: bit_array_set_bits(bitarr, 3, 1,20,31);
+// Note: variable args are of type unsigned int
+void bit_array_set_bits(BIT_ARRAY* bitarr, size_t n, ...);
+
+// Clear multiple bits at once.
+// e.g. clear bits 1, 20 & 31: bit_array_clear_bits(bitarr, 3, 1,20,31);
+// Note: variable args are of type unsigned int
+void bit_array_clear_bits(BIT_ARRAY* bitarr, size_t n, ...);
+
+// Toggle multiple bits at once
+// e.g. toggle bits 1, 20 & 31: bit_array_toggle_bits(bitarr, 3, 1,20,31);
+// Note: variable args are of type unsigned int
+void bit_array_toggle_bits(BIT_ARRAY* bitarr, size_t n, ...);
+
+//
+// Set, clear and toggle all bits in a region
+//
+
+// Set all the bits in a region
+void bit_array_set_region(BIT_ARRAY* bitarr, bit_index_t start, bit_index_t len);
+
+// Clear all the bits in a region
+void bit_array_clear_region(BIT_ARRAY* bitarr, bit_index_t start, bit_index_t len);
+
+// Toggle all the bits in a region
+void bit_array_toggle_region(BIT_ARRAY* bitarr, bit_index_t start, bit_index_t len);
+
+//
+// Set, clear and toggle all bits at once
+//
+
+// Set all bits in this array to 1
+void bit_array_set_all(BIT_ARRAY* bitarr);
+
+// Set all bits in this array to 0
+void bit_array_clear_all(BIT_ARRAY* bitarr);
+
+// Set all 1 bits to 0, and all 0 bits to 1
+void bit_array_toggle_all(BIT_ARRAY* bitarr);
+
+//
+// Get / set a word of a given size
+//
+
+// First bit is in the least significant bit position
+// start index must be within the range of the bit array (0 <= x < length)
+uint64_t bit_array_get_word64(const BIT_ARRAY* bitarr, bit_index_t start);
+uint32_t bit_array_get_word32(const BIT_ARRAY* bitarr, bit_index_t start);
+uint16_t bit_array_get_word16(const BIT_ARRAY* bitarr, bit_index_t start);
+uint8_t  bit_array_get_word8(const BIT_ARRAY* bitarr, bit_index_t start);
+uint64_t bit_array_get_wordn(const BIT_ARRAY* bitarr, bit_index_t start, int n);
+
+// Set 64 bits at once from a particular start position
+// Doesn't extend bit array. However it is safe to TRY to set bits beyond the
+// end of the array, as long as: `start` is < `bit_array_length(arr)`
+void bit_array_set_word64(BIT_ARRAY* bitarr, bit_index_t start, uint64_t word);
+void bit_array_set_word32(BIT_ARRAY* bitarr, bit_index_t start, uint32_t word);
+void bit_array_set_word16(BIT_ARRAY* bitarr, bit_index_t start, uint16_t word);
+void bit_array_set_word8(BIT_ARRAY* bitarr, bit_index_t start, uint8_t byte);
+void bit_array_set_wordn(BIT_ARRAY* bitarr, bit_index_t start, uint64_t word, int n);
+
+//
+// Number of bits set
+//
+
+// Get the number of bits set (hamming weight)
+bit_index_t bit_array_num_bits_set(const BIT_ARRAY* bitarr);
+
+// Get the number of bits not set (length - hamming weight)
+bit_index_t bit_array_num_bits_cleared(const BIT_ARRAY* bitarr);
+
+// Get the number of bits set in on array and not the other.  This is equivalent
+// to hamming weight of the XOR when the two arrays are the same length.
+// e.g. 10101 vs 00111 => hamming distance 2 (XOR is 10010)
+bit_index_t bit_array_hamming_distance(const BIT_ARRAY* arr1,
+                                       const BIT_ARRAY* arr2);
+
+// Parity - returns 1 if odd number of bits set, 0 if even
+char bit_array_parity(const BIT_ARRAY* bitarr);
+
+//
+// Find indices of set/clear bits
+//
+
+// Find the index of the next bit that is set, at or after `offset`
+// Returns 1 if a bit is set, otherwise 0
+// Index of next set bit is stored in the integer pointed to by result
+// If no next bit is set result is not changed
+char bit_array_find_next_set_bit(const BIT_ARRAY* bitarr, bit_index_t offset,
+                                 bit_index_t* result);
+
+// Find the index of the next bit that is NOT set, at or after `offset`
+// Returns 1 if a bit is NOT set, otherwise 0
+// Index of next zero bit is stored in the integer pointed to by `result`
+// If no next bit is zero, value at `result` is not changed
+char bit_array_find_next_clear_bit(const BIT_ARRAY* bitarr, bit_index_t offset,
+                                 bit_index_t* result);
+
+// Find the index of the previous bit that is set, before offset.
+// Returns 1 if a bit is set, otherwise 0
+// Index of previous set bit is stored in the integer pointed to by `result`
+// If no previous bit is set result is not changed
+char bit_array_find_prev_set_bit(const BIT_ARRAY* bitarr, bit_index_t offset,
+                                 bit_index_t* result);
+
+// Find the index of the previous bit that is NOT set, before offset.
+// Returns 1 if a bit is clear, otherwise 0
+// Index of previous zero bit is stored in the integer pointed to by `result`
+// If no previous bit is zero result is not changed
+char bit_array_find_prev_clear_bit(const BIT_ARRAY* bitarr, bit_index_t offset,
+                                   bit_index_t* result);
+
+// Find the index of the first bit that is set.
+// Returns 1 if a bit is set, otherwise 0
+// Index of first set bit is stored in the integer pointed to by `result`
+// If no bit is set result is not changed
+char bit_array_find_first_set_bit(const BIT_ARRAY* bitarr, bit_index_t* result);
+
+// Find the index of the first bit that is NOT set.
+// Returns 1 if a bit is clear, otherwise 0
+// Index of first zero bit is stored in the integer pointed to by `result`
+// If no bit is zero result is not changed
+char bit_array_find_first_clear_bit(const BIT_ARRAY* bitarr, bit_index_t* result);
+
+// Find the index of the last bit that is set.
+// Returns 1 if a bit is set, otherwise 0
+// Index of last set bit is stored in the integer pointed to by `result`
+// If no bit is set result is not changed
+char bit_array_find_last_set_bit(const BIT_ARRAY* bitarr, bit_index_t* result);
+
+// Find the index of the last bit that is NOT set.
+// Returns 1 if a bit is clear, otherwise 0
+// Index of last zero bit is stored in the integer pointed to by `result`
+// If no bit is zero result is not changed
+char bit_array_find_last_clear_bit(const BIT_ARRAY* bitarr, bit_index_t* result);
+
+
+//
+// Sorting
+//
+
+// Put all the 0s before all the 1s
+void bit_array_sort_bits(BIT_ARRAY* bitarr);
+
+// Put all the 1s before all the 0s
+void bit_array_sort_bits_rev(BIT_ARRAY* bitarr);
+
+
+//
+// String and printing methods
+//
+
+// Construct a BIT_ARRAY from a string.
+void bit_array_from_str(BIT_ARRAY* bitarr, const char* bitstr);
+
+// Construct a BIT_ARRAY from a substring with given on and off characters.
+void bit_array_from_substr(BIT_ARRAY* bitarr, bit_index_t offset,
+                           const char* str, size_t len,
+                           const char *on, const char *off, char left_to_right);
+
+// Takes a char array to write to.  `str` must be bitarr->num_of_bits+1 in
+// length. Terminates string with '\0'
+char* bit_array_to_str(const BIT_ARRAY* bitarr, char* str);
+char* bit_array_to_str_rev(const BIT_ARRAY* bitarr, char* str);
+
+// Get a string representations for a given region, using given on/off
+// characters.
+// Note: does not null-terminate
+void bit_array_to_substr(const BIT_ARRAY* bitarr,
+                         bit_index_t start, bit_index_t length,
+                         char* str, char on, char off, char left_to_right);
+
+// Print this array to a file stream.  Prints '0's and '1'.  Doesn't print
+// newline.
+void bit_array_print(const BIT_ARRAY* bitarr, FILE* fout);
+
+// Print a string representations for a given region, using given on/off
+// characters. Reverse prints from highest to lowest -- this is useful for
+// printing binary numbers
+void bit_array_print_substr(const BIT_ARRAY* bitarr,
+                            bit_index_t start, bit_index_t length,
+                            FILE* fout, char on, char off, char left_to_right);
+
+//
+// Decimal
+//
+
+// Get bit array as decimal str (e.g. 0b1101 -> "13")
+size_t bit_array_to_decimal(const BIT_ARRAY *bitarr, char *str, size_t len);
+
+// Return number of characters used
+size_t bit_array_from_decimal(BIT_ARRAY *bitarr, const char* decimal);
+
+//
+// Hexidecimal
+//
+
+// Loads array from hex string
+// Returns the number of bits loaded (will be chars rounded up to multiple of 8)
+// (0 on failure)
+bit_index_t bit_array_from_hex(BIT_ARRAY* bitarr, bit_index_t offset,
+                               const char* str, size_t len);
+
+// Returns number of characters written
+size_t bit_array_to_hex(const BIT_ARRAY* bitarr,
+                        bit_index_t start, bit_index_t length,
+                        char* str, char uppercase);
+
+// Print bit array as hex
+size_t bit_array_print_hex(const BIT_ARRAY* bitarr,
+                           bit_index_t start, bit_index_t length,
+                           FILE* fout, char uppercase);
+
+//
+// Clone and copy
+//
+
+// Copy a BIT_ARRAY struct and the data it holds - returns pointer to new object
+#define bit_array_dup	bit_array_clone
+BIT_ARRAY* bit_array_clone(const BIT_ARRAY* bitarr);
+
+// Copy bits from one array to another
+// Note: use MACRO bit_array_copy
+// Destination and source can be the same bit_array and
+// src/dst regions can overlap
+void bit_array_copy(BIT_ARRAY* dst, bit_index_t dstindx,
+                    const BIT_ARRAY* src, bit_index_t srcindx,
+                    bit_index_t length);
+
+// copy all of src to dst. dst is resized to match src.
+void bit_array_copy_all(BIT_ARRAY* dst, const BIT_ARRAY* src);
+
+//
+// Logic operators
+//
+
+// BIT_ARRAYs can all be different or the same object
+// dest array will be resized if it is too short
+//
+void bit_array_and(BIT_ARRAY* dest, const BIT_ARRAY* src1, const BIT_ARRAY* src2);
+void bit_array_or (BIT_ARRAY* dest, const BIT_ARRAY* src1, const BIT_ARRAY* src2);
+void bit_array_xor(BIT_ARRAY* dest, const BIT_ARRAY* src1, const BIT_ARRAY* src2);
+void bit_array_not(BIT_ARRAY* dest, const BIT_ARRAY* src);
+
+//
+// Comparisons
+//
+
+// Note: (bit_array_cmp(a,b) == 0) <=> (bit_array_cmp_big_endian(a,b) == 0)
+
+// comparison functions return:
+//   1 iff bitarr1 > bitarr2
+//   0 iff bitarr1 == bitarr2
+//  -1 iff bitarr1 < bitarr2
+
+// Compare two bit arrays by value stored, with index 0 being the Least
+// Significant Bit (LSB). Arrays do not have to be the same length.
+// Example: ..0101 (5) > ...0011 (3) [index 0 is LSB at right hand side]
+int bit_array_cmp(const BIT_ARRAY* bitarr1, const BIT_ARRAY* bitarr2);
+
+// Compare two bit arrays by value stored, with index 0 being the Most
+// Significant Bit (MSB). Arrays do not have to be the same length.
+// Example: 10.. > 01.. [index 0 is MSB at left hand side]
+int bit_array_cmp_big_endian(const BIT_ARRAY* bitarr1, const BIT_ARRAY* bitarr2);
+
+// compare bitarr with (bitarr2 << pos)
+int bit_array_cmp_words(const BIT_ARRAY *bitarr,
+                        bit_index_t pos, const BIT_ARRAY *bitarr2);
+
+//
+// Shift, interleave, reverse
+//
+
+// Shift array left/right.  If fill is zero, filled with 0, otherwise 1
+void bit_array_shift_right(BIT_ARRAY* bitarr, bit_index_t shift_dist, char fill);
+void bit_array_shift_left (BIT_ARRAY* bitarr, bit_index_t shift_dist, char fill);
+
+// shift left without losing any bits. Resizes bitarr.
+void bit_array_shift_left_extend(BIT_ARRAY* bitarr, bit_index_t shift_dist,
+                                 char fill);
+
+// Cyclic shift
+void bit_array_cycle_right(BIT_ARRAY* bitarr, bit_index_t dist);
+void bit_array_cycle_left (BIT_ARRAY* bitarr, bit_index_t dist);
+
+// Interleave
+// dst cannot point to the same bit array as src1 or src2
+// src1, src2 may point to the same bit array
+// abcd 1234 -> a1b2c3d4
+// 0011 0000 -> 00001010
+// 1111 0000 -> 10101010
+// 0101 1010 -> 01100110
+// Extends dst if it is too short, but does not shrink it if it is too long
+// if dst is longer than length(src1)+length(src2), the end bits are not altered
+void bit_array_interleave(BIT_ARRAY* dst,
+                          const BIT_ARRAY* src1,
+                          const BIT_ARRAY* src2);
+
+// Reverse the whole array or part of it
+void bit_array_reverse(BIT_ARRAY* bitarr);
+void bit_array_reverse_region(BIT_ARRAY* bitarr, bit_index_t start, bit_index_t len);
+
+//
+// Numeric
+//
+
+// Returns 1 on sucess, 0 if value in array is too big
+char bit_array_as_num(const BIT_ARRAY* bitarr, uint64_t* result);
+
+// 1 iff bitarr > value
+// 0 iff bitarr == value
+// -1 iff bitarr < value
+int bit_array_cmp_uint64(const BIT_ARRAY* bitarr, uint64_t value);
+
+//
+// Arithmetic
+//
+
+// bitarr will be extended if needed
+void bit_array_add_uint64(BIT_ARRAY* bitarr, uint64_t value);
+
+// Add `add` to `bitarr` at `pos` -- same as:
+//   bitarr + (add << pos)
+// where pos can be bigger than the length of the array (bitarr will be resized)
+void bit_array_add_word(BIT_ARRAY *bitarr, bit_index_t pos, uint64_t add);
+
+// Add `add` to `bitarr` at `pos`
+void bit_array_add_words(BIT_ARRAY *bitarr, bit_index_t pos, const BIT_ARRAY *add);
+
+// If value is greater than bitarr, bitarr is not changed and 0 is returned
+// Returns 1 on success, 0 if value > bitarr
+char bit_array_sub_uint64(BIT_ARRAY* bitarr, uint64_t value);
+
+// minus `minus` from `bitarr` at `pos` -- same as:
+//   bitarr + (minus << pos)
+// Returns 1 on success, 0 if value > bitarr
+char bit_array_sub_word(BIT_ARRAY *bitarr, bit_index_t pos, word_t minus);
+
+// minus `minus` from `bitarr` at `pos`
+// Returns 1 on success, 0 if value > bitarr
+char bit_array_sub_words(BIT_ARRAY* bitarr, bit_index_t pos, BIT_ARRAY* minus);
+
+// Multiply by some value
+void bit_array_mul_uint64(BIT_ARRAY *bitarr, uint64_t multiplier);
+
+// bitarr = round_down(bitarr / divisor)
+// rem = bitarr % divisor
+void bit_array_div_uint64(BIT_ARRAY *bitarr, uint64_t divisor, uint64_t *rem);
+
+//
+// Arithmetic between arrays
+//
+
+// dst = src1 + src2
+// src1, src2 and dst can all be the same BIT_ARRAY
+// If dst is shorter than either of src1, src2, it is enlarged
+void bit_array_add(BIT_ARRAY* dst, const BIT_ARRAY* src1, const BIT_ARRAY* src2);
+
+// dst = src1 - src2
+// src1, src2 and dst can all be the same BIT_ARRAY
+// If dst is shorter than src1, it will be extended to be as long as src1
+// src1 must be greater than or equal to src2 (src1 >= src2)
+void bit_array_subtract(BIT_ARRAY* dst,
+                        const BIT_ARRAY* src1, const BIT_ARRAY* src2);
+
+// dst = src1 * src2
+// Pointers cannot all point to the same BIT_ARRAY
+void bit_array_multiply(BIT_ARRAY *dst, BIT_ARRAY *src1, BIT_ARRAY *src2);
+
+// Results in:
+//   quotient = dividend / divisor
+//   dividend = dividend % divisor
+// (dividend is used to return the remainder)
+void bit_array_divide(BIT_ARRAY *dividend, BIT_ARRAY *quotient, BIT_ARRAY *divisor);
+
+//
+// Read/Write bit_array to a file
+//
+// File format is [8 bytes: for number of elements in array][data]
+// Number of bytes of data is: (int)((num_of_bits + 7) / 8)
+//
+
+// Saves bit array to a file
+// returns the number of bytes written
+bit_index_t bit_array_save(const BIT_ARRAY* bitarr, FILE* f);
+
+// Reads bit array from a file. bitarr is resized and filled.
+// Returns 1 on success, 0 on failure
+char bit_array_load(BIT_ARRAY* bitarr, FILE* f);
+
+
+//
+// Hash function
+//
+
+// Pass seed as 0 on first call, pass previous hash value if rehashing due
+// to a collision
+// Using bob jenkins hash lookup3
+uint64_t bit_array_hash(const BIT_ARRAY* bitarr, uint64_t seed);
+
+//
+// Randomness
+//
+
+// Get the next permutation of an array with a fixed size and given number of
+// bits set.  Also known as next lexicographic permutation.
+// Given a bit array find the next lexicographic orginisation of the bits
+// Number of possible combinations given by (size choose bits_set) i.e. nCk
+// 00011 -> 00101 -> 00110 -> 01001 -> 01010 ->
+// 01100 -> 10001 -> 10010 -> 10100 -> 11000 -> 00011 (back to start)
+void bit_array_next_permutation(BIT_ARRAY* bitarr);
+
+//
+// Generally useful functions
+//
+
+// Generalised 'binary to string' function
+// Adds bits to the string in order of lsb to msb
+// e.g. 0b11010 (26 in decimal) would come out as "01011"
+char* bit_array_word2str(const void *ptr, size_t num_of_bits, char *str);
+
+// Same as above but in reverse
+char* bit_array_word2str_rev(const void *ptr, size_t num_of_bits, char *str);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

datalink814_ge/src/bit_array/bit_macros.h

@@ -0,0 +1,205 @@
+/*
+ bit_macros.h
+ project: bit array C library
+ url: https://github.com/noporpoise/BitArray/
+ author: Isaac Turner <[email protected]>
+ license: Public Domain, no warranty
+ date: Dec 2013
+*/
+
+#ifndef BITSET_H_
+#define BITSET_H_
+
+#include <inttypes.h>
+#include <sched.h>
+
+// trailing_zeros is number of least significant zeros
+// leading_zeros is number of most significant zeros
+#if defined(_WIN32)
+  #define trailing_zeros(x) ({ __typeof(x) _r; _BitScanReverse64(&_r, x); _r; })
+  #define leading_zeros(x) ({ __typeof(x) _r; _BitScanForward64(&_r, x); _r; })
+#else
+  #define trailing_zeros(x) ((x) ? (__typeof(x))__builtin_ctzll(x) : (__typeof(x))sizeof(x)*8)
+  #define leading_zeros(x) ((x) ? (__typeof(x))__builtin_clzll(x) : (__typeof(x))sizeof(x)*8)
+#endif
+
+// Get index of top set bit. If x is 0 return nbits
+#define top_set_bit(x) ((x) ? sizeof(x)*8-leading_zeros(x)-1 : sizeof(x)*8)
+
+#define roundup_bits2bytes(bits)   (((bits)+7)/8)
+#define roundup_bits2words32(bits) (((bits)+31)/32)
+#define roundup_bits2words64(bits) (((bits)+63)/64)
+
+// Round a number up to the nearest number that is a power of two
+#define roundup2pow(x) (1UL << (64 - leading_zeros(x)))
+
+#define rot32(x,r) (((x)<<(r)) | ((x)>>(32-(r))))
+#define rot64(x,r) (((x)<<(r)) | ((x)>>(64-(r))))
+
+// need to check for length == 0, undefined behaviour if uint64_t >> 64 etc
+#define bitmask(nbits,type) ((nbits) ? ~(type)0 >> (sizeof(type)*8-(nbits)): (type)0)
+#define bitmask32(nbits) bitmask(nbits,uint32_t)
+#define bitmask64(nbits) bitmask(nbits,uint64_t)
+
+// A possibly faster way to combine two words with a mask
+//#define bitmask_merge(a,b,abits) ((a & abits) | (b & ~abits))
+#define bitmask_merge(a,b,abits) (b ^ ((a ^ b) & abits))
+
+// Swap lowest four bits. A nibble is 4 bits (i.e. half a byte)
+#define rev_nibble(x) ((((x)&1)<<3)|(((x)&2)<<1)|(((x)&4)>>1)|(((x)&8)>>3))
+
+//
+// Bit array (bitset)
+//
+// bitsetX_wrd(): get word for a given position
+// bitsetX_idx(): get index within word for a given position
+#define _VOLPTR(x) ((volatile __typeof(x) *)(&(x)))
+#define _VOLVALUE(x) (*_VOLPTR(x))
+
+#define _TYPESHIFT(arr,word,shift) \
+        ((__typeof(*(arr)))((__typeof(*(arr)))(word) << (shift)))
+
+#define bitsetX_wrd(wrdbits,pos) ((pos) / (wrdbits))
+#define bitsetX_idx(wrdbits,pos) ((pos) % (wrdbits))
+
+#define bitset32_wrd(pos) ((pos) >> 5)
+#define bitset32_idx(pos) ((pos) & 31)
+
+#define bitset64_wrd(pos) ((pos) >> 6)
+#define bitset64_idx(pos) ((pos) & 63)
+
+//
+// Bit functions on arrays
+//
+#define bitset2_get(arr,wrd,idx)     (((arr)[wrd] >> (idx)) & 0x1)
+#define bitset2_set(arr,wrd,idx)     ((arr)[wrd] |=  _TYPESHIFT(arr,1,idx))
+#define bitset2_del(arr,wrd,idx)     ((arr)[wrd] &=~ _TYPESHIFT(arr,1,idx))
+#define bitset2_tgl(arr,wrd,idx)     ((arr)[wrd] ^=  _TYPESHIFT(arr,1,idx))
+#define bitset2_or(arr,wrd,idx,bit)  ((arr)[wrd] |=  _TYPESHIFT(arr,bit,idx))
+#define bitset2_xor(arr,wrd,idx,bit) ((arr)[wrd]  = ~((arr)[wrd] ^ (~_TYPESHIFT(arr,bit,idx))))
+#define bitset2_and(arr,wrd,idx,bit) ((arr)[wrd] &= (_TYPESHIFT(arr,bit,idx) | ~_TYPESHIFT(arr,1,idx)))
+#define bitset2_cpy(arr,wrd,idx,bit) ((arr)[wrd]  = ((arr)[wrd] &~ _TYPESHIFT(arr,1,idx)) | _TYPESHIFT(arr,bit,idx))
+
+//
+// Thread safe versions
+//
+// They return the value of the bit (0 or 1) before it was updated
+#define bitset2_get_mt(arr,wrd,idx)     bitset2_get(_VOLPTR(*(arr)),wrd,idx)
+#define bitset2_set_mt(arr,wrd,idx)     ((__sync_fetch_and_or (_VOLPTR((arr)[wrd]),  _TYPESHIFT(arr,1,idx)) >> (idx))&1)
+#define bitset2_del_mt(arr,wrd,idx)     ((__sync_fetch_and_and(_VOLPTR((arr)[wrd]), ~_TYPESHIFT(arr,1,idx)) >> (idx))&1)
+#define bitset2_tgl_mt(arr,wrd,idx)     ((__sync_fetch_and_xor(_VOLPTR((arr)[wrd]),  _TYPESHIFT(arr,1,idx)) >> (idx))&1)
+#define bitset2_or_mt(arr,wrd,idx,bit)  ((__sync_fetch_and_or (_VOLPTR((arr)[wrd]),  _TYPESHIFT(arr,bit,idx)) >> (idx))&1)
+#define bitset2_xor_mt(arr,wrd,idx,bit) ((__sync_fetch_and_xor(_VOLPTR((arr)[wrd]),  _TYPESHIFT(arr,bit,idx)) >> (idx))&1)
+#define bitset2_and_mt(arr,wrd,idx,bit) ((__sync_fetch_and_and(_VOLPTR((arr)[wrd]), (_TYPESHIFT(arr,bit,idx) | ~_TYPESHIFT(arr,1,idx))) >> (idx))&1)
+#define bitset2_cpy_mt(arr,wrd,idx,bit) ((bit) ? bitset2_set_mt(arr,wrd,idx) : bitset2_del_mt(arr,wrd,idx))
+
+//
+// Auto detect size of type from pointer
+//
+#define bitset_wrd(arr,pos) bitsetX_wrd(sizeof(*(arr))*8,pos)
+#define bitset_idx(arr,pos) bitsetX_idx(sizeof(*(arr))*8,pos)
+#define bitset_op(func,arr,pos)      func(arr, bitset_wrd(arr,pos), bitset_idx(arr,pos))
+#define bitset_op2(func,arr,pos,bit) func(arr, bitset_wrd(arr,pos), bitset_idx(arr,pos), bit)
+
+// Auto-detect type size: bit functions
+#define bitset_get(arr,pos)     bitset_op(bitset2_get, arr, pos)
+#define bitset_set(arr,pos)     bitset_op(bitset2_set, arr, pos)
+#define bitset_del(arr,pos)     bitset_op(bitset2_del, arr, pos)
+#define bitset_tgl(arr,pos)     bitset_op(bitset2_tgl, arr, pos)
+#define bitset_or(arr,pos,bit)  bitset_op2(bitset2_or, arr, pos, bit)
+#define bitset_xor(arr,pos,bit) bitset_op2(bitset2_xor, arr, pos, bit)
+#define bitset_and(arr,pos,bit) bitset_op2(bitset2_and, arr, pos, bit)
+#define bitset_cpy(arr,pos,bit) bitset_op2(bitset2_cpy, arr, pos, bit)
+
+// Auto-detect type size: thread safe bit functions
+// They return the value of the bit (0 or 1) before it was updated
+#define bitset_get_mt(arr,pos)     bitset_op(bitset2_get_mt,  arr, pos)
+#define bitset_set_mt(arr,pos)     bitset_op(bitset2_set_mt,  arr, pos)
+#define bitset_del_mt(arr,pos)     bitset_op(bitset2_del_mt,  arr, pos)
+#define bitset_tgl_mt(arr,pos)     bitset_op(bitset2_tgl_mt,  arr, pos)
+#define bitset_or_mt(arr,pos,bit)  bitset_op2(bitset2_or_mt,  arr, pos, bit)
+#define bitset_xor_mt(arr,pos,bit) bitset_op2(bitset2_xor_mt, arr, pos, bit)
+#define bitset_and_mt(arr,pos,bit) bitset_op2(bitset2_and_mt, arr, pos, bit)
+#define bitset_cpy_mt(arr,pos,bit) bitset_op2(bitset2_cpy_mt, arr, pos, bit)
+
+// Clearing a word does not return a meaningful value
+#define bitset_clear_word(arr,pos) ((arr)[bitset_wrd(arr,pos)] = 0)
+#define bitset_clear_word_mt(arr,pos) (_VOLVALUE((arr)[bitset_wrd(arr,pos)]) = 0)
+
+//
+// Compact bit array of spin locks
+// These are most effecient when arr is of type: volatile char*
+//
+// Acquire a lock
+#define bitlock_acquire_block(arr,pos,wait,abandon) do {                       \
+  size_t _w = bitset_wrd(arr,pos);                                             \
+  __typeof(*(arr)) _o, _n, _b = _TYPESHIFT(arr, 1, bitset_idx(arr,pos));       \
+  do {                                                                         \
+    while((_o = _VOLVALUE((arr)[_w])) & _b) { wait }                           \
+    abandon                                                                    \
+    _n = _o | _b;                                                              \
+  } while(!__sync_bool_compare_and_swap(_VOLPTR((arr)[_w]), _o, _n));          \
+  __sync_synchronize(); /* Must not move commands to before acquiring lock */  \
+} while(0)
+
+// Undefined behaviour if you do not already hold the lock
+#define bitlock_release(arr,pos) do {                                          \
+  size_t _w = bitset_wrd(arr,pos);                                             \
+  __typeof(*(arr)) _mask = ~_TYPESHIFT(arr, 1, bitset_idx(arr,pos));           \
+  __sync_synchronize(); /* Must get the lock before releasing it */            \
+  __sync_and_and_fetch(_VOLPTR((arr)[_w]), _mask);                             \
+} while(0)
+
+#define bitlock_acquire(arr,pos) bitlock_acquire_block(arr,pos,{},{})
+
+// calls yield if cannot acquire the lock
+#define bitlock_yield_acquire(arr,pos) bitlock_acquire_block(arr,pos,sched_yield();,{})
+
+// Block until we get the lock or someone else does
+// sets the memory pointed to by retptr to 1 if we got the lock, 0 otherwise
+#define bitlock_try_acquire(arr,pos,retptr) do {                               \
+  *(retptr) = 1; /* default to success, set to zero if locked */               \
+  bitlock_acquire_block(arr,pos,{*(retptr)=0;break;},if(!*(retptr)){break;});  \
+} while(0)
+
+/*
+ * Byteswapping
+ */
+
+/* clang uses these to check for features */
+#ifndef __has_feature
+#define __has_feature(x) 0
+#endif
+
+#ifndef __has_builtin
+#define __has_builtin(x) 0
+#endif
+
+/* GCC versions < 4.3 do not have __builtin_bswapX() */
+#if ( defined(__clang__) && !__has_builtin(__builtin_bswap64) ) ||             \
+    ( !defined(__clang__) && defined(__GNUC__) && defined(__GNUC_MINOR__) &&   \
+      ( (__GNUC__ < 4)  || (__GNUC__ == 4 && __GNUC_MINOR__ < 3)) )
+  #define byteswap64(x) ( (((uint64_t)(x) << 56))                       | \
+                          (((uint64_t)(x) << 40) & 0xff000000000000ULL) | \
+                          (((uint64_t)(x) << 24) & 0xff0000000000ULL)   | \
+                          (((uint64_t)(x) <<  8) & 0xff00000000ULL)     | \
+                          (((uint64_t)(x) >>  8) & 0xff000000ULL)       | \
+                          (((uint64_t)(x) >> 24) & 0xff0000ULL)         | \
+                          (((uint64_t)(x) >> 40) & 0xff00ULL)           | \
+                          (((uint64_t)(x) >> 56)) )
+
+  #define byteswap32(x) ( (((uint32_t)(x) << 24))                       | \
+                          (((uint32_t)(x) <<  8) & 0xff0000U)           | \
+                          (((uint32_t)(x) >>  8) & 0xff00U)             | \
+                          (((uint32_t)(x) >> 24)) )
+
+  /* uint16_t type might be bigger than 2 bytes, so need to mask */
+  #define byteswap16(x) ( (((uint16_t)(x) & 0xff) << 8) | \
+                          (((uint16_t)(x) >> 8) & 0xff) )
+#else
+  #define byteswap64(x) __builtin_bswap64(x)
+  #define byteswap32(x) __builtin_bswap64(x)
+  #define byteswap16(x) __builtin_bswap64(x)
+#endif
+
+#endif /* BITLOCK_H_ */

datalink814_ge/src/common.c

@@ -0,0 +1,44 @@
+/*****************************************************************************/
+/**
+ * Description: Common functions
+ *
+ * Date: 2021-11-16 00:08
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-16 17:13
+ * Revisions: Rev 0.1
+ * History:
+ * [2022-07-16]: New branch for Dijian.
+ * [2021-11-16]: Initial version.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "common.h"
+#include "error.h"
+#include "util/util.h"
+#include "util/util.h"
+
+/************************** Constant Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * @brief
+ *
+ * @param
+ *
+ * @return
+ *
+ ******************************************************************************/
+void AppAssert(const char * file, int line){
+	DBG_PRINT("in %s #%4d [assert] ",file, line);
+	while(1);
+}

datalink814_ge/src/common.h

@@ -0,0 +1,81 @@
+/*****************************************************************************/
+/**
+ * Description: Common definitions
+ *
+ * Date: 2021-12-04 16:32
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-16 17:13
+ * Revisions: Rev 0.1
+ * History:
+ * [2022-07-16]: New branch for Dijian.
+ * [2021-11-16]: Initial version.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+/***************************** Include Files *********************************/
+#ifndef DATAKINK_COMMON_H_
+#define DATAKINK_COMMON_H_
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <assert.h>
+#include "util/util.h"
+#include "error.h"
+
+/************************** Constant Definitions *****************************/
+/***************** Macros (Inline Functions) Definitions *********************/
+#define __PRINT_BLOCK(block) do {\
+	block\
+} while(0)
+
+#define ASSERT(exp) ((exp) ? (void)0 : AppAssert(__FILE__, __LINE__))
+#define _nop_()	__asm__("nop")
+
+/* Stringify */
+#define STR(x)   #x
+
+//#define _814_DEBUG_LEVEL 3
+
+#if _814_DEBUG_LEVEL > 0
+#define DBG_PRINT(...)  printf(__VA_ARGS__)
+#endif
+#if _814_DEBUG_LEVEL >= 1
+#define DBG_ERROR(...) __PRINT_BLOCK( \
+    printf("in"__FILE__" #%4d [error]\t",__LINE__); \
+    printf(__VA_ARGS__); \
+)
+#endif
+#if _814_DEBUG_LEVEL >= 2
+#define DBG_WARNING(...) __PRINT_BLOCK( \
+    printf("[warning]\t"); \
+    printf(__VA_ARGS__); \
+)
+#endif
+#if _814_DEBUG_LEVEL >= 3
+#define DBG_INFO(...) __PRINT_BLOCK( \
+    printf("[Info]\t"); \
+    printf(__VA_ARGS__); \
+)
+#endif
+
+#ifndef DBG_ERROR
+#define DBG_ERROR(...)  {}
+#endif
+#ifndef DBG_WARNING
+#define DBG_WARNING(...)  {}
+#endif
+#ifndef DBG_INFO
+#define DBG_INFO(...)  {}
+#endif
+#ifndef DBG_PRINT
+#define DBG_PRINT(...)  {}
+#endif
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+void AppAssert(const char * file, int line);
+#endif /* COMMON_H_ */

datalink814_ge/src/config/app_config.h

@@ -0,0 +1,77 @@
+/*****************************************************************************/
+/**
+ * Description: Global configurations.
+ *
+ * Date: 2021-04-28 13:19
+ * Last Editors: Fan Hao
+ * Last Edit Time: [2022-05-23 20:32]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2021-04-28]: Initial edition.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+#ifndef CONFIG_H_
+#define CONFIG_H_
+
+#define XILINX_PLATFORM
+
+#include "xparameters.h"
+
+/******** MPC Status Configuration ********/
+#define _MPC_CTRL
+#define _MPC_PCIE
+
+/******** Software Version Switch ********/
+#define _EX_VER
+
+/*********** Debug Info Level ************/
+ #define _814_DEBUG_LEVEL -1
+// 3 - print all debug info
+// 2 - print warnings and errors
+// 1 - print only errors
+// other - print nothing
+#define FRAME_MSB_FIRST_
+/*********** Indoor Test Mode ************/
+#define PHY_BEAM_SET_PRESET
+#define PHY_BEAM_FORMING_ENABLE
+
+// Physical layer instance coindig
+#define PHY_CTRL_BASEADDR	XPAR_PHYC_BASEADDR
+#define ANTCONFIG_BRAM_ID	XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID
+#define TXBUFF_BRAM_ID		XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
+#define RXBUFF_BRAM_ID		XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID
+#define MPC_PCIE_BRAM_ID	XPAR_MPC_BRAM_INTERFACE_MPC_BRAM_CTRL_DEVICE_ID
+
+// Time controller config
+#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR
+/************ Hardware Configs ************/
+#define CPU_CLK_HZ		XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ
+#define FCLK_CLK0_HZ	125000000
+
+/********* Zynq Platform Configs **********/
+// Device ID Configs
+#define SCUGIC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
+#define PHY_DEVICE_ID 0
+
+// Interrupt Configs
+#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
+#define MPC_RX_DONE_INTR_ID XPAR_FABRIC_MPC_IRQ_INTR
+#define MPC_BUFFER_LENGTH (XPAR_MPC_BRAM_INTERFACE_MPC_BRAM_CTRL_S_AXI_HIGHADDR \
+							- XPAR_MPC_BRAM_INTERFACE_MPC_BRAM_CTRL_S_AXI_BASEADDR)
+
+// Test Mode Configs
+//#define DATA_ERROR_TEST			// fill 1.2M frames with 0xCC
+#define TEST_200KBPS				// set all mgmt svc tsync frame as 200KBPS
+
+// Configuration Check
+#if defined(PHY_BEAM_SET_PRESET) && !defined(PHY_BEAM_FORMING_ENABLE)
+#define L2_BEAM_FORMING_ENABLE
+#warning To impliment beam scan must enable beam forming...
+#endif
+
+#endif

datalink814_ge/src/config/platform.c

@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_cache.h"
+#include "platform_config.h"
+
+/*
+ * Uncomment one of the following two lines, depending on the target,
+ * if ps7/psu init source files are added in the source directory for
+ * compiling example outside of SDK.
+ */
+/*#include "ps7_init.h"*/
+/*#include "psu_init.h"*/
+
+#ifdef STDOUT_IS_16550
+ #include "xuartns550_l.h"
+
+ #define UART_BAUD 9600
+#endif
+
+void
+enable_caches()
+{
+#ifdef __PPC__
+    Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
+    Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
+#elif __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+    Xil_ICacheEnable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+    Xil_DCacheEnable();
+#endif
+#endif
+}
+
+void
+disable_caches()
+{
+#ifdef __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+    Xil_DCacheDisable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+    Xil_ICacheDisable();
+#endif
+#endif
+}
+
+void
+init_uart()
+{
+#ifdef STDOUT_IS_16550
+    XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
+    XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
+#endif
+    /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
+}
+
+void
+init_platform()
+{
+    /*
+     * If you want to run this example outside of SDK,
+     * uncomment one of the following two lines and also #include "ps7_init.h"
+     * or #include "ps7_init.h" at the top, depending on the target.
+     * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
+     * along with this example source files for compilation.
+     */
+    /* ps7_init();*/
+    /* psu_init();*/
+    enable_caches();
+    init_uart();
+}
+
+void
+cleanup_platform()
+{
+    disable_caches();
+}

datalink814_ge/src/config/platform.h

@@ -0,0 +1,41 @@
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef __PLATFORM_H_
+#define __PLATFORM_H_
+
+#include "platform_config.h"
+
+void init_platform();
+void cleanup_platform();
+
+#endif

datalink814_ge/src/config/platform_config.h

@@ -0,0 +1,7 @@
+#ifndef __PLATFORM_CONFIG_H_
+#define __PLATFORM_CONFIG_H_
+
+#define STDOUT_IS_PS7_UART
+#define UART_DEVICE_ID 0
+
+#endif

datalink814_ge/src/error.h

@@ -0,0 +1,31 @@
+#ifndef DATAKINK_ERROR_H_
+#define DATAKINK_ERROR_H_
+
+#include <errno.h>
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#ifdef SUCCESS
+#undef SUCCESS
+#endif
+#define SUCCESS		0
+#ifdef FAILURE
+#undef FAILURE
+#endif
+#define FAILURE		-1
+
+#define EPARAM -2	/*!< Data crc check failed */
+#define ECRC -3     /*!< Data crc check failed */
+#define EDINVAL -4	/*!< Device is invalid (sleep or power off) */
+#define EDCONF -5	/*!< Device confugure error */
+#define ETIMEOUT -6 /*!< Timeout error */
+#define EIGNORE -7	/*!< Received an unsupported command, and ignore it */
+#define EQUEUE  -8	/*!< Queue overflow */
+#define EALLOC  -9	/*!< Failed to allocate memory */
+#define EUNEXP  -10	/*!< Encounter an unexpected error */
+
+// #define IS_ERR_VALUE(x)	((x) != SUCCESS)
+
+#endif // ERROR_H_

datalink814_ge/src/hardware/common.c

@@ -0,0 +1,275 @@
+/**
+ * \file common.c
+ * \brief Contains Mykonos API common wrapper functions for user hardware platform drivers
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#include <stdio.h>
+#include <time.h>
+#include <errno.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "common.h" 
+#include "platform_drivers.h"
+#include "parameters.h"
+
+ADI_LOGLEVEL CMB_LOGLEVEL = ADIHAL_LOG_NONE;
+
+static uint32_t _desired_time_to_elapse_us = 0;
+struct spi_desc 	*spi_ad_desc;
+struct gpio_desc	*gpio_ad9371_resetb;
+struct gpio_desc	*gpio_ad9528_resetb;
+struct gpio_desc	*gpio_ad9528_sysref_req;
+
+commonErr_t CMB_initPlatform(void)
+{
+	struct spi_init_param spi_param;
+	int32_t status = COMMONERR_OK;
+
+	status |= gpio_get(&gpio_ad9371_resetb, AD9371_RESET_B);
+	status |= gpio_get(&gpio_ad9528_resetb, AD9528_RESET_B);
+	status |= gpio_get(&gpio_ad9528_sysref_req, AD9528_SYSREF_REQ);
+
+	spi_param.id = 0;
+	spi_param.mode = SPI_MODE_0;
+	spi_param.chip_select = AD9371_CS;
+	spi_param.max_speed_hz = 25000000u;
+
+	status |= spi_init(&spi_ad_desc, &spi_param);
+
+	if (status != SUCCESS) {
+		return COMMONERR_FAILED;
+	}
+
+	return COMMONERR_OK;
+}
+
+commonErr_t CMB_closeHardware(void)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_setGPIO(uint32_t GPIO)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex)
+{
+	struct gpio_desc *reset_gpio;
+
+	switch (spiChipSelectIndex) {
+	case AD9371_CS:
+		reset_gpio = gpio_ad9371_resetb;
+		break;
+	case AD9528_CS:
+		reset_gpio = gpio_ad9528_resetb;
+		break;
+	default:
+		return(COMMONERR_FAILED);
+	}
+
+	gpio_direction_output(reset_gpio, 1);
+	CMB_wait_ms(1);
+	gpio_direction_output(reset_gpio, 0);
+	CMB_wait_ms(1);
+	gpio_direction_output(reset_gpio, 1);
+	CMB_wait_ms(1);
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex )
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr,
+			     uint8_t data)
+{
+	uint8_t buf[3];
+
+	spi_ad_desc->chip_select = spiSettings->chipSelectIndex - 1;
+
+	buf[0] = (uint8_t) ((addr >> 8) & 0x7f);
+	buf[1] = (uint8_t) (addr & 0xff);
+	buf[2] = (uint8_t) data;
+
+	spi_write_and_read(spi_ad_desc, buf, 3);
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr,
+			      uint8_t *data, uint32_t count)
+{
+	uint32_t index;
+
+	for (index = 0; index < count; index++)
+		if (CMB_SPIWriteByte(spiSettings, *(addr + index),
+				     *(data + index)) != COMMONERR_OK)
+			return(COMMONERR_FAILED);
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_SPIReadByte(spiSettings_t *spiSettings, uint16_t addr,
+			    uint8_t *readdata)
+{
+	uint8_t buf[3];
+
+	spi_ad_desc->chip_select = spiSettings->chipSelectIndex - 1;
+
+	buf[0] = (uint8_t) ((addr >> 8) | 0x80);
+	buf[1] = (uint8_t) (addr & 0xff);
+	buf[2] = (uint8_t) 0x00;
+
+	spi_write_and_read(spi_ad_desc, buf, 3);
+	*readdata = buf[2];
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr,
+			      uint8_t field_val, uint8_t mask, uint8_t start_bit)
+{
+	uint8_t data;
+
+	if (CMB_SPIReadByte(spiSettings, addr, &data) != COMMONERR_OK)
+		return(COMMONERR_FAILED);
+
+	data = (data & ~mask) | ((field_val << start_bit) & mask);
+
+	if (CMB_SPIWriteByte(spiSettings, addr, data) != COMMONERR_OK)
+		return(COMMONERR_FAILED);
+
+	return(COMMONERR_OK);
+}
+
+/* read a field in a single register space (not multibyte fields) */
+commonErr_t CMB_SPIReadField(spiSettings_t *spiSettings, uint16_t addr,
+			     uint8_t *field_val, uint8_t mask, uint8_t start_bit)
+{
+	uint8_t data;
+
+	if (CMB_SPIReadByte(spiSettings, addr, &data) != COMMONERR_OK)
+		return(COMMONERR_FAILED);
+
+	data = (data & mask) >> start_bit;
+	*field_val = data;
+
+	return(COMMONERR_OK);
+}
+
+
+commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex,
+			   uint32_t errorCode, const char *comment)
+{
+
+	if((CMB_LOGLEVEL & ADIHAL_LOG_ERROR) && (level == ADIHAL_LOG_ERROR)) {
+		printf("ERROR: %d: %s", (int)errorCode, comment);
+	} else if((CMB_LOGLEVEL & ADIHAL_LOG_WARNING)
+		  && (level == ADIHAL_LOG_WARNING)) {
+		printf("WARNING: %d: %s",(int)errorCode, comment);
+	} else if((CMB_LOGLEVEL & ADIHAL_LOG_MESSAGE)
+		  && (level == ADIHAL_LOG_MESSAGE)) {
+		printf("MESSAGE: %d: %s",(int)errorCode, comment);
+	} else if(CMB_LOGLEVEL == ADIHAL_LOG_NONE ) {
+		//printf("MESSAGE: %d: %s",(int)errorCode, comment);
+	} else {
+		printf("Undefined Log Level: 0x%X", level);
+	}
+
+	return(COMMONERR_OK);
+}
+
+/* if filename null, a default path will be used in logging.c */
+commonErr_t CMB_openLog(const char *filename)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_closeLog(void)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_flushLog(void)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_wait_ms(uint32_t time_ms)
+{
+	mdelay(time_ms);
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_wait_us(uint32_t time_us)
+{
+	udelay(time_us);
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms)
+{
+#ifdef _XPARAMETERS_PS_H_
+	_desired_time_to_elapse_us = timeOut_ms * 1000;
+#else
+	_desired_time_to_elapse_us = timeOut_ms * 50;	// FIXME
+#endif
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_setTimeout_us(uint32_t timeOut_us)
+{
+	_desired_time_to_elapse_us = timeOut_us;
+
+	return(COMMONERR_OK);
+}
+
+
+commonErr_t CMB_hasTimeoutExpired()
+{
+	udelay(1);
+
+	_desired_time_to_elapse_us--;
+	if (_desired_time_to_elapse_us > 0)
+		return(COMMONERR_OK);
+
+	return(COMMONERR_FAILED);
+}
+
+commonErr_t CMB_regRead(uint32_t offset, uint32_t *data)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_regWrite(uint32_t offset, uint32_t data)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len)
+{
+	return(COMMONERR_OK);
+}

datalink814_ge/src/hardware/common.h

@@ -0,0 +1,131 @@
+/**
+ * \file common.h
+ * \brief Contains type definitions and prototype declarations for common.c
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* build project settings include the path to the desired platform folder for correct includes */
+#include "stdint.h"
+
+#define THROW_ERROR()
+
+#define SPIARRAYSIZE 1024
+
+/* assuming 3 byte SPI message - integer math enforces floor() */
+#define SPIARRAYTRIPSIZE ((SPIARRAYSIZE / 3) * 3)
+
+/*========================================
+ * Enums and structures
+ *=======================================*/
+/* proposed to increase number of error return values to make unique for each return */
+typedef enum
+{
+    ADIERR_OK=0,
+    ADIERR_INV_PARM,
+    ADIERR_FAILED
+} ADI_ERR;
+
+/*!< \brief COMMON layer error reporting enumerated types */
+typedef enum
+{
+    COMMONERR_OK=0,
+    COMMONERR_FAILED
+} commonErr_t;
+
+/* bit 0 is MESSAGE, bit 1 is WARNING, bit 2 is ERROR */
+typedef enum
+{
+    ADIHAL_LOG_NONE    = 0x0,
+    ADIHAL_LOG_MESSAGE = 0x1,
+    ADIHAL_LOG_WARNING = 0x2,
+    ADIHAL_LOG_ERROR   = 0x4,
+	ADIHAL_LOG_SPI     = 0x8,
+	ADIHAL_LOG_AXI_REG = 0x10,
+	ADIHAL_LOG_AXI_MEM = 0x20,
+	ADIHAL_LOG_ALL     = 0x3F
+} ADI_LOGLEVEL;
+
+/**
+ * \brief Data structure to hold SPI settings for all system device types
+ */
+typedef struct
+{
+	uint8_t chipSelectIndex;        ///< valid 1~8
+	uint8_t writeBitPolarity;       ///< the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation
+	uint8_t longInstructionWord;    ///< 1 = 16bit instruction word, 0 = 8bit instruction word
+	uint8_t MSBFirst;               ///< 1 = MSBFirst, 0 = LSBFirst
+	uint8_t CPHA;                   ///< clock phase, sets which clock edge the data updates (valid 0 or 1)
+	uint8_t CPOL;                   ///< clock polarity 0 = clock starts low, 1 = clock starts high
+    uint8_t enSpiStreaming;         ///< Not implemented. SW feature to improve SPI throughput.
+    uint8_t autoIncAddrUp;          ///< Not implemented. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr = addr-1
+    uint8_t fourWireMode;           ///< 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode.
+    uint32_t spiClkFreq_Hz;         ///< SPI Clk frequency in Hz (default 25000000), platform will use next lowest frequency that it's baud rate generator can create */
+
+} spiSettings_t;
+
+/* global variable so application layer can set the log level */
+extern ADI_LOGLEVEL CMB_LOGLEVEL;
+extern struct spi_desc 	*spi_ad_desc;
+extern struct gpio_desc	*gpio_ad9371_resetb;
+extern struct gpio_desc	*gpio_ad9528_resetb;
+extern struct gpio_desc	*gpio_ad9528_sysref_req;
+
+/* initialize hardware platform */
+commonErr_t CMB_initPlatform(void);
+
+/* close hardware pointers */
+commonErr_t CMB_closeHardware(void);
+
+/* GPIO function */
+commonErr_t CMB_setGPIO(uint32_t GPIO);
+
+/* hardware reset function */
+commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex);
+
+/* SPI read/write functions */
+commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings); /* allows the platform HAL to work with devices with various SPI settings */
+commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex );  /* value of 0 deasserts all chip selects */
+commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr, uint8_t data); /* single SPI byte write function */
+commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr, uint8_t *data, uint32_t count);
+commonErr_t CMB_SPIReadByte (spiSettings_t *spiSettings, uint16_t addr, uint8_t *readdata); /* single SPI byte read function */
+commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr, uint8_t  field_val, uint8_t mask, uint8_t start_bit); /* write a field in a single register */
+commonErr_t CMB_SPIReadField (spiSettings_t *spiSettings, uint16_t addr, uint8_t *field_val, uint8_t mask, uint8_t start_bit);	/* read a field in a single register */
+
+/* platform timer functions */
+commonErr_t CMB_wait_ms(uint32_t time_ms);
+commonErr_t CMB_wait_us(uint32_t time_us);
+commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms);
+commonErr_t CMB_setTimeout_us(uint32_t timeOut_us);
+commonErr_t CMB_hasTimeoutExpired();
+
+/* platform logging functions */
+commonErr_t CMB_openLog(const char *filename);
+commonErr_t CMB_closeLog(void);
+commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex, uint32_t errorCode, const char *comment);
+commonErr_t CMB_flushLog(void);
+
+/* platform FPGA AXI register read/write functions */
+commonErr_t CMB_regRead(uint32_t offset, uint32_t *data);
+commonErr_t CMB_regWrite(uint32_t offset, uint32_t data);
+
+/* platform DDR3 memory read/write functions */
+commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len);
+commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

datalink814_ge/src/hardware/headless.h

@@ -0,0 +1,348 @@
+/*
+ * headless.h
+ *
+ *  Created on: 2021Äê6ÔÂ8ÈÕ
+ *      Author: Josh
+ */
+
+#ifndef SRC_HEADLESS_H_
+#define SRC_HEADLESS_H_
+
+/***************************** Include Files ********************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include "xil_cache.h"
+#include "xscugic.h"
+//#include "xgpio.h"
+
+#include "common.h"
+#include "./mykonos/ad9528.h"
+#include "./mykonos/mykonos.h"
+#include "./mykonos/Mykonos_M3.h"
+#include "./mykonos/mykonos_gpio.h"
+#include "myk_ad9528init.h"
+#include "myk_init.h"
+
+#include "parameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/*
+*
+* This function setups ad9528 and ad9371 via spi.
+*
+* @param	None.
+*
+* @return
+*       - ADIERR_FAILED if successful,
+*       - ADIERR_OK if not succesful
+*
+* @note     None.
+*
+******************************************************************************/
+int HARDWARE_initialize();
+
+int HARDWARE_ad9371Config(void);
+
+/*****************************************************************************/
+/*
+*
+* Setup up Axi Gpio, through which ad9371 can be reconfigured. Axi Gpio
+* instance and interrupt system initialization are included.
+*
+* @param	None.
+*
+* @return
+*       - ADIERR_FAILED if successful,
+*       - ADIERR_OK if not succesful
+*
+* @note     None.
+*
+******************************************************************************/
+int HW_ad9371DynamicCfgInit(void);
+
+/*****************************************************************************/
+/*
+*
+* Setup up interrupt system, initialize exception handlers.
+*
+* @param	DeviceId is the unique identifier for a device.
+* @param	GicPtr is a pointer to the XScuGic instance.
+*
+* @return
+*       - XST_SUCCESS if successful,
+*       - XST_FAILURE if not succesful
+*
+* @note     None.
+*
+******************************************************************************/
+int HW_setupIntrSystem(u16 DeviceId, XScuGic * GicPtr);
+
+/*****************************************************************************/
+/*
+*
+* Make the connection between the Int_Id of the interrupt source and the
+* associated handler. Set the interrupt priority and trigger type  for the
+* specified IRQ source..
+*
+* @param	GicPtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param	Handler to the handler for that interrupt.
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+*           priority, 0xF8(248) is lowest. There are 32 priority levels
+*           supported with a step of 8. Hence the supported priorities are
+*           0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return
+*       - XST_SUCCESS if successful,
+*       - XST_FAILURE if not succesful
+*
+* @note     None.
+*
+******************************************************************************/
+int HW_connectIntr(XScuGic *GicPtr,u32 IntrId,Xil_InterruptHandler Handler,
+		void *CallBackRef, u8 Priority, u8 Trigger);
+
+/*****************************************************************************/
+/*
+*
+* Initialize Analog Device related configuration profile. This is a HARDWARE-
+* ASSOTIATED function, which may differ between different board.
+*
+* @param	None.
+*
+* @return
+*       - ADIERR_OK if configuration profile exists,
+*       - ADIERR_FAILED if onfiguration profile does not exist
+*
+* @note     None.
+*
+******************************************************************************/
+int HW_adiCfgProfileInit(void);
+
+/******************************************************************************/
+/**
+*
+* This function conducts AD9528 device configuration initializing procedure.
+*
+* @param	clockAD9528_device is a pointer to the data structure holding
+* 			AD9528 settings, which contains basic AD9528 settings such as
+* 			spi and gpio.
+*
+* @return
+*       - ADIERR_OK if successful.
+*       - ADIERR_FAILED if not successful.
+*
+* @note		None.
+*
+*******************************************************************************/
+int HW_9528Config(ad9528Device_t *clockAD9528_device);
+
+/******************************************************************************/
+/**
+*
+* This function read AD9528 reg508 status, to check whether ad9528 is locked or
+* not.
+*
+* @param	clockAD9528_device is a pointer to the data structure holding
+* 			AD9528 settings, which contains basic AD9528 settings.
+*
+* @return
+*       - ADIERR_OK if successful.
+*       - ADIERR_FAILED if not successful.
+*
+* @note		None.
+*
+*******************************************************************************/
+int HW_9528GetLockStatus(ad9528Device_t *device, uint8_t *reg508);
+
+/******************************************************************************/
+/**
+*
+* Conduct AD9371 device configuration initializing procedure.
+*
+* @param	clockAD9528_device is a pointer to the data structure holding
+* 			AD9528 settings, which contains basic AD9528 settings.
+* @param	mykDevice is ADI hardware layer settings pointer specific to
+* 			a Mykonos instance which contains basic settings such as spi,
+* 			gpio, tx/rx and jesd configurations.
+*
+* @return
+*       - ADIERR_OK if successful.
+*       - ADIERR_FAILED if not successful.
+*
+* @note		None.
+*
+*******************************************************************************/
+int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice);
+
+/******************************************************************************/
+/**
+*
+* Read AD9371's RX framer, ORX framer and TX deframer status, to check jesd204b
+* sync status.
+*
+* @param	mykDevice is ADI hardware layer settings pointer specific to
+* 			a Mykonos instance which contains basic settings such as spi,
+* 			gpio, tx/rx and jesd configurations.
+* @param	framerStatus is the RX framer status byte read
+* framerStatus |  Description
+* -------------|-----------------------------------------------------------------------------
+*         [7]  | SYSREF phase error ? a new SYSREF had different timing than the first that set the LMFC timing.
+*         [6]  | Framer lane FIFO read/write pointer delta has changed.  Can help debug issues with deterministic latency.
+*         [5]  | Framer has received the SYSREF and has retimed its LMFC
+*       [4:2]  | Framer ILAS state: 0=CGS, 1= 1st Multframe, 2= 2nd Multiframe, 3= 3rd Multiframe, 4= 4th multiframe, 5= Last multiframe, 6=invalid, 7= ILAS complete
+*       [1:0]  | Framer Tx state: 0=CGS, 1= ILAS, 2 = ADC Data
+* @param	obsFramerStatus is the ORX framer status byte read
+* obsFramerStatus |  Description
+* ----------------|-----------------------------------------------------------------------------
+*            [7]  | SYSREF phase error ? a new SYSREF had different timing than the first that set the LMFC timing.
+*            [6]  | Framer lane FIFO read/write pointer delta has changed.  Can help debug issues with deterministic latency.
+*            [5]  | Framer has received the SYSREF and has retimed its LMFC
+*          [4:2]  | Framer ILAS state: 0=CGS, 1= 1st Multframe, 2= 2nd Multiframe, 3= 3rd Multiframe, 4= 4th multiframe, 5= Last multiframe, 6=invalid, 7= ILAS complete
+*          [1:0]  | Framer Tx state: 0=CGS, 1= ILAS, 2 = ADC Data
+* @param	deframerStatus  is the TX deframer status byte read
+* deframerStatus  |  Bit Name                |  Description
+* ----------------|--------------------------|---------------------------------------------
+*            [7]  | Unused                   | Unused
+*            [6]  | Deframer IRQ             | This bit indicates that the IRQ interrupt was asserted.
+*            [5]  | Deframer SYSREF Received | When this bit is set, it indicates that the SYSREF pulse was received by the deframer IP
+*            [4]  | Deframer Receiver Error  | This bit is set when PRBS has received an error.
+*            [3]  | Valid Checksum           | This bit is set when the received ILAS checksum is valid.
+*            [2]  | EOF Event                | This bit captures the internal status of the framer End of Frame event. Value =1 if framing error during ILAS
+*            [1]  | EOMF Event               | This bit captures the internal status of the framer End of Multi-Frame event. Value =1 if framing error during ILAS
+*            [0]  | FS Lost                  | This bit captures the internal status of the framer Frame Symbol event. Value =1 if framing error during ILAS or user data (invalid replacement characters)
+*
+* @return
+*       - ADIERR_OK if successful.
+*       - ADIERR_FAILED if not successful.
+*
+* @note		None.
+*
+*******************************************************************************/
+int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus,
+		uint8_t *obsFramerStatus, uint8_t *deframerStatus);
+
+/******************************************************************************/
+/**
+*
+* This function conducts AD9371/9375 samll RF PLL frequcny change procedure. The
+* procedure is performed as follows:
+*	1. Move the device into the radio off state.
+*	2. Program the new local oscillator (LO) frequency.
+*	3. Reset the external channel.(ignored)
+* 	4. Move the device back into the radio on state.
+*	5. Reenable tracking calibrations.(ignored)
+*
+* @param	mykDevice is ADI hardware layer settings pointer specific to
+* 			a Mykonos instance which contains basic settings such as spi,
+* 			gpio, tx/rx and jesd configurations.
+* @param	freq_Hz is the target frequancy in Hz.
+*
+* @return	None.
+*
+* @note		The procedure is used when a radio frequency (RF) phased-lock loop
+*		(PLL) change is required with the following conditions:
+*		- A desire to change the Rx, Tx, and ORx frequencies.
+* 		- The frequency step change is less than 100 MHz.
+* 		- The frequency step does not cross the divide by 2 boundaries outlined
+*			in AD9371/9375-UG-992-Rev.B-Table 96.
+*
+*******************************************************************************/
+int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz);
+
+/******************************************************************************/
+/**
+*
+* This function conducts AD9371/9375 large RF PLL frequcny change procedure. The
+* procedure is performed as follows:
+*	1. Move the device into the radio off state.
+*	2. Program the new local oscillator (LO) frequency.
+*	3. Rerun the initialization calibrations.
+* 	4. Move the device back into the radio on state.
+*	5. Reenable tracking calibrations.(ignored)
+*
+* @param	mykDevice is ADI hardware layer settings pointer specific to
+* 			a Mykonos instance which contains basic settings such as spi,
+* 			gpio, tx/rx and jesd configurations.
+* @param	freq_Hz is the target frequancy in Hz.
+*
+* @return	None.
+*
+* @note		The procedure is used when a radio frequency (RF) phased-lock loop
+*		(PLL) change is required with the following conditions:
+*		- A desire to change the Rx, Tx, and ORx frequencies.
+* 		- The frequency step change is more than 100 MHz.
+* 		- The frequency step does cross the divide by 2 boundaries outlined
+*			in AD9371/9375-UG-992-Rev.B-Table 96.
+*
+*******************************************************************************/
+int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz);
+
+/******************************************************************************/
+/**
+*
+* Handles AD9371 TX & RX frequency change axi gpio interruput.
+*
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return	None.
+*
+* @note		None.
+*
+*******************************************************************************/
+void FreqIntrHandler(void *CallbackRef);
+
+/******************************************************************************/
+/**
+*
+* Handles AD9371 Rx gain index change axi gpio interruput.
+*
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return	None.
+*
+* @note		None.
+*
+*******************************************************************************/
+void GainIntrHandler(void *CallbackRef);
+
+/******************************************************************************/
+/**
+*
+* Handles AD9371 Tx attenuation change axi gpio interruput.
+*
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return	None.
+*
+* @note		None.
+*
+*******************************************************************************/
+void AttnIntrHandler(void *CallbackRef);
+
+#endif /* SRC_HEADLESS_H_ */

datalink814_ge/src/hardware/myk_ad9528init.c

@@ -0,0 +1,189 @@
+///*
+// * myk_clock_init.c
+// *
+// */
+//
+///**
+//* \page Disclaimer Legal Disclaimer
+//* Copyright 2015-2017 Analog Devices Inc.
+//* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+//*
+//*/
+//
+//#ifndef MYK_CLOCK_INIT_C_
+//#define MYK_CLOCK_INIT_C_
+//#include <stdint.h>
+//#include <stdlib.h>
+//#include <stddef.h>
+//#include "common.h"
+//
+//#include "ad9528.h"
+//#include "t_ad9528.h"
+//#include "myk_ad9528init.h"
+//#include "parameters.h"
+//
+//static ad9528pll1Settings_t clockPll1Settings =
+//{
+//	.refA_Frequency_Hz  = 30720000,
+//	.refA_Divider       = 1,
+//	.refA_bufferCtrl    = DISABLED,
+//	.refB_Frequency_Hz  = 0,
+//	.refB_Divider       = 1,
+//	.refB_bufferCtrl    = DISABLED,
+//	.vcxo_Frequency_Hz  = 122880000,
+//	.vcxoBufferCtrl     = NEG_SINGLE_ENDED,
+//	.nDivider           = 4,
+//	.bypassPll1			= 0
+//};
+//
+//static ad9528pll2Settings_t clockPll2Settings =
+//{
+//	.rfDivider = 4,
+//	.n2Divider = 10,
+//	.totalNdiv = 30
+//};
+//
+//static ad9528outputSettings_t clockOutputSettings =
+//{
+//	.outPowerDown 		= 53237, // 0xCFF5
+//	.outSource 			= {
+//			CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, SYSREF,
+//			CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV,
+//			CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV,
+//			SYSREF,		 CHANNEL_DIV},
+//	.outBufferCtrl  	= {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+//	.outAnalogDelay 	= {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+//	.outDigitalDelay 	= {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+//	.outChannelDiv 		= {10,10,10,10,10,10,10,10,10,10,10,10,10,10},
+//	.outFrequency_Hz 	= {122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000}
+//};
+//
+//static ad9528sysrefSettings_t clockSysrefSettings =
+//{
+//	.sysrefRequestMethod    = PIN,
+//	.sysrefSource           = INTERNAL,
+//	.sysrefPinEdgeMode      = LEVEL_ACTIVE_HIGH,
+//	.sysrefPinBufferMode    = DISABLED,
+//	.sysrefPatternMode      = NSHOT,
+//	.sysrefNshotMode        = ONE_PULSE,
+//	.sysrefDivide           = 512
+//};
+//
+//static spiSettings_t clockSpiSettings =
+//{
+//	.chipSelectIndex        = AD9528_CS, //chip select Index
+//	.writeBitPolarity       = 0, //Write bit polarity
+//	.longInstructionWord    = 1, //16bit instruction word
+//	.MSBFirst               = 1, //MSB first
+//	.CPHA                   = 0, //Clock phase
+//	.CPOL                   = 0, //Clock polarity
+//	.enSpiStreaming         = 0, //uint8_t enSpiStreaming;
+//	.autoIncAddrUp          = 1, //uint8_t autoIncAddrUp;
+//	.fourWireMode           = 1  //uint8_t fourWireMode;
+//};
+//
+//ad9528Device_t clockAD9528_ =
+//{
+//	&clockSpiSettings,
+//	&clockPll1Settings,
+//	&clockPll2Settings,
+//	&clockOutputSettings,
+//	&clockSysrefSettings
+//};
+//
+//ad9528Device_t *ad9528Init = &clockAD9528_;
+//
+//#endif /* MYK_CLOCK_INIT_C_ */
+
+
+/* AD9528 data structure initialization file */
+#include <stdint.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include "common.h"
+
+#include "./mykonos/ad9528.h"
+#include "./mykonos/t_ad9528.h"
+#include "myk_ad9528init.h"
+#include "parameters.h"
+
+static ad9528pll1Settings_t clockPll1Settings = {
+    .refA_Frequency_Hz  = 122880000,
+    .refA_Divider       = 1,
+    .refA_bufferCtrl    = SINGLE_ENDED,
+    .refB_Frequency_Hz  = 0,
+    .refB_Divider       = 1,
+    .refB_bufferCtrl    = DISABLED,
+    .vcxo_Frequency_Hz  = 122880000,
+    .vcxoBufferCtrl     = DIFFERENTIAL,
+    .nDivider           = 1,
+	.bypassPll1 		= 0
+};
+
+static ad9528pll2Settings_t clockPll2Settings = {
+    .rfDivider = 3,
+    .n2Divider = 10,
+    .totalNdiv = 30
+};
+
+/*******************************************************************
+ * Output Distribution Settings
+ * 9369CE02A uses the following clock outputs
+ * OUT 1: FPGA_REF_CLK
+ * OUT 2: FPGA_AUX_CLK
+ * OUT 3: FPGA_SYSREF
+ * OUT 12: SYSREF_IN
+ * OUT 13: DEV_CLK_IN
+ *******************************************************************
+ */
+static ad9528outputSettings_t clockOutputSettings = {
+    .outPowerDown       = 0x0,
+    .outSource          = {
+    	SYSREF,      SYSREF,      CHANNEL_DIV, SYSREF,
+    	CHANNEL_DIV, CHANNEL_DIV, SYSREF,      SYSREF,
+    	CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV,
+    	SYSREF     , CHANNEL_DIV
+    },
+    .outBufferCtrl      = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+    .outAnalogDelay     = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+    .outDigitalDelay    = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+    .outChannelDiv      = {10,10,10,10,10,10,10,10,10,10,10,10,10,10},
+    .outFrequency_Hz    = {
+    		122880000, 122880000, 122880000, 122880000,
+			122880000, 122880000, 122880000, 122880000,
+			122880000, 122880000, 122880000, 122880000,
+			122880000, 122880000
+    }
+};
+
+static ad9528sysrefSettings_t clockSysrefSettings = {
+    .sysrefRequestMethod    = SPI,
+    .sysrefSource           = INTERNAL,
+    .sysrefPinEdgeMode      = LEVEL_ACTIVE_HIGH,
+    .sysrefPinBufferMode    = DISABLED,
+    .sysrefPatternMode      = CONTINUOUS,
+    .sysrefNshotMode        = FOUR_PULSES,
+    .sysrefDivide           = 512
+};
+
+static spiSettings_t clockSpiSettings = {
+    .chipSelectIndex        = 2, //chip select Index
+    .writeBitPolarity       = 0, //Write bit polarity
+    .longInstructionWord    = 1, //16bit instruction word
+    .MSBFirst               = 1, //MSB first
+    .CPHA                   = 0, //Clock phase
+    .CPOL                   = 0, //Clock polarity
+    .enSpiStreaming         = 0, //uint8_t enSpiStreaming;
+    .autoIncAddrUp          = 1, //uint8_t autoIncAddrUp;
+    .fourWireMode           = 1  //uint8_t fourWireMode;
+};
+
+ad9528Device_t clockAD9528_ = {
+    &clockSpiSettings,
+    &clockPll1Settings,
+    &clockPll2Settings,
+    &clockOutputSettings,
+    &clockSysrefSettings
+};
+
+ad9528Device_t *ad9528Init = &clockAD9528_;

datalink814_ge/src/hardware/myk_ad9528init.h

@@ -0,0 +1,20 @@
+/*
+ * myk_clock_init.h
+ *
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef MYK_CLOCK_INIT_H_
+#define MYK_CLOCK_INIT_H_
+
+#include "./mykonos/ad9528.h"
+
+extern ad9528Device_t *ad9528Init;
+
+#endif /* MYK_CLOCK_INIT_H_ */

datalink814_ge/src/hardware/myk_init.c

@@ -0,0 +1,558 @@
+/**
+ * \file myk_init.c
+ *
+ * \brief Contains init setting structure declarations for the _instance API
+ *
+ * The top level structure mykonosDevice_t mykDevice uses keyword
+ * extern to allow the application layer main() to have visibility
+ * to these settings.
+ *
+ * All data structures required for operation have been initialized with values which reflect
+ * these settings:
+ *
+ * Device Clock = $122.88$ Mhz
+ * Rx enabled channels = $2$
+ * Tx enabled channels = $2$
+ *
+ * Mykonos Framer:
+ * Lane Rate = $4915.2$ Mbs
+ * L = $2$
+ * K = $32$
+ * M = $4$
+ * F = $4$
+ *
+ * Mykonos Deframer:
+ * Lane Rate = $4915.2$ Mbs
+ * L = $2$
+ * K = $32$
+ * M = $4$
+ * F = $4$
+ *
+ * Mykonos Observation framer:
+ * Lane Rate = $4915.2$ Mbs
+ * L = $2$
+ * K = $32$
+ * M = $4$
+ * F = $4$
+ *
+ * Using these profiles:
+ * $Rx 100Mhz, IQrate 122.88Mhz, Dec5$
+ * $Tx 100/100Mhz, IQrate 122.88Mhz, Dec5$
+ * $ORX 100Mhz, IQrate 122.88Mhz, Dec5$
+ * $SRx 20Mhz, IQrate 30.72Mhz, Dec5$
+ *
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#include <stddef.h>
+#include "./mykonos/t_mykonos.h"
+#include "myk_init.h"
+#include "parameters.h"
+#include "./mykonos/mykonos_gpio.h"
+
+static int16_t txFirCoefs[] = {-94,-26,282,177,-438,-368,756,732,-1170,-1337,1758,2479,-2648,-5088,4064,16760,16759,4110,-4881,-2247,2888,1917,-1440,-1296,745,828,-358,-474,164,298,-16,-94};
+
+static mykonosFir_t txFir =
+{
+    6,              /* Filter gain in dB*/
+    32,             /* Number of coefficients in the FIR filter*/
+    &txFirCoefs[0]  /* A pointer to an array of filter coefficients*/
+};
+
+static int16_t rxFirCoefs[] = {-20,6,66,22,-128,-54,240,126,-402,-248,634,444,-956,-756,1400,1244,-2028,-2050,2978,3538,-4646,-7046,9536,30880,30880,9536,-7046,-4646,3538,2978,-2050,-2028,1244,1400,-756,-956,444,634,-248,-402,126,240,-54,-128,22,66,6,-20};
+
+static mykonosFir_t rxFir =
+{
+    -6,             /* Filter gain in dB*/
+    48,             /* Number of coefficients in the FIR filter*/
+    &rxFirCoefs[0]  /* A pointer to an array of filter coefficients*/
+};
+
+static int16_t obsrxFirCoefs[] = {-14,-19,44,41,-89,-95,175,178,-303,-317,499,527,-779,-843,1184,1317,-1781,-2059,2760,3350,-4962,-7433,9822,32154,32154,9822,-7433,-4962,3350,2760,-2059,-1781,1317,1184,-843,-779,527,499,-317,-303,178,175,-95,-89,41,44,-19,-14};
+static mykonosFir_t obsrxFir =
+{
+    -6,             /* Filter gain in dB*/
+    48,             /* Number of coefficients in the FIR filter*/
+    &obsrxFirCoefs[0]/* A pointer to an array of filter coefficients*/
+};
+
+static int16_t snifferFirCoefs[] = {-1,-5,-14,-23,-16,24,92,137,80,-120,-378,-471,-174,507,1174,1183,98,-1771,-3216,-2641,942,7027,13533,17738,17738,13533,7027,942,-2641,-3216,-1771,98,1183,1174,507,-174,-471,-378,-120,80,137,92,24,-16,-23,-14,-5,-1};
+static mykonosFir_t snifferRxFir=
+{
+    -6,             /* Filter gain in dB*/
+    48,             /* Number of coefficients in the FIR filter*/
+    &snifferFirCoefs[0]/* A pointer to an array of filter coefficients*/
+};
+
+static mykonosJesd204bFramerConfig_t rxFramer =
+{
+    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
+    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
+    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
+    4,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
+    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
+    0,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
+    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/
+    0x03,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
+    0xE4,           /* serializerLaneCrossbar*/
+    22,             /* serializerAmplitude - default 22 (valid (0-31)*/
+    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/
+    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
+    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
+    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
+    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
+    0,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
+    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
+    0,              /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
+    0               /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/
+};
+
+static mykonosJesd204bFramerConfig_t obsRxFramer =
+{
+    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
+    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
+    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
+    2,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
+    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
+    0,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
+    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/
+    0x04,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
+    0xE4,           /* Lane crossbar to map framer lane outputs to physical lanes*/
+    22,             /* serializerAmplitude - default 22 (valid (0-31)*/
+    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/
+    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
+    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
+    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
+    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
+    1,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
+    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
+    0,              /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
+    0               /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/
+};
+
+static mykonosJesd204bDeframerConfig_t deframer =
+{
+    0,              /* bankId extension to Device ID (Valid 0..15)*/
+    0,              /* deviceId  link identification number. (Valid 0..255)*/
+    0,              /* lane0Id Lane0 ID. (Valid 0..31)*/
+    4,              /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
+    32,             /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)*/
+    0,              /* scramble  scrambling off if scramble= 0.*/
+    1,              /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/
+    0x03,           /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
+    0xE4,           /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */
+    1,              /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/
+    0,              /* PN inversion per each lane.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).*/
+    0,              /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/
+    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set*/
+    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
+    0,              /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
+    0               /* Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used*/
+};
+
+static mykonosRxGainControl_t rxGainControl =
+{
+    MGC,            /* Current Rx gain control mode setting*/
+    255,            /* Rx1 Gain Index, can be used in different ways for manual and AGC gain control*/
+    255,            /* Rx2 Gain Index, can be used in different ways for manual and AGC gain control*/
+    255,            /* Max gain index for the currently loaded Rx1 Gain table*/
+    195,            /* Min gain index for the currently loaded Rx1 Gain table*/
+    255,            /* Max gain index for the currently loaded Rx2 Gain table*/
+    195,            /* Min gain index for the currently loaded Rx2 Gain table*/
+    0,              /* Stores Rx1 RSSI value read back from the Mykonos*/
+    0               /* Stores Rx2 RSSI value read back from the Mykonos*/
+};
+
+
+static mykonosORxGainControl_t orxGainControl =
+{
+    MGC,            /* Current ORx gain control mode setting*/
+    255,            /* ORx1 Gain Index, can be used in different ways for manual and AGC gain control*/
+    255,            /* ORx2 Gain Index, can be used in different ways for manual and AGC gain control*/
+    255,            /* Max gain index for the currently loaded ORx Gain table*/
+    237             /* Min gain index for the currently loaded ORx Gain table*/
+};
+
+static mykonosSnifferGainControl_t snifferGainControl =
+{
+    MGC,            /* Current Sniffer gain control mode setting*/
+    255,            /* Current Sniffer gain index. Can be used differently for MANUAL Gain control/AGC*/
+    255,            /* Max gain index for the currently loaded Sniffer Gain table*/
+    203             /* Min gain index for the currently loaded Sniffer Gain table*/
+};
+
+static mykonosPeakDetAgcCfg_t rxPeakAgc =
+{
+	0x0C,	/* apdHighThresh: */
+	0x08,	/* apdLowThresh */
+	0xB5,	/* hb2HighThresh */
+	0x80,	/* hb2LowThresh */
+	0x40,	/* hb2VeryLowThresh */
+	0x06,	/* apdHighThreshExceededCnt */
+	0x04,	/* apdLowThreshExceededCnt */
+	0x06,	/* hb2HighThreshExceededCnt */
+	0x04,	/* hb2LowThreshExceededCnt */
+	0x04,	/* hb2VeryLowThreshExceededCnt */
+	0x4,	/* apdHighGainStepAttack */
+	0x2,	/* apdLowGainStepRecovery */
+	0x4,	/* hb2HighGainStepAttack */
+	0x2,	/* hb2LowGainStepRecovery */
+	0x4,	/* hb2VeryLowGainStepRecovery */
+	0x1,	/* apdFastAttack */
+	0x1,	/* hb2FastAttack */
+	0x1,	/* hb2OverloadDetectEnable */
+	0x1,	/* hb2OverloadDurationCnt */
+	0x1	/* hb2OverloadThreshCnt */
+};
+
+static mykonosPowerMeasAgcCfg_t rxPwrAgc =
+{
+    0x01,	/* pmdUpperHighThresh */
+    0x03,	/* pmdUpperLowThresh */
+    0x0C,	/* pmdLowerHighThresh */
+    0x00,	/* pmdLowerLowThresh */
+    0x4,	/* pmdUpperHighGainStepAttack */
+    0x2,	/* pmdUpperLowGainStepAttack */
+    0x2,	/* pmdLowerHighGainStepRecovery */
+    0x4,	/* pmdLowerLowGainStepRecovery */
+    0x08,	/* pmdMeasDuration */
+    0x02	/* pmdMeasConfig */
+};
+
+static mykonosAgcCfg_t rxAgcConfig =
+{
+    255,	/* agcRx1MaxGainIndex */
+    195,	/* agcRx1MinGainIndex */
+    255,	/* agcRx2MaxGainIndex */
+    195,	/* agcRx2MinGainIndex: */
+    255,	/* agcObsRxMaxGainIndex */
+    203,	/* agcObsRxMinGainIndex */
+    1,		/* agcObsRxSelect */
+    1,		/* agcPeakThresholdMode */
+    1,		/* agcLowThsPreventGainIncrease */
+	30720,	/* agcGainUpdateCounter */
+    3,	/* agcSlowLoopSettlingDelay */
+    2,	/* agcPeakWaitTime */
+    1,	/* agcResetOnRxEnable */
+    0,	/* agcEnableSyncPulseForGainCounter */
+    &rxPeakAgc,
+    &rxPwrAgc
+};
+
+static mykonosPeakDetAgcCfg_t obsRxPeakAgc =
+{
+	0x1F,	/* apdHighThresh: */
+	0x16,	/* apdLowThresh */
+	0xB5,	/* hb2HighThresh */
+	0x80,	/* hb2LowThresh */
+	0x40,	/* hb2VeryLowThresh */
+	0x06,	/* apdHighThreshExceededCnt */
+	0x04,	/* apdLowThreshExceededCnt */
+	0x06,	/* hb2HighThreshExceededCnt */
+	0x04,	/* hb2LowThreshExceededCnt */
+	0x04,	/* hb2VeryLowThreshExceededCnt */
+	0x4,	/* apdHighGainStepAttack */
+	0x2,	/* apdLowGainStepRecovery */
+	0x4,	/* hb2HighGainStepAttack */
+	0x2,	/* hb2LowGainStepRecovery */
+	0x4,	/* hb2VeryLowGainStepRecovery */
+	0x1,	/* apdFastAttack */
+	0x1,	/* hb2FastAttack */
+	0x1,	/* hb2OverloadDetectEnable */
+	0x1,	/* hb2OverloadDurationCnt */
+	0x1		/* hb2OverloadThreshCnt */
+};
+
+static mykonosPowerMeasAgcCfg_t obsRxPwrAgc =
+{
+    0x01,	/* pmdUpperHighThresh */
+    0x03,	/* pmdUpperLowThresh */
+    0x0C,	/* pmdLowerHighThresh */
+    0x00,	/* pmdLowerLowThresh */
+    0x4,	/* pmdUpperHighGainStepAttack */
+    0x2,	/* pmdUpperLowGainStepAttack */
+    0x2,	/* pmdLowerHighGainStepRecovery */
+    0x4,	/* pmdLowerLowGainStepRecovery */
+    0x08,	/* pmdMeasDuration */
+    0x02	/* pmdMeasConfig */
+};
+
+static mykonosAgcCfg_t obsRxAgcConfig =
+{
+    255,	/* agcRx1MaxGainIndex */
+    195,	/* agcRx1MinGainIndex */
+    255,	/* agcRx2MaxGainIndex */
+    195,	/* agcRx2MinGainIndex: */
+    255,	/* agcObsRxMaxGainIndex */
+    203,	/* agcObsRxMinGainIndex */
+    1,		/* agcObsRxSelect */
+    1,		/* agcPeakThresholdMode */
+    1,		/* agcLowThsPreventGainIncrease */
+	30720,	/* agcGainUpdateCounter */
+    3,		/* agcSlowLoopSettlingDelay */
+    2,		/* agcPeakWaitTime */
+    1,		/* agcResetOnRxEnable */
+    0,		/* agcEnableSyncPulseForGainCounter */
+    &obsRxPeakAgc,
+    &obsRxPwrAgc
+};
+
+
+static mykonosRxProfile_t rxProfile =
+{/* Rx 100MHz, IQrate 122.88MSPS, Dec5 */
+    1,              /* The divider used to generate the ADC clock*/
+    &rxFir,         /* Pointer to Rx FIR filter structure*/
+    2,              /* Rx FIR decimation (1,2,4)*/
+    5,              /* Decimation of Dec5 or Dec4 filter (5,4)*/
+    1,              /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
+    1,              /* RX Half band 1 decimation (1 or 2)*/
+    122880,         /* Rx IQ data rate in kHz*/
+    100000000,      /* The Rx RF passband bandwidth for the profile*/
+    100000,         /* Rx BBF 3dB corner in kHz*/
+    NULL            /* pointer to custom ADC profile*/
+};
+
+static mykonosRxProfile_t orxProfile =
+{/* ORX 100MHz, IQrate 122.88MSPS, Dec5 */
+    1,              /* The divider used to generate the ADC clock*/
+    &obsrxFir,      /* Pointer to Rx FIR filter structure or NULL*/
+    2,              /* Rx FIR decimation (1,2,4)*/
+    5,              /* Decimation of Dec5 or Dec4 filter (5,4)*/
+    0,              /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
+    1,              /* RX Half band 1 decimation (1 or 2)*/
+    122880,         /* Rx IQ data rate in kHz*/
+    100000000,      /* The Rx RF passband bandwidth for the profile*/
+    100000,         /* Rx BBF 3dB corner in kHz*/
+    NULL            /* pointer to custom ADC profile*/
+};
+
+
+static mykonosRxProfile_t snifferProfile =
+{ /* SRx 20MHz, IQrate 30.72MSPS, Dec5 */
+    1,              /* The divider used to generate the ADC clock*/
+    &snifferRxFir,  /* Pointer to Rx FIR filter structure or NULL*/
+    4,              /* Rx FIR decimation (1,2,4)*/
+    5,              /* Decimation of Dec5 or Dec4 filter (5,4)*/
+    0,              /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
+    2,              /* RX Half band 1 decimation (1 or 2)*/
+    30720,          /* Rx IQ data rate in kHz*/
+    10000000,       /* The Rx RF passband bandwidth for the profile*/
+    100000,         /* Rx BBF 3dB corner in kHz*/
+    NULL            /* pointer to custom ADC profile*/
+};
+
+
+
+static mykonosTxProfile_t txProfile =
+{ /* Tx 20/100MHz, IQrate 122.88MSPS, Dec5 */
+    DACDIV_2p5,     /* The divider used to generate the DAC clock*/
+    &txFir,         /* Pointer to Tx FIR filter structure*/
+    2,              /* The Tx digital FIR filter interpolation (1,2,4)*/
+    2,              /* Tx Halfband1 filter interpolation (1,2)*/
+    1,              /* Tx Halfband2 filter interpolation (1,2)*/
+    1,              /* TxInputHbInterpolation (1,2)*/
+    122880,         /* Tx IQ data rate in kHz*/
+	100000000,      /* Primary Signal BW*/
+    100000000,      /* The Tx RF passband bandwidth for the profile*/
+    710539,         /* The DAC filter 3dB corner in kHz*/
+    50000,          /* Tx BBF 3dB corner in kHz*/
+    0               /* Enable DPD, only valid for AD9373*/
+};
+
+static mykonosDigClocks_t mykonosClocks =
+{
+    122880,         /* CLKPLL and device reference clock frequency in kHz*/
+    9830400,        /* CLKPLL VCO frequency in kHz*/
+    VCODIV_2,       /* CLKPLL VCO divider*/
+    4               /* CLKPLL high speed clock divider*/
+};
+
+static mykonosRxSettings_t  rxSettings =
+{
+    &rxProfile,     /* Rx datapath profile, 3dB corner frequencies, and digital filter enables*/
+    &rxFramer,      /* Rx JESD204b framer configuration structure*/
+    &rxGainControl, /* Rx Gain control settings structure*/
+    &rxAgcConfig,   /* Rx AGC control settings structure*/
+	RX1_RX2,        /* The desired Rx Channels to enable during initialization*/
+    0,              /* Internal LO = 0, external LO*2 = 1*/
+    2550000000U,    /* Rx PLL LO Frequency (internal or external LO)*/
+    0               /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data*/
+};
+
+static mykonosDpdConfig_t dpdConfig =
+{
+    5,              /* 1/2^(damping + 8) fraction of power `forgotten' per sample (default: `1/8192' = 5, valid 0 to 15), 0 = infinite damping*/
+    1,              /* number of weights to use for int8_cpx weights weights member of this structure (default = 1)*/
+    2,              /* DPD model version: one of four different generalized polynomial models: 0 = same as R0 silicon, 1-3 are new and the best one depends on the PA (default: 2)*/
+    1,              /* 1 = Update saved model whenever peak Tx digital RMS is within 1dB of historical peak Tx RMS*/
+    20,             /* Determines how much weight the loaded prior model has on DPD modeling (Valid 0 - 32, default 20)*/
+    0,              /* Default off = 0, 1=enables automatic outlier removal during DPD modeling */
+    512,            /* Number of samples to capture (default: 512, valid 64-32768)*/
+    4096,           /* threshold for sample in AM-AM plot outside of 1:1 line to be thrown out. (default: 50% = 8192/2, valid 8192 to 1)*/
+    0,              /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
+    255,            /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range  1 to 8191)*/
+    {{64,0},{0,0},{0,0}}/* DPD model error weighting (real/imag valid from -128 to 127)*/
+};
+
+static mykonosClgcConfig_t clgcConfig =
+{
+    -2000,          /* (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx1 output to ORx1 input in (dB * 100)*/
+    -2000,          /* (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx2 output to ORx2 input in (dB * 100)*/
+    0,              /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx1Atten is not reduced below the limit*/
+    0,              /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx2Atten is not reduced below the limit*/
+    75,             /* valid range 1-100, default 75*/
+    75,             /* valid range 1-100, default 45*/
+    0,              /* 0= allow CLGC to run, but Tx1Atten will not be updated. User can still read back power measurements.  1=CLGC runs, and Tx1Atten automatically updated*/
+    0,              /* 0= allow CLGC to run, but Tx2Atten will not be updated. User can still read back power measurements.  1=CLGC runs, and Tx2Atten automatically updated*/
+    0,              /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
+    255,            /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range  1 to 8191)*/
+    600,            /* Threshold for Tx1 in order to stop tracking, value = 100 * dB, default 6db then value = 600*/
+    600,            /* Threshold for Tx2 in order to stop tracking, value = 100 * dB, default 6db then value = 600*/
+    0,              /* Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0*/
+    0               /* Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0*/
+};
+
+static mykonosVswrConfig_t vswrConfig =
+{
+    0,              /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
+    255,            /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range  1 to 8191)*/
+    0,              /* 3p3V GPIO pin to use to control VSWR switch for Tx1 (valid 0-11) (output from Mykonos)*/
+    1,              /* 3p3V GPIO pin to use to control VSWR switch for Tx2 (valid 0-11) (output from Mykonos)*/
+    0,              /* 3p3v GPIO pin polarity for forward path of Tx1, opposite used for reflection path (1 = high level, 0 = low level)*/
+    0,              /* 3p3v GPIO pin polarity for forward path of Tx2, opposite used for reflection path (1 = high level, 0 = low level)*/
+    50,             /* Delay for Tx1 after flipping the VSWR switch until measurement is made. In us resolution*/
+    50              /* Delay for Tx2 after flipping the VSWR switch until measurement is made. In us resolution*/
+};
+
+static mykonosTxSettings_t txSettings =
+{
+    &txProfile,     /* Tx datapath profile, 3dB corner frequencies, and digital filter enables*/
+    &deframer,      /* Mykonos JESD204b deframer config for the Tx data path*/
+    TX1_TX2,        /* The desired Tx channels to enable during initialization*/
+    0,              /* Internal LO=0, external LO*2 if =1*/
+    2500000000U,    /* Tx PLL LO frequency (internal or external LO)*/
+    TXATTEN_0P05_DB,/* Initial and current Tx1 Attenuation*/
+    10000,          /* Initial and current Tx1 Attenuation mdB*/
+    10000,          /* Initial and current Tx2 Attenuation mdB*/
+    NULL,           /* DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL otherwise*/
+    NULL,           /* CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
+    NULL            /* VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
+};
+
+
+static mykonosObsRxSettings_t obsRxSettings =
+{
+    &orxProfile,    /* ORx datapath profile, 3dB corner frequencies, and digital filter enables*/
+    &orxGainControl,/* ObsRx gain control settings structure*/
+    &obsRxAgcConfig,/* ORx AGC control settings structure*/
+    &snifferProfile,/* Sniffer datapath profile, 3dB corner frequencies, and digital filter enables*/
+    &snifferGainControl,/* SnRx gain control settings structure*/
+    &obsRxFramer,   /* ObsRx JESD204b framer configuration structure */
+    (MYK_ORX1_ORX2 | MYK_SNRXA_B_C),/* obsRxChannel */
+    OBSLO_TX_PLL,   /* (obsRxLoSource) The Obs Rx mixer can use the Tx Synth(TX_PLL) or Sniffer Synth (SNIFFER_PLL) */
+    2600000000U,    /* SnRx PLL LO frequency in Hz */
+    0,              /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where if > 0 = real IF data, '0' = complex data*/
+    NULL,           /* Custom Loopback ADC profile to set the bandwidth of the ADC response */
+    OBS_RXOFF       /* Default ObsRx channel to enter when radioOn called */
+};
+
+static mykonosArmGpioConfig_t armGpio =
+{
+    1,	// useRx2EnablePin; /*!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate RX1_ENABLE/RX2_ENABLE pins */
+    1,	// useTx2EnablePin; /*!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate TX1_ENABLE/TX2_ENABLE pins */
+    1,	// txRxPinMode;     /*!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx chains */
+    0,	// orxPinMode;      /*!< 0= ARM command mode, 1 = Pin mode to power up ObsRx receiver*/
+
+    /*Mykonos ARM input GPIO pins -- Only valid if orxPinMode = 1 */
+    0,	// orxTriggerPin; /*!< Select desired GPIO pin (valid 4-15) */
+    0,	// orxMode2Pin;   /*!< Select desired GPIO pin (valid 0-18) */
+    0,	// orxMode1Pin;   /*!< Select desired GPIO pin (valid 0-18) */
+    0,	// orxMode0Pin;   /*!< Select desired GPIO pin (valid 0-18) */
+
+    /* Mykonos ARM output GPIO pins  --  always available, even when pin mode not enabled*/
+    0,	// rx1EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// rx2EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// tx1EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// tx2EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// orx1EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// orx2EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// srxEnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0 	// txObsSelect;   /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    /* When 2Tx are used with only 1 ORx input, this GPIO tells the BBIC which Tx channel is   */
+    /* active for calibrations, so BBIC can route correct RF Tx path into the single ORx input*/
+};
+
+static mykonosGpio3v3_t gpio3v3 =
+{
+    0,				/*!< Oe per pin, 1=output, 0 = input */
+    GPIO3V3_BITBANG_MODE,	/*!< Mode for GPIO3V3[3:0] */
+    GPIO3V3_BITBANG_MODE,	/*!< Mode for GPIO3V3[7:4] */
+    GPIO3V3_BITBANG_MODE,	/*!< Mode for GPIO3V3[11:8] */
+};
+
+static mykonosGpioLowVoltage_t gpio =
+{
+    0,/* Oe per pin, 1=output, 0 = input */
+    GPIO_MONITOR_MODE,/* Mode for GPIO[3:0] */
+    GPIO_MONITOR_MODE,/* Mode for GPIO[7:4] */
+    GPIO_MONITOR_MODE,/* Mode for GPIO[11:8] */
+    GPIO_MONITOR_MODE,/* Mode for GPIO[15:12] */
+    GPIO_MONITOR_MODE,/* Mode for GPIO[18:16] */
+};
+
+static mykonosAuxIo_t mykonosAuxIo =
+{
+    0,	//auxDacEnableMask uint16_t
+    {0,0,0,0,0,0,0,0,0,0},	 //AuxDacValue uint16[10]
+    {0,0,0,0,0,0,0,0,0,0},	 //AuxDacSlope uint8[10]
+    {0,0,0,0,0,0,0,0,0,0},	 //AuxDacVref uint8[10]
+    &gpio3v3,	//pointer to gpio3v3 struct
+    &gpio,	//pointer to gpio1v8 struct
+    &armGpio
+};
+
+static spiSettings_t mykSpiSettings =
+{
+    1, /* chip select index - valid 1~8 */
+    0, /* the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation */
+    1, /* 1 = 16-bit instruction word, 0 = 8-bit instruction word */
+    1, /* 1 = MSBFirst, 0 = LSBFirst */
+    0, /* clock phase, sets which clock edge the data updates (valid 0 or 1) */
+    0, /* clock polarity 0 = clock starts low, 1 = clock starts high */
+    0, /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
+    1, /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
+    1  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
+};
+
+static mykonosTempSensorConfig_t tempSensor =
+{
+    7,              /* 3-bit value that controls the AuxADC decimation factor when used for temp sensor calculations; AuxADC_decimation = 256 * 2^tempDecimation*/
+    67,             /* 8-bit offset that gets added to temp sensor code internally*/
+    1,              /* this bit overrides the factory-calibrated fuse offset and uses the value stored in the offset member*/
+    15,             /* 4-bit code with a resolution of 1°C/LSB, each time a temperature measurement is performed, the device compares the current temperature against the previous value.*/
+};
+
+static mykonosTempSensorStatus_t tempStatus =
+{
+    0,              /* 16-bit signed temperature value (in deg C) that is read back*/
+    0,              /* If the absolute value of the difference is greater than the value in temperature configuration tempWindow, the windowExceeded flag is set.*/
+    0,              /* when windowExceeded member gets set, this bit is set to 1 if current value is greater than previous value, else reset*/
+    0,              /* when the reading is complete and a valid temperature value stored in tempCode.*/
+};
+
+mykonosDevice_t mykDevice =
+{
+    &mykSpiSettings,    /* SPI settings data structure pointer */
+    &rxSettings,        /* Rx settings data structure pointer */
+    &txSettings,        /* Tx settings data structure pointer */
+    &obsRxSettings,     /* ObsRx settings data structure pointer */
+    &mykonosAuxIo,          /* Auxiliary IO settings data structure pointer */
+    &mykonosClocks,     /* Holds settings for CLKPLL and reference clock */
+    0                   /* Mykonos initialize function uses this as an output to remember which profile data structure pointers are valid */
+};

datalink814_ge/src/hardware/myk_init.h

@@ -0,0 +1,24 @@
+/**
+ * \file myk_init.h
+ *
+ * \brief Contains structure definitions for myk_init.c
+ *
+ * The top level structure mykonosDevice_t mykDevice uses keyword
+ * extern to allow the application layer main() to have visibility
+ * to these settings.
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef MYK_INIT_H_
+#define MYK_INIT_H_
+
+
+extern mykonosDevice_t mykDevice;
+
+#endif

datalink814_ge/src/hardware/mykonos/Mykonos_M3.h

@@ -0,0 +1,13 @@
+/**
+SOFTWARE LICENSE AGREEMENT
+20180301-AD937X-CTSLA
+**/
+
+// Version 5.2.2
+#ifndef SRC_MYKONOS_BIN_H_
+#define SRC_MYKONOS_BIN_H_
+
+unsigned char firmware_Mykonos_M3_bin[];
+unsigned int firmware_Mykonos_M3_bin_len;
+
+#endif

datalink814_ge/src/hardware/mykonos/ad9528.c

@@ -0,0 +1,740 @@
+/**
+ * \file ad9528.c
+ * \brief Contains source code for configuring and initializing AD9528 clock device
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#include "ad9528.h"
+
+/**
+ * \brief Performs a hard reset on the AD9528 DUT
+ *
+ * <B>Dependencies</B>
+ * - device->spiSettings->chipSelectIndex
+ *
+ * \param device is structure pointer to the AD9528 data structure containing settings
+ * \return Returns enum ADI_ERR, ADIERR_OK=pass, !ADIERR_OK=fail
+ */
+ADI_ERR AD9528_resetDevice(ad9528Device_t *device)
+{
+    /* toggle RESETB on device with matching spi chip select index */
+    CMB_hardReset(device->spiSettings->chipSelectIndex);
+    return ADIERR_OK;
+}
+
+/**
+ * \brief Sets the AD9528 device SPI settings (3wire/4wire, MSBFirst, etc).
+ *
+ * This function will use the settings in the device->spiSettings structure
+ * to set SPI stream mode, address auto increment direction, MSBFirst/LSBfirst,
+ * and 3wire/4wire mode.  The AD9528 device always uses SPI MODE 0 (CPHA=0, CPOL=0).
+ * This function will update your device->spiSettings to set CHPA=0 and CPOL=0 and
+ * longInstructionWord =1 to use a 16bit instruction word.
+ *
+ * <B>Dependencies</B>
+ * - writes device->spiSettings->CPHA = 0
+ * - writes device->spiSettings->CPOL = 0
+ * - writes device->spiSettings->longInstructionWord = 1
+ *
+ * - device->spiSettings->MSBFirst
+ * - device->spiSettings->enSpiStreaming
+ * - device->spiSettings->autoIncAddrUp
+ * - device->spiSettings->fourWireMode
+ *
+ * \param device is structure pointer to the AD9528 data structure containing settings
+ *
+ * \return Returns enum ADI_ERR, ADIERR_OK=pass, !ADIERR_OK=fail
+ */
+ADI_ERR AD9528_setSpiSettings(ad9528Device_t *device)
+{
+    //device->spiSettings->enSpiStreaming
+    uint8_t spiReg = 0;
+
+    device->spiSettings->CPHA = 0;
+    device->spiSettings->CPOL = 0;
+    device->spiSettings->longInstructionWord = 1;
+
+    if (device->spiSettings->MSBFirst == 0)
+    {
+        spiReg |= 0x42; /* SPI bit is 1=LSB first */
+    }
+
+    if (device->spiSettings->autoIncAddrUp > 0)
+    {
+        spiReg |= 0x24;
+    }
+
+    if (device->spiSettings->fourWireMode > 0)
+    {
+        spiReg |= 0x18;
+    }
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_A, spiReg);
+
+    if (device->spiSettings->enSpiStreaming > 0)
+    {
+        /* Allow SPI streaming mode: SPI message ends when chip select deasserts */
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x00);
+    }
+    else
+    {
+        /* Force single instruction mode */
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x80);
+    }
+
+    return ADIERR_OK;
+}
+
+
+/**
+ * \brief Helper function for ADI transceiver eval boards to init the AD9528 data structure
+ *
+ * This function inits the AD9528 device data structure with defaults that
+ * are known to work with the ADI AD9369 and AD9371 evaluation boards.  NOTE: This function will
+ * modify the contents of the AD9528 device data structure.
+ *
+ * <B>Dependencies</B>
+ * - spi->chipSelectIndex
+ * - spi
+ *
+ * \param device Pointer to the AD9528 device data structure to initialize
+ * \param vcxoFrequency_Hz The VCXO frequency that is connected to the AD9528
+ * \param refAFrequency_Hz The reference clock frequency being input into the AD9528 REFCLK A input
+ * \param outputDeviceClock_Hz Desired output clock frequency to the FPGA and transceiver device
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+*/
+ADI_ERR AD9528_initDeviceDataStruct(ad9528Device_t *device, uint32_t vcxoFrequency_Hz, uint32_t refAFrequency_Hz, uint32_t outputDeviceClock_Hz)
+{
+//    uint16_t chDiv;
+//    uint8_t i = 0;
+//
+//    uint32_t pll1PfdFreq_Hz = 0;
+//    uint8_t pll1Ndiv = 0;
+//    uint8_t validPll1DivSetting = 0;
+//    uint8_t refAdiv = 1;
+//
+//
+//    uint8_t pll2RfDiv = 3; /* Valid values 3,4,5 */
+//    uint16_t pll2Ndiv = 1; /* Valid values 1-256 */
+//    uint32_t pll2InputFreq_Hz = 0;
+//    uint64_t pll2VcoFreq_Hz = 0;
+//    uint16_t pll2NdivStart = 0;
+//    uint8_t validPll2DivSetting = 0;
+//    uint64_t chDivU64 = 0;
+//
+//    static const uint64_t PLL2_MIN_VCO_FREQ_HZ = 3450000000ULL;
+//    static const uint64_t PLL2_MAX_VCO_FREQ_HZ = 4025000000ULL;
+//    /*******************************************************************
+//     * PLL1 Settings
+//     *******************************************************************
+//     */
+//
+//    /* find valid PLL1 Ndiv and REFA div */
+//    for (pll1Ndiv = 1; pll1Ndiv < 20; pll1Ndiv++)
+//    {
+//        pll1PfdFreq_Hz = vcxoFrequency_Hz / pll1Ndiv;
+//
+//        if ((pll1PfdFreq_Hz <= 110000000) && (pll1PfdFreq_Hz >= 1000000) &&
+//            (pll1PfdFreq_Hz <= refAFrequency_Hz) &&
+//            (refAFrequency_Hz % pll1PfdFreq_Hz == 0)
+//           )
+//        {
+//            validPll1DivSetting = 1;
+//            refAdiv = refAFrequency_Hz / pll1PfdFreq_Hz ;
+//            break;
+//        }
+//    }
+//
+//    if (validPll1DivSetting == 0)
+//    {
+//        return ADIERR_INV_PARM;
+//    }
+//
+//    device->pll1Settings->nDivider = pll1Ndiv; //This init function always runs PLL1 at 30.72MHz Pfd rate
+//    device->pll1Settings->refA_bufferCtrl = DIFFERENTIAL;       //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
+//    device->pll1Settings->refA_Divider = refAdiv;
+//    device->pll1Settings->refA_Frequency_Hz = refAFrequency_Hz;
+//    device->pll1Settings->refB_bufferCtrl = DISABLED;           //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
+//    device->pll1Settings->refB_Divider = 1;
+//    device->pll1Settings->refB_Frequency_Hz = 0;
+//    device->pll1Settings->vcxoBufferCtrl  = NEG_SINGLE_ENDED;   //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
+//    device->pll1Settings->vcxo_Frequency_Hz = vcxoFrequency_Hz;
+//
+//    /*******************************************************************
+//     * PLL2 Settings
+//     *******************************************************************
+//     */
+//
+//    /*******************************************************************
+//     * Output Distribution Settings
+//     * 9369CE02A uses the following clock outputs
+//     * OUT 1: FPGA REFCLK
+//     * OUT 3: FPGA SYSREF
+//     * OUT 12: DUT SYSREF
+//     * OUT 13: DUT REFCLK
+//     *******************************************************************
+//     */
+//
+//    /* PLL 2 input clock can be several different things.  Currently hard coded by this init funciton to use
+//     * PLL 1 output (VCXO Frequency) with no scaling
+//     */
+//    pll2InputFreq_Hz = device->pll1Settings->vcxo_Frequency_Hz;
+//    validPll2DivSetting = 0;
+//
+//    /* Sweep PLL2 Divider settings to find something that has a valid integer divide (3,4,5)*/
+//    for (pll2RfDiv = 3; pll2RfDiv <= 5; pll2RfDiv++)
+//    {
+//
+//        pll2NdivStart = (PLL2_MIN_VCO_FREQ_HZ / pll2RfDiv / pll2InputFreq_Hz);
+//        /* find valid PLL2 Ndiv (1-256) */
+//        for (pll2Ndiv = pll2NdivStart; pll2Ndiv <= 256; pll2Ndiv++)
+//        {
+//            pll2VcoFreq_Hz = (pll2InputFreq_Hz * pll2RfDiv * pll2Ndiv);
+//
+//            if (pll2VcoFreq_Hz < PLL2_MIN_VCO_FREQ_HZ)
+//            {
+//                /* Continue to next PLL2 N div */
+//                continue;
+//            }
+//            else if (pll2VcoFreq_Hz > PLL2_MAX_VCO_FREQ_HZ)
+//            {
+//                /* Break to next PLL2 RF div */
+//                break;
+//            }
+//
+//            if (((pll2VcoFreq_Hz / pll2RfDiv) % outputDeviceClock_Hz) == 0)
+//            {
+//
+//                device->pll2Settings->rfDivider = pll2RfDiv;
+//                device->pll2Settings->n2Divider = pll2Ndiv;
+//                device->pll2Settings->totalNdiv = pll2RfDiv * pll2Ndiv;
+//                chDivU64 = ((pll2VcoFreq_Hz / pll2RfDiv) / outputDeviceClock_Hz);
+//
+//                if ((chDivU64 < 1) || (chDivU64 > 256))
+//                {
+//                    return ADIERR_INV_PARM;
+//                }
+//                else
+//                {
+//                    chDiv = (uint16_t)(chDivU64);
+//                }
+//
+//                validPll2DivSetting = 1;
+//                break;
+//            }
+//        }
+//
+//        if (validPll2DivSetting == 1)
+//        {
+//            break;
+//        }
+//    }
+//
+//    if (validPll2DivSetting == 0)
+//    {
+//        return ADIERR_INV_PARM;
+//    }
+//
+//    device->outputSettings->outPowerDown = (uint16_t)(~0x300A);     //enable outputs 13,12,3 and 1
+//
+//    for (i=0; i<14; i++){
+//        device->outputSettings->outSource[i] = CHANNEL_DIV; //CHANNEL_DIV , PLL1_OUTPUT, SYSREF, INV_PLL1_OUTPUT
+//        device->outputSettings->outBufferCtrl[i] = LVDS;        //LVDS, LVDS_BOOST, HSTL
+//        device->outputSettings->outChannelDiv[i] = chDiv;
+//        device->outputSettings->outFrequency_Hz[i] = outputDeviceClock_Hz;
+//        device->outputSettings->outAnalogDelay[i] = 0;
+//        device->outputSettings->outDigitalDelay[i] = 0;
+//    }
+//
+//
+//    device->outputSettings->outSource[3] = SYSREF;
+//    device->outputSettings->outSource[12] = SYSREF;
+//
+//
+//    device->sysrefSettings->sysrefDivide = 512; //SYSREF frequency = VCXO / 2 / sysrefDivde
+//    device->sysrefSettings->sysrefNshotMode = ONE_PULSE;        //ONE_PULSE=0, TWO_PULSES=2, FOUR_PULSES=3, SIX_PULSES=4, EIGHT_PULSES=5
+//    device->sysrefSettings->sysrefPatternMode = NSHOT;          //NSHOT=0, CONTINUOUS=1, PRBS=2, STOP=3
+//    device->sysrefSettings->sysrefPinBufferMode = DISABLED;     //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
+//    device->sysrefSettings->sysrefPinEdgeMode = LEVEL_ACTIVE_HIGH;  //LEVEL_ACTIVE_HIGH=0, LEVEL_ACTIVE_LOW=1, RISING_EDGE=2, FALLING_EDGE=3
+//    device->sysrefSettings->sysrefRequestMethod = SPI;          //SPI=0,PIN=1
+//    device->sysrefSettings->sysrefSource = INTERNAL;            //EXTERNAL=0, EXT_RESAMPLED=1, INTERNAL=2
+    return ADIERR_OK;
+}
+
+/**
+ * \brief Debug function to print out summary of AD9528 setup
+ *
+ * \param device AD9528 Device data structure describing setup of device.
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+***********************************************************************************/
+ADI_ERR AD9528_reportClockRates(ad9528Device_t *device)
+{
+
+    return ADIERR_OK;
+} //debug function to help verify data structure is setup correctly.
+
+/**
+ * \brief Initializes the AD9528 by writing all SPI registers
+ *
+ * Initializes the AD9528 for use with the AD9369 transceiver.  Designed to work with
+ * a reference clock of 122.88MHz.  Reference clock is expected to be 30.72MHz.
+ * The output clocks from the AD9528 can run at 122.88M, 153.6M, 184.32M, 245.76M, or 307.2M.
+ * Typical setup: REFA frequency = 30.72, VCXO = 122.88MHz
+ * SYNC(SYSREF) pulses output at rate of 120kHz
+ *
+ * <B>Dependencies</B>
+ * - All parameters in device structure
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ */
+ADI_ERR AD9528_initialize(ad9528Device_t *device) { //writes all registers to desired values, leaves clock outputs off, SYSREF output disabled.
+    uint8_t pll2_Adiv=0;
+    uint8_t pll2_Bdiv=0;
+    uint8_t reg108=0;
+    uint8_t reg109=0;
+    uint8_t i = 0;
+    uint8_t j = 0;
+    uint8_t reg508;
+    ADI_ERR retval = ADIERR_OK;
+
+    CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, ADIERR_OK, "\n// AD9528_initialize\n");
+
+    //CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_A, 0x18); //[4] and [3] =1 enable 4 wire SPI
+    //CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x00);
+    retval = AD9528_setSpiSettings(device);
+    if (retval != ADIERR_OK)
+    {
+        return retval;
+    }
+
+    /**********************************************************************
+     * Configure PLL1
+     **********************************************************************
+     */
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_A_DIVIDER_LSB,
+    		device->pll1Settings->refA_Divider & 0xFF);		//REF A div[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_A_DIVIDER_MSB,
+    		(device->pll1Settings->refA_Divider >> 8) & 0x03); //REF A div[9:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_B_DIVIDER_LSB,
+    		device->pll1Settings->refB_Divider & 0xFF);		//REF B div[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_B_DIVIDER_MSB,
+    		(device->pll1Settings->refB_Divider >> 8) & 0x03); //REF B div[9:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_N_DIV_LSB,
+    		device->pll1Settings->nDivider & 0xFF); //PLL1 N div[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_N_DIV_MSB,
+    		(device->pll1Settings->nDivider >> 8) & 0x03); //PLL1 N div[9:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_CHARGEPUMP,
+    		0x0A); //PLL1 Charge Pump control 1
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_CP_CTRL2,
+    		0x03); //PLL1 Charge Pump control 2
+
+    switch (device->pll1Settings->refA_bufferCtrl){
+        case DISABLED:
+        	reg108 &= ~0x28;
+        	reg109 &= ~0x01;
+        	break; //clear all REFA enable bits
+        case SINGLE_ENDED:
+        	reg108 |=  0x08;
+        	reg109 &= ~0x01;
+        	break; //Set REFA receiver enable, clear REFA SE negative input enable
+        case NEG_SINGLE_ENDED:
+        	reg108 |=  0x08;
+        	reg108 &= ~0x10;
+        	reg109 |= 0x01;
+        	break; //Disable REFA diff receiver, enable REFA receiver and use negative REFA input
+        case DIFFERENTIAL:
+        	reg108 |=  0x28;
+        	reg109 &= ~0x01;
+        	break;
+        default:
+        	reg108 |=  0x08;
+        	reg109 &= ~0x01;
+        	break; //default to single ended case
+    }
+    switch (device->pll1Settings->refB_bufferCtrl){
+        case DISABLED:
+        	reg108 &= ~0x50;
+        	reg109 &= ~0x02;
+        	break; //clear all REFB enable bits
+        case SINGLE_ENDED:
+        	reg108 |=  0x10;
+        	reg109 &= ~0x02;
+        	break; //Set REFB receiver enable, clear REFB SE negative input enable
+        case NEG_SINGLE_ENDED:
+        	reg108 |=  0x10;
+        	reg108 &= ~0x40;
+        	reg109 |= 0x02;
+        	break; //Disable REFB diff receiver, enable REFB receiver and use negative REFB input
+        case DIFFERENTIAL:
+        	reg108 |=  0x50;
+        	reg109 &= ~0x02;
+        	break;
+        default:
+        	reg108 |=  0x10;
+        	reg109 &= ~0x02;
+        	break; //default to single ended case
+    }
+    switch (device->pll1Settings->vcxoBufferCtrl){
+        case DISABLED:
+        	reg108 &= ~0x03;
+        	reg108 |=  0x04;
+        	break; //power down VCXO input
+        case SINGLE_ENDED:
+        	reg108 &= ~0x07;
+        	break; //Clear VCXO receiver power down, defaults to Single ended mode
+        case NEG_SINGLE_ENDED:
+        	reg108 &= ~0x07;
+        	reg108 |=  0x02;
+        	break; //Clear VCXO power down, enable Negative single ended mode[1]
+        case DIFFERENTIAL:
+        	reg108 &= ~0x07;
+        	reg108 |=  0x01;
+        	break; //Clear VCXO power down, enable differential input buffer[0]
+        default:
+        	reg108 &= ~0x07;
+        	break; //default to positive single ended case
+    }
+
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS1,
+    		reg108); //Input receiver settings (single ended or differential clock inputs)
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS2,
+    		reg109); //Input receiver settings
+
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS3,
+    		0x0A); //Reference selection mode
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_FASTLOCK,
+    		0x00); //Disable Fast lock
+
+    /**********************************************************************
+     * Configure PLL2
+     **********************************************************************
+     */
+    pll2_Bdiv = device->pll2Settings->totalNdiv / 4;
+    pll2_Adiv = device->pll2Settings->totalNdiv % 4;
+
+    if (pll2_Adiv > 3) {  //A div valid range (0 to 3)
+        CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 A Divider out of range (0 to 3)\n");
+        return ADIERR_INV_PARM;
+    }
+    if (pll2_Bdiv < 3 || pll2_Bdiv > 63) {
+        CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 B Divider out of range (3 to 63)\n");
+        return ADIERR_INV_PARM;
+    }
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_CHARGEPUMP,
+    		0xE6); //PLL2 Charge Pump[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_N_DIV,
+    		((pll2_Adiv & 0x3) << 6) | (pll2_Bdiv & 0x3F)); //PLL2 A and B divider
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_CTRL, 0x03); //PLL2 control
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_VCO_CTRL, 0x01); //Manual VCO CAL
+
+    if (device->pll2Settings->rfDivider < 3 || device->pll2Settings->rfDivider > 5) {
+        CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 RF Divider out of range (3,4, or 5)\n");
+        return ADIERR_INV_PARM;
+    }
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_VCO_DIV,
+    		device->pll2Settings->rfDivider); //VCO divider
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_LF_CTRL1,
+    		0x3A); //PLL2 Loop filter [7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_LF_CTRL2,
+    		0x00); //PLL2 Loop filter [8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_RDIV,
+    		0x00); //R divider
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_REPLICA_CHDIV,
+    		(device->pll2Settings->totalNdiv / device->pll2Settings->rfDivider)
+			-1 ); //Replica channel divider: Ndivider = rfDivider * R divider
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_REPLICA_DIV_PHASE,
+    		0x00); //Replica Channel Divider phase
+
+    /**********************************************************************
+     * Configure Output Distribution
+     **********************************************************************
+     */
+    for (i=0; i<14; i=i+1){
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CTRL1 + j,
+        		((device->outputSettings->outSource[i] & 0x7) << 5) |
+				(device->outputSettings->outAnalogDelay[i] & 0x1F));
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CTRL2 + j,
+        		((device->outputSettings->outBufferCtrl[i] & 0x3) << 6) |
+				(device->outputSettings->outDigitalDelay[i] & 0x3F));
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CHDIV + j,
+        		device->outputSettings->outChannelDiv[i]-1);
+        j = j+3;
+    }
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_OUTPUT_SYNC, 0x00); //Sync outputs
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_MASK_SYNC1, 0x00); //Mask SYNC[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_MASK_SYNC2, 0x00); //Mask SYNC[13:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_EN_OUTPUT_PATH_SEL1,
+    		0x00); //Bypass SYSREF resample [6:0], bit0:Enable VCXO to feed output distrubution
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_EN_OUTPUT_PATH_SEL2,
+    		0x00); //Bypass SYSREF resample [13:7]
+
+    /**********************************************************************
+     * Configure SYSREF operation
+     **********************************************************************
+     */
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSERF_DIV_LSB,
+    		device->sysrefSettings->sysrefDivide & 0xFF); //SYSREF divider [7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSERF_DIV_MSB,
+    		(device->sysrefSettings->sysrefDivide >> 8) & 0xFF); //SYSREF divider [7:0]
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL3,
+    		((device->sysrefSettings->sysrefRequestMethod & 0x1) << 7) |
+    		((device->sysrefSettings->sysrefPinEdgeMode & 0x3) << 5) );
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4,
+    		((device->sysrefSettings->sysrefSource & 0x03) << 6) |
+    		((device->sysrefSettings->sysrefPatternMode & 0x3) << 4 ) |
+    		((device->sysrefSettings->sysrefNshotMode & 0x7) << 1) );
+
+    if(device->sysrefSettings->sysrefPinBufferMode == DISABLED)
+    {
+    	CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
+    			0x04); //power down input buffer for external SYSREF
+    }
+    else if(device->sysrefSettings->sysrefPinBufferMode == SINGLE_ENDED)
+    {
+    	CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
+    			0x00); //enable positive singled ended input
+    }
+    else if(device->sysrefSettings->sysrefPinBufferMode == NEG_SINGLE_ENDED)
+    {
+    	CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
+    			0x02); //enable negative singled ended input
+    }
+    else if(device->sysrefSettings->sysrefPinBufferMode == DIFFERENTIAL)
+    {
+    	CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
+    			0x01); //enable differential input buffer
+    }
+    else
+    {
+    	CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
+    			0x04); //power down input buffer for external SYSREF
+    }
+
+    /**********************************************************************
+     * Power down control
+     **********************************************************************
+     */
+
+    if (device->pll1Settings->bypassPll1 > 0)
+    {
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_POWERDOWN_CTRL,
+        		0x14);// power up PLL2 and output distribution, power down PLL1
+    }
+    else
+    {
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_POWERDOWN_CTRL,
+        		0x10);// power up PLL1, PLL2 and output distribution
+    }
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN1,
+    		device->outputSettings->outPowerDown & 0xFF); //power down out[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN2,
+    		((device->outputSettings->outPowerDown >> 8) & 0x3F)); //power down out[13:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_LDO_ENABLES1,
+    		0xFF); //LDO enable per output channel [7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_LDO_ENABLES2,
+    		0xFF); //LDO enable per output channel [15:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS0_CTRL,
+    		0x07); //STATUS 0 outputs REFA present
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS1_CTRL,
+    		0x01); //STATUS 1 outputs PLL1 and PLL2 locked
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS_OE,
+    		0x0C);// Make Status0 and Status1 outputs after reset.
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE,
+    		0x01); //IO update to make all these settings valid in the 9528
+
+    CMB_setTimeout_ms(1000);
+     do{
+         CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
+         if(CMB_hasTimeoutExpired() > 0)
+         {
+             return ADIERR_FAILED;
+         }
+     }while((reg508 & 0xA2) != 0xA2);
+
+    return ADIERR_OK;
+}
+
+/// Send a SPI message to request a SYSREF pulse or continuous SYSREF from the AD9528.
+/*******************************************************************************//**
+ * Requests a SYSREF from the AD9528.  It will use whatever settings for SYSREF
+ * that are current configured in the AD9528.  This could be a single pulse,
+ * multiple pulses, or continuous pulses.
+ * <B>Dependencies</B>
+ * - device->spiSettings
+ * - device->sysrefSettings->sysrefPatternMode
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ * \param enableSYSREF If NSHOT SYSREF mode, this parameter is ignored.  If PRBS/CONTINUOUS SYSREF mode, 1= enable SYSREF, 0= disable SYSREF.
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ ***********************************************************************************/
+ADI_ERR AD9528_requestSysref(ad9528Device_t *device, uint8_t enableSYSREF){
+    uint8_t _enableSYSREF=0;
+
+    if (device->sysrefSettings->sysrefPatternMode == NSHOT || enableSYSREF > 0)
+    {
+        _enableSYSREF = 1;
+    }
+    else
+    {
+        _enableSYSREF = 0;
+    }
+
+    CMB_SPIWriteField(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, _enableSYSREF, 0x01, 0x00); //Set SPI SYSREF request bit
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528
+
+    return ADIERR_OK;
+}
+
+/// Allow changing the 9528 SYSREF frequency and pattern mode(CONTINUOUS, PRBS vs NSHOT mode)
+/*******************************************************************************//**
+ * NOTE: this function will update the device structure with the parameter values passed
+ * into this function. The device->sysrefSettings->sysrefPatternMode, device->sysrefSettings->sysrefNshotMode,
+ * and device->sysrefSettings->sysrefDivide values will be updated in the device structure.
+ *
+ * <B>Dependencies</B>
+ * - device->spiSettings
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ * \param divideFromPll1Out Sets the SYSREF pulse frequency. SYSREF frequency = PLL1_VCXO frequency/divideFromPll1Out
+ * \param sysrefPatternMode Valid settings: NSHOT, CONTINUOUS, PRBS, STOP
+ * \param nShotPulses Valid settings: ONE_PULSE=0, TWO_PULSES=2, FOUR_PULSES=3, SIX_PULSES=4, EIGHT_PULSES=5
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ ***********************************************************************************/
+ADI_ERR AD9528_setupSYSREF(ad9528Device_t *device, uint16_t divideFromPll1Out,  sysrefPatternMode_t sysrefPatternMode, sysrefNshotMode_t nShotPulses)
+{
+    uint8_t reg403=0;
+
+    device->sysrefSettings->sysrefPatternMode = sysrefPatternMode;
+    device->sysrefSettings->sysrefNshotMode = nShotPulses;
+    device->sysrefSettings->sysrefDivide = divideFromPll1Out >> 1;  //SYSREF frequency is (PLL1)VCXO frequency / 2 / device->sysrefSettings->sysrefDivide
+
+    CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, &reg403);
+
+    reg403 = reg403 & ~0x01; //clear bit 0 to stop a continuous sysref if it is on.
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, reg403);
+
+    reg403 = reg403 & ~0x3E; //clear bits for pattern mode and Nshot mode bitfields
+    reg403 = reg403 | ((sysrefPatternMode & 0x3) << 4) | ((nShotPulses & 0x7) << 1);
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, reg403); //update internal sysref pattern mode and Nshot mode (number of pulses)
+
+    //SYSREF request bit x403[0] is left 0.  The next call to AD9528_requestSysref will start the SYSREF
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528
+
+
+    return ADIERR_OK;
+}
+
+/// Update the AD9528 clock outputs that are enabled.
+/*******************************************************************************//**
+ * NOTE: this function will update the device structure with the parameter values passed
+ * into this function. The device->sysrefSettings->sysrefPatternMode, device->sysrefSettings->sysrefNshotMode,
+ * and device->sysrefSettings->sysrefDivide values will be updated in the device structure.
+ *
+ * <B>Dependencies</B>
+ * - device->spiSettings
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ * \param clkEnable Sets which clock outputs are enabled. Bit per clock output. bit0 = out0, etc.
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ ***********************************************************************************/
+ADI_ERR AD9528_enableClockOutputs(ad9528Device_t *device, uint16_t clkEnable)
+{ //clkEnable: bit per clock output
+
+    device->outputSettings->outPowerDown = ~clkEnable;
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN1, device->outputSettings->outPowerDown & 0xFF); //power down out[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN2, ((device->outputSettings->outPowerDown >> 8) & 0x3F)); //power down out[13:8]
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528
+    return ADIERR_OK;
+}
+
+/// Waits for PLL1 and PLL2 to lock and the REFA and VCXO clocks to be present
+/*******************************************************************************//**
+ * Waits until Reference A clock and VCXO clock input to be detected (present),
+ * and PLL1 and PLL2 to lock.  Will timeout after 1 second and return ADIERR_FAILED.
+ * If clock are detected and PLLs locked, returns ADIERR_OK.
+ *
+ * <B>Dependencies</B>
+ * - device->spiSettings
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ ***********************************************************************************/
+ADI_ERR AD9528_waitForPllLock(ad9528Device_t *device)
+{
+    uint8_t reg508;
+
+    CMB_setTimeout_ms(1000);
+    do{
+        CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
+        if(CMB_hasTimeoutExpired() > 0)
+        {
+            return ADIERR_FAILED;
+        }
+    }while((reg508 & 0x27) != 0x27);
+
+    return ADIERR_OK;
+}
+
+/// Reads the Lock Status of the PLLs and present detect of the reference clocks
+/*******************************************************************************//**
+ * NOTE: This is a non blocking function that reads a register to see if PLL1
+ * and PLL2 are locked and Reference clock A and the VCXO input clock are
+ * detected (present). If the *status parameter is not NULL, the status will
+ * be returned.  If *status is NULL, the error return value will denote if
+ * the PllStatus is locked or not with ADIERR_OK or ADIERR_FAILED.
+ *
+ * <B>Dependencies</B>
+ * - device->spiSettings
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ ***********************************************************************************/
+ADI_ERR AD9528_readPllStatus(ad9528Device_t *device, uint8_t *status)
+{
+    uint8_t reg508;
+
+    //bit5 is VCXO clock detected
+    //bit2 is REFCLK A detected
+    //bit1 is PLL2 lock detect
+    //bit0 is PLL1 lock detect
+
+    /* read twice to refresh status bits */
+    CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
+    CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
+    /* if status is a valid pointer, return the PLL status */
+    if (status > 0)
+    {
+        *status = reg508;
+    }
+
+    /* PLLs 1 and 2 are locked and VCXO and REFA detected if reg508 has bits 5,2,1 and 0 set */
+    if((reg508 & 0x27) == 0x27)
+        return ADIERR_OK;
+    else
+        return ADIERR_FAILED;
+}

datalink814_ge/src/hardware/mykonos/ad9528.h

@@ -0,0 +1,44 @@
+/**
+ * \file ad9528.h
+ * \brief Contains function declarations and ad9528Device_t structure typedef for ad9528.c
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef _AD9528_LIB_H_
+#define _AD9528_LIB_H_
+
+#include <stdint.h>
+#include "../common.h"
+#include "t_ad9528.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CLEMENTE_TDD_AD9528_CLKOUT_INDEX 13
+
+//Helper function to setup the 9528 device data structure specifically for the ADI transceiver evaluation cards
+ADI_ERR AD9528_initDeviceDataStruct(ad9528Device_t *device, uint32_t vcxoFrequency_Hz, uint32_t refAFrequency_Hz, uint32_t outputDeviceClock_Hz);
+ADI_ERR AD9528_reportClockRates(ad9528Device_t *device); //debug function to help verify data structure is setup correctly.
+
+//AD9528 API functions
+ADI_ERR AD9528_resetDevice(ad9528Device_t *device);
+ADI_ERR AD9528_setSpiSettings(ad9528Device_t *device);
+ADI_ERR AD9528_initialize(ad9528Device_t *device); //writes all registers to desired values, leaves clock outputs off.
+ADI_ERR AD9528_waitForPllLock(ad9528Device_t *device);
+ADI_ERR AD9528_readPllStatus(ad9528Device_t *device, uint8_t *status);
+ADI_ERR AD9528_enableClockOutputs(ad9528Device_t *device, uint16_t clkEnable); //clkEnable: bit per clock output
+ADI_ERR AD9528_setupSYSREF(ad9528Device_t *device, uint16_t divideFromPll1Out,  sysrefPatternMode_t sysrefPatternMode, sysrefNshotMode_t nShotPulses);
+ADI_ERR AD9528_requestSysref(ad9528Device_t *device, uint8_t enableSYSREF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

datalink814_ge/src/hardware/mykonos/mykonos.h

@@ -0,0 +1,277 @@
+/*!
+ * \file mykonos.h
+ * \brief Contains macro definitions and function prototypes for mykonos.c
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef _MYKONOS_LIB_H_
+#define _MYKONOS_LIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "t_mykonos.h"
+#include "mykonos_version.h"
+
+#define TX_PROFILE_VALID    0x01
+#define RX_PROFILE_VALID    0x02
+#define ORX_PROFILE_VALID   0x04
+#define SNIFF_PROFILE_VALID 0x08
+
+/* 
+ ****************************************************************************
+ * General Initialization functions 
+ ****************************************************************************
+ */
+mykonosErr_t MYKONOS_resetDevice(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getDeviceRev(mykonosDevice_t *device, uint8_t *revision);
+mykonosErr_t MYKONOS_getProductId(mykonosDevice_t *device, uint8_t *productId);
+mykonosErr_t MYKONOS_setSpiSettings(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_verifyDeviceDataStructure(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_verifyProfiles(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_initialize(mykonosDevice_t *device); 
+mykonosErr_t MYKONOS_waitForEvent(mykonosDevice_t *device, waitEvent_t waitEvent, uint32_t timeout_us);
+mykonosErr_t MYKONOS_readEventStatus(mykonosDevice_t *device, waitEvent_t waitEvent, uint8_t *eventDone);
+mykonosErr_t MYKONOS_getApiVersion (mykonosDevice_t *device, uint32_t *siVer, uint32_t *majorVer, uint32_t *minorVer, uint32_t *buildVer);
+
+/*
+ *****************************************************************************
+ * PLL / Synthesizer functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_initDigitalClocks(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setRfPllFrequency(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint64_t rfPllLoFrequency_Hz);
+mykonosErr_t MYKONOS_getRfPllFrequency(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint64_t *rfPllLoFrequency_Hz);
+mykonosErr_t MYKONOS_checkPllsLockStatus(mykonosDevice_t *device, uint8_t *pllLockStatus);
+mykonosErr_t MYKONOS_setRfPllLoopFilter(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint16_t loopBandwidth_kHz, uint8_t stability);
+mykonosErr_t MYKONOS_getRfPllLoopFilter(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint16_t *loopBandwidth_kHz, uint8_t *stability);
+/*
+ *****************************************************************************
+ * ARM Processor Control Functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_initArm(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_loadArmFromBinary(mykonosDevice_t *device, uint8_t *binary, uint32_t count);
+mykonosErr_t MYKONOS_loadArmConcurrent(mykonosDevice_t *device, uint8_t *binary, uint32_t count);
+mykonosErr_t MYKONOS_verifyArmChecksum(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_checkArmState(mykonosDevice_t *device, mykonosArmState_t armStateCheck);
+mykonosErr_t MYKONOS_getArmVersion(mykonosDevice_t *device, uint8_t *majorVer, uint8_t *minorVer, uint8_t *rcVer, mykonosBuild_t *buildType);
+
+mykonosErr_t MYKONOS_configDpd(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getDpdConfig(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getDpdStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdStatus_t *dpdStatus);
+mykonosErr_t MYKONOS_restoreDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes);
+mykonosErr_t MYKONOS_saveDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes);
+mykonosErr_t MYKONOS_setDpdActState(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t actState);
+mykonosErr_t MYKONOS_resetDpd(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdResetMode_t reset);
+mykonosErr_t MYKONOS_setDpdBypassConfig(mykonosDevice_t *device, mykonosDpdBypassConfig_t *actConfig);
+mykonosErr_t MYKONOS_getDpdBypassConfig(mykonosDevice_t *device, mykonosDpdBypassConfig_t *actConfig);
+mykonosErr_t MYKONOS_setDpdActuatorCheck(mykonosDevice_t *device, mykonosDpdActuatorCheck_t *actCheck);
+mykonosErr_t MYKONOS_getDpdActuatorCheck(mykonosDevice_t *device, mykonosDpdActuatorCheck_t *actCheck);
+
+mykonosErr_t MYKONOS_setClgcAttenTuningConfig(mykonosDevice_t *device, mykonosClgcAttenTuningConfig_t *attRangeCfg);
+mykonosErr_t MYKONOS_getClgcAttenTuningConfig(mykonosDevice_t *device, mykonosClgcAttenTuningConfig_t *attRangeCfg);
+
+mykonosErr_t MYKONOS_configClgc(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getClgcConfig(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getClgcStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosClgcStatus_t *clgcStatus);
+mykonosErr_t MYKONOS_setClgcGain(mykonosDevice_t *device, mykonosTxChannels_t txChannel, int16_t gain);
+
+mykonosErr_t MYKONOS_configVswr(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getVswrConfig(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getVswrStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosVswrStatus_t *vswrStatus);
+
+mykonosErr_t MYKONOS_runInitCals(mykonosDevice_t *device, uint32_t calMask);
+mykonosErr_t MYKONOS_waitInitCals(mykonosDevice_t *device, uint32_t timeoutMs, uint8_t *errorFlag, uint8_t *errorCode);
+mykonosErr_t MYKONOS_abortInitCals(mykonosDevice_t *device, uint32_t *calsCompleted);
+mykonosErr_t MYKONOS_getInitCalStatus(mykonosDevice_t *device, mykonosInitCalStatus_t *initCalStatus);
+
+mykonosErr_t MYKONOS_resetExtTxLolChannel(mykonosDevice_t *device, mykonosTxChannels_t channelSel);
+
+mykonosErr_t MYKONOS_radioOn(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_radioOff(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getRadioState(mykonosDevice_t *device, uint32_t *radioStatus);
+mykonosErr_t MYKONOS_enableTrackingCals(mykonosDevice_t *device, uint32_t enableMask);
+mykonosErr_t MYKONOS_rescheduleTrackingCal(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal);
+mykonosErr_t MYKONOS_setAllTrackCalState(mykonosDevice_t *device, uint32_t trackingCalMask);
+mykonosErr_t MYKONOS_getAllTrackCalState(mykonosDevice_t *device, uint32_t *trackCals);
+mykonosErr_t MYKONOS_setTrackingCalState(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal, uint8_t trackCalState);
+mykonosErr_t MYKONOS_getTrackingCalState(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal, uint8_t *trackCalState);
+mykonosErr_t MYKONOS_getEnabledTrackingCals(mykonosDevice_t *device, uint32_t *enableMask);
+mykonosErr_t MYKONOS_getPendingTrackingCals(mykonosDevice_t *device, uint32_t *pendingCalMask);
+mykonosErr_t MYKONOS_getTxLolStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosTxLolStatus_t *txLolStatus);
+mykonosErr_t MYKONOS_getTxQecStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosTxQecStatus_t *txQecStatus);
+
+mykonosErr_t MYKONOS_getRxQecStatus(mykonosDevice_t *device, mykonosRxChannels_t rxChannel, mykonosRxQecStatus_t *rxQecStatus);
+mykonosErr_t MYKONOS_getOrxQecStatus(mykonosDevice_t *device, mykonosObsRxChannels_t orxChannel, mykonosOrxQecStatus_t *orxQecStatus);
+
+mykonosErr_t MYKONOS_setSnifferChannel(mykonosDevice_t *device, mykonosSnifferChannel_t snifferChannel);
+mykonosErr_t MYKONOS_setRadioControlPinMode(mykonosDevice_t *device);
+
+mykonosErr_t MYKONOS_setPathDelay(mykonosDevice_t *device, mykonosPathdelay_t *pathDelay);
+mykonosErr_t MYKONOS_getPathDelay(mykonosDevice_t *device, mykonosPathDelaySel_t select, mykonosPathdelay_t *pathDelay);
+
+mykonosErr_t MYKONOS_getDpdErrorCounters(mykonosDevice_t *device,  mykonosTxChannels_t txChannel, mykonosDpdErrorCounters_t *dpdErrCnt);
+
+/* Low level ARM functions */
+mykonosErr_t MYKONOS_readArmMem(mykonosDevice_t *device, uint32_t address, uint8_t *returnData, uint32_t bytesToRead, uint8_t autoIncrement);
+mykonosErr_t MYKONOS_writeArmMem(mykonosDevice_t *device, uint32_t address, uint8_t *data, uint32_t byteCount);
+mykonosErr_t MYKONOS_writeArmConfig(mykonosDevice_t *device, uint8_t objectId, uint16_t offset, uint8_t *data, uint8_t byteCount);
+mykonosErr_t MYKONOS_readArmConfig(mykonosDevice_t *device, uint8_t objectId, uint16_t offset, uint8_t *data, uint8_t byteCount);
+mykonosErr_t MYKONOS_sendArmCommand(mykonosDevice_t *device, uint8_t opCode,  uint8_t *extendedData, uint8_t extendedDataNumBytes);
+mykonosErr_t MYKONOS_readArmCmdStatus(mykonosDevice_t *device, uint16_t *errorWord, uint16_t *statusWord);
+mykonosErr_t MYKONOS_readArmCmdStatusByte(mykonosDevice_t *device, uint8_t opCode, uint8_t *cmdStatByte);
+mykonosErr_t MYKONOS_waitArmCmdStatus(mykonosDevice_t *device, uint8_t opCode, uint32_t timeoutMs, uint8_t *cmdStatByte);
+mykonosErr_t MYKONOS_writeArmProfile(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_loadAdcProfiles(mykonosDevice_t *device);
+
+
+/*
+ *****************************************************************************
+ * JESD204B Datapath Functions
+ *****************************************************************************
+ */
+/* Functions to setup the JESD204B IP */
+mykonosErr_t MYKONOS_resetDeframer(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setupSerializers(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setupDeserializers(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setupJesd204bFramer(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setupJesd204bObsRxFramer(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setupJesd204bDeframer(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_enableRxFramerLink(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_enableObsRxFramerLink(mykonosDevice_t *device, uint8_t enable);
+
+/* Functions to initialize the JESD204B link */
+mykonosErr_t MYKONOS_enableMultichipSync(mykonosDevice_t *device, uint8_t enableMcs, uint8_t *mcsStatus);
+mykonosErr_t MYKONOS_enableSysrefToRxFramer(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_enableSysrefToObsRxFramer(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_enableSysrefToDeframer(mykonosDevice_t *device, uint8_t enable);
+
+/* Functions to help debug the JESD204B link */
+mykonosErr_t MYKONOS_readRxFramerStatus(mykonosDevice_t *device, uint8_t *framerStatus);
+mykonosErr_t MYKONOS_readOrxFramerStatus(mykonosDevice_t *device, uint8_t *obsFramerStatus);
+mykonosErr_t MYKONOS_readDeframerStatus(mykonosDevice_t *device, uint8_t *deframerStatus);
+mykonosErr_t MYKONOS_getDeframerFifoDepth(mykonosDevice_t *device, uint8_t *fifoDepth, uint8_t *readEnLmfcCount);
+
+/* PRBS debug functions */
+mykonosErr_t MYKONOS_enableRxFramerPrbs(mykonosDevice_t *device, mykonosPrbsOrder_t polyOrder, uint8_t enable);
+mykonosErr_t MYKONOS_enableObsRxFramerPrbs(mykonosDevice_t *device, mykonosPrbsOrder_t polyOrder, uint8_t enable);
+mykonosErr_t MYKONOS_rxInjectPrbsError(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_obsRxInjectPrbsError(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_enableDeframerPrbsChecker(mykonosDevice_t *device, uint8_t lanes, mykonosPrbsOrder_t polyOrder, uint8_t enable);
+mykonosErr_t MYKONOS_clearDeframerPrbsCounters(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_readDeframerPrbsCounters(mykonosDevice_t *device, uint8_t counterSelect, uint32_t *prbsErrorCount);
+
+/* Miscellaneous debug functions */
+mykonosErr_t MYKONOS_jesd204bIlasCheck(mykonosDevice_t *device, uint16_t *mismatch);
+mykonosErr_t MYKONOS_setRxFramerDataSource(mykonosDevice_t *device, uint8_t dataSource);
+mykonosErr_t MYKONOS_setObsRxFramerDataSource(mykonosDevice_t *device, uint8_t dataSource);
+
+/*
+ *****************************************************************************
+ * Shared Data path functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_programFir(mykonosDevice_t *device, mykonosfirName_t filterToProgram, mykonosFir_t *firFilter);
+mykonosErr_t MYKONOS_readFir(mykonosDevice_t *device, mykonosfirName_t filterToRead, mykonosFir_t *firFilter);
+
+/*
+ *****************************************************************************
+ * Rx Data path functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_programRxGainTable(mykonosDevice_t *device, uint8_t *gainTablePtr, uint8_t numGainIndexesInTable, mykonosGainTable_t rxChannel);
+mykonosErr_t MYKONOS_setRx1ManualGain(mykonosDevice_t *device, uint8_t gainIndex);
+mykonosErr_t MYKONOS_setRx2ManualGain(mykonosDevice_t *device, uint8_t gainIndex);
+mykonosErr_t MYKONOS_getRx1Gain(mykonosDevice_t *device, uint8_t *rx1GainIndex);
+mykonosErr_t MYKONOS_getRx2Gain(mykonosDevice_t *device, uint8_t *rx2GainIndex);
+mykonosErr_t MYKONOS_setupRxAgc(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_resetRxAgc(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setRxAgcMinMaxGainIndex(mykonosDevice_t *device, mykonosRxChannels_t rxChannelSelect, uint8_t maxGainIndex, uint8_t minGainIndex);
+mykonosErr_t MYKONOS_setObsRxAgcMinMaxGainIndex(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxChannelSelect, uint8_t maxGainIndex, uint8_t minGainIndex);
+mykonosErr_t MYKONOS_setRx1TempGainComp(mykonosDevice_t *device, int16_t rx1TempCompGain_mdB);
+mykonosErr_t MYKONOS_getRx1TempGainComp(mykonosDevice_t *device, int16_t *rx1TempCompGain_mdB);
+mykonosErr_t MYKONOS_setRx2TempGainComp(mykonosDevice_t *device, int16_t rx2TempCompGain_mdB);
+mykonosErr_t MYKONOS_getRx2TempGainComp(mykonosDevice_t *device, int16_t *rx2TempCompGain_mdB);
+mykonosErr_t MYKONOS_setObsRxTempGainComp(mykonosDevice_t *device, int16_t obsRxTempCompGain_mdB);
+mykonosErr_t MYKONOS_getObsRxTempGainComp(mykonosDevice_t *device, int16_t *obsRxTempCompGain_mdB);
+mykonosErr_t MYKONOS_enableRxGainCtrSyncPulse(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_setRxGainControlMode(mykonosDevice_t *device, mykonosGainMode_t mode);
+mykonosErr_t MYKONOS_getRx1DecPower(mykonosDevice_t *device, uint16_t *rx1DecPower_mdBFS);
+mykonosErr_t MYKONOS_getRx2DecPower(mykonosDevice_t *device, uint16_t *rx2DecPower_mdBFS);
+
+/*
+ *****************************************************************************
+ * Observation Rx Data path functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_setDefaultObsRxPath(mykonosDevice_t *device,  mykonosObsRxChannels_t defaultObsRxCh);
+mykonosErr_t MYKONOS_setObsRxPathSource(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxCh);
+mykonosErr_t MYKONOS_getObsRxPathSource(mykonosDevice_t *device, mykonosObsRxChannels_t *obsRxCh);
+mykonosErr_t MYKONOS_setObsRxManualGain(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxCh, uint8_t gainIndex);
+mykonosErr_t MYKONOS_getObsRxGain(mykonosDevice_t *device, uint8_t *gainIndex);
+mykonosErr_t MYKONOS_setupObsRxAgc(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_enableObsRxGainCtrSyncPulse(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_setObsRxGainControlMode(mykonosDevice_t *device, mykonosGainMode_t mode);
+mykonosErr_t MYKONOS_getObsRxDecPower(mykonosDevice_t *device, uint16_t *obsRxDecPower_mdBFS);
+
+/*
+ *****************************************************************************
+ * Tx Data path functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_setTx1Attenuation(mykonosDevice_t *device, uint16_t tx1Attenuation_mdB);
+mykonosErr_t MYKONOS_setTx2Attenuation(mykonosDevice_t *device, uint16_t tx2Attenuation_mdB);
+mykonosErr_t MYKONOS_getTx1Attenuation(mykonosDevice_t *device, uint16_t *tx1Attenuation_mdB);
+mykonosErr_t MYKONOS_getTx2Attenuation(mykonosDevice_t *device, uint16_t *tx2Attenuation_mdB);
+mykonosErr_t MYKONOS_getTxFilterOverRangeStatus(mykonosDevice_t *device, uint8_t *txFilterStatus);
+mykonosErr_t MYKONOS_enableTxNco(mykonosDevice_t *device, uint8_t enable, int32_t tx1ToneFreq_kHz, int32_t tx2ToneFreq_kHz);
+
+/*
+ *****************************************************************************
+ * PA Protection Functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_setupPaProtection(mykonosDevice_t *device, uint16_t powerThreshold, uint8_t attenStepSize, uint8_t avgDuration, uint8_t stickyFlagEnable, uint8_t txAttenControlEnable);
+mykonosErr_t MYKONOS_enablePaProtection(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_getDacPower(mykonosDevice_t *device, mykonosTxChannels_t channel, uint16_t *channelPower);
+mykonosErr_t MYKONOS_getPaProtectErrorFlagStatus(mykonosDevice_t *device, uint8_t *errorFlagStatus);
+mykonosErr_t MYKONOS_clearPaErrorFlag(mykonosDevice_t *device);
+
+/*
+ *****************************************************************************
+ * Low level functions and helper functions. BBP should not need to call
+ *****************************************************************************
+ */
+const char* getMykonosErrorMessage(mykonosErr_t errorCode);
+
+mykonosErr_t MYKONOS_initSubRegisterTables(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setTxPfirSyncClk(mykonosDevice_t *device); /* Helper function */
+mykonosErr_t MYKONOS_setRxPfirSyncClk(mykonosDevice_t *device); /* Helper function */
+
+/*
+ *****************************************************************************
+ * Functions to configure DC offsets
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_setRfDcOffsetCnt(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint16_t measureCount);
+mykonosErr_t MYKONOS_getRfDcOffsetCnt(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint16_t *measureCount);
+mykonosErr_t MYKONOS_setDigDcOffsetMShift(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint8_t mShift);
+mykonosErr_t MYKONOS_getDigDcOffsetMShift(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint8_t *mShift);
+mykonosErr_t MYKONOS_setDigDcOffsetEn(mykonosDevice_t *device, uint8_t enableMask);
+mykonosErr_t MYKONOS_getDigDcOffsetEn(mykonosDevice_t *device, uint8_t *enableMask);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

datalink814_ge/src/hardware/mykonos/mykonosMmap.c

@@ -0,0 +1,136 @@
+/**
+ * \file mykonosMmap.c
+ * \brief Contains the Mykonos memory mapping
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#include <stdint.h>
+uint8_t mykonosMmap [] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x13,0x03,0x03,0x13,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+                                 0x00,0xE4,0xE4,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA5,0xA5,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x01,0x00,0xE4,0xE4,0x00,0x00,0x00,0x1F,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x9F,0xE0,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0xF5,0x8F,0x0F,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
+/*!< Mykonos memory map */

datalink814_ge/src/hardware/mykonos/mykonos_gpio.h

@@ -0,0 +1,172 @@
+/*!
+ * \file mykonos_gpio.h
+ * \brief Contains macro definitions and function prototypes for mykonos_gpio.c
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef MYKONOSGPIO_H_
+#define MYKONOSGPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "t_mykonos.h"
+#include "t_mykonos_gpio.h"
+
+/*
+ *****************************************************************************
+ * GPIO functions
+ *****************************************************************************
+ */
+
+/* GPIO CMOS and SPI setting Functions */
+mykonosGpioErr_t MYKONOS_setGpioDrv(mykonosDevice_t *device, uint32_t gpioDrv);
+mykonosGpioErr_t MYKONOS_getGpioDrv(mykonosDevice_t *device, uint32_t *gpioDrv);
+
+mykonosGpioErr_t MYKONOS_setGpioSlewRate(mykonosDevice_t *device, mykonosGpioSelect_t gpioSelect, mykonosGpioSlewRate_t slewRate);
+mykonosGpioErr_t MYKONOS_getGpioSlewRate(mykonosDevice_t *device, mykonosGpioSelect_t gpioSelect, mykonosGpioSlewRate_t *slewRate);
+
+mykonosGpioErr_t MYKONOS_setCmosDrv(mykonosDevice_t *device, mykonosCmosPadDrvStr_t spiDrv);
+mykonosGpioErr_t MYKONOS_getCmosDrv(mykonosDevice_t *device, mykonosCmosPadDrvStr_t *spiDrv);
+
+
+/* Monitor output Functions */
+mykonosGpioErr_t MYKONOS_setGpioMonitorOut(mykonosDevice_t *device, uint8_t monitorIndex, uint8_t monitorMask);
+mykonosGpioErr_t MYKONOS_getGpioMonitorOut(mykonosDevice_t *device, uint8_t *monitorIndex, uint8_t *monitorMask);
+
+/* RX GPIO Functions */
+mykonosGpioErr_t MYKONOS_setRx1GainCtrlPin(mykonosDevice_t *device, uint8_t incStep, uint8_t decStep, mykonosGpioSelect_t rx1GainIncPin, mykonosGpioSelect_t rx1GainDecPin, uint8_t enable);
+mykonosGpioErr_t MYKONOS_setRx2GainCtrlPin(mykonosDevice_t *device, uint8_t incStep, uint8_t decStep, mykonosGpioSelect_t rx2GainIncPin, mykonosGpioSelect_t rx2GainDecPin, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getRx1GainCtrlPin(mykonosDevice_t *device, uint8_t *incStep, uint8_t *decStep, mykonosGpioSelect_t *rx1GainIncPin, mykonosGpioSelect_t *rx1GainDecPin, uint8_t *enable);
+mykonosGpioErr_t MYKONOS_getRx2GainCtrlPin(mykonosDevice_t *device, uint8_t *incStep, uint8_t *decStep, mykonosGpioSelect_t *rx2GainIncPin, mykonosGpioSelect_t *rx2GainDecPin, uint8_t *enable);
+
+mykonosGpioErr_t MYKONOS_setRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t rx1GainChangePin, mykonosGpioSelect_t rx2GainChangePin);
+mykonosGpioErr_t MYKONOS_getRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t *rx1GainChangePin, mykonosGpioSelect_t *rx2GainChangePin);
+mykonosGpioErr_t MYKONOS_setObsRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t obsRxGainChangePin);
+mykonosGpioErr_t MYKONOS_getObsRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t *obsRxGainChangePin);
+
+mykonosGpioErr_t MYKONOS_setRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t rx1AgcSyncPin, mykonosGpioSelect_t rx2AgcSyncPin);
+mykonosGpioErr_t MYKONOS_getRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t *rx1AgcSyncPin, mykonosGpioSelect_t *rx2AgcSyncPin);
+mykonosGpioErr_t MYKONOS_setObsRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t obsRxAgcSyncPin);
+mykonosGpioErr_t MYKONOS_getObsRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t *obsRxAgcSyncPin);
+
+/* TX GPIO Functions */
+mykonosGpioErr_t MYKONOS_setTx1AttenCtrlPin(mykonosDevice_t *device, uint8_t stepSize, mykonosGpioSelect_t tx1AttenIncPin, mykonosGpioSelect_t tx1AttenDecPin, uint8_t enable, uint8_t useTx1ForTx2);
+mykonosGpioErr_t MYKONOS_setTx2AttenCtrlPin(mykonosDevice_t *device, uint8_t stepSize, mykonosGpioSelect_t tx2AttenIncPin, mykonosGpioSelect_t tx2AttenDecPin, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getTx1AttenCtrlPin(mykonosDevice_t *device, uint8_t *stepSize, mykonosGpioSelect_t *tx1AttenIncPin, mykonosGpioSelect_t *tx1AttenDecPin, uint8_t *enable, uint8_t *useTx1ForTx2);
+mykonosGpioErr_t MYKONOS_getTx2AttenCtrlPin(mykonosDevice_t *device, uint8_t *stepSize, mykonosGpioSelect_t *tx2AttenIncPin, mykonosGpioSelect_t *tx2AttenDecPin, uint8_t *enable, uint8_t *useTx1ForTx2);
+
+mykonosGpioErr_t MYKONOS_spi2GpioSetup(mykonosDevice_t *device, uint8_t enable, uint8_t updateTxAttenPinSelect);
+
+/* GPIO memory source Functions */
+mykonosGpioErr_t MYKONOS_setGpioPinLevel(mykonosDevice_t *device, uint32_t gpioPinLevel);
+mykonosGpioErr_t MYKONOS_getGpioPinLevel(mykonosDevice_t *device, uint32_t *gpioPinLevel);
+mykonosGpioErr_t MYKONOS_getGpioSetLevel(mykonosDevice_t *device, uint32_t *gpioPinSetLevel);
+
+/* Gain Compensation Functions */
+mykonosGpioErr_t MYKONOS_setRxGainCompensation (mykonosDevice_t *device, mykonosGainComp_t *gainComp, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getRxGainCompensation (mykonosDevice_t *device, mykonosGainComp_t *gainComp, uint8_t *enabled);
+
+mykonosGpioErr_t MYKONOS_setObsRxGainCompensation (mykonosDevice_t *device, mykonosObsRxGainComp_t *gainComp, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getObsRxGainCompensation (mykonosDevice_t *device, mykonosObsRxGainComp_t *gainComp, uint8_t *enabled);
+
+/* SLICER Functions */
+mykonosGpioErr_t MYKONOS_setRxSlicerCtrl(mykonosDevice_t *device, uint8_t slicerStep, mykonosRxSlicer_t rx1Pins, mykonosRxSlicer_t rx2Pins, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getRxSlicerCtrl(mykonosDevice_t *device, uint8_t *slicerStep, mykonosRxSlicer_t *rx1Pins, mykonosRxSlicer_t *rx2Pins, uint8_t *enable);
+
+mykonosGpioErr_t MYKONOS_setObsRxSlicerCtrl(mykonosDevice_t *device, uint8_t slicerStep, mykonosObsRxSlicer_t obsRxPins, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getObsRxSlicerCtrl(mykonosDevice_t *device, uint8_t *slicerStep, mykonosObsRxSlicer_t *obsRxPins, uint8_t *enable);
+
+/* Floating Point Formatter Functions */
+mykonosGpioErr_t MYKONOS_setFloatPointFrmt (mykonosDevice_t *device, mykonosFloatPntFrmt_t *floatFrmt);
+mykonosGpioErr_t MYKONOS_getFloatPointFrmt (mykonosDevice_t *device, mykonosFloatPntFrmt_t *floatFrmt);
+
+mykonosGpioErr_t MYKONOS_setRxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t rx1Att, uint8_t rx2Att, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getRxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t *rx1Att, uint8_t *rx2Att, uint8_t *enable);
+
+mykonosGpioErr_t MYKONOS_setOrxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t orxAtt, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getOrxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t *orxAtt, uint8_t *enable);
+
+/*
+ *****************************************************************************
+ * General Purpose Interrupt functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_configGpInterrupt(mykonosDevice_t *device, uint16_t gpMask);
+mykonosGpioErr_t MYKONOS_readGpInterruptStatus(mykonosDevice_t *device, uint16_t *status);
+
+/*
+ *****************************************************************************
+ * ARM GPIO usage functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_setArmGpioPins(mykonosDevice_t *device);
+
+/*
+ *****************************************************************************
+ * AuxADC/AuxDAC functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_setupAuxAdcs(mykonosDevice_t *device, uint8_t adcDecimation, uint8_t enable);
+mykonosGpioErr_t MYKONOS_setAuxAdcChannel(mykonosDevice_t *device, mykonosAuxAdcChannels_t auxAdcChannel);
+mykonosGpioErr_t MYKONOS_readAuxAdc(mykonosDevice_t *device, uint16_t *adcCode);
+mykonosGpioErr_t MYKONOS_setupAuxDacs(mykonosDevice_t *device);
+mykonosGpioErr_t MYKONOS_writeAuxDac(mykonosDevice_t *device, uint8_t auxDacIndex, uint16_t auxDacCode);
+
+/*
+ *****************************************************************************
+ * GPIO3v3 functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_setupGpio3v3(mykonosDevice_t *device);
+
+mykonosGpioErr_t MYKONOS_setGpio3v3PinLevel(mykonosDevice_t *device, uint16_t gpio3v3PinLevel);
+mykonosGpioErr_t MYKONOS_getGpio3v3SetLevel(mykonosDevice_t *device, uint16_t *gpio3v3SetLevel);
+
+mykonosGpioErr_t MYKONOS_getGpio3v3PinLevel(mykonosDevice_t *device, uint16_t *gpio3v3PinLevel);
+
+mykonosGpioErr_t MYKONOS_setGpio3v3Oe(mykonosDevice_t *device, uint16_t gpio3v3OutEn);
+mykonosGpioErr_t MYKONOS_getGpio3v3Oe(mykonosDevice_t *device, uint16_t *gpio3v3OutEn);
+
+mykonosGpioErr_t MYKONOS_setGpio3v3SourceCtrl(mykonosDevice_t *device, uint16_t gpio3v3SrcCtrl);
+mykonosGpioErr_t MYKONOS_getGpio3v3SourceCtrl(mykonosDevice_t *device, uint16_t *gpio3v3SrcCtrl);
+
+/*
+ *****************************************************************************
+ * GPIO helper functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_setupGpio(mykonosDevice_t *device);
+mykonosGpioErr_t MYKONOS_setGpioOe(mykonosDevice_t *device, uint32_t gpioOutEn, uint32_t gpioUsedMask);
+mykonosGpioErr_t MYKONOS_getGpioOe(mykonosDevice_t *device, uint32_t *gpioOutEn);
+
+mykonosGpioErr_t MYKONOS_setGpioSourceCtrl(mykonosDevice_t *device, uint32_t gpioSrcCtrl);
+mykonosGpioErr_t MYKONOS_getGpioSourceCtrl(mykonosDevice_t *device, uint32_t *gpioSrcCtrl);
+
+/*
+ *****************************************************************************
+ * Temperature Sensor functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_setupTempSensor(mykonosDevice_t *device, mykonosTempSensorConfig_t *tempSensor);
+mykonosGpioErr_t MYKONOS_getTempSensorConfig(mykonosDevice_t *device, mykonosTempSensorConfig_t *tempSensor);
+
+mykonosGpioErr_t MYKONOS_startTempMeasurement(mykonosDevice_t *device);
+mykonosGpioErr_t MYKONOS_readTempSensor(mykonosDevice_t *device, mykonosTempSensorStatus_t *tempStatus);
+
+const char* getGpioMykonosErrorMessage(mykonosGpioErr_t errorCode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MYKONOSGPIO_H_ */

datalink814_ge/src/hardware/mykonos/mykonos_macros.h

@@ -0,0 +1,707 @@
+/**
+ * \file mykonos_macros.h
+ * \brief Contains address and miscellaneous macro definitions for Mykonos API
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef CLEMENTE_TDD_MACROS_H
+#define CLEMENTE_TDD_MACROS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MYKONOS_ADDR_CONFIGURATION_CONTROL_0                0x000
+#define MYKONOS_ADDR_SPI_CONFIGURATION_CONTROL_1            0x001
+#define MYKONOS_ADDR_PRODUCT_ID                             0x004
+#define MYKONOS_GPIO_DRV_CTL_0                              0x020
+#define MYKONOS_GPIO_DRV_CTL_1                              0x021
+#define MYKONOS_GPIO_SLEW_CTL_0                             0x022
+#define MYKONOS_GPIO_SLEW_CTL_1                             0x023
+#define MYKONOS_GPIO_SLEW_CTL_2                             0x024
+#define MYKONOS_GPIO_SLEW_CTL_3                             0x025
+
+#define MYKONOS_ADDR_DIGITAL_IO_CONTROL                     0x028
+
+#define MYKONOS_ADDR_SYSREF_PAD_CONFIG                      0x040
+#define MYKONOS_ADDR_TX1_SYNC_PAD_CONFIG                    0x041
+#define MYKONOS_ADDR_TX2_SYNC_PAD_CONFIG                    0x042
+#define MYKONOS_ADDR_RX1_SYNC_CONFIG                        0x043
+#define MYKONOS_ADDR_RX2_SYNC_CONFIG                        0x044
+
+/* Mykonos Framer Registers */
+#define MYKONOS_ADDR_FRAMER_RESET                           0x059
+#define MYKONOS_ADDR_FRAMER_CLK_EN                          0x05A
+#define MYKONOS_ADDR_FRAMER_ADDR                            0x05B
+#define MYKONOS_ADDR_FRAMER_DATA                            0x05C
+#define MYKONOS_ADDR_FRAMER_WRITE_EN                        0x05D
+#define MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN                  0x05E
+#define MYKONOS_ADDR_FRAMER_CONFIG_F                        0x05F
+#define MYKONOS_ADDR_FRAMER_LANE_CTL                        0x060
+#define MYKONOS_ADDR_FRAMER_ADC_XBAR_SEL                    0x061
+#define MYKONOS_ADDR_FRAMER_LANE_XBAR_SEL                   0x062
+#define MYKONOS_ADDR_FRAMER_CONFIG_LOOPBACK_XBAR_REV        0x063
+#define MYKONOS_ADDR_FRAMER_SYNCN_FILT                      0x064
+#define MYKONOS_ADDR_FRAMER_LMFC_F_OFFSET                   0x065
+#define MYKONOS_ADDR_FRAMER_LMFC_K_OFFSET                   0x066
+#define MYKONOS_ADDR_FRAMER_TEST_CNTR_CTL                   0x067
+#define MYKONOS_ADDR_FRAMER_STATUS_STRB                     0x068
+#define MYKONOS_ADDR_FRAMER_STATUS                          0x069
+#define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_CNTR_STAT        0x06A
+#define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN       0x06B
+#define MYKONOS_ADDR_FRAMER_LANE_FIFO_STRB                  0x06C
+#define MYKONOS_ADDR_FRAMER_LANE0_FIFO_RDWR_ADDR            0x06D
+#define MYKONOS_ADDR_FRAMER_LANE1_FIFO_RDWR_ADDR            0x06E
+#define MYKONOS_ADDR_FRAMER_LANE2_FIFO_RDWR_ADDR            0x06F
+#define MYKONOS_ADDR_FRAMER_LANE3_FIFO_RDWR_ADDR            0x070
+#define MYKONOS_ADDR_FRAMER_PRBS10_CTL                      0x071
+#define MYKONOS_ADDR_FRAMER_PRBS20_CTL                      0x072
+#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_EN                  0x073
+#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_7_TO_0              0x074
+#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_15_TO_8             0x075
+#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_19_TO_16            0x076
+#define MYKONOS_ADDR_FRAMER_CONFIG_JTX_GEN                  0x077
+#define MYKONOS_ADDR_FRAMER_LANE_DATA_CTL                   0x078
+#define MYKONOS_ADDR_FRAMER_DATA_SAMPLE_CTL                 0x079
+
+/* Mykonos Deframer Sub Address Map */
+#define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_RECVD           0x00
+#define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_CFG             0x50
+
+/* Mykonos Deframer Registers */
+#define MYKONOS_ADDR_DEFRAMER_RESET                         0x07A
+#define MYKONOS_ADDR_DEFRAMER_CLK_EN                        0x07B
+#define MYKONOS_ADDR_DEFRAMER_ADDR                          0x07C
+#define MYKONOS_ADDR_DEFRAMER_DATA                          0x07D
+#define MYKONOS_ADDR_DEFRAMER_WR_EN                         0x07E
+#define MYKONOS_ADDR_DEFRAMER_SYSREF_FIFO_EN                0x07F
+#define MYKONOS_ADDR_DEFRAMER_CONFIG_F                      0x080
+#define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_CTL                 0x081
+#define MYKONOS_ADDR_DEFRAMER_DAC_XBAR_SEL                  0x082
+#define MYKONOS_ADDR_DEFRAMER_LANE_XBAR_SEL                 0x083
+#define MYKONOS_ADDR_DEFRAMER_LMFC_F_OFFSET                 0x084
+#define MYKONOS_ADDR_DEFRAMER_LMFC_K_OFFSET                 0x085
+#define MYKONOS_ADDR_DEFRAMER_CONFIG_SYNC_USER_DATA_CTL     0x086
+#define MYKONOS_ADDR_DEFRAMER_SYNC_REQ_RETIME               0x087
+#define MYKONOS_ADDR_DEFRAMER_TEST                          0x088
+#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_STRT_DAC_XBAR_REV 0x089
+#define MYKONOS_ADDR_DEFRAMER_STAT_STRB                     0x08A
+#define MYKONOS_ADDR_DEFRAMER_STAT                          0x08B
+#define MYKONOS_ADDR_DEFRAMER_TEST_ERR_CNT_STAT             0x08C
+#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_RD_ADDR              0x08D
+#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_ADDR              0x08E
+#define MYKONOS_ADDR_DEFRAMER_QBLMFC_VS_EXTLMFC_CNTR_STAT   0x08F
+#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_STAT                 0x090
+#define MYKONOS_ADDR_DEFRAMER_STRT_RD_DEL_STOP_WR           0x091
+#define MYKONOS_ADDR_DEFRAMER_FIFO_SAMPLE_SPI_ADDR_RD       0x092
+#define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_ADDR_RD         0x093
+#define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_DATA_RD         0x094
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE0_7_TO_0                0x095
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE0_15_TO_8               0x096
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE1_7_TO_0                0x097
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE1_15_TO_8               0x098
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE2_7_TO_0                0x099
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE2_15_TO_8               0x09A
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE3_7_TO_0                0x09B
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE3_15_TO_8               0x09C
+#define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_STRB                0x09D
+#define MYKONOS_ADDR_DEFRAMER_LANE0_FIFO_RDWR_ADDR          0x09E
+#define MYKONOS_ADDR_DEFRAMER_LANE1_FIFO_RDWR_ADDR          0x09F
+#define MYKONOS_ADDR_DEFRAMER_LANE2_FIFO_RDWR_ADDR          0x0A0
+#define MYKONOS_ADDR_DEFRAMER_LANE3_FIFO_RDWR_ADDR          0x0A1
+#define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_CNTR_STAT      0x0A2
+#define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_ERR_MARGIN     0x0A3
+#define MYKONOS_ADDR_DEFRAMER_PRBS10_CTL                    0x0A4
+#define MYKONOS_ADDR_DEFRAMER_PRBS20_CTL                    0x0A5
+#define MYKONOS_ADDR_DEFRAMER_PRBS20_STRB_CHKSUM_TYPE       0x0A6
+#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_7_TO_0        0x0A7
+#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_15_TO_8       0x0A8
+#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_23_TO_16      0x0A9
+#define MYKONOS_ADDR_DEFRAMER_LANE_DATA_CTL                 0x0AA
+#define MYKONOS_ADDR_DEFRAMER_STATUS_2                      0x0AB
+#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_PHASE                0x0AC
+
+/* Mykonos Serializer Registers */
+#define MYKONOS_ADDR_SERIALIZER_CTL_0                       0x0B0
+#define MYKONOS_ADDR_SERIALIZER_CTL_1                       0x0B1
+#define MYKONOS_ADDR_SERIALIZER_CTL_2                       0x0B2
+#define MYKONOS_ADDR_SERIALIZER_CTL_3                       0x0B3
+#define MYKONOS_ADDR_SERIALIZER_HS_DIV_TXSER_CLK_EN         0x0B4
+#define MYKONOS_ADDR_SERIALIZER_SPECIAL                     0x0B5
+
+/* Mykonos Deserializer Registers */
+#define MYKONOS_ADDR_DESERIALIZER_PDET_CTL                  0x0BC
+#define MYKONOS_ADDR_DESERIALIZER_CTL_0                     0x0BD
+#define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_0               0x0BE
+#define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_1               0x0BF
+#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_0                  0x0C1
+#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1                  0x0C2
+#define MYKONOS_ADDR_DESERIALIZER_MISC_CTL                  0x0C3
+#define MYKONOS_ADDR_DESERIALIZER_EQ_HP_EN                  0x0C4
+#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1_TO_0             0x0C5
+#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_3_TO_2             0x0C6
+#define MYKONOS_ADDR_DESERIALIZER_HS_DIV_RXCDR_CLK_EN       0x0CD
+#define MYKONOS_ADDR_DESERIALIZER_SPECIAL                   0x0CE
+#define MYKONOS_ADDR_DESERIALIZER_CDR_CAL_CTL               0x0D0
+
+#define MYKONOS_ADDR_CONFIGURATION_CONTROL_1                0x100
+#define MYKONOS_ADDR_CONFIGURATION_CONTROL_2                0x101
+#define MYKONOS_ADDR_CONFIGURATION_CONTROL_4                0x102
+#define MYKONOS_ADDR_CONFIGURATION_CONTROL_5                0x103
+#define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_1    0x104
+#define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_2    0x105
+#define MYKONOS_ADDR_DPD_SNIFFER_GPIO_SELECT                0x106
+#define MYKONOS_ADDR_SNIFFER_CONFIGURATION_CONTROL          0x107
+#define MYKONOS_ADDR_DPD_CONFIGURATION_CONTROL              0x108
+#define MYKONOS_ADDR_LOOPBACK_CONFIGURATION_CONTROL         0x109
+
+#define MYKONOS_ADDR_CLOCK_CONTROL_0						0x117
+#define MYKONOS_ADDR_CLOCK_CONTROL_1						0x118
+#define MYKONOS_ADDR_CLOCK_CONTROL_2						0x119
+#define MYKONOS_ADDR_CLOCK_CONTROL_3						0x11A
+#define MYKONOS_ADDR_CLOCK_CONTROL_4						0x11B
+#define MYKONOS_ADDR_CLOCK_CONTROL_5                        0x11C
+
+#define MYKONOS_ADDR_MCS_CONTROL                            0x120
+#define MYKONOS_ADDR_MCS_STATUS                             0x121
+
+/* CLK PLL Registers */
+#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE0            0x141
+#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE1            0x142
+#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE0           0x143
+#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE1           0x144
+#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE2           0x145
+#define MYKONOS_ADDR_CLK_SYNTH_F_VCOTN_BYTE1                0x148
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE1                        0x149
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE2                        0x14A
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE3                        0x14B
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE5                        0x14D
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE6                        0x14E
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE7                        0x14F
+#define MYKONOS_ADDR_CLK_SYNTH_LF_R3                        0x150
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE9                        0x152
+#define MYKONOS_ADDR_CLK_SYNTH_CAL_STAT                     0x154
+#define MYKONOS_ADDR_CLK_SYNTH_VCO_CAL_REF                  0x155
+#define MYKONOS_ADDR_CLK_SYNTH_VCO_BAND_BYTE1               0x157
+#define MYKONOS_ADDR_CLK_SYNTH_CAL_CONTROL                  0x159
+#define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL1                 0x15E
+#define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL2                 0x15F
+
+/* DPD Registers */
+#define MYKONOS_ADDR_TX1_DPD_MODEL_INDIRECT_PTR             0x178
+#define MYKONOS_ADDR_TX2_DPD_MODEL_INDIRECT_PTR             0x17C
+#define MYKONOS_ADDR_DPD_RMS_BUF_SIZE                       0x180
+#define MYKONOS_ADDR_TX1_DPD_MODEL_WORKING_PTR              0x188
+#define MYKONOS_ADDR_TX2_DPD_MODEL_WORKING_PTR              0x18C
+
+/* Rx NCO Control registers */
+#define MYKONOS_ADDR_CALPLL_SDM_CONTROL                     0x17F
+#define MYKONOS_ADDR_RX_NCO_CONTROL                         0x190
+#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_3                  0x191
+#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_2                  0x192
+#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_1                  0x193
+#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_3                  0x194
+#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_2                  0x195
+#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_1                  0x196
+#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_3          0x197
+#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_2          0x198
+#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_1          0x199
+
+#define MYKONOS_ADDR_ENSM_CONFIG_7_0                        0x1B0
+#define MYKONOS_ADDR_CALIBRATION_CONTROL                    0x1B2
+#define MYKONOS_ADDR_ENSM_MANUAL_GAIN_LOCK_GPIO_SELECT      0x1B5
+#define MYKONOS_ADDR_REFERENCE_CLOCK_CYCLES                 0x1C0
+#define MYKONOS_ADDR_TX_PD_OVERIDE_7_0                      0x209
+#define MYKONOS_ADDR_RCAL_CONTROL                           0x224
+#define MYKONOS_ADDR_REF_PAD_CONFIG1                        0x230
+#define MYKONOS_ADDR_REF_PAD_CONFIG2                        0x231
+
+#define MYKONOS_ADDR_RXSYNTH_CP_CAL_STAT                    0x254
+#define MYKONOS_ADDR_RXSYNTH_VCO_BAND_BYTE1                 0x257
+#define MYKONOS_ADDR_TXSYNTH_CP_CAL_STAT                    0x2C4
+#define MYKONOS_ADDR_TXSYNTH_VCO_BAND_BYTE1                 0x2C7
+#define MYKONOS_ADDR_SNIFF_RXSYNTH_CP_CAL_STAT              0x354
+#define MYKONOS_ADDR_SNIFF_RXSYNTH_VCO_BAND_BYTE1           0x357
+#define MYKONOS_ADDR_SNIFF_RXLOGEN_BYTE1                    0x380
+
+#define MYKONOS_ADDR_RX_FILTER_CONFIGURATION                0x410
+#define MYKONOS_ADDR_RX_FILTER_GAIN                         0x411
+#define MYKONOS_ADDR_DPD_SNIFFER_RX_FILTER_GAIN             0x412
+
+/* Mykonos Temperature Gain Compensation Registers */
+#define MYKONOS_ADDR_RX1_TEMP_GAIN_COMP                     0x420
+#define MYKONOS_ADDR_RX2_TEMP_GAIN_COMP                     0x421
+#define MYKONOS_ADDR_OBS_TEMP_GAIN_COMP                     0x422
+
+/* Mykonos AGC General Registers */
+#define MYKONOS_ADDR_AGC_CFG_1                              0x42E
+#define MYKONOS_ADDR_AGC_CFG_2                              0x42F
+#define MYKONOS_ADDR_AGC_GAIN_CHANGE_GPIO_SEL               0x430
+#define MYKONOS_ADDR_AGC_RX1_MAX_GAIN_INDEX                 0x431
+#define MYKONOS_ADDR_AGC_RX1_MIN_GAIN_INDEX                 0x432
+#define MYKONOS_ADDR_AGC_MANUAL_GAIN_CFG                    0x433
+#define MYKONOS_ADDR_AGC_MANUAL_GAIN_GPIO_SEL               0x434
+#define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_1             0x435
+#define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_2             0x436
+#define MYKONOS_ADDR_AGC_LOCK_LEVEL                         0x437
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_1                   0x438
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_2                   0x439
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_3                   0x43A
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_4                   0x43B
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_5                   0x43C
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_6                   0x43D
+#define MYKONOS_ADDR_AGC_RX1_GAIN_LOCK_DELAY                0x43E
+#define MYKONOS_ADDR_AGC_RX2_GAIN_LOCK_DELAY                0x43F
+#define MYKONOS_ADDR_AGC_RX1_ATTACK_DELAY                   0x440
+#define MYKONOS_ADDR_AGC_RX2_ATTACK_DELAY                   0x441
+#define MYKONOS_ADDR_AGC_ULB_THRSH                          0x442
+#define MYKONOS_ADDR_AGC_LLB_THRSH                          0x443
+#define MYKONOS_ADDR_AGC_RX_BLOCK_DET_DECAY                 0x444
+#define MYKONOS_ADDR_AGC_RESET_PD_HIGH_CNT                  0x445
+#define MYKONOS_ADDR_AGC_RX2_MAX_GAIN_INDEX                 0x446
+#define MYKONOS_ADDR_AGC_RX2_MIN_GAIN_INDEX                 0x447
+#define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_1                     0x448
+#define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_2                     0x449
+#define MYKONOS_ADDR_AGC_ORX_SNRX_MAX_GAIN_INDEX            0x44A
+#define MYKONOS_ADDR_AGC_ORX_SNRX_MIN_GAIN_INDEX            0x44B
+#define MYKONOS_ADDR_AGC_ORX_SNRX_MANUAL_GAIN_CFG           0x44C
+#define MYKONOS_ADDR_AGC_ORX_SNRX_GPIO_SEL                  0x44D
+#define MYKONOS_ADDR_AGC_ORX_SNRX_LOCK_LEVEL                0x44E
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_1          0x44F
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_2          0x450
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_3          0x451
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_4          0x452
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_5          0x453
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_6          0x454
+#define MYKONOS_ADDR_AGC_ORX_SNRX_GAIN_LOCK_DELAY           0x455
+#define MYKONOS_ADDR_AGC_ORX_SNRX_ATTACK_DELAY              0x456
+#define MYKONOS_ADDR_AGC_ORX_SNRX_ULB_THRSH                 0x457
+#define MYKONOS_ADDR_AGC_ORX_SNRX_LLB_THRSH                 0x458
+#define MYKONOS_ADDR_AGC_ORX_SNRX_BLOCK_DET_DECAY           0x459
+#define MYKONOS_ADDR_AGC_ORX_SNRX_RESET_PD_HIGH_CNT         0x45A
+#define MYKONOS_ADDR_AGC_ORX1_MANUAL_GAIN_INDEX             0x45B
+#define MYKONOS_ADDR_AGC_ORX2_MANUAL_GAIN_INDEX             0x45C
+#define MYKONOS_ADDR_AGC_SNRX_MANUAL_GAIN_INDEX             0x45D
+#define MYKONOS_ADDR_AGC_LOOPBACK1_MANUAL_GAIN_INDEX        0x45E
+#define MYKONOS_ADDR_AGC_LOOPBACK2_MANUAL_GAIN_INDEX        0x45F
+#define MYKONOS_ADDR_AGC_ORX_SNRX_ACTIVE                    0x460
+
+/* Mykonos Fast Attack AGC Registers */
+#define MYKONOS_ADDR_AGC_FAST_CFG_1                         0x468
+#define MYKONOS_ADDR_AGC_FAST_CFG_2                         0x469
+#define MYKONOS_ADDR_AGC_FAST_ENRGY_LOST_THRSH              0x46A
+#define MYKONOS_ADDR_AGC_FAST_STRONG_SIG_THRSH              0x46B
+#define MYKONOS_ADDR_AGC_FAST_SETTING_DELAY                 0x46C
+#define MYKONOS_ADDR_AGC_FAST_OPT_MAX_GAIN                  0x46D
+#define MYKONOS_ADDR_AGC_FAST_ENRGY_DET_CNT                 0x46E
+#define MYKONOS_ADDR_AGC_FAST_AGCLL_UPPER_LIMIT             0x46F
+#define MYKONOS_ADDR_AGC_FAST_GAIN_LOCK_EXIT_CNT            0x470
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_1                0x471
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_2                0x472
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_LOST_THRSH     0x473
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_STRONG_SIG_THRSH     0x474
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_SET_DELAY            0x475
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_OPT_MAX_GAIN         0x476
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_DET_CNT        0x477
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_AGCLL_UPPER_LIMIT    0x478
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_GAIN_LOCK_EXIT_CNT   0x479
+
+/* Mykonos Slow Loop - Hybrid AGC Registers */
+#define MYKONOS_ADDR_AGC_SLOW_LOCK_LEV_THRSH                    0x480
+#define MYKONOS_ADDR_AGC_SLOW_ULB_CNT_THRSH                     0x481
+#define MYKONOS_ADDR_AGC_SLOW_LLB_CNT_THRSH                     0x482
+#define MYKONOS_ADDR_AGC_SLOW_HIGH_OVRG_CNT_THRSH               0x483
+#define MYKONOS_ADDR_AGC_SLOW_LOW_OVRG_CNT_THRSH                0x484
+#define MYKONOS_ADDR_AGC_SLOW_VERYLOW_OVRG_CNT_THRSH            0x485
+#define MYKONOS_ADDR_AGC_SLOW_DIG_SAT_CNT_THRSH                 0x486
+#define MYKONOS_ADDR_AGC_SLOW_UPPER0_THRSH_GAIN_STEP            0x487
+#define MYKONOS_ADDR_AGC_SLOW_LOWER0_THRSH_GAIN_STEP            0x488
+#define MYKONOS_ADDR_AGC_SLOW_UPPER1_THRSH_GAIN_STEP            0x489
+#define MYKONOS_ADDR_AGC_SLOW_LOWER1_THRSH_GAIN_STEP            0x48A
+#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_1                 0x48B
+#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_2                 0x48C
+#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_3                 0x48D
+#define MYKONOS_ADDR_AGC_SLOW_LOOP_CFG                          0x48E
+#define MYKONOS_ADDR_AGC_SLOW_POWER_THRSH                       0x48F
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOCK_LEV_THRSH           0x490
+
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ULB_CNT_THRSH                0x491
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LLB_CNT_THRSH                0x492
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_HIGH_OVRG_CNT_THRSH      0x493
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_LOW_OVRG_CNT_THRSH       0x494
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_VERYLOW_OVRG_CNT_THRSH   0x495
+
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_DIG_SAT_CNT_THRSH        0x496
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER0_THRSH_GAIN_STEP   0x497
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER0_THRSH_GAIN_STEP   0x498
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER1_THRSH_GAIN_STEP   0x499
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER1_THRSH_GAIN_STEP   0x49A
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_1        0x49B
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_2        0x49C
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_3        0x49D
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOOP_CFG                 0x49E
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_POWER_THRSH              0x49F
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_1    0x4A0
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_2    0x4A1
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_1    0x4A2
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_2    0x4A3
+
+/* Mykonos Gain Control Read Registers */
+#define MYKONOS_ADDR_GAIN_CTL_CHANNEL_1                         0x4B0
+#define MYKONOS_ADDR_GAIN_CTL_FAST_ATTK_STATE                   0x4B1
+#define MYKONOS_ADDR_GAIN_CTL_SLOW_LOOP_STATE                   0x4B2
+#define MYKONOS_ADDR_GAIN_CTL_CHANNEL_2                         0x4B3
+#define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_1               0x4B4
+#define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_2               0x4B5
+#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_GAIN                     0x4B6
+#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_LOOP_STATE               0x4B7
+#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_OVRG_SIGS                0x4B8
+
+/* Mykonos Rx Data Path Overrange Registers */
+#define MYKONOS_ADDR_RX_OVRG_DATAPATH_OVRFLW                    0x4B9
+#define MYKONOS_ADDR_RX_OVRG_ORX_SNRX_DATAPATH_OVRFLW           0x4BA
+
+/* Mykonos RSSI Measurement Registers and Dec Power Measurement Registers*/
+#define MYKONOS_ADDR_RSSI_MEAS_DURATION_0_1                     0x4C0
+#define MYKONOS_ADDR_RSSI_MEAS_DURATION_2_3                     0x4C1
+#define MYKONOS_ADDR_RSSI_CFG                                   0x4C6
+#define MYKONOS_DEC_POWER_CONFIG_1                              0x4C7
+#define MYKONOS_DEC_POWER_CONFIG_2								0x4C8
+#define MYKONOS_ADDR_DPD_SNF_RSSI_CFG                           0x4CF
+#define MYKONOS_ADDR_DPD_RSSI_CFG                               0x4D6
+#define MYKONOS_SNIFFER_DEC_POWER_CONFIG_1						0x4D7
+#define MYKONOS_SNIFFER_DEC_POWER_CONFIG_2						0x4D8
+#define MYKONOS_CH1_DECIMATED_PWR								0x4DE
+#define MYKONOS_CH2_DECIMATED_PWR								0x4DF
+#define MYKONOS_SNIFFER_DECIMATED_PWR							0x4E6
+
+#define MYKONOS_ADDR_DIGITAL_GAIN_CONFIG                    0x4F0
+#define MYKONOS_ADDR_DPD_SNIFFER_DIGITAL_GAIN_CONFIG        0x4F1
+#define MYKONOS_ADDR_GAIN_TABLE_ADDR						0x500
+#define MYKONOS_ADDR_GAIN_TABLE_RX1_FE_GAIN					0x501
+#define MYKONOS_ADDR_GAIN_TABLE_RX1_EXT_CTL					0x502
+#define MYKONOS_ADDR_GAIN_TABLE_RX1_DIG_GAIN				0x503
+#define MYKONOS_ADDR_GAIN_TABLE_RX2_FE_GAIN					0x504
+#define MYKONOS_ADDR_GAIN_TABLE_RX2_EXT_CTL					0x505
+#define MYKONOS_ADDR_GAIN_TABLE_RX2_DIG_GAIN				0x506
+#define MYKONOS_ADDR_GAIN_TABLE_RX3_FE_GAIN					0x507
+#define MYKONOS_ADDR_GAIN_TABLE_RX3_LNA_ENAB				0x508
+#define MYKONOS_ADDR_GAIN_TABLE_RX3_DIG_GAIN				0x509
+#define MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION               0x516
+#define MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION           0x517
+#define MYKONOS_ADDR_RXFE1_LOCM                             0x520
+#define MYKONOS_ADDR_RXFE2_LOCM                             0x521
+#define MYKONOS_ADDR_RXLOOPBACK1_CNTRL_1                    0x540
+#define MYKONOS_ADDR_RXLOOPBACK2_CNTRL_1                    0x541
+#define MYKONOS_ADDR_RX_LOOPBACK1_CNTRL_4                   0x546
+#define MYKONOS_ADDR_RX_LOOPBACK2_CNTRL_4                   0x547
+
+/* Mykonos Overload/Peak Detection Registers */
+#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_CFG                    0x580
+#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_UPPER_THRSH            0x581
+#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_LOWER_THRSH            0x582
+
+#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_CFG                 0x583
+#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_UPPER_THRSH         0x584
+#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_LOWER_THRSH         0x585
+#define MYKONOS_ADDR_OVRLD_PD_DEC_VERYLOW_THRSH             0x586
+#define MYKONOS_ADDR_ORX_SNRX_OVRLD_ADC_OVRLD_CFG           0x587
+#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_CFG        0x58A
+#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_UPPER_THRSH    0x58B
+#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_LOWER_THRSH    0x58C
+#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_VERYLOW_THRSH  0x58D
+
+#define MYKONOS_ADDR_RX_ADC_FLASH_DELAY                     0x5B6
+#define MYKONOS_ADDR_RX_ADC_FLASH_CTRL                      0x5B7
+#define MYKONOS_ADDR_RX_ADC1_PRFL                           0x5DD
+#define MYKONOS_ADDR_RX_ADC2_PRFL                           0x5DE
+#define MYKONOS_ADDR_ORX_ADC_PRFL                           0x5DF
+
+#define MYKONOS_ADDR_RFDC_MEASURE_COUNT_1                   0x631
+#define MYKONOS_ADDR_RFDC_MEASURE_COUNT_2                   0x632
+#define MYKONOS_ADDR_RFDC_PROGRAM_SHIFT                     0x635
+#define MYKONOS_ADDR_RFDC_CONFIG2                           0x636
+#define MYKONOS_DPD_Sniffer_RFDC_CAL_TRACK_EN               0x642
+#define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_1               0x644
+#define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_2               0x645
+#define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_1               0x650
+#define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_2               0x651
+#define MYKONOS_ADDR_DIGITAL_DC_MIN_CAL_IDX                 0x63A
+#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SHIFT                0x674
+#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CONFIG               0x676
+#define MYKONOS_DIGITAL_DC_OFFSET_CH3_TRACKING              0x67A
+#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SNF                  0x67C
+#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CH3_DPD_M_SHIFT      0x67D
+
+#define MYKONOS_ADDR_RX_GAIN_COMP_DELAY                     0x710
+#define MYKONOS_ADDR_RX1_GAIN_COMP_OFFSET                   0x711
+#define MYKONOS_ADDR_RX2_GAIN_COMP_OFFSET                   0x712
+#define MYKONOS_ADDR_RX_GAIN_COMP_CFG                       0x713
+#define MYKONOS_ADDR_RX_SLCR_PIN_CFG                        0x714
+#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_DELAY             0x715
+#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_OFFSET            0x716
+#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_CFG               0x717
+#define MYKONOS_ADDR_DPD_SNF_RX_SLCR_PIN_CFG                0x718
+
+#define MYKONOS_ADDR_FLOATING_POINT_CFG                     0x750
+#define MYKONOS_ADDR_FLOATING_POINT_RX_CTRL                 0x751
+#define MYKONOS_ADDR_FLOATING_POINT_ORX_CTRL                0x752
+
+
+#define MYKONOS_ADDR_SNRX_LNA_BIAS_C                        0x81B
+
+
+#define MYKONOS_ADDR_ORX_ADC_FLASH_DELAY                     0x846
+#define MYKONOS_ADDR_ORX_ADC_FLASH_CTRL                      0x847
+
+#define MYKONOS_ADDR_TX_FILTER_CONFIGURATION                0x910
+#define MYKONOS_ADDR_TX1_ATTENUATION_0_READBACK             0x940
+#define MYKONOS_ADDR_TX1_ATTENUATION_1_READBACK             0x941
+#define MYKONOS_ADDR_TX2_ATTENUATION_0_READBACK             0x942
+#define MYKONOS_ADDR_TX2_ATTENUATION_1_READBACK             0x943
+#define MYKONOS_ADDR_TX_FILTER_OVERFLOW 					0x950
+
+/* Mykonos PA Protection Block Registers */
+#define MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION            0x955
+#define MYKONOS_ADDR_PA_PROTECTION_ATTEN_CONTROL            0x956
+#define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_LSB            0x957
+#define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_MSB            0x958
+#define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_LSB       0x959
+#define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_MSB       0x95A
+#define MYKONOS_ADDR_TX1_ATTENUATION_0                      0x960
+#define MYKONOS_ADDR_TX1_ATTENUATION_1                      0x961
+#define MYKONOS_ADDR_TX2_ATTENUATION_0                      0x962
+#define MYKONOS_ADDR_TX2_ATTENUATION_1                      0x963
+#define MYKONOS_ADDR_TX1_GAIN_0                             0x967
+#define MYKONOS_ADDR_TX1_GAIN_1                             0x968
+#define MYKONOS_ADDR_TX1_GAIN_2                             0x969
+#define MYKONOS_ADDR_TX2_GAIN_0                             0x96A
+#define MYKONOS_ADDR_TX2_GAIN_1                             0x96B
+#define MYKONOS_ADDR_TX2_GAIN_2                             0x96C
+#define MYKONOS_ADDR_TX_INCR_DECR_WORD                      0x96D
+#define MYKONOS_ADDR_TX_TPC_CONFIG                          0x96E
+#define MYKONOS_ADDR_TX_TPC_GPIO_CFG                        0x96F
+
+#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_MSB             0x9CB
+#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_LSB             0x9CC
+#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_MSB             0x9CD
+#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_LSB             0x9CE
+
+/* Mykonos GPIO Registers */
+#define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_7_0					0xB00
+#define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_15_8					0xB01
+#define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_7_0					0xB02
+#define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_15_8					0xB03
+#define MYKONOS_ADDR_GPIO_3V3_SPI_READ_7_0					0xB04
+#define MYKONOS_ADDR_GPIO_3V3_SPI_READ_15_8					0xB05
+#define MYKONOS_ADDR_GPIO_3V3_LSB_SRC_CTL					0xB06
+#define MYKONOS_ADDR_GPIO_3V3_MSB_SRC_CTL					0xB07
+
+#define MYKONOS_ADDR_GPIO_DIR_CTL_7_0					    0xB20
+#define MYKONOS_ADDR_GPIO_DIR_CTL_15_8					    0xB21
+#define MYKONOS_ADDR_GPIO_DIR_CTL_18_16					    0xB22
+#define MYKONOS_ADDR_GPIO_SPI_SRC_7_0					    0xB23
+#define MYKONOS_ADDR_GPIO_SPI_SRC_15_8					    0xB24
+#define MYKONOS_ADDR_GPIO_SPI_SRC_18_16					    0xB25
+#define MYKONOS_ADDR_GPIO_SPI_READ_7_0					    0xB26
+#define MYKONOS_ADDR_GPIO_SPI_READ_15_8					    0xB27
+#define MYKONOS_ADDR_GPIO_SPI_READ_18_16				    0xB28
+#define MYKONOS_ADDR_SOURCE_CONTROL_LOWER_BYTE              0xB29
+#define MYKONOS_ADDR_SOURCE_CONTROL_UPPER_BYTE              0xB2A
+#define MYKONOS_ADDR_SOURCE_CONTROL_EXTRA_BITS              0xB2B
+
+#define MYKONOS_ADDR_GPIO_MONITOR_INDEX                     0xB40
+#define MYKONOS_ADDR_GPIO_MONITOR_ENABLE                    0xB41
+
+#define MYKONOS_ADDR_GP_INTERRUPT_MASK_1                    0xB42
+#define MYKONOS_ADDR_GP_INTERRUPT_MASK_0                    0xB43
+#define MYKONOS_ADDR_GP_INTERRUPT_READ_1                    0xB44
+#define MYKONOS_ADDR_GP_INTERRUPT_READ_0                    0xB45
+
+#define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_5_0            0xB73
+#define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_9_6            0xB74
+#define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_5_0                 0xB75
+#define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_9_6                 0xB76
+#define MYKONOS_ADDR_AUX_DAC_LATCH_CONTROL                  0xB9F
+#define MYKONOS_ADDR_AUXDAC_0_WORD_MSB                      0xBA0
+
+#define MYKONOS_ADR_AUX_ADC_CLOCK_DIVIDE                    0xBC0
+#define MYKONOS_ADDR_AUX_ADC_CFG                            0xBC1
+#define MYKONOS_ADDR_AUX_ADC_READ_MSB                       0xBC2
+#define MYKONOS_ADDR_AUX_ADC_READ_LSB                       0xBC3
+#define MYKONOS_ADDR_AUX_ADC_SEL                            0xBC4
+#define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_0                0xBC5
+#define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_1                0xBC6
+
+#define MYKONOS_ADDR_TEMP_SENSOR_OFFSET                     0xBE0
+#define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB                0xBE1
+#define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_MSB                0xBE2
+#define MYKONOS_ADDR_TEMP_SENSOR_READ                       0xBE3
+#define MYKONOS_ADDR_TEMP_SENSOR_CONFIG                     0xBE4
+
+#define MYKONOS_ADDR_DIGITAL_TEST_BYTE_0                    0xC40
+
+/* ARM subsystem registers */
+#define MYKONOS_ADDR_ARM_CTL_1								0xD00
+#define MYKONOS_ADDR_ARM_CTL_2								0xD01
+#define MYKONOS_ADDR_ARM_ADDR_BYTE_0						0xD02
+#define MYKONOS_ADDR_ARM_ADDR_BYTE_1						0xD03
+#define MYKONOS_ADDR_ARM_DATA_BYTE_0						0xD04
+#define MYKONOS_ADDR_ARM_DATA_BYTE_1						0xD05
+#define MYKONOS_ADDR_ARM_DATA_BYTE_2						0xD06
+#define MYKONOS_ADDR_ARM_DATA_BYTE_3						0xD07
+#define MYKONOS_ADDR_ARM_CLK_CTL							0xD08
+#define MYKONOS_ADDR_AHB_SPI_BRIDGE							0xD09
+#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_0					0xD0A
+#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_1					0xD0B
+#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_2					0xD0C
+#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_3					0xD0D
+#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_0					0xD0E
+#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_1					0xD0F
+#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_2					0xD10
+#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_3					0xD11
+#define MYKONOS_ADDR_ARM_BRIDGE_CLK_CTL						0xD14
+
+/* ARM mailbox registers */
+#define MYKONOS_ADDR_ARM_CMD								0xD30
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_1						0xD31
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_2						0xD32
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_3						0xD33
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_4						0xD34
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_5						0xD35
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_6						0xD36
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_7						0xD37
+#define MYKONOS_ADDR_ARM_CMD_STATUS_0						0xD38
+#define MYKONOS_ADDR_ARM_CMD_STATUS_1						0xD39
+#define MYKONOS_ADDR_ARM_CMD_STATUS_2						0xD3A
+#define MYKONOS_ADDR_ARM_CMD_STATUS_3						0xD3B
+#define MYKONOS_ADDR_ARM_CMD_STATUS_4						0xD3C
+#define MYKONOS_ADDR_ARM_CMD_STATUS_5						0xD3D
+#define MYKONOS_ADDR_ARM_CMD_STATUS_6						0xD3E
+#define MYKONOS_ADDR_ARM_CMD_STATUS_7						0xD3F
+
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_0						0xD40
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_1						0xD41
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_2						0xD42
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_3						0xD43
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_4						0xD44
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_5						0xD45
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_6						0xD46
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_7						0xD47
+
+/* Mykonos Power-Down Override Control Registers */
+#define MYKONOS_ADDR_TX_PD_OVERRIDE_CONTROL_7_0             0xD89
+
+/* Mykonos Observation Framer Registers */
+#define MYKONOS_ADDR_OBS_FRAMER_RESET						0xDC0
+#define MYKONOS_ADDR_OBS_FRAMER_CLK_EN						0xDC1
+#define MYKONOS_ADDR_OBS_FRAMER_ADDR						0xDC2
+#define MYKONOS_ADDR_OBS_FRAMER_DATA						0xDC3
+#define MYKONOS_ADDR_OBS_FRAMER_WRITE_EN					0xDC4
+#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN				0xDC5
+#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_F					0xDC6
+#define MYKONOS_ADDR_OBS_FRAMER_LANE_CTL					0xDC7
+#define MYKONOS_ADDR_OBS_FRAMER_ADC_XBAR_SEL				0xDC8
+#define MYKONOS_ADDR_OBS_FRAMER_LANE_XBAR_SEL				0xDC9
+#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_LOOPBACK_XBAR_REV	0xDCA
+#define MYKONOS_ADDR_OBS_FRAMER_SYNCN_FILT					0xDCB
+#define MYKONOS_ADDR_OBS_FRAMER_LMFC_F_OFFSET				0xDCC
+#define MYKONOS_ADDR_OBS_FRAMER_LMFC_K_OFFSET				0xDCD
+#define MYKONOS_ADDR_OBS_FRAMER_TEST_CNTR_CTL				0xDCE
+#define MYKONOS_ADDR_OBS_FRAMER_STATUS_STRB					0xDCF
+#define MYKONOS_ADDR_OBS_FRAMER_STATUS						0xDD0
+#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_CNTR_STAT	0xDD1
+#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN	0xDD2
+#define MYKONOS_ADDR_OBS_FRAMER_LANE_FIFO_STRB				0xDD3
+#define MYKONOS_ADDR_OBS_FRAMER_LANE0_FIFO_RDWR_ADDR		0xDD4
+#define MYKONOS_ADDR_OBS_FRAMER_LANE1_FIFO_RDWR_ADDR		0xDD5
+#define MYKONOS_ADDR_OBS_FRAMER_LANE2_FIFO_RDWR_ADDR		0xDD6
+#define MYKONOS_ADDR_OBS_FRAMER_LANE3_FIFO_RDWR_ADDR		0xDD7
+#define MYKONOS_ADDR_OBS_FRAMER_PRBS10_CTL					0xDD8
+#define MYKONOS_ADDR_OBS_FRAMER_PRBS20_CTL					0xDD9
+#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_EN				0xDDA
+#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_7_TO_0			0xDDB
+#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_15_TO_8			0xDDC
+#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_19_TO_16		0xDDD
+#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_JTX_GEN				0xDDE
+#define MYKONOS_ADDR_OBS_FRAMER_LANE_DATA_CTL				0xDDF
+#define MYKONOS_ADDR_OBS_FRAMER_DATA_SAMPLE_CTL				0xDE0
+
+#define MYKONOS_ADDR_PFIR_COEFF_CTL                         0xDFF
+#define MYKONOS_ADDR_PFIR_COEFF_DATA                        0xE00
+#define MYKONOS_ADDR_PFIR_COEFF_ADDR                        0xE01
+
+/* ARM memory */
+#define MYKONOS_ADDR_ARM_START_PROG_ADDR					0x01000000
+#define MYKONOS_ADDR_ARM_END_PROG_ADDR						0x01017FFF
+#define MYKONOS_ADDR_ARM_START_DATA_ADDR					0x20000000
+#define MYKONOS_ADDR_ARM_END_DATA_ADDR						0x2000FFFF
+#define MYKONOS_ADDR_ARM_BUILD_CHKSUM_ADDR					0x01017FE0
+#define MYKONOS_ADDR_ARM_CALC_CHKSUM_ADDR					0x01017FE4
+#define MYKONOS_ADDR_ARM_VERSION                            0x01000128
+#define MYKONOS_ARM_ABORT_OPCODE                            0x00
+#define MYKONOS_ARM_RUNINIT_OPCODE                          0x02
+#define MYKONOS_ARM_RADIOON_OPCODE                          0x04
+#define MYKONOS_ARM_WRITECFG_OPCODE                         0x06
+#define MYKONOS_ARM_READCFG_OPCODE                          0x08
+#define MYKONOS_ARM_SET_OPCODE                              0x0A
+#define MYKONOS_ARM_GET_OPCODE                              0x0C
+
+#define MYKONOS_ARM_OBJECTID_DPDINIT_CONFIG                 0x0F
+#define MYKONOS_ARM_OBJECTID_CLGCINIT_CONFIG                0x10
+#define MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG                0x11
+#define MYKONOS_ARM_OBJECTID_DPDCONFIG                      0x24
+#define MYKONOS_ARM_DPD_RESET                               0x02
+#define MYKONOS_ARM_OBJECTID_GS_TRACKCALS                   0x66
+#define MYKONOS_ARM_OBJECTID_RXQEC_TRACKING                 0x20
+#define MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING                0x21
+#define MYKONOS_ARM_OBJECTID_TXLOL_TRACKING                 0x22
+#define MYKONOS_ARM_OBJECTID_TXQEC_TRACKING                 0x23
+#define MYKONOS_ARM_OBJECTID_CLGCCONFIG                     0x25
+#define MYKONOS_ARM_OBJECTID_VSWRCONFIG                     0x26
+#define MYKONOS_ARM_OBJECTID_CAL_STATUS                     0x42
+#define MYKONOS_ARM_OBJECTID_INIT_CAL_DONE                  0x43
+#define MYKONOS_ARM_OBJECTID_ORX_MODE                       0x61
+#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_SUSPEND_RESUME    0x65
+#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_CONTROL           0x66
+#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_PENDING           0x67
+#define MYKONOS_ARM_OBJECTID_RADIO_CONTROL                  0x81
+#define MYKONOS_ARM_OBJECTID_CALSCHEDULER                   0x83
+
+#define MYKONOS_ARM_SYSTEMSTATE_POWERUP                     0x00
+#define MYKONOS_ARM_SYSTEMSTATE_READY                       0x01
+#define MYKONOS_ARM_SYSTEMSTATE_IDLE                        0x02
+#define MYKONOS_ARM_SYSTEMSTATE_RADIO_ON                    0x03
+
+#define ORX_TRIGGER_SIGNALID      0x00
+#define ORX_MODE_0_SIGNALID       0x01
+#define ORX_MODE_1_SIGNALID       0x02
+#define ORX_MODE_2_SIGNALID       0x03
+#define RX1_ENABLE_ACK_SIGNALID   0x04
+#define RX2_ENABLE_ACK_SIGNALID   0x05
+#define TX1_ENABLE_ACK_SIGNALID   0x06
+#define TX2_ENABLE_ACK_SIGNALID   0x07
+#define ORX1_ENABLE_ACK_SIGNALID  0x08
+#define ORX2_ENABLE_ACK_SIGNALID  0x09
+#define SRX_ENABLE_ACK_SIGNALID   0x0A
+#define TX_OBS_SELECT_SIGNALID    0x0B
+
+#define DISABLE_DPD_ACTUATOR      0x03
+#define ENABLE_DPD_ACTUATOR       0x04
+#define SET_CLGC_DESIRED_GAIN_1   0x05
+#define SET_CLGC_DESIRED_GAIN_2   0x06
+#define SET_PATH_DELAY            0x08
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

datalink814_ge/src/hardware/mykonos/mykonos_user.c

@@ -0,0 +1,176 @@
+/**
+ * \file mykonos_user.c
+ * \brief Contains Mykonos default gain table values for Rx, ObsRx, and SnRx
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#include <stdint.h>
+#include "t_mykonos.h"
+#include "mykonos_user.h"
+
+/**
+ * \brief Default Rx gain table settings
+ */
+uint8_t RxGainTable [61][4] =
+{
+	/* Order: {FE table, External Ctl, Digital Gain/Atten, Enable Atten} */
+        {0, 0, 0, 0},  /* Gain index 255 */
+        {3, 0, 2, 1},  /* Gain index 254 */
+        {6, 0, 3, 1},  /* Gain index 253 */
+        {10, 0, 0, 0}, /* Gain index 252 */
+        {13, 0, 1, 1}, /* Gain index 251 */
+        {16, 0, 0, 0}, /* Gain index 250 */
+        {18, 0, 3, 1}, /* Gain index 249 */
+        {21, 0, 1, 1}, /* Gain index 248 */
+        {23, 0, 3, 1}, /* Gain index 247 */
+        {25, 0, 4, 1}, /* Gain index 246 */
+        {28, 0, 0, 0}, /* Gain index 245 */
+        {30, 0, 0, 0}, /* Gain index 244 */
+        {31, 0, 5, 1}, /* Gain index 243 */
+        {33, 0, 4, 1}, /* Gain index 242 */
+        {35, 0, 2, 1}, /* Gain index 241 */
+        {37, 0, 0, 0}, /* Gain index 240 */
+        {38, 0, 4, 1}, /* Gain index 239 */
+        {39, 0, 7, 1}, /* Gain index 238 */
+        {41, 0, 2, 1}, /* Gain index 237 */
+        {42, 0, 4, 1}, /* Gain index 236 */
+        {43, 0, 6, 1}, /* Gain index 235 */
+        {44, 0, 8, 1}, /* Gain index 234 */
+        {45, 0, 9, 1},  /* Gain index 233 */
+        {46, 0, 10, 1}, /* Gain index 232 */
+        {47, 0, 10, 1}, /* Gain index 231 */
+        {48, 0, 9, 1}, /* Gain index 230 */
+        {49, 0, 8, 1}, /* Gain index 229 */
+        {50, 0, 6, 1}, /* Gain index 228 */
+        {51, 0, 3, 1}, /* Gain index 227 */
+        {51, 0, 13, 1}, /* Gain index 226 */
+        {52, 0, 9, 1}, /* Gain index 225 */
+        {53, 0, 5, 1}, /* Gain index 224 */
+        {53, 0, 15, 1}, /* Gain index 223 */
+        {54, 0, 9, 1}, /* Gain index 222 */
+        {54, 0, 19, 1}, /* Gain index 221 */
+        {55, 0, 11, 1}, /* Gain index 220 */
+        {55, 0, 21, 1}, /* Gain index 219 */
+        {56, 0, 11, 1}, /* Gain index 218 */
+        {56, 0, 21, 1}, /* Gain index 217 */
+        {57, 0, 9, 1}, /* Gain index 216 */
+        {57, 0, 19, 1}, /* Gain index 215 */
+        {57, 0, 29, 1}, /* Gain index 214 */
+        {58, 0, 12, 1}, /* Gain index 213 */
+        {58, 0, 22, 1}, /* Gain index 212 */
+        {58, 0, 32, 1}, /* Gain index 211 */
+        {59, 0, 11, 1}, /* Gain index 210 */
+        {59, 0, 21, 1}, /* Gain index 209 */
+        {59, 0, 31, 1}, /* Gain index 208 */
+        {59, 0, 41, 1}, /* Gain index 207 */
+        {60, 0, 13, 1}, /* Gain index 206 */
+        {60, 0, 23, 1}, /* Gain index 205 */
+        {60, 0, 33, 1}, /* Gain index 204 */
+        {60, 0, 43, 1}, /* Gain index 203 */
+        {60, 0, 53, 1}, /* Gain index 202 */
+        {61, 0, 14, 1}, /* Gain index 201 */
+        {61, 0, 24, 1}, /* Gain index 200 */
+        {61, 0, 34, 1}, /* Gain index 199 */
+        {61, 0, 44, 1}, /* Gain index 198 */
+        {61, 0, 54, 1}, /* Gain index 197 */
+        {61, 0, 64, 1}, /* Gain index 196 */
+        {61, 0, 74, 1}, /* Gain index 195 */
+};
+
+/**
+ * \brief Default ORx gain table settings
+ */
+uint8_t ORxGainTable [19][4] =
+{
+	/* Order: {FE table, External Ctl, Digital Gain/Atten, Enable Atten} */
+	{0, 0, 0, 0},	/* Gain index 255 */
+	{7, 0, 0, 0},	/* Gain index 254 */
+	{13, 0, 1, 1},	/* Gain index 253 */
+	{18, 0, 3, 1},	/* Gain index 252 */
+	{23, 0, 3, 1},	/* Gain index 251 */
+	{28, 0, 0, 0},	/* Gain index 250 */
+	{32, 0, 0, 0},	/* Gain index 249 */
+	{35, 0, 2, 1},	/* Gain index 248 */
+	{38, 0, 4, 1},	/* Gain index 247 */
+	{41, 0, 2, 1},	/* Gain index 246 */
+	{43, 0, 6, 1},	/* Gain index 245 */
+	{46, 0, 0, 0},	/* Gain index 244 */
+	{47, 0, 10, 1},	/* Gain index 243 */
+	{49, 0, 8, 1},	/* Gain index 242 */
+	{51, 0, 3, 1},	/* Gain index 241 */
+	{52, 0, 9, 1},	/* Gain index 240 */
+	{53, 0, 14, 1},	/* Gain index 239 */
+	{54, 0, 18, 1},	/* Gain index 238 */
+	{56, 0, 0, 0}	/* Gain index 237 */
+
+};
+
+/**
+ * \brief Default SnRx gain table settings
+ */
+uint8_t SnRxGainTable [53][4] =
+{
+	/* Order: {FE table, LNA Bypass, Digital Gain/Atten, Enable Atten} */
+    {0,  0,  0, 0},  /* Gain index 255 */
+    {1,  0,  7, 1},  /* Gain index 254 */
+    {3,  0,  1, 0},  /* Gain index 253 */
+    {3,  0, 15, 1}, /* Gain index 252 */
+    {5,  0,  0, 0},  /* Gain index 251 */
+    {6,  0,  2, 1},  /* Gain index 250 */
+    {7,  0,  2, 1},  /* Gain index 249 */
+    {8,  0, 12, 1}, /* Gain index 248 */
+    {9,  0,  7, 1},  /* Gain index 247 */
+    {11, 0,  1, 0}, /* Gain index 246 */
+    {11, 0, 15, 1},/* Gain index 245 */
+    {13, 0,  1, 0}, /* Gain index 244 */
+    {14, 0,  2, 0}, /* Gain index 243 */
+    {14, 0, 10, 1},/* Gain index 242 */
+    {15, 0,  0, 0}, /* Gain index 241 */
+    {15, 0, 20, 1},/* Gain index 240 */
+    {16, 0,  2, 1}, /* Gain index 239 */
+    {16, 0, 22, 1},/* Gain index 238 */
+    {17, 0,  1, 0}, /* Gain index 237 */
+    {17, 0, 15, 1},/* Gain index 236 */
+    {17, 0, 35, 1},/* Gain index 235 */
+    {17, 0, 55, 1},/* Gain index 234 */
+    {18, 0,  7, 1}, /* Gain index 233 */
+    {18, 0, 27, 1},/* Gain index 232 */
+    { 6, 1,  7, 1},  /* Gain index 231 */
+    { 7, 1,  7, 1},  /* Gain index 230 */
+    { 8, 1, 17, 1}, /* Gain index 229 */
+    { 9, 1, 12, 1}, /* Gain index 228 */
+    {11, 1,  0, 0}, /* Gain index 227 */
+    {12, 1,  3, 1}, /* Gain index 226 */
+    {13, 1,  0, 0}, /* Gain index 225 */
+    {14, 1,  1, 0}, /* Gain index 224 */
+    {14, 1, 15, 1},/* Gain index 223 */
+    {15, 1,  5, 1}, /* Gain index 222 */
+    {15, 1, 25, 1},/* Gain index 221 */
+    {16, 1,  7, 1}, /* Gain index 220 */
+    {16, 1, 27, 1},/* Gain index 219 */
+    {17, 1,  0, 0}, /* Gain index 218 */
+    {17, 1, 20, 1},/* Gain index 217 */
+    {17, 1, 40, 1},/* Gain index 216 */
+    {17, 1, 60, 1},/* Gain index 215 */
+    {18, 1, 12, 1},/* Gain index 214 */
+    {18, 1, 32, 1},/* Gain index 213 */
+    {18, 1, 52, 1},/* Gain index 212 */
+    {18, 1, 72, 1},/* Gain index 211 */
+    {18, 1, 92, 1},/* Gain index 210 */
+    {19, 1,  1, 0}, /* Gain index 209 */
+    {19, 1, 15, 1},/* Gain index 208 */
+    {19, 1, 35, 1},/* Gain index 207 */
+    {19, 1, 55, 1},/* Gain index 206 */
+    {19, 1, 75, 1},/* Gain index 205 */
+    {19, 1, 95, 1},/* Gain index 204 */
+    {19, 1, 115, 1}/* Gain index 203 */
+};
+

datalink814_ge/src/hardware/mykonos/mykonos_user.h

@@ -0,0 +1,85 @@
+/**
+ * \file mykonos_user.h
+ *
+ * \brief Contains macro definitions and global structure declarations for mykonos_user.c
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef _MYKONOSPROFILES_H_
+#define _MYKONOSPROFILES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* turns verbose messaging on */
+#define MYKONOS_VERBOSE 1
+#define MYK_ENABLE_SPIWRITEARRAY 1
+
+/* 3 Bytes per SPI transaction * 341 transactions = ~1024 byte buffer size */
+/* Minimum MYK_SPIWRITEARRAY_BUFFERSIZE = 27 */
+#define MYK_SPIWRITEARRAY_BUFFERSIZE 341
+/*
+ *****************************************
+ * Rx, ObsRx, and Sniffer gain tables
+ ******************************************
+ */
+#define MAX_GAIN_TABLE_INDEX			255
+
+#define START_RX_GAIN_INDEX 			255
+#define MAX_RX_GAIN_TABLE_NUMINDEXES	(START_RX_GAIN_INDEX + 1)
+#define MIN_RX_GAIN_TABLE_INDEX			0
+
+#define START_ORX_GAIN_INDEX 			47
+#define MAX_ORX_GAIN_TABLE_NUMINDEXES  	(START_ORX_GAIN_INDEX + 1)
+#define MIN_ORX_GAIN_TABLE_INDEX		(MAX_GAIN_TABLE_INDEX - START_ORX_GAIN_INDEX)
+
+#define START_SNRX_GAIN_INDEX 			127
+#define MAX_SNRX_GAIN_TABLE_NUMINDEXES	(START_SNRX_GAIN_INDEX + 1)
+#define MIN_SNRX_GAIN_TABLE_INDEX		(MAX_GAIN_TABLE_INDEX - START_SNRX_GAIN_INDEX)
+
+#define START_LOOPBACK_GAIN_INDEX           47
+#define MAX_LOOPBACK_GAIN_TABLE_NUMINDEXES  (START_LOOPBACK_GAIN_INDEX + 1)
+#define MIN_LOOPBACK_GAIN_TABLE_INDEX       (MAX_GAIN_TABLE_INDEX - START_SNRX_GAIN_INDEX)
+
+extern uint8_t RxGainTable [61][4];
+extern uint8_t ORxGainTable [19][4];
+extern uint8_t SnRxGainTable [53][4];
+
+
+/*
+ ********************************************
+ * Rx, Sniffer, ObsRx and Tx Profiles limits
+ ********************************************
+ */
+#define MIN_RX_IQRATE_KHZ   15000       /*!< Mykonos minimum IQ rate for the Rx channel, expressed in KHz */
+#define MAX_RX_IQRATE_KHZ   320000      /*!< Mykonos maximum IQ rate for the Rx channel, expressed in KHz */
+
+#define MIN_TX_IQRATE_KHZ   15000       /*!< Mykonos minimum IQ rate for the Tx channel, expressed in KHz */
+#define MAX_TX_IQRATE_KHZ   492000      /*!< Mykonos maximum IQ rate for the Tx channel, expressed in KHz */
+
+#define MIN_SNIFFER_RFBW_HZ 5000000     /*!< Mykonos minimum Sniffer channel bandwidth expressed in Hz */
+#define MAX_SNIFFER_RFBW_HZ 20000000    /*!< Mykonos maximum Sniffer channel bandwidth expressed in Hz */
+
+#define MIN_ORX_RFBW_HZ     5000000     /*!< Mykonos minimum Observation channel bandwidth expressed in Hz */
+#define MAX_ORX_RFBW_HZ     250000000   /*!< Mykonos maximum Observation channel bandwidth expressed in Hz */
+
+#define MIN_RX_RFBW_HZ      5000000     /*!< Mykonos minimum Rx channel bandwidth expressed in Hz */
+#define MAX_RX_RFBW_HZ      100000000   /*!< Mykonos maximum Rx channel bandwidth expressed in Hz */
+
+#define MIN_TX_RFBW_HZ      20000000    /*!< Mykonos minimum Tx channel bandwidth expressed in Hz */
+#define MAX_TX_RFBW_HZ      250000000   /*!< Mykonos maximum Tx channel bandwidth expressed in Hz */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

datalink814_ge/src/hardware/mykonos/mykonos_version.h

@@ -0,0 +1,31 @@
+/**
+ * \file mykonos_version.h
+ * \brief Contains the version number for the Mykonos API
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in * this zip file.
+*
+*/
+
+#ifndef MYKONOS_VERSION_H_
+#define MYKONOS_VERSION_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MYKONOS_CURRENT_SI_VERSION 1    		/*!< Mykonos current silicon version */
+#define MYKONOS_CURRENT_MAJOR_VERSION 5			/*!< Mykonos current ARM major version */
+#define MYKONOS_CURRENT_MINOR_VERSION 2			/*!< Mykonos current ARM minor version */
+#define MYKONOS_CURRENT_BUILD_VERSION 3566		/*!< Mykonos current API build version */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MYKONOS_VERSION_H_ */

datalink814_ge/src/hardware/mykonos/t_ad9528.h

@@ -0,0 +1,194 @@
+/**
+ * \file t_ad9528.h
+ * \brief Contains enum and structure data types for all AD9528 function calls
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef _AD9528_TYPES_H_
+#define _AD9528_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "../common.h"
+
+/* AD9528 SPI Address defines */
+#define AD9528_ADDR_ADI_SPI_CONFIG_A  0x000
+#define AD9528_ADDR_ADI_SPI_CONFIG_B  0x001
+#define AD9528_ADDR_IO_UPDATE         0x00F
+
+#define AD9528_ADDR_REF_A_DIVIDER_LSB 0x100
+#define AD9528_ADDR_REF_A_DIVIDER_MSB 0x101
+#define AD9528_ADDR_REF_B_DIVIDER_LSB 0x102
+#define AD9528_ADDR_REF_B_DIVIDER_MSB 0x103
+#define AD9528_ADDR_PLL1_N_DIV_LSB    0x104
+#define AD9528_ADDR_PLL1_N_DIV_MSB    0x105
+#define AD9528_ADDR_PLL1_CHARGEPUMP   0x106
+#define AD9528_ADDR_PLL1_CP_CTRL2     0x107
+#define AD9528_ADDR_INPUT_RECEIVERS1  0x108
+#define AD9528_ADDR_INPUT_RECEIVERS2  0x109
+#define AD9528_ADDR_INPUT_RECEIVERS3  0x10A
+#define AD9528_ADDR_PLL1_FASTLOCK     0x10B
+
+#define AD9528_ADDR_PLL2_CHARGEPUMP        0x200
+#define AD9528_ADDR_PLL2_N_DIV             0x201
+#define AD9528_ADDR_PLL2_CTRL              0x202
+#define AD9528_ADDR_PLL2_VCO_CTRL          0x203
+#define AD9528_ADDR_PLL2_VCO_DIV           0x204
+#define AD9528_ADDR_PLL2_LF_CTRL1          0x205
+#define AD9528_ADDR_PLL2_LF_CTRL2          0x206
+#define AD9528_ADDR_PLL2_RDIV              0x207
+#define AD9528_ADDR_PLL2_REPLICA_CHDIV     0x208
+#define AD9528_ADDR_PLL2_REPLICA_DIV_PHASE 0x209
+
+#define AD9528_ADDR_CH_OUT0_CTRL1       0x300
+#define AD9528_ADDR_CH_OUT0_CTRL2       0x301
+#define AD9528_ADDR_CH_OUT0_CHDIV       0x302
+#define AD9528_ADDR_OUTPUT_SYNC         0x32A
+#define AD9528_ADDR_MASK_SYNC1          0x32B
+#define AD9528_ADDR_MASK_SYNC2          0x32C
+#define AD9528_ADDR_EN_OUTPUT_PATH_SEL1 0x32D
+#define AD9528_ADDR_EN_OUTPUT_PATH_SEL2 0x32E
+
+#define AD9528_ADDR_SYSERF_DIV_LSB      0x400
+#define AD9528_ADDR_SYSERF_DIV_MSB      0x401
+#define AD9528_ADDR_SYSREF_CTRL3        0x402
+#define AD9528_ADDR_SYSREF_CTRL4        0x403
+#define AD9528_ADDR_SYSREF_CTRL5        0x404
+
+#define AD9528_ADDR_POWERDOWN_CTRL      0x500
+#define AD9528_ADDR_CH_POWERDOWN1       0x501
+#define AD9528_ADDR_CH_POWERDOWN2       0x502
+#define AD9528_ADDR_LDO_ENABLES1        0x503
+#define AD9528_ADDR_LDO_ENABLES2        0x504
+#define AD9528_ADDR_STATUS0_CTRL        0x505
+#define AD9528_ADDR_STATUS1_CTRL        0x506
+#define AD9528_ADDR_STATUS_OE           0x507
+#define AD9528_ADDR_STATUS_READBACK0    0x508
+#define AD9528_ADDR_STATUS_READBACK1    0x509
+
+
+
+///Enum to select what source outputs from each AD9528 output channel
+typedef enum
+{
+    CHANNEL_DIV = 0, PLL1_OUTPUT = 1, //VCXO frequency
+    SYSREF = 2,
+    INV_PLL1_OUTPUT = 5 //VCXO inverted
+} ad9528outSourceSel_t;
+
+///Enum to select what output buffer standard is used for the clock outputs
+typedef enum
+{
+    LVDS = 0, LVDS_BOOST = 1, HSTL = 2
+} ad9528outBufferControl_t;
+
+///Enum to select the clock input buffer mode.
+typedef enum
+{
+    DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
+} ad9528RefBuffer_t;
+
+/// Structure to hold AD9528 PLL1 settings
+typedef struct
+{
+    uint32_t refA_Frequency_Hz;
+    uint16_t refA_Divider;
+    ad9528RefBuffer_t refA_bufferCtrl;
+
+    uint32_t refB_Frequency_Hz;
+    uint16_t refB_Divider;
+    ad9528RefBuffer_t refB_bufferCtrl;
+
+    uint32_t vcxo_Frequency_Hz;
+    ad9528RefBuffer_t vcxoBufferCtrl;
+
+    uint16_t nDivider;
+    uint8_t bypassPll1;
+} ad9528pll1Settings_t;
+
+/// Structure to hold AD9528 PLL2 settings
+typedef struct
+{
+    uint8_t rfDivider; //VCO divider: Valid range (3,4,5)
+    uint8_t n2Divider; //PLL2 N2 Divider
+    uint8_t totalNdiv; //NDiv = 4*Bdiv + Adiv //Bdiv valid range (3 to 63), Adiv valid range (0-3)
+} ad9528pll2Settings_t;
+
+/// Structure to hold AD9528 Output Clock settings
+typedef struct
+{
+    uint16_t outPowerDown; //bit per output, if 1 power down that output.
+    ad9528outSourceSel_t outSource[14]; //CHANNEL_DIV, PLL1_OUTPUT, SYSREF, INV_PLL1_OUTPUT
+    ad9528outBufferControl_t outBufferCtrl[14]; //LVDS, LVDS_BOOST, HSTL
+    uint8_t outAnalogDelay[14]; //5 bits
+    uint8_t outDigitalDelay[14]; //6 bits, 1/2 clock resolution @ channel div input frequency
+    uint8_t outChannelDiv[14]; //8 bit channel divider
+    uint32_t outFrequency_Hz[14]; //output clock frequency per clock output
+} ad9528outputSettings_t;
+
+///Enum to select the SYSREF output source
+typedef enum
+{
+    EXTERNAL = 0, EXT_RESAMPLED = 1, INTERNAL = 2
+} sysrefSourceSelection_t;
+
+///Enum to choose the SYSREF pattern mode.
+typedef enum
+{
+    NSHOT = 0, CONTINUOUS = 1, PRBS = 2, STOP = 3
+} sysrefPatternMode_t;
+
+///Enum to select the SYSREF input pin mode.
+typedef enum
+{
+    LEVEL_ACTIVE_HIGH = 0, LEVEL_ACTIVE_LOW = 1, RISING_EDGE = 2, FALLING_EDGE = 3
+} sysrefPinEdgeMode_t;
+
+///Enum to select the SYSREF output # of pulses for NSHOT mode.
+typedef enum
+{
+    ONE_PULSE = 0, TWO_PULSES = 2, FOUR_PULSES = 3, SIX_PULSES = 4, EIGHT_PULSES = 5
+} sysrefNshotMode_t;
+
+//Enum to select how a SYSREF is requested.
+typedef enum
+{
+    SPI = 0, PIN = 1
+} sysrefRequestMethod_t;
+
+/// Structure to hold AD9528 SYSREF output settings
+typedef struct
+{
+    sysrefRequestMethod_t sysrefRequestMethod;
+    sysrefSourceSelection_t sysrefSource;
+    sysrefPinEdgeMode_t sysrefPinEdgeMode;
+    ad9528RefBuffer_t sysrefPinBufferMode;
+    sysrefPatternMode_t sysrefPatternMode;
+    sysrefNshotMode_t sysrefNshotMode;
+    uint16_t sysrefDivide;
+
+} ad9528sysrefSettings_t;
+
+/// Structure to hold AD9528 settings
+typedef struct
+{
+    spiSettings_t *spiSettings;
+    ad9528pll1Settings_t *pll1Settings;
+    ad9528pll2Settings_t *pll2Settings;
+    ad9528outputSettings_t *outputSettings;
+    ad9528sysrefSettings_t *sysrefSettings;
+} ad9528Device_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

datalink814_ge/src/hardware/mykonos/t_mykonos_gpio.h

@@ -0,0 +1,375 @@
+/*!
+ * \file t_mykonos_gpio.h
+ * \brief Mykonos GPIO error handling and type defines
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef T_MYKONOSGPIO_H_
+#define T_MYKONOSGPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include "../common.h"
+
+/**
+ *  \brief Enum of unique error codes from the Mykonos GPIO API functions.
+ * Each error condition in the library should get its own enum value to allow
+ * easy debug of errors.
+ */
+typedef enum
+{
+	MYKONOS_ERR_GPIO_OK = 0,
+	MYKONOS_ERR_EN_MONITOR_OUT_NOT_ENABLED,
+    MYKONOS_ERR_EN_MONITOR_OUT_SRC_CTRL,
+    MYKONOS_ERR_MONITOR_OUT_INDEX_RANGE,
+    MYKONOS_ERR_GETGPIOMON_INDEX_NULL_PARM,
+    MYKONOS_ERR_GETGPIOMON_MONITORMASK_NULL_PARM,
+
+    MYKONOS_ERR_MGCRX2_GPIO_DECPIN_INV_PARAM,
+    MYKONOS_ERR_MGCRX2_GPIO_INCPIN_INV_PARAM,
+    MYKONOS_ERR_MGCRX2_SOURCE_CONFIG,
+    MYKONOS_ERR_MGCRX2_STEP_INV_PARAM,
+    MYKONOS_ERR_MGCRX1_GPIO_DECPIN_INV_PARAM,
+    MYKONOS_ERR_MGCRX1_GPIO_INCPIN_INV_PARAM,
+    MYKONOS_ERR_MGCRX1_STEP_INV_PARAM,
+    MYKONOS_ERR_GETRX2PIN_INCSTEP_NULL_PARM,
+    MYKONOS_ERR_GETRX2PIN_DECSTEP_NULL_PARM,
+    MYKONOS_ERR_GETRX2PIN_INCPIN_NULL_PARM,
+    MYKONOS_ERR_GETRX2PIN_DECPIN_NULL_PARM,
+    MYKONOS_ERR_GETRX2PIN_EN_NULL_PARM,
+    MYKONOS_ERR_GETRX1PIN_INCSTEP_NULL_PARM,
+    MYKONOS_ERR_GETRX1PIN_DECSTEP_NULL_PARM,
+    MYKONOS_ERR_GETRX1PIN_INCPIN_NULL_PARM,
+    MYKONOS_ERR_GETRX1PIN_DECPIN_NULL_PARM,
+    MYKONOS_ERR_GETRX1PIN_EN_NULL_PARM,
+
+    MYKONOS_ERR_TPCTX2_GPIO_DECPIN_INV_PARAM,
+    MYKONOS_ERR_TPCTX2_GPIO_INCPIN_INV_PARAM,
+    MYKONOS_ERR_TPCTX2_GPIO_STEP_INV_PARAM,
+    MYKONOS_ERR_TPCTX1_GPIO_DECPIN_INV_PARAM,
+    MYKONOS_ERR_TPCTX1_GPIO_INCPIN_INV_PARAM,
+    MYKONOS_ERR_TPCTX1_GPIO_STEP_INV_PARAM,
+    MYKONOS_ERR_GETTX2PIN_STEP_NULL_PARM,
+    MYKONOS_ERR_GETTX2PIN_INC_NULL_PARM,
+    MYKONOS_ERR_GETTX2PIN_DEC_NULL_PARM,
+    MYKONOS_ERR_GETTX2PIN_EN_NULL_PARM,
+    MYKONOS_ERR_GETTX2PIN_TX1TX2_NULL_PARM,
+    MYKONOS_ERR_GETTX1PIN_STEP_NULL_PARM,
+    MYKONOS_ERR_GETTX1PIN_INC_NULL_PARM,
+    MYKONOS_ERR_GETTX1PIN_DEC_NULL_PARM,
+    MYKONOS_ERR_GETTX1PIN_EN_NULL_PARM,
+    MYKONOS_ERR_GETTX1PIN_TX1TX2_NULL_PARM,
+
+	MYKONOS_ERR_SPI2_INV_GPIO,
+	MYKONOS_ERR_SPI2_INV_SETUP,
+
+	MYKONOS_ERR_SET_GPIO_1V8_INV_POINTER,
+
+	MYKONOS_ERR_GETGPIOSETLEVEL_NULL_PARM,
+	MYKONOS_ERR_READGPIOSPI_NULL_PARM,
+    MYKONOS_ERR_SET_GPIO_1V8_INV_MODE,
+    MYKONOS_ERR_GETGPIO_OE_NULL_PARM,
+    MYKONOS_ERR_GPIO_OE_INV_PARAM,
+    MYKONOS_ERR_GPIO_SRC_PARAM_INV,
+    MYKONOS_ERR_GET_GPIO_SOURCE_CONTROL_NULL_PARM,
+
+    MYKONOS_ERR_INV_GP_INT_MASK_PARM,
+    MYKONOS_ERR_GP_INT_STATUS_NULL_PARAM,
+
+    MYKONOS_ERR_GETGPIO3V3OUT_NULL_PARM,
+    MYKONOS_ERR_SET_GPIO_3V3_INV_POINTER,
+    MYKONOS_ERR_GETGPIO3V3SPI_NULL_PARM,
+    MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM,
+    MYKONOS_ERR_SET_GPIO_3V3_INV_MODE,
+    MYKONOS_ERR_SET_GPIO_3V3_INV_SRC_CTRL,
+
+    MYKONOS_ERR_SET_ARMGPIO_INV_POINTER,
+    MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR,
+    MYKONOS_ERR_SET_ARMGPIO_PINS_INV_SIGNALID,
+    MYKONOS_ERR_SET_ARMGPIO_PINS_INV_GPIOPIN,
+
+    MYKONOS_ERR_SETUPAUXDAC_NULL_PARAM,
+    MYKONOS_ERR_WRITEAUXDAC_NULL_AUXIO,
+    MYKONOS_ERR_READAUXADC_NULL_PARAM,
+    MYKONOS_ERR_SETUPAUXDAC_INV_AUXDACCODE,
+    MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACCODE,
+    MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACINDEX,
+    MYKONOS_ERR_INV_AUX_ADC_CHAN_PARM,
+    MYKONOS_ERR_SETUPAUXADC_INV_VCODIV,
+    MYKONOS_ERR_INV_AUX_ADC_DEC_PARM,
+
+    MYKONOS_ERR_GAINCOMP_NULL_STRUCT,
+    MYKONOS_ERR_GAINCOMP_EN_NULL_PARM,
+    MYKONOS_ERR_GAINCOMP_SET_NULL_STRUCT,
+    MYKONOS_ERR_GAINCOMP_INV_RX1_OFFSET,
+    MYKONOS_ERR_GAINCOMP_INV_RX2_OFFSET,
+    MYKONOS_ERR_GAINCOMP_INV_STEP,
+    MYKONOS_ERR_GAINCOMP_INV_EN,
+
+    MYKONOS_ERR_OBS_RX_GAINCOMP_SET_NULL_STRUCT,
+    MYKONOS_ERR_OBS_RX_GAINCOMP_EN_NULL_PARAM,
+    MYKONOS_ERR_OBS_RX_GAINCOMP_INV_EN,
+    MYKONOS_ERR_OBS_RX_GAINCOMP_INV_OFFSET,
+    MYKONOS_ERR_OBS_RX_GAINCOMP_INV_STEP,
+    MYKONOS_ERR_OBS_RX_GAINCOMP_NULL_STRUCT,
+
+    MYKONOS_ERR_SLICER_STEP_OUT_OF_RANGE,
+    MYKONOS_ERR_SLICER_INV_RX1_SEL,
+    MYKONOS_ERR_SLICER_INV_RX2_SEL,
+    MYKONOS_ERR_SLICER_EN_INV,
+
+    MYKONOS_ERR_SLICER_RX1PIN_NULL_PARM,
+    MYKONOS_ERR_SLICER_RX2PIN_NULL_PARM,
+    MYKONOS_ERR_SLICER_STEP_NULL_PARM,
+    MYKONOS_ERR_SLICER_EN_NULL_PARM,
+
+    MYKONOS_ERR_SLICER_INV_OBS_RX_SEL,
+    MYKONOS_ERR_SLICER_OBS_RX_STEP_OUT_OF_RANGE,
+    MYKONOS_ERR_SLICER_OBS_RX_EN_INV,
+    MYKONOS_ERR_SLICER_OBS_RX_EN_NULL_PARM,
+    MYKONOS_ERR_SLICER_OBS_RX_STEP_NULL_PARM,
+    MYKONOS_ERR_SLICER_OBS_RXPIN_NULL_PARM,
+
+    MYKONOS_ERR_FLOATFRMT_NULL_STRUCT,
+    MYKONOS_ERR_FLOATFRMT_SET_NULL_STRUCT,
+    MYKONOS_ERR_FLOATFRMT_INV_ROUND_MODE,
+    MYKONOS_ERR_FLOATFRMT_INV_DATA_FORMAT,
+    MYKONOS_ERR_FLOATFRMT_INV_ENC_NAN,
+    MYKONOS_ERR_FLOATFRMT_INV_EXP_BITS,
+    MYKONOS_ERR_FLOATFRMT_INV_LEADING,
+    MYKONOS_ERR_FLOATFRMT_INV_RX1ATT,
+    MYKONOS_ERR_FLOATFRMT_INV_RX2ATT,
+    MYKONOS_ERR_FLOATFRMT_INV_EN,
+    MYKONOS_ERR_FLOATFRMT_NULL_RX1ATT,
+    MYKONOS_ERR_FLOATFRMT_NULL_RX2ATT,
+    MYKONOS_ERR_FLOATFRMT_NULL_ENABLE,
+    MYKONOS_ERR_FLOATFRMT_SET_INV_EN,
+    MYKONOS_ERR_FLOATFRMT_SET_INV_RX1ATT,
+    MYKONOS_ERR_FLOATFRMT_SET_INV_RX2ATT,
+
+    MYKONOS_ERR_FLOATFRMT_INV_ORXATT,
+    MYKONOS_ERR_FLOATFRMT_INV_ORXEN,
+    MYKONOS_ERR_FLOATFRMT_NULL_ORXATT,
+    MYKONOS_ERR_FLOATFRMT_NULL_ORXENABLE,
+
+    MYKONOS_ERR_SETUPTEMPSENSOR_NULL_PARAM,
+    MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPDECIMATION,
+    MYKONOS_ERR_SETUPTEMPSENSOR_INV_OFFSET,
+    MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPWINDOW,
+    MYKONOS_ERR_GETTEMPSENSORCFG_NULL_PARAM,
+    MYKONOS_ERR_READTEMPSENSOR_NULL_PARAM,
+    MYKONOS_ERR_READTEMPSENSOR_NOT_LOCKED,
+
+    MYKONOS_ERR_GAIN_CONTROL_NOT_HYBRID,
+    MYKONOS_ERR_GPIO_HYBRID_RX1_PIN,
+    MYKONOS_ERR_GPIO_HYBRID_RX2_PIN,
+    MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_NULL_PARM,
+    MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_NULL_PARM,
+    MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_READ,
+    MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_READ,
+    MYKONOS_ERR_AGC_OBS_NOT_IN_HYBRID,
+    MYKONOS_ERR_GPIO_HYBRID_ORX_PIN,
+    MYKONOS_ERR_GPIO_HYBRID_ORX_PIN_NULL_PARM,
+
+    MYKONOS_ERR_GAIN_CONTROL_NOT_AGC,
+    MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN,
+    MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN,
+    MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN_NULL_PARM,
+    MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN_NULL_PARM,
+    MYKONOS_ERR_OBS_GAIN_CONTROL_NOT_AGC,
+    MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN,
+    MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN_NULL_PARM,
+
+    MYKONOS_ERR_GETGPIODRV_NULL_PARAM,
+    MYKONOS_ERR_GPIO_DRV_INV_PARAM,
+
+    MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM,
+    MYKONOS_ERR_GPIO_GETSLEW_NULL_PARAM,
+
+    MYKONOS_ERR_CMOS_DRV_INV_PARAM,
+    MYKONOS_ERR_CMOS_DRV_NULL_PARAM
+} mykonosGpioErr_t;
+
+/**
+ *  \brief Enum of possible Rx Slicer pin combinations
+ */
+typedef enum
+{
+    GPIO_0_1_2      = 0,    /*!< GPIO combination for RX1        */
+    GPIO_5_6_7      = 1,    /*!< GPIO combination for RX1 or RX2 */
+    GPIO_8_9_10     = 2,    /*!< GPIO combination for RX1        */
+    GPIO_11_12_13   = 3     /*!< GPIO combination for RX2        */
+} mykonosRxSlicer_t;
+
+/**
+ *  \brief Enum of possible observation channel Slicer pin combinations
+ */
+typedef enum
+{
+    GPIO_18_17_16      = 0,    /*!< GPIO combination for observation channel */
+    GPIO_16_15_14      = 1     /*!< GPIO combination for observation channel */
+} mykonosObsRxSlicer_t;
+
+/**
+ *  \brief Enum of possible GPIO slew rate settings
+ */
+typedef enum
+{
+    MYK_SLEWRATE_NONE    = 0,    /*!< Lower slew rate for the GPIO  */
+    MYK_SLEWRATE_LOW     = 1,    /*!< Low slew rate for the GPIO    */
+    MYK_SLEWRATE_MEDIUM  = 2,    /*!< Medium slew rate for the GPIO */
+    MYK_SLEWRATE_HIGH    = 3     /*!< High slew rate for the GPIO   */
+} mykonosGpioSlewRate_t;
+
+/**
+ * \brief Enumerated list of CMOS pads drive strength options
+ */
+typedef enum
+{
+    MYK_CMOSPAD_DRV_1X  = 0x00,       /*!<  2.5pF  load @ 65MHz */
+    MYK_CMOSPAD_DRV_2X  = 0x01,       /*!<    5pF  load @ 65MHz */
+    MYK_CMOSPAD_DRV_3X  = 0x03,       /*!<  7.5pF  load @ 65MHz */
+    MYK_CMOSPAD_DRV_4X  = 0x07,       /*!<   10pF  load @ 65MHz */
+    MYK_CMOSPAD_DRV_5X  = 0x0F        /*!< 12.5pF  load @ 65MHz */
+} mykonosCmosPadDrvStr_t;
+
+
+/**
+ * \brief Enumerated list for Aux ADCs
+ */
+typedef enum
+{
+    MYK_AUXADC_0        = 0x00,       /*!< Aux ADC channel 0 */
+    MYK_AUXADC_1        = 0x01,       /*!< Aux ADC channel 1 */
+    MYK_AUXADC_2        = 0x02,       /*!< Aux ADC channel 2 */
+    MYK_AUXADC_3        = 0x03,       /*!< Aux ADC channel 3 */
+    MYK_AUXADC_0_DIV2   = 0x04,       /*!< Aux ADC channel 0 with the divider by 2 set */
+    MYK_TEMPSENSOR      = 0x10        /*!< Temperature sensor channel */
+} mykonosAuxAdcChannels_t;
+
+
+/**
+ *  \brief Data structure to hold Gain compensation settings for the main receive channels
+ **/
+typedef struct
+{
+    uint8_t rx1Offset;  /*!< These parameter contains the Rx1 offset word used for the gain compensation
+                        when the gain index is at its maximum setting.
+                         It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */
+    uint8_t rx2Offset;  /*!< These parameter contains the Rx2 offset word used for the gain compensation
+                        when the gain index is at its maximum setting.
+                        It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */
+    uint8_t compStep;   /*!< These bits contains the value in dB that the total Rx gain changes
+                         when there is an LSB change in the gain index according to the following settings:
+                         compStep |  dB ramp
+                         ---------|------------
+                            0     |   0.25dB
+                            1     |   0.5dB
+                            2     |   1.0dB
+                            3     |   2.0dB
+                            4     |   3.0dB
+                            5     |   4.0dB
+                            6     |   6.0dB
+                            7     |   Not valid defaulted to 0.25dB */
+} mykonosGainComp_t;
+
+/**
+ *  \brief Data structure to hold Gain compensation settings for the observation channel
+ **/
+typedef struct
+{
+    uint8_t obsRxOffset;    /*!< These parameter contains the Rx1 offset word used for the gain compensation
+                            when the gain index is at its maximum setting.
+                            It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */
+    uint8_t compStep;       /*!< These bits contains the value in dB that the total Rx gain changes
+                            when there is an LSB change in the gain index according to the following settings:
+                            compStep |  dB ramp
+                            ---------|------------
+                               0     |   0.25dB
+                               1     |   0.5dB
+                               2     |   1.0dB
+                               3     |   2.0dB
+                               4     |   3.0dB
+                               5     |   4.0dB
+                               6     |   6.0dB
+                               7     |   Not valid defaulted to 0.25dB */
+} mykonosObsRxGainComp_t;
+
+/**
+ * \brief Data structure to hold floating point formatter settings for the floating point
+ *  number generation
+ **/
+typedef struct
+{
+   uint8_t roundMode;   /*!<These parameter set the round modes for the significand.
+                        The following settings are defined in the IEEE754 specification:
+                        roundMode |  Round type
+                        ----------|-----------------
+                             0    |  RoundTiesToEven
+                             1    |  RoundTowardsPositive
+                             2    |  RoundTowardsNegative
+                             3    |  RoundTowardsZero
+                             4    |  RoundTiesToAway*/
+   uint8_t dataFormat;  /*!< These parameter sets the format of the 16-bit output on the JESD interface:
+                        Setting this to 1 then the format is from MSB to LSB to {sign, significand, exponent}.
+                        Clearing this bit sets the format to {sign, exponent, significand}.*/
+   uint8_t encNan;      /*!< if this parameter is set to 1 then the floating point formatter reserves the highest value
+                        of exponent for NaN to be compatible to the IEEE754 specification.
+                        Clearing this parameter increases the range of the exponent by one.*/
+   uint8_t expBits;     /*!<These parameter is used to indicate the number of exponent bits in the floating point number
+                        according to the following settings:
+                          expBits|  Round type
+                         --------|------------------------------------------------
+                            0    |  2 bit exponent, 13 bit significand, 1 bit sign
+                            1    |  3 bit exponent, 12 bit significand, 1 bit sign
+                            2    |  4 bit exponent, 11 bit significand, 1 bit sign
+                            3    |  5 bit exponent, 10 bit significand, 1 bit sign */
+   uint8_t leading;     /*!< Setting this parameter hides the leading one in the the significand to be compatible to the IEEE754 specification.
+                        Clearing this parameter causes the leading one to be at the MSB of the significand.*/
+}mykonosFloatPntFrmt_t;
+
+/**
+ *  \brief Data structure used to configure the on-die Temperature Sensor
+ */
+typedef struct
+{
+    uint8_t tempDecimation;      /*!<3-bit value that controls the AuxADC decimation factor when used for temp sensor calculations;
+                                 AuxADC_decimation = 256 * 2^tempDecimation */
+    uint8_t offset;              /*!< 8-bit offset that gets added to temp sensor code internally */
+    uint8_t overrideFusedOffset; /*!< This bit overrides the factory-calibrated fuse offset
+                                 and uses the value stored in the offset member */
+    uint8_t tempWindow;          /*!<  4-bit code with a resolution of 1?C/LSB, each time a temperature measurement is performed,
+                                 the device compares the current temperature against the previous value.*/
+}mykonosTempSensorConfig_t;
+
+
+/**
+ *  \brief Data structure used to store Temperature Sensor related values
+ */
+typedef struct
+{
+    int16_t tempCode;       /*!< 16-bit signed temperature value (in deg C) that is read back */
+    uint8_t windowExceeded; /*!< If the absolute value of the difference is greater than the value in temperature configuration
+                            tempWindow, the windowExceeded flag is set.*/
+    uint8_t windowHiLo;     /*!<when windowExceeded member gets set,
+                            this bit is set to 1 if current value is greater than previous value, else reset */
+    uint8_t tempValid;      /*!< When the reading is complete and a valid temperature value stored in tempCode*/
+}mykonosTempSensorStatus_t;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* T_MYKONOSGPIO_H_ */

datalink814_ge/src/hardware/parameters.h

@@ -0,0 +1,82 @@
+/***************************************************************************//**
+ *   @file   ad9371/src/devices/adi_hal/parameters.h
+ *   @brief  Platform dependent parameters.
+ *   @author DBogdan (dragos.bogdan@analog.com)
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef _PARAMETERS_H_
+#define _PARAMETERS_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include "platform_drivers.h"
+#include "xparameters.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define DDR_MEM_BASEADDR		XPAR_DDR_MEM_BASEADDR
+#define INTC_DEVICE_ID			XPAR_SCUGIC_SINGLE_DEVICE_ID
+#define GPIO_0_DEVICE_ID		XPAR_PS7_GPIO_0_DEVICE_ID
+
+//#define FREQ_CTRL_DEVICE_ID		XPAR_AXI_9731_FREQ_CTRL_DEVICE_ID
+//#define GAIN_CTRL_DEVICE_ID		XPAR_AXI_9731_RX_GAIN_DEVICE_ID
+//#define ATTN_CTRL_DEVICE_ID		XPAR_AXI_9731_TX_ATTN_DEVICE_ID
+//
+//#define FREQ_CTRL_INTR_ID		XPAR_FABRIC_AXI_9731_FREQ_CTRL_IP2INTC_IRPT_INTR
+//#define GAIN_CTRL_INTR_ID		XPAR_FABRIC_AXI_9731_RX_GAIN_IP2INTC_IRPT_INTR
+//#define ATTN_CTRL_INTR_ID		XPAR_FABRIC_AXI_9731_TX_ATTN_IP2INTC_IRPT_INTR
+
+#define GPIO_OFFSET				54
+#define AD9528_CS				1
+#define AD9371_CS				2
+
+#define TX_FREQ_INTR_MASK		XGPIO_IR_CH1_MASK
+#define RX_FREQ_INTR_MASK		XGPIO_IR_CH2_MASK
+#define TX1_ATTN_INTR_MASK		XGPIO_IR_CH1_MASK
+#define TX2_ATTN_INTR_MASK		XGPIO_IR_CH2_MASK
+#define RX1_ATTN_INTR_MASK		XGPIO_IR_CH1_MASK
+#define RX2_ATTN_INTR_MASK		XGPIO_IR_CH2_MASK
+
+#define AXI_GPIO_BANK_1 1
+#define AXI_GPIO_BANK_2 2
+
+//#define DAC_GPIO_PLDDR_BYPASS	GPIO_OFFSET + 60
+#define AD9528_RESET_B			GPIO_OFFSET + 4
+#define AD9528_SYSREF_REQ		GPIO_OFFSET + 3
+#define AD9371_RESET_B			GPIO_OFFSET + 1
+
+#endif

datalink814_ge/src/hardware/platform_drivers.c

@@ -0,0 +1,497 @@
+/***************************************************************************//**
+ *   @file   platform_drivers.c
+ *   @brief  Implementation of Xilinx Platform Drivers.
+ *   @author DBogdan (dragos.bogdan@analog.com)
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <sleep.h>
+#include "platform_drivers.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Initialize the I2C communication peripheral.
+ * @param desc - The I2C descriptor.
+ * @param init_param - The structure that contains the I2C parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t i2c_init(struct i2c_desc **desc,
+		 const struct i2c_init_param *param)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (param->type) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by i2c_init().
+ * @param desc - The I2C descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t i2c_remove(struct i2c_desc *desc)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write data to a slave device.
+ * @param desc - The I2C descriptor.
+ * @param data - Buffer that stores the transmission data.
+ * @param bytes_number - Number of bytes to write.
+ * @param stop_bit - Stop condition control.
+ *                   Example: 0 - A stop condition will not be generated;
+ *                            1 - A stop condition will be generated.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t i2c_write(struct i2c_desc *desc,
+		  uint8_t *data,
+		  uint8_t bytes_number,
+		  uint8_t stop_bit)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (data) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (bytes_number) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (stop_bit) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Read data from a slave device.
+ * @param desc - The I2C descriptor.
+ * @param data - Buffer that will store the received data.
+ * @param bytes_number - Number of bytes to read.
+ * @param stop_bit - Stop condition control.
+ *                   Example: 0 - A stop condition will not be generated;
+ *                            1 - A stop condition will be generated.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t i2c_read(struct i2c_desc *desc,
+		 uint8_t *data,
+		 uint8_t bytes_number,
+		 uint8_t stop_bit)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (data) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (bytes_number) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (stop_bit) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initialize the SPI communication peripheral.
+ * @param desc - The SPI descriptor.
+ * @param init_param - The structure that contains the SPI parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_init(struct spi_desc **desc,
+		 const struct spi_init_param *param)
+{
+	spi_desc *descriptor;
+	int32_t ret;
+
+	descriptor = (struct spi_desc *) calloc(1, sizeof(*descriptor));
+	if (!descriptor)
+		return FAILURE;
+
+	descriptor->mode = param->mode;
+	descriptor->chip_select = param->chip_select;
+	descriptor->flags = param->flags;
+
+#ifdef _XPARAMETERS_PS_H_
+	descriptor->config = XSpiPs_LookupConfig(param->id);
+	if (descriptor->config == NULL)
+		goto error;
+
+	ret = XSpiPs_CfgInitialize(&descriptor->instance,
+				   descriptor->config, descriptor->config->BaseAddress);
+	if (ret != 0)
+		goto error;
+
+	XSpiPs_SetOptions(&descriptor->instance,
+			  XSPIPS_MASTER_OPTION |
+			  ((descriptor->flags & SPI_CS_DECODE) ?
+			   XSPIPS_DECODE_SSELECT_OPTION : 0) |
+			  XSPIPS_FORCE_SSELECT_OPTION |
+			  ((descriptor->mode & SPI_CPOL) ?
+			   XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) |
+			  ((descriptor->mode & SPI_CPHA) ?
+			   XSPIPS_CLK_PHASE_1_OPTION : 0));
+
+	XSpiPs_SetClkPrescaler(&descriptor->instance,
+			       XSPIPS_CLK_PRESCALE_64);
+
+	XSpiPs_SetSlaveSelect(&descriptor->instance, 0xf);
+#else
+	ret = XSpi_Initialize(&descriptor->instance, param->id);
+	if (ret != 0)
+		goto error;
+
+	XSpi_SetOptions(&descriptor->instance,
+			XSP_MASTER_OPTION |
+			((descriptor->mode & SPI_CPOL) ?
+			 XSP_CLK_ACTIVE_LOW_OPTION : 0) |
+			((descriptor->mode & SPI_CPHA) ?
+			 XSP_CLK_PHASE_1_OPTION : 0));
+
+	XSpi_Start(&descriptor->instance);
+
+	XSpi_IntrGlobalDisable(&descriptor->instance);
+#endif
+
+	*desc = descriptor;
+
+	return SUCCESS;
+
+error:
+	free(descriptor);
+
+	return FAILURE;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_remove(struct spi_desc *desc)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write and read data to/from SPI.
+ * @param desc - The SPI descriptor.
+ * @param data - The buffer with the transmitted/received data.
+ * @param bytes_number - Number of bytes to write/read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+
+int32_t spi_write_and_read(struct spi_desc *desc,
+			   uint8_t *data,
+			   uint8_t bytes_number)
+{
+#ifdef _XPARAMETERS_PS_H_
+	XSpiPs_SetOptions(&desc->instance,
+			  XSPIPS_MASTER_OPTION |
+			  ((desc->flags & SPI_CS_DECODE) ?
+			   XSPIPS_DECODE_SSELECT_OPTION : 0) |
+			  XSPIPS_FORCE_SSELECT_OPTION |
+			  ((desc->mode & SPI_CPOL) ?
+			   XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) |
+			  ((desc->mode & SPI_CPHA) ?
+			   XSPIPS_CLK_PHASE_1_OPTION : 0));
+
+	XSpiPs_SetSlaveSelect(&desc->instance, desc->chip_select);
+			     // 0xf & ~desc->chip_select);
+	XSpiPs_PolledTransfer(&desc->instance,
+			      data, data, bytes_number);
+#else
+	XSpi_SetOptions(&desc->instance,
+			XSP_MASTER_OPTION |
+			((desc->mode & SPI_CPOL) ?
+			 XSP_CLK_ACTIVE_LOW_OPTION : 0) |
+			((desc->mode & SPI_CPHA) ?
+			 XSP_CLK_PHASE_1_OPTION : 0));
+
+	XSpi_SetSlaveSelect(&desc->instance,
+			    desc->chip_select);
+
+	XSpi_Transfer(&desc->instance,
+		      data, data, bytes_number);
+#endif
+	return 0;
+}
+
+/**
+ * @brief Obtain the GPIO decriptor.
+ * @param desc - The GPIO descriptor.
+ * @param gpio_number - The number of the GPIO.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get(struct gpio_desc **desc,
+		 uint8_t gpio_number)
+{
+	gpio_desc *descriptor;
+	int32_t ret;
+
+	descriptor = (struct gpio_desc *) malloc(sizeof(*descriptor));
+	if (!descriptor)
+		return FAILURE;
+
+#ifdef _XPARAMETERS_PS_H_
+	descriptor->config = XGpioPs_LookupConfig(0);
+	if (descriptor->config == NULL)
+		goto error;
+
+	ret = XGpioPs_CfgInitialize(&descriptor->instance,
+				    descriptor->config, descriptor->config->BaseAddr);
+	if (ret != 0)
+		goto error;
+#else
+	ret = XGpio_Initialize(&descriptor->instance, 0);
+	if (ret != 0)
+		goto error;
+#endif
+
+	descriptor->number = gpio_number;
+
+	*desc = descriptor;
+
+	return SUCCESS;
+
+error:
+	free(descriptor);
+
+	return FAILURE;
+}
+
+/**
+ * @brief Free the resources allocated by gpio_get().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_remove(struct gpio_desc *desc)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Enable the input direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_input(struct gpio_desc *desc)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Enable the output direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+			      uint8_t value)
+{
+#ifdef _XPARAMETERS_PS_H_
+	XGpioPs_SetDirectionPin(&desc->instance, desc->number, 1);
+
+	XGpioPs_SetOutputEnablePin(&desc->instance, desc->number, 1);
+
+	XGpioPs_WritePin(&desc->instance, desc->number, value);
+#else
+	uint8_t pin = desc->number;
+	uint8_t channel;
+	uint32_t reg_val;
+
+	if (pin >= 32) {
+		channel = 2;
+		pin -= 32;
+	} else
+		channel = 1;
+
+	reg_val = XGpio_GetDataDirection(&desc->instance, channel);
+	reg_val &= ~(1 << pin);
+	XGpio_SetDataDirection(&desc->instance, channel, reg_val);
+
+	reg_val = XGpio_DiscreteRead(&desc->instance, channel);
+	if(value)
+		reg_val |= (1 << pin);
+	else
+		reg_val &= ~(1 << pin);
+	XGpio_DiscreteWrite(&desc->instance, channel, reg_val);
+#endif
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Get the direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param direction - The direction.
+ *                    Example: GPIO_OUT
+ *                             GPIO_IN
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+			   uint8_t *direction)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (direction) {
+		// Unused variable - fix compiler warning
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Set the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_set_value(struct gpio_desc *desc,
+		       uint8_t value)
+{
+#ifdef _XPARAMETERS_PS_H_
+	XGpioPs_WritePin(&desc->instance, desc->number, value);
+#else
+	uint8_t pin = desc->number;
+	uint8_t channel;
+	uint32_t reg_val;
+
+	if (pin >= 32) {
+		channel = 2;
+		pin -= 32;
+	} else
+		channel = 1;
+
+	reg_val = XGpio_DiscreteRead(&desc->instance, channel);
+	if(value)
+		reg_val |= (1 << pin);
+	else
+		reg_val &= ~(1 << pin);
+	XGpio_DiscreteWrite(&desc->instance, channel, reg_val);
+#endif
+
+	return 0;
+}
+
+/**
+ * @brief Get the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_value(struct gpio_desc *desc,
+		       uint8_t *value)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (value) {
+		// Unused variable - fix compiler warning
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Generate microseconds delay.
+ * @param usecs - Delay in microseconds.
+ * @return None.
+ */
+void udelay(uint32_t usecs)
+{
+	usleep(usecs);
+}
+
+/**
+ * @brief Generate miliseconds delay.
+ * @param msecs - Delay in miliseconds.
+ * @return None.
+ */
+void mdelay(uint32_t msecs)
+{
+#ifdef _XPARAMETERS_PS_H_
+	usleep(msecs * 1000);
+#else
+	usleep(msecs * 50);	// FIXME
+#endif
+}

datalink814_ge/src/hardware/platform_drivers.h

@@ -0,0 +1,223 @@
+/***************************************************************************//**
+ *   @file   platform_drivers.h
+ *   @brief  Header file of Xilinx Platform Drivers.
+ *   @author DBogdan (dragos.bogdan@analog.com)
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef PLATFORM_DRIVERS_H_
+#define PLATFORM_DRIVERS_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include <xparameters.h>
+#ifdef _XPARAMETERS_PS_H_
+#include <xspips.h>
+#include <xgpiops.h>
+#else
+#include <xspi.h>
+#include <xgpio.h>
+#endif
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define SUCCESS		0
+#define FAILURE		-1
+
+#define	SPI_CPHA	0x01
+#define	SPI_CPOL	0x02
+
+#define SPI_CS_DECODE	0x01
+#define SPI_CS_DECODE_DISABLE	0x00
+
+#define GPIO_OUT	0x01
+#define GPIO_IN		0x00
+
+#define GPIO_HIGH	0x01
+#define GPIO_LOW	0x00
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+typedef enum i2c_type {
+	XILINX_I2C
+} i2c_type;
+
+typedef struct i2c_init_param {
+	enum i2c_type	type;
+	uint32_t	id;
+	uint32_t	max_speed_hz;
+	uint8_t		slave_address;
+} i2c_init_param;
+
+typedef struct i2c_desc {
+	enum i2c_type	type;
+	uint32_t	id;
+	uint32_t	max_speed_hz;
+	uint8_t		slave_address;
+} i2c_desc;
+
+typedef enum spi_type {
+	XILINX_SPI
+} spi_type;
+
+/**
+ * @enum spi_mode
+ * @brief SPI configuration for clock phase and polarity.
+ */
+typedef enum spi_mode {
+	/** Data on rising, shift out on falling */
+	SPI_MODE_0 = (0 | 0),
+	/** Data on falling, shift out on rising */
+	SPI_MODE_1 = (0 | SPI_CPHA),
+	/** Data on falling, shift out on rising */
+	SPI_MODE_2 = (SPI_CPOL | 0),
+	/** Data on rising, shift out on falling */
+	SPI_MODE_3 = (SPI_CPOL | SPI_CPHA)
+} spi_mode;
+
+typedef struct spi_init_param {
+	enum spi_type	type;
+	uint32_t	id;
+	uint32_t	max_speed_hz;
+	enum spi_mode	mode;
+	uint8_t		chip_select;
+	uint32_t	flags;
+} spi_init_param;
+
+typedef struct spi_desc {
+	enum spi_type	type;
+	uint32_t		id;
+	uint32_t		max_speed_hz;
+	enum spi_mode	mode;
+	uint8_t			chip_select;
+	uint32_t		flags;
+#ifdef _XPARAMETERS_PS_H_
+	XSpiPs_Config	*config;
+	XSpiPs			instance;
+#else
+	XSpi			instance;
+#endif
+} spi_desc;
+
+typedef enum gpio_type {
+	XILINX_GPIO
+} gpio_type;
+
+typedef struct gpio_desc {
+	enum gpio_type	type;
+	uint32_t		id;
+	uint8_t			number;
+#ifdef _XPARAMETERS_PS_H_
+	XGpioPs_Config	*config;
+	XGpioPs			instance;
+#else
+	XGpio			instance;
+#endif
+} gpio_desc;
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Initialize the I2C communication peripheral. */
+int32_t i2c_init(struct i2c_desc **desc,
+		 const struct i2c_init_param *param);
+
+/* Free the resources allocated by i2c_init(). */
+int32_t i2c_remove(struct i2c_desc *desc);
+
+/* Write data to a slave device. */
+int32_t i2c_write(struct i2c_desc *desc,
+		  uint8_t *data,
+		  uint8_t bytes_number,
+		  uint8_t stop_bit);
+
+/* Read data from a slave device. */
+int32_t i2c_read(struct i2c_desc *desc,
+		 uint8_t *data,
+		 uint8_t bytes_number,
+		 uint8_t stop_bit);
+
+/* Initialize the SPI communication peripheral. */
+int32_t spi_init(struct spi_desc **desc,
+		 const struct spi_init_param *param);
+
+/* Free the resources allocated by spi_init() */
+int32_t spi_remove(struct spi_desc *desc);
+
+/* Write and read data to/from SPI. */
+int32_t spi_write_and_read(struct spi_desc *desc,
+			   uint8_t *data,
+			   uint8_t bytes_number);
+
+/* Obtain the GPIO decriptor. */
+int32_t gpio_get(struct gpio_desc **desc,
+		 uint8_t gpio_number);
+
+/* Free the resources allocated by gpio_get() */
+int32_t gpio_remove(struct gpio_desc *desc);
+
+/* Enable the input direction of the specified GPIO. */
+int32_t gpio_direction_input(struct gpio_desc *desc);
+
+/* Enable the output direction of the specified GPIO. */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+			      uint8_t value);
+
+/* Get the direction of the specified GPIO. */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+			   uint8_t *direction);
+
+/* Set the value of the specified GPIO. */
+int32_t gpio_set_value(struct gpio_desc *desc,
+		       uint8_t value);
+
+/* Get the value of the specified GPIO. */
+int32_t gpio_get_value(struct gpio_desc *desc,
+		       uint8_t *value);
+
+/* Generate microseconds delay. */
+void udelay(uint32_t usecs);
+
+/* Generate miliseconds delay. */
+void mdelay(uint32_t msecs);
+
+#endif // PLATFORM_DRIVERS_H_

datalink814_ge/src/linklayer/framing.c

@@ -0,0 +1,327 @@
+/*****************************************************************************/
+/**
+ * Description:  Functions for framing operations.
+ * 
+ * Date: 2022-07-16 14:17
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-16 17:11
+ * Revisions: Rev x.x
+ * History: 
+ * [YYYY-MM-DD]: Description of modification.
+ * 
+ * Copyright(c) 2022 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include <stdint.h>
+#include "linklayer814.h"
+#include "msg_def.h"
+#include "../error.h"
+#include "../common.h"
+#include "../bit_array/bit_array.h"
+
+/************************** Constant Definitions *****************************/
+// Definition of each slot content
+L2_MSG_TYPE intraBmFrameMsgs[1] = {
+		L2_MSG_BM
+};
+L2_MSG_TYPE intraW2AcqFrameMsgs[6] = {
+		L2_MSG_SCAN_INIT,
+		L2_MSG_SCAN_CONT_1,
+		L2_MSG_SCAN_CONT_2,
+		L2_MSG_SCAN_CONT_3,
+		L2_MSG_SCAN_CONT_4,
+		L2_MSG_SCAN_CONT_5
+};
+
+L2_MSG_TYPE intraMgmtFrameMsgs[6] = {
+		L2_MSG_TK_INIT,
+		L2_MSG_TK_EXTD,
+		L2_MSG_TK_CONT_1,
+		L2_MSG_TK_CONT_2,
+		L2_MSG_TK_CONT_3,
+		L2_MSG_NQT_INIT
+};
+
+L2_MSG_TYPE taFrameMsgs[4] = {
+		L2_MSG_TA_INIT,
+		L2_MSG_TA_EXTD,
+		L2_MSG_TA_CONT_1,
+		L2_MSG_TA_CONT_2
+};
+
+L2_MSG_TYPE interSvcFrameMsgs[2] = {
+		L2_MSG_LINK_INIT,
+		L2_MSG_LINK_CONT_1
+};
+
+L2_MSG_TYPE rttReqFrameMsgs[3] = {
+		L2_MSG_RTT_REQ_INIT,
+		L2_MSG_RTT_REQ_EXTD,
+		L2_MSG_RTT_REQ_CONT
+};
+
+L2_MSG_TYPE rttRspFrameMsgs[3] = {
+		L2_MSG_RTT_RSP_INIT,
+		L2_MSG_RTT_RSP_EXTD,
+		L2_MSG_RTT_RSP_CONT
+};
+
+
+/*****************************************************************************/
+/**
+ * @brief   Insert a data chunk to a bit array.
+ *
+ * @param   bitarr	pointer to target bit array.
+ *          offset	offset of insert start position.
+ *          numBit	number of insert bits
+ *          chunk	64 bit data chunk, contains the data should be stored
+ *          		in LSB style.
+ *
+ * @return	FAILURE	insert operation exceed bit array size.
+ * 			SUCCESS
+ *
+ ******************************************************************************/
+void FrameInsertChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t chunk){
+	ASSERT(bitarr != NULL);
+	ASSERT(bitarr->num_of_bits >= offset+numBit && numBit <= 64);
+#ifdef CHUNK_FILL_STYLE_XJY
+	int32_t bitRmn = numBit;
+	uint64_t dataWr = 0;
+	uint32_t bitOff = 0;
+	uint32_t byteOff = 0;
+	uint32_t bitWr = 0;
+	uint32_t bitWrCnt = 0;
+	while (bitRmn > 0){
+		bitOff = offset%8;
+		byteOff = offset/8;
+		bitWr = (bitRmn > (8-bitOff)) ? (8-bitOff) : bitRmn;
+		dataWr = chunk>>(numBit-(bitWr + bitWrCnt));
+		bit_array_set_wordn(bitarr, byteOff*8 + (8-bitOff-bitWr), dataWr, bitWr);
+		bitWrCnt += bitWr;
+		bitRmn -= bitWr;
+		offset += bitWr;
+	}
+#else
+	bit_array_set_wordn(bitarr, offset, chunk, numBit);
+#endif
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get a data chunk to a bit array.
+ *
+ * @param   bitarr	pointer to target bit array.
+ *          offset	offset of data chunk start position.
+ *          numBit	number of data chunk
+ *          chunk	pointer to a 64 bit data chunk container, data will be stored
+ *          		in LSB style.
+ *
+ * @return	FAILURE	 read operation exceed bit array size.
+ * 			SUCCESS
+ *
+ ******************************************************************************/
+void FrameGetChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t* chunk){
+	ASSERT(bitarr != NULL);
+	ASSERT(bitarr->num_of_bits >= offset+numBit && numBit <= 64);
+
+#ifdef CHUNK_FILL_STYLE_XJY
+	int32_t bitRmn = numBit;
+	uint64_t dataRd = 0;
+	uint32_t bitOff = offset%8;
+	uint32_t byteOff = offset/8;
+	uint32_t bitRd = (bitRmn > (8-bitOff)) ? (8-bitOff) : bitRmn;
+	uint32_t bitRdCnt = 0;
+	while (bitRmn > 0){
+		dataRd |= bit_array_get_wordn(bitarr, byteOff*8 + (8-bitOff-bitRd), bitRd);
+		bitRdCnt += bitRd;
+		bitRmn -= bitRd;
+		offset += bitRd;
+		bitOff = offset%8;
+		byteOff = offset/8;
+		bitRd = (bitRmn > (8-bitOff)) ? (8-bitOff) : bitRmn;
+		dataRd = dataRd<<bitRd;
+	}
+	*chunk = dataRd;
+	return SUCCESS;
+#else
+	*chunk = bit_array_get_wordn(bitarr, offset, numBit);
+#endif
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Generate crc of specified data.
+ *
+ * @param   dataBuff	pointer to data buffer.
+ *          dataLen		length of specified data.
+ *          crcType		type of crc
+ *          crc			a pointer to 32 bit crc container.
+ *
+ * @return	FAILURE	crc type not support.
+ * 			SUCCESS
+ *
+ ******************************************************************************/
+static int32_t L2_CrcGen(uint8_t* dataBuff, uint32_t dataLen, L2_CRC_TYPE crcType, uint32_t* crc){
+//	ASSERT(dataBuff != NULL);
+	int32_t Status = SUCCESS;
+	uint32_t crcVal = 0;
+	switch (crcType){
+	case L2_CRC16_1021:
+		Status = crc16_gen(dataBuff, dataLen, 0x1021, (uint16_t*)&crcVal);
+		break;
+	case L2_CRC16_8005:
+		Status = crc16_gen(dataBuff, dataLen, 0x8005, (uint16_t*)&crcVal);
+		break;
+	case L2_CRC8_31:
+		Status = crc8_gen(dataBuff, dataLen, 0x31, (uint8_t*)&crcVal);
+		break;
+	default:
+		Status = EPARAM;
+		break;
+	}
+	if(Status == SUCCESS){
+		*crc = crcVal;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Append a crc of specified data, to a specified position.
+ *
+ * @param   dataBuff	pointer to data buffer.
+ *          dataLen		length of specified data.
+ *          crcPos		position of crc insert position
+ *          crcType		type of crc
+ *
+ * @return	FAILURE	crc type not support.
+ * 			SUCCESS
+ *
+ ******************************************************************************/
+int32_t L2_CrcAppend(uint8_t* dataBuff, uint32_t dataLen, uint32_t crcPos, L2_CRC_TYPE crcType){
+//	ASSERT(dataBuff != NULL);
+	int32_t Status = SUCCESS;
+	uint32_t crcVal = 0;
+	uint8_t* crcPtr = dataBuff+crcPos;
+	Status = L2_CrcGen(dataBuff,dataLen, crcType, &crcVal);
+	if(Status != SUCCESS){
+		return Status;
+	}
+#ifdef CHUNK_FILL_STYLE_XJY
+	switch (crcType){
+	case L2_CRC16_1021:
+		*crcPtr = (uint8_t)(crcVal>>8);
+		*(crcPtr+1) = (uint8_t)(crcVal);
+		break;
+	case L2_CRC16_8005:
+		*crcPtr = (uint8_t)(crcVal>>8);
+		*(crcPtr+1) = (uint8_t)(crcVal);
+		break;
+	case L2_CRC8_31:
+		*crcPtr = (uint8_t)crcVal;
+		break;
+	default:
+		Status = EPARAM;
+		break;
+	}
+#else
+	switch (crcType){
+	case L2_CRC16_1021:
+		*(crcPtr+1) = (uint8_t)(crcVal>>8);
+		*crcPtr = (uint8_t)(crcVal);
+		break;
+	case L2_CRC16_8005:
+		*(crcPtr+1) = (uint8_t)(crcVal>>8);
+		*crcPtr = (uint8_t)(crcVal);
+		break;
+	case L2_CRC8_31:
+		*crcPtr = (uint8_t)crcVal;
+		break;
+	default:
+		Status = EPARAM;
+		break;
+	}
+#endif
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Check data validation by crc.
+ *
+ * @param   dataBuff	pointer to data buffer.
+ *          dataLen		length of specified data.
+ *          crcPos		position of crc insert position
+ *          crcType		type of crc
+ *
+ * @return	FAILURE	crc type not support.
+ * 			SUCCESS
+ *
+ ******************************************************************************/
+bool L2_CrcCheck(uint8_t* dataBuff, uint32_t dataLen, uint32_t crcPos, L2_CRC_TYPE crcType){
+	ASSERT(dataBuff != NULL);
+
+	int32_t Status = SUCCESS;
+	uint32_t crcVal = 0;
+	uint32_t crcComp = 0;
+	uint8_t* crcPtr = dataBuff+crcPos;
+	Status = L2_CrcGen(dataBuff,dataLen, crcType, &crcVal);
+	if(Status != SUCCESS){
+		return false;
+	}
+#ifdef CHUNK_FILL_STYLE_XJY
+	switch (crcType){
+	case L2_CRC16_1021:
+		crcComp = ((uint32_t)(*crcPtr)) << 8;
+		crcComp |= (uint32_t)(*(crcPtr+1));
+		break;
+	case L2_CRC16_8005:
+		crcComp = ((uint32_t)(*crcPtr)) << 8;
+		crcComp |= (uint32_t)(*(crcPtr+1));
+		break;
+	case L2_CRC8_31:
+		crcComp = (uint32_t)(*crcPtr);
+		break;
+	default:
+		Status = EPARAM;
+		break;
+	}
+#else
+	switch (crcType){
+	case L2_CRC16_1021:
+		crcComp = ((uint32_t)(*(crcPtr+1))) << 8;
+		crcComp |= (uint32_t)(*crcPtr);
+		break;
+	case L2_CRC16_8005:
+		crcComp = ((uint32_t)(*(crcPtr+1))) << 8;
+		crcComp |= (uint32_t)(*crcPtr);
+		break;
+	case L2_CRC8_31:
+		crcComp = (uint32_t)(*crcPtr);
+		break;
+	default:
+		Status = EPARAM;
+		break;
+	}
+#endif
+	if(Status == SUCCESS){
+//		if ( crcVal == 0 )
+//		{
+//			return false ;
+//		}
+//		else
+		if(crcComp == crcVal){
+			return true;
+		}
+		else{
+			return false;
+		}
+	}
+	else{
+		return false;
+	}
+
+}

datalink814_ge/src/linklayer/geometry/coord.c

@@ -0,0 +1,195 @@
+//
+// Copyright (C) 2020 OpenSim Ltd.
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+#include <math.h>
+#include "coord.h"
+
+
+const COORD COORD_NIL = {NAN, NAN, NAN};
+const COORD COORD_ZERO = {0.0, 0.0, 0.0};
+const COORD COORD_ONE = {1.0, 1.0, 1.0};
+const COORD COORD_X_AXIS = {1.0, 0.0, 0.0};
+const COORD COORD_Y_AXIS = {0.0, 1.0, 0.0};
+const COORD COORD_Z_AXIS = {0.0, 0.0, 1.0};
+
+ /** @brief Subtracts two coordinate vectors. */
+COORD Coord_Sub(COORD a, COORD b) {
+    COORD ret;
+    ret.x = a.x - b.x;
+    ret.y = a.y - b.y;
+    ret.z = a.z - b.z;
+    return ret;
+}
+
+/** @brief Adds two coordinate vectors. */
+COORD Coord_Add(COORD a, COORD b) {
+    COORD ret;
+    ret.x = a.x + b.x;
+    ret.y = a.y + b.y;
+    ret.z = a.z + b.z;
+    return ret;
+}
+
+/** @brief Multiplies a coordinate vector by a real number. */
+void Coord_ScalarMult(COORD *a, double t) {
+    a->x *= t;
+    a->y *= t;
+    a->z *= t;
+}
+
+/** @brief Multiplies a coordinate vector by a real number. */
+COORD Coord_GetScalarMult(COORD a, double t) {
+    COORD ret;
+    ret.x = a.x * t;
+    ret.y = a.y * t;
+    ret.z = a.z * t;
+    return ret;
+}
+
+/** @brief Divides a coordinate vector by a real number. */
+void Coord_ScalarDiv(COORD *a, double t) {
+    a->x /= t;
+    a->y /= t;
+    a->z /= t;
+}
+
+/** @brief Divides a coordinate vector by a real number. */
+COORD Coord_GetScalarDiv(COORD a, double t) {
+    COORD ret;
+    ret.x = a.x / t;
+    ret.y = a.y / t;
+    ret.z = a.z / t;
+    return ret;
+}
+
+/** @brief Dot product. */
+inline double Coord_Dot(COORD a, COORD b) {
+    return (a.x * b.x + a.y * b.y + a.z * b.z);
+}
+
+/** @brief Cross product. */
+COORD Coord_Cross(COORD a, COORD b) {
+    COORD ret;
+    ret.x = a.y * b.z - a.z * b.y;
+    ret.y = a.z * b.x - a.x * b.z;
+    ret.z = a.x * b.y - a.y * b.x;
+    return ret;
+}
+
+/** @brief Multiplies two coordinate vector in elementwise. */
+COORD Coord_ElementwiseMult(COORD a, COORD b) {
+    COORD ret;
+    ret.x = a.x * b.x;
+    ret.y = a.y * b.y;
+    ret.z = a.z * b.z;
+    return ret;
+}
+
+/** @brief Divides two coordinate vector in elementwise. */
+COORD Coord_ElementwiseDiv(COORD a, COORD b) {
+    COORD ret;
+    ret.x = a.x / b.x;
+    ret.y = a.y / b.y;
+    ret.z = a.z / b.z;
+    return ret;
+}
+
+/** @brief Calculate a coordinate vector length^2 (omits calling square root). */
+double Coord_SquareLength(COORD a) {
+    return (a.x*a.x + a.y*a.y + a.z*a.z);
+}
+
+/** @brief Calculate a coordinate vector length. */
+double Coord_Length(COORD a) {
+    return sqrt(Coord_SquareLength(a));
+}
+
+/** @brief Calculate two coordinates' distance. */
+double Coord_Distance(COORD a, COORD b) {
+    return Coord_Length(Coord_Sub(a, b));
+}
+
+/** @brief Normalize coordinate vector. */
+void Coord_Normalize(COORD *a) {
+    Coord_ScalarDiv(a, Coord_Length(*a));
+}
+
+/** @brief Normalize coordinate vector. */
+COORD Coord_GetNormalized(COORD a) {
+    Coord_Normalize(&a);
+    return a;
+}
+
+/** @brief Returns the angle between the two vectors. */
+double Coord_Angle(COORD a, COORD b) {
+    Coord_Normalize(&a);
+    Coord_Normalize(&b);
+    return acos(Coord_Dot(a, b));
+}
+
+
+// Additional Coordinates convert
+// TODO: Confirm correctness
+/** @brief Convert coordinate from Launch coordinate system to ECEF. */
+COORD Coord_Launch2Ecef(COORD o, COORD p, double A, double B, double lambda) {
+    COORD ret;
+    double sinA,cosA, sinB, cosB, sinL, cosL;
+    double S11, S12, S13, S21, S22, S23, S31, S32, S33;
+    sinA = sin(A);
+    cosA = cos(A);
+    sinB = sin(B);
+    cosB = cos(B);
+    sinL = sin(lambda);
+    cosL = cos(lambda);
+
+    S11 = -sinA*sinL - cosA*sinB*cosL;
+    S12 = cosB*cosL;
+    S13 = -cosA*sinL + sinA*sinB*cosL;
+
+    S21 = sinA*cosL - cosA*sinB*sinL;
+    S22 = cosB*sinL;
+    S23 = cosA*cosL + sinA*sinB*sinL;
+
+    S31 = cosA*cosB;
+    S32 = sinB;
+    S33 = -sinA*cosB;
+
+    ret.x = p.x*(S11 + S21 + S31) + o.x;
+    ret.y = p.y*(S12 + S22 + S32) + o.y;
+    ret.z = p.z*(S13 + S23 + S33) + o.z;
+
+    return ret;
+}
+
+/** @brief Convert coordinate from launch coordinate system to Inertia coordinate system. */
+COORD Coord_Launch2Inertia(COORD o, COORD p, double A, double B, double we, double t) {
+    COORD ret;
+    double OmgX, OmgY, OmgZ, sinwet, coswet;
+    double M11, M12, M13, M21, M22, M23, M31, M32, M33;
+    OmgX = cos(A)*cos(B);
+    OmgY = sin(B);
+    OmgZ = -sin(A)*cos(B);
+    sinwet = sin(we*t);
+    coswet = cos(we*t);
+
+    M11 = 1 - (1 - OmgX*OmgX)*(1-coswet);
+    M12 = OmgX*OmgY*(1-coswet) + OmgZ*sinwet;
+    M13 = OmgX*OmgZ*(1-coswet)-OmgY*sinwet;
+
+    M21 = OmgY*OmgX*(1-coswet) - OmgZ*sinwet;
+    M22 = 1-(1-OmgY*OmgY)*(1-coswet);
+    M23 = OmgY*OmgZ*(1-coswet) + OmgX*sinwet;
+
+    M31 = OmgZ*OmgX*(1-coswet) + OmgY*sinwet;
+    M32 = OmgZ*OmgY*(1-coswet) - OmgX*sinwet;
+    M33 = 1 - (1-OmgZ*OmgZ)*(1-coswet);
+
+    ret.x = p.x*(M11 + M21 + M31) + o.x;
+    ret.y = p.y*(M12 + M22 + M32) + o.y;
+    ret.z = p.z*(M13 + M23 + M33) + o.z;
+
+    return ret;
+}

datalink814_ge/src/linklayer/geometry/coord.h

@@ -0,0 +1,81 @@
+//
+// Copyright (C) 2020 OpenSim Ltd.
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+#ifndef _COORD_H
+#define _COORD_H
+
+/**
+ * @brief Structure for storing 3D coordinates.
+ *
+ * Some comparison and basic arithmetic operators are implemented.
+ *
+ * @ingroup utils
+ */
+
+typedef struct{
+    double x;
+    double y;
+    double z;
+} COORD;
+
+extern const COORD COORD_NIL;
+extern const COORD COORD_ZERO;
+extern const COORD COORD_ONE;
+extern const COORD COORD_X_AXIS;
+extern const COORD COORD_Y_AXIS;
+extern const COORD COORD_Z_AXIS;
+
+/** @brief Subtracts two coordinate vectors. */
+COORD Coord_Sub(COORD a, COORD b);
+
+/** @brief Adds two coordinate vectors. */
+COORD Coord_Add(COORD a, COORD b);
+
+/** @brief Multiplies a coordinate vector by a real number. */
+void Coord_ScalarMult(COORD *a, double t);
+
+/** @brief Multiplies a coordinate vector by a real number. */
+COORD Coord_GetScalarMult(COORD a, double t);
+
+/** @brief Divides a coordinate vector by a real number. */
+void Coord_ScalarDiv(COORD *a, double t);
+
+/** @brief Divides a coordinate vector by a real number. */
+COORD Coord_GetScalarDiv(COORD a, double t);
+
+/** @brief Dot product. */
+double Coord_Dot(COORD a, COORD b);
+
+/** @brief Cross product. */
+COORD Coord_Cross(COORD a, COORD b);
+
+/** @brief Multiplies two coordinate vector in elementwise. */
+COORD Coord_ElementwiseMult(COORD a, COORD b);
+
+/** @brief Divides two coordinate vector in elementwise. */
+COORD Coord_ElementwiseDiv(COORD a, COORD b);
+
+/** @brief Calculate a coordinate vector length^2 (omits calling square root). */
+double Coord_SquareLength(COORD a);
+
+/** @brief Calculate a coordinate vector length. */
+double Coord_Length(COORD a);
+
+/** @brief Calculate two coordinates' distance. */
+double Coord_Distance(COORD a, COORD b);
+
+/** @brief Normalize coordinate vector. */
+void Coord_Normalize(COORD *a);
+
+/** @brief Normalize coordinate vector. */
+COORD Coord_GetNormalized(COORD a);
+
+/** @brief Returns the angle between the two vectors. */
+double Coord_Angle(COORD a, COORD b);
+
+#endif
+

datalink814_ge/src/linklayer/geometry/eulerangles.c

@@ -0,0 +1,57 @@
+//
+// Copyright (C) 2020 OpenSim Ltd.
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+#include <math.h>
+#include "eulerangles.h"
+
+
+const EULERANGLES EULERANGLES_NIL = {NAN, NAN, NAN};
+const EULERANGLES EULERANGLES_ZERO = {0.0, 0.0, 0.0};
+
+
+/** @brief Add two EulerAngles. */
+EULERANGLES EulerAngles_Add(EULERANGLES e1, EULERANGLES e2) {
+    EULERANGLES ret;
+    ret.alpha = e1.alpha + e2.alpha;
+    ret.beta  = e1.beta  + e2.beta ;
+    ret.gamma = e1.gamma + e2.gamma;
+    return ret;
+}
+
+/** @brief Subtracts two EulerAngles. */
+EULERANGLES EulerAngles_Sub(EULERANGLES e1, EULERANGLES e2) {
+    EULERANGLES ret;
+    ret.alpha = e1.alpha - e2.alpha;
+    ret.beta  = e1.beta  - e2.beta ;
+    ret.gamma = e1.gamma - e2.gamma;
+    return ret;
+}
+
+/** @brief Multiplies EulerAngles by a real number. */
+void EulerAngles_ScalarMult(EULERANGLES *e, double f) {
+    e->alpha *= f;
+    e->beta  *= f;
+    e->gamma *= f;
+}
+
+/** @brief Multiplies EulerAngles by a real number. */
+EULERANGLES EulerAngles_GetScalarMult(EULERANGLES e, double f) {
+    EulerAngles_ScalarMult(&e, f);
+    return e;
+}
+
+/** @brief Normalize EulerAngles. */
+void EulerAngles_Normalize(EULERANGLES *e) {
+    e->alpha = fmod(e->alpha, 2*EUL_PI);
+    e->beta  = fmod(e->beta , 2*EUL_PI);
+    e->gamma = fmod(e->gamma, 2*EUL_PI);
+}
+
+/** @brief Normalize EulerAngles. */
+EULERANGLES EulerAngles_GetNormalize(EULERANGLES e) {
+    EulerAngles_Normalize(&e);
+    return e;
+}

datalink814_ge/src/linklayer/geometry/eulerangles.h

@@ -0,0 +1,54 @@
+#ifndef __EULERANGLES_H
+#define __EULERANGLES_H
+
+#define EUL_PI 3.14159265358979323846
+
+#define DEG2RAD(d)  ((EUL_PI/180.0)*d)
+#define RAD2DEG(r)  ((180.0/EUL_PI)*r)
+
+/**
+ * Orientations are represented by 3D double precision Tait-Bryan (Euler) tuples
+ * called EulerAngles. The angles are in Z, Y', X" order that is often called
+ * intrinsic rotations, they are measured in radians. The default (unrotated)
+ * orientation is along the X axis. Conceptually, the Z axis rotation is heading,
+ * the Y' axis rotation is descending (negative elevation), the X" axis rotation is bank.
+ * For example, positive rotation along the Z axis rotates X into Y (turns left), positive
+ * rotation along the Y axis rotates Z into X (leans forward), positive rotation
+ * along the X axis rotates Y into Z (leans right).
+ */
+typedef struct {
+  double alpha; // unit rad
+  double beta;  // unit rad
+  double gamma; // unit rad
+} EULERANGLES;
+
+typedef enum {
+	EULERANGLES_NONE = 0,
+	EULERANGLES_ZYX = 1,
+	EULERANGLES_ZYZ = 2,
+	EULERANGLES_XYZ = 3,
+}EULERANGLES_TYPE;
+
+extern const EULERANGLES EULERANGLES_ZERO;
+extern const EULERANGLES EULERANGLES_NIL;
+
+/** @brief Add two EulerAngles. */
+EULERANGLES EulerAngles_Add(EULERANGLES e1, EULERANGLES e2);
+
+/** @brief Subtracts two EulerAngles. */
+EULERANGLES EulerAngles_Sub(EULERANGLES e1, EULERANGLES e2);
+
+/** @brief Multiplies EulerAngles by a real number. */
+void EulerAngles_ScalarMult(EULERANGLES *e, double f);
+
+/** @brief Multiplies EulerAngles by a real number. */
+EULERANGLES EulerAngles_GetScalarMult(EULERANGLES e, double f);
+
+/** @brief Normalize EulerAngles. */
+void EulerAngles_Normalize(EULERANGLES *e);
+
+/** @brief Normalize EulerAngles. */
+EULERANGLES EulerAngles_GetNormalize(EULERANGLES e);
+
+#endif
+

datalink814_ge/src/linklayer/geometry/quaternion.c

@@ -0,0 +1,413 @@
+//
+// Copyright (C) 2014 OpenSim Ltd.
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+#include <math.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "coord.h"
+#include "eulerangles.h"
+#include "quaternion.h"
+
+typedef union {
+    float value;
+    uint32_t raw;
+} SOFT_FLOAT;
+
+typedef union {
+    double value;
+    uint64_t raw;
+} SOFT_DOUBLE;
+
+const SOFT_FLOAT EPS_FLOAT = {.raw = 0x34000000};
+const SOFT_DOUBLE EPS_DOUBLE = {.raw = 0x3CB0000000000000};
+
+const QUATERNION QUATERNION_IDENTITY = {1.0, 0.0, 0.0 ,0.0};
+const QUATERNION QUATERNION_NIL = {NAN, NAN, NAN, NAN};
+/** @brief Subtracts two quaternions. */
+QUATERNION Quaternion_Sub(QUATERNION q1, QUATERNION q2)  {
+    QUATERNION ret;
+    ret.s = q1.s - q2.s;
+    ret.i = q1.i - q2.i;
+    ret.j = q1.j - q2.j;
+    ret.k = q1.k - q2.k;
+    return ret;
+}
+
+/** @brief Adds two quaternions. */
+QUATERNION Quaternion_Add(QUATERNION q1, QUATERNION q2)  {
+    QUATERNION ret;
+    ret.s = q1.s + q2.s;
+    ret.i = q1.i + q2.i;
+    ret.j = q1.j + q2.j;
+    ret.k = q1.k + q2.k;
+    return ret;
+}
+
+/** @brief Multiplies a quaternion by a real number. */
+void Quaternion_ScalarMult(QUATERNION *q, double t) {
+    q->s *= t;
+    q->i *= t;
+    q->j *= t;
+    q->k *= t;
+}
+
+/** @brief Multiplies a quaternion by a real number. */
+QUATERNION Quaternion_GetScalarMult(QUATERNION a, double t) {
+    Quaternion_ScalarMult(&a, t);
+    return a;
+}
+
+/** @brief Divides a quaternion by a real number. */
+void Quaternion_ScalarDiv(QUATERNION *q, double t) {
+    q->s /= t;
+    q->i /= t;
+    q->j /= t;
+    q->k /= t;
+}
+
+/** @brief Divides a quaternion by a real number. */
+QUATERNION Quaternion_GetScalarDiv(QUATERNION q, double t) {
+    Quaternion_ScalarDiv(&q, t);
+    return q;
+}
+
+/** @brief Multiplies two quaternions. */
+QUATERNION Quaternion_Mult(QUATERNION q1, QUATERNION q2)  {
+    QUATERNION ret;
+    ret.s = q1.s * q2.s - (q1.i*q2.i + q1.j*q2.j + q1.k*q2.k);
+    ret.i = q1.j * q2.k - q1.k * q2.j + q1.s * q2.i + q1.i * q2.s;
+    ret.j = q1.k * q2.i - q1.i * q2.k + q1.s * q2.j + q1.j * q2.s;
+    ret.k = q1.i * q2.j - q1.j * q2.i + q1.s * q2.k + q1.k * q2.s;
+    return ret;
+}
+
+/** @brief Divides two quaternions. */
+QUATERNION Quaternion_Div(QUATERNION q1, QUATERNION q2)  {
+    Quaternion_Inverse(&q2);
+    return Quaternion_Mult(q1, q2);
+}
+
+/** @brief Dot product. */
+inline double Quaternion_Dot(QUATERNION q1, QUATERNION q2)  {
+    return (q1.s*q2.s + q1.i*q2.i + q1.j*q2.j + q1.k*q2.k);
+}
+
+/** @brief Calculate a quaternion length^2 (omits calling square root). */
+inline double Quaternion_SquareLength(QUATERNION q) {
+    return (q.s*q.s + q.i*q.i + q.j*q.j + q.k*q.k);
+}
+
+/** @brief Calculate a quaternion length. */
+inline double Quaternion_Length(QUATERNION q) {
+    return sqrt(Quaternion_SquareLength(q));
+}
+
+/** @brief Normalize quaternion. */
+void Quaternion_Normalize(QUATERNION *q) {
+    Quaternion_ScalarDiv(q, Quaternion_Length(*q));
+}
+
+/** @brief Normalize quaternion. */
+QUATERNION Quaternion_GetNormalized(QUATERNION q) {
+    Quaternion_Normalize(&q);
+    return q;
+}
+
+/** @brief Conjugated quaternion. */
+void Quaternion_Conjugated(QUATERNION *q) {
+    q->i = -q->i;
+    q->j = -q->j;
+    q->k = -q->k;
+}
+
+/** @brief Conjugated quaternion. */
+QUATERNION Quaternion_GetConjugated(QUATERNION q) {
+    Quaternion_Conjugated(&q);
+    return q;
+}
+
+/** @brief Inverse quaternion. */
+void Quaternion_Inverse(QUATERNION *q) {
+    Quaternion_Conjugated(q);
+    Quaternion_ScalarDiv(q, Quaternion_SquareLength(*q));
+}
+
+/** @brief Inverse quaternion. */
+QUATERNION Quaternion_GeInverse(QUATERNION q) {
+    Quaternion_Inverse(&q);
+    return q;
+}
+
+inline double Quaternion_GetRotationAngle(QUATERNION q) {
+    return (acos(q.s) * 2);
+}
+
+
+/** @brief Get axis of quaternion. */
+COORD Quaternion_GetRotationAxis(QUATERNION q) {
+    double sin_theta_inv;
+    COORD ret;
+    sin_theta_inv = 1.0 / sin(acos(q.s));
+    ret.x = q.i * sin_theta_inv;
+    ret.y = q.j * sin_theta_inv;
+    ret.z = q.k * sin_theta_inv;
+    return ret;
+}
+
+/** @brief Get the axis and rotate angle of a unit Quaternion */
+void Quaternion_GetRotationAxisAndAngle(QUATERNION q, COORD *axis, double *angle) {
+    double sin_theta_inv;
+    *angle = acos(q.s);
+
+    // pre-compute to save time
+    sin_theta_inv = 1.0 / sin(*angle);
+
+    // now the vector
+    axis->x = q.i * sin_theta_inv;
+    axis->y = q.j * sin_theta_inv;
+    axis->z = q.k * sin_theta_inv;
+    *angle = (*angle) * 2;
+}
+
+/** @brief Decompose the rotation on to 2 parts. */
+void Quaternion_GetSwingAndTwist(QUATERNION q, COORD axis, QUATERNION *swing, QUATERNION *twist) {
+    double p;
+    COORD v;
+    v.x = q.i;
+    v.y = q.j;
+    v.z = q.k;
+    // return projection v1 on to v2  (parallel component)
+    p = Coord_Dot(v, axis);
+    v = Coord_GetScalarMult(axis, p);
+    twist->s = q.s;
+    twist->i = v.x;
+    twist->j = v.y;
+    twist->k = v.z;
+    Quaternion_Normalize(twist);
+    *swing = Quaternion_Mult(q, Quaternion_GetConjugated(*twist));
+}
+
+/** @brief rotates v by this quaternion (quaternion must be unit) */
+COORD Quaternion_Rotate(QUATERNION q, COORD v) {
+    QUATERNION temp;
+    COORD ret;
+    temp.s = 0;
+    temp.i = v.x;
+    temp.j = v.y;
+    temp.k = v.z;
+    temp = Quaternion_Mult(q,temp);
+    Quaternion_Conjugated(&q);
+    temp = Quaternion_Mult(temp,q);
+    ret.x = temp.i;
+    ret.y = temp.j;
+    ret.z = temp.k;
+    return ret;
+}
+
+/** @brief returns the euler angles from a rotation Quaternion */
+EULERANGLES Quaternion_ToEulerAngles(QUATERNION q, EULERANGLES_TYPE type) {
+	EULERANGLES ret;
+	switch (type) {
+	case EULERANGLES_ZYX : {
+		/* Covert form matlab 2023a */
+		// Cap all inputs to asin to 1, since values >1 produce complex
+		// results
+		// Since the quaternion is of unit length, this should never happen,
+		// but some code generation configuration seem to hit this edge case
+		// under some circumstances.
+
+		double asinValue;
+		bool mask1, mask2;
+
+		asinValue = -2.0 *(q.i*q.k - q.s*q.j);
+		mask1 = asinValue >= 1.0 - 10*EPS_DOUBLE.value;
+		mask2 = asinValue <= -1.0 + 10*EPS_DOUBLE.value;
+		if (mask1)
+			asinValue = 1;
+		if (mask2)
+			asinValue = -1;
+
+		if(mask1 || mask2) {
+			ret.alpha = (asinValue > 0) ? (-2.0 * atan2(q.i, q.s)) : (2.0 * atan2(q.i, q.s));
+			ret.gamma = 0;
+		}
+		else {
+			ret.alpha = atan2(2.0*(q.i*q.j + q.s*q.k), q.s*q.s + q.i*q.i - q.j*q.j - q.k*q.k);
+			ret.gamma = atan2(2.0*(q.j*q.k + q.s*q.i), q.s*q.s - q.i*q.i - q.j*q.j + q.k*q.k);
+		}
+		ret.beta = asin( asinValue );
+		break;
+	}
+
+	case EULERANGLES_ZYZ : {
+		// TODO;
+		ret = EULERANGLES_NIL;
+		break;
+	}
+
+	case EULERANGLES_XYZ : {
+		/* Covert form matlab 2023a */
+		// Prevent singularities as done in ZYX case
+		// Alternative to rotm2eul(quat2rotm(q), 'XYZ') with fewer
+		// operations
+		// sin(y) = R13 = 2 * (qx*qz + qy*qw)
+		// tan(x) = sin(x) / cos(x) = -R23 / R33
+		//        = -2 * (qy*qz - qx*qw) / (1 - 2*(qx^2 + qy^2))
+		//        = -2 * (qy*qz - qx*qw) / (qw^2 - qx^2 - qy^2 + qz^2)
+		// tan(z) = sin(z) / cos(z) = -R12 / R11
+		//        = -2 * (qx*qy - qz*qw) / (1 - 2*(qy^2 + qz^2))
+		//        = -2 * (qy*qz - qx*qw) / (qw^2 + qx^2 - qy^2 - qz^2)
+
+		double asinValue;
+		bool mask1, mask2;
+
+		asinValue = 2.0 *(q.i*q.k + q.s*q.j);
+		mask1 = asinValue >= 1.0 - 10*EPS_DOUBLE.value;
+		mask2 = asinValue <= -1.0 + 10*EPS_DOUBLE.value;
+		if (mask1)
+			asinValue = 1;
+		if (mask2)
+			asinValue = -1;
+		if(mask1 || mask2) {
+			ret.alpha = 0;
+			ret.gamma = (asinValue > 0) ? (2.0 * atan2(q.i, q.s)) : (-2.0 * atan2(q.i, q.s));
+		}
+		else {
+			ret.alpha = atan2(-2.0*(q.j*q.k - q.s*q.i), q.s*q.s - q.i*q.i - q.j*q.j + q.k*q.k);
+			ret.gamma = atan2(-2.0*(q.i*q.j - q.s*q.k), q.s*q.s + q.i*q.i - q.j*q.j - q.k*q.k);
+		}
+		ret.beta = asin( asinValue );
+		break;
+	}
+
+
+	default:
+		ret = EULERANGLES_NIL;
+	}
+	return ret;
+}
+
+/** @brief returns the rotation Quaternion from a euler angles */
+QUATERNION Quaternion_FromeEulerAngles(EULERANGLES e, EULERANGLES_TYPE type) {
+	QUATERNION ret;
+	double cosx, sinx, cosy, siny, cosz, sinz;
+	cosx = cos(e.alpha * 0.5);
+    sinx = sin(e.alpha * 0.5);
+    cosy = cos(e.beta * 0.5);
+    siny = sin(e.beta * 0.5);
+    cosz = cos(e.gamma * 0.5);
+    sinz = sin(e.gamma * 0.5);
+	switch (type) {
+	case EULERANGLES_ZYX :
+		ret.s = cosx * cosy * cosz + sinx * siny * sinz;
+		ret.i = cosx * cosy * sinz - sinx * siny * cosz;
+		ret.j = cosx * siny * cosz + sinx * cosy * sinz;
+		ret.k = sinx * cosy * cosz - cosx * siny * sinz;
+		break;
+	case EULERANGLES_ZYZ :
+		ret.s = cosx * cosy * cosz - sinx * cosy * sinz;
+		ret.i = cosx * siny * sinz - sinx * siny * cosz;
+		ret.j = cosx * siny * cosz + sinx * siny * sinz;
+		ret.k = sinx * cosy * cosz + cosx * cosy * sinz;
+		break;
+	case EULERANGLES_XYZ :
+	    ret.s = cosx * cosy * cosz - sinx * siny * sinz;
+	    ret.i = sinx * cosy * cosz + cosx * siny * sinz;
+	    ret.j = -sinx * cosy * sinz + cosx * siny * cosz;
+	    ret.k = cosx * cosy * sinz + sinx * siny * cosz;
+		break;
+	default:
+		ret = QUATERNION_NIL;
+		break;
+	}
+	return ret;
+}
+
+/** @brief adapted from https://svn.code.sf.net/p/irrlicht/code/trunk/include/quaternion.h */
+QUATERNION Quaternion_RotationFromTo(COORD from, COORD to)
+{
+    // Based on Stan Melax's article in Game Programming Gems
+    COORD axis;
+    QUATERNION ret;
+    double c, s;
+    Coord_Normalize(&from);
+    Coord_Normalize(&to);
+
+    c = Coord_Dot(from, to);
+
+    if (c >= 1.0) { // If dot == 1, vectors are the same
+        return QUATERNION_IDENTITY; // identity
+    }
+    else if (c <= -1.0) { // exactly opposite
+        axis = Coord_Cross(COORD_X_AXIS, from);
+
+        if (Coord_Length(axis) == 0)
+            axis = Coord_Cross(COORD_Y_AXIS, from);
+
+        // same as fromAxisAngle(axis, PI).normalize();
+        ret.s = 0;
+        ret.i = axis.x;
+        ret.j = axis.y;
+        ret.k = axis.z;
+        Quaternion_Normalize(&ret);
+        return ret;
+    }
+
+    s = sqrt((1 + c) * 2);
+    axis = Coord_Cross(from, to);
+    Coord_ScalarDiv(&axis, s);
+    ret.s = s * 0.5;
+    ret.i = axis.x;
+    ret.j = axis.y;
+    ret.k = axis.z;
+    Quaternion_Normalize(&ret);
+    return ret;
+}
+
+
+/** @brief linear quaternion interpolation */
+QUATERNION Quaternion_Lerp(QUATERNION q1, QUATERNION q2, double t) {
+    QUATERNION ret;
+    Quaternion_ScalarMult(&q1, 1 - t);
+    Quaternion_ScalarMult(&q1, t);
+    ret = Quaternion_Add(q1, q2);
+    Quaternion_Normalize(&ret);
+    return ret; 
+}
+
+
+/** @brief spherical linear interpolation */
+QUATERNION Quaternion_Slerp(QUATERNION q1, QUATERNION q2, double t) {
+    double dot;
+    QUATERNION q3, ret;
+    dot = Quaternion_Dot(q1, q2);
+    /*  dot = cos(theta)
+        if (dot < 0), q1 and q2 are more than 90 degrees apart,
+        so we can invert one to reduce spinning */
+    if (dot < 0) {
+        dot = -dot;
+        q3.s = -q2.s;
+        q3.i = -q2.i;
+        q3.j = -q2.j;
+        q3.k = -q2.k;
+    }
+    else {
+    	q3 = q2;
+    }
+
+    if (dot < 0.95) {
+        double angle = acos(dot);
+        Quaternion_ScalarMult(&q1, sin(angle * (1 - t)));
+        Quaternion_ScalarMult(&q3, sin(angle * t));
+        ret = Quaternion_Add(q1, q3);
+        Quaternion_ScalarDiv(&ret, sin(angle));
+        return ret;
+    }
+    // if the angle is small, use linear interpolation
+    else {
+        return Quaternion_Lerp(q1, q3, t);
+    }
+}

datalink814_ge/src/linklayer/geometry/quaternion.h

@@ -0,0 +1,109 @@
+
+#ifndef __QUATERNION_H
+#define __QUATERNION_H
+
+#include "coord.h"
+#include "eulerangles.h"
+
+// borrowed and adapted from https://github.com/MegaManSE/willperone/blob/master/Math/quaternion.h
+typedef struct {
+  double s;
+  double i;
+  double j;
+  double k;
+} QUATERNION;
+
+extern const QUATERNION QUATERNION_IDENTITY;
+extern const QUATERNION QUATERNION_NIL;
+
+/** @brief Subtracts two quaternions. */
+QUATERNION Quaternion_Sub(QUATERNION q1, QUATERNION q2);
+
+/** @brief Adds two quaternions. */
+QUATERNION Quaternion_Add(QUATERNION q1, QUATERNION q2);
+
+/** @brief Multiplies a quaternion by a real number. */
+void Quaternion_ScalarMult(QUATERNION *q, double t);
+
+/** @brief Multiplies a quaternion by a real number. */
+QUATERNION Quaternion_GetScalarMult(QUATERNION a, double t);
+
+/** @brief Divides a quaternion by a real number. */
+void Quaternion_ScalarDiv(QUATERNION *q, double t);
+
+/** @brief Divides a quaternion by a real number. */
+QUATERNION Quaternion_GetScalarDiv(QUATERNION a, double t);
+
+/** @brief Multiplies two quaternions. */
+QUATERNION Quaternion_Mult(QUATERNION q1, QUATERNION q2);
+
+/** @brief Divides two quaternions. */
+QUATERNION Quaternion_Div(QUATERNION q1, QUATERNION q2);
+
+/** @brief Dot product. */
+double Quaternion_Dot(QUATERNION q1, QUATERNION q2);
+
+/** @brief Calculate a quaternion length^2 (omits calling square root). */
+double Quaternion_SquareLength(QUATERNION q);
+
+/** @brief Calculate a quaternion length. */
+double Quaternion_Length(QUATERNION q);
+
+/** @brief Normalize quaternion. */
+void Quaternion_Normalize(QUATERNION *q);
+
+/** @brief Normalize quaternion. */
+QUATERNION Quaternion_GetNormalized(QUATERNION q);
+
+/** @brief Conjugated quaternion. */
+void Quaternion_Conjugated(QUATERNION *q);
+
+/** @brief Conjugated quaternion. */
+QUATERNION Quaternion_GetConjugated(QUATERNION q);
+
+/** @brief Inverse quaternion. */
+void Quaternion_Inverse(QUATERNION *q);
+
+/** @brief Inverse quaternion. */
+QUATERNION Quaternion_GeInverse(QUATERNION q);
+
+/** @brief Get rotate angle of quaternion. */
+double Quaternion_GetRotationAngle(QUATERNION q);
+
+/** @brief Get axis of quaternion. */
+COORD Quaternion_GetRotationAxis(QUATERNION q);
+
+/** @brief Get the axis and rotate angle of a unit Quaternion */
+void Quaternion_GetRotationAxisAndAngle(QUATERNION q, COORD *axis, double *angle);
+
+/** @brief Decompose the rotation on to 2 parts.
+    1. Twist - rotation around the "direction" vector
+    2. Swing - rotation around axis that is perpendicular to "direction" vector
+    The rotation can be composed back by rotation = swing * twist
+
+    has singularity in case of swing_rotation close to 180 degrees rotation.
+    if the input quaternion is of non-unit length, the outputs are non-unit as well
+    otherwise, outputs are both unit
+*/
+void Quaternion_GetSwingAndTwist(QUATERNION q, COORD axis, QUATERNION *swing, QUATERNION *twist);
+
+/** @brief rotates v by this quaternion (quaternion must be unit) */
+COORD Quaternion_Rotate(QUATERNION q, COORD v);
+
+/** @brief returns the euler angles from a rotation Quaternion */
+EULERANGLES Quaternion_ToEulerAngles(QUATERNION q, EULERANGLES_TYPE type);
+
+/** @brief returns the rotation Quaternion from a euler angles */
+QUATERNION Quaternion_FromeEulerAngles(EULERANGLES e, EULERANGLES_TYPE type);
+
+/** @brief adapted from https://svn.code.sf.net/p/irrlicht/code/trunk/include/quaternion.h */
+QUATERNION Quaternion_RotationFromTo(COORD from, COORD to);
+
+/** @brief linear quaternion interpolation */
+QUATERNION Quaternion_Lerp(QUATERNION q1, QUATERNION q2, double t);
+
+/** @brief spherical linear interpolation */
+QUATERNION Quaternion_Slerp(QUATERNION q1, QUATERNION q2, double t);
+
+#endif
+

datalink814_ge/src/linklayer/linklayer814.h

@@ -0,0 +1,179 @@
+/*****************************************************************************/
+/**
+ * Description: Header file for 814 linklayer functions
+ * 
+ * Date: 2021-11-13 13:33
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-16 10:12
+ * Revisions: Rev 0.1
+ * History: 
+ * [2022-07-16]: New branch for DiJian.
+ * [2021-11-23]: Initial version.
+ * 
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+#ifndef LINKLAYER814_H_
+#define LINKLAYER814_H_
+
+/***************************** Include Files *********************************/
+#include <stdint.h>
+#include "linklayer814_types.h"
+#include "node_list.h"
+#include "rtt.h"
+#include "../bit_array/bit_array.h"
+#include "../phy_ctrl/phy_ctrl.h"
+#include "../time_ctrl/time_ctrl.h"
+
+
+
+/************************** Constant Definitions *****************************/
+#define DATA_STORE_INTERVAL 100 // 250ms
+
+#define NET_INI_STAGE 0
+#define NET_NORMAL_STAGE 1
+#define NET_INTER_SEEK_STAGE 2
+#define NET_INTRA_SEEK_STAGE 3
+#define NET_SEEK_STAGE 4
+#define NET_ERROR_STAGE -1
+
+#define L2_PACKET_LEN_MAX 1024 //bit
+/***************** Macros (Inline Functions) Definitions *********************/
+#define AssertL2Event(instPtr, event) Linklayer_EventHandler(instPtr, event)
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	L2_NODE_TYPE myType;
+	bool isInterHead;
+	uint8_t clustId;
+	uint8_t myId;
+	uint8_t headId;
+	uint8_t bkpHeadId;
+	uint8_t netScale;
+	PHY_INST* phyInstPtr;
+	TIMECTRL_INST* tmcInstPtr;
+} L2_CONFIG;
+
+typedef struct {
+	L2_CONFIG config;
+	L2_NODE_INFO myInfo;
+	NODE_LIST* nodeList;
+	L2_SCHD_EVENT* l2SchdEventPool[L2_SCHD_EVENT_MAX];
+	uint32_t schdEventCnt;
+	uint32_t netStartTime;
+	bool isEnable; // if the node is connected to the network
+	bool dataAvail; // if there is a valid received frame data in rx buffer
+	bool cxn2Net; // if the node is connected to the network
+	L2_RCD frameNum; // stores the last current and next frame number.
+	L2_RCD slotNum;  // stores the last current and next slot number.
+	L2_RCD frame;   // stores the last current and next link layer frame type.
+	L2_NODE_STATE mainState; // the main state of link layer state
+	L2_NODE_STATE nextState; // next state of link layer state, which will be applied to mainState every second.
+	L2_RTNE_CONFIG rtneConfig; // current routine table configuration and status.
+	L2_SCAN_FSM* scanNetFSM;   // FSM of scan net (link set up)
+	L2_MGMT_FSM* mgmtNetFSM;   // FSM of management net (link management and time sync)
+	L2_SVC_FSM* serviceNetFSM; // FSM of service net (data service)
+	L2_RTT_FSM* rttFSM;     // FSM for RTT (time sync algorithm)
+	uint8_t* sendPktData;
+	uint8_t* recvPktData;
+	// for MPC
+	uint8_t buffSwitch;
+	uint8_t mgmtMsgRecvCnt0;
+	uint8_t svcMsgRecvCnt0;
+	uint8_t* mgmtMsgRecvBuff0;	 	// mgmtMsg receive data buffer
+	uint8_t* svcMsgRecvBuff0; 		// svc receive data buffer
+	uint8_t mgmtMsgRecvCnt1;
+	uint8_t svcMsgRecvCnt1;
+	uint8_t* mgmtMsgRecvBuff1;	 	// mgmtMsg receive data buffer
+	uint8_t* svcMsgRecvBuff1; 		// svc receive data buffer
+} L2_INST;
+
+/************************** Variable Definitions *****************************/
+extern L2_RTNE_TABLE_ENTRY* initTable[L2_INIT_RTNE_PERIOD];
+extern L2_RTNE_TABLE_ENTRY* seekTable[L2_SEEK_RTNE_PERIOD];
+extern L2_RTNE_TABLE_ENTRY* interSeekTable[L2_NORMAL_RTNE_PERIOD];
+extern L2_RTNE_TABLE_ENTRY* intraSeekTable[L2_NORMAL_RTNE_PERIOD];
+extern L2_RTNE_TABLE_ENTRY* normalTable[L2_NORMAL_RTNE_PERIOD];
+/************************** Function Prototypes ******************************/
+// Main
+int32_t Linklayer_Init(L2_INST** instPtr, const L2_CONFIG *config);
+int32_t Linklayer_Reconfig(L2_INST* instPtr,  const L2_CONFIG *config);
+void Linklayer_Destroy(L2_INST* instPtr);
+int32_t Linklayer_Start(L2_INST* instPtr);
+int32_t Linklayer_Halt(L2_INST* instPtr);
+int32_t Linklayer_Proc(L2_INST* instPtr);
+int32_t Linklayer_EventHandler(L2_INST* instPtr, const L2_EVENT* l2Event);
+int32_t Linklayer_PktHandler(L2_INST* instPtr, L2_FRAME_TYPE frameType);
+int32_t L2_SetupNextSlot(L2_INST* instPtr, L2_TOR_TYPE txrxMode, L2_FRAME_TYPE frameType);
+
+// Event
+bool L2_isEventScheduled(L2_SCHD_EVENT* schdEvent);
+int32_t L2_CancelEvent(L2_SCHD_EVENT* schdEvent);
+int32_t L2_SchdEventAppendMsg(L2_SCHD_EVENT* schdEvent, void* msg);
+L2_SCHD_EVENT* L2_CreatNewSchdEvent(L2_INST* instPtr, L2_EVENT_TYPE event);
+int32_t L2_DeletSchdEvent(L2_INST* instPtr, int32_t eventId);
+void L2_ClearSchdEvent(L2_INST* instPtr);
+int32_t L2_ScheduleEventAt(L2_INST* instPtr, L2_SCHD_EVENT* schdEvent, uint32_t frameNo, uint32_t slotNo);
+int32_t L2_ScheduleEventAfter(L2_INST* instPtr, L2_SCHD_EVENT* schdEvent, uint32_t numSlots);
+int32_t L2_RecheduleEventAt(L2_INST* instPtr, L2_SCHD_EVENT* schdEvent, uint32_t frameNo, uint32_t slotNo);
+int32_t L2_RecheduleEventAfter(L2_INST* instPtr, L2_SCHD_EVENT* schdEvent, uint32_t numSlots);
+
+// Framing
+void L2_FrameStateUpdate(L2_INST* instPtr);
+L2_FRAME_TYPE L2_GetLastRcvFrameType(L2_INST* instPtr);
+L1_FRAME_TYPE L2_L2frame2L1frame(L2_FRAME_TYPE l2Frame);
+void FrameGetChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t* chunk);
+void FrameInsertChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t chunck);
+int32_t L2_CrcAppend(uint8_t* dataBuff, uint32_t dataLen, uint32_t crcPos, L2_CRC_TYPE crcType);
+bool L2_CrcCheck(uint8_t* dataBuff, uint32_t dataLen, uint32_t crcPos, L2_CRC_TYPE crcType);
+
+// Scan Net
+int32_t ScanNet_Init(L2_SCAN_FSM** scanFSMPtr);
+void ScanNet_Reset(L2_SCAN_FSM* scanFSMPtr);
+void ScanNet_Destroy(L2_SCAN_FSM* scanFSMPtr);
+int32_t ScanNet_Proc(L2_INST* instPtr);
+int32_t ScanNet_PktHandler(L2_INST* instPtr);
+int32_t ScanNet_Routine(L2_INST* instPtr, const L2_RTNE_TABLE_ENTRY* rtneEntry);
+
+// Management Net
+int32_t MgmtNet_Init(L2_MGMT_FSM** mgmtFSM);
+void MgmtNet_Reset(L2_MGMT_FSM* mgmtFSM);
+void MgmtNet_Destroy(L2_MGMT_FSM* mgmtFSM);
+int32_t MgmtNet_PktHandler(L2_INST* instPtr);
+int32_t MgmtNet_Routine(L2_INST* instPtr, const L2_RTNE_TABLE_ENTRY* rtneEntry);
+
+
+// Service net
+int32_t ServiceNet_Init(L2_SVC_FSM** serviceFSM);
+void ServiceNet_Reset(L2_SVC_FSM* serviceFSM);
+void ServiceNet_Destroy(L2_SVC_FSM* serviceFSM);
+int32_t ServiceNet_PktHandler(L2_INST* instPtr);
+int32_t ServiceNet_Routine(L2_INST* instPtr, const L2_RTNE_TABLE_ENTRY* schedEntry);
+
+// Miscellaneous
+L2_NODE_STATE L2_GetMainState(L2_INST* instPtr);
+L2_RTT_FSM* L2_GetRttDesc(L2_INST* instPtr);
+bool L2_isDataAvail(L2_INST* instPtr);
+bool L2_isCxn2Net(L2_INST* instPtr);
+void L2_RcdShift(L2_RCD* rcd, int32_t netxVal);
+uint32_t L2_GetFrameLen(L2_FRAME_TYPE l2FrameType);
+uint32_t L2_GetLastFrameNum(L2_INST* instPtr);
+uint32_t L2_GetLastSlotNum(L2_INST* instPtr);
+uint32_t L2_GetCurrentFrameNum(L2_INST* instPtr);
+uint32_t L2_GetCurrentSlotNum(L2_INST* instPtr);
+uint32_t L2_GetNextFrameNum(L2_INST* instPtr);
+uint32_t L2_GetNextSlotNum(L2_INST* instPtr);
+
+// Time syncronization
+int32_t L2_TimeAlign(L2_INST* instPtr, uint32_t frameNum, uint32_t slotNum);
+
+// RTT
+int32_t RTT_Init(L2_RTT_FSM** rttFsmPtr);
+void RTT_Reset(L2_RTT_FSM* rttFsmPtr);
+void RTT_Destroy(L2_RTT_FSM* rttFsmPtr);
+int32_t RTT_Proc(L2_INST* instPtr);
+
+
+#endif /* LINKLAYER814_H_ */

datalink814_ge/src/linklayer/linklayer814_types.h

@@ -0,0 +1,324 @@
+/*****************************************************************************/
+/**
+ * Description: A brief description of this file
+ * 
+ * Date: 2022-08-28 22:53
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-08-29 00:45
+ * Revisions: Rev x.x
+ * History: 
+ * [YYYY-MM-DD]: Description of modification.
+ * 
+ * Copyright(c) 2022 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+******************************************************************************/
+
+#ifndef LINKLAYER814_DEF_H_
+#define LINKLAYER814_DEF_H_
+
+/***************************** Include Files *********************************/
+#include <stdbool.h>
+#include <inttypes.h>
+#include "geometry/coord.h"
+#include "../phy_ctrl/phy_ctrl.h"
+/************************** Constant Definitions *****************************/
+// Common node ID definition
+#define BROADCAST_ID 0x1F
+#define NONE_ID BROADCAST_ID
+
+// for MPC Configure
+#define MSG_STROAGE_BUFF_MAX 16384 // 16K Bytes
+
+// Routine configure
+#define L2_INIT_RTNE_PERIOD 24
+#define L2_NORMAL_RTNE_PERIOD 60
+#define L2_SEEK_RTNE_PERIOD 60
+#define L2_INTER_SEEK_RTNE_PERIOD 60
+#define L2_INTRA_SEEK_RTNE_PERIOD 60
+
+// Common slot number definition
+#define L2_SLOTNO_NONE 0
+#define L2_FRAMENO_NONE 0
+
+// Common number of slots definition
+#define L2_SLOTS_PER_FRAME  200
+#define L2_SLOTS_PER_SUBFRAME  20
+
+#define NUM_SLOTS_NONE UINT32_MAX
+#define NUM_SLOTS_20MS	4
+#define NUM_SLOTS_10MS	2
+#define NUM_SLOTS_5MS	1
+#define NUM_SLOTS_SKIP	0
+
+// Common schedule event definition
+#define L2_SCHD_EVENT_MAX 16
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	uint32_t last;
+	uint32_t curr;
+	uint32_t next;
+} L2_RCD;
+
+/** @name Tx/Rx mode code
+ */
+typedef enum {
+	L2_TOR_SUSPEND = 0,
+	L2_TOR_TX = 1,
+	L2_TOR_RX = 2
+} L2_TOR_TYPE;
+
+/** @name Prior information type definition
+ */
+typedef enum {
+	NONE_TYPE = 0,
+	HEAD_NODE = 1,
+	MEMBER_NODE = 2,
+	BACKUP_HEAD = 3
+} L2_NODE_TYPE;
+
+/** @name Node state type definition
+ */
+typedef enum {
+	NONE_STATE = 0, 
+	INIT_STATE = 1, 
+	NORMAL_STATE = 2, 
+	INTRA_SEEK_STATE = 3, 
+	INTER_SEEK_STATE = 4,
+	SEEK_STATE = 5
+} L2_NODE_STATE;
+
+typedef struct {
+	uint8_t nodeId;
+	uint8_t clustId;
+	L2_NODE_TYPE nodeType;
+	uint8_t beamNo;
+	COORD pos;
+	COORD speed;
+} L2_NODE_INFO;
+
+/** @name L2 event enum
+ * A enum of L2 event types.
+ */
+typedef enum {
+	L2_EV_NONE = 0,
+	L2_EV_SCAN_PROC_DONE = 1,
+	L2_EV_MGMT_PROC_DONE = 2,
+	L2_EV_NET_SETUP_DONE = 3,
+	L2_EV_TIME_SYNC = 4,
+	L2_EV_LINK_SET_REQ = 6,
+	L2_EV_LOST_CXN = 7,
+	L2_EV_LOST_NODE = 8,
+	L2_EV_SET_FRAME_NUM = 9,
+	L2_EV_SET_SLOT_NUM = 10,
+	L2_EV_MAIN_STATE_UPDATE = 11,
+	L2_ROUTINE_FINISH = 12,
+	L2_ROUTINE_UPDATE = 13
+} L2_EVENT_TYPE;
+
+/** @name L2 event
+ * A definition of L2 event instance.
+ */
+typedef struct {
+	L2_EVENT_TYPE event;
+	void* msg;
+} L2_EVENT;
+
+/** @name L2 event
+ * A definition of L2 event instance.
+ */
+typedef struct {
+	uint8_t eventId;
+	bool isSchd;
+	L2_EVENT l2Event;
+	uint32_t schdFrame;
+	uint32_t schdSlot;
+} L2_SCHD_EVENT;
+
+/** @name Slot types
+ * A definition of different slots.
+ */
+typedef enum {
+	SLOT_NONE = 0,
+	SLOT_IDLE = 1,
+	SLOT_INTER_SCAN_ACQ = 2,
+	SLOT_INTRA_SCAN_ACQ = 3,
+	SLOT_INTER_SCAN_BM = 4,
+	SLOT_INTRA_SCAN_BM = 5,
+	SLOT_INTER_SCAN_2W = 6,
+	SLOT_INTRA_SCAN_2W = 7,
+	SLOT_INTER_SVC = 8,
+	SLOT_INTRA_SVC = 9,
+	SLOT_INTER_MGMT = 10,
+	SLOT_INTRA_MGMT = 11,
+	SLOT_INTER_TSYNC = 12,
+	SLOT_INTRA_TSYNC = 13,
+} L2_SLOT_TYPE;
+
+/** @name Frame types
+ * A definition of different frame types.
+ */
+typedef enum {
+	L2_CRC_NONE = 0,
+	L2_CRC16_1021 = 1,
+	L2_CRC16_8005 = 2,
+	L2_CRC8_31 = 3
+} L2_CRC_TYPE;
+
+/** @name Frame types
+ * A definition of different frame types.
+ */
+typedef enum {
+	L2_NONE_FRAME = 0,
+	L2_INTER_SCAN_FRAME = 1,
+	L2_INTRA_SCAN_FRAME = 2,
+	L2_INTER_BM_FRAME = 3,
+	L2_INTRA_BM_FRAME = 4,
+	L2_INTER_W2_ACQ_FRAME = 5,
+	L2_INTRA_W2_ACQ_FRAME = 6,
+	L2_INTER_MGMT_FRAME = 7,
+	L2_INTRA_MGMT_FRAME = 8,
+	L2_INTER_TSYNC_FRAME = 9,
+	L2_INTRA_TSYNC_FRAME = 10,
+	L2_INTER_SVC_FRAME = 11,
+	L2_INTRA_SVC_FRAME = 12
+} L2_FRAME_TYPE;
+
+/** @name Schedule subtable entry
+ * A definition of Schedule subtable entry.
+ */
+typedef struct {
+	L2_SLOT_TYPE slotType : 8;
+	uint8_t slotSeq;
+	uint8_t src0;
+	uint8_t dst0;
+	uint8_t src1;
+	uint8_t dst1;
+} L2_RTNE_TABLE_ENTRY;
+
+
+
+ // Scan net
+typedef struct {
+	uint8_t NodeId;
+	uint8_t ClusterId;
+	uint32_t frameNum;
+	uint32_t slotNum;
+	uint16_t EastSpeed;
+	uint16_t NorthSpeed;
+	uint16_t UpperSpeed;
+	uint32_t Height;
+	uint32_t Longitude;
+	uint32_t Latitude;
+} L2_BM_LOG;
+
+typedef struct {
+	uint8_t  NodeId;
+	uint8_t  ClusterId;
+	uint16_t EastSpeed;
+	uint16_t NorthSpeed;
+	uint16_t UpperSpeed;
+	uint32_t Height;
+	uint32_t Longitude;
+	uint32_t Latitude;
+	L2_NODE_STATE  NetStage;
+	uint32_t NetScanTime;
+} L2_W2ACQ_LOG;
+
+typedef enum {
+	NONE_STAGE = 0,
+	INIT_SCAN_STAGE = 1,
+	BM_ADVT_STAGE = 2, // Benchmark advertisement
+	WAY2_ACQ_STAGE = 3
+} SCAN_STAGE;
+
+typedef enum {
+	NONE_MODE = 0,
+	INTRA_CLUSTER_MODE = 1,
+	INTER_CLUSTER_MODE = 2
+} SCAN_MODE;
+
+typedef struct {
+	bool isLocked; // init acq done.
+	bool isBmRcved;// bm received.
+	bool isAcked;  // 2way acq done.
+	uint32_t bmTimeout;
+	uint32_t w2acqTimeout;
+	SCAN_STAGE scanStage; // only for member node
+	SCAN_MODE scanMode;   // inter sanc or intra scan
+	L2_BM_LOG BMrcvLog;
+	L2_W2ACQ_LOG W2ACQrcvLog;
+} L2_SCAN_FSM;
+
+// Service Net
+typedef struct {
+	bool isBisar;
+	bool isBisarEven; // Send frame at even slot at bisar mode.
+	uint8_t bisarDst;
+	uint32_t bisarEndframe;
+} L2_SVC_FSM;
+
+
+// Management net
+typedef struct {
+	uint8_t wordTag	;
+	uint8_t msgTag	;
+	uint8_t msgSubTag;
+	uint8_t srcNodeId ;
+	uint8_t quitNodeId ;
+	uint8_t quitCtrlWord ;
+	uint8_t nextNetState;
+	uint16_t EastSpeed ;
+	uint16_t NorthSpeed;
+	uint16_t UpperSpeed;
+	uint32_t Height    ;
+	uint32_t Longitude ;
+	uint32_t Latitude  ;
+	bool isValid;
+} MGMT_MSG_RECORD;
+
+typedef struct {
+	uint16_t wordTag;
+	uint16_t msgTag;
+	uint16_t msgSubTag;
+	uint16_t msgLen;
+	uint16_t srcAddr;
+	uint16_t dstAddr;
+	uint32_t timeWordL;
+	uint32_t timeWordH;
+	int32_t  doppler;
+} RTT_MSG_RECORD;
+
+typedef struct {
+	uint32_t timeH;
+	uint32_t timeL;
+} L2_TIME_WORD;
+
+typedef struct {
+	L2_TIME_WORD rttTime;
+	uint32_t rttDoppler;
+} RTT_DATA;
+
+typedef struct {
+	bool isBisarProc;
+	bool isPendTimeAlloc;
+	bool isPendSlotAlloc;
+	MGMT_MSG_RECORD mgmtMsgLog;
+	RTT_MSG_RECORD rttMsgRspLog;
+	RTT_MSG_RECORD rttMsgReqLog;
+	RTT_DATA rttData;
+} L2_MGMT_FSM;
+
+
+typedef struct{
+	L2_RTNE_TABLE_ENTRY** rtneTable;
+	uint32_t rtnePrd;
+	L2_RTNE_TABLE_ENTRY* last;
+	L2_RTNE_TABLE_ENTRY* curr;
+	L2_RTNE_TABLE_ENTRY* next;
+}L2_RTNE_CONFIG;
+
+/************************** Variable Definitions *****************************/
+#endif /* LINKLAYER814_H_ */

datalink814_ge/src/linklayer/linklayer_routine.c

@@ -0,0 +1,791 @@
+/*****************************************************************************/
+/**
+ * Description: Time allocations for 814 datalink, 
+ * Date: 2022-07-16 17:05
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-16 17:05
+ * Revisions: Rev 0.1
+ * History:
+ * [2021-11-13]: Initial version.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+#include <inttypes.h>
+
+#include "linklayer814_types.h"
+
+L2_RTNE_TABLE_ENTRY normalSubT_0[L2_SLOTS_PER_FRAME] = {
+// Frame 1
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 2
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 3
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 4
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 5
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 6
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 7
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 8
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 9
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 10
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00}
+};
+
+
+
+L2_RTNE_TABLE_ENTRY normalSubT_1[L2_SLOTS_PER_FRAME] = {
+// Frame 1
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 2
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 3
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 4
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 5
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 6
+	{SLOT_INTRA_TSYNC,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 7
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_TSYNC,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_TSYNC,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 8
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_TSYNC,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 9
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+
+// Frame 10
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00}, {SLOT_INTRA_SVC  ,0x00,0x02,0x01,0x00,0x00},
+	{SLOT_INTRA_MGMT ,0x00,0x01,0x02,0x00,0x00}, {SLOT_INTRA_MGMT ,0x00,0x02,0x01,0x00,0x00}
+};
+
+// L2_RTNE_TABLE_ENTRY interScanSubT_0[L2_SLOTS_PER_FRAME] = {
+// // Frame 1
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// // Frame 2
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// // Frame 3
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// // Frame 4
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// // Frame 5
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// // Frame 6
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// // Frame 7
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// // Frame 8
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_ACQ,0x00,0x02,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_ACQ,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_BM,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_BM,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_BM,0x02,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_BM,0x03,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_BM,0x04,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_BM,0x05,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_BM,0x06,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_BM,0x07,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_BM,0x08,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_BM,0x09,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_BM,0x0A,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_BM,0x0B,0x01,0x1F,0x00,0x00},
+// // Frame 9
+// 	{SLOT_INTER_SCAN_BM,0x0C,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_BM,0x0D,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_BM,0x0E,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_BM,0x0F,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_BM,0x10,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_BM,0x11,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_BM,0x12,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_BM,0x13,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x1F,0x01,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x1F,0x01,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x01,0x1F,0x00,0x00},
+// // Frame 10
+// 	{SLOT_INTER_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x1F,0x01,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x1F,0x01,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x1F,0x01,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x1F,0x01,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x01,0x1F,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x1F,0x01,0x00,0x00},
+// 	{SLOT_INTER_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTER_SCAN_2W,0x01,0x1F,0x01,0x00,0x00}
+// };
+
+
+L2_RTNE_TABLE_ENTRY interScanSubT_0[L2_SLOTS_PER_FRAME] = {
+// Frame 1
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 2
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 3
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 4
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 5
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 6
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 7
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 8
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 9
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 10
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}
+};
+
+L2_RTNE_TABLE_ENTRY interScanSubT_1[L2_SLOTS_PER_FRAME] = {
+// Frame 1
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 2
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 3
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 4
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 5
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 6
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 7
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 8
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 9
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 10
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+};
+
+L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
+// Frame 1
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// Frame 2
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// Frame 3
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+// Frame 4
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_ACQ,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_ACQ,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_BM,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_BM,0x01,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_BM,0x02,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_BM,0x03,0x01,0x1F,0x00,0x00},
+	{SLOT_IDLE,0x00,0x00,0x00,0x00,0x00}, {SLOT_IDLE,0x00,0x00,0x00,0x00,0x00},
+// Frame 5
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+// Frame 6
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+// Frame 7
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+// Frame 8
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+// Frame 9
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+// Frame 10
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x01,0x1F,0x00,0x00},
+	{SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}, {SLOT_INTRA_SCAN_2W,0x00,0x1F,0x01,0x00,0x00}
+};
+
+
+L2_RTNE_TABLE_ENTRY* initTable[L2_INIT_RTNE_PERIOD] = {
+	interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1,
+	interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1,
+	intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT,
+	intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT
+};
+
+
+L2_RTNE_TABLE_ENTRY* seekTable[L2_SEEK_RTNE_PERIOD] = {
+	interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1,
+	interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1
+};
+
+// L2_RTNE_TABLE_ENTRY* seekTable[L2_SEEK_RTNE_PERIOD] = {
+// 	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+// 	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+// 	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+// 	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+// 	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+// 	intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT,
+// 	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+// 	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+// 	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+// 	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1
+// };
+
+L2_RTNE_TABLE_ENTRY* interSeekTable[L2_INTER_SEEK_RTNE_PERIOD] = {
+	interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1,
+	interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1, interScanSubT_0, interScanSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1
+};
+
+L2_RTNE_TABLE_ENTRY* intraSeekTable[L2_INTRA_SEEK_RTNE_PERIOD] = {
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT, intraScanSubT,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1
+};
+
+L2_RTNE_TABLE_ENTRY* normalTable[L2_NORMAL_RTNE_PERIOD] = {
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1,
+	normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1, normalSubT_1
+};

datalink814_ge/src/linklayer/msg_def.h

@@ -0,0 +1,614 @@
+/*****************************************************************************/
+/**
+ * Description: Header of 814 linklayer messages
+ *
+ * Date: 2022-07-14 00:08
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-14 22:52
+ * Revisions: Rev 0.0
+ * History:
+ * [2022-07-14]: Initial version.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+#ifndef MSG_DEF_H_
+#define MSG_DEF_H_
+
+#define L2_MSG_LEN 72 // bit
+#define L2_MSG_MAX 512 // bit
+#define PDU_CRC_LEN 16
+// ** 77 Basic Header 1 Format ** //
+#define PDUH0_LEN 112
+#define PDUH0_TYPE_LEN 1
+#define PDUH0_TYPE_OFFSET 0
+#define PDUH0_RESV_LEN 7
+#define PDUH0_RESV_OFFSET 1
+#define PDUH0_LENGTH_LEN 16
+#define PDUH0_LENGTH_OFFSET 8
+#define PDUH0_SRC_ADDR_LEN 10
+#define PDUH0_SRC_ADDR_OFFSET 24
+#define PDUH0_DST_ADDR_LEN 10
+#define PDUH0_DST_ADDR_OFFSET 34
+#define PDUH0_SEQ_NUM_LEN 16
+#define PDUH0_SEQ_NUM_OFFSET 44
+#define PDUH0_RESV_1_LEN 44
+#define PDUH0_RESV_1_OFFSET 60
+#define PDUH0_HEADER_CRC_LEN 8
+#define PDUH0_HEADER_CRC_OFFSET 104
+
+// ** 78 Message Key Format ** //
+#define MSG_KEY_LENGTH_LEN 88
+
+// ** 79 Basic Header 2 Format ** //
+#define PDUH1_LEN 48
+#define PDUH1_TYPE_LEN 1
+#define PDUH1_TYPE_OFFSET 0
+#define PDUH1_LENGTH_LEN 8
+#define PDUH1_LENGTH_OFFSET 1
+#define PDUH1_SRC_ADDR_LEN 10
+#define PDUH1_SRC_ADDR_OFFSET 9
+#define PDUH1_DST_ADDR_LEN 10
+#define PDUH1_DST_ADDR_OFFSET 19
+#define PDUH1_SLICEH_TAGE_LEN 1
+#define PDUH1_SLICEH_TAGE_OFFSET 29
+#define PDUH1_SLICET_TAGE_LEN 1
+#define PDUH1_SLICET_TAGE_OFFSET 30
+#define PDUH1_RESV_LEN 1
+#define PDUH1_RESV_OFFSET 31
+#define PDUH1_HEADER_CRC_LEN 8
+#define PDUH1_HEADER_CRC_OFFSET 32
+
+// ** 74 Assembling Header Format ** //
+#define UDUH_LEN 64
+#define UDUH_PRI_LEN 3
+#define UDUH_PRI_OFFSET 0
+#define UDUH_RESERV_LEN 1
+#define UDUH_RESERV_OFFSET 3
+#define UDUH_MSG_TYPE_LEN 4
+#define UDUH_MSG_TYPE_OFFSET 4
+#define UDUH_LENGTH_LEN 16
+#define UDUH_LENGTH_OFFSET 8
+#define UDUH_SRC_ADDR_LEN 10
+#define UDUH_SRC_ADDR_OFFSET 24
+#define UDUH_DST_ADDR_LEN 10
+#define UDUH_DST_ADDR_OFFSET 34
+#define UDUH_UDU_SEQ_NUM_LEN 10
+#define UDUH_UDU_SEQ_NUM_OFFSET 44
+#define UDUH_RETRANS_NUM_LEN 2
+#define UDUH_RETRANS_NUM_OFFSET 54
+#define UDUH_NUM_SLICE_LEN 4
+#define UDUH_NUM_SLICE_OFFSET 56
+#define UDUH_SLICE_ID_LEN 4
+#define UDUH_SLICE_ID_OFFSET 60
+
+// ** 88 Benchmark Message ** //
+#define BM_MSG_LEN 232 // bit
+#define BM_MSG_TYPE_LEN 3
+#define BM_MSG_TYPE_OFFSET 0
+#define BM_MSG_SRC_ADDR_LEN 10
+#define BM_MSG_SRC_ADDR_OFFSET 3
+#define BM_MSG_NETMG_ADDR_LEN 10
+#define BM_MSG_NETMG_ADDR_OFFSET 13
+#define BM_MSG_TUNIT_NUM_LEN 17
+#define BM_MSG_TUNIT_NUM_OFFSET 23
+#define BM_MSG_TFRAME_NUM_LEN 4
+#define BM_MSG_TFRAME_NUM_OFFSET 40
+#define BM_MSG_TSLOT_NUM_LEN 6
+#define BM_MSG_TSLOT_NUM_OFFSET 44
+#define BM_MSG_LAG_TIME_TAG_LEN 6
+#define BM_MSG_LAG_TIME_TAG_OFFSET 50
+#define BM_MSG_LONGITUDE_LEN 21
+#define BM_MSG_LONGITUDE_OFFSET 56
+#define BM_MSG_LATITUDE_LEN 20
+#define BM_MSG_LATITUDE_OFFSET 77
+#define BM_MSG_HEIGHT_LEN 15
+#define BM_MSG_HEIGHT_OFFSET 97
+#define BM_MSG_EAST_SPEED_LEN 8
+#define BM_MSG_EAST_SPEED_OFFSET 112
+#define BM_MSG_NORTH_SPEED_LEN 8
+#define BM_MSG_NORTH_SPEED_OFFSET 120
+#define BM_MSG_UPPER_SPEED_LEN 8
+#define BM_MSG_UPPER_SPEED_OFFSET 128
+#define BM_MSG_CRC_LEN 8
+#define BM_MSG_CRC_OFFSET 136
+#define BM_MSG_KEY_LEN 88
+#define BM_MSG_KEY_OFFSET 144
+
+// ** 82 Net Scan Message - INI ** //
+#define NS_MSG_LEN 72
+#define NS_MSG_INI_SER_TAG_LEN 2
+#define NS_MSG_INI_SER_TAG_OFFSET 0
+#define NS_MSG_INI_WTAG_LEN 2
+#define NS_MSG_INI_WTAG_OFFSET 2
+#define NS_MSG_INI_MTAG_LEN 5
+#define NS_MSG_INI_MTAG_OFFSET 4
+#define NS_MSG_INI_STAG_LEN 3
+#define NS_MSG_INI_STAG_OFFSET 9
+#define NS_MSG_INI_LEN_LEN 3
+#define NS_MSG_INI_LEN_OFFSET 12
+#define NS_MSG_INI_TYPE_LEN 1
+#define NS_MSG_INI_TYPE_OFFSET 15
+#define NS_MSG_INI_SRC_ADDR_LEN 10
+#define NS_MSG_INI_SRC_ADDR_OFFSET 16
+#define NS_MSG_INI_DEST_ADDR_LEN 10
+#define NS_MSG_INI_DEST_ADDR_OFFSET 26
+#define NS_MSG_INI_NET_STAGE_LEN 4
+#define NS_MSG_INI_NET_STAGE_OFFSET 36
+#define NS_MSG_INI_SCAN_TIME_LEN 32
+#define NS_MSG_INI_SCAN_TIME_OFFSET 40
+
+// **  83 Net Scan Message - Continue 1 ** //
+#define NS_MSG_CONT_1_RESV_LEN 2
+#define NS_MSG_CONT_1_RESV_OFFSET 0 
+#define NS_MSG_CONT_1_WTAG_LEN 2
+#define NS_MSG_CONT_1_WTAG_OFFSET 2
+#define NS_MSG_CONT_1_CONTID_LEN 4
+#define NS_MSG_CONT_1_CONTID_OFFSET 4
+#define NS_MSG_CONT_1_TIME_TAG_LEN 48
+#define NS_MSG_CONT_1_TIME_TAG_OFFSET 8 
+#define NS_MSG_CONT_1_EAST_SPEED_LEN 16
+#define NS_MSG_CONT_1_EAST_SPEED_OFFSET 56
+
+// **  84 Net Scan Message - Continue 2 ** //
+#define NS_MSG_CONT_2_RESV_1_LEN 2
+#define NS_MSG_CONT_2_RESV_1_OFFSET 0 
+#define NS_MSG_CONT_2_WTAG_LEN 2
+#define NS_MSG_CONT_2_WTAG_OFFSET 2
+#define NS_MSG_CONT_2_CONTID_LEN 4
+#define NS_MSG_CONT_2_CONTID_OFFSET 4
+#define NS_MSG_CONT_2_NORTH_SPEED_LEN 16
+#define NS_MSG_CONT_2_NORTH_SPEED_OFFSET 8
+#define NS_MSG_CONT_2_UPPER_SPEED_LEN 16
+#define NS_MSG_CONT_2_UPPER_SPEED_OFFSET 24
+#define NS_MSG_CONT_2_HEIGHT_LEN 24
+#define NS_MSG_CONT_2_HEIGHT_OFFSET 40
+#define NS_MSG_CONT_2_RESV_2_LEN 8
+#define NS_MSG_CONT_2_RESV_2_OFFSET 64
+
+// **  85 Net Scan Message - Continue 3 ** //
+#define NS_MSG_CONT_3_RESV_LEN 2
+#define NS_MSG_CONT_3_RESV_OFFSET 0 
+#define NS_MSG_CONT_3_WTAG_LEN 2
+#define NS_MSG_CONT_3_WTAG_OFFSET 2
+#define NS_MSG_CONT_3_CONTID_LEN 4
+#define NS_MSG_CONT_3_CONTID_OFFSET 4
+#define NS_MSG_CONT_3_LONGITUDE_LEN 32
+#define NS_MSG_CONT_3_LONGITUDE_OFFSET 8
+#define NS_MSG_CONT_3_LATITUDE_LEN 32
+#define NS_MSG_CONT_3_LATITUDE_OFFSET 40
+
+// **  86 Net Scan Message - Continue 4 ** //
+#define NS_MSG_CONT_4_RESV_LEN 2
+#define NS_MSG_CONT_4_RESV_OFFSET 0 
+#define NS_MSG_CONT_4_WTAG_LEN 2
+#define NS_MSG_CONT_4_WTAG_OFFSET 2
+#define NS_MSG_CONT_4_CONTID_LEN 4
+#define NS_MSG_CONT_4_CONTID_OFFSET 4
+#define NS_MSG_CONT_4_CRC_LEN 16
+#define NS_MSG_CONT_4_CRC_OFFSET 8
+#define NS_MSG_CONT_4_KEY_LEN 48
+#define NS_MSG_CONT_4_KEY_OFFSET 24
+
+// **  87 Net Scan Message - Continue 5 ** //
+#define NS_MSG_CONT_5_RESV_1_LEN 2
+#define NS_MSG_CONT_5_RESV_1_OFFSET 0 
+#define NS_MSG_CONT_5_WTAG_LEN 2
+#define NS_MSG_CONT_5_WTAG_OFFSET 2
+#define NS_MSG_CONT_5_CONTID_LEN 4
+#define NS_MSG_CONT_5_CONTID_OFFSET 4
+#define NS_MSG_CONT_5_KEY_LEN 40
+#define NS_MSG_CONT_5_KEY_OFFSET 8
+#define NS_MSG_CONT_5_RESV_2_LEN 24
+#define NS_MSG_CONT_5_RESV_2_OFFSET 48
+
+#define MGMT_MSG_LEN 72
+// ** 89 Tracking Message INI ** //
+#define TK_MSG_INI_SER_TAG_LEN 2
+#define TK_MSG_INI_SER_TAG_OFFSET 0
+#define TK_MSG_INI_WTAG_LEN 2
+#define TK_MSG_INI_WTAG_OFFSET 2
+#define TK_MSG_INI_TAG_LEN 5
+#define TK_MSG_INI_TAG_OFFSET 4
+#define TK_MSG_INI_STAG_LEN 3
+#define TK_MSG_INI_STAG_OFFSET 9
+#define TK_MSG_INI_LEN 3
+#define TK_MSG_INI_OFFSET 12
+#define TK_MSG_INI_TK_TAG_LEN 4
+#define TK_MSG_INI_TK_TAG_OFFSET 15
+#define TK_MSG_INI_TQLT_LEN 4
+#define TK_MSG_INI_TQLT_OFFSET 19
+#define TK_MSG_INI_TBASE_ID_INDICATE_LEN 1
+#define TK_MSG_INI_TBASE_ID_INDICATE_OFFSET 23 
+#define TK_MSG_INI_CSCALE_NUM_LEN 4
+#define TK_MSG_INI_CSCALE_NUM_OFFSET 24
+#define TK_MSG_INI_MEMBER_NUM_LEN 4
+#define TK_MSG_INI_MEMBER_NUM_OFFSET 28
+#define TK_MSG_INI_MUTE_TAG_LEN 1
+#define TK_MSG_INI_MUTE_TAG_OFFSET 32 
+#define TK_MSG_INI_NET_STATE_LEN 4
+#define TK_MSG_INI_NET_STATE_OFFSET 33
+#define TK_MSG_INI_RESV_LEN 35
+#define TK_MSG_INI_RESV_OFFSET 37
+
+// ** 90 Tracking Message Extend ** //
+#define TK_MSG_EXTEND_RESV_1_LEN 2
+#define TK_MSG_EXTEND_RESV_1_OFFSET 0
+#define TK_MSG_EXTEND_WTAG_LEN 2
+#define TK_MSG_EXTEND_WTAG_OFFSET 2
+#define TK_MSG_EXTEND_TIME_TAG_LEN 48
+#define TK_MSG_EXTEND_TIME_TAG_OFFSET 4
+#define TK_MSG_EXTEND_EAST_SPEED_LEN 16
+#define TK_MSG_EXTEND_EAST_SPEED_OFFSET 52
+#define TK_MSG_EXTEND_RESV_2_LEN 4
+#define TK_MSG_EXTEND_RESV_2_OFFSET 68
+
+// ** 91 Tracking Message Continue 1 ** //
+#define TK_MSG_CONT_1_RESV_1_LEN 2
+#define TK_MSG_CONT_1_RESV_1_OFFSET 0
+#define TK_MSG_CONT_1_WTAG_LEN 2
+#define TK_MSG_CONT_1_WTAG_OFFSET 2
+#define TK_MSG_CONT_1_CONTID_LEN 4
+#define TK_MSG_CONT_1_CONTID_OFFSET 4
+#define TK_MSG_CONT_1_NORTH_SPEED_LEN 16
+#define TK_MSG_CONT_1_NORTH_SPEED_OFFSET 8
+#define TK_MSG_CONT_1_UPPER_SPEED_LEN 16
+#define TK_MSG_CONT_1_UPPER_SPEED_OFFSET 24
+#define TK_MSG_CONT_1_HEIGHT_LEN 24
+#define TK_MSG_CONT_1_HEIGHT_OFFSET 40
+#define TK_MSG_CONT_1_RESV_2_LEN 8
+#define TK_MSG_CONT_1_RESV_2_OFFSET 64
+
+// ** 92 Tracking Message Continue 2 ** //
+#define TK_MSG_CONT_2_RESV_1_LEN 2
+#define TK_MSG_CONT_2_RESV_1_OFFSET 0
+#define TK_MSG_CONT_2_WTAG_LEN 2
+#define TK_MSG_CONT_2_WTAG_OFFSET 2
+#define TK_MSG_CONT_2_CONTID_LEN 4
+#define TK_MSG_CONT_2_CONTID_OFFSET 4
+#define TK_MSG_CONT_2_LONGITUDE_LEN 32
+#define TK_MSG_CONT_2_LONGITUDE_OFFSET 8
+#define TK_MSG_CONT_2_LATITUDE_LEN 32
+#define TK_MSG_CONT_2_LATITUDE_OFFSET 40
+
+// ** 93 Tracking Message Continue 3 ** //
+#define TK_MSG_CONT_3_RESV_1_LEN 2
+#define TK_MSG_CONT_3_RESV_1_OFFSET 0
+#define TK_MSG_CONT_3_WTAG_LEN 2
+#define TK_MSG_CONT_3_WTAG_OFFSET 2
+#define TK_MSG_CONT_3_CONTID_LEN 4
+#define TK_MSG_CONT_3_CONTID_OFFSET 4
+#define TK_MSG_CONT_3_MEMBER_ADDR_LEN 10
+#define TK_MSG_CONT_3_MEMBER_ADDR_OFFSET 8
+#define TK_MSG_CONT_3_RESV_2_LEN 6
+#define TK_MSG_CONT_3_RESV_2_OFFSET 18
+#define TK_MSG_CONT_3_EAST_ACC_LEN 16
+#define TK_MSG_CONT_3_EAST_ACC_OFFSET 24
+#define TK_MSG_CONT_3_NORTH_ACC_LEN 16
+#define TK_MSG_CONT_3_NORTH_ACC_OFFSET 40
+#define TK_MSG_CONT_3_UPPER_ACC_LEN 16
+#define TK_MSG_CONT_3_UPPER_ACC_OFFSET 56
+
+
+// ** 94 Time Announcements Initial ** //
+#define TA_MSG_SER_TAG_LEN 2
+#define TA_MSG_SER_TAG_OFFSET 0
+#define TA_MSG_WTAG_LEN 2
+#define TA_MSG_WTAG_OFFSET 2
+#define TA_MSG_MSG_TAG_LEN 5
+#define TA_MSG_MSG_TAG_OFFSET 4
+#define TA_MSG_MSG_STAG_LEN 3
+#define TA_MSG_MSG_STAG_OFFSET 9
+#define TA_MSG_MSG_LEN 3
+#define TA_MSG_MSG_OFFSET 12
+#define TA_MSG_RESV_LEN 2
+#define TA_MSG_RESV_OFFSET 14
+#define TA_MSG_SRC_ADDR_LEN 10
+#define TA_MSG_SRC_ADDR_OFFSET 16
+#define TA_MSG_CURR_TUNIT_NUM_LEN 17
+#define TA_MSG_CURR_TUNIT_NUM_OFFSET 26
+#define TA_MSG_CURR_TFRAME_NUM_LEN 4
+#define TA_MSG_CURR_TFRAME_NUM_OFFSET 43
+#define TA_MSG_HEIGHT_LEN 24
+#define TA_MSG_HEIGHT_OFFSET 46
+
+// ** 95 Time Announcements Extend ** //
+#define TA_MSG_EX_RESV0_LEN 2
+#define TA_MSG_EX_RESV0_OFFSET 0
+#define TA_MSG_EX_WTAG_LEN 2
+#define TA_MSG_EX_WTAG_OFFSET 2
+#define TA_MSG_EX_LONGITUDE_LEN 32
+#define TA_MSG_EX_LONGITUDE_OFFSET 4
+#define TA_MSG_EX_LATITUDE_LEN 32
+#define TA_MSG_EX_LATITUDE_OFFSET 36
+#define TA_MSG_EX_RESV1_LEN 4
+#define TA_MSG_EX_RESV1_OFFSET 68
+
+// ** 96 Time Announcements Continue 1  ** //
+#define TA_MSG_CONT_1_RESV0_LEN 2
+#define TA_MSG_CONT_1_RESV0_OFFSET 0
+#define TA_MSG_CONT_1_WTAG_LEN 2
+#define TA_MSG_CONT_1_WTAG_OFFSET 2
+#define TA_MSG_CONT_1_TAG_LEN 4
+#define TA_MSG_CONT_1_TAG_OFFSET 4
+#define TA_MSG_CONT_1_TIME_TAG_LEN 48
+#define TA_MSG_CONT_1_TIME_TAG_OFFSET 8
+#define TA_MSG_CONT_1_TSLOT_LEN 6
+#define TA_MSG_CONT_1_TSLOT_OFFSET 56
+#define TA_MSG_CONT_1_RESV1_LEN 10
+#define TA_MSG_CONT_1_RESV1_OFFSET 62
+
+
+// ** 97 Time Announcements Continue 2  ** //
+#define TA_MSG_CONT_2_RESV0_LEN 2
+#define TA_MSG_CONT_2_RESV0_OFFSET 0
+#define TA_MSG_CONT_2_WTAG_LEN 2
+#define TA_MSG_CONT_2_WTAG_OFFSET 2
+#define TA_MSG_CONT_2_TAG_LEN 4
+#define TA_MSG_CONT_2_TAG_OFFSET 4
+#define TA_MSG_CONT_2_EAST_LEN 16
+#define TA_MSG_CONT_2_EAST_OFFSET 8
+#define TA_MSG_CONT_2_NORTH_LEN 16
+#define TA_MSG_CONT_2_NORTH_OFFSET 24
+#define TA_MSG_CONT_2_UPPER_LEN 16 
+#define TA_MSG_CONT_2_UPPER_OFFSET 40 
+#define TA_MSG_CONT_2_RESV1_LEN 16
+#define TA_MSG_CONT_2_RESV1_OFFSET 56
+
+// ** 98 Mission Network Adjustment Notification Message Initial Word  ** //
+#define MADJ_MSG_INI_SER_TAG_LEN 2
+#define MADJ_MSG_INI_SER_TAG_OFFSET 0
+#define MADJ_MSG_INI_WTAG_LEN 2
+#define MADJ_MSG_INI_WTAG_OFFSET 2
+#define MADJ_MSG_INI_MSG_TAG_LEN 5
+#define MADJ_MSG_INI_MSG_TAG_OFFSET 4
+#define MADJ_MSG_INI_MSG_STAG_LEN 3
+#define MADJ_MSG_INI_MSG_STAG_OFFSET 9
+#define MADJ_MSG_INI_MSG_LEN 3
+#define MADJ_MSG_INI_MSG_OFFSET 12
+#define MADJ_MSG_INI_CTRL_CODE_LEN 4
+#define MADJ_MSG_INI_CTRL_CODE_OFFSET 15
+#define MADJ_MSG_INI_TCHIP_LEN 8
+#define MADJ_MSG_INI_TCHIP_OFFSET 19
+#define MADJ_MSG_INI_ADJ_TUNIT_NUM_LEN 17
+#define MADJ_MSG_INI_ADJ_TUNIT_NUM_OFFSET 27
+#define MADJ_MSG_INI_ADJ_TFRAME_NUM_LEN 4
+#define MADJ_MSG_INI_ADJ_TFRAME_NUM_OFFSET 44
+#define MADJ_MSG_INI_ADJ_ANNED_NODE_ADDR_LEN 10
+#define MADJ_MSG_INI_ADJ_ANNED_NODE_ADDR_OFFSET 48
+#define MADJ_MSG_INI_ADJ_RESV_LEN 14
+#define MADJ_MSG_INI_ADJ_RESV_OFFSET 58
+
+// ** 99 Mission Network Adjustment Notification Message Extend Word  ** //
+#define MADJ_MSG_EX_RESV_1_LEN 2
+#define MADJ_MSG_EX_RESV_1_OFFSET 0
+#define MADJ_MSG_EX_WTAG_LEN 2
+#define MADJ_MSG_EX_WTAG_OFFSET 2
+#define MADJ_MSG_EX_PNODE_ADDR_1_LEN 10
+#define MADJ_MSG_EX_PNODE_ADDR_1_OFFSET 4
+#define MADJ_MSG_EX_PNODE_ADDR_2_LEN 10
+#define MADJ_MSG_EX_PNODE_ADDR_2_OFFSET 14
+#define MADJ_MSG_EX_PNODE_ADDR_3_LEN 10
+#define MADJ_MSG_EX_PNODE_ADDR_3_OFFSET 24
+#define MADJ_MSG_EX_PNODE_ADDR_4_LEN 10
+#define MADJ_MSG_EX_PNODE_ADDR_4_OFFSET 34
+#define MADJ_MSG_EX_PNODE_ADDR_5_LEN 10
+#define MADJ_MSG_EX_PNODE_ADDR_5_OFFSET 44
+#define MADJ_MSG_EX_PNODE_ADDR_6_LEN 10
+#define MADJ_MSG_EX_PNODE_ADDR_6_OFFSET 54
+#define MADJ_MSG_EX_RESV_2_LEN 8
+#define MADJ_MSG_EX_RESV_2_OFFSET 64
+
+// ** 100 RTT Inquiry Initial Word ** //
+#define RTT_MSG_LEN 72
+#define RTT_REQ_SER_TAG_LEN 2
+#define RTT_REQ_SER_TAG_OFFSET 0
+#define RTT_REQ_WTAG_LEN 2
+#define RTT_REQ_WTAG_OFFSET 2
+#define RTT_REQ_MSG_TAG_LEN 5
+#define RTT_REQ_MSG_TAG_OFFSET 4
+#define RTT_REQ_MSG_STAG_LEN 3
+#define RTT_REQ_MSG_STAG_OFFSET 9
+#define RTT_REQ_MSG_LEN 3
+#define RTT_REQ_MSG_OFFSET 12
+#define RTT_REQ_SRC_ADDR_LEN 10
+#define RTT_REQ_SRC_ADDR_OFFSET 15
+#define RTT_REQ_DST_ADDR_LEN 10
+#define RTT_REQ_DST_ADDR_OFFSET 25
+#define RTT_REQ_RESV_LEN 37
+#define RTT_REQ_RESV_OFFSET 35
+
+// ** RTT Inquiry Extend Word ** //
+#define RTT_REQ_EX_RESV0_LEN 2
+#define RTT_REQ_EX_RESV0_OFFSET 0
+#define RTT_REQ_EX_WTAG_LEN 2
+#define RTT_REQ_EX_WTAG_OFFSET 2
+#define RTT_REQ_EX_TTAGL_LEN 32
+#define RTT_REQ_EX_TTAGL_OFFSET 4
+#define RTT_REQ_EX_TTAGH_LEN 32
+#define RTT_REQ_EX_TTAGH_OFFSET 36
+#define RTT_REQ_EX_RESV1_LEN 4
+#define RTT_REQ_EX_RESV1_OFFSET 68
+
+// ** RTT Inquiry Continue Word ** //
+#define RTT_REQ_CONT_RESV0_LEN 2
+#define RTT_REQ_CONT_RESV0_OFFSET 0
+#define RTT_REQ_CONT_WTAG_LEN 2
+#define RTT_REQ_CONT_WTAG_OFFSET 2
+#define RTT_REQ_CONT_TAG_LEN 4
+#define RTT_REQ_CONT_TAG_OFFSET 4
+#define RTT_REQ_CONT_DOP_LEN 24
+#define RTT_REQ_CONT_DOP_OFFSET 8
+#define RTT_REQ_CONT_RESV1_LEN 40
+#define RTT_REQ_CONT_RESV1_OFFSET 32
+
+
+// ** 101 RTT Response Initial Word ** //
+#define RTT_RSP_SER_TAG_LEN 2
+#define RTT_RSP_SER_TAG_OFFSET 0
+#define RTT_RSP_WTAG_LEN 2
+#define RTT_RSP_WTAG_OFFSET 2
+#define RTT_RSP_MSG_TAG_LEN 5
+#define RTT_RSP_MSG_TAG_OFFSET 4
+#define RTT_RSP_MSG_STAG_LEN 3
+#define RTT_RSP_MSG_STAG_OFFSET 9
+#define RTT_RSP_MSG_LEN 3
+#define RTT_RSP_MSG_OFFSET 12
+#define RTT_RSP_SRC_ADDR_LEN 10
+#define RTT_RSP_SRC_ADDR_OFFSET 15
+#define RTT_RSP_DST_ADDR_LEN 10
+#define RTT_RSP_DST_ADDR_OFFSET 25
+#define RTT_RSP_ARV_TIME_LEN 25
+#define RTT_RSP_ARV_TIME_OFFSET 35
+#define RTT_RSP_RESV_LEN 12
+#define RTT_RSP_RESV_OFFSET 60
+
+// ** RTT Response Extend Word ** //
+#define RTT_RSP_EX_RESV0_LEN 2
+#define RTT_RSP_EX_RESV0_OFFSET 0
+#define RTT_RSP_EX_WTAG_LEN 2
+#define RTT_RSP_EX_WTAG_OFFSET 2
+#define RTT_RSP_EX_TTAGL_LEN 32
+#define RTT_RSP_EX_TTAGL_OFFSET 4
+#define RTT_RSP_EX_TTAGH_LEN 32
+#define RTT_RSP_EX_TTAGH_OFFSET 36
+#define RTT_RSP_EX_RESV1_LEN 4
+#define RTT_RSP_EX_RESV1_OFFSET 68
+
+// ** RTT Response Continue Word ** //
+#define RTT_RSP_CONT_RESV0_LEN 2
+#define RTT_RSP_CONT_RESV0_OFFSET 0
+#define RTT_RSP_CONT_WTAG_LEN 2
+#define RTT_RSP_CONT_WTAG_OFFSET 2
+#define RTT_RSP_CONT_TAG_LEN 4
+#define RTT_RSP_CONT_TAG_OFFSET 4
+#define RTT_RSP_CONT_DOP_LEN 24
+#define RTT_RSP_CONT_DOP_OFFSET 8
+#define RTT_RSP_CONT_RESV1_LEN 40
+#define RTT_RSP_CONT_RESV1_OFFSET 32
+
+// ** 102 Network Exit Initial Word ** //
+#define NQT_MSG_SER_TAG_LEN 2
+#define NQT_MSG_SER_TAG_OFFSET 0
+#define NQT_MSG_WTAG_LEN 2
+#define NQT_MSG_WTAG_OFFSET 2
+#define NQT_MSG_MSG_TAG_LEN 5
+#define NQT_MSG_MSG_TAG_OFFSET 4
+#define NQT_MSG_MSG_STAG_LEN 3
+#define NQT_MSG_MSG_STAG_OFFSET 9
+#define NQT_MSG_MSG_LEN 3
+#define NQT_MSG_MSG_OFFSET 12
+#define NQT_MSG_CTRL_MUTE_LEN 7
+#define NQT_MSG_CTRL_MUTE_OFFSET 15
+#define NQT_MSG_OBJ_LEN 10
+#define NQT_MSG_OBJ_OFFSET 22
+#define NQT_MSG_RESV_LEN 40
+#define NQT_MSG_RESV_OFFSET 32
+
+// ** 103 Cluster Merge Message Initial Word ** //
+#define CMG_MSG_SER_TAG_LEN 2
+#define CMG_MSG_SER_TAG_OFFSET 0
+#define CMG_MSG_WTAG_LEN 2
+#define CMG_MSG_WTAG_OFFSET 2
+#define CMG_MSG_MSG_TAG_LEN 5
+#define CMG_MSG_MSG_TAG_OFFSET 4
+#define CMG_MSG_MSG_STAG_LEN 3
+#define CMG_MSG_MSG_STAG_OFFSET 9
+#define CMG_MSG_MSG_LEN 3
+#define CMG_MSG_MSG_OFFSET 12
+#define CMG_MSG_CTRL_MUTE_LEN 7
+#define CMG_MSG_CTRL_MUTE_OFFSET 15
+#define CMG_MSG_NEW_CLR_ADDR_LEN 10
+#define CMG_MSG_NEW_CLR_ADDR_OFFSET 22
+#define CMG_MSG_RESV_LEN 40
+#define CMG_MSG_RESV_OFFSET 32
+
+// ** 104 Backup Cluster Head Upgrade Message Initial Word ** //
+#define BCU_MSG_SER_TAG_LEN 2
+#define BCU_MSG_SER_TAG_OFFSET 0
+#define BCU_MSG_WTAG_LEN 2
+#define BCU_MSG_WTAG_OFFSET 2
+#define BCU_MSG_MSG_TAG_LEN 5
+#define BCU_MSG_MSG_TAG_OFFSET 4
+#define BCU_MSG_MSG_STAG_LEN 3
+#define BCU_MSG_MSG_STAG_OFFSET 9
+#define BCU_MSG_MSG_LEN 3
+#define BCU_MSG_MSG_OFFSET 12
+#define BCU_MSG_CTRL_MUTE_LEN 7
+#define BCU_MSG_CTRL_MUTE_OFFSET 15
+#define BCU_MSG_NEW_CLR_ADDR_LEN 10
+#define BCU_MSG_NEW_CLR_ADDR_OFFSET 22
+#define BCU_MSG_BEGIN_TUNIT_NUM_LEN 17
+#define BCU_MSG_BEGIN_TUNIT_NUM_OFFSET 32
+#define BCU_MSG_BEGIN_TFRANE_NUM_LEN 4
+#define BCU_MSG_BEGIN_TFRANE_NUM_OFFSET 49
+#define BCU_MSG_RESV_LEN 19
+#define BCU_MSG_RESV_OFFSET 53
+
+typedef enum{
+	L2_MSG_NONE = 0,
+	L2_MSG_BM = 1,
+	L2_MSG_SCAN_INIT = 2,
+	L2_MSG_SCAN_CONT_1 = 3,
+	L2_MSG_SCAN_CONT_2 = 4,
+	L2_MSG_SCAN_CONT_3 = 5,
+	L2_MSG_SCAN_CONT_4 = 6,
+	L2_MSG_SCAN_CONT_5 = 7,
+	L2_MSG_TK_INIT = 8,
+	L2_MSG_TK_EXTD = 9,
+	L2_MSG_TK_CONT_1 = 10,
+	L2_MSG_TK_CONT_2 = 11,
+	L2_MSG_TK_CONT_3 = 12,
+	L2_MSG_TA_INIT = 13,
+	L2_MSG_TA_EXTD = 14,
+	L2_MSG_TA_CONT_1 = 15,
+	L2_MSG_TA_CONT_2 = 16,
+	L2_MSG_MADJ_INIT = 17,
+	L2_MSG_MADJ_EXTD = 18,
+	L2_MSG_RTT_REQ_INIT = 19,
+	L2_MSG_RTT_REQ_EXTD = 20,
+	L2_MSG_RTT_REQ_CONT = 21,
+	L2_MSG_RTT_RSP_INIT = 22,
+	L2_MSG_RTT_RSP_EXTD = 23,
+	L2_MSG_RTT_RSP_CONT = 24,
+	L2_MSG_NQT_INIT = 25,
+	L2_MSG_CMG_INIT = 26,
+	L2_MSG_BCU_INIT = 27,
+	L2_MSG_LINK_INIT = 28,
+	L2_MSG_LINK_CONT_1 = 29
+}L2_MSG_TYPE;
+
+typedef enum{
+	L2_PDU_HEADER_NONE = 0,
+	L2_PDU_HEADER_0 = 1,
+	L2_PDU_HEADER_1 = 2
+}L2_PDU_HEADER_TYPE;
+
+// Intra-cluster frames
+#define INTRA_BM_FRAME_LENGTH_MAX (232/8) // byte
+#define INTRA_W2ACQ_FRAME_LENGTH_MAX	(2040/8) // byte
+#define INTRA_MGMT_FRAME_LENGTH_MAX (2040/8) // byte
+#define INTRA_TA_FRAME_LENGTH_MAX (2040/8) // byte
+#define INTRA_SVC_FRAME_LENGTH_MAX (2040/8) // byte
+#define INTRA_RTT_FRAME_LENGTH_MAX (2040/8) // byte
+
+// Inter-cluster frames
+#define INTER_BM_FRAME_LENGTH_MAX (312/8) // byte
+#define INTER_W2ACQ_FRAME_LENGTH_MAX	(712/8) // byte
+#define W2ACQ_FRAME_CRC_DLEN ((NS_MSG_LEN*4)/8) //byte
+#define W2ACQ_FRAME_CRC_POS ((NS_MSG_LEN*4 + NS_MSG_CONT_4_CRC_OFFSET)/8)// byte
+
+#define INTER_MGMT_FRAME_LENGTH_MAX (2152/8) // byte
+#define INTER_TA_FRAME_LENGTH_MAX (2152/8) // byte
+#define INTER_SVC_FRAME_LENGTH_MAX (2152/8) // byte
+#define INTER_RTT_FRAME_LENGTH_MAX (2152/8) // byte
+
+extern L2_MSG_TYPE intraBmFrameMsgs[1];
+extern L2_MSG_TYPE intraW2AcqFrameMsgs[6];
+extern L2_MSG_TYPE intraMgmtFrameMsgs[6];
+extern L2_MSG_TYPE taFrameMsgs[4];
+extern L2_MSG_TYPE interSvcFrameMsgs[2];
+extern L2_MSG_TYPE rttReqFrameMsgs[3];
+extern L2_MSG_TYPE rttRspFrameMsgs[3];
+#endif //MSG_DEF_H_

datalink814_ge/src/linklayer/net_mgmt.c

@@ -0,0 +1,991 @@
+/*****************************************************************************/
+/**
+ * Description: Implementations of 814 linklayer management net.
+ * 
+ * Date: 2021-11-18 17:27
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-01-16 15:52
+ * Revisions: Rev 0.1
+ * History: 
+ * [2022-07-16]: New branch for DiJian.
+ * [2021-11-18]: Initial version.
+ * 
+ * Copyright(c) 2022 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include <string.h>
+#include "linklayer814.h"
+#include "linklayer814_types.h"
+#include "msg_def.h"
+#include "rtt.h"
+#include "../error.h"
+#include "../common.h"
+#include "node_list.h"
+/************************** Constant Definitions *****************************/
+#define SQUENCE_MGMT_SLOTS  0
+#define INTER_MGMT_SLOTS	2
+#define INTRA_MGMT_SLOTS	1
+#define NONE_MGMT_SLOTS		-1
+#define CONN_LOST_TH 		10      // 10 count of mgmt msg no response to delete
+#define TIME2QUIT 			80		// time to send quit message
+
+#define SENDRTT 0
+#define RCVDRTT 1
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+typedef enum {
+	MGMTPKT_NONE = 0,
+	MGMTPKT_INTER_MGMT = 1,
+	MGMTPKT_INTRA_MGMT = 2,
+	MGMTPKT_INTER_RTTREQ = 3,
+	MGMTPKT_INTER_RTTRSP = 4,
+	MGMTPKT_INTRA_RTTREQ = 5,
+	MGMTPKT_INTRA_RTTRSP = 6
+} MGMTPKT_TYPE;
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+static int32_t MgmtMsg_Packing(L2_INST* instPtr, BIT_ARRAY* bitarr, L2_MSG_TYPE msgType);
+static int32_t MgmtPkt_Packing(L2_INST* instPtr, MGMTPKT_TYPE pktType);
+/*****************************************************************************/
+/**
+ * @brief   Packing management message to a bit array.
+ *
+ * @param   bitarr	pointer to bit array buffer.
+ *          msgType	message type.
+ *
+ * @return	EPARAM
+ * 			SUCCESS
+ *
+ ******************************************************************************/
+static int32_t MgmtMsg_Packing(L2_INST* instPtr, BIT_ARRAY* bitarr, L2_MSG_TYPE msgType) {
+	ASSERT(instPtr != NULL);
+	ASSERT(bitarr != NULL);
+	if (bitarr->num_of_bits < MGMT_MSG_LEN || msgType < L2_MSG_TK_INIT
+			|| msgType > L2_MSG_BCU_INIT) {
+		return EPARAM;
+	}
+	uint64_t dataChunk = 0;
+	memset(bitarr->words, 0x99, (size_t) (MGMT_MSG_LEN / 8));
+	switch (msgType) {
+	case L2_MSG_TK_INIT:
+		if (bitarr->num_of_bits < MGMT_MSG_LEN) {
+			return EPARAM;
+		}
+		// Series tag
+		dataChunk = 0;
+		FrameInsertChunk(bitarr, TK_MSG_INI_SER_TAG_OFFSET, TK_MSG_INI_SER_TAG_LEN, dataChunk);
+
+		// word tag
+		dataChunk = 3;
+		FrameInsertChunk(bitarr, TK_MSG_INI_WTAG_OFFSET, TK_MSG_INI_WTAG_LEN, dataChunk);
+
+		// message tag
+		dataChunk = 28;
+		FrameInsertChunk(bitarr, TK_MSG_INI_TAG_OFFSET, TK_MSG_INI_TAG_LEN, dataChunk);
+
+		// message sub tag
+		dataChunk = 1;
+		FrameInsertChunk(bitarr, TK_MSG_INI_STAG_OFFSET, TK_MSG_INI_STAG_LEN, dataChunk);
+
+		// message length tag
+		dataChunk = 4;
+		FrameInsertChunk(bitarr, TK_MSG_INI_OFFSET, TK_MSG_INI_LEN, dataChunk);
+
+		// Next net stage
+		if (instPtr->myInfo.nodeType == HEAD_NODE) {
+			switch (instPtr->nextState) {
+			case INIT_STATE:
+				dataChunk = NET_INI_STAGE;
+				break;
+			case NORMAL_STATE:
+				dataChunk = NET_NORMAL_STAGE;
+				break;
+			case INTRA_SEEK_STATE:
+				dataChunk = NET_INTRA_SEEK_STAGE;
+				break;
+			case INTER_SEEK_STATE:
+				dataChunk = NET_INTER_SEEK_STAGE;
+				break;
+			case SEEK_STATE:
+				dataChunk = NET_SEEK_STAGE;
+				break;
+			default:
+				dataChunk = NET_ERROR_STAGE;
+				break;
+			}
+			FrameInsertChunk(bitarr, TK_MSG_INI_NET_STATE_OFFSET, TK_MSG_INI_NET_STATE_LEN, dataChunk);
+		}
+		break;
+	case L2_MSG_TK_EXTD:
+		if (bitarr->num_of_bits < MGMT_MSG_LEN) {
+			return EPARAM;
+		}
+		// Word tag
+		dataChunk = 1;
+		FrameInsertChunk(bitarr, TK_MSG_EXTEND_WTAG_OFFSET, TK_MSG_EXTEND_WTAG_LEN, dataChunk);
+
+		// Time tag
+		dataChunk = 0xAAAAAAAAAAAA;
+		FrameInsertChunk(bitarr, TK_MSG_EXTEND_TIME_TAG_OFFSET, TK_MSG_EXTEND_TIME_TAG_LEN, dataChunk);
+
+		// East speed
+		dataChunk = 0xBBBB;
+		FrameInsertChunk(bitarr, TK_MSG_EXTEND_EAST_SPEED_OFFSET, TK_MSG_EXTEND_EAST_SPEED_LEN, dataChunk);
+		break;
+	case L2_MSG_TK_CONT_1:
+		// Word tag
+		dataChunk = 2;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_1_WTAG_OFFSET, TK_MSG_CONT_1_WTAG_LEN, dataChunk);
+
+		// Continue word identification.
+		dataChunk = 1;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_1_CONTID_OFFSET, TK_MSG_CONT_1_CONTID_LEN, dataChunk);
+
+		// North speed
+		dataChunk = 0xCCCC;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_1_NORTH_SPEED_OFFSET, TK_MSG_CONT_1_NORTH_SPEED_LEN, dataChunk);
+
+		// Upper speed
+		dataChunk = 0xDDDD;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_1_UPPER_SPEED_OFFSET,
+		TK_MSG_CONT_1_UPPER_SPEED_LEN, dataChunk);
+
+		// Height
+		dataChunk = 0xEEEEEE;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_1_HEIGHT_OFFSET, TK_MSG_CONT_1_HEIGHT_LEN, dataChunk);
+		break;
+
+	case L2_MSG_TK_CONT_2:
+		// Word tag
+		dataChunk = 2;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_2_WTAG_OFFSET, TK_MSG_CONT_2_WTAG_LEN, dataChunk);
+
+		// Continue word identification.
+		dataChunk = 2;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_2_CONTID_OFFSET, TK_MSG_CONT_2_CONTID_LEN, dataChunk);
+
+		// Longitude
+		dataChunk = 0xAAAAAAAA;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_2_LONGITUDE_OFFSET, TK_MSG_CONT_2_LONGITUDE_LEN, dataChunk);
+
+		// Latitude
+		dataChunk = 0xBBBBBBBB;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_2_LATITUDE_OFFSET, TK_MSG_CONT_2_LATITUDE_LEN, dataChunk);
+		break;
+	case L2_MSG_TK_CONT_3:
+
+		// Word tag
+		dataChunk = 2;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_3_WTAG_OFFSET, TK_MSG_CONT_3_WTAG_LEN, dataChunk);
+
+		// Continue word identification.
+		dataChunk = 3;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_3_CONTID_OFFSET, TK_MSG_CONT_3_CONTID_LEN, dataChunk);
+
+		// source node id
+		dataChunk = (instPtr->myInfo.nodeId & 0x1F)
+				| (((uint16_t) (instPtr->myInfo.clustId & 0x1F)) << 5);
+		FrameInsertChunk(bitarr, TK_MSG_CONT_3_MEMBER_ADDR_OFFSET, TK_MSG_CONT_3_MEMBER_ADDR_LEN, dataChunk);
+
+		// East speed
+		dataChunk = 0xBBBB;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_3_EAST_ACC_OFFSET, TK_MSG_CONT_3_EAST_ACC_LEN, dataChunk);
+
+		// North speed
+		dataChunk = 0xCCCC;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_3_NORTH_ACC_OFFSET, TK_MSG_CONT_3_NORTH_ACC_LEN, dataChunk);
+
+		// Upper speed
+		dataChunk = 0xDDDD;
+		FrameInsertChunk(bitarr, TK_MSG_CONT_3_UPPER_ACC_OFFSET, TK_MSG_CONT_3_UPPER_ACC_LEN, dataChunk);
+
+		break;
+
+	case L2_MSG_TA_INIT:
+
+		// Word tag
+		dataChunk = 3;
+		FrameInsertChunk(bitarr, TA_MSG_WTAG_OFFSET, TA_MSG_WTAG_LEN, dataChunk);
+
+		// Msg tag
+		dataChunk = 29;
+		FrameInsertChunk(bitarr, TA_MSG_MSG_TAG_OFFSET, TA_MSG_MSG_TAG_LEN, dataChunk);
+
+		// Sub msg tag
+		dataChunk = 0;
+		FrameInsertChunk(bitarr, TA_MSG_MSG_STAG_OFFSET, TA_MSG_MSG_STAG_LEN, dataChunk);
+
+		// Source node id
+		dataChunk = (instPtr->myInfo.nodeId & 0x1F)
+				| (((uint16_t) (instPtr->myInfo.clustId & 0x1F)) << 5);
+		FrameInsertChunk(bitarr, TA_MSG_SRC_ADDR_OFFSET, TA_MSG_SRC_ADDR_LEN, dataChunk);
+
+		// Height
+		dataChunk = 0xEEEEEE;
+		FrameInsertChunk(bitarr, TA_MSG_HEIGHT_OFFSET, TA_MSG_HEIGHT_LEN, dataChunk);
+
+		break;
+	case L2_MSG_TA_EXTD:
+
+		// Longitude
+		dataChunk = 0xAAAAAAAA;
+		FrameInsertChunk(bitarr, TA_MSG_EX_LONGITUDE_OFFSET, TA_MSG_EX_LONGITUDE_LEN, dataChunk);
+
+		// Latitude
+		dataChunk = 0xBBBBBBBB;
+		FrameInsertChunk(bitarr, TA_MSG_EX_LATITUDE_OFFSET, TA_MSG_EX_LATITUDE_LEN, dataChunk);
+
+		break;
+	case L2_MSG_TA_CONT_1:
+
+		// Time tag
+		dataChunk = 0xCCCCCCCCCCCC;
+		FrameInsertChunk(bitarr, TA_MSG_CONT_1_TIME_TAG_OFFSET, TA_MSG_CONT_1_TIME_TAG_LEN, dataChunk);
+
+		break;
+	case L2_MSG_TA_CONT_2:
+
+		// East speed
+		dataChunk = 0xBBBB;
+		FrameInsertChunk(bitarr, TA_MSG_CONT_2_EAST_OFFSET, TA_MSG_CONT_2_EAST_LEN, dataChunk);
+
+		// North speed
+		dataChunk = 0xCCCC;
+		FrameInsertChunk(bitarr, TA_MSG_CONT_2_NORTH_OFFSET, TA_MSG_CONT_2_NORTH_LEN, dataChunk);
+
+		// Upper speed
+		dataChunk = 0xDDDD;
+		FrameInsertChunk(bitarr, TA_MSG_CONT_2_UPPER_OFFSET, TA_MSG_CONT_2_UPPER_LEN, dataChunk);
+
+		break;
+	case L2_MSG_MADJ_INIT:
+		break;
+	case L2_MSG_MADJ_EXTD:
+		break;
+	case L2_MSG_RTT_REQ_INIT:
+		// Series tag
+		dataChunk = 0;
+		FrameInsertChunk(bitarr, RTT_REQ_SER_TAG_OFFSET, RTT_REQ_SER_TAG_LEN, dataChunk);
+
+		// Word tag
+		dataChunk = 3;
+		FrameInsertChunk(bitarr, RTT_REQ_WTAG_OFFSET, RTT_REQ_WTAG_LEN, dataChunk);
+
+		// message identification.
+		dataChunk = 29;
+		FrameInsertChunk(bitarr, RTT_REQ_MSG_TAG_OFFSET, RTT_REQ_MSG_TAG_LEN, dataChunk);
+
+		// message identification.
+		dataChunk = 1;
+		FrameInsertChunk(bitarr, RTT_REQ_MSG_STAG_OFFSET, RTT_REQ_MSG_STAG_LEN, dataChunk);
+
+		// message length.
+		dataChunk = 2;		//request
+		FrameInsertChunk(bitarr, RTT_REQ_MSG_OFFSET, RTT_REQ_MSG_LEN, dataChunk);
+
+		// source node address length.
+		dataChunk = (instPtr->myInfo.nodeId & 0x1F)
+				| (((uint16_t) (instPtr->myInfo.clustId & 0x1F)) << 5);
+		FrameInsertChunk(bitarr, RTT_REQ_SRC_ADDR_OFFSET, RTT_REQ_SRC_ADDR_LEN, dataChunk);
+
+		// destination node address length.
+		dataChunk = (0x02) | (((uint16_t) (instPtr->myInfo.clustId & 0x1F)) << 5);
+		FrameInsertChunk(bitarr, RTT_REQ_DST_ADDR_OFFSET, RTT_REQ_DST_ADDR_LEN, dataChunk);
+		break;
+
+	case L2_MSG_RTT_REQ_EXTD:
+		// Word tag
+		dataChunk = 1;
+		FrameInsertChunk(bitarr, RTT_REQ_EX_WTAG_OFFSET, RTT_REQ_EX_WTAG_LEN, dataChunk);
+
+		// Time tag Low.
+		dataChunk = instPtr->mgmtNetFSM->rttData.rttTime.timeL;
+		FrameInsertChunk(bitarr, RTT_REQ_EX_TTAGL_OFFSET, RTT_REQ_EX_TTAGL_LEN, dataChunk);
+
+		// Time tag High.
+		dataChunk = instPtr->mgmtNetFSM->rttData.rttTime.timeH;
+		FrameInsertChunk(bitarr, RTT_REQ_EX_TTAGH_OFFSET, RTT_REQ_EX_TTAGH_LEN, dataChunk);
+		break;
+	case L2_MSG_RTT_REQ_CONT:
+		// Doppler
+		dataChunk = instPtr->mgmtNetFSM->rttData.rttDoppler;
+		FrameInsertChunk(bitarr, RTT_REQ_CONT_DOP_OFFSET, RTT_REQ_CONT_DOP_LEN, dataChunk);
+
+		////////////////////////////////////////////////////////////////////////////////////////////
+		break;
+	case L2_MSG_RTT_RSP_INIT:
+		// Series tag
+		dataChunk = 0;
+		FrameInsertChunk(bitarr, RTT_RSP_SER_TAG_OFFSET, RTT_RSP_SER_TAG_LEN, dataChunk);
+
+		// Word tag
+		dataChunk = 3;
+		FrameInsertChunk(bitarr, RTT_RSP_WTAG_OFFSET, RTT_RSP_WTAG_LEN, dataChunk);
+
+		// message identification.
+		dataChunk = 29;
+		FrameInsertChunk(bitarr, RTT_RSP_MSG_TAG_OFFSET,
+		RTT_RSP_MSG_TAG_LEN, dataChunk);
+
+		// message identification.
+		dataChunk = 2;		// response
+		FrameInsertChunk(bitarr, RTT_RSP_MSG_STAG_OFFSET, RTT_RSP_MSG_STAG_LEN, dataChunk);
+
+		// message length.
+		dataChunk = 2;
+		FrameInsertChunk(bitarr, RTT_RSP_MSG_OFFSET, RTT_RSP_MSG_LEN, dataChunk);
+
+		// source node address length.
+		dataChunk = (instPtr->myInfo.nodeId & 0x1F)
+				| (((uint16_t) (instPtr->myInfo.clustId & 0x1F)) << 5);
+		FrameInsertChunk(bitarr, RTT_RSP_SRC_ADDR_OFFSET, RTT_RSP_SRC_ADDR_LEN, dataChunk);
+
+		// destination node address length.
+		dataChunk = (0x01) | (((uint16_t) (instPtr->myInfo.clustId & 0x1F)) << 5);
+		FrameInsertChunk(bitarr, RTT_RSP_DST_ADDR_OFFSET, RTT_RSP_DST_ADDR_LEN, dataChunk);
+		break;
+	case L2_MSG_RTT_RSP_EXTD:
+
+		// Word tag
+		dataChunk = 1;
+		FrameInsertChunk(bitarr, RTT_RSP_EX_WTAG_OFFSET, RTT_RSP_EX_WTAG_LEN, dataChunk);
+
+		// Time tag Low.
+		dataChunk = instPtr->mgmtNetFSM->rttData.rttTime.timeL;
+		FrameInsertChunk(bitarr, RTT_RSP_EX_TTAGL_OFFSET, RTT_RSP_EX_TTAGL_LEN, dataChunk);
+
+		// Time tag High.
+		dataChunk = instPtr->mgmtNetFSM->rttData.rttTime.timeH;
+		FrameInsertChunk(bitarr, RTT_RSP_EX_TTAGH_OFFSET, RTT_RSP_EX_TTAGH_LEN, dataChunk);
+		break;
+	case L2_MSG_RTT_RSP_CONT:
+		// Doppler
+		dataChunk = instPtr->mgmtNetFSM->rttData.rttDoppler;
+		FrameInsertChunk(bitarr, RTT_RSP_CONT_DOP_OFFSET, RTT_RSP_CONT_DOP_LEN, dataChunk);
+		break;
+	case L2_MSG_NQT_INIT:
+//		if (priorInfo.myType == MEMBER_NODE && ( L2_GetCurrentFrameNo() == ( myInfo->netScanTime + TIME2QUIT ) )) {
+//			// word tag
+//			dataChunk = 3;
+//			FrameInsertChunk(bitarr, NQT_MSG_WTAG_OFFSET,
+//			NQT_MSG_WTAG_LEN, dataChunk);
+//
+//			// msg tag
+//			dataChunk = 30;
+//			FrameInsertChunk(bitarr, NQT_MSG_MSG_TAG_OFFSET,
+//			NQT_MSG_MSG_TAG_LEN, dataChunk);
+//
+//			// msg sub tag
+//			dataChunk = 1;
+//			FrameInsertChunk(bitarr, NQT_MSG_MSG_STAG_OFFSET,
+//			NQT_MSG_MSG_STAG_LEN, dataChunk);
+//
+//			// msg length
+//			dataChunk = 0;
+//			FrameInsertChunk(bitarr, NQT_MSG_MSG_OFFSET,
+//			NQT_MSG_MSG_LEN, dataChunk);
+//
+//			// Ctrol Word
+//			dataChunk = 1;
+//			FrameInsertChunk(bitarr, NQT_MSG_CTRL_MUTE_OFFSET,
+//			NQT_MSG_CTRL_MUTE_LEN, dataChunk);
+//
+//			// Quit object
+//			dataChunk = (priorInfo.myId & 0x1F)
+//					| (((uint16_t) (priorInfo.clustId & 0x1F)) << 5);
+//			FrameInsertChunk(bitarr, NQT_MSG_OBJ_OFFSET,
+//			NQT_MSG_OBJ_LEN, dataChunk);
+//			L2_NODE_STATE newState = INIT_STATE;
+//			L2_EVENT stateEvent = { 
+//				.event = L2_EV_MAIN_STATE_UPDATE, 
+//				.msg = &newState 
+//			};
+//			AssertL2Event(&stateEvent);
+//			L2_EVENT lostCxnEvent = { 
+//				.event = L2_EV_LOST_CXN, 
+//				.msg = NULL
+//			};
+//			AssertL2Event(&lostCxnEvent);
+//		}
+		break;
+	case L2_MSG_CMG_INIT:
+		break;
+	case L2_MSG_BCU_INIT:
+		break;
+	default:
+		return EPARAM;
+		break;
+	}
+	return SUCCESS;
+}
+
+
+
+static int32_t MgmtPkt_Packing(L2_INST* instPtr, MGMTPKT_TYPE pktType) {
+	ASSERT(instPtr != NULL);
+	uint8_t* buff = instPtr->sendPktData;
+	uint32_t filedSize = 0;
+	BIT_ARRAY* mgmtPkt = bit_array_create(L2_MSG_MAX);
+	if (mgmtPkt == NULL) {
+		DBG_ERROR("Failed to allocate memory for scanMsg.\n");
+		return NUM_SLOTS_NONE;
+	}
+	switch (pktType) {
+	case MGMTPKT_INTRA_MGMT:
+		for (int i = 0; i < ARRAY_SIZE(intraMgmtFrameMsgs); i++) {
+			if (MgmtMsg_Packing(instPtr, mgmtPkt, intraMgmtFrameMsgs[i]) == SUCCESS) {
+				memcpy((uint8_t*)buff + (size_t) (i * (MGMT_MSG_LEN / 8)),
+						mgmtPkt->words, (size_t) (MGMT_MSG_LEN / 8));
+			}
+			else {
+				DBG_ERROR("Failed to packing intraMgmtFrameMsgs[%d].\n", i);
+				goto failed;
+			}
+			filedSize += MGMT_MSG_LEN;
+			if (filedSize / 8 >= INTRA_MGMT_FRAME_LENGTH_MAX) {
+				DBG_ERROR("Message is too long to be properly packed.\n");
+				goto failed;
+			}
+		}
+		break;
+	case MGMTPKT_INTRA_RTTREQ:
+		for(int i = 0; i < ARRAY_SIZE(rttReqFrameMsgs); i++) {
+			if (MgmtMsg_Packing(instPtr, mgmtPkt, rttReqFrameMsgs[i]) == SUCCESS) {
+				memcpy(buff + (size_t)(i * (MGMT_MSG_LEN / 8)),
+						mgmtPkt->words,
+						(size_t)(MGMT_MSG_LEN / 8));
+			}
+			else {
+				DBG_ERROR("Failed to packing rttReqFrameMsgs[%d].\n", i);
+				goto failed;
+			}
+			filedSize += MGMT_MSG_LEN;
+			if (filedSize / 8 >= INTRA_MGMT_FRAME_LENGTH_MAX) {
+				DBG_ERROR("Message is too long to be properly packed.\n");
+				goto failed;
+			}
+		}
+		break;
+	case MGMTPKT_INTRA_RTTRSP:
+		for (int i = 0; i < ARRAY_SIZE(rttRspFrameMsgs); i++) {
+			if (MgmtMsg_Packing(instPtr, mgmtPkt, rttRspFrameMsgs[i]) == SUCCESS) {
+				memcpy(buff + (size_t) (i * (MGMT_MSG_LEN / 8)),
+						mgmtPkt->words,
+						(size_t) (MGMT_MSG_LEN / 8));
+			}
+			else {
+				DBG_ERROR("Failed to packing rttRspFrameMsgs[%d].\n", i);
+				goto failed;
+			}
+			filedSize += MGMT_MSG_LEN;
+			if (filedSize / 8 >= INTRA_MGMT_FRAME_LENGTH_MAX) {
+				DBG_ERROR("Message is too long to be properly packed.\n");
+				goto failed;
+			}
+		}
+		break;
+	default:
+		DBG_ERROR("Scan Packet type [%d] is not surpported yet.\n", pktType);
+		goto failed;
+	}
+	bit_array_free(mgmtPkt);
+	return SUCCESS;
+failed:
+	bit_array_free(mgmtPkt);
+	return FAILURE;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   initialize the management FSM instance.
+ * 
+ * @param   mgmtFSM  A second rank pointer to management FSM instance.
+ * 
+ * @return  SUCCESS Initialize successfully
+ *          EALLOC Memory allocation error.
+ * 
+ ******************************************************************************/
+int32_t MgmtNet_Init(L2_MGMT_FSM** mgmtFSM) {
+	(*mgmtFSM) = (L2_MGMT_FSM*) malloc(sizeof(L2_MGMT_FSM));
+	if (*mgmtFSM == NULL) {
+		return EALLOC;
+	}
+	MgmtNet_Reset(*mgmtFSM);
+	return SUCCESS;
+}
+
+void MgmtNet_Reset(L2_MGMT_FSM* mgmtFSM) {
+	mgmtFSM->isBisarProc = false;
+	mgmtFSM->isPendSlotAlloc = false;
+	mgmtFSM->isPendTimeAlloc = false;
+
+	mgmtFSM->mgmtMsgLog.nextNetState = NONE_STATE;
+	mgmtFSM->mgmtMsgLog.isValid = false;
+	mgmtFSM->mgmtMsgLog.quitCtrlWord = 0;
+	mgmtFSM->mgmtMsgLog.quitNodeId = 0;
+	mgmtFSM->mgmtMsgLog.msgSubTag = 0 ;
+	mgmtFSM->mgmtMsgLog.msgTag = 0;
+	mgmtFSM->mgmtMsgLog.wordTag = 0;
+	mgmtFSM->mgmtMsgLog.srcNodeId = 0;
+
+	// Position value
+	mgmtFSM->mgmtMsgLog.EastSpeed  = 0 ;
+	mgmtFSM->mgmtMsgLog.NorthSpeed = 0 ;
+	mgmtFSM->mgmtMsgLog.UpperSpeed = 0 ;
+	mgmtFSM->mgmtMsgLog.Height     = 0 ;
+	mgmtFSM->mgmtMsgLog.Longitude  = 0 ;
+	mgmtFSM->mgmtMsgLog.Latitude   = 0 ;
+
+	// clear buffer.
+	memset(&(mgmtFSM->rttMsgRspLog), 0x00, sizeof(RTT_MSG_RECORD));
+	memset(&(mgmtFSM->rttMsgReqLog), 0x00, sizeof(RTT_MSG_RECORD));
+	memset(&(mgmtFSM->rttData), 0x00, sizeof(RTT_DATA));
+}
+
+void MgmtNet_Destroy(L2_MGMT_FSM* mgmtFSM){
+	free(mgmtFSM);
+}
+/*****************************************************************************/
+/**
+ * @brief   Handles management net packet, apply time sync and other management
+ *          net functions.
+ * 
+ * @param   msg A pointer to packet data buffer.
+ * 
+ * @return  SUCCESS Packet was successfully handled.
+ *          Other Packed was dumped(not addressed to me, unrecognized frame type)
+ * 
+ ******************************************************************************/
+int32_t MgmtNet_PktHandler(L2_INST* instPtr) {
+	ASSERT(instPtr != NULL);
+	int32_t Status;
+	uint32_t filedSize = 0;
+	uint64_t dataChunk = 0;
+	MGMT_MSG_RECORD *mgmtMsgLog = &(instPtr->mgmtNetFSM->mgmtMsgLog);
+	RTT_MSG_RECORD *rttMsgRspLog = &(instPtr->mgmtNetFSM->rttMsgRspLog);
+	RTT_MSG_RECORD *rttMsgReqLog = &(instPtr->mgmtNetFSM->rttMsgReqLog);
+
+	BIT_ARRAY* mgmtMsg = bit_array_create(L2_MSG_MAX);
+	if (mgmtMsg == NULL) {
+		free(mgmtMsg);
+		return EALLOC;
+	}
+	switch (L2_GetLastRcvFrameType(instPtr)) {
+	case L2_INTER_MGMT_FRAME:
+	case L2_INTRA_MGMT_FRAME: {
+		for (int i = 0; i < ARRAY_SIZE(intraMgmtFrameMsgs); i++) {
+			memcpy(mgmtMsg->words,
+					instPtr->recvPktData + (size_t) (i * (MGMT_MSG_LEN / 8)),
+					(size_t) (MGMT_MSG_LEN / 8));
+			switch (intraMgmtFrameMsgs[i]) {
+			case L2_MSG_TK_INIT:
+				FrameGetChunk(mgmtMsg, TK_MSG_INI_NET_STATE_OFFSET, TK_MSG_INI_NET_STATE_LEN, &dataChunk);
+				mgmtMsgLog->nextNetState = (uint8_t) (dataChunk);
+
+				FrameGetChunk(mgmtMsg, TK_MSG_INI_WTAG_OFFSET, TK_MSG_INI_WTAG_LEN, &dataChunk);
+				mgmtMsgLog->wordTag = (uint8_t) (dataChunk);
+
+				FrameGetChunk(mgmtMsg, TK_MSG_INI_TAG_OFFSET, TK_MSG_INI_TAG_LEN, &dataChunk);
+				mgmtMsgLog->msgTag = (uint8_t) (dataChunk);
+
+				FrameGetChunk(mgmtMsg, TK_MSG_INI_STAG_OFFSET, TK_MSG_INI_STAG_LEN, &dataChunk);
+				mgmtMsgLog->msgSubTag = (uint8_t) (dataChunk);
+
+				if ( mgmtMsgLog->wordTag == 3 
+					&& mgmtMsgLog->msgTag == 28 
+					&& mgmtMsgLog->msgSubTag == 1 ) {
+					mgmtMsgLog->isValid = true;
+				}
+				else {
+					mgmtMsgLog->isValid = false ;
+				}
+				break;
+			case L2_MSG_TK_EXTD :
+				FrameGetChunk(mgmtMsg, TK_MSG_EXTEND_EAST_SPEED_OFFSET, TK_MSG_EXTEND_EAST_SPEED_LEN, &dataChunk);
+				mgmtMsgLog->EastSpeed = (uint16_t) (dataChunk);
+
+				break;
+			case L2_MSG_TK_CONT_1:
+				FrameGetChunk(mgmtMsg, TK_MSG_EXTEND_EAST_SPEED_OFFSET, TK_MSG_EXTEND_EAST_SPEED_LEN, &dataChunk);
+				mgmtMsgLog->EastSpeed = (uint16_t) (dataChunk);
+
+				FrameGetChunk(mgmtMsg, TK_MSG_CONT_1_NORTH_SPEED_OFFSET, TK_MSG_CONT_1_NORTH_SPEED_LEN, &dataChunk);
+				mgmtMsgLog->NorthSpeed = (uint16_t) (dataChunk);
+
+				FrameGetChunk(mgmtMsg, TK_MSG_CONT_1_UPPER_SPEED_OFFSET, TK_MSG_CONT_1_UPPER_SPEED_LEN, &dataChunk);
+				mgmtMsgLog->UpperSpeed = (uint16_t) (dataChunk);
+
+				FrameGetChunk(mgmtMsg, TK_MSG_CONT_1_HEIGHT_OFFSET, TK_MSG_CONT_1_HEIGHT_LEN, &dataChunk);
+				mgmtMsgLog->Height = (uint32_t) (dataChunk);
+
+				break;
+			case L2_MSG_TK_CONT_2:
+				FrameGetChunk(mgmtMsg, TK_MSG_CONT_2_LONGITUDE_OFFSET, TK_MSG_CONT_2_LONGITUDE_LEN, &dataChunk);
+				mgmtMsgLog->Longitude = (uint32_t) (dataChunk);
+
+				FrameGetChunk(mgmtMsg, TK_MSG_CONT_2_LATITUDE_OFFSET, TK_MSG_CONT_2_LATITUDE_LEN, &dataChunk);
+				mgmtMsgLog->Latitude = (uint32_t) (dataChunk);
+
+				break;
+			case L2_MSG_TK_CONT_3:
+				FrameGetChunk(mgmtMsg, TK_MSG_CONT_3_MEMBER_ADDR_OFFSET, TK_MSG_CONT_3_MEMBER_ADDR_LEN, &dataChunk);
+				mgmtMsgLog->srcNodeId = (uint8_t) (dataChunk & 0x1F);
+
+				break;
+			case L2_MSG_NQT_INIT:
+				FrameGetChunk(mgmtMsg, NQT_MSG_OBJ_OFFSET, NQT_MSG_OBJ_LEN, &dataChunk);
+				mgmtMsgLog->quitNodeId = (uint8_t) (dataChunk & 0x1F);
+				if (mgmtMsgLog->quitNodeId != instPtr->myInfo.nodeId) {
+					FrameGetChunk(mgmtMsg, NQT_MSG_CTRL_MUTE_OFFSET, NQT_MSG_CTRL_MUTE_LEN, &dataChunk);
+					mgmtMsgLog->quitCtrlWord = (uint8_t)(dataChunk & 0x7F);
+					if (mgmtMsgLog->quitCtrlWord == 0x01) {
+						DeletNode(instPtr->nodeList, mgmtMsgLog->quitNodeId);
+					}
+				}
+				else {
+					DBG_WARNING("Ignore node quit request(ID not mine), target node id is [%d]\n", mgmtMsgLog->quitNodeId);
+				}
+				break;
+			default:
+				DBG_ERROR("Cannot decapsulate message type [%d] in L2_INTRA_MGMT_FRAME.\n", intraMgmtFrameMsgs[i]);
+				Status = EPARAM;
+				goto failed;
+			}
+			filedSize += MGMT_MSG_LEN;
+			if (filedSize / 8 >= INTRA_MGMT_FRAME_LENGTH_MAX) {
+				DBG_ERROR("Message decapsulate exceeds frame length.\n");
+				Status = EPARAM;
+				goto failed;
+			}
+		}
+		// Member Node update state with received message
+		if(instPtr->myInfo.nodeId != HEAD_NODE && mgmtMsgLog->isValid == true ){
+			L2_NODE_STATE newState = NONE_STATE;
+			// FIXME :
+			switch (mgmtMsgLog->nextNetState) {
+			case NET_INI_STAGE:
+				newState = INIT_STATE;
+				break;
+			case NET_NORMAL_STAGE:
+				newState = NORMAL_STATE;
+				break;
+			case NET_INTRA_SEEK_STAGE:
+				newState = INTRA_SEEK_STATE;
+				break;
+			case NET_INTER_SEEK_STAGE:
+				newState = INTER_SEEK_STATE;
+				break;
+			case NET_SEEK_STAGE:
+				newState = SEEK_STATE;
+				break;
+			default:
+				DBG_WARNING("Unknown Head node state [%d].\n", mgmtMsgLog->nextNetState);
+				newState = L2_GetMainState(instPtr);
+				break;
+			}
+			L2_EVENT stateUpEvent = {
+				.event = L2_EV_MAIN_STATE_UPDATE,
+				.msg = &newState
+			};
+			AssertL2Event(instPtr, &stateUpEvent);
+		}
+		// TODO: Reset of tracking message src
+		RstNodeTTL(instPtr->nodeList, mgmtMsgLog->srcNodeId);
+
+		if(mgmtMsgLog->srcNodeId == instPtr->config.headId){
+			L2_TimeAlign(instPtr, L2_GetCurrentFrameNum(instPtr), L2_GetCurrentSlotNum(instPtr));
+		}
+		break;
+	}
+	case L2_INTER_TSYNC_FRAME:
+	case L2_INTRA_TSYNC_FRAME: {
+		L2_RTT_FSM* rttFsmPtr = L2_GetRttDesc(instPtr);
+		L2_RTT_SATGE rttStage = RTT_GetCurrentStage(rttFsmPtr);
+		if(rttStage == RTT_REQ1 || rttStage == RTT_REQ2){
+			for (int i = 0; i < ARRAY_SIZE(rttReqFrameMsgs); i++) {
+				memcpy(mgmtMsg->words,
+						instPtr->recvPktData + (size_t) (i * (RTT_MSG_LEN / 8)),
+						(size_t) (RTT_MSG_LEN / 8));
+				switch (rttReqFrameMsgs[i]) {
+				case L2_MSG_RTT_REQ_INIT:
+					FrameGetChunk(mgmtMsg, RTT_REQ_WTAG_OFFSET, RTT_REQ_WTAG_LEN, &dataChunk);
+					rttMsgReqLog->wordTag = (uint16_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_REQ_MSG_TAG_OFFSET, RTT_REQ_MSG_TAG_LEN, &dataChunk);
+					rttMsgReqLog->msgTag = (uint16_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_REQ_MSG_STAG_OFFSET, RTT_REQ_MSG_STAG_LEN, &dataChunk);
+					rttMsgReqLog->msgSubTag = (uint16_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_REQ_MSG_OFFSET, RTT_REQ_MSG_LEN, &dataChunk);
+					rttMsgReqLog->msgLen = (uint16_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_REQ_SRC_ADDR_OFFSET, RTT_REQ_SRC_ADDR_LEN, &dataChunk);
+					rttMsgReqLog->srcAddr = (uint16_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_REQ_DST_ADDR_OFFSET, RTT_REQ_DST_ADDR_LEN, &dataChunk);
+					rttMsgReqLog->dstAddr = (uint16_t) (dataChunk);
+
+					break;
+				case L2_MSG_RTT_REQ_EXTD:
+					FrameGetChunk(mgmtMsg, RTT_REQ_EX_TTAGL_OFFSET, RTT_REQ_EX_TTAGL_LEN, &dataChunk);
+					rttMsgReqLog->timeWordL = (uint32_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_REQ_EX_TTAGH_OFFSET, RTT_REQ_EX_TTAGH_LEN, &dataChunk);
+					rttMsgReqLog->timeWordH = (uint32_t) (dataChunk);
+
+					break;
+				case L2_MSG_RTT_REQ_CONT:
+					FrameGetChunk(mgmtMsg, RTT_REQ_CONT_DOP_OFFSET, RTT_REQ_CONT_DOP_LEN, &dataChunk);
+					rttMsgReqLog->doppler = (int32_t) (dataChunk);
+
+					break;
+				default:
+					DBG_ERROR("Cannot decapsulate message type [%d] in L2_INTRA_TSYNC_FRAME.\n", rttReqFrameMsgs[i]);
+					Status = EPARAM;
+					goto failed;
+				}
+				filedSize += RTT_MSG_LEN;
+				if (filedSize / 8 >= INTRA_RTT_FRAME_LENGTH_MAX) {
+					DBG_ERROR("Message decapsulate exceeds frame length.\n");
+					Status = EPARAM;
+					goto failed;
+				}
+			}
+		}
+		else if(rttStage == RTT_RSP1 || rttStage == RTT_RSP2){
+			for (int i = 0; i < ARRAY_SIZE(rttRspFrameMsgs); i++) {
+				memcpy(mgmtMsg->words,
+						instPtr->recvPktData + (size_t) (i * (RTT_MSG_LEN / 8)),
+						(size_t) (RTT_MSG_LEN / 8));
+				switch (rttRspFrameMsgs[i]) {
+				case L2_MSG_RTT_RSP_INIT:
+					FrameGetChunk(mgmtMsg, RTT_RSP_WTAG_OFFSET, RTT_RSP_WTAG_LEN, &dataChunk);
+					rttMsgRspLog->wordTag = (uint16_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_RSP_MSG_TAG_OFFSET, RTT_RSP_MSG_TAG_LEN, &dataChunk);
+					rttMsgRspLog->msgTag = (uint16_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_RSP_MSG_STAG_OFFSET, RTT_RSP_MSG_STAG_LEN, &dataChunk);
+					rttMsgRspLog->msgSubTag = (uint16_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_RSP_MSG_OFFSET, RTT_RSP_MSG_LEN, &dataChunk);
+					rttMsgRspLog->msgLen = (uint16_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_RSP_SRC_ADDR_OFFSET, RTT_RSP_SRC_ADDR_LEN, &dataChunk);
+					rttMsgRspLog->srcAddr = (uint16_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_RSP_DST_ADDR_OFFSET, RTT_RSP_DST_ADDR_LEN, &dataChunk);
+					rttMsgRspLog->dstAddr = (uint16_t) (dataChunk);
+
+					break;
+				case L2_MSG_RTT_RSP_EXTD:
+					FrameGetChunk(mgmtMsg, RTT_RSP_EX_TTAGL_OFFSET, RTT_RSP_EX_TTAGL_LEN, &dataChunk);
+					rttMsgRspLog->timeWordL = (uint32_t) (dataChunk);
+
+					FrameGetChunk(mgmtMsg, RTT_RSP_EX_TTAGH_OFFSET, RTT_RSP_EX_TTAGH_LEN, &dataChunk);
+					rttMsgRspLog->timeWordH = (uint32_t) (dataChunk);
+
+					break;
+				case L2_MSG_RTT_RSP_CONT:
+					FrameGetChunk(mgmtMsg, RTT_RSP_CONT_DOP_OFFSET,
+					RTT_RSP_CONT_DOP_LEN, &dataChunk);
+					rttMsgRspLog->doppler = (int32_t) (dataChunk);
+
+					break;
+				default:
+					DBG_ERROR("Cannot decapsulate message type [%d] in L2_INTRA_TSYNC_FRAME.\n", rttRspFrameMsgs[i]);
+					Status = EPARAM;
+					goto failed;
+				}
+				filedSize += RTT_MSG_LEN;
+				if (filedSize / 8 >= INTRA_RTT_FRAME_LENGTH_MAX) {
+					DBG_ERROR("Message decapsulate exceeds frame length.\n");
+					Status = EPARAM;
+					goto failed;
+				}
+			}
+		}
+		// TODO: Reset of tracking message src
+		RstNodeTTL(instPtr->nodeList, rttMsgRspLog->srcAddr & 0x001F);
+		if((rttMsgRspLog->srcAddr&0x001F) == instPtr->config.headId){
+			L2_TimeAlign(instPtr, L2_GetCurrentFrameNum(instPtr), L2_GetCurrentSlotNum(instPtr));
+		}
+		break;
+	}
+	default:
+		DBG_ERROR("Cannot handle frame type [%d] properly.\n", L2_GetLastRcvFrameType(instPtr));
+		Status = EPARAM;
+		goto failed;
+	}
+	bit_array_free(mgmtMsg);
+	return SUCCESS;
+failed:
+	bit_array_free(mgmtMsg);
+	return Status;
+}
+
+// helper function
+static bool IsTTLValid(NODE_ENTRY* entry) {
+	ASSERT(entry != NULL);
+	return (entry->ttlCnt <= CONN_LOST_TH);
+}
+/*****************************************************************************/
+/**
+ * @brief   Management net FSM procedure.
+ * 
+ * @param   mgmtFSM 
+ *          mainState
+ * 
+ * @return  Slot has be used.
+ * 
+ ******************************************************************************/
+int32_t MgmtNet_Routine(L2_INST* instPtr, const L2_RTNE_TABLE_ENTRY* rtneEntry){
+	ASSERT(instPtr != NULL);
+	int32_t Status;
+	RTT_DATA *rttData = &(instPtr->mgmtNetFSM->rttData);
+	RTT_RECORD *rttRecord = &(L2_GetRttDesc(instPtr)->rttRecord);
+	DBG_INFO("-------- MgmtNet Routine --------\n");
+
+	if(rtneEntry->slotSeq != 0){
+		return SUCCESS;
+	}
+
+	// Check if there is any node exceeds the ttl threshold.
+	IterDeleteNode(instPtr->nodeList, IsTTLValid);
+
+	// Determine next slot TOR state.
+	L2_TOR_TYPE torState = L2_TOR_SUSPEND;
+	if ((rtneEntry->src0 == instPtr->myInfo.nodeId)
+			|| (rtneEntry->src1 == instPtr->myInfo.nodeId)) {
+		torState = L2_TOR_TX;
+	}
+	else if ((rtneEntry->dst0 == instPtr->myInfo.nodeId)
+			|| (rtneEntry->dst1 == instPtr->myInfo.nodeId)) {
+		torState = L2_TOR_RX;
+	}
+	else {
+		torState = L2_TOR_SUSPEND;
+	}
+
+	switch (rtneEntry->slotType) {
+	case SLOT_INTER_MGMT:
+		// TODO: 
+		L2_SetupNextSlot(instPtr, torState, L2_INTER_MGMT_FRAME);
+		break;
+	case SLOT_INTRA_MGMT:
+		memset(instPtr->sendPktData, 0xAA, INTRA_MGMT_FRAME_LENGTH_MAX);
+		if (torState == L2_TOR_TX) {
+			if(MgmtPkt_Packing(instPtr, MGMTPKT_INTRA_MGMT) != SUCCESS) {
+				Status = FAILURE;
+				goto routine_err;
+			}
+		}
+		L2_SetupNextSlot(instPtr, torState, L2_INTRA_MGMT_FRAME);
+		break;
+	case SLOT_INTER_TSYNC:
+		// TODO: 
+		L2_SetupNextSlot(instPtr, torState, L2_INTER_TSYNC_FRAME);
+		break;
+	case SLOT_INTRA_TSYNC:
+		if (torState == L2_TOR_TX) {
+			// TODO: 
+			memset(instPtr->sendPktData, 0x00, INTRA_RTT_FRAME_LENGTH_MAX); // FIXME
+			L2_RTT_FSM* rttFsmPtr = L2_GetRttDesc(instPtr);
+			L2_RTT_SATGE rttStage = RTT_GetCurrentStage(rttFsmPtr);
+			if(rttStage == RTT_REQ1 || rttStage == RTT_REQ2){
+				if(rttStage == RTT_REQ1){
+					DBG_INFO("MGMT Sending RTT REQ-1\n");
+					rttData->rttTime.timeH = rttRecord->Tt1.timeH;
+					rttData->rttTime.timeL = rttRecord->Tt1.timeL;
+					rttData->rttDoppler = RTT_DOPPLER_NONE;
+				}
+				else{ //RTT_REQ2
+					DBG_INFO("MGMT Sending RTT REQ-2\n");
+					rttData->rttTime.timeH = (rttFsmPtr->isR2Valid)? rttRecord->TroundA.timeH : RTT_TIME_NONE;
+					rttData->rttTime.timeL = (rttFsmPtr->isR2Valid)? rttRecord->TroundA.timeL : RTT_TIME_NONE;
+					rttData->rttDoppler = (rttFsmPtr->isR2Valid)? rttRecord->dopplerR2:RTT_DOPPLER_NONE;
+				}
+				if(MgmtPkt_Packing(instPtr, MGMTPKT_INTRA_RTTREQ) != SUCCESS) {
+					Status = FAILURE;
+					goto routine_err;
+				}
+			}
+			else if(rttStage == RTT_RSP1 || rttStage == RTT_RSP2){
+				if(rttStage == RTT_RSP1){
+					DBG_INFO("MGMT Sending RTT RSP-1\n");
+					rttData->rttTime.timeH = (rttFsmPtr->isR1Valid) ? rttRecord->TreplyB.timeH : RTT_TIME_NONE;
+					rttData->rttTime.timeL = (rttFsmPtr->isR1Valid) ? rttRecord->TreplyB.timeL : RTT_TIME_NONE;
+					rttData->rttDoppler = (rttFsmPtr->isR1Valid) ? rttRecord->dopplerR1 : RTT_DOPPLER_NONE;
+				}
+				else{ //RTT_RSP2
+					DBG_INFO("MGMT Sending RTT RSP-2\n");
+					rttData->rttTime.timeH = (rttFsmPtr->isR3Valid) ? rttRecord->TreplyB.timeH : RTT_TIME_NONE;
+					rttData->rttTime.timeL = (rttFsmPtr->isR3Valid) ? rttRecord->TreplyB.timeL : RTT_TIME_NONE;
+					rttData->rttDoppler = (rttFsmPtr->isR3Valid) ? rttRecord->dopplerR3 : RTT_DOPPLER_NONE;
+				}
+				// Packing message.
+				if(MgmtPkt_Packing(instPtr, MGMTPKT_INTRA_RTTRSP) != SUCCESS) {
+					Status = FAILURE;
+					goto routine_err;
+				}
+
+			}
+			else{
+				DBG_ERROR("Unexpected RTT Stage: %d.\n", rttStage);
+				torState = L2_TOR_SUSPEND;
+			}
+		}
+		L2_SetupNextSlot(instPtr, torState, L2_INTRA_TSYNC_FRAME);
+		break;
+	default:
+		DBG_ERROR("UNKNOWN slot type [%d].\n", rtneEntry->slotType);
+		Status = FAILURE;
+		goto routine_err;
+	}
+
+	/*************************************************/
+	// Update link layer state...
+	if (instPtr->myInfo.nodeType == HEAD_NODE) {
+		L2_NODE_STATE newState = NONE_STATE;
+		L2_EVENT stateEvent = {
+			.event = L2_EV_MAIN_STATE_UPDATE,
+			.msg = &newState
+		};
+		if (instPtr->nodeList->nodeNum < instPtr->config.netScale
+				&& L2_GetMainState(instPtr) != INTRA_SEEK_STATE) {
+			newState = INTRA_SEEK_STATE;
+			AssertL2Event(instPtr, &stateEvent);
+		}
+		else if(instPtr->nodeList->nodeNum >= instPtr->config.netScale &&
+				L2_GetMainState(instPtr) != NORMAL_STATE){
+			newState = NORMAL_STATE;
+			AssertL2Event(instPtr, &stateEvent);
+		}
+	}
+	else{ // MEMBER_NODE or BACKUP_HEAD
+		if(IsNodeInList(instPtr->nodeList, instPtr->config.headId) == false){
+			L2_NODE_STATE newState = INIT_STATE;
+			L2_EVENT stateEvent = {
+				.event = L2_EV_MAIN_STATE_UPDATE,
+				.msg = &newState
+			};
+			AssertL2Event(instPtr, &stateEvent);
+			L2_EVENT lostCxnEvent = {
+				.event = L2_EV_LOST_CXN,
+				.msg = NULL
+			};
+			AssertL2Event(instPtr, &lostCxnEvent);
+			DBG_WARNING("Lost connection with head node [%d].\n", instPtr->config.headId);
+		}
+	}
+	return SUCCESS;
+routine_err:
+	return Status;
+}

datalink814_ge/src/linklayer/net_service.c

@@ -0,0 +1,295 @@
+/*****************************************************************************/
+/**
+ * Description: Implementations for 814 datalink service net.
+ * Date: 2021-11-16 00:08
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-16 17:04
+ * Revisions: Rev 0.1
+ * History:
+ * [2022-07-16]: New branch for DiJian.
+ * [2021-11-16]: Initial version.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include <string.h>
+#include "linklayer814.h"
+#include "linklayer814_types.h"
+#include "msg_def.h"
+#include "../error.h"
+#include "../common.h"
+
+
+#ifdef _MPC_CTRL
+
+#endif
+
+/************************** Constant Definitions *****************************/
+#define SQUENCE_SVC_SLOTS 0
+#define INER_SVC_SLOTS   2
+#define INRA_SVC_SLOTS   1
+#define NONE_SVC_SLOTS   0
+#define TEST_UDU_PDLEN	 16
+#define TEST_UDU_LEN	 (UDUH_LEN/8 + TEST_UDU_PDLEN + PDU_CRC_LEN/8 )
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+#ifdef _MPC_CTRL
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef _MPC_CTRL
+
+#endif
+
+/*****************************************************************************/
+/**
+ * @brief   Packing UDU Header to a bit array.
+ *
+ * @param   bitarr		pointer to bit array buffer.
+ *          dst			Destination node address.
+ *          dataLen		Length of UDU data.
+ *
+ * @return	EPARAM
+ * 			SUCCESS
+ *
+ ******************************************************************************/
+static int UduHeader_Packing(L2_INST* instPtr, BIT_ARRAY* bitarr, uint8_t dst, uint32_t dataLen){
+	ASSERT(bitarr != NULL);
+	if(bitarr->num_of_bits < UDUH_LEN){
+		return EPARAM;
+	}
+	uint64_t dataChunk = 0;
+	memset(bitarr->words, 0xF0, (size_t)(UDUH_LEN/8));
+	// priority
+	dataChunk = 1;
+	FrameInsertChunk(bitarr, UDUH_PRI_OFFSET, UDUH_PRI_LEN, dataChunk);
+	// message type
+	dataChunk = 2;
+	FrameInsertChunk(bitarr, UDUH_MSG_TYPE_OFFSET, UDUH_MSG_TYPE_LEN, dataChunk);
+	// data length
+	dataChunk = dataLen;
+	FrameInsertChunk(bitarr, UDUH_LENGTH_OFFSET, UDUH_LENGTH_LEN, dataChunk);
+	// source node id
+	dataChunk = (instPtr->myInfo.nodeId & 0x1F)|((instPtr->myInfo.clustId & 0x1F) << 5);
+	FrameInsertChunk(bitarr, UDUH_SRC_ADDR_OFFSET, UDUH_SRC_ADDR_LEN, dataChunk);
+	// destination node id
+	dataChunk = (dst & 0x1F)|((instPtr->myInfo.clustId & 0x1F) << 5);
+	FrameInsertChunk(bitarr, UDUH_DST_ADDR_OFFSET, UDUH_DST_ADDR_LEN, dataChunk);
+	// UDU Sequence number
+	dataChunk = 0;
+	FrameInsertChunk(bitarr, UDUH_UDU_SEQ_NUM_OFFSET, UDUH_UDU_SEQ_NUM_LEN, dataChunk);
+	// retransmission times
+	dataChunk = 0;
+	FrameInsertChunk(bitarr, UDUH_RETRANS_NUM_OFFSET, UDUH_RETRANS_NUM_LEN, dataChunk);
+	// number of slice
+	dataChunk = 1;
+	FrameInsertChunk(bitarr, UDUH_NUM_SLICE_OFFSET, UDUH_NUM_SLICE_LEN, dataChunk);
+	// slice id
+	dataChunk = 1;
+	FrameInsertChunk(bitarr, UDUH_SLICE_ID_OFFSET, UDUH_SLICE_ID_LEN, dataChunk);
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Packing PDU Header to a bit array.
+ *
+ * @param   bitarr		pointer to bit array buffer.
+ *          headerType	PDU header type.
+ *          dst			Destination node address.
+ *
+ * @return	EPARAM
+ * 			SUCCESS
+ *
+ ******************************************************************************/
+static int PduHeader_Packing(L2_INST* instPtr, BIT_ARRAY* bitarr, L2_PDU_HEADER_TYPE headerType, uint8_t dst){
+	ASSERT(bitarr != NULL);
+	if(headerType < L2_PDU_HEADER_0	|| headerType > L2_PDU_HEADER_1){
+		return EPARAM;
+	}
+	uint64_t dataChunk = 0;
+	if(headerType == L2_PDU_HEADER_0){
+		if(bitarr->num_of_bits < PDUH0_LEN){
+			return EPARAM;
+		}
+		memset(bitarr->words, 0xF0, (size_t)(PDUH0_LEN/8));
+		// PDU type
+		dataChunk = 0;
+		FrameInsertChunk(bitarr, PDUH0_TYPE_OFFSET, PDUH0_TYPE_LEN, dataChunk);
+		// frame length
+		dataChunk = INTRA_SVC_FRAME_LENGTH_MAX;
+		FrameInsertChunk(bitarr, PDUH0_LENGTH_OFFSET, PDUH0_LENGTH_LEN, dataChunk);
+		// source node id
+		dataChunk = (instPtr->myInfo.nodeId & 0x1F)|((instPtr->myInfo.clustId & 0x1F) << 5);
+		FrameInsertChunk(bitarr, PDUH0_SRC_ADDR_OFFSET, PDUH0_SRC_ADDR_LEN, dataChunk);
+		// destination node id
+		dataChunk = (dst & 0x1F)|((instPtr->myInfo.clustId & 0x1F) << 5);
+		FrameInsertChunk(bitarr, PDUH0_DST_ADDR_OFFSET, PDUH0_DST_ADDR_LEN, dataChunk);
+		// Sequence number
+		dataChunk = 0;
+		FrameInsertChunk(bitarr, PDUH0_SEQ_NUM_OFFSET, PDUH0_SEQ_NUM_LEN, dataChunk);
+		// Append CRC
+		L2_CrcAppend((uint8_t*)bitarr->words, PDUH0_HEADER_CRC_OFFSET/8, PDUH0_HEADER_CRC_OFFSET/8, L2_CRC8_31);
+	}
+	else if(headerType == L2_PDU_HEADER_1){
+		if(bitarr->num_of_bits < PDUH1_LEN){
+			return EPARAM;
+		}
+		memset(bitarr->words, 0xF0, (size_t)(PDUH1_LEN/8));
+		// PDU type
+		dataChunk = 1;
+		FrameInsertChunk(bitarr, PDUH1_TYPE_OFFSET, PDUH1_TYPE_LEN, dataChunk);
+		// frame length
+		dataChunk = INTRA_SVC_FRAME_LENGTH_MAX;
+		FrameInsertChunk(bitarr, PDUH1_LENGTH_OFFSET, PDUH1_LENGTH_LEN, dataChunk);
+		// source node id
+		dataChunk = (instPtr->myInfo.nodeId & 0x1F)|((instPtr->myInfo.clustId & 0x1F) << 5);
+		FrameInsertChunk(bitarr, PDUH1_SRC_ADDR_OFFSET, PDUH1_SRC_ADDR_LEN, dataChunk);
+		// destination node id
+		dataChunk = (dst & 0x1F)|((instPtr->myInfo.clustId & 0x1F) << 5);
+		FrameInsertChunk(bitarr, PDUH1_DST_ADDR_OFFSET, PDUH1_DST_ADDR_LEN, dataChunk);
+		// Slice tage...
+		// Append CRC
+		L2_CrcAppend((uint8_t*)bitarr->words, PDUH1_HEADER_CRC_OFFSET/8, PDUH1_HEADER_CRC_OFFSET/8, L2_CRC8_31);
+	}
+	else{
+		return FAILURE;
+	}
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Initialize service net FSM
+ *
+ * @param   serviceFSM  A pointer to service FSM instance.
+ *
+ * @return  SUCCESS Initialize successfully.
+ *          Other       Initialize failed.
+ *
+ ******************************************************************************/
+int32_t ServiceNet_Init(L2_SVC_FSM** serviceFSM) {
+	(*serviceFSM) = (L2_SVC_FSM*) malloc(sizeof(L2_SVC_FSM));
+	if (*serviceFSM == NULL) {
+		return EALLOC;
+	}
+	ServiceNet_Reset(*serviceFSM);
+	return SUCCESS;
+}
+
+
+void ServiceNet_Reset(L2_SVC_FSM* serviceFSM) {
+	serviceFSM->isBisar = false;
+	serviceFSM->isBisarEven = false;
+	serviceFSM->bisarDst = NONE_ID;
+}
+
+void ServiceNet_Destroy(L2_SVC_FSM* serviceFSM){
+	free(serviceFSM);
+}
+/*****************************************************************************/
+/**
+ * @brief   Handle service received packet. Send data up to MPC
+ *
+ * @param   instPtr	a pointer to linklayer layer instance
+ *
+ * @return  SUCCESS message has been successfully handled.
+ *          other       error occurred.
+ *
+ ******************************************************************************/
+int32_t ServiceNet_PktHandler(L2_INST* instPtr) {
+	// TODO:
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Service net FSM procedure.
+ *
+ * @param   instPtr	a pointer to linklayer layer instance
+ * @param   rtneEntry	
+ *
+ * @return  Slot has been used.
+ *
+ ******************************************************************************/
+int32_t ServiceNet_Routine(L2_INST* instPtr, const L2_RTNE_TABLE_ENTRY* rtneEntry) {
+	ASSERT(instPtr != NULL);
+	int32_t Status;
+	L2_TOR_TYPE torState;
+	DBG_INFO("-------- ServiceNet Routine --------\n");
+
+	if(rtneEntry->slotSeq != 0){
+		return SQUENCE_SVC_SLOTS;
+	}
+
+	// Determine TOR State.
+	if(rtneEntry->src0 == instPtr->myInfo.nodeId){
+		torState = L2_TOR_TX;
+	}
+	else if(rtneEntry->dst0 == instPtr->myInfo.nodeId){
+		torState = L2_TOR_RX;
+	}
+	else{
+		torState = L2_TOR_SUSPEND;
+	}
+
+	BIT_ARRAY* svcMsg = bit_array_create(L2_MSG_MAX);
+	if(svcMsg == NULL){
+		DBG_ERROR("Failed to allocate memory for svcMsg.\n");
+		return NUM_SLOTS_NONE;
+	}
+	memset(instPtr->sendPktData, 0xCC, (size_t)(INTRA_SVC_FRAME_LENGTH_MAX));
+	switch(rtneEntry->slotType){
+	case SLOT_INTER_SVC:
+		L2_SetupNextSlot(instPtr, torState, L2_INTER_SVC_FRAME);
+		break;
+	case SLOT_INTRA_SVC:
+		if(torState == L2_TOR_TX){
+			//TODO: 
+			memset(instPtr->sendPktData, 0xAA, INTRA_SVC_FRAME_LENGTH_MAX);
+			// Pack PDU header
+			if(PduHeader_Packing(instPtr, svcMsg, L2_PDU_HEADER_0, rtneEntry->dst0) != SUCCESS){
+				DBG_ERROR("Failed to packing PduHeader.\n");
+				Status = FAILURE;
+				goto routine_err;
+			}
+			memcpy(instPtr->sendPktData, svcMsg->words, (size_t)(PDUH0_LEN/8));
+			// Pack UDU Header
+			if(UduHeader_Packing(instPtr, svcMsg, rtneEntry->dst0, 
+					INTRA_SVC_FRAME_LENGTH_MAX-(PDUH0_LEN+MSG_KEY_LENGTH_LEN)/8) 
+				!= SUCCESS){
+				DBG_ERROR("Failed to packing UduHeader.\n");
+				Status = FAILURE;
+				goto routine_err;
+			}
+			memcpy(instPtr->sendPktData + ((PDUH0_LEN+MSG_KEY_LENGTH_LEN)/8), svcMsg->words, (size_t)(UDUH_LEN/8));
+			// For ZhiQiang
+			// Payload Byte3, bit0~2: message class, bit3~7 message subclass
+			// FIXME: message class tag 0x01, only for test.
+			memset(instPtr->sendPktData+((PDUH0_LEN+MSG_KEY_LENGTH_LEN+UDUH_LEN)/8) + 3, 0x01, 1);
+			L2_CrcAppend(instPtr->sendPktData + ((PDUH0_LEN+MSG_KEY_LENGTH_LEN)/8),
+					INTRA_SVC_FRAME_LENGTH_MAX-(PDUH0_LEN+MSG_KEY_LENGTH_LEN+PDU_CRC_LEN)/8,
+					INTRA_SVC_FRAME_LENGTH_MAX-(PDUH0_LEN+MSG_KEY_LENGTH_LEN+PDU_CRC_LEN)/8,
+					L2_CRC16_8005
+			);
+		}
+		L2_SetupNextSlot(instPtr, torState, L2_INTRA_SVC_FRAME);
+		break;
+	default:
+		DBG_ERROR("UNKNOWN slot type [%d].\n", rtneEntry->slotType);
+		DBG_ERROR("Failed to packing PduHeader.\n");
+		Status = FAILURE;
+		goto routine_err;
+	}
+	bit_array_free(svcMsg);// free memory
+	return SUCCESS;
+routine_err:
+	bit_array_free(svcMsg);// free memory
+	return Status;
+}

datalink814_ge/src/linklayer/node_list.c

@@ -0,0 +1,477 @@
+/*****************************************************************************/
+/**
+ * Description: Implementations of 814 linklayer local record.
+ *
+ * Date: 2022-07-14 00:08
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-14 22:52
+ * Revisions: Rev 0.0
+ * History:
+ * [2022-07-14]: Initial version.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include <stdlib.h>
+#include <string.h>
+#include "linklayer814_types.h"
+#include "node_list.h"
+#include "../common.h"
+#include "../error.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+inline int32_t GetNodeNum(NODE_LIST *list) {
+	ASSERT(list != NULL);
+	return list->nodeNum;
+}
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+ * @brief   Initialize node list
+ *
+ * @param   list
+ *
+ * @return  SUCCESS
+ * 			ENOMEM - not enough memory.
+ *
+ ******************************************************************************/
+int32_t NodeList_Init(NODE_LIST **list) {
+	NODE_ENTRY *entry;
+	(*list) = malloc(sizeof(NODE_LIST));
+	if (*list == NULL) {
+		return ENOMEM;
+	}
+	entry = malloc(sizeof(NODE_ENTRY));
+	if(entry == NULL) {
+		free(*list);
+		return ENOMEM;
+	}
+	entry->nodeInfo.nodeId = 0;
+	entry->nextNode = entry;
+	entry->preNode = entry;
+	(*list)->head = entry;
+	(*list)->nodeNum = 0;
+	return SUCCESS;
+}
+
+void NodeList_Clear(NODE_LIST *list){
+	ASSERT(list != NULL);
+	NODE_ENTRY *nodeEntry, *deletEntry;
+	nodeEntry = list->head->nextNode;
+	while (nodeEntry != list->head) {
+		deletEntry = nodeEntry;
+		nodeEntry = nodeEntry->nextNode;
+		deletEntry->preNode->nextNode = deletEntry->nextNode;
+		deletEntry->nextNode->preNode = deletEntry->preNode;
+		DBG_INFO("Deleting node [%d].\n", deletEntry->nodeInfo.nodeId);
+		free(deletEntry);
+		list->nodeNum--;
+	}
+}
+
+void NodeList_Destroy(NODE_LIST *list){
+	if(list == NULL){
+		return;
+	}
+	NodeList_Clear(list);
+	free(list->head);
+	free(list);
+}
+/*****************************************************************************/
+/**
+ * @brief   Get node entry frome node list base on node id.
+ *
+ * @param   list
+ * @param   nodeId
+ *
+ * @return  Node entry
+ *          NULL if node dose not exist.
+ *
+ ******************************************************************************/
+NODE_ENTRY* GetNode(NODE_LIST *list, uint32_t nodeId) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = list->head->nextNode;
+	while (nodeEntry != list->head) {
+		if (nodeEntry->nodeInfo.nodeId == nodeId) {
+			break;
+		}
+		else {
+			nodeEntry = nodeEntry->nextNode;
+		}
+	}
+	if (nodeEntry == list->head) {
+		return NULL;
+	}
+	else {
+		return nodeEntry;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Check whether the node is already in the node list.
+ *
+ * @param   list
+ * @param   nodeId
+ *
+ * @return  true node in the list
+ *          false node not in the list
+ *
+ ******************************************************************************/
+inline bool IsNodeInList(NODE_LIST *list, uint8_t nodeId) {
+	ASSERT(list != NULL);
+	return (GetNode(list, nodeId) != NULL);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Append a new node entry to the node list
+ *
+ * @param   list
+ * @param   nodeId
+ * @param   nodeType
+ *
+ * @return  SUCCESS Node was added successfully.
+ *          Other       Error occurred.(Node already exist, memory alloc error ect.)
+ *
+ ******************************************************************************/
+int32_t AppendNode(NODE_LIST *list, uint8_t nodeId, L2_NODE_TYPE nodeType)
+{
+	ASSERT(list != NULL);
+	if(IsNodeInList(list, nodeId)){
+		DBG_WARNING("Node [%d] already exist.\n", nodeId);
+		return FAILURE;
+	}
+	DBG_INFO("Link layer appending node [%d] to node list.\n", nodeId);
+	NODE_ENTRY* nodeEntry = (NODE_ENTRY*) malloc(sizeof(NODE_ENTRY));
+	if (nodeEntry == NULL) {
+		return ENOMEM;
+	}
+	nodeEntry->nodeInfo.nodeId = nodeId;
+	nodeEntry->nodeInfo.nodeType = (uint8_t) nodeType;
+	nodeEntry->nodeInfo.pos.x = 0;
+	nodeEntry->nodeInfo.pos.y = 0;
+	nodeEntry->nodeInfo.pos.z = 0;
+	nodeEntry->nodeInfo.speed.x = 0;
+	nodeEntry->nodeInfo.speed.y = 0;
+	nodeEntry->nodeInfo.speed.z = 0;
+	nodeEntry->nodeInfo.beamNo = 0;
+	nodeEntry->ttlCnt = 0;
+
+	nodeEntry->nextNode = list->head;
+	nodeEntry->preNode = list->head->nextNode;
+	list->head->nextNode = nodeEntry;
+
+	list->nodeNum++;
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Delete a node in list based on node id.
+ *
+ * @param   list
+ * @param   nodeId
+ *
+ * @return  SUCCESS Node has been successfully deleted.
+ *          Other       Node not exist.
+ *
+ ******************************************************************************/
+int32_t DeletNode(NODE_LIST *list, uint8_t nodeId) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = GetNode(list, nodeId);
+	if(nodeEntry == NULL){
+		DBG_WARNING("Node [%d] in not in node list, skip deleting process.\n", nodeId);
+		return SUCCESS;
+	}
+	nodeEntry->preNode->nextNode = nodeEntry->nextNode;
+	nodeEntry->nextNode->preNode = nodeEntry->preNode;
+	DBG_INFO("Deleting node [%d].\n", nodeId);
+	free(nodeEntry);
+	list->nodeNum--;
+	return SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Get the distance between me and the node.
+ *
+ * @param   list
+ * @param   nodeId
+ * @param	dst     A pointer to store distance.
+ *
+ * @return  SUCCESS distance has been successfully store in dst
+ *          FAILURE Node dose not exit.
+ *
+ ******************************************************************************/
+
+int32_t GetDistance(NODE_LIST *list, COORD myCoord, uint8_t nodeId, double* dst) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = GetNode(list, nodeId);
+	if (nodeEntry == NULL) {
+		return FAILURE;
+	}
+	else {
+		*dst = Coord_Distance(myCoord, nodeEntry->nodeInfo.pos);
+		return SUCCESS;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Update node positions information.
+ *
+ * @param   list
+ * @param   nodeId
+ * @param   newPos A structure stores the corresponding node position info.
+ *
+ * @return  SUCCESS update successfully.
+ *          FAILURE node not exist.
+ *
+ ******************************************************************************/
+int32_t UpdateNodePos(NODE_LIST *list, uint8_t nodeId, const COORD *newPos) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = GetNode(list, nodeId);
+	if (nodeEntry == NULL) {
+		return FAILURE;
+	}
+	else {
+		memcpy(&(nodeEntry->nodeInfo.pos), newPos, sizeof(COORD));
+	}
+	return SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Get node positions information.
+ *
+ * @param   list
+ * @param   nodeId
+ * @param   newPos A structure stores the corresponding node position info.
+ *
+ * @return  SUCCESS update successfully.
+ *          FAILURE node not exist.
+ *
+ ******************************************************************************/
+int32_t GetNodePos(NODE_LIST *list, uint8_t nodeId, COORD *pos) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = GetNode(list, nodeId);
+	if (nodeEntry == NULL) {
+		return FAILURE;
+	}
+	else {
+		memcpy(pos, &(nodeEntry->nodeInfo.pos), sizeof(COORD));
+	}
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Update node speed information.
+ *
+ * @param   list
+ * @param   nodeId
+ * @param   newSpeed A structure stores the corresponding node speed info.
+ *
+ * @return  SUCCESS update successfully.
+ *          FAILURE node not exist.
+ *
+ ******************************************************************************/
+int32_t UpdateNodeSpeed(NODE_LIST *list, uint8_t nodeId, const COORD *newSpeed) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = GetNode(list, nodeId);
+	if (nodeEntry == NULL) {
+		return FAILURE;
+	}
+	else {
+		memcpy(&(nodeEntry->nodeInfo.speed), newSpeed, sizeof(COORD));
+	}
+	return SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Get node speed information.
+ *
+ * @param   list
+ * @param   nodeId
+ * @param   newSpeed A structure stores the corresponding node speed info.
+ *
+ * @return  SUCCESS update successfully.
+ *          FAILURE node not exist.
+ *
+ ******************************************************************************/
+int32_t GetNodeSpeed(NODE_LIST *list, uint8_t nodeId, COORD *speed) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = GetNode(list, nodeId);
+	if (nodeEntry == NULL) {
+		return FAILURE;
+	}
+	else {
+		memcpy(speed, &(nodeEntry->nodeInfo.speed), sizeof(COORD));
+	}
+	return SUCCESS;
+}
+/*****************************************************************************/
+/**
+ * @brief   Update node ACK status.
+ *
+ * @param   list
+ * @param   nodeId
+ * @param   defl
+ *
+ * @return  SUCCESS update successfully.
+ *          FAILURE Node not exist.
+ *
+ ******************************************************************************/
+int32_t UpdateNodeTimeDeviation(NODE_LIST *list, uint8_t nodeId, int32_t devi) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = GetNode(list, nodeId);
+	if (nodeEntry == NULL) {
+		return FAILURE;
+	}
+	else {
+		nodeEntry->timeDevi = devi;
+	}
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Increase TTL of specified node in the list.
+ *
+ * @param   list
+ * @param   inc		cnt of slot to add
+ * @param   nodeId
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+int32_t IncNodeTTL(NODE_LIST *list, uint8_t nodeId, uint32_t inc) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = GetNode(list, nodeId);
+	if (nodeEntry == NULL) {
+		return FAILURE;
+	}
+	else {
+		nodeEntry->ttlCnt += inc;
+	}
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Reset node TTL based on node id.
+ *
+ * @param   list
+ * @param   nodeId
+ *
+ * @return  SUCCESS TTL has been successfully cleared.
+ *          FAILURE Node not exist.
+ *
+ ******************************************************************************/
+int32_t RstNodeTTL(NODE_LIST *list, uint8_t nodeId) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = GetNode(list, nodeId);
+	if (nodeEntry == NULL) {
+		return FAILURE;
+	}
+	else {
+		nodeEntry->ttlCnt = 0;
+	}
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get TTL of specified node in the list.
+ *
+ * @param   list
+ * @param   nodeId
+ * @param	ttl
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+int32_t GetNodeTTL(NODE_LIST *list, uint8_t nodeId, uint32_t *ttl) {
+	ASSERT(list != NULL);
+	NODE_ENTRY* nodeEntry = GetNode(list, nodeId);
+	if (nodeEntry == NULL) {
+		return FAILURE;
+	}
+	else {
+		*ttl = nodeEntry->ttlCnt;
+	}
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Implements a edit operations to each node.
+ *
+ * @param   list
+ * @param	param
+ * @param   operation  A pointer to a function handled "NODE_ENTRY*" as input
+ *                  which defines the operations need to be apply.
+ *
+ * @return SUCCESS Operations has been applied successfully to all nodes.
+ *         Other       Error occurred.
+ *
+ ******************************************************************************/
+int32_t IterEditNode(NODE_LIST *list, const void *param, int32_t (*operation)(NODE_ENTRY *, const void *)) {
+	ASSERT(list != NULL);
+	int32_t Status = SUCCESS;
+	NODE_ENTRY *nodeEntry = list->head->nextNode;
+	while (nodeEntry != list->head) {
+		Status = operation(nodeEntry, param);
+		if(Status != SUCCESS){
+			break;
+		}
+		nodeEntry = nodeEntry->nextNode;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Filter all node, delete all the node not satisfied the condition.
+ *
+ * @param   list
+ * @param   condition  A pointer to a function handled "NODE_ENTRY*" as input
+ *                  which defines the condition need to be verify.
+ *
+ * @return SUCCESS
+ *
+ ******************************************************************************/
+int32_t IterDeleteNode(NODE_LIST *list, bool (*condition)(NODE_ENTRY *)) {
+	ASSERT(list != NULL);
+	NODE_ENTRY *nodeEntry, *deletEntry;
+	nodeEntry = list->head->nextNode;
+	while (nodeEntry != list->head) {
+		if (condition(nodeEntry) == false) {
+			deletEntry = nodeEntry;
+			nodeEntry = nodeEntry->nextNode;
+			deletEntry->preNode->nextNode = deletEntry->nextNode;
+			deletEntry->nextNode->preNode = deletEntry->preNode;
+			DBG_INFO("Deleting node [%d].\n", deletEntry->nodeInfo.nodeId);
+			free(deletEntry);
+			list->nodeNum--;
+		}
+		else {
+			nodeEntry = nodeEntry->nextNode;
+		}
+	}
+	return SUCCESS;
+}
+

datalink814_ge/src/linklayer/node_list.h

@@ -0,0 +1,67 @@
+/*****************************************************************************/
+/**
+ * Description: Header of 814 linklayer local record.
+ *
+ * Date: 2022-07-14 00:08
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-14 22:52
+ * Revisions: Rev 0.0
+ * History:
+ * [2022-07-14]: Initial version.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef NODE_LIST_H_
+#define NODE_LIST_H_
+#include <stdlib.h>
+#include <stdio.h>
+#include <math.h>
+#include <stdbool.h>
+#include "linklayer814_types.h"
+#include "geometry/coord.h"
+#include "../util/util.h"
+
+/************************** Constant Definitions *****************************/
+/***************** Macros (Inline Functions) Definitions *********************/
+/**************************** Type Definitions *******************************/
+typedef struct NODE_LIST_ENTRY {
+	L2_NODE_INFO nodeInfo;
+	uint32_t ttlCnt;
+	int32_t timeDevi;
+	struct NODE_LIST_ENTRY *nextNode;
+	struct NODE_LIST_ENTRY *preNode;
+} NODE_ENTRY;
+
+typedef struct {
+	uint32_t nodeNum;
+	NODE_ENTRY *head;
+} NODE_LIST;
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+int32_t NodeList_Init(NODE_LIST **list);
+void NodeList_Clear(NODE_LIST *list);
+void NodeList_Destroy(NODE_LIST *list);
+NODE_ENTRY *GetNode(NODE_LIST *list, uint32_t nodeId);
+int32_t AppendNode(NODE_LIST *list, uint8_t nodeId, L2_NODE_TYPE nodeType);
+int32_t DeletNode(NODE_LIST *list, uint8_t nodeId);
+int32_t UpdateNodePos(NODE_LIST *list, uint8_t nodeId, const COORD *newPos);
+int32_t GetNodePos(NODE_LIST *list, uint8_t nodeId, COORD *newPos);
+int32_t UpdateNodeSpeed(NODE_LIST *list, uint8_t nodeId, const COORD *newSpeed);
+int32_t GetNodeSpeed(NODE_LIST *list, uint8_t nodeId, COORD *speed);
+int32_t UpdateNodeTimeDeviation(NODE_LIST *list, uint8_t nodeId, int32_t devi);
+int32_t GetDistance(NODE_LIST *list, COORD myCoord, uint8_t nodeId, double* dst);
+int32_t GetNodeNum(NODE_LIST *list);
+int32_t RstNodeTTL(NODE_LIST *list, uint8_t nodeId);
+int32_t IncNodeTTL(NODE_LIST *list, uint8_t nodeId, uint32_t inc);
+int32_t GetNodeTTL(NODE_LIST *list, uint8_t nodeId, uint32_t *ttl);
+bool IsNodeInList(NODE_LIST *list, uint8_t nodeId);
+int32_t IterEditNode(NODE_LIST *list, const void *param, int32_t (*operation)(NODE_ENTRY*, const void*));
+int32_t IterDeleteNode(NODE_LIST *list, bool (*condition)(NODE_ENTRY *));
+
+#endif /* NODE_LIST_H_ */

datalink814_ge/src/linklayer/rtt.h

@@ -0,0 +1,102 @@
+/*****************************************************************************/
+/**
+ * Description: A simplified version of timesync for datalink 814 (Dijian)
+ * 
+ * Date: 2021-12-04 16:32
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-06 16:32
+ * Revisions: Rev 0.0
+ * History: 
+ * [2022-07-06]: Initial version.
+ * [2021-12-04]: Initial version.
+ * 
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+#ifndef RTT_H_
+#define RTT_H_
+
+/***************************** Include Files *********************************/
+#include <stdint.h>
+#include "linklayer814.h"
+#include "linklayer814_types.h"
+
+/************************** Constant Definitions *****************************/
+#define MAX_FREQ_EST_NUM 128 // 32bit word
+#define SVC_FREQ_EST_NUM 512 // byte
+#define MGMT_FREQ_EST_NUM 512 // byte
+#define BISAR_FREQ_EST_NUM 480 // byte
+
+#define CXR_FREQ 3800000000.0       // Hz
+
+#define LIGHT_SPPED_AIR 299702547.0 // m/s
+#define LIGHT_SPPED_VAC 299792458.0 // m/s
+
+#define RCV2FSYNC_CLOCKS 0 // clocks from frame sync time to receive time
+#define PHYRSP_DELAY_CLOCKS 0// clocks from frame sync time to receive time
+//#define PHY_SYNCT2FEND_200K 904052L
+//#define PHY_SYNCT2FEND_200K 924232L
+#define PHY_SYNCT2FEND_200K 905052L
+
+#define RTT_TIME_NONE	UINT32_MAX
+#define RTT_DOPPLER_NONE	UINT32_MAX
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+// TODO: Multi-node RTT
+typedef struct {
+	L2_TIME_WORD Tt1;
+	L2_TIME_WORD Tr1;
+	L2_TIME_WORD Tt2;
+	L2_TIME_WORD Tr2;
+	L2_TIME_WORD Tt3;
+	L2_TIME_WORD Tr3;
+	L2_TIME_WORD Tt4;
+	L2_TIME_WORD Tr4;
+	int32_t dopplerR1;
+	int32_t dopplerR2;
+	int32_t dopplerR3;
+	int32_t dopplerR4;
+	L2_TIME_WORD TroundA;
+	L2_TIME_WORD TreplyA;
+	L2_TIME_WORD TroundB;
+	L2_TIME_WORD TreplyB;
+	int32_t rttAdj;
+} RTT_RECORD;
+
+typedef enum {
+	RTT_NONE_STAGE = 0,
+	RTT_REQ1 = 1,
+	RTT_RSP1 = 2,
+	RTT_REQ2 = 3,
+	RTT_RSP2 = 4, // Rtt Stages
+} L2_RTT_SATGE;
+
+typedef struct {
+	L2_RCD rttStatge;
+	bool isR1Valid;
+	bool isR2Valid;
+	bool isR3Valid;
+	bool isR4Valid;
+	RTT_RECORD rttRecord;
+} L2_RTT_FSM;
+
+typedef enum {
+	RTT_NONE = 0,
+	RTT_SEND = 1,
+	RTT_RCV = 2,
+} L2_RTT_TOR;
+
+/************************** Function Prototypes ******************************/
+
+// RTT
+L2_RTT_SATGE RTT_GetLastStage(L2_RTT_FSM* rttFsmPtr);
+L2_RTT_SATGE RTT_GetCurrentStage(L2_RTT_FSM* rttFsmPtr);
+L2_RTT_SATGE RTT_GetNextStage(L2_RTT_FSM* rttFsmPtr);
+
+#endif /* RTT_H_ */

datalink814_ge/src/linklayer/time_sync.c

@@ -0,0 +1,523 @@
+/*****************************************************************************/
+/**
+ * Description: Time sync implementation file.
+ * 
+ * Author: Author's name
+ * Date: 2021-12-04 16:32
+ * LastEditors: FanHao
+ * LastEditTime: 2022-07-10 20:43
+ * Revisions: Rev 0.0
+ * History: 
+ * [2022-07-10]: New branch for Dijian.
+ * [2021-12-04]: Initial version.
+ * 
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include <string.h>
+#include <stdlib.h>
+#include "linklayer814.h"
+#include "rtt.h"
+#include "../time_ctrl/time_ctrl.h"
+#include "../error.h"
+#include "../common.h"
+
+/************************** Constant Definitions *****************************/
+/***************** Macros (Inline Functions) Definitions *********************/
+/**************************** Type Definitions *******************************/
+/************************** Variable Definitions *****************************/
+/************************** Function Prototypes ******************************/
+
+static void RTT_StageUpdate(L2_RTT_FSM* rttFsmPtr, L2_RTT_SATGE newSatge);
+static void RTT_ResetRecord(RTT_RECORD* recordPtr);
+static int32_t RTT_GetCounter10nsDeviation(PHY_INST *phyRef);
+
+
+/*****************************************************************************/
+/**
+ * @brief    a slot alignment, base on physical layer information.
+ *
+ * @param   instPtr	a pointer to linklayer layer instance
+ * @param   frameNum	
+ * @param   slotNum	
+ *
+ * @return  SUCCESS Initialize successfully.
+ *          FAILURE Initialization failed, allocate memory fail or initial
+ *          bram controller fail.
+ *
+ ******************************************************************************/
+// TODO: Check
+int32_t L2_TimeAlign(L2_INST* instPtr, uint32_t frameNum, uint32_t slotNum){
+	L1_FRAME_TYPE lastRecvdFrame;
+	lastRecvdFrame = Phy_GetLastRecvFrameType(instPtr->config.phyInstPtr);
+	if(lastRecvdFrame != L1_NONE_FRAME){
+		return EIGNORE;
+	}
+
+	// read nextSendTime from physical layer
+	uint64_t currTime, expctTime;
+	int64_t timeDiff;
+	TIME_WORD timeStamp, slotTimerAdjmet;
+	expctTime = ((uint64_t)(frameNum*L2_SLOTS_PER_FRAME + slotNum))*COUNTE_FRAC_MAX;
+	expctTime += Phy_GetTimeComp(lastRecvdFrame);
+
+	Phy_GetFrameSyncTimeStamp(instPtr->config.phyInstPtr, &timeStamp);
+	currTime = (uint64_t)timeStamp.frac_part;
+	currTime += ((uint64_t)timeStamp.int_part) * COUNTE_FRAC_MAX;
+
+	timeDiff = (int64_t)(expctTime - currTime);
+
+	slotTimerAdjmet.int_part = (uint32_t)(timeDiff/COUNTE_FRAC_MAX);
+	slotTimerAdjmet.frac_part = (uint32_t)(timeDiff%COUNTE_FRAC_MAX);
+	TimeCtrl_TimeAdjust(instPtr->config.tmcInstPtr, &slotTimerAdjmet, TM_ADJ_ADD);
+	return SUCCESS;
+}
+
+/**
+ * @brief   Get last RTT stage of a specified RTT descriptor.
+ */
+inline L2_RTT_SATGE RTT_GetLastStage(L2_RTT_FSM* rttFsmPtr){
+	ASSERT(rttFsmPtr != NULL);
+	return rttFsmPtr->rttStatge.last;
+}
+/**
+ * @brief   Get current RTT stage of a specified RTT descriptor.
+ */
+inline L2_RTT_SATGE RTT_GetCurrentStage(L2_RTT_FSM* rttFsmPtr){
+	ASSERT(rttFsmPtr != NULL);
+	return rttFsmPtr->rttStatge.curr;
+}
+/**
+ * @brief   Get next RTT stage of a specified RTT descriptor.
+ */
+inline L2_RTT_SATGE RTT_GetNextStage(L2_RTT_FSM* rttFsmPtr){
+	ASSERT(rttFsmPtr != NULL);
+	return rttFsmPtr->rttStatge.next;
+}
+/**
+ * @brief   Get next RTT stage of a specified RTT descriptor.
+ */
+static inline void RTT_ResetRecord(RTT_RECORD* recordPtr){
+	ASSERT(recordPtr != NULL);
+	memset(recordPtr, 0x00, sizeof(RTT_RECORD));
+	return;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Update corrent time-sync for RTT stage
+ *
+ * @param   scanFsmPtr  A pointer to scan net fsm.
+ *          newSatge    New state.
+ *
+ * @return  NONE.
+ *
+ ******************************************************************************/
+static void RTT_StageUpdate(L2_RTT_FSM* rttFsmPtr, L2_RTT_SATGE newSatge) {
+	ASSERT(rttFsmPtr != NULL);
+	ASSERT(newSatge >= RTT_NONE_STAGE && newSatge <= RTT_RSP2);
+	DBG_INFO("RTT current Stage: %u -> RTT new Stage: %u, Stage: arranged.%d.\n",
+			rttFsmPtr->rttStatge.curr, rttFsmPtr->rttStatge.next, newSatge);
+	L2_RcdShift(&(rttFsmPtr->rttStatge), newSatge);
+	return;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Reset RTT systerm .
+ *
+ * @param   rttFsmPtr
+ *
+ * @return  SUCCESS Initialization successful.
+ *          EMAC_MEMORY_ALLOC_ERROR Memory allocate error.
+ *
+ ******************************************************************************/
+void RTT_Reset(L2_RTT_FSM* rttFsmPtr){
+	ASSERT(rttFsmPtr != NULL);
+	RTT_ResetRecord(&(rttFsmPtr->rttRecord));
+	rttFsmPtr->rttStatge.last = RTT_NONE_STAGE;
+	rttFsmPtr->rttStatge.curr = RTT_NONE_STAGE;
+	rttFsmPtr->rttStatge.next = RTT_NONE_STAGE;
+	rttFsmPtr->isR1Valid = false;
+	rttFsmPtr->isR2Valid = false;
+	rttFsmPtr->isR3Valid = false;
+	rttFsmPtr->isR4Valid = false;
+}
+
+void RTT_Destroy(L2_RTT_FSM* rttFsmPtr){
+	free(rttFsmPtr);
+}
+
+
+static int32_t RTT_GetCounter10nsDeviation(PHY_INST *phyRef) {
+	TIME_WORD timeStamp;
+	int64_t lastFrameSyncT, lastSlotStartT;
+	Phy_GetFrameSyncTimeStamp(phyRef, &timeStamp);
+	lastFrameSyncT = (uint64_t) timeStamp.frac_part;
+	lastFrameSyncT += ((uint64_t)timeStamp.int_part) * COUNTE_FRAC_MAX;
+	Phy_GetLastSlotStartTimeStamp(phyRef, &timeStamp);
+	lastSlotStartT = (uint64_t) timeStamp.frac_part;
+	lastSlotStartT += ((uint64_t)timeStamp.int_part) * COUNTE_FRAC_MAX;
+	return (PHY_SYNCT2FEND_200K - (lastSlotStartT - lastFrameSyncT));
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Initialize RTT FSM, allocate memory for FSM instance.
+ *
+ * @param   rttFsmPtr
+ *
+ * @return  SUCCESS Initialization successful.
+ *          EMAC_MEMORY_ALLOC_ERROR Memory allocate error.
+ *
+ ******************************************************************************/
+int32_t RTT_Init(L2_RTT_FSM** rttFsmPtr){
+	(*rttFsmPtr) = (L2_RTT_FSM*) malloc(sizeof(L2_RTT_FSM));
+	if (*rttFsmPtr == NULL) {
+		free(*rttFsmPtr);
+		return EALLOC;
+	}
+	RTT_Reset(*rttFsmPtr);
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Execute a Time-Sync Process.
+ *
+ * @param   instPtr	a pointer to linklayer layer instance
+ *
+ * @return  SUCCESS Time-Sync Process Done.
+ *          FAILURE Time-Sync Process end with error.
+ *
+ ******************************************************************************/
+int32_t RTT_Proc(L2_INST* instPtr) {
+	ASSERT(instPtr != NULL);
+	L2_RTT_FSM* rttFsmPtr = L2_GetRttDesc(instPtr);
+	RTT_RECORD* rttRecord = &(rttFsmPtr->rttRecord);
+	PHY_INST *phyRef = instPtr->config.phyInstPtr;
+	int32_t Status = SUCCESS;
+	L2_RTT_TOR lastTor, nextTor;
+	if(instPtr->rtneConfig.last != NULL && instPtr->rtneConfig.last->slotType == SLOT_INTRA_TSYNC){
+		// Get last tor state
+		if(instPtr->rtneConfig.last->src0 == instPtr->myInfo.nodeId){
+			lastTor = RTT_SEND;
+		}
+		else if(instPtr->rtneConfig.last->dst0 == instPtr->myInfo.nodeId){
+			lastTor = RTT_RCV;
+		}
+		else{
+			lastTor = RTT_NONE;
+		}
+	}
+	else{
+		lastTor = RTT_NONE;
+	}
+
+	if(instPtr->rtneConfig.next != NULL && instPtr->rtneConfig.next->slotType == SLOT_INTRA_TSYNC){
+		// Get next tor state
+		if(instPtr->rtneConfig.next->src0 == instPtr->myInfo.nodeId){
+			nextTor = RTT_SEND;
+		}
+		else if(instPtr->rtneConfig.next->dst0 == instPtr->myInfo.nodeId){
+			nextTor = RTT_RCV;
+		}
+		else{
+			nextTor = RTT_NONE;
+		}
+	}
+	else{
+		nextTor = RTT_NONE;
+	}
+
+	DBG_INFO("-------- RTT Procedure --------\n");
+	// Stage trans
+	// For Head Node: Tx->Rx->Tx->Rx
+	if(instPtr->myInfo.nodeType == HEAD_NODE){
+		switch(rttFsmPtr->rttStatge.next) {
+		case RTT_NONE_STAGE :
+			DBG_INFO("RTT procedure start...\n");
+			// TODO
+//			RTT_ResetRecord(rttRecord);
+			RTT_StageUpdate(rttFsmPtr, RTT_REQ1);
+			break;
+		case RTT_REQ1 :
+			if(nextTor == RTT_SEND){
+				DBG_INFO("Prepare data for RTT REQ-1\n");
+				rttRecord->Tt1.timeH  = L2_GetNextFrameNum(instPtr)*L2_SLOTS_PER_FRAME + L2_GetNextSlotNum(instPtr);
+				rttRecord->Tt1.timeL = 0 ;
+				DBG_INFO("Tt1-timeL:%u.\n", rttRecord->Tt1.timeL);
+				DBG_INFO("Tt1-timeH:%u.\n", rttRecord->Tt1.timeH);
+				RTT_StageUpdate(rttFsmPtr, RTT_RSP1);
+			}
+			else{
+				DBG_INFO("Skip RTT slot, [Stage: %u].\n", rttFsmPtr->rttStatge.next);
+			}
+			break;
+		case RTT_RSP1 :
+			if(lastTor == RTT_RCV){
+				if(L2_isDataAvail(instPtr) == true){
+					DBG_INFO("RTT RSP-1 have been received.\n");
+					DBG_INFO("Preparing data for RTT REQ-2.\n");
+					rttFsmPtr->isR2Valid = true;
+					// Calculate doppler
+					double doppler = Phy_GetCoarseFreqEst(phyRef);
+					rttRecord->dopplerR2 = (int32_t)doppler;
+					DBG_INFO("rttRecord->dopplerR2: %u.\n", rttRecord->dopplerR2);
+
+					// Calculate last frame receive time.
+					int32_t counter10ns = RTT_GetCounter10nsDeviation(phyRef);
+					// response for rtt Adj
+					counter10ns += 10000;
+					counter10ns -= rttRecord->rttAdj;
+					if ( counter10ns < 0) {
+						counter10ns += COUNTE_FRAC_MAX;
+						rttRecord->Tr2.timeH -- ;
+						_nop_();
+					}
+					rttRecord->Tr2.timeH = L2_GetLastFrameNum(instPtr)*L2_SLOTS_PER_FRAME + L2_GetLastSlotNum(instPtr);
+					rttRecord->Tr2.timeL = (uint32_t)counter10ns;
+					DBG_INFO("Tr2-timeL:%u.\n", rttRecord->Tr2.timeL);
+					DBG_INFO("Tr2-timeH:%u.\n", rttRecord->Tr2.timeH);
+
+					// Calculate TroundA
+					rttRecord->TroundA.timeL = rttRecord->Tr2.timeL;
+					rttRecord->TroundA.timeH = rttRecord->Tr2.timeH - rttRecord->Tt1.timeH;
+					DBG_INFO("TroundA-timeL:%u.\n", rttRecord->TroundA.timeL);
+					DBG_INFO("TroundA-timeH:%u.\n", rttRecord->TroundA.timeH);
+				}
+				else{
+					rttFsmPtr->isR2Valid = false;
+					rttRecord->dopplerR2 = RTT_DOPPLER_NONE;
+					rttRecord->TroundA.timeL = RTT_TIME_NONE;
+					rttRecord->TroundA.timeH = RTT_TIME_NONE;
+					DBG_WARNING("RTT RSP-1 have not been received [Stage: %u].\n", rttFsmPtr->rttStatge.next);
+					DBG_WARNING("Set dopplerR2 and TroundA to dummy value.\n");
+					DBG_INFO("dopplerR2:%08X.\n", rttRecord->dopplerR2);
+					DBG_INFO("TroundA-timeL:%08X.\n", rttRecord->TroundA.timeL);
+					DBG_INFO("TroundA-timeH:%08X.\n", rttRecord->TroundA.timeH);
+				}
+				RTT_StageUpdate(rttFsmPtr, RTT_REQ2);
+			}
+			else{
+				DBG_INFO("Skip RTT slot, [Stage: %u].\n", rttFsmPtr->rttStatge.next);
+			}
+			break;
+		case RTT_REQ2 :
+			if(nextTor == RTT_SEND){
+				DBG_INFO("Prepare data for RTT REQ-2\n");
+				rttRecord->Tt3.timeH  = L2_GetNextFrameNum(instPtr)*L2_SLOTS_PER_FRAME + L2_GetNextSlotNum(instPtr);
+				rttRecord->Tt3.timeL = 0 ;
+				DBG_INFO("Tt3-timeL:%u.\n", rttRecord->Tt3.timeL);
+				DBG_INFO("Tt3-timeH:%u.\n", rttRecord->Tt3.timeH);
+
+				if ( rttFsmPtr->isR2Valid ) {
+					// Calculate reply A
+					rttRecord->TreplyA.timeL = COUNTE_FRAC_MAX - rttRecord->Tr2.timeL;
+					rttRecord->TreplyA.timeH = rttRecord->Tt3.timeH - rttRecord->Tr2.timeH - 1;
+					DBG_INFO("TreplyA-timeL:%u.\n", rttRecord->TreplyA.timeL);
+					DBG_INFO("TreplyA-timeH:%u.\n", rttRecord->TreplyA.timeH);
+				}
+				else {
+					rttRecord->TreplyA.timeL = RTT_TIME_NONE;
+					rttRecord->TreplyA.timeH = RTT_TIME_NONE;
+					DBG_WARNING("RTT RSP-1 have not been received [Stage: %u].\n", rttFsmPtr->rttStatge.next);
+					DBG_WARNING("Set TreplyA to dummy value.\n");
+					DBG_INFO("TreplyA-timeL:%08X.\n", rttRecord->TreplyA.timeL);
+					DBG_INFO("TreplyA-timeH:%08X.\n", rttRecord->TreplyA.timeH);
+				}
+				RTT_StageUpdate(rttFsmPtr, RTT_RSP2);
+			}
+			else{
+				DBG_INFO("Skip RTT slot, [Stage: %u].\n", rttFsmPtr->rttStatge.next);
+			}
+			break;
+		case RTT_RSP2 :
+			if(lastTor == RTT_RCV){
+				if(L2_isDataAvail(instPtr) == true){
+					DBG_INFO("RTT RSP-2 have been received.\n");
+					rttFsmPtr->isR4Valid = true;
+					// Calculate doppler
+					double doppler = Phy_GetCoarseFreqEst(phyRef);
+					rttRecord->dopplerR2 = (int32_t)doppler;
+					DBG_INFO("rttRecord->dopplerR2: %d.\n", rttRecord->dopplerR2);
+
+					// Calculate last frame receive time.
+					int32_t counter10ns = RTT_GetCounter10nsDeviation(phyRef);
+					if ( counter10ns < 0) {
+						counter10ns += COUNTE_FRAC_MAX;
+						rttRecord->Tr4.timeH -- ;
+					}
+					rttRecord->Tr2.timeH = L2_GetLastFrameNum(instPtr)*L2_SLOTS_PER_FRAME + L2_GetLastSlotNum(instPtr);
+					// Get a cnt with clk of 192MHz
+					rttRecord->Tr4.timeL = (uint32_t)counter10ns;
+					DBG_INFO("Tr4-timeL:%u.\n", rttRecord->Tr4.timeL);
+					DBG_INFO("Tr4-timeH:%u.\n", rttRecord->Tr4.timeH);
+				}
+				else{
+					rttFsmPtr->isR4Valid = false;
+					rttRecord->Tr4.timeL = RTT_TIME_NONE;
+					rttRecord->Tr4.timeH = RTT_TIME_NONE;
+					DBG_WARNING("RTT RSP-2 have not been received [Stage: %u].\n", rttFsmPtr->rttStatge.next);
+					DBG_WARNING("Set Tr4 to dummy value.\n");
+					DBG_INFO("Tr4-timeL:%08X.\n", rttRecord->Tr4.timeL);
+					DBG_INFO("Tr4-timeH:%08X.\n", rttRecord->Tr4.timeH);
+				}
+				RTT_StageUpdate(rttFsmPtr, RTT_NONE_STAGE);
+				DBG_INFO("RTT procedure end...\n");
+			}
+			break;
+		default :
+			break;
+		}
+	}
+	// For Member Node: Rx->Tx->Rx->Tx
+	else{
+		switch (rttFsmPtr->rttStatge.next) {
+		case RTT_NONE_STAGE :
+			DBG_INFO("RTT procedure start...\n");
+			// TODO
+//			RTT_ResetRecord(rttRecord);
+			RTT_StageUpdate(rttFsmPtr, RTT_REQ1);
+			break;
+		case RTT_REQ1 :
+			if(lastTor == RTT_RCV){
+				if(L2_isDataAvail(instPtr) == true){
+					DBG_INFO("RTT REQ-1 have been received.\n");
+					DBG_INFO("Preparing data for RTT RSP-1.\n");
+					rttFsmPtr->isR2Valid = true;
+					// Calculate doppler
+					double doppler = Phy_GetCoarseFreqEst(phyRef);
+					rttRecord->dopplerR2 = (int32_t)doppler;
+					DBG_INFO("rttRecord->dopplerR2: %d.\n", rttRecord->dopplerR2);
+
+					// Calculate last frame receive time.
+					int32_t counter10ns = RTT_GetCounter10nsDeviation(phyRef);
+					if ( counter10ns < 0) {
+						counter10ns += COUNTE_FRAC_MAX;
+						rttRecord->Tr1.timeH -- ;
+					}
+					rttRecord->Tr1.timeH = L2_GetLastFrameNum(instPtr)*L2_SLOTS_PER_FRAME + L2_GetLastSlotNum(instPtr);
+					rttRecord->Tr1.timeL = (uint32_t)counter10ns;
+					DBG_INFO("Tr1-timeL:%u.\n", rttRecord->Tr1.timeL);
+					DBG_INFO("Tr1-timeH:%u.\n", rttRecord->Tr1.timeH);
+				}
+				else{
+					rttFsmPtr->isR1Valid = false;
+					rttRecord->dopplerR1 = RTT_DOPPLER_NONE;
+					rttRecord->Tr1.timeL = RTT_TIME_NONE;
+					rttRecord->Tr1.timeH = RTT_TIME_NONE;
+					DBG_WARNING("RTT REQ-1 have not been received [Stage: %u].\n", rttFsmPtr->rttStatge.next);
+					DBG_WARNING("Set dopplerR1 and Tr1 to dummy value.\n");
+					DBG_INFO("dopplerR1:%08X.\n", rttRecord->dopplerR1);
+					DBG_INFO("Tr1-timeL:%08X.\n", rttRecord->Tr1.timeL);
+					DBG_INFO("Tr1-timeH:%08X.\n", rttRecord->Tr1.timeH);
+				}
+				RTT_StageUpdate(rttFsmPtr, RTT_RSP1);
+			}
+			break;
+		case RTT_RSP1 :
+			if(nextTor == RTT_SEND){
+				DBG_INFO("Prepare data for RTT RSP-1\n");
+				rttRecord->Tt2.timeH  = L2_GetNextFrameNum(instPtr)*L2_SLOTS_PER_FRAME + L2_GetNextSlotNum(instPtr);
+				rttRecord->Tt2.timeL = 0 ;
+				DBG_INFO("Tt2-timeL:%u.\n", rttRecord->Tt2.timeL);
+				DBG_INFO("Tt2-timeH:%u.\n", rttRecord->Tt2.timeH);
+
+				if ( rttFsmPtr->isR1Valid ) {
+					// Calculate reply B
+					rttRecord->TreplyB.timeL = COUNTE_FRAC_MAX - rttRecord->Tr1.timeL;
+					rttRecord->TreplyB.timeH = rttRecord->Tt2.timeH - rttRecord->Tr1.timeH - 1;
+					DBG_INFO("TreplyB-timeL:%u.\n", rttRecord->TreplyB.timeL);
+					DBG_INFO("TreplyB-timeH:%u.\n", rttRecord->TreplyB.timeH);
+				}
+				else {
+					rttRecord->TreplyB.timeL = RTT_TIME_NONE;
+					rttRecord->TreplyB.timeH = RTT_TIME_NONE;
+					DBG_WARNING("RTT REQ-1 have not been received [Stage: %u].\n", rttFsmPtr->rttStatge.next);
+					DBG_WARNING("Set ReplayB to dummy value.\n");
+					DBG_INFO("TreplyB-timeL:%08X.\n", rttRecord->TreplyB.timeL);
+					DBG_INFO("TreplyB-timeH:%08X.\n", rttRecord->TreplyB.timeH);
+				}
+				RTT_StageUpdate(rttFsmPtr, RTT_REQ2);
+			}
+			break;
+		case RTT_REQ2 :
+			if(lastTor == RTT_RCV){
+				if(L2_isDataAvail(instPtr) == true){
+					DBG_INFO("RTT REQ-2 have been received.\n");
+					DBG_INFO("Preparing data for RTT RSP-2.\n");
+					rttFsmPtr->isR3Valid = true;
+
+					// Calculate doppler
+					double doppler = Phy_GetCoarseFreqEst(phyRef);
+					rttRecord->dopplerR2 = (int32_t)doppler;
+					DBG_INFO("rttRecord->dopplerR2: %d.\n", rttRecord->dopplerR2);
+
+					// Calculate last frame receive time.
+					int32_t counter10ns = RTT_GetCounter10nsDeviation(phyRef);
+					if ( counter10ns < 0) {
+						counter10ns += COUNTE_FRAC_MAX;
+						rttRecord->Tr3.timeH -- ;
+					}
+					rttRecord->Tr3.timeL = (uint32_t)counter10ns;
+					DBG_INFO("Tr3-timeL:%u.\n", rttRecord->Tr3.timeL);
+					DBG_INFO("Tr3-timeH:%u.\n", rttRecord->Tr3.timeH);
+
+					// Calculate TroundB
+					rttRecord->TroundB.timeL = rttRecord->Tr3.timeL;
+					rttRecord->TroundB.timeH = rttRecord->Tr3.timeH - rttRecord->Tt2.timeH;
+					DBG_INFO("TroundB-timeL:%u.\n", rttRecord->TroundB.timeL);
+					DBG_INFO("TroundB-timeH:%u.\n", rttRecord->TroundB.timeH);
+				}
+				else{
+					rttFsmPtr->isR3Valid = false;
+					rttRecord->dopplerR3 = RTT_DOPPLER_NONE;
+					rttRecord->TroundB.timeL = RTT_TIME_NONE;
+					rttRecord->TroundB.timeH = RTT_TIME_NONE;
+					DBG_WARNING("RTT REQ-2 have not been received [Stage: %u].\n", rttFsmPtr->rttStatge.next);
+					DBG_WARNING("Set dopplerR3 and ReplayB to dummy value.\n");
+					DBG_INFO("dopplerR3:%08X.\n", rttRecord->dopplerR3);
+					DBG_INFO("TroundB-timeL:%08X.\n", rttRecord->TroundB.timeL);
+					DBG_INFO("TroundB-timeH:%08X.\n", rttRecord->TroundB.timeH);
+				}
+				RTT_StageUpdate(rttFsmPtr, RTT_RSP2);
+			}
+			break;
+		case RTT_RSP2 :
+			if(nextTor == RTT_SEND){
+				DBG_INFO("Prepare data for RTT RSP-2\n");
+				rttRecord->Tt4.timeH  = L2_GetNextFrameNum(instPtr)*L2_SLOTS_PER_FRAME + L2_GetNextSlotNum(instPtr);
+				rttRecord->Tt4.timeL = 0;
+				DBG_INFO("Tt4-timeL:%u.\n", rttRecord->Tt4.timeL);
+				DBG_INFO("Tt4-timeH:%u.\n", rttRecord->Tt4.timeH);
+
+				if ( rttFsmPtr->isR3Valid ) {
+					// Calculate reply B
+					rttRecord->TreplyB.timeL = COUNTE_FRAC_MAX - rttRecord->Tr3.timeL;
+					rttRecord->TreplyB.timeH = rttRecord->Tt4.timeH - rttRecord->Tr3.timeH - 1;
+					DBG_INFO("TreplyB-timeL:%u.\n", rttRecord->TreplyB.timeL);
+					DBG_INFO("TreplyB-timeH:%u.\n", rttRecord->TreplyB.timeH);
+					// TODO implement a time adjustment.
+					DBG_INFO("RTT procedure end...\n");
+				}
+				else {
+					rttRecord->TreplyB.timeL = RTT_TIME_NONE;
+					rttRecord->TreplyB.timeH = RTT_TIME_NONE;
+					DBG_WARNING("RTT REQ-2 have not been received [Stage: %u].\n", rttFsmPtr->rttStatge.next);
+					DBG_WARNING("Set ReplayB to dummy value.\n");
+					DBG_INFO("TreplyB-timeL:%08X.\n", rttRecord->TreplyB.timeL);
+					DBG_INFO("TreplyB-timeH:%08X.\n", rttRecord->TreplyB.timeH);
+				}
+				RTT_StageUpdate(rttFsmPtr, RTT_NONE_STAGE);
+			}
+			break;
+		default :
+			break;
+		}
+	}
+	return Status;
+}

datalink814_ge/src/lscript.ld

@@ -0,0 +1,292 @@
+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version: 2019.1.3                                               */
+/*                                                                 */
+/* Copyright (c) 2010-2016 Xilinx, Inc.  All rights reserved.      */
+/*                                                                 */
+/* Description : Cortex-A9 Linker Script                           */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x40000;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   phy_data_interface_tx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
+   phy_data_interface_ant_info_bram_ctrl_Mem0 : ORIGIN = 0x42000000, LENGTH = 0x2000
+   mpc_bram_interface_mpc_bram_ctrl_Mem0 : ORIGIN = 0x44000000, LENGTH = 0x8000
+   phy_data_interface_rx_frame_bram_ctrl_Mem0 : ORIGIN = 0x46000000, LENGTH = 0x2000
+   ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
+   ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
+   ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
+   ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+   KEEP (*(.vectors))
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.vfp11_veneer)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+} > ps7_ddr_0
+
+.init : {
+   KEEP (*(.init))
+} > ps7_ddr_0
+
+.fini : {
+   KEEP (*(.fini))
+} > ps7_ddr_0
+
+.rodata : {
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > ps7_ddr_0
+
+.rodata1 : {
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > ps7_ddr_0
+
+.sdata2 : {
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   __sdata2_end = .;
+} > ps7_ddr_0
+
+.sbss2 : {
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > ps7_ddr_0
+
+.data : {
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   __data_end = .;
+} > ps7_ddr_0
+
+.data1 : {
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > ps7_ddr_0
+
+.got : {
+   *(.got)
+} > ps7_ddr_0
+
+.ctors : {
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > ps7_ddr_0
+
+.dtors : {
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > ps7_ddr_0
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > ps7_ddr_0
+
+.eh_frame : {
+   *(.eh_frame)
+} > ps7_ddr_0
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > ps7_ddr_0
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > ps7_ddr_0
+
+.mmu_tbl (ALIGN(16384)) : {
+   __mmu_tbl_start = .;
+   *(.mmu_tbl)
+   __mmu_tbl_end = .;
+} > ps7_ddr_0
+
+.ARM.exidx : {
+   __exidx_start = .;
+   *(.ARM.exidx*)
+   *(.gnu.linkonce.armexidix.*.*)
+   __exidx_end = .;
+} > ps7_ddr_0
+
+.preinit_array : {
+   __preinit_array_start = .;
+   KEEP (*(SORT(.preinit_array.*)))
+   KEEP (*(.preinit_array))
+   __preinit_array_end = .;
+} > ps7_ddr_0
+
+.init_array : {
+   __init_array_start = .;
+   KEEP (*(SORT(.init_array.*)))
+   KEEP (*(.init_array))
+   __init_array_end = .;
+} > ps7_ddr_0
+
+.fini_array : {
+   __fini_array_start = .;
+   KEEP (*(SORT(.fini_array.*)))
+   KEEP (*(.fini_array))
+   __fini_array_end = .;
+} > ps7_ddr_0
+
+.ARM.attributes : {
+   __ARM.attributes_start = .;
+   *(.ARM.attributes)
+   __ARM.attributes_end = .;
+} > ps7_ddr_0
+
+.sdata : {
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > ps7_ddr_0
+
+.sbss (NOLOAD) : {
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   __sbss_end = .;
+} > ps7_ddr_0
+
+.tdata : {
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > ps7_ddr_0
+
+.tbss : {
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > ps7_ddr_0
+
+.bss (NOLOAD) : {
+   __bss_start = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   __bss_end = .;
+} > ps7_ddr_0
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(16);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+   HeapLimit = .;
+} > ps7_ddr_0
+
+.stack (NOLOAD) : {
+   . = ALIGN(16);
+   _stack_end = .;
+   . += _STACK_SIZE;
+   . = ALIGN(16);
+   _stack = .;
+   __stack = _stack;
+   . = ALIGN(16);
+   _irq_stack_end = .;
+   . += _IRQ_STACK_SIZE;
+   . = ALIGN(16);
+   __irq_stack = .;
+   _supervisor_stack_end = .;
+   . += _SUPERVISOR_STACK_SIZE;
+   . = ALIGN(16);
+   __supervisor_stack = .;
+   _abort_stack_end = .;
+   . += _ABORT_STACK_SIZE;
+   . = ALIGN(16);
+   __abort_stack = .;
+   _fiq_stack_end = .;
+   . += _FIQ_STACK_SIZE;
+   . = ALIGN(16);
+   __fiq_stack = .;
+   _undef_stack_end = .;
+   . += _UNDEF_STACK_SIZE;
+   . = ALIGN(16);
+   __undef_stack = .;
+} > ps7_ddr_0
+
+_end = .;
+}
+

datalink814_ge/src/main.c

@@ -0,0 +1,422 @@
+/*****************************************************************************/
+/**
+ * Description: main.c
+ *
+
+ * Date: 2021-11-13 13:19
+ * Last Editors: Fan Hao
+ * Last Edit Time: [2022-03-28 20:32]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2021-11-13]: Initial edition.
+ * [2022-03-28]: Add bit error test mode.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include <stdint.h>
+#include "config/app_config.h"
+#include "xscugic.h"        // The generic interrupt controller driver component
+#include "xil_exception.h"  // ARM Cortex A9 specific exception related APIs
+#include "xgpio.h"
+#include "sleep.h"          // Sleep APIs for Cortex A9
+#include "xil_cache.h"
+#include "linklayer/linklayer814.h"
+#include "linklayer/msg_def.h"
+#include "phy_ctrl/phy_ctrl.h"
+#include "bit_array/bit_array.h"
+#include "mpc/mpc_ctrl.h"
+
+#ifdef _MPC_CTRL
+#include "./mpc/mpc_ctrl.h"
+#endif
+
+#include "hardware/headless.h"
+
+/************************** Constant Definitions *****************************/
+L2_CONFIG l2Config = {
+	.myType = MEMBER_NODE,
+	.isInterHead = false,
+	.myId = 2,
+	.clustId = 1,
+	.headId = 1,
+	.bkpHeadId = 1,
+	.netScale = 2,
+	.phyInstPtr = NULL,
+	.tmcInstPtr = NULL
+};
+
+TIMECTRL_CONFIG tmcConfig = {
+	.baseAddr = TIME_CONTROLLER_BASEADDR,
+	.reset = 10
+};
+
+PHY_CONFIG l1Config = {
+	.devId = PHY_DEVICE_ID,
+	.txBramId = TXBUFF_BRAM_ID,
+	.rxBramId = RXBUFF_BRAM_ID,
+	.antBramId = ANTCONFIG_BRAM_ID,
+	.baseAddr = PHY_CTRL_BASEADDR
+};
+MPC_CONFIG mpcConfig = {
+	.bramDevId = MPC_PCIE_BRAM_ID,
+	.msgLenMax = MPC_BUFFER_LENGTH //byte
+};
+static bool mpcStatusUpAssert = false;
+/************************** Function Prototypes ******************************/
+int SetupInterruptSystem(XScuGic* instPtr, uint32_t devId);
+void PeriodicPull_Handler(void *callBackRef);
+#ifdef _MPC_CTRL
+void MPC_IntrHandler(void* CallBackRef);
+#endif
+
+/*********************** Driver Instance Definitions **************************/
+TIMECTRL_INST* tmcInstPtr = NULL;
+PHY_INST* phyInstPtr = NULL;
+L2_INST* linkInstPtr = NULL;
+static XScuGic gicInst; //General interrupt controller intance
+// FIXME: Only for test...
+XGpio configGpio; /* The Instance of the GPIO Driver */
+/****************************************************************************/
+/**
+ * This function is responsible for initializing the SCUGIC instance, looking
+ * for the device configuration based on the unique device ID, initializing a
+ * SCUGIC instance, and initialize the interrupt at IRQ_F2P[0:0]
+ *
+ * @param    devId is the XPAR_<GPIO_instance>_DEVICE_ID value from
+ *           "xparameters.h".
+ * @param    instPtr is a reference to the XScuGic driver Instance.
+ *
+ * @return  SUCCESS if initialize successful.
+ *          FAILURE if initialization failed.
+ *
+ *****************************************************************************/
+int SetupInterruptSystem(XScuGic* instPtr, uint32_t devId){
+	XScuGic_Config *configPtr;
+	int Status;
+	uint32_t intrState;
+	// Initialize the GIC instance.
+	configPtr = XScuGic_LookupConfig(devId);
+	Status = XScuGic_CfgInitialize(instPtr, configPtr,
+			configPtr->CpuBaseAddress);
+	if (Status != SUCCESS) {
+		return Status;
+	}
+
+	// Perform a self-test to ensure that the hardware was built correctly.
+	Status = XScuGic_SelfTest(instPtr);
+	if (Status != SUCCESS) {
+		return Status;
+	}
+	// Clear any pending interrupt flags
+	intrState = XScuGic_CPUReadReg(instPtr, XSCUGIC_INT_ACK_OFFSET);
+	XScuGic_CPUWriteReg(instPtr, XSCUGIC_EOI_OFFSET, intrState);
+	/*
+	 * FOR PRIORITY:
+	 * 0 is highest priority, 0xF8(248) is lowest. There are 32 priority levels
+	 * supported with a step of 8. Hence the supported priorities are 0, 8, 16,
+	 * 32, 40 ..., 248.
+	 *
+	 * FOR TRIGGER:
+	 * SFI    Read Only   b10 always
+	 * PPI    Read Only   depending on how the PPIs are configured.
+	 *                    b01    Active HIGH level sensitive
+	 *                    b11 Rising edge sensitive
+	 * SPI                LSB is read only.
+	 *                    b01    Active HIGH level sensitive
+	 *                    b11 Rising edge sensitive
+	 */
+	/* Set the priority of IRQ_F2P[1:1] to 0x00 (highest) and a trigger for a
+	 * rising edge 0x03.
+	 */
+
+	// Initialize physical layer interrupt.
+	XScuGic_SetPriorityTriggerType(instPtr, PERIODIC_5MS_INTR_ID, 0x00, 0x03);
+
+	// Connect the interrupt service routine isr1 to the interrupt controller
+	Status = XScuGic_Connect(instPtr, PERIODIC_5MS_INTR_ID,
+			(Xil_ExceptionHandler) PeriodicPull_Handler, (void *) instPtr);
+	if (Status != SUCCESS) {
+		return Status;
+	}
+	XScuGic_Enable(instPtr, PERIODIC_5MS_INTR_ID);
+
+#ifdef _MPC_CTRL
+	// Initialize MPC interrupt.
+	XScuGic_SetPriorityTriggerType(instPtr, MPC_RX_DONE_INTR_ID, 0x00, 0x03);
+	// Connect the interrupt service routine isr1 to the interrupt controller
+	Status = XScuGic_Connect(instPtr, MPC_RX_DONE_INTR_ID,
+			(Xil_ExceptionHandler) MPC_IntrHandler, (void *) instPtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+	XScuGic_Enable(instPtr, MPC_RX_DONE_INTR_ID);
+#endif
+
+	/* Initialize the exception table and register the interrupt controller
+	 * handler with the exception table
+	 */
+	Xil_ExceptionInit();
+
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+			(Xil_ExceptionHandler) XScuGic_InterruptHandler,
+			(void *) instPtr);
+
+	// Enable non-critical exceptions
+	Xil_ExceptionEnable();
+
+	return Status;
+} // SetupInterruptSystem
+
+
+
+#ifdef _MPC_CTRL
+void MPC_PCIESentStart(){
+	uint32_t GpioConfig = XGpio_DiscreteRead(&configGpio, 2);
+	GpioConfig ^= 0x00000002;
+	XGpio_DiscreteWrite(&configGpio, 2, GpioConfig);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Handler of mater pc contrl interrupt.
+ *
+ * @param   CallBackRef A pointer to corresponding frame UART instance.
+ *
+ * @return  None.
+ *
+ ******************************************************************************/
+void MPC_IntrHandler(void* CallBackRef) {
+	MPC_MsgHandler(mpcInstPtr);
+}
+#endif
+
+/****************************************************************************/
+/**
+ * This function is a interrupt service routine for IRQ_F2P[1:1], IRQ_F2P[1:1]
+ * tells CPU that the data in OCM is ready!
+ *
+ * @param    callBackRef is the SCUGIC instance pointer.
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ *****************************************************************************/
+void PeriodicPull_Handler(void *callBackRef) {
+	int32_t Status;
+	Phy_UpdateState(phyInstPtr);
+	uint32_t GpioConfig = XGpio_DiscreteRead(&configGpio, 2);
+	if(phyInstPtr->TOR.curr == PHY_TOR_TX){
+		switch(phyInstPtr->frameType.curr){
+		case L1_1M2BPS_5MS_FRAME:
+			mpcRecord->frame1Sent ++ ;
+			break;
+		case L1_200KBPS_5MS_FRAME:
+			mpcRecord->frame2Sent ++ ;
+			break;
+		case L1_40KBPS_10MS_FRAME:
+			mpcRecord->frame3Sent ++ ;
+			break;
+		case L1_40KBPS_20MS_FRAME:
+			mpcRecord->frame4Sent ++ ;
+			break;
+		case L1_10KBPS_20MS_FRAME:
+			mpcRecord->frame5Sent ++ ;
+			break;
+		case L1_2KBPS_100MS_FRAME:
+			mpcRecord->frame6Sent ++ ;
+			break;
+		case L1_10KBPS_10MS_FRAME:
+			mpcRecord->frame7Sent ++ ;
+			break;
+		case L1_2KBPS_20MS_FRAME:
+			mpcRecord->frame8Sent ++ ;
+			break;
+		default:
+			break;
+		}
+	}
+	if(phyInstPtr->TOR.last == PHY_TOR_RX && phyInstPtr->isFrameSync){
+		switch(phyInstPtr->frameType.last){
+		case L1_1M2BPS_5MS_FRAME:
+			mpcRecord->frame1Recv ++ ;
+			break;
+		case L1_200KBPS_5MS_FRAME:
+			mpcRecord->frame2Recv ++ ;
+			break;
+		case L1_40KBPS_10MS_FRAME:
+			mpcRecord->frame3Recv ++ ;
+			break;
+		case L1_40KBPS_20MS_FRAME:
+			mpcRecord->frame4Recv ++ ;
+			break;
+		case L1_10KBPS_20MS_FRAME:
+			mpcRecord->frame5Recv ++ ;
+			break;
+		case L1_2KBPS_100MS_FRAME:
+			mpcRecord->frame6Recv ++ ;
+			break;
+		case L1_10KBPS_10MS_FRAME:
+			mpcRecord->frame7Recv ++ ;
+			break;
+		case L1_2KBPS_20MS_FRAME:
+			mpcRecord->frame8Recv ++ ;
+			break;
+		default:
+			break;
+		}
+	}
+
+	Status = Linklayer_Proc(linkInstPtr);
+	if(Status != SUCCESS){
+		DBG_ERROR("Link layer runs failed, with error code: %ld\n", Status);
+		_nop_();
+	}
+
+	if(L2_isDataAvail(linkInstPtr) == true ){
+		GpioConfig^=0x00000001;
+	}
+
+	if (linkInstPtr->slotNum.next % DATA_STORE_INTERVAL == 1) {
+		mpcStatusUpAssert = true;
+		mpcRecord->frame1Cnt = mpcRecord->frame1Recv - mpcRecord->frame1CntLast;
+		mpcRecord->frame2Cnt = mpcRecord->frame2Recv - mpcRecord->frame2CntLast;
+		mpcRecord->frame3Cnt = mpcRecord->frame3Recv - mpcRecord->frame3CntLast;
+		mpcRecord->frame4Cnt = mpcRecord->frame4Recv - mpcRecord->frame4CntLast;
+		mpcRecord->frame5Cnt = mpcRecord->frame5Recv - mpcRecord->frame5CntLast;
+		mpcRecord->frame6Cnt = mpcRecord->frame6Recv - mpcRecord->frame6CntLast;
+		mpcRecord->frame7Cnt = mpcRecord->frame7Recv - mpcRecord->frame7CntLast;
+		mpcRecord->frame8Cnt = mpcRecord->frame8Recv - mpcRecord->frame8CntLast;
+
+		// Store last time received frame number
+		mpcRecord->frame1CntLast = mpcRecord->frame1Recv;
+		mpcRecord->frame2CntLast = mpcRecord->frame2Recv;
+		mpcRecord->frame3CntLast = mpcRecord->frame3Recv;
+		mpcRecord->frame4CntLast = mpcRecord->frame4Recv;
+		mpcRecord->frame5CntLast = mpcRecord->frame5Recv;
+		mpcRecord->frame6CntLast = mpcRecord->frame6Recv;
+		mpcRecord->frame7CntLast = mpcRecord->frame7Recv;
+		mpcRecord->frame8CntLast = mpcRecord->frame8Recv;
+	}
+
+	// TODO: Dijian frequency pattern TX_RX State.
+	GpioConfig ^= 0x80000000;
+	GpioConfig = (phyInstPtr->TOR.next == PHY_TOR_TX) ? GpioConfig|0x40000000 : GpioConfig&0xBFFFFFFF;
+	XGpio_DiscreteWrite(&configGpio, 2, GpioConfig);
+}  // PhyIntr_Handler
+
+/*****************************************************************************/
+/**
+ * @brief	Main function, initialize all the device needed, initialize
+ * 			interrupt system, halt in while(1) wait for event interrupt.
+ *
+ * @param   None.
+ *
+ * @return
+ *
+ ******************************************************************************/
+int main(void) {
+	int Status;
+	Status = HARDWARE_initialize();
+	if (Status == SUCCESS) {
+		DBG_PRINT("Hardware Init SUCCESS! \n");
+	}
+	else {
+		DBG_PRINT("Hardware Init FAILED! \n");
+		return Status;
+	}
+
+	Status = XGpio_Initialize(&configGpio, XPAR_CONFIG_GPIO_DEVICE_ID);
+	if (Status != SUCCESS) {
+		DBG_PRINT("Config Gpio Initialization Failed\n");
+		return FAILURE;
+	}
+	XGpio_SetDataDirection(&configGpio, 1, 0xFFFFFFFF);
+	XGpio_SetDataDirection(&configGpio, 2, 0x00000000);
+
+	// Init time controller
+	Status = TimeCtrl_Init(&tmcInstPtr, &tmcConfig);
+	if (Status == SUCCESS) {
+		DBG_PRINT("TmcCtrl Init SUCCESS! \n");
+	}
+	else {
+		DBG_PRINT("TmcCtrl Init FAILED! \n");
+		return Status;
+	}
+
+	// Init physical layer
+	Status = Phy_InstInit(&phyInstPtr, &l1Config);
+	if (Status == SUCCESS) {
+		DBG_PRINT("PhyCtrl Init SUCCESS! \n");
+	}
+	else {
+		DBG_PRINT("PhyCtrl Init FAILED! \n");
+		return Status;
+	}
+
+	// Update l2 config
+	l2Config.phyInstPtr = phyInstPtr;
+	l2Config.tmcInstPtr = tmcInstPtr;
+
+	Status = Linklayer_Init(&linkInstPtr, &l2Config);
+	if (Status == SUCCESS) {
+		DBG_PRINT("LinkLayer Init SUCCESS! \n");
+	}
+	else {
+		DBG_PRINT("Linklayer Init FAILED! \n");
+		return Status;
+	}
+
+	// Init MPC
+	Status = MPC_Init(&mpcInstPtr, &mpcConfig);
+	if (Status == SUCCESS) {
+		DBG_PRINT("MPC Init SUCCESS! \n");
+	}
+	else {
+		DBG_PRINT("MPC Init FAILED! \n");
+		return Status;
+	}
+
+	// Initialize GIC.
+	Status = SetupInterruptSystem(&gicInst ,SCUGIC_DEVICE_ID);
+	if (Status == SUCCESS) {
+		DBG_PRINT("Intc Init SUCCESS! \n");
+	}
+	else {
+		DBG_PRINT("Intc Init FAILED! \n");
+		return Status;
+	}
+
+	Status = Phy_SetMode(phyInstPtr, PHY_MODE_SCHEDULE);
+	if (Status == SUCCESS) {
+		DBG_PRINT("Physical Mode %u Setup SUCCESS! \n", PHY_MODE_LISTEN);
+	}
+	else {
+		DBG_PRINT("Physical Mode %u Setup FAILED! \n", PHY_MODE_LISTEN);
+		return Status;
+	}
+
+	DBG_PRINT("Starting Physical Layer...");
+	Phy_Start(phyInstPtr);
+
+	Linklayer_Start(linkInstPtr);
+
+	while(true) {
+		if (mpcStatusUpAssert == true) {
+			mpcStatusUpAssert = false;
+			if (linkInstPtr->buffSwitch == 0) {
+				MPC_StateUpload(mpcInstPtr, linkInstPtr->mgmtMsgRecvBuff1, linkInstPtr->mgmtMsgRecvCnt1,
+						linkInstPtr->svcMsgRecvBuff1, linkInstPtr->svcMsgRecvCnt1, &(linkInstPtr->mgmtNetFSM->mgmtMsgLog));
+			}
+			else {
+				MPC_StateUpload(mpcInstPtr, linkInstPtr->mgmtMsgRecvBuff0, linkInstPtr->mgmtMsgRecvCnt0,
+						linkInstPtr->svcMsgRecvBuff0, linkInstPtr->svcMsgRecvCnt0, &(linkInstPtr->mgmtNetFSM->mgmtMsgLog));
+			}
+		}
+	}
+} // main

datalink814_ge/src/mpc/mpc_ctrl.c

@@ -0,0 +1,474 @@
+/*****************************************************************************/
+/**
+ * Description: A brief description of this file
+ * 
+ * Date: 2022-01-19 00:54
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-03-28 20:24
+ * Revisions: Rev 0.0
+ * History: 
+ * [2022-01-19]: Initial version.
+ * [2022-03-28]: Add general information print function.
+ * 
+ * Copyright(c) 2022 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+#include <inttypes.h>
+#include <string.h>
+#include "mpc_ctrl.h"
+#include "mpc_msg_def.h"
+#include "../error.h"
+#include "../config/app_config.h"
+#include "../bit_array/bit_array.h"
+#include "../util/util.h"
+#include "../linklayer/linklayer814.h"
+#include "../linklayer/msg_def.h"
+#include "../linklayer/node_list.h"
+#include "../linklayer/rtt.h"
+#ifdef _MPC_CTRL
+
+#define STATE_STROAGE_BUFF_MAX 32768 // 32K Bytes
+
+static int32_t MPC_InsertChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t chunk);
+static int32_t MPC_GetChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t* chunk);
+
+#ifdef _MPC_UART
+#include <frame_uart.h>
+
+//...
+#endif //_MPC_CTRL
+
+#ifdef _MPC_PCIE
+#include "../phy_ctrl/phy_ctrl.h"
+
+extern L2_CONFIG l2Config;
+extern PHY_INST* phyInstPtr;
+extern L2_INST* linkInstPtr;
+
+MPC_INST* mpcInstPtr = NULL;
+MPC_RECORD* mpcRecord = NULL;
+BIT_ARRAY* mpcTxMsgBuff = NULL;
+BIT_ARRAY* mpcRxMsgBuff = NULL;
+
+static MPC_MSG_HEADER mpcHeader = {
+	.head = 0x5302,
+};
+
+
+/*****************************************************************************/
+/**
+ * @brief   Insert a data chunk to a bit array.
+ *
+ * @param   bitarr	pointer to target bit array.
+ *          offset	offset of insert start position.
+ *          numBit	number of insert bits
+ *          chunk	64 bit data chunk, contains the data should be stored
+ *          		in LSB style.
+ *
+ * @return	FAILURE	insert operation exceed bit array size.
+ * 			SUCCESS
+ *
+ ******************************************************************************/
+static int32_t MPC_InsertChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t chunk){
+	ASSERT(bitarr != NULL);
+	if(bitarr->num_of_bits < offset+numBit){
+		return FAILURE;
+	}
+	bit_array_set_wordn(bitarr, offset, chunk, numBit);
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get a data chunk to a bit array.
+ *
+ * @param   bitarr	pointer to target bit array.
+ *          offset	offset of data chunk start position.
+ *          numBit	number of data chunk
+ *          chunk	pointer to a 64 bit data chunk container, data will be stored
+ *          		in LSB style.
+ *
+ * @return	FAILURE	 read operation exceed bit array size.
+ * 			SUCCESS
+ *
+ ******************************************************************************/
+static int32_t MPC_GetChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t* chunk){
+	ASSERT(bitarr != NULL);
+	if(bitarr->num_of_bits < offset+numBit || numBit > 64){
+		return FAILURE;
+	}
+	*chunk = bit_array_get_wordn(bitarr, offset, numBit);
+	return SUCCESS;
+}
+
+static uint32_t MPC_GetMsgLen(MPC_MSG_TYPE type){
+	switch(type){
+	case MPC_MSG_TEST:
+		return (MPC_MSG_TEST_LEN/8);
+	case MPC_MSG_STATE:
+		return (MPC_MSG_STATE_LEN/8);
+	default:
+		return MPC_MSG_LEN_NONE;
+	}
+}
+/*****************************************************************************/
+/**
+ * @brief   Initialize mpc instance, apply customize configurations.
+ *
+ * @param   instPtr	pointer mpc descriptor.
+ *          configPtr	pointer to mpc configurations.
+ *
+ * @return	SUCCESS	 MPC init successfully.
+ * 			error code.
+ *
+ ******************************************************************************/
+int MPC_Init(MPC_INST** instPtr, MPC_CONFIG* configPtr){
+	ASSERT(instPtr != NULL);
+	ASSERT(configPtr != NULL);
+	int Status = SUCCESS;
+	XBram_Config *bramConfigPtr;
+	(*instPtr) = (MPC_INST*)malloc(sizeof(MPC_INST));
+	if((*instPtr) == NULL){
+		Status = EALLOC;
+		goto init_failed;
+	}
+	(*instPtr)->configs.bramDevId = configPtr->bramDevId;
+	(*instPtr)->configs.msgLenMax = configPtr->msgLenMax;
+
+	bramConfigPtr = XBram_LookupConfig(configPtr->bramDevId);
+	if (bramConfigPtr == NULL) {
+		Status = EDINVAL;
+		goto init_failed;
+	}
+	Status = XBram_CfgInitialize(&((*instPtr)->pcieBram), bramConfigPtr,
+			bramConfigPtr->CtrlBaseAddress);
+	if (Status != SUCCESS) {
+		goto init_failed;
+	}
+	/* Execute the BRAM driver selftest. */
+	Status = XBram_SelfTest(&((*instPtr)->pcieBram), 0);
+	if (Status != SUCCESS) {
+		goto init_failed;
+	}
+	(*instPtr)->txBaseAddr = (uint8_t*)((*instPtr)->pcieBram.Config.MemBaseAddress);
+	(*instPtr)->rxBaseAddr = (uint8_t*)((*instPtr)->pcieBram.Config.MemBaseAddress);
+
+	mpcRecord = (MPC_RECORD*) malloc(sizeof(MPC_RECORD));
+	if(mpcRecord == NULL){
+		Status = EALLOC;
+		goto init_failed;
+	}
+
+	memset(mpcRecord, 0x00, sizeof(MPC_RECORD));
+
+	mpcTxMsgBuff = bit_array_create(STATE_STROAGE_BUFF_MAX*8);
+	if(mpcTxMsgBuff == NULL){
+		goto init_failed;
+	}
+	mpcRxMsgBuff = bit_array_create(MPC_MSG_LEN_MAX);
+	if(mpcRxMsgBuff == NULL){
+		goto init_failed;
+	}
+	return Status;
+
+init_failed:
+	free(*instPtr);
+	free(mpcRecord);
+	free(mpcTxMsgBuff);
+	free(mpcRxMsgBuff);
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Handle a mpc message in rx buffer.
+ *
+ * @param   instPtr	pointer mpc descriptor.
+ *
+ * @return	SUCCESS	 MPC handler runs successfully.
+ * 			error code.
+ *
+ ******************************************************************************/
+int MPC_MsgHandler(MPC_INST* instPtr){
+	ASSERT(instPtr != NULL);
+	MPC_MSG_HEADER* pktHeader = (MPC_MSG_HEADER*)(instPtr->rxBaseAddr);
+	// instPtr->txBaseAddr + MPC_MSG_HEAD_LEN;
+	uint64_t dataChunk = 0;
+	switch(pktHeader->type){
+		case MPC_MSG_TEST_CODE:
+			memcpy(mpcRxMsgBuff->words,
+					instPtr->rxBaseAddr + (MPC_MSG_HEAD_LEN/8),
+					DIV_ROUND_UP(MPC_MSG_TEST_LEN,8));
+			MPC_GetChunk(mpcRxMsgBuff, TEST_REQ_CMD_OFFSET, TEST_REQ_CMD_LEN, &dataChunk);
+			if((uint8_t)dataChunk == TEST_REQ_CMD_START){
+				MPC_GetChunk(mpcRxMsgBuff, TEST_MODE_SET_OFFSET, TEST_MODE_SET_LEN, &dataChunk);
+				// FIXME
+				if((uint8_t)dataChunk == TEST_MODE_HEAD){
+					l2Config.myType = HEAD_NODE;
+					l2Config.myId = 1;
+				}
+				else{
+					l2Config.myType = MEMBER_NODE;
+					l2Config.myId = 2;
+				}
+				MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_FPGA_ST_OFFSET, TEST_REQ_FPGA_ST_LEN, 0x01);
+				MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_AD_ST_OFFSET, TEST_REQ_AD_ST_LEN, 0x01);
+				MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_RF_ST_OFFSET, TEST_REQ_RF_ST_LEN, 0x01);
+				MPC_SendMsg(instPtr, MPC_MSG_TEST, (uint8_t*)mpcTxMsgBuff->words, MPC_MSG_TEST_LEN);
+				Linklayer_Reconfig(linkInstPtr, &l2Config);
+				Linklayer_Start(linkInstPtr);
+			}
+			else if((uint8_t)dataChunk == TEST_REQ_CMD_END){
+				MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_FPGA_ST_OFFSET, TEST_REQ_FPGA_ST_LEN, 0x00);
+				MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_AD_ST_OFFSET, TEST_REQ_AD_ST_LEN, 0x00);
+				MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_RF_ST_OFFSET, TEST_REQ_RF_ST_LEN, 0x00);
+				MPC_SendMsg(instPtr, MPC_MSG_TEST, (uint8_t*)mpcTxMsgBuff->words, MPC_MSG_TEST_LEN);
+				memset(mpcRecord, 0x00, sizeof(MPC_RECORD));
+				memset((uint8_t*)mpcTxMsgBuff->words,0x00,STATE_STROAGE_BUFF_MAX);
+				Linklayer_Halt(linkInstPtr);
+				MPC_SendMsg(instPtr, MPC_MSG_STATE, (uint8_t*)mpcTxMsgBuff->words, STATE_STROAGE_BUFF_MAX);
+				Phy_SetupNextSlot(phyInstPtr, PHY_TOR_SUSPEND, L1_200KBPS_5MS_FRAME, NULL); // any frame type is okay
+
+			}
+			else{
+				DBG_WARNING("Unexpected self-test command.\n");
+			}
+			break;
+		case MPC_MSG_TSYNC_CODE:
+			memcpy(mpcRxMsgBuff->words,
+					instPtr->rxBaseAddr + ((MPC_MSG_HEAD_LEN/8)/2),
+					DIV_ROUND_UP(MPC_MSG_TSYNC_LEN,8));
+			//FIXME:
+//			MPC_GetChunk(mpcRxMsgBuff, RTT_ADJ_OFFSET, RTT_ADJ_LEN, &dataChunk);
+//			rttRecord->rttAdj = (double)dataChunk ;
+//			MPC_GetChunk(mpcRxMsgBuff, TSYNC_ADJ_OFFSET, TSYNC_ADJ_LEN, &dataChunk);
+//			double tsyncAdj = (double)dataChunk * 0.192;
+			//FIXME:
+//			PhyWrite(TSYNC_PULS_ADJ, (uint32_t)tsyncAdj);
+//			MPC_GetChunk(mpcRxMsgBuff, DOPPLER_OFFSET, DOPPLER_LEN, &dataChunk);
+//			double dopplerAdj = (double)((dataChunk << 32)/192000000) ;
+//			PhyWrite(DOPPLER_ADJ, (uint32_t)dopplerAdj);
+			break;
+		default:
+			DBG_ERROR("Unknown message type code: %04X.\n\r", pktHeader->type);
+			return EPARAM;
+	}
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Encapsulate upload a packet to master pc, upload content defined
+ * 			in the mpc message protocols.
+ *
+ * @param   instPtr	pointer mpc descriptor.
+ * 			type	packet type
+ * 			buffer	pinter to send packet buffer.
+ * 			dlen	length of data need to be sent.
+ *
+ * @return	SUCCESS	 MPC handler runs successfully.
+ * 			error code.
+ *
+ ******************************************************************************/
+int MPC_SendMsg(MPC_INST* instPtr, MPC_MSG_TYPE type, uint8_t* buffer, uint32_t dlen){
+	ASSERT(instPtr != NULL);
+	if(buffer == NULL ||
+		dlen >= instPtr->configs.msgLenMax ||
+		(type <= MPC_MSG_NONE || type > MPC_MSG_STATE)){
+		return EPARAM;
+	}
+	if(instPtr->pcieBram.IsReady == false){
+		return EDINVAL;
+	}
+	int Status = SUCCESS;
+	switch(type){
+	case MPC_MSG_TEST:
+		mpcHeader.type = MPC_MSG_TEST_CODE;
+		break;
+	case MPC_MSG_STATE:
+		mpcHeader.type = MPC_MSG_STATE_CODE;
+		break;
+	default:
+		DBG_ERROR("Unknown mpc message type: %d.\n", type);
+		break;
+	}
+	memcpy(instPtr->txBaseAddr, &mpcHeader, MPC_MSG_HEAD_LEN/8);
+	memcpy(instPtr->txBaseAddr + (MPC_MSG_HEAD_LEN/8), buffer, dlen);
+	MPC_PCIESentStart();
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief	Upload current state to master pc.(content detail defined in mpc
+ * 			mesage protocol)
+ *
+ * @param   instPtr	pointer mpc descriptor.
+ *
+ * @return	SUCCESS	 MPC handler runs successfully.
+ * 			error code.
+ *
+ ******************************************************************************/
+int MPC_StateUpload(MPC_INST* instPtr ,  uint8_t* mgmtBuffer , uint32_t mgmtMsgCnt ,
+					 uint8_t* svcBuffer  , uint32_t svcMsgCnt  , MGMT_MSG_RECORD* mgmtMsg){
+	ASSERT(instPtr != NULL);
+	int32_t Status = SUCCESS;
+	uint64_t dataChunk = 0;
+	if(instPtr->pcieBram.IsReady == false){
+		return EDINVAL;
+	}
+
+	// Stage
+	switch (linkInstPtr->mainState) {
+	case INIT_STATE :
+		dataChunk = STATE_STAGE_SETUP;
+		break;
+	case INTRA_SEEK_STATE:
+		dataChunk = STATE_STAGE_RTNE;
+		break;
+	case NORMAL_STATE :
+		dataChunk = STATE_STAGE_SVC;
+		break;
+	default:
+		return EUNEXP;
+	}
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_STAGE_OFFSET, STATE_STAGE_LEN, dataChunk);
+
+	// Net setup time
+	dataChunk = (L2_GetNextFrameNum(linkInstPtr) - linkInstPtr->netStartTime) * 1000 + L2_GetNextSlotNum(linkInstPtr) * 5 ;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_SETUP_TIME_OFFSET, STATE_SETUP_TIME_LEN, dataChunk);
+	// number of nodes
+	dataChunk = GetNodeNum(linkInstPtr->nodeList);
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_NUM_NODE_OFFSET, STATE_NUM_NODE_LEN, dataChunk);
+
+	// frame 1 counter
+	dataChunk = mpcRecord->frame1Cnt;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_1_CNT_OFFSET, STATE_FRAME_1_CNT_LEN, dataChunk);
+	// frame 2 counter
+	dataChunk = mpcRecord->frame2Cnt;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_2_CNT_OFFSET, STATE_FRAME_2_CNT_LEN, dataChunk);
+	// frame 3 counter
+	dataChunk = mpcRecord->frame3Cnt;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_3_CNT_OFFSET, STATE_FRAME_3_CNT_LEN, dataChunk);
+	// frame 4 counter
+	dataChunk = mpcRecord->frame4Cnt;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_4_CNT_OFFSET, STATE_FRAME_4_CNT_LEN, dataChunk);
+	// frame 5 counter
+	dataChunk = mpcRecord->frame5Cnt;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_5_CNT_OFFSET, STATE_FRAME_5_CNT_LEN, dataChunk);
+	// frame 6 counter
+	dataChunk = mpcRecord->frame6Cnt;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_6_CNT_OFFSET, STATE_FRAME_6_CNT_LEN, dataChunk);
+	// frame 7 counter
+	dataChunk = mpcRecord->frame7Cnt;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_7_CNT_OFFSET, STATE_FRAME_7_CNT_LEN, dataChunk);
+	// frame 8 counter
+	dataChunk = mpcRecord->frame8Cnt;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_8_CNT_OFFSET, STATE_FRAME_8_CNT_LEN, dataChunk);
+
+	// frame 1 sent counter
+	dataChunk = mpcRecord->frame1Sent;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_1_SENT_OFFSET, STATE_FRAME_1_SENT_LEN, dataChunk);
+	// frame 2 sent counter
+	dataChunk = mpcRecord->frame2Sent;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_2_SENT_OFFSET, STATE_FRAME_2_SENT_LEN, dataChunk);
+	// frame 3 sent counter
+	dataChunk = mpcRecord->frame3Sent;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_3_SENT_OFFSET, STATE_FRAME_3_SENT_LEN, dataChunk);
+	// frame 4 sent counter
+	dataChunk = mpcRecord->frame4Sent;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_4_SENT_OFFSET, STATE_FRAME_4_SENT_LEN, dataChunk);
+	// frame 5 sent counter
+	dataChunk = mpcRecord->frame5Sent;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_5_SENT_OFFSET, STATE_FRAME_5_SENT_LEN, dataChunk);
+	// frame 6 sent counter
+	dataChunk = mpcRecord->frame6Sent;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_6_SENT_OFFSET, STATE_FRAME_6_SENT_LEN, dataChunk);
+	// frame 7 sent counter
+	dataChunk = mpcRecord->frame7Sent;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_7_SENT_OFFSET, STATE_FRAME_7_SENT_LEN, dataChunk);
+	// frame 8 sent counter
+	dataChunk = mpcRecord->frame8Sent;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_8_SENT_OFFSET, STATE_FRAME_8_SENT_LEN, dataChunk);
+
+	// frame 1 received counter
+	dataChunk = mpcRecord->frame1Recv;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_1_RECV_OFFSET, STATE_FRAME_1_RECV_LEN, dataChunk);
+	// frame 2 received counter
+	dataChunk = mpcRecord->frame2Recv;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_2_RECV_OFFSET, STATE_FRAME_2_RECV_LEN, dataChunk);
+	// frame 3 received counter
+	dataChunk = mpcRecord->frame3Recv;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_3_RECV_OFFSET, STATE_FRAME_3_RECV_LEN, dataChunk);
+	// frame 4 received counter
+	dataChunk = mpcRecord->frame4Recv;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_4_RECV_OFFSET, STATE_FRAME_4_RECV_LEN, dataChunk);
+	// frame 5 received counter
+	dataChunk = mpcRecord->frame5Recv;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_5_RECV_OFFSET, STATE_FRAME_5_RECV_LEN, dataChunk);
+	// frame 6 received counter
+	dataChunk = mpcRecord->frame6Recv;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_6_RECV_OFFSET, STATE_FRAME_6_RECV_LEN, dataChunk);
+	// frame 7 received counter
+	dataChunk = mpcRecord->frame7Recv;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_7_RECV_OFFSET, STATE_FRAME_7_RECV_LEN, dataChunk);
+	// frame 8 received counter
+	dataChunk = mpcRecord->frame8Recv;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_8_RECV_OFFSET, STATE_FRAME_8_RECV_LEN, dataChunk);
+
+	// Trajectory pos X
+	dataChunk = mgmtMsg->Longitude % 1000 ;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_TRAJ_X_OFFSET, STATE_TRAJ_X_LEN, dataChunk);
+	// Trajectory pos Y
+	dataChunk = mgmtMsg->Latitude % 1000 ;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_TRAJ_Y_OFFSET, STATE_TRAJ_Y_LEN, dataChunk);
+	// Trajectory alpha
+	dataChunk = 45;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_TRAJ_ALPHA_OFFSET, STATE_TRAJ_ALPHA_LEN, dataChunk);
+
+	// TODO : Currently DJ is node 1 , only Byte 1 is activate , others is useless
+	// Topo node 1
+	dataChunk = BIT(linkInstPtr->myInfo.nodeId - 1);
+	if (GetNodeNum(linkInstPtr->nodeList) > 1 ) {
+		for(int i = 1; i <= linkInstPtr->config.netScale; i++){
+			if (IsNodeInList(linkInstPtr->nodeList, i)) {
+				dataChunk |= BIT(i-1);
+			}
+		}
+	}
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_TOPO_1_OFFSET, STATE_TOPO_1_LEN, dataChunk);
+	// Topo node 2
+	dataChunk = 0x00;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_TOPO_2_OFFSET, STATE_TOPO_2_LEN, dataChunk);
+	// Topo node 3
+	dataChunk = 0x00;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_TOPO_3_OFFSET, STATE_TOPO_3_LEN, dataChunk);
+	// Topo node 4
+	dataChunk = 0x00;
+	MPC_InsertChunk(mpcTxMsgBuff, STATE_TOPO_4_OFFSET, STATE_TOPO_4_LEN, dataChunk);
+
+	// Mgmt message Number
+	dataChunk = mgmtMsgCnt;
+	MPC_InsertChunk(mpcTxMsgBuff, MGMT_MSG_NUM_OFFSET, MGMT_MSG_NUM_LEN, dataChunk);
+
+	// Svc message Number
+	dataChunk = svcMsgCnt;
+	MPC_InsertChunk(mpcTxMsgBuff, SVC_MSG_NUM_OFFSET, SVC_MSG_NUM_LEN, dataChunk);
+
+	// Copy msg data
+	size_t svcLen = mgmtMsgCnt*(72/8*6);
+	size_t mgmtLen = svcMsgCnt*(2040/8);
+	memcpy(((uint8_t*)mpcTxMsgBuff->words) + MPC_MSG_STATE_LEN/8, mgmtBuffer, svcLen);
+	memcpy(((uint8_t*)mpcTxMsgBuff->words) + MPC_MSG_STATE_LEN/8 + mgmtMsgCnt*(72/8*6),
+			svcBuffer, mgmtLen);
+
+	Status = MPC_SendMsg(instPtr, MPC_MSG_STATE,(uint8_t*)mpcTxMsgBuff->words, MPC_MSG_STATE_LEN/8 + svcLen + mgmtLen);
+//	Status = MPC_SendMsg(instPtr, MPC_MSG_STATE,(uint8_t*)stateMsg->words, MPC_MSG_STATE_LEN/8);
+	return Status;
+}
+
+#endif //_MPC_PCIE
+#endif //_MPC_CTRL

datalink814_ge/src/mpc/mpc_ctrl.h

@@ -0,0 +1,106 @@
+/*****************************************************************************/
+/**
+ * Description: A brief description of this file
+ * 
+ * Date: 2022-01-19 00:54
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-03-28 20:24
+ * Revisions: Rev 0.0
+ * History: 
+ * [2022-01-19]: Initial version.
+ * [2022-03-28]: Add general information print function.
+ * 
+ * Copyright(c) 2022 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+#ifndef MPC_CTRL_H_
+#define MPC_CTRL_H_
+
+#include <inttypes.h>
+#include "../config/app_config.h"
+#ifdef _MPC_CTRL
+#ifdef _MPC_UART
+//...
+#endif //_MPC_UART
+
+#ifdef _MPC_PCIE
+#include "xbram.h"
+#include "../phy_ctrl/phy_ctrl.h"
+#include "../linklayer/linklayer814.h"
+
+typedef struct {
+	const uint16_t head;
+	uint16_t type;
+	uint8_t reserve[4];
+} MPC_MSG_HEADER;
+
+typedef struct{
+	uint32_t bramDevId;
+	uint32_t msgLenMax;
+} MPC_CONFIG;
+
+typedef struct{
+	MPC_CONFIG configs;
+	XBram pcieBram;
+	uint8_t* txBaseAddr;
+	uint8_t* rxBaseAddr;
+} MPC_INST;
+
+typedef enum{
+	MPC_MSG_NONE = 0,
+	MPC_MSG_TEST = 1,
+	MPC_MSG_STATE = 2,
+} MPC_MSG_TYPE;
+
+// FIXME: Simplify this part.
+typedef struct {
+	uint8_t frame1Cnt;
+	uint8_t frame2Cnt;
+	uint8_t frame3Cnt;
+	uint8_t frame4Cnt;
+	uint8_t frame5Cnt;
+	uint8_t frame6Cnt;
+	uint8_t frame7Cnt;
+	uint8_t frame8Cnt;
+	uint8_t frame1CntLast;
+	uint8_t frame2CntLast;
+	uint8_t frame3CntLast;
+	uint8_t frame4CntLast;
+	uint8_t frame5CntLast;
+	uint8_t frame6CntLast;
+	uint8_t frame7CntLast;
+	uint8_t frame8CntLast;
+	uint16_t frame1Sent;
+	uint16_t frame2Sent;
+	uint16_t frame3Sent;
+	uint16_t frame4Sent;
+	uint16_t frame5Sent;
+	uint16_t frame6Sent;
+	uint16_t frame7Sent;
+	uint16_t frame8Sent;
+	uint16_t frame1Recv;
+	uint16_t frame2Recv;
+	uint16_t frame3Recv;
+	uint16_t frame4Recv;
+	uint16_t frame5Recv;
+	uint16_t frame6Recv;
+	uint16_t frame7Recv;
+	uint16_t frame8Recv;
+} MPC_RECORD;
+
+
+extern void MPC_PCIESentStart();
+extern MPC_RECORD* mpcRecord;
+extern MPC_INST* mpcInstPtr;
+
+int MPC_Init(MPC_INST** instPtr, MPC_CONFIG* configPtr);
+int MPC_MsgHandler(MPC_INST* instPtr);
+int MPC_StateUpload(MPC_INST* instPtr ,  uint8_t* mgmtBuffer , uint32_t mgmtMsgCnt
+			, uint8_t* svcBuffer , uint32_t svcMsgCnt , MGMT_MSG_RECORD* mgmtmsg);
+int MPC_SendMsg(MPC_INST* instPtr, MPC_MSG_TYPE type, uint8_t* buffer, uint32_t dlen);
+
+#endif //_MPC_PCIE
+#endif //_MPC_CTRL
+#endif //MPC_CTRL_H_

datalink814_ge/src/mpc/mpc_msg_def.h

@@ -0,0 +1,134 @@
+/*
+ * mpc_msg_def.h
+ *
+ *  Created on: Sep 19, 2022
+ */
+
+#ifndef _MPC_MSG_DEF
+#define _MPC_MSG_DEF
+#define MPC_MSG_HEAD_LEN 64 //bit
+#define MPC_MSG_LEN_MAX 1024 //bit
+#define MPC_MSG_LEN_NONE UINT32_MAX
+
+// ** Self Test Message ** //
+// Type code
+#define MPC_MSG_TEST_CODE 0x00AA
+#define MPC_MSG_TEST_LEN 128 // bit
+// data segment - self test request message.
+#define TEST_REQ_CMD_OFFSET 0
+#define TEST_REQ_CMD_LEN 8
+#define TEST_REQ_CMD_START 0xAA
+#define TEST_REQ_CMD_END 0xFF
+#define TEST_MODE_SET_OFFSET 8
+#define TEST_MODE_SET_LEN 8
+#define TEST_MODE_HEAD 0x01
+#define TEST_MODE_MEMBER 0x02
+// data segment - self test response message.
+#define TEST_REQ_FPGA_ST_OFFSET 0
+#define TEST_REQ_FPGA_ST_LEN 8
+#define TEST_REQ_AD_ST_OFFSET 8
+#define TEST_REQ_AD_ST_LEN 8
+#define TEST_REQ_RF_ST_OFFSET 16
+#define TEST_REQ_RF_ST_LEN 8
+
+// ** State Report Message ** //
+// Type code
+#define MPC_MSG_STATE_CODE 0x00FF
+#define MPC_MSG_STATE_LEN 544 // bit
+// data segment
+#define STATE_STAGE_OFFSET 0
+#define STATE_STAGE_LEN 8
+#define STATE_STAGE_SETUP 0x51
+#define STATE_STAGE_RTNE 0x52
+#define STATE_STAGE_SVC 0x53
+#define STATE_SETUP_TIME_OFFSET 8
+#define STATE_SETUP_TIME_LEN 32
+#define STATE_NUM_NODE_OFFSET 40
+#define STATE_NUM_NODE_LEN 8
+#define STATE_FRAME_1_CNT_OFFSET 48
+#define STATE_FRAME_1_CNT_LEN 8
+#define STATE_FRAME_2_CNT_OFFSET 56
+#define STATE_FRAME_2_CNT_LEN 8
+#define STATE_FRAME_3_CNT_OFFSET 64
+#define STATE_FRAME_3_CNT_LEN 8
+#define STATE_FRAME_4_CNT_OFFSET 72
+#define STATE_FRAME_4_CNT_LEN 8
+#define STATE_FRAME_5_CNT_OFFSET 80
+#define STATE_FRAME_5_CNT_LEN 8
+#define STATE_FRAME_6_CNT_OFFSET 88
+#define STATE_FRAME_6_CNT_LEN 8
+#define STATE_FRAME_7_CNT_OFFSET 96
+#define STATE_FRAME_7_CNT_LEN 8
+#define STATE_FRAME_8_CNT_OFFSET 104
+#define STATE_FRAME_8_CNT_LEN 8
+
+#define STATE_FRAME_1_SENT_OFFSET 112
+#define STATE_FRAME_1_SENT_LEN 16
+#define STATE_FRAME_2_SENT_OFFSET 128
+#define STATE_FRAME_2_SENT_LEN 16
+#define STATE_FRAME_3_SENT_OFFSET 144
+#define STATE_FRAME_3_SENT_LEN 16
+#define STATE_FRAME_4_SENT_OFFSET 160
+#define STATE_FRAME_4_SENT_LEN 16
+#define STATE_FRAME_5_SENT_OFFSET 176
+#define STATE_FRAME_5_SENT_LEN 16
+#define STATE_FRAME_6_SENT_OFFSET 192
+#define STATE_FRAME_6_SENT_LEN 16
+#define STATE_FRAME_7_SENT_OFFSET 208
+#define STATE_FRAME_7_SENT_LEN 16
+#define STATE_FRAME_8_SENT_OFFSET 224
+#define STATE_FRAME_8_SENT_LEN 16
+
+#define STATE_FRAME_1_RECV_OFFSET 240
+#define STATE_FRAME_1_RECV_LEN 16
+#define STATE_FRAME_2_RECV_OFFSET 256
+#define STATE_FRAME_2_RECV_LEN 16
+#define STATE_FRAME_3_RECV_OFFSET 272
+#define STATE_FRAME_3_RECV_LEN 16
+#define STATE_FRAME_4_RECV_OFFSET 288
+#define STATE_FRAME_4_RECV_LEN 16
+#define STATE_FRAME_5_RECV_OFFSET 304
+#define STATE_FRAME_5_RECV_LEN 16
+#define STATE_FRAME_6_RECV_OFFSET 320
+#define STATE_FRAME_6_RECV_LEN 16
+#define STATE_FRAME_7_RECV_OFFSET 336
+#define STATE_FRAME_7_RECV_LEN 16
+#define STATE_FRAME_8_RECV_OFFSET 352
+#define STATE_FRAME_8_RECV_LEN 16
+
+#define STATE_TRAJ_X_OFFSET 368
+#define STATE_TRAJ_X_LEN 32
+#define STATE_TRAJ_Y_OFFSET 400
+#define STATE_TRAJ_Y_LEN 32
+#define STATE_TRAJ_ALPHA_OFFSET 432
+#define STATE_TRAJ_ALPHA_LEN 64
+
+#define STATE_TOPO_1_OFFSET 496
+#define STATE_TOPO_1_LEN 8
+#define STATE_TOPO_2_OFFSET 504
+#define STATE_TOPO_2_LEN 8
+#define STATE_TOPO_3_OFFSET 512
+#define STATE_TOPO_3_LEN 8
+#define STATE_TOPO_4_OFFSET 520
+#define STATE_TOPO_4_LEN 8
+
+#define MGMT_MSG_NUM_OFFSET 528
+#define MGMT_MSG_NUM_LEN 8
+#define SVC_MSG_NUM_OFFSET 536
+#define SVC_MSG_NUM_LEN 8
+
+#define STORE_ADDR_START_OFFSET 544
+
+
+// ** Time SyncAdj Message ** //
+// Type code
+#define MPC_MSG_TSYNC_CODE 0x00FF
+#define MPC_MSG_TSYNC_LEN 128 // bit
+// data segment - self test response message.
+#define RTT_ADJ_OFFSET 0
+#define RTT_ADJ_LEN 32
+#define TSYNC_ADJ_OFFSET 32
+#define TSYNC_ADJ_LEN 32
+#define DOPPLER_OFFSET 64
+#define DOPPLER_LEN 32
+#endif //_MPC_MSG_DEF

datalink814_ge/src/phy_ctrl/antenna.c

@@ -0,0 +1,371 @@
+/*****************************************************************************/
+/**
+ * Description: Antenna configuration functions.
+ *
+ * Author: Fan Hao
+ * Date: 2022-06-18 16:37
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-06-18 17:15
+ * Revisions: Rev 0.0
+ * History:
+ * [2022-06-18]: Initial version.
+ *
+ * Copyright(c) 2022 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+#include <string.h>
+#include <stdint.h>
+#include <math.h>
+#include "phy_ctrl.h"
+#include "../error.h"
+
+#define ANT_PI 3.14159265358979323846
+#define ANT_COINFO_HEAD 0xAA
+#define ANT_COINFO_TAIL 0xCC
+
+#define CTRL_WORD_DEFAULT 0x00
+
+#define ANT_MODE_BEAM_MASK 0xF0
+#define ANT_MODE_NARROR_BEAM 0x00 // 8
+#define ANT_MODE_WIDE_BEAM_1 0x10 // 25
+#define ANT_MODE_WIDE_BEAM_2 0x20 // 60
+#define ANT_MODE_WIDE_BEAM_3 0x30 // 120
+
+#define ANT_MODE_HIGH_POWER 0x00
+#define ANT_MODE_LOWAPOWER 0x04
+#define ANT_MODE_STANDBY 0x0F
+#define ATN_MODE_DEFAULT (ANT_MODE_WIDE_BEAM_1 | ANT_MODE_LOWAPOWER)
+#define ATN_MODE_HIGH 	 (ANT_MODE_WIDE_BEAM_1 | ANT_MODE_HIGH_POWER)
+
+#define DEFAULT_CENTRTAL_FREQ 0x06D7 // 26.25GHz
+
+#define RXTXMODE_RX 0x00
+#define RXTXMODE_TX 0x01
+
+#define CALIBRMODE_NORMAL 0x00
+#define CALIBRMODE_SINGLE_TR_CAL 0x01
+
+#define MODECTRL_DEFAULT 0x00
+
+uint16_t hopPattern_Config[L1_FRAME_MAX_HOPS] = {0};
+
+uint16_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS] = {1500};
+
+uint16_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS] = {
+		2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+		2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+		2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+		2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+		2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+		2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+		2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400
+};
+
+uint16_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS] = {1500};
+
+uint16_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS] = { 1500, 1600, 1700,
+		1800, 1900, 2000, 1500, 1600, 1700, 1800, 1900 };
+
+uint16_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS] = {
+		2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400
+};
+
+uint16_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS] = {
+		2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
+		2400, 2400, 2400, 2400, 2400, 2400, 2400
+};
+
+uint16_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS] ={ 1500, 1600, 1700, 1800, 1900, 2000, 1500, 1600 , 1700,
+		1800, 1900, 2000, 1500, 1600 , 1700, 1800, 1900, 2000, 1500, 1500};
+
+uint16_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS] = { 500, 600, 700, 800, 900, 1000, 500, 600 , 700,
+		800, 900, 1000, 500, 600 , 700, 800, 900, 1000, 500, 500 };
+
+// Pair by regex
+// Regex: ((\{\.oaxis = [0-9]+[ ,]+\.raxis = [0-9]+[ ]*\}, ){2})
+#if defined(PHY_BEAM_SET_PRESET)
+ANT_ANGLE antSubnrrwPattern[NUM_ANT_SUBNRRW_PATTERN] = {
+	{.oaxis = 0 , .raxis = 222}, {.oaxis = 10, .raxis = 85 },
+	{.oaxis = 14, .raxis = 307}, {.oaxis = 17, .raxis = 170},
+	{.oaxis = 19, .raxis = 32 }, {.oaxis = 21, .raxis = 255},
+	{.oaxis = 24, .raxis = 117}, {.oaxis = 25, .raxis = 340},
+	{.oaxis = 27, .raxis = 202}, {.oaxis = 29, .raxis = 65 },
+	{.oaxis = 31, .raxis = 287}, {.oaxis = 32, .raxis = 150},
+	{.oaxis = 34, .raxis = 12 }, {.oaxis = 35, .raxis = 235},
+	{.oaxis = 36, .raxis = 97 }, {.oaxis = 38, .raxis = 320},
+	{.oaxis = 39, .raxis = 182}, {.oaxis = 40, .raxis = 45 },
+	{.oaxis = 41, .raxis = 267}, {.oaxis = 43, .raxis = 130},
+	{.oaxis = 44, .raxis = 352}, {.oaxis = 45, .raxis = 215},
+	{.oaxis = 46, .raxis = 77 }, {.oaxis = 47, .raxis = 300},
+	{.oaxis = 48, .raxis = 162}, {.oaxis = 49, .raxis = 25 },
+	{.oaxis = 50, .raxis = 247}, {.oaxis = 51, .raxis = 110},
+	{.oaxis = 52, .raxis = 332}, {.oaxis = 53, .raxis = 195},
+	{.oaxis = 54, .raxis = 57 }, {.oaxis = 55, .raxis = 280},
+	{.oaxis = 56, .raxis = 142}, {.oaxis = 57, .raxis = 5  },
+	{.oaxis = 58, .raxis = 227}, {.oaxis = 59, .raxis = 90 },
+	{.oaxis = 60, .raxis = 312}
+};
+ANT_ANGLE antNrrwPattern[NUM_ANT_NRRW_PATTERN] = {
+	{.oaxis = 0 , .raxis = 222}, {.oaxis = 7 , .raxis = 85 },
+	{.oaxis = 10, .raxis = 307}, {.oaxis = 13, .raxis = 170},
+	{.oaxis = 15, .raxis = 32 }, {.oaxis = 17, .raxis = 255},
+	{.oaxis = 18, .raxis = 117}, {.oaxis = 20, .raxis = 340},
+	{.oaxis = 21, .raxis = 202}, {.oaxis = 22, .raxis = 65 },
+	{.oaxis = 24, .raxis = 287}, {.oaxis = 25, .raxis = 150},
+	{.oaxis = 26, .raxis = 12 }, {.oaxis = 27, .raxis = 235},
+	{.oaxis = 28, .raxis = 97 }, {.oaxis = 29, .raxis = 320},
+	{.oaxis = 30, .raxis = 182}, {.oaxis = 31, .raxis = 45 },
+	{.oaxis = 32, .raxis = 267}, {.oaxis = 33, .raxis = 130},
+	{.oaxis = 34, .raxis = 352}, {.oaxis = 34, .raxis = 215},
+	{.oaxis = 35, .raxis = 77 }, {.oaxis = 36, .raxis = 300},
+	{.oaxis = 37, .raxis = 162}, {.oaxis = 38, .raxis = 25 },
+	{.oaxis = 38, .raxis = 247}, {.oaxis = 39, .raxis = 110},
+	{.oaxis = 40, .raxis = 332}, {.oaxis = 41, .raxis = 195},
+	{.oaxis = 41, .raxis = 57 }, {.oaxis = 42, .raxis = 280},
+	{.oaxis = 43, .raxis = 142}, {.oaxis = 44, .raxis = 5  },
+	{.oaxis = 44, .raxis = 227}, {.oaxis = 45, .raxis = 90 },
+	{.oaxis = 46, .raxis = 312}, {.oaxis = 46, .raxis = 175},
+	{.oaxis = 47, .raxis = 37 }, {.oaxis = 48, .raxis = 260},
+	{.oaxis = 48, .raxis = 122}, {.oaxis = 49, .raxis = 345},
+	{.oaxis = 49, .raxis = 207}, {.oaxis = 50, .raxis = 70 },
+	{.oaxis = 51, .raxis = 292}, {.oaxis = 51, .raxis = 155},
+	{.oaxis = 52, .raxis = 17 }, {.oaxis = 53, .raxis = 240},
+	{.oaxis = 53, .raxis = 102}, {.oaxis = 54, .raxis = 325},
+	{.oaxis = 54, .raxis = 187}, {.oaxis = 55, .raxis = 50 },
+	{.oaxis = 55, .raxis = 272}, {.oaxis = 56, .raxis = 135},
+	{.oaxis = 57, .raxis = 357}, {.oaxis = 57, .raxis = 220},
+	{.oaxis = 58, .raxis = 82 }, {.oaxis = 58, .raxis = 305},
+	{.oaxis = 59, .raxis = 167}, {.oaxis = 59, .raxis = 30 },
+	{.oaxis = 60, .raxis = 252}
+};
+#elif defined(PHY_BEAM_SET_PRESET_LSX)
+ANT_ANGLE antSubnrrwPattern[NUM_ANT_SUBNRRW_PATTERN] = {
+	{.oaxis = 0  , .raxis =2225},{.oaxis = 96 , .raxis =850 },
+	{.oaxis = 135, .raxis =3075},{.oaxis = 166, .raxis =1700},
+	{.oaxis = 192, .raxis =325 },{.oaxis = 215, .raxis =2550},
+	{.oaxis = 236, .raxis =1174},{.oaxis = 255, .raxis =3399},
+	{.oaxis = 273, .raxis =2024},{.oaxis = 290, .raxis =649 },
+	{.oaxis = 306, .raxis =2874},{.oaxis = 321, .raxis =1499},
+	{.oaxis = 336, .raxis =124 },{.oaxis = 350, .raxis =2349},
+	{.oaxis = 363, .raxis =974 },{.oaxis = 377, .raxis =3199},
+	{.oaxis = 389, .raxis =1824},{.oaxis = 402, .raxis =449 },
+	{.oaxis = 414, .raxis =2674},{.oaxis = 426, .raxis =1298},
+	{.oaxis = 438, .raxis =3523},{.oaxis = 449, .raxis =2148},
+	{.oaxis = 460, .raxis =773 },{.oaxis = 471, .raxis =2998},
+	{.oaxis = 482, .raxis =1623},{.oaxis = 492, .raxis =248 },
+	{.oaxis = 503, .raxis =2473},{.oaxis = 513, .raxis =1098},
+	{.oaxis = 523, .raxis =3323},{.oaxis = 533, .raxis =1948},
+	{.oaxis = 543, .raxis =573 },{.oaxis = 553, .raxis =2798},
+	{.oaxis = 563, .raxis =1422},{.oaxis = 572, .raxis =47  },
+	{.oaxis = 581, .raxis =2272},{.oaxis = 591, .raxis =897 },
+	{.oaxis = 600, .raxis =3122}
+};
+ANT_ANGLE antNrrwPattern[NUM_ANT_NRRW_PATTERN] = {
+	{.oaxis = 0  , .raxis =2225},{.oaxis = 74 , .raxis =850 },
+	{.oaxis = 105, .raxis =3075},{.oaxis = 128, .raxis =1700},
+	{.oaxis = 148, .raxis =325 },{.oaxis = 166, .raxis =2550},
+	{.oaxis = 182, .raxis =1174},{.oaxis = 197, .raxis =3399},
+	{.oaxis = 210, .raxis =2024},{.oaxis = 223, .raxis =649 },
+	{.oaxis = 236, .raxis =2874},{.oaxis = 247, .raxis =1499},
+	{.oaxis = 258, .raxis =124 },{.oaxis = 269, .raxis =2349},
+	{.oaxis = 280, .raxis =974 },{.oaxis = 290, .raxis =3199},
+	{.oaxis = 299, .raxis =1824},{.oaxis = 309, .raxis =449 },
+	{.oaxis = 318, .raxis =2674},{.oaxis = 327, .raxis =1298},
+	{.oaxis = 336, .raxis =3523},{.oaxis = 344, .raxis =2148},
+	{.oaxis = 352, .raxis =773 },{.oaxis = 361, .raxis =2998},
+	{.oaxis = 369, .raxis =1623},{.oaxis = 377, .raxis =248 },
+	{.oaxis = 384, .raxis =2473},{.oaxis = 392, .raxis =1098},
+	{.oaxis = 399, .raxis =3323},{.oaxis = 407, .raxis =1948},
+	{.oaxis = 414, .raxis =573 },{.oaxis = 421, .raxis =2798},
+	{.oaxis = 428, .raxis =1422},{.oaxis = 435, .raxis =47  },
+	{.oaxis = 442, .raxis =2272},{.oaxis = 449, .raxis =897 },
+	{.oaxis = 456, .raxis =3122},{.oaxis = 462, .raxis =1747},
+	{.oaxis = 469, .raxis =372 },{.oaxis = 475, .raxis =2597},
+	{.oaxis = 482, .raxis =1222},{.oaxis = 488, .raxis =3447},
+	{.oaxis = 495, .raxis =2072},{.oaxis = 501, .raxis =697 },
+	{.oaxis = 507, .raxis =2922},{.oaxis = 513, .raxis =1546},
+	{.oaxis = 519, .raxis =171 },{.oaxis = 525, .raxis =2396},
+	{.oaxis = 531, .raxis =1021},{.oaxis = 537, .raxis =3246},
+	{.oaxis = 543, .raxis =1871},{.oaxis = 549, .raxis =496 },
+	{.oaxis = 555, .raxis =2721},{.oaxis = 561, .raxis =1346},
+	{.oaxis = 566, .raxis =3571},{.oaxis = 572, .raxis =2196},
+	{.oaxis = 578, .raxis =821 },{.oaxis = 583, .raxis =3045},
+	{.oaxis = 589, .raxis =1670},{.oaxis = 594, .raxis =295 },
+	{.oaxis = 600, .raxis =2520}
+};
+#else
+PHY_ANT_ANGLE antSubnrrwPattern[NUM_ANT_SUBNRRW_PATTERN]  = {0};
+PHY_ANT_ANGLE antNrrwPattern[NUM_ANT_NRRW_PATTERN] = {0};
+#endif
+/*****************************************************************************/
+/**
+ * @brief
+ *
+ * @param   antCoinfoPtr
+ *
+ * @return
+ *
+ ******************************************************************************/
+int32_t Phy_AntCoinfoInit(PHY_ANT_CONFIG *antCoinfoPtr)
+{
+	if (antCoinfoPtr == NULL)
+	{
+		return FAILURE;
+	}
+	antCoinfoPtr->head = ANT_COINFO_HEAD;
+	antCoinfoPtr->tail = ANT_COINFO_TAIL;
+	antCoinfoPtr->ctrlWord = 0x00;
+#ifdef ANT_HIGH_POWER
+	antCoinfoPtr->antMode = ATN_MODE_HIGH;
+#else
+	antCoinfoPtr->antMode = ATN_MODE_DEFAULT;
+#endif
+
+
+	// FIXME: Dummy default value.
+	// off axis angle setting
+	antCoinfoPtr->oaxis[0] = 0;
+	antCoinfoPtr->oaxis[1] = 0;
+	// round axis angle setting
+	antCoinfoPtr->raxis[0] = 0;
+	antCoinfoPtr->raxis[1] = 0;
+	// ***********************
+
+	antCoinfoPtr->antFreq[0] = (uint8_t)(DEFAULT_CENTRTAL_FREQ);
+	antCoinfoPtr->antFreq[1] = (uint8_t)(DEFAULT_CENTRTAL_FREQ >> 8);
+
+	// FIXME: Dummy default value.
+	// trSelect
+	antCoinfoPtr->trSlect = 0;
+	// Antenna attenuation setting
+	antCoinfoPtr->antAtt = 20;
+	// phase setting
+	antCoinfoPtr->phase = 0;
+	// ***********************
+
+	antCoinfoPtr->rxtxMode = RXTXMODE_RX;
+	antCoinfoPtr->calibrMode = CALIBRMODE_NORMAL;
+
+	// FIXME: Dummy default value.
+	// DD enable
+	antCoinfoPtr->ddEn = 0;
+	// DD mgc
+	antCoinfoPtr->ddMgc = 0;
+	// RF mode control
+	antCoinfoPtr->rfCtrl = 0;
+	// RF MGC control
+	antCoinfoPtr->rfMgc = 0;
+	// RF channel 1&2 calibration mgc
+	antCoinfoPtr->rf12CalMgc = 0;
+	// RF channel 2&3 calibration mgc
+	antCoinfoPtr->rf34CalMgc = 0;
+	// Receive channel 1 MGC
+	antCoinfoPtr->rcv1Mgc = 0;
+	// Receive channel 2 MGC
+	antCoinfoPtr->rcv2Mgc = 0;
+	// Receive channel 3 MGC
+	antCoinfoPtr->rcv3Mgc = 0;
+	// Receive channel 4 MGC
+	antCoinfoPtr->rcv4Mgc = 0;
+	// ***********************
+
+	memset(antCoinfoPtr->dummy, 0x00, sizeof(antCoinfoPtr->dummy));
+
+	return SUCCESS;
+}
+
+int32_t Phy_SetBeamNo(PHY_INST *instPtr, int32_t beamNo)
+{
+	if(instPtr->beamWd.next == ANT_BEAM_8){
+		if (beamNo >= NUM_ANT_NRRW_PATTERN)
+		{
+			return FAILURE;
+		}
+		else
+		{
+			instPtr->beamNo.next = beamNo;
+			instPtr->antCoinfoPtr.oaxis[1] = (uint8_t)(antNrrwPattern[beamNo].oaxis);
+			instPtr->antCoinfoPtr.oaxis[0] = (uint8_t)((antNrrwPattern[beamNo].oaxis) >> 8);
+			instPtr->antCoinfoPtr.raxis[1] = (uint8_t)(antNrrwPattern[beamNo].raxis);
+			instPtr->antCoinfoPtr.raxis[0] = (uint8_t)((antNrrwPattern[beamNo].raxis) >> 8);
+			return SUCCESS;
+		}
+	}
+	else if(instPtr->beamWd.next == ANT_BEAM_25){
+		if (beamNo >= NUM_ANT_SUBNRRW_PATTERN)
+		{
+			return FAILURE;
+		}
+		else
+		{
+			instPtr->beamNo.next = beamNo;
+			instPtr->antCoinfoPtr.oaxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].oaxis);
+			instPtr->antCoinfoPtr.oaxis[0] = (uint8_t)((antSubnrrwPattern[beamNo].oaxis) >> 8);
+			instPtr->antCoinfoPtr.raxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].raxis);
+			instPtr->antCoinfoPtr.raxis[0] = (uint8_t)((antSubnrrwPattern[beamNo].raxis) >> 8);
+			return SUCCESS;
+		}
+	}
+	else{
+		// Beam number assign not support.
+		// Assign default angle (0,0)
+		instPtr->beamNo.next = 0;
+		instPtr->antCoinfoPtr.oaxis[1] = 0;
+		instPtr->antCoinfoPtr.oaxis[0] = 0;
+		instPtr->antCoinfoPtr.raxis[1] = 0;
+		instPtr->antCoinfoPtr.raxis[0] = 0;
+		DBG_WARNING("Using default beam number...");
+		return SUCCESS;
+	}
+}
+
+int32_t Phy_SetBeamWidth(PHY_INST *instPtr, PHY_ANT_BEAM_WIDTH beamWidth)
+{
+	uint8_t beamConfig = instPtr->antCoinfoPtr.antMode & (~ANT_MODE_BEAM_MASK);
+	switch (beamWidth)
+	{
+	case ANT_BEAM_120:
+		beamConfig |= ANT_MODE_WIDE_BEAM_3;
+		break;
+	case ANT_BEAM_60:
+		beamConfig |= ANT_MODE_WIDE_BEAM_2;
+		break;
+	case ANT_BEAM_25:
+		beamConfig |= ANT_MODE_WIDE_BEAM_1;
+		break;
+	case ANT_BEAM_8:
+		beamConfig |= ANT_MODE_NARROR_BEAM;
+		break;
+	default:
+		DBG_ERROR("Beam width code: 0x%08X is illegal.\n\r", beamWidth);
+		return EPARAM;
+		break;
+	}
+	instPtr->antCoinfoPtr.antMode = beamConfig;
+	instPtr->beamWd.next = beamWidth;
+	return SUCCESS;
+}
+
+// Common version radius double input
+int32_t Phy_SetBeamAngle(PHY_INST *instPtr, double offAx, double rndAx)
+{
+	uint16_t offAxDeg = 0;
+	uint16_t rndAxDeg = 0;
+	offAxDeg = (offAx > 0) ? (((int32_t)(offAx * 180 / ANT_PI)) % 360) : (((int32_t)(offAx * 180 / ANT_PI)) % 360 + 360);
+	rndAxDeg = (rndAx > 0) ? (((int32_t)(rndAx * 180 / ANT_PI)) % 360) : (((int32_t)(rndAx * 180 / ANT_PI)) % 360 + 360);
+	if (offAxDeg > 60)
+	{
+		DBG_ERROR("Angle out of range, off axis angle: %u(should be 0~60), round axis angle: %u(should be 0~360).",
+				offAxDeg, rndAxDeg);
+		return EPARAM;
+	}
+	offAxDeg = offAxDeg * 10;
+	rndAxDeg = rndAxDeg * 10;
+	instPtr->antCoinfoPtr.oaxis[1] = (uint8_t)offAxDeg;
+	instPtr->antCoinfoPtr.oaxis[0] = (uint8_t)(offAxDeg >> 8);
+	instPtr->antCoinfoPtr.raxis[1] = (uint8_t)rndAxDeg;
+	instPtr->antCoinfoPtr.raxis[0] = (uint8_t)(rndAxDeg >> 8);
+	return SUCCESS;
+}
+

datalink814_ge/src/phy_ctrl/phy_ctrl.c

@@ -0,0 +1,813 @@
+/*****************************************************************************/
+/**
+ * Description: Implementation of physical control functions
+ *
+ * Date: 2021-11-16 00:08
+ * LastEditTime: 2023-04-23 17:48
+ * Revisions: Rev 0.2
+ * History:
+ * [2021-11-16]: Initial version.
+ * [2022-06-18]: New branch for glink control purpose:
+ * 				 -Add poll mode, physical layer will start Tx/Rx procedure
+ * 				  at specific time stamp.
+ * 				 -Add 61/37 beam switch
+ * 				 -Code simplification.
+ * [2023-04-24]: Feature add:
+ * 				- Read frame type from PL status register.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include <string.h>
+#include <stdlib.h>
+#include <math.h>
+#include "phy_ctrl.h"
+#include "../util/util.h"
+#include "../error.h"
+#ifndef EMULATION
+#include "xbram.h"
+#endif
+/************************** Constant Definitions *****************************/
+/***************** Macros (Inline Functions) Definitions *********************/
+/************************** Function Prototypes ******************************/
+static void Phy_RcdShift(PHY_RCD* rcd, int32_t netxVal);
+static int32_t Phy_SetSendData(PHY_INST* instPtr, L1_FRAME_TYPE frameType, uint8_t* dataBuff);
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * @brief   Setup data will be sent in next slot.
+ *
+ * @param   instPtr  A pointer to physical layer control instance.
+ *
+ * @return  FAILURE Error occurred.
+ *          SUCCESS Setting data successful.
+ *
+ ******************************************************************************/
+static int32_t Phy_SetSendData(PHY_INST* instPtr, L1_FRAME_TYPE frameType, uint8_t* dataBuff) {
+	ASSERT(instPtr != NULL);
+	ASSERT(dataBuff != NULL);
+	uint32_t frameLen, sendCmd;
+
+	frameLen = Phy_GetFrameLen(frameType);
+
+	if (frameLen == L1_FRAME_NONE_LEN) {
+		DBG_ERROR("Invalid frame length.\n");
+		return EPARAM;
+	}
+	instPtr->sendDataOffset = (TXRXDATA_MAX_LEN >> 1) - instPtr->sendDataOffset;	
+	memcpy((uint8_t*)(instPtr->sendDataAddr + instPtr->sendDataOffset), dataBuff, frameLen);
+	
+	sendCmd = frameLen & SEND_DATA_CMD_LEN_MASK;
+	sendCmd |= (instPtr->sendDataOffset << SEND_DATA_CMD_OFFSET_SHIFT) & SEND_DATA_CMD_OFFSET_MASK;
+
+	// Physical layer start fetching data.
+	PhyWrite(instPtr, SEND_DATA_CMD, sendCmd);
+	return SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Check whether a frame was detected. (Do not check if the frame was
+ *          deoced.)
+ *
+ * @param   instPtr A pointer to physical layer control instance.
+ *
+ * @return  true
+ *          false
+ *
+ ******************************************************************************/
+inline bool Phy_IsFrameDetected(PHY_INST* instPtr) {
+	ASSERT(instPtr != NULL);
+	if(instPtr->TOR.last == PHY_TOR_RX && instPtr->isAcq && instPtr->isFrameSync) {
+		return true;
+	}
+	else {
+		return false;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Check whether a frame was received. (Do not check if the frame was
+ *          crashed.)
+ * 
+ * @param   instPtr A pointer to physical layer control instance.
+ * 
+ * @return  true
+ *          false
+ * 
+ ******************************************************************************/
+inline bool Phy_IsFrameReceived(PHY_INST* instPtr) {
+	ASSERT(instPtr != NULL);
+	if(instPtr->TOR.last == PHY_TOR_RX && instPtr->isAcq 
+		&& instPtr->isFrameSync && instPtr->isDecode) {
+		return true;
+	}
+	else {
+		return false;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Check whether a frame was valid. (if the frame was crashed, it will
+ *          be regarded as not valid.
+ *
+ * @param   instPtr
+ *
+ * @return  true
+ *          false
+ *
+ ******************************************************************************/
+inline bool Phy_IsFrameValid(PHY_INST* instPtr) {
+	ASSERT(instPtr != NULL);
+	if (instPtr->TOR.last == PHY_TOR_RX && instPtr->isAcq && instPtr->isFrameSync
+			&& instPtr->isDecode && instPtr->isValid) {
+		return true;
+	}
+	else {
+		return false;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief    Get frame type of the frame in receive data buffer (Base on PL Record).
+ *
+ * @param   instPtr  A pointer to physical layer control instance.
+ *
+ * @return  Layer2 frame type. Refer "frame_def.h"
+ *
+ ******************************************************************************/
+inline L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr) {
+	ASSERT(instPtr != NULL);
+	if (Phy_IsFrameReceived(instPtr) == false) {
+		return L1_NONE_FRAME;
+	}
+	int32_t frame_type = (PhyRead(instPtr, PHY_MODE_CTRL) & PHY_MODE_CTRL_FRAME_MASK)
+			>> PHY_MODE_CTRL_FRAME_SHIFT;
+	if(frame_type < L1_1M2BPS_5MS_FRAME)
+		return frame_type;
+	else
+		return L1_NONE_FRAME;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get frame type of the frame was sent in last slot.
+ *
+ * @param   instPtr  A pointer to physical layer control instance.
+ *
+ * @return  Layer2 frame type. Refer "frame_def.h"
+ *
+ ******************************************************************************/
+inline L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST* instPtr) {
+	ASSERT(instPtr != NULL);
+	if (instPtr->TOR.last != PHY_TOR_TX) {
+		return L1_NONE_FRAME;
+	}
+	return instPtr->frameType.last;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Shift l1 status record.(newval->next->curr->last)
+ *
+ * @param   instPtr  A pointer to physical layer control instance.
+ *
+ * @return  NONE.
+ *
+ ******************************************************************************/
+static void Phy_RcdShift(PHY_RCD* rcd, int32_t netxVal){
+	ASSERT(rcd != NULL);
+	rcd->last = rcd->curr;
+	rcd->curr = rcd->next;
+	rcd->next = netxVal;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get corresponding frame length in byte of L1 frame.
+ *
+ * @param   frameType
+ *
+ * @return Corresponding frame length
+ *         L1_FRAME_NONE_LEN if the frame type code cannot be recognized.
+ *
+ ******************************************************************************/
+uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType) {
+	switch (frameType) {
+	case L1_2KBPS_20MS_FRAME:
+		return L1_FRAME_2KBPS_20MS_LEN;
+	case L1_2KBPS_100MS_FRAME:
+		return L1_FRAME_2KBPS_100MS_LEN;
+	case L1_10KBPS_10MS_FRAME:
+		return L1_FRAME_10KBPS_10MS_LEN;
+	case L1_10KBPS_20MS_FRAME:
+		return L1_FRAME_10KBPS_20MS_LEN;
+	case L1_40KBPS_20MS_FRAME:
+		return L1_FRAME_40KBPS_20MS_LEN;
+	case L1_40KBPS_10MS_FRAME:
+		return L1_FRAME_40KBPS_10MS_LEN;
+	case L1_200KBPS_5MS_FRAME:
+		return L1_FRAME_200KBPS_5MS_LEN;
+	case L1_1M2BPS_5MS_FRAME:
+		return L1_FRAME_1M2BPS_5MS_LEN;
+	default:
+		return L1_FRAME_NONE_LEN;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief	Update physical layer status cache.
+ *
+ * @param   instPtr A pointer to physical layer control instance.
+ *
+ * @return	NONE.
+ *
+ ******************************************************************************/
+void Phy_UpdateState(PHY_INST* instPtr) {
+	ASSERT(instPtr != NULL);
+
+	Phy_RcdShift(&(instPtr->TOR),PHY_TOR_SUSPEND);
+	Phy_RcdShift(&(instPtr->frameType),L1_NONE_FRAME);
+	Phy_RcdShift(&(instPtr->antNo), INIT_ANT_NO);
+	Phy_RcdShift(&(instPtr->beamNo), INIT_BEAM_NO);
+	Phy_RcdShift(&(instPtr->beamWd), INIT_ANT_WD);
+	/* Update Frame Sate. */
+	uint32_t txrxSate = PhyRead(instPtr, TXRX_STATE);
+	instPtr->isAcq = ((txrxSate & TXRX_STATE_ACQ_MASK) == TXRX_STATE_ACQ_SUCCESS) ? true : false;
+	instPtr->isFrameSync = ((txrxSate & TXRX_STATE_FSYNC_MASK) == TXRX_STATE_FSYNC_SUCCESS) ? true : false;
+	instPtr->isDecode = ((txrxSate & TXRX_STATE_DECODE_MASK) == TXRX_STATE_DECODE_SUCCESS) ? true : false;
+	if (Phy_IsFrameReceived(instPtr)) {
+		instPtr->isValid = ((txrxSate & TXRX_STATE_CRC_MASK) == TXRX_STATE_CRC_OK) ? true : false;
+	}
+	else {
+		instPtr->isValid = false;
+	}
+	return;
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Initialize physical layer instance accordingly.
+ * 
+ * @param   instPtr  a pointer to physical instance
+ * @param   phyConfig a pointer to cinfiguration staructure.
+ * 
+ * @return  SUCCESS
+ * 
+ ******************************************************************************/
+int32_t Phy_InstInit(PHY_INST** instPtr, PHY_CONFIG *phyConfig) {
+	ASSERT(instPtr != NULL);
+	ASSERT(phyConfig != NULL);
+	int32_t Status;
+
+	*instPtr = (PHY_INST*) malloc(sizeof(PHY_INST));
+	if ((*instPtr) == NULL) {
+		return EALLOC;
+	}
+	memcpy(&(*instPtr)->phyCofig, phyConfig, sizeof(PHY_CONFIG));
+
+	(*instPtr)->isPhyEn = false;
+	(*instPtr)->isAcq = false;
+	(*instPtr)->isFrameSync = false;
+	(*instPtr)->isDecode = false;
+	(*instPtr)->isValid = false;
+	(*instPtr)->isPresetHop = false;
+	(*instPtr)->antConfigOffset = 0;
+	(*instPtr)->sendDataOffset = 0;
+	Phy_AntCoinfoInit(&((*instPtr)->antCoinfoPtr));
+
+	memset(&((*instPtr))->TOR, PHY_TOR_SUSPEND, sizeof(PHY_RCD));
+	memset(&((*instPtr)->frameType), L1_NONE_FRAME, sizeof(PHY_RCD));
+	memset(&((*instPtr)->antNo), (int32_t)INIT_BEAM_NO, sizeof(PHY_RCD));
+	memset(&((*instPtr)->beamNo), (int32_t)INIT_ANT_NO, sizeof(PHY_RCD));
+	memset(&((*instPtr)->beamWd), (int32_t)INIT_ANT_WD, sizeof(PHY_RCD));
+
+#ifndef EMULATION
+	XBram antInfoBram;
+	XBram txFrameBram;
+	XBram rxFrameBram;
+
+	XBram_Config *ConfigPtr;
+	ConfigPtr = XBram_LookupConfig(phyConfig->antBramId);
+	if (ConfigPtr == NULL) {
+		Status = EDINVAL;
+		goto error;
+	}
+	Status = XBram_CfgInitialize(&antInfoBram, ConfigPtr,
+			ConfigPtr->CtrlBaseAddress);
+	if (Status != SUCCESS) {
+		goto error;
+	}
+	/*
+	 * Execute the BRAM driver selftest.
+	 */
+	Status = XBram_SelfTest(&antInfoBram, 0);
+	if (Status != SUCCESS) {
+		goto error;
+	}
+
+	ConfigPtr = XBram_LookupConfig(phyConfig->txBramId);
+	if (ConfigPtr == NULL) {
+		Status =  EDINVAL;
+		goto error;
+	}
+	Status = XBram_CfgInitialize(&txFrameBram, ConfigPtr,
+			ConfigPtr->CtrlBaseAddress);
+	if (Status != SUCCESS) {
+		goto error;
+	}
+	/*
+	 * Execute the BRAM driver selftest.
+	 */
+	Status = XBram_SelfTest(&txFrameBram, 0);
+	if (Status != SUCCESS) {
+		goto error;
+	}
+
+	ConfigPtr = XBram_LookupConfig(phyConfig->rxBramId);
+	if (ConfigPtr == NULL) {
+		Status =  EDINVAL;
+		goto error;
+	}
+	Status = XBram_CfgInitialize(&rxFrameBram, ConfigPtr,
+			ConfigPtr->CtrlBaseAddress);
+	if (Status != SUCCESS) {
+		goto error;
+	}
+	/*
+	 * Execute the BRAM driver selftest.
+	 */
+	Status = XBram_SelfTest(&rxFrameBram, 0);
+	if (Status != SUCCESS) {
+		goto error;
+	}
+
+	(*instPtr)->antConfigAddr = antInfoBram.Config.MemBaseAddress;
+	(*instPtr)->recvDataAddr = rxFrameBram.Config.MemBaseAddress;
+	(*instPtr)->sendDataAddr = txFrameBram.Config.MemBaseAddress;
+#else
+	(*instPtr)->antConfigAddr = (uintptr_t)calloc(ANTCONFIG_MAX_LEN/sizeof(uint64_t), sizeof(uint64_t));
+	if ((*instPtr)->antConfigAddr == (uintptr_t)NULL) {
+		Status = EALLOC;
+		goto error;
+	}
+	(*instPtr)->recvDataAddr = (uintptr_t)calloc(TXRXDATA_MAX_LEN/sizeof(uint64_t), sizeof(uint64_t));
+	if ((*instPtr)->recvDataAddr == (uintptr_t)NULL) {
+		Status = EALLOC;
+		goto error;
+	}
+	(*instPtr)->sendDataAddr = (uintptr_t)calloc(TXRXDATA_MAX_LEN/sizeof(uint64_t), sizeof(uint64_t));
+	if ((*instPtr)->sendDataAddr == (uintptr_t)NULL) {
+		Status = EALLOC;
+		goto error;
+	}
+#endif
+	return SUCCESS;
+error:
+	Phy_Destroy(*instPtr);
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Destroy physical layer inctance, free allocated memory.
+ * 
+ * @param   instPtr  a pointer to physical instance
+ * 
+ * @return  NONE
+ * 
+ ******************************************************************************/
+void Phy_Destroy(PHY_INST* instPtr) {
+	if (instPtr == NULL){
+		return;
+	}
+#ifdef EMULATION
+	free((void*)instPtr->antConfigAddr);
+	free((void*)instPtr->recvDataAddr);
+	free((void*)instPtr->sendDataAddr);
+#endif
+	free(instPtr);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Start physical layer
+ * 
+ * @param   instPtr  a pointer to physical instance
+ * 
+ * @return  NONE
+ * 
+ ******************************************************************************/
+void Phy_Start(PHY_INST* instPtr) {
+	ASSERT(instPtr != NULL);
+	uint32_t phyMainCtrl = PhyRead(instPtr, PHY_MAIN_CTRL);
+	if((phyMainCtrl & PHY_MAIN_CTRL_EN_MASK) == PHY_MAIN_CTRL_EN_EN) {
+		DBG_WARNING("Physical layer was allready enabled.\n");
+	}
+	instPtr->isPhyEn = true;
+	// Enable CRC check automatically
+	PhyWrite(instPtr, PHY_MAIN_CTRL, (phyMainCtrl | PHY_MAIN_CTRL_EN_EN));
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Halt physical layer operation
+ * 
+ * @param   instPtr  a pointer to physical instance
+ * 
+ * @return  NONE
+ * 
+ ******************************************************************************/
+void Phy_Halt(PHY_INST* instPtr) {
+	ASSERT(instPtr != NULL);
+	uint32_t phyMainCtrl = PhyRead(instPtr, PHY_MAIN_CTRL);
+	if((phyMainCtrl & PHY_MAIN_CTRL_EN_MASK) == PHY_MAIN_CTRL_EN_DSBL) {
+		DBG_WARNING("Physical layer was allready halted.\n");
+	}
+	instPtr->isPhyEn = false;
+	PhyWrite(instPtr, PHY_MAIN_CTRL, (phyMainCtrl & (~PHY_MAIN_CTRL_EN_MASK)));
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Set physical layer working mode.
+ * 
+ * @param   instPtr  a pointer to physical instance
+ * @param   modeCod  intened mode code
+ * 
+ * @return  SUCCESS
+ * 			other
+ * 
+ ******************************************************************************/
+int32_t Phy_SetMode(PHY_INST* instPtr, PHY_MODE modeCod) {
+	ASSERT(instPtr != NULL);
+
+	uint32_t phyMainCtrl = PhyRead(instPtr, PHY_MAIN_CTRL) & ~PHY_MAIN_CTRL_MODE_MASK;
+	switch (modeCod) {
+	case PHY_MODE_NONE:
+		phyMainCtrl |= PHY_MAIN_CTRL_MODE_NONE;
+		break;
+	case PHY_MODE_LISTEN:
+		phyMainCtrl |= PHY_MAIN_CTRL_MODE_LISTEN;
+		break;
+	case PHY_MODE_SCHEDULE:
+		phyMainCtrl |= PHY_MAIN_CTRL_MODE_SCHEDULE;
+		break;
+	case PHY_MODE_PULL:
+		phyMainCtrl |= PHY_MAIN_CTRL_MODE_PULL;
+		break;
+	default:
+		return FAILURE;
+		break;
+	}
+	PhyWrite(instPtr, PHY_MAIN_CTRL, phyMainCtrl);
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Setup next slot operation.
+ * 
+ * @param   instPtr  a pointer to physical instance
+ * @param   txrxMode tor type of next slot
+ * @param   frameType frame type of next slot
+ * 
+ * @return  SUCCESS
+ * 			other
+ * 
+ ******************************************************************************/
+int32_t Phy_SetupNextSlot(PHY_INST* instPtr, PHY_TOR_TYPE txrxMode,
+		L1_FRAME_TYPE frameType, uint8_t* dataBuff) {
+	ASSERT(instPtr != NULL);
+	int32_t Status;
+	uint32_t phyModeCtrl, hopNum;
+	uint16_t* hopPattern = NULL;
+	// Implement a ping-pong flow, offset always is 0 or half of buffer depth.
+	instPtr->antConfigOffset = (ANTCONFIG_MAX_LEN >> 1) - instPtr->antConfigOffset;
+	uint32_t antConfigAddr = instPtr->antConfigAddr + instPtr->antConfigOffset;
+
+	instPtr->TOR.next = txrxMode;
+	instPtr->frameType.next = frameType;
+
+	switch (txrxMode) {
+	case PHY_TOR_SUSPEND:
+		phyModeCtrl = PHY_MODE_CTRL_TOR_SUSPEND;
+		break;
+	case PHY_TOR_RX:
+		phyModeCtrl = PHY_MODE_CTRL_TOR_RX;
+		break;
+	case PHY_TOR_TX:
+		phyModeCtrl = PHY_MODE_CTRL_TOR_TX;
+		break;
+	default:
+		return EPARAM;
+	}
+	switch (frameType) {
+	case L1_2KBPS_20MS_FRAME:
+		phyModeCtrl |= PHY_MODE_CTRL_FRAME_2KBPS_20MS;
+		hopNum = L1_FRAME_2KBPS_20MS_HOPS;
+		hopPattern = hopPattern_10KBPS_10MS;
+		break;
+	case L1_2KBPS_100MS_FRAME:
+		phyModeCtrl |= PHY_MODE_CTRL_FRAME_2KBPS_100MS;
+		hopNum = L1_FRAME_2KBPS_100MS_HOPS;
+		hopPattern = hopPattern_2KBPS_100MS;
+		break;
+	case L1_10KBPS_10MS_FRAME:
+		phyModeCtrl |= PHY_MODE_CTRL_FRAME_10KBPS_10MS;
+		hopNum = L1_FRAME_10KBPS_10MS_HOPS;
+		hopPattern = hopPattern_10KBPS_10MS;
+		break;
+	case L1_10KBPS_20MS_FRAME:
+		phyModeCtrl |= PHY_MODE_CTRL_FRAME_10KBPS_20MS;
+		hopNum = L1_FRAME_10KBPS_20MS_HOPS;
+		hopPattern = hopPattern_10KBPS_20MS;
+		break;
+	case L1_40KBPS_20MS_FRAME:
+		phyModeCtrl |= PHY_MODE_CTRL_FRAME_200KBPS_5MS;
+		hopNum = L1_FRAME_200KBPS_5MS_HOPS;
+		hopPattern = hopPattern_200KBPS_5MS;
+		break;
+	case L1_40KBPS_10MS_FRAME:
+		phyModeCtrl |= PHY_MODE_CTRL_FRAME_40KBPS_10MS;
+		hopNum = L1_FRAME_40KBPS_10MS_HOPS;
+		hopPattern = hopPattern_40KBPS_10MS;
+		break;
+	case L1_200KBPS_5MS_FRAME:
+		phyModeCtrl |= PHY_MODE_CTRL_FRAME_200KBPS_5MS;
+		hopNum = L1_FRAME_200KBPS_5MS_HOPS;
+		hopPattern = hopPattern_200KBPS_5MS;
+		break;
+	case L1_1M2BPS_5MS_FRAME:
+		phyModeCtrl |= PHY_MODE_CTRL_FRAME_1M2BPS_5MS;
+		hopNum = L1_FRAME_1M2BPS_5MS_HOPS;
+		hopPattern = hopPattern_1M2BPS_5MS;
+		break;
+	default:
+		return EPARAM;
+		break;
+	}
+	hopPattern = (instPtr->isPresetHop) ? hopPattern : hopPattern_Config;
+
+	uint8_t* dataSrcPtr = (uint8_t*)(&(instPtr->antCoinfoPtr));
+	for (int32_t i = 0; i < hopNum; i++) {
+		instPtr->antCoinfoPtr.antFreq[1] = (uint8_t)(hopPattern[i] & 0x00FF);
+		instPtr->antCoinfoPtr.antFreq[0] = (uint8_t)(
+				(hopPattern[i] >> 8) & 0x00FF);
+		memcpy((uint8_t*) (antConfigAddr + i * sizeof(PHY_ANT_CONFIG)),
+				dataSrcPtr, sizeof(PHY_ANT_CONFIG));
+	}
+	uint32_t antCtrl = (instPtr->antConfigOffset & ANT_CONFIG_OFFSET_MASK)
+			| ((hopNum << ANT_CONFIG_NUM_SHIFT) & ANT_CONFIG_NUM_MASK)
+			| ((sizeof(PHY_ANT_CONFIG) << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK);
+
+/*
+	memcpy((uint8_t*)antConfigDataAddr, hopPattern, hopNum*sizeof(uint16_t));
+	uint32_t antCtrl = (instPtr->antCoinfigOffset & ANT_CONFIG_OFFSET_MASK)
+			| ((hopNum << ANT_CONFIG_NUM_SHIFT) & ANT_CONFIG_NUM_MASK)
+			| ((sizeof(uint16_t) << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK);
+*/
+	PhyWrite(instPtr, PHY_MODE_CTRL, phyModeCtrl|PHY_MODE_CTRL_CRC_EN);
+	PhyWrite(instPtr, ANT_CONFIG, antCtrl);
+
+
+	// Trigger physical configuration.
+	if(txrxMode == PHY_TOR_TX) {
+		Status = Phy_SetSendData(instPtr, frameType, dataBuff);
+		if(Status != SUCCESS) {
+			DBG_ERROR("Failed to apply send data.\n");
+			return Status;
+		}
+	}
+	PhyWrite(instPtr, SLOT_CMD, SLOT_CMD_KEY); // Phy statr fetching data.
+	return SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Get coarse frequency estimation of last valid frame.
+ *
+ * @param   instPtr  a pointer to physical instance
+ *
+ * @return  SUCCESS If load the data successfully.
+ *          FAILURE If last receive frame is not valid.
+ *
+ ******************************************************************************/
+
+double Phy_GetCoarseFreqEst(PHY_INST* instPtr) {
+	ASSERT(instPtr != NULL);
+	uint32_t regValue;
+	uint8_t acqFreqIdx;
+	int8_t syncFreqIdx;
+	L1_FRAME_TYPE frameType;
+	double freqEst;
+
+	frameType = Phy_GetLastRecvFrameType(instPtr);
+	if(frameType > L1_1M2BPS_5MS_FRAME  || frameType == L1_NONE_FRAME){
+		return INFINITY; // FIXME
+	}
+	regValue = PhyRead(instPtr, COASE_FREQEST);
+	acqFreqIdx = (regValue >> COASE_FREQEST_ACQ_SHIFT) && COASE_FREQEST_ACQ_MASK;
+	acqFreqIdx = 80 - acqFreqIdx;
+	syncFreqIdx = (regValue >> COASE_FREQEST_SYNC_SHIFT) && COASE_FREQEST_SYNC_MASK;
+	syncFreqIdx = 8 - syncFreqIdx;
+	if(frameType >= L1_200KBPS_5MS_FRAME) {
+		freqEst = (double)acqFreqIdx*(250e3/4);
+		freqEst += (double)syncFreqIdx*1.5e6/64/128;
+	}
+	else {
+		freqEst = acqFreqIdx*(250e3/4);
+		freqEst += (double)syncFreqIdx*12e6/64/128;
+	}
+
+	return freqEst;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get the corresponding frequency hopping pattern length of a
+ * 			specified L1 frame type.
+ *
+ * @param   frameType	a L1 frame type enumeration.
+ *
+ * @return  SUCCESS
+ * 			FAILURE	frame type cannot be recognized
+ *
+ ******************************************************************************/
+uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType){
+	switch (frameType) {
+	case L1_2KBPS_20MS_FRAME:
+		return L1_FRAME_2KBPS_20MS_HOPS;
+	case L1_2KBPS_100MS_FRAME:
+		return L1_FRAME_2KBPS_100MS_HOPS;
+	case L1_10KBPS_10MS_FRAME:
+		return L1_FRAME_10KBPS_10MS_HOPS;
+	case L1_10KBPS_20MS_FRAME:
+		return L1_FRAME_10KBPS_20MS_HOPS;
+	case L1_40KBPS_20MS_FRAME:
+		return L1_FRAME_40KBPS_20MS_HOPS;
+	case L1_40KBPS_10MS_FRAME:
+		return L1_FRAME_40KBPS_10MS_HOPS;
+	case L1_200KBPS_5MS_FRAME:
+		return L1_FRAME_200KBPS_5MS_HOPS;
+	case L1_1M2BPS_5MS_FRAME:
+		return L1_FRAME_1M2BPS_5MS_HOPS;
+	default:
+		return L1_FRAME_NONE_LEN;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get the corresponding time compensation value (time interval from 
+ * 			frame start to frame sync)
+ *
+ * @param   frameType	a L1 frame type enumeration.
+ *
+ * @return  SUCCESS
+ * 			FAILURE	frame type cannot be recognized
+ *
+ ******************************************************************************/
+uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType){
+	switch (frameType) {
+	case L1_2KBPS_20MS_FRAME:
+		return L1_FRAME_2KBPS_20MS_COMP;
+	case L1_2KBPS_100MS_FRAME:
+		return L1_FRAME_2KBPS_100MS_COMP;
+	case L1_10KBPS_10MS_FRAME:
+		return L1_FRAME_10KBPS_10MS_COMP;
+	case L1_10KBPS_20MS_FRAME:
+		return L1_FRAME_10KBPS_20MS_COMP;
+	case L1_40KBPS_20MS_FRAME:
+		return L1_FRAME_40KBPS_20MS_COMP;
+	case L1_40KBPS_10MS_FRAME:
+		return L1_FRAME_40KBPS_10MS_COMP;
+	case L1_200KBPS_5MS_FRAME:
+		return L1_FRAME_200KBPS_5MS_COMP;
+	case L1_1M2BPS_5MS_FRAME:
+		return L1_FRAME_1M2BPS_5MS_COMP;
+	default:
+		return L1_FRAME_NONE_LEN;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Setup a frequency hopping pattern.
+ *
+ * @param   patternBuff	a pointer to hopping pattern buffer
+ * @param   patternLen	a integer indicate the length of hopping pattern.
+ *
+ * @return  SUCCESS
+ * 			FAILURE	pattern length exceeds maximum length.
+ *
+ ******************************************************************************/
+int32_t Phy_SetHopPattern(void* patternBuff, uint32_t patternLen){
+	ASSERT(patternBuff != NULL);
+	if(patternLen > L1_FRAME_MAX_HOPS){
+		return FAILURE;
+	}
+	memcpy(hopPattern_Config, patternBuff, patternLen*sizeof(uint16_t));
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Setup a specific timer word register in physical controller.
+ *
+ * @param   patternBuff	a pointer to hopping pattern buffer
+ * @param   patternLen	a integer indicate the length of hopping pattern.
+ *
+ * @return  SUCCESS
+ * 			FAILURE	pattern length exceeds maximum length.
+ *
+ ******************************************************************************/
+int32_t Phy_SetTimeWord(PHY_INST* instPtr, const TIME_WORD* tmWord, PHY_TIME_WORD_TYPE tmType){
+	ASSERT(instPtr != NULL);
+	if(tmWord->frac_part>=PHY_TIME_WORD_L_MAX){
+		return EPARAM;
+	}
+	switch(tmType){
+	case TIME_WORD_POLL:
+		PhyWrite(instPtr, POLLTIME_L, tmWord->frac_part);
+		PhyWrite(instPtr, POLLTIME_H, tmWord->int_part);
+		break;
+	case TIME_WORD_LISTEN_TIMEOUT:
+		PhyWrite(instPtr, LISTENTIMEOUT_L, tmWord->frac_part);
+		PhyWrite(instPtr, LISTENTIMEOUT_H, tmWord->int_part);
+		break;
+	default:
+		return EPARAM;
+	}
+	return SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Get the frame sync time of last received frame.
+ *
+ * @param   instPtr  a pointer to physical instance
+ * @param   frameSycT   a pointer to the frame sync time data buffer.
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void Phy_GetFrameSyncTimeStamp(PHY_INST* instPtr, TIME_WORD* frameSyncT) {
+	ASSERT(instPtr != NULL);
+	ASSERT(frameSyncT != NULL);
+	frameSyncT->int_part = PhyRead(instPtr, TM_TARGET_H);
+	frameSyncT->frac_part = PhyRead(instPtr, TM_TARGET_L);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get the frame sync time of last received frame.
+ *
+ * @param   instPtr  a pointer to physical instance
+ * @param   slotStart   a pointer to the time data buffer.
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void Phy_GetLastSlotStartTimeStamp(PHY_INST* instPtr, TIME_WORD* slotStart) {
+	ASSERT(instPtr != NULL);
+	ASSERT(slotStart != NULL);
+	slotStart->int_part = PhyRead(instPtr, FSTIME_H);
+	slotStart->frac_part = PhyRead(instPtr, FSTIME_L);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get received data (base on PL Record), store it to data buffer.
+ *
+ * @param   instPtr  a pointer to physical layer control instance.
+ *
+ * @return  SUCCESS
+ * 			FAILURE	last frame type cannot be recognized.
+ *
+ ******************************************************************************/
+void Phy_RetrieveRecvData(PHY_INST* instPtr, uint8_t* dataBuff) {
+	ASSERT(instPtr != NULL);
+	ASSERT(dataBuff != NULL);
+	uint32_t frameLen, offset;
+
+	frameLen = (PhyRead(instPtr, RECVDATA_STATE) & RECVDATA_STATE_LEN_MASK) >> RECVDATA_STATE_LEN_SHIFT;
+	offset = (PhyRead(instPtr, RECVDATA_STATE) & RECVDATA_STATE_OFFSET_MASK) >> RECVDATA_STATE_OFFSET_SHIFT;
+	
+	memcpy(dataBuff, (uint8_t*)(instPtr->recvDataAddr + offset), frameLen);
+}

datalink814_ge/src/phy_ctrl/phy_ctrl.h

@@ -0,0 +1,268 @@
+/*****************************************************************************/
+/**
+ * Description: Physical layer control definitions and function prototypes.
+ * 
+ * Date: 2021-12-04 16:32
+ * LastEditTime: 2023-04-24 17:41
+ * Revisions: Rev 0.1
+ * History: 
+ * [2021-12-08]: Initial version.
+ * [2022-06-18]: New branch for glink control purpose:
+ * 				 -Add poll mode, physical layer will start Tx/Rx procedure
+ * 				  at specific time stamp.
+ * 				 -Add 61/37 beam switch
+ * 				 -Code simplification.
+ * [2023-04-24]: Feature add:
+ * 				- Read frame type from PL status register.
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+#ifndef PHY_CTRL_H_
+#define PHY_CTRL_H_
+
+/***************************** Include Files *********************************/
+#include <stdint.h>
+#include "phy_ctrlreg.h"
+#include "../common.h"
+#include "../time_ctrl/time_ctrl.h"
+/************************** Constant Definitions *****************************/
+#define TMWORD_FRAC_MAX	500000
+#define ANTCONFIG_MAX_LEN	8192
+#define TXRXDATA_MAX_LEN	2048
+#define NUM_ANT_SUBNRRW_PATTERN    37
+#define NUM_ANT_NRRW_PATTERN    61
+#define INIT_BEAM_NO 0
+#define INIT_ANT_WD ANT_BEAM_120
+#define INIT_ANT_NO 0
+
+#define L1_FRAME_NONE_HOPS           UINT32_MAX
+#define L1_FRAME_MAX_HOPS            81
+#define L1_FRAME_2KBPS_20MS_HOPS     1
+#define L1_FRAME_2KBPS_100MS_HOPS    81
+#define L1_FRAME_10KBPS_10MS_HOPS    1
+#define L1_FRAME_10KBPS_20MS_HOPS    11
+#define L1_FRAME_40KBPS_20MS_HOPS    19
+#define L1_FRAME_40KBPS_10MS_HOPS    9
+#define L1_FRAME_200KBPS_5MS_HOPS    20
+#define L1_FRAME_1M2BPS_5MS_HOPS     20
+
+#define L1_FRAME_NONE_LEN           UINT32_MAX// byte
+#define L1_FRAME_LEN_MAX           	(8192/8) // byte
+#define L1_FRAME_2KBPS_20MS_LEN     1        // byte
+#define L1_FRAME_2KBPS_100MS_LEN    312/8    // byte
+#define L1_FRAME_10KBPS_10MS_LEN    1        // byte
+#define L1_FRAME_10KBPS_20MS_LEN    (232/8)  // byte
+#define L1_FRAME_40KBPS_20MS_LEN    (2152/8) // byte
+#define L1_FRAME_40KBPS_10MS_LEN    (712/8)  // byte
+#define L1_FRAME_200KBPS_5MS_LEN    (2040/8) // byte
+#define L1_FRAME_1M2BPS_5MS_LEN     (8176/8) // byte
+
+#define L1_FRAME_NONE_COMP			UINT32_MAX  // *10ns(Timer_L)
+#define L1_FRAME_2KBPS_20MS_COMP	1841158  	// *10ns(Timer_L)
+#define L1_FRAME_2KBPS_100MS_COMP	1841158 	// *10ns(Timer_L)
+#define L1_FRAME_10KBPS_10MS_COMP	847733  	// *10ns(Timer_L)
+#define L1_FRAME_10KBPS_20MS_COMP	847733  	// *10ns(Timer_L)
+#define L1_FRAME_40KBPS_20MS_COMP	110667  	// *10ns(Timer_L)
+#define L1_FRAME_40KBPS_10MS_COMP	110667  	// *10ns(Timer_L)
+#define L1_FRAME_200KBPS_5MS_COMP	19725   	// *10ns(Timer_L)
+#define L1_FRAME_1M2BPS_5MS_COMP	19725  		// *10ns(Timer_L)
+
+
+#define PHY_TIME_WORD_H_MAX			UINT32_MAX
+#define PHY_TIME_WORD_L_MAX			0x0007A120 // 5ms/10ns
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+typedef enum {
+	L1_NONE_FRAME = 0,
+	L1_2KBPS_20MS_FRAME = 1,
+	L1_2KBPS_100MS_FRAME = 2,
+	L1_10KBPS_10MS_FRAME = 3,
+	L1_10KBPS_20MS_FRAME = 4,
+	L1_40KBPS_20MS_FRAME = 5,
+	L1_40KBPS_10MS_FRAME = 6,
+	L1_200KBPS_5MS_FRAME = 7,
+	L1_1M2BPS_5MS_FRAME = 8
+} L1_FRAME_TYPE;
+
+typedef struct {
+	/* Antenna control frame head 0xAA */
+	uint8_t head;
+	/* default 0, reserved for further use */
+	uint8_t ctrlWord;
+	/* high 4 bits specified beam mode.
+	 * low 4 bits specified power control */
+	uint8_t antMode;
+	/* off-axis angle range is 0~60,
+	 * 0.1 degree each LSB */
+	uint8_t oaxis[2];
+	/* round-axis angle range is 0~360,
+	 * 0.1 degree each LSB */
+	uint8_t raxis[2];
+	/* 0~3500Mhz, step 1MHz */
+	uint8_t antFreq[2];
+	/* in single tr mode, 0~63 specified tr channel
+	 * in single subarray mode, 0~3 specified the subarray
+	 * Only in debug mode*/
+	uint8_t trSlect;
+	/* Antenna attenuation 0~31, 0.5dB each LSB, Only in debug mode */
+	uint8_t antAtt;
+	/* 0~63, 5.625 degree each LSB, Only in debug mode*/
+	uint8_t phase;
+	/* 0x00 Nromal RX, 0x01 Normal TX
+	 * 0x11~0xA1 beam debug mode (TR duty 1%~10%)*/
+	uint8_t rxtxMode;
+	/* 0x00 Normal, 0x01 single tr calibration */
+	uint8_t calibrMode;
+	/* reserved for further use */
+	uint8_t reserved;
+	/* DD enable */
+	uint8_t ddEn;
+	/* DD mgc */
+	uint8_t ddMgc;
+	/* [7:4]RF enable: 0-On, 1-Off(Default); [3:0]Work mode: 0(default) */
+	uint8_t rfCtrl;
+	/* RF MGC control: 0~31, 1dB each LSB*/
+	uint8_t rfMgc;
+	/* RF channel 1&2 calibration mgc: [7:4] Channle1 - max 15db, 1dB each LSB
+	 * 								   [3:0] Channle2 - max 15db, 1dB each LSB*/
+	uint8_t rf12CalMgc;
+	/* RF channel 3&4 calibration mgc: [7:4] Channle3 - max 15db, 1dB each LSB
+	 * 								   [3:0] Channle4 - max 15db, 1dB each LSB*/
+	uint8_t rf34CalMgc;
+	/* Receive channel 1 MGC: 0~31, 1dB each LSB */
+	uint8_t rcv1Mgc;
+	/* Receive channel 2 MGC: 0~31, 1dB each LSB */
+	uint8_t rcv2Mgc;
+	/* Receive channel 3 MGC: 0~31, 1dB each LSB */
+	uint8_t rcv3Mgc;
+	/* Receive channel 4 MGC: 0~31, 1dB each LSB */
+	uint8_t rcv4Mgc;
+	/* Antenna control frame tail 0xCC */
+	uint8_t tail;
+	uint8_t dummy[6];
+} PHY_ANT_CONFIG;
+
+typedef struct {
+	/* off-axis angle range is 0~60,
+	 * 0.1 degree each LSB */
+	uint16_t oaxis;
+	/* round-axis angle range is 0~360,
+	 * 0.1 degree each LSB */
+	uint16_t raxis;
+} PHY_ANT_ANGLE;
+
+typedef enum {
+	TIME_WORD_NONE = 0,
+	TIME_WORD_POLL = 1,
+	TIME_WORD_LISTEN_TIMEOUT = 2
+} PHY_TIME_WORD_TYPE;
+
+typedef enum {
+	ANT_BEAM_NONE = 0,
+	ANT_BEAM_120 = 1,
+	ANT_BEAM_60 = 2,
+	ANT_BEAM_25 = 3,
+	ANT_BEAM_8 = 4
+} PHY_ANT_BEAM_WIDTH;
+
+typedef enum {
+	PHY_TOR_SUSPEND = 0,
+	PHY_TOR_TX = 1,
+	PHY_TOR_RX = 2
+} PHY_TOR_TYPE;
+
+typedef enum {
+	PHY_MODE_NONE = 0,
+	PHY_MODE_LISTEN = 1,
+	PHY_MODE_SCHEDULE = 2,
+	PHY_MODE_PULL = 3
+} PHY_MODE;
+
+typedef struct {
+	uint32_t devId;
+	uint32_t txBramId;
+	uint32_t rxBramId;
+	uint32_t antBramId;
+	uintptr_t baseAddr;
+} PHY_CONFIG;
+
+typedef struct {
+	int32_t last;
+	int32_t curr;
+	int32_t next;
+} PHY_RCD;
+
+typedef struct {
+	PHY_CONFIG phyCofig; // Device address configs
+	uintptr_t recvDataAddr;
+	uintptr_t sendDataAddr;
+	uintptr_t antConfigAddr;
+	bool isPhyEn;			// is physical layer running
+	bool isAcq;				// is last reception acquisition success
+	bool isFrameSync;		// is last reception frame sync success
+	bool isDecode;			// is last reception decode success
+	bool isValid;		 	// is last reception frame data valid (crc check pass)
+	bool isPresetHop;	 	// is using preset frequency hop
+	PHY_RCD antNo;		 	// antenna number record
+	PHY_RCD beamNo;		 	// beam number record
+	PHY_RCD beamWd;		 	// beam width record
+	PHY_RCD TOR;		 	// tx rx state record
+	PHY_RCD frameType;	 	// frame type record
+	uint32_t sendDataOffset;  // antenna configuration bram offset (to implement ping-pong data flow)
+	uint32_t antConfigOffset; // antenna configuration bram offset (to implement ping-pong data flow)
+	PHY_ANT_CONFIG antCoinfoPtr;// antenna configuration pointer
+} PHY_INST;
+
+/************************** Variable Definitions *****************************/
+extern uint16_t hopPattern_Config[L1_FRAME_MAX_HOPS];
+extern uint16_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS];
+extern uint16_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS];
+extern uint16_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS];
+extern uint16_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS];
+extern uint16_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS];
+extern uint16_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS];
+extern uint16_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS];
+extern uint16_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS];
+
+extern PHY_ANT_ANGLE antSubnrrwPattern[NUM_ANT_SUBNRRW_PATTERN];
+extern PHY_ANT_ANGLE antNrrwPattern[NUM_ANT_NRRW_PATTERN];
+
+/************************** Function Prototypes ******************************/
+int32_t Phy_InstInit(PHY_INST** instPtr, PHY_CONFIG *phyConfig);
+void Phy_Destroy(PHY_INST* instPtr);
+
+void Phy_UpdateState(PHY_INST* instPtr);
+
+void Phy_Start(PHY_INST* instPtr);
+void Phy_Halt(PHY_INST* instPtr);
+int32_t Phy_SetMode(PHY_INST* instPtr, PHY_MODE modeCod);
+
+int32_t Phy_SetupNextSlot(PHY_INST* instPtr, PHY_TOR_TYPE txrxMode, L1_FRAME_TYPE frameType, uint8_t* dataBuff);
+void Phy_RetrieveRecvData(PHY_INST* instPtr, uint8_t* dataBuff);
+
+bool Phy_IsFrameDetected(PHY_INST* instPtr);
+bool Phy_IsFrameReceived(PHY_INST* instPtr);
+bool Phy_IsFrameValid(PHY_INST* instPtr);
+uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType);
+
+L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST* instPtr);
+L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST* instPtr);
+
+int32_t Phy_SetHopPattern(void* patternBuff, uint32_t patternLen);
+uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType);
+uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType);
+
+int32_t Phy_AntCoinfoInit(PHY_ANT_CONFIG* antCoinfoPtr);
+int32_t Phy_SetBeamWidth(PHY_INST* instPtr, PHY_ANT_BEAM_WIDTH beamWidth);
+int32_t Phy_SetBeamNo(PHY_INST* instPtr, int32_t beamNo);
+int32_t Phy_SetBeamAngle(PHY_INST* phyInstPtr, double offAx, double rndAx);
+int32_t Phy_SetTimeWord(PHY_INST* instPtr, const TIME_WORD* tmWord, PHY_TIME_WORD_TYPE tmType);
+
+double Phy_GetCoarseFreqEst(PHY_INST* instPtr);
+void Phy_GetFrameSyncTimeStamp(PHY_INST* instPtr, TIME_WORD* frameSyncT);
+void Phy_GetLastSlotStartTimeStamp(PHY_INST* instPtr, TIME_WORD* slotStart);
+#endif /* PHY_CTRL_H_ */

datalink814_ge/src/phy_ctrl/phy_ctrlreg.h

@@ -0,0 +1,262 @@
+/*****************************************************************************/
+/**
+ * Description: Physical layer register definitions
+ *
+ * Author: Fan Hao
+ * Date: 2021-11-16 00:08
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-06-18 17:32
+ * Revisions: Rev 0.0
+ * History:
+ * [2021-11-16]: Initial version.
+ * [2022-06-18]: New branch for glink control purpose:
+ *               -Add poll modephysical layer will start Tx/Rx procedure
+ * 				  at specific time stamp.
+ * 
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+#ifndef PHY_CTRLREG_H_
+#define PHY_CTRLREG_H_
+
+/***************************** Include Files *********************************/
+#include "../util/util.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define PhyRead(instPtr, addr)			IO_In32(instPtr->phyCofig.baseAddr + addr)
+#define PhyWrite(instPtr, addr, value)	IO_Out32(instPtr->phyCofig.baseAddr + addr, value)
+
+/************************** Constant Definitions *****************************/
+/**
+ * Register: PHY_MAIN_CTRL
+ */
+#define PHY_MAIN_CTRL                   0X00000000U
+#define PHY_MAIN_CTRL_EN_SHIFT          0
+#define PHY_MAIN_CTRL_EN_WIDTH          1
+#define PHY_MAIN_CTRL_EN_MASK           0x00000001U
+#define PHY_MAIN_CTRL_MODE_SHIFT        8
+#define PHY_MAIN_CTRL_MODE_WIDTH        8
+#define PHY_MAIN_CTRL_MODE_MASK         0x0000FF00U
+
+#define PHY_MAIN_CTRL_EN_EN             0x00000001U
+#define PHY_MAIN_CTRL_EN_DSBL           0x00000000U
+#define PHY_MAIN_CTRL_MODE_NONE         0x00000000U
+#define PHY_MAIN_CTRL_MODE_LISTEN       0x00000100U
+#define PHY_MAIN_CTRL_MODE_SCHEDULE     0x00000200U
+#define PHY_MAIN_CTRL_MODE_PULL         0x00000300U
+
+/**
+ * Register: TXRX_CTRL
+ */
+#define PHY_MODE_CTRL    					0x00000004U
+#define PHY_MODE_CTRL_TOR_SHIFT             0
+#define PHY_MODE_CTRL_TOR_WIDTH             8
+#define PHY_MODE_CTRL_TOR_MASK              0x000000FFU
+#define PHY_MODE_CTRL_FRAME_SHIFT           8
+#define PHY_MODE_CTRL_FRAME_WIDTH           8
+#define PHY_MODE_CTRL_FRAME_MASK            0x0000FF00U
+#define PHY_MODE_CTRL_CRC_SHIFT           	8
+#define PHY_MODE_CTRL_CRC_WIDTH           	16
+#define PHY_MODE_CTRL_CRC_MASK            	0x00FF0000U
+
+#define PHY_MODE_CTRL_TOR_SUSPEND           0x00000000U
+#define PHY_MODE_CTRL_TOR_TX                0x00000001U
+#define PHY_MODE_CTRL_TOR_RX                0x00000002U
+
+#define PHY_MODE_CTRL_FRAME_NONE            0x00000000U
+#define PHY_MODE_CTRL_FRAME_2KBPS_20MS      0x00000100U
+#define PHY_MODE_CTRL_FRAME_2KBPS_100MS     0x00000200U
+#define PHY_MODE_CTRL_FRAME_10KBPS_10MS     0x00000300U // Initial Scan Frame
+#define PHY_MODE_CTRL_FRAME_10KBPS_20MS     0x00000400U // Benchmark Frame
+#define PHY_MODE_CTRL_FRAME_40KBPS_20MS     0x00000500U
+#define PHY_MODE_CTRL_FRAME_40KBPS_10MS     0x00000600U
+#define PHY_MODE_CTRL_FRAME_200KBPS_5MS     0x00000700U // 2-Way ACQ Frame, Management Frame, Service Frame
+#define PHY_MODE_CTRL_FRAME_1M2BPS_5MS      0x00000800U // Bistatic Synthetic Aperture Radar Frame
+
+#define PHY_MODE_CTRL_CRC_EN            	0x00010000U
+#define PHY_MODE_CTRL_CRC_DSBL            	0x00000000U
+/**
+ * Register: POLLTIME_L
+ */
+#define POLLTIME_L				0x00000008U
+#define POLLTIME_L_SHIFT		0
+#define POLLTIME_L_WIDTH		32
+#define POLLTIME_L_MASK 		0xFFFFFFFFU
+
+/**
+ * Register: POLLTIME_H
+ */
+#define POLLTIME_H				0x0000000CU
+#define POLLTIME_H_SHIFT		0
+#define POLLTIME_H_WIDTH		32
+#define POLLTIME_H_MASK 		0xFFFFFFFFU
+
+
+/**
+ * Register: TIMEOUT_L
+ */
+#define LISTENTIMEOUT_L			0x00000010U
+#define LISTENTIMEOUT_L_SHIFT	0
+#define LISTENTIMEOUT_L_WIDTH	32
+#define LISTENTIMEOUT_L_MASK	0xFFFFFFFFU
+
+/**
+ * Register: TIMEOUT_H
+ */
+#define LISTENTIMEOUT_H			0x00000014U
+#define LISTENTIMEOUT_H_SHIFT	0
+#define LISTENTIMEOUT_H_WIDTH	32
+#define LISTENTIMEOUT_H_MASK	0xFFFFFFFFU
+
+/**
+ * Register: ANT_CTRL
+ */
+#define ANT_CONFIG					0x00000018U
+#define ANT_CONFIG_OFFSET_SHIFT		0
+#define ANT_CONFIG_OFFSET_WIDTH		16
+#define ANT_CONFIG_OFFSET_MASK		0x0000FFFFU
+#define ANT_CONFIG_LEN_SHIFT		16
+#define ANT_CONFIG_LEN_WIDTH		8
+#define ANT_CONFIG_LEN_MASK			0x00FF0000U
+#define ANT_CONFIG_NUM_SHIFT		24
+#define ANT_CONFIG_NUM_WIDTH		8
+#define ANT_CONFIG_NUM_MASK			0xFF000000U
+
+/**
+ * Register: SEND_DATA_CMD
+ */
+#define SEND_DATA_CMD			0x0000001CU
+#define SEND_DATA_CMD_SHIFT		0
+#define SEND_DATA_CMD_WIDTH		32
+#define SEND_DATA_CMD_MASK		0xFFFFFFFFU
+
+#define SEND_DATA_CMD_LEN_SHIFT             0
+#define SEND_DATA_CMD_LEN_WIDTH             16
+#define SEND_DATA_CMD_LEN_MASK              0x0000FFFFU
+#define SEND_DATA_CMD_OFFSET_SHIFT          16
+#define SEND_DATA_CMD_OFFSET_WIDTH          16
+#define SEND_DATA_CMD_OFFSET_MASK           0xFFFF0000U
+
+/**
+ * Register: SEND_CONFIG_CMD
+ */
+#define SLOT_CMD				0x00000020U
+#define SLOT_CMD_SHIFT			0
+#define SLOT_CMD_WIDTH			32
+#define SLOT_CMD_MASK			0xFFFFFFFFU
+#define SLOT_CMD_KEY			0x434D442EU
+
+/**
+ * Register: TXRX_STATE
+ */
+#define TXRX_STATE				0x00000024U
+#define TXRX_STATE_ACQ_SHIFT	0
+#define TXRX_STATE_ACQ_WIDTH	8
+#define TXRX_STATE_ACQ_MASK		0x000000FFU
+#define TXRX_STATE_ACQ_SUCCESS	0x00000001U
+#define TXRX_STATE_ACQ_FAIL		0x00000002U
+
+#define TXRX_STATE_FSYNC_SHIFT 		8
+#define TXRX_STATE_FSYNC_WIDTH  	8
+#define TXRX_STATE_FSYNC_MASK		0x0000FF00U
+#define TXRX_STATE_FSYNC_SUCCESS	0x00000100U
+#define TXRX_STATE_FSYNC_FAIL		0x00000200U
+
+#define TXRX_STATE_DECODE_SHIFT		16
+#define TXRX_STATE_DECODE_WIDTH		8
+#define TXRX_STATE_DECODE_MASK		0x00FF0000U
+#define TXRX_STATE_DECODE_SUCCESS	0x00010000U
+#define TXRX_STATE_DECODE_FAIL		0x00020000U
+
+#define TXRX_STATE_CRC_SHIFT		24
+#define TXRX_STATE_CRC_WIDTH		8
+#define TXRX_STATE_CRC_MASK			0xFF000000U
+#define TXRX_STATE_CRC_OK			0x01000000U
+#define TXRX_STATE_CRC_ERROR		0x02000000U
+
+
+/**
+ * Register: RECVDATA_STATE
+ */
+#define RECVDATA_STATE				0x00000028U
+#define RECVDATA_STATE_LEN_SHIFT	0
+#define RECVDATA_STATE_LEN_WIDTH	16
+#define RECVDATA_STATE_LEN_MASK		0x0000FFFFU
+
+#define RECVDATA_STATE_OFFSET_SHIFT	16
+#define RECVDATA_STATE_OFFSET_WIDTH	16
+#define RECVDATA_STATE_OFFSET_MASK	0xFFFF0000U
+/**
+ * Register: FSTIME_L
+ */
+#define FSTIME_L		0x000002CU
+#define FSTIME_L_SHIFT	0
+#define FSTIME_L_WIDTH	32
+#define FSTIME_L_MASK	0xFFFFFFFFU
+
+/**
+ * Register: FSTIME_INT1
+ */
+#define FSTIME_H			0x0000030U
+#define FSTIME_H_SHIFT		0
+#define FSTIME_H_WIDTH		32
+#define FSTIME_H_MASK		0xFFFFFFFFU
+
+/**
+ * Register: TM_TARGET_L
+ */
+#define TM_TARGET_L			0x0000064U
+#define TM_TARGET_L_SHIFT	0
+#define TM_TARGET_L_WIDTH	32
+#define TM_TARGET_L_MASK	0xFFFFFFFFU
+
+/**
+ * Register: TM_TARGET_H
+ */
+#define TM_TARGET_H			0x0000038U
+#define TM_TARGET_H_SHIFT	0
+#define TM_TARGET_H_WIDTH	32
+#define TM_TARGET_H_MASK	0xFFFFFFFFU
+
+/**
+ * Register: COASEFREQEST
+ */
+#define COASE_FREQEST				0x0000003CU
+#define COASE_FREQEST_ACQ_SHIFT		0
+#define COASE_FREQEST_ACQ_WIDTH		8
+#define COASE_FREQEST_ACQ_MASK		0x000000FFU
+#define COASE_FREQEST_SYNC_SHIFT	0
+#define COASE_FREQEST_SYNC_WIDTH	16
+#define COASE_FREQEST_SYNC_MASK		0x000FF00U
+
+/**
+ * Register: FINE_FREQEST
+ */
+#define FINE_FREQEST		0x00000040U
+#define FINE_FREQEST_SHIFT	0
+#define FINE_FREQEST_WIDTH	32
+#define FINE_FREQEST_MASK	0xFFFFFFFFU
+
+/**
+ * Register: BEAM_SELECT
+ */
+#define BEAM_SELECT_INDEX		0x00000044U
+#define BEAM_SELECT_INDEX_SHIFT	0
+#define BEAM_SELECT_INDEX_WIDTH	32
+#define BEAM_SELECT_INDEX_MASK	0xFFFFFFFFU
+
+/**
+ * Register: BEAM_SELECT
+ */
+#define BEAM_AXIS			0x00000044U
+#define BEAM_AXIS_EL_SHIFT	0
+#define BEAM_AXIS_EL_WIDTH	16
+#define BEAM_AXIS_EL_MASK	0x0000FFFFU
+#define BEAM_AXIS_AZ_SHIFT	16
+#define BEAM_AXIS_AZ_WIDTH	16
+#define BEAM_AXIS_AZ_MASK	0xFFFF0000U
+
+// Reserved.
+#endif /* PHY_CTRLREG_H_ */

datalink814_ge/src/time_ctrl/time_ctrl.c

@@ -0,0 +1,221 @@
+/*****************************************************************************/
+/**
+ * Description: Time sync implementation file.
+ * 
+ * Author: Author's name
+ * Date: 2021-12-04 16:32
+ * LastEditors: FanHao
+ * LastEditTime: 2022-07-10 20:43
+ * Revisions: Rev 0.0
+ * History: 
+ * [2022-07-10]: New branch for Dijian.
+ * [2021-12-04]: Initial version.
+ * 
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include <string.h>
+#include "time_ctrl.h"
+#include "../error.h"
+#include "../common.h"
+#include "../util/util.h"
+
+/************************** Constant Definitions *****************************/
+#define VERSION_REG		0x00000004
+#define TIME_INT_REG	0x00000008
+#define TIME_FRAC_REG	0x0000000C
+#define TIME_RESET		0x00000010
+#define PRESET_HIGH		0x00000014
+#define PRESET_LOW		0x00000018
+#define TIME_ADJ_INT	0x0000001C
+#define TIME_ADJ_FRAC	0x00000020
+#define TIME_ADJ_TRIG	0x00000024
+#define CNTSTEP_OPT		0x00000028
+
+#define TM_RESET_CODE	0x5253542E
+/***************** Macros (Inline Functions) Definitions *********************/
+#define TMC_Read(instPtr, addr)			IO_In32(instPtr->config.baseAddr + addr)
+#define TMC_Write(instPtr, addr, value)	IO_Out32(instPtr->config.baseAddr + addr, value)
+
+
+/*****************************************************************************/
+/**
+ * @brief   Initialize Time-Controller Process
+ *
+ * @param   instPtr a second rank pointer to time controller instance
+ * @param	config  time controller configurations
+ *
+ * @return  SUCCESS Initialize successfully.
+ *          FAILURE Initialization failed
+ *
+ ******************************************************************************/
+int32_t TimeCtrl_Init(TIMECTRL_INST **instPtr, TIMECTRL_CONFIG *config){
+	ASSERT(config != NULL);
+	ASSERT(instPtr != NULL);
+	(*instPtr) = malloc(sizeof(TIMECTRL_INST));
+	memcpy(&((*instPtr)->config), config, sizeof(TIMECTRL_CONFIG));
+	(*instPtr)->modelVer = TMC_Read((*instPtr), VERSION_REG);
+	return SUCCESS;
+}
+
+void TimeCtrl_Destroy(TIMECTRL_INST *instPtr) {
+	free(instPtr);
+}
+
+uint32_t TimeCtrl_GetVersion(TIMECTRL_INST *instPtr){
+	return TMC_Read(instPtr, VERSION_REG);
+}
+/*****************************************************************************/
+/**
+ * @brief   Apply a reset process to time controller
+ *
+ * @param   instPtr a pointer to time controller instance
+ *
+ * @return  SUCCESS Initialize successfully.
+ *          FAILURE Initialization failed
+ *
+ ******************************************************************************/
+void TimeCtrl_Reset(TIMECTRL_INST *instPtr){
+	ASSERT(instPtr != NULL);
+	TMC_Write(instPtr, CNTSTEP_OPT, TM_RESET_CODE);
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Assert time controller reset high
+ *
+ * @param   instPtr a pointer to time controller instance
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void TimeCtrl_ResetHigh(TIMECTRL_INST *instPtr){
+	ASSERT(instPtr != NULL);
+	// TODO:
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Assert time controller reset low
+ *
+ * @param   instPtr a pointer to time controller instance
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void TimeCtrl_ResetLow(TIMECTRL_INST *instPtr){
+	ASSERT(instPtr != NULL);
+	// TODO:
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Get current time integer value.
+ *
+ * @param   instPtr a pointer to time controller instance
+ *
+ * @return  integer value
+ *
+ ******************************************************************************/
+inline TIME_INT TimeCtrl_GetIntCnt(TIMECTRL_INST *instPtr){
+	ASSERT(instPtr != NULL);
+	return TMC_Read(instPtr, TIME_INT_REG);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get current time fractional value.
+ *
+ * @param   instPtr a pointer to time controller instance
+ *
+ * @return  fractional value
+ *
+ ******************************************************************************/
+inline TIME_FRAC TimeCtrl_GetFracCnt(TIMECTRL_INST *instPtr){
+	ASSERT(instPtr != NULL);
+	return TMC_Read(instPtr, TIME_FRAC_REG);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get current time value.
+ *
+ * @param   instPtr a pointer to time controller instance
+ * @param	tmWord  a pointer to time data buffer
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void TimeCtrl_GetCurrentTime(TIMECTRL_INST *instPtr, TIME_WORD* tmWord){
+	ASSERT(instPtr != NULL);
+	ASSERT(tmWord != NULL);
+	tmWord->frac_part = TMC_Read(instPtr, TIME_FRAC_REG);
+	tmWord->int_part = TMC_Read(instPtr, TIME_INT_REG);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Get current optimal counter step adjustment value.
+ *
+ * @param   instPtr a pointer to time controller instance
+ * @param	config  a pointer to time data buffer
+ *
+ * @return  NONE.
+ *
+ ******************************************************************************/
+void TimeCtrl_GetCurrentStep(TIMECTRL_INST *instPtr, TIME_FRAC* tmFrac) {
+	ASSERT(instPtr != NULL);
+	ASSERT(tmFrac != NULL);
+	*tmFrac = TMC_Read(instPtr, CNTSTEP_OPT);
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief   Set a new optimal adjustment value to the counter step.
+ *
+ * @param   instPtr a pointer to time controller instance
+ * @param	tmWord  a pointer to the time data
+ * @param	type    adjustment type
+ *
+ * @return  NONE.
+ *
+ ******************************************************************************/
+void TimeCtrl_TimeAdjust(TIMECTRL_INST *instPtr, const TIME_WORD* tmWord, TIMECTRL_ADJ_TYPE type){
+	ASSERT(instPtr != NULL);
+	ASSERT(tmWord != NULL);
+	if(type < TM_ADJ_ADD || TM_ADJ_ADD > TM_ADJ_SET){
+		DBG_ERROR("Unsupported adjustment type: %d", type);
+		return;
+	}
+	if(((int32_t)tmWord->frac_part) > COUNTE_FRAC_MAX ) {
+		DBG_ERROR("Invalid fractional value 0x%08X (should <= 0x%08X).\n", 
+			tmWord->frac_part, COUNTE_FRAC_MAX);
+		return;
+	}
+	TMC_Write(instPtr, TIME_ADJ_FRAC, tmWord->frac_part);
+	TMC_Write(instPtr, TIME_ADJ_INT, tmWord->int_part);
+	TMC_Write(instPtr, TIME_ADJ_TRIG, type);
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Set a new optimal adjustment value to the counter step.
+ *
+ * @param   instPtr a pointer to time controller instance
+ * @param	tmFrac  a pointer to the time data
+ *
+ * @return  NONE.
+ *
+ ******************************************************************************/
+void TimeCtrl_SetOptimizeStep(TIMECTRL_INST* instPtr, TIME_FRAC* tmFrac) {
+	ASSERT(instPtr != NULL);
+	ASSERT(tmFrac != NULL);
+	TMC_Write(instPtr, CNTSTEP_OPT, *tmFrac);
+}

datalink814_ge/src/time_ctrl/time_ctrl.h

@@ -0,0 +1,71 @@
+/*****************************************************************************/
+/**
+ * Description: A simplified version of timesync for datalink 814 (Dijian)
+ * 
+ * Date: 2021-12-04 16:32
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-06 16:32
+ * Revisions: Rev 0.0
+ * History: 
+ * [2022-07-06]: Initial version.
+ * [2021-12-04]: Initial version.
+ * 
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+#ifndef TIME_CTRL_H_
+#define TIME_CTRL_H_
+
+/***************************** Include Files *********************************/
+#include <stdint.h>
+/************************** Constant Definitions *****************************/
+#define COUNTE_FRAC_MAX	500000  // how many 10ns in a 5ms
+/***************** Macros (Inline Functions) Definitions *********************/
+/**************************** Type Definitions *******************************/
+typedef enum {
+	TM_ADJ_NONE = 0,
+	TM_ADJ_ADD = 1,
+	TM_ADJ_SET = 2
+} TIMECTRL_ADJ_TYPE;
+
+typedef uint32_t TIME_FRAC;
+typedef uint32_t TIME_INT;
+
+typedef struct {
+	/* 5ms each LSB */
+	TIME_INT int_part;
+	/* 10ns each LSB */
+	TIME_FRAC frac_part;
+} TIME_WORD;
+
+typedef struct {
+	uintptr_t baseAddr;
+	uint32_t reset;    //time for reset (unit: us)
+} TIMECTRL_CONFIG;
+
+typedef struct {
+	TIMECTRL_CONFIG config;
+	uint32_t modelVer;
+} TIMECTRL_INST;
+
+/************************** Function Prototypes ******************************/
+int32_t TimeCtrl_Init(TIMECTRL_INST **instPtr, TIMECTRL_CONFIG *config);
+uint32_t TimeCtrl_GetVersion(TIMECTRL_INST *instPtr);
+void TimeCtrl_Destroy(TIMECTRL_INST *instPtr);
+void TimeCtrl_Reset(TIMECTRL_INST *instPtr);
+void TimeCtrl_ResetLow(TIMECTRL_INST *instPtr);
+void TimeCtrl_ResetHigh(TIMECTRL_INST *instPtr);
+
+TIME_INT TimeCtrl_GetIntCnt(TIMECTRL_INST *instPtr);
+TIME_FRAC TimeCtrl_GetFracCnt(TIMECTRL_INST *instPtr);
+
+void TimeCtrl_GetCurrentTime(TIMECTRL_INST *instPtr, TIME_WORD* tmWord);
+void TimeCtrl_GetCurrentStep(TIMECTRL_INST *instPtr, TIME_FRAC* tmFrac);
+
+void TimeCtrl_SetOptimizeStep(TIMECTRL_INST *instPtr, TIME_FRAC* tmFrac);
+void TimeCtrl_TimeAdjust(TIMECTRL_INST *instPtr, const TIME_WORD* tmWord, TIMECTRL_ADJ_TYPE type);
+
+
+#endif /* TIME_SYNC_H_ */

datalink814_ge/src/util/crc.c

@@ -0,0 +1,417 @@
+/*****************************************************************************/
+/**
+ * Description: CRC implementation file
+ * 
+ * Author: Hao Fan
+ * Date: 2021-11-16 00:50
+ * LastEditors: Hao Fan
+ * LastEditTime: 2022-07-17 20:53
+ * Revisions: Rev 0.0
+ * History: 
+ * [2022-07-17]: Add CRC16_0x8005 CRC8_0x31.
+ * [2022-01-06]: Initial verion (Basic CRC-16).
+ * 
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+#include "util.h"
+#include "../error.h"
+
+#ifdef __CRC_LSB
+// CRC-16-CCITT   G(X)=X16+X12+X5+1
+// Reversed
+static const uint16_t crc16_1021_lsb_lut[256] = {
+    0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF, 
+    0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7, 
+    0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E, 
+    0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876, 
+    0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD, 
+    0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5, 
+    0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C, 
+    0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974, 
+    0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB, 
+    0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3, 
+    0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A, 
+    0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72, 
+    0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9, 
+    0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1, 
+    0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738, 
+    0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70, 
+    0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7, 
+    0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF, 
+    0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036, 
+    0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E, 
+    0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5, 
+    0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD, 
+    0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134, 
+    0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C, 
+    0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3, 
+    0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB, 
+    0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232, 
+    0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A, 
+    0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1, 
+    0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9, 
+    0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330, 
+    0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
+};
+
+// CRC-16-MAXIM   G(X)=X16+X15+X2+1
+const uint16_t crc16_8005_lsb_lut[256] = {
+    0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
+    0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
+    0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
+    0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
+    0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
+    0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
+    0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
+    0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
+    0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+    0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
+    0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
+    0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
+    0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
+    0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
+    0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
+    0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
+    0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
+    0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+    0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
+    0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
+    0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
+    0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
+    0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
+    0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
+    0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
+    0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
+    0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+    0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
+    0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
+    0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
+    0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
+    0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
+};
+
+// CRC-8-MAXIM   G(X)=X8+X5+X4+1
+const uint8_t crc8_31_lsb_lut[256] = {
+    0x00, 0x5E, 0xBC, 0xE2, 0x61, 0x3F, 0xDD, 0x83,
+    0xC2, 0x9C, 0x7E, 0x20, 0xA3, 0xFD, 0x1F, 0x41,
+    0x9D, 0xC3, 0x21, 0x7F, 0xFC, 0xA2, 0x40, 0x1E,
+    0x5F, 0x01, 0xE3, 0xBD, 0x3E, 0x60, 0x82, 0xDC,
+    0x23, 0x7D, 0x9F, 0xC1, 0x42, 0x1C, 0xFE, 0xA0,
+    0xE1, 0xBF, 0x5D, 0x03, 0x80, 0xDE, 0x3C, 0x62,
+    0xBE, 0xE0, 0x02, 0x5C, 0xDF, 0x81, 0x63, 0x3D,
+    0x7C, 0x22, 0xC0, 0x9E, 0x1D, 0x43, 0xA1, 0xFF,
+    0x46, 0x18, 0xFA, 0xA4, 0x27, 0x79, 0x9B, 0xC5,
+    0x84, 0xDA, 0x38, 0x66, 0xE5, 0xBB, 0x59, 0x07,
+    0xDB, 0x85, 0x67, 0x39, 0xBA, 0xE4, 0x06, 0x58,
+    0x19, 0x47, 0xA5, 0xFB, 0x78, 0x26, 0xC4, 0x9A,
+    0x65, 0x3B, 0xD9, 0x87, 0x04, 0x5A, 0xB8, 0xE6,
+    0xA7, 0xF9, 0x1B, 0x45, 0xC6, 0x98, 0x7A, 0x24,
+    0xF8, 0xA6, 0x44, 0x1A, 0x99, 0xC7, 0x25, 0x7B,
+    0x3A, 0x64, 0x86, 0xD8, 0x5B, 0x05, 0xE7, 0xB9,
+    0x8C, 0xD2, 0x30, 0x6E, 0xED, 0xB3, 0x51, 0x0F,
+    0x4E, 0x10, 0xF2, 0xAC, 0x2F, 0x71, 0x93, 0xCD,
+    0x11, 0x4F, 0xAD, 0xF3, 0x70, 0x2E, 0xCC, 0x92,
+    0xD3, 0x8D, 0x6F, 0x31, 0xB2, 0xEC, 0x0E, 0x50,
+    0xAF, 0xF1, 0x13, 0x4D, 0xCE, 0x90, 0x72, 0x2C,
+    0x6D, 0x33, 0xD1, 0x8F, 0x0C, 0x52, 0xB0, 0xEE,
+    0x32, 0x6C, 0x8E, 0xD0, 0x53, 0x0D, 0xEF, 0xB1,
+    0xF0, 0xAE, 0x4C, 0x12, 0x91, 0xCF, 0x2D, 0x73,
+    0xCA, 0x94, 0x76, 0x28, 0xAB, 0xF5, 0x17, 0x49,
+    0x08, 0x56, 0xB4, 0xEA, 0x69, 0x37, 0xD5, 0x8B,
+    0x57, 0x09, 0xEB, 0xB5, 0x36, 0x68, 0x8A, 0xD4,
+    0x95, 0xCB, 0x29, 0x77, 0xF4, 0xAA, 0x48, 0x16,
+    0xE9, 0xB7, 0x55, 0x0B, 0x88, 0xD6, 0x34, 0x6A,
+    0x2B, 0x75, 0x97, 0xC9, 0x4A, 0x14, 0xF6, 0xA8,
+    0x74, 0x2A, 0xC8, 0x96, 0x15, 0x4B, 0xA9, 0xF7,
+    0xB6, 0xE8, 0x0A, 0x54, 0xD7, 0x89, 0x6B, 0x35
+};
+#else
+// CRC-16-CCITT   G(X)=X16+X12+X5+1
+static const uint16_t crc16_1021_msb_lut[256] = { 
+    0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, 
+    0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF, 
+    0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6, 
+    0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE, 
+    0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485, 
+    0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D, 
+    0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4, 
+    0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC, 
+    0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823, 
+    0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B, 
+    0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12, 
+    0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A, 
+    0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41, 
+    0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49, 
+    0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70, 
+    0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78, 
+    0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F, 
+    0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067, 
+    0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E, 
+    0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256, 
+    0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D, 
+    0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, 
+    0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C, 
+    0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634, 
+    0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB, 
+    0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3, 
+    0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A, 
+    0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92, 
+    0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9, 
+    0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1, 
+    0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8, 
+    0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
+};
+
+// CRC-16-MAXIM   G(X)=X16+X15+X2+1
+const uint16_t crc16_8005_msb_lut[256] = {
+    0x0000, 0x8005, 0x800F, 0x000A, 0x801B, 0x001E, 0x0014, 0x8011,
+    0x8033, 0x0036, 0x003C, 0x8039, 0x0028, 0x802D, 0x8027, 0x0022,
+    0x8063, 0x0066, 0x006C, 0x8069, 0x0078, 0x807D, 0x8077, 0x0072,
+    0x0050, 0x8055, 0x805F, 0x005A, 0x804B, 0x004E, 0x0044, 0x8041,
+    0x80C3, 0x00C6, 0x00CC, 0x80C9, 0x00D8, 0x80DD, 0x80D7, 0x00D2,
+    0x00F0, 0x80F5, 0x80FF, 0x00FA, 0x80EB, 0x00EE, 0x00E4, 0x80E1,
+    0x00A0, 0x80A5, 0x80AF, 0x00AA, 0x80BB, 0x00BE, 0x00B4, 0x80B1,
+    0x8093, 0x0096, 0x009C, 0x8099, 0x0088, 0x808D, 0x8087, 0x0082,
+    0x8183, 0x0186, 0x018C, 0x8189, 0x0198, 0x819D, 0x8197, 0x0192,
+    0x01B0, 0x81B5, 0x81BF, 0x01BA, 0x81AB, 0x01AE, 0x01A4, 0x81A1,
+    0x01E0, 0x81E5, 0x81EF, 0x01EA, 0x81FB, 0x01FE, 0x01F4, 0x81F1,
+    0x81D3, 0x01D6, 0x01DC, 0x81D9, 0x01C8, 0x81CD, 0x81C7, 0x01C2,
+    0x0140, 0x8145, 0x814F, 0x014A, 0x815B, 0x015E, 0x0154, 0x8151,
+    0x8173, 0x0176, 0x017C, 0x8179, 0x0168, 0x816D, 0x8167, 0x0162,
+    0x8123, 0x0126, 0x012C, 0x8129, 0x0138, 0x813D, 0x8137, 0x0132,
+    0x0110, 0x8115, 0x811F, 0x011A, 0x810B, 0x010E, 0x0104, 0x8101,
+    0x8303, 0x0306, 0x030C, 0x8309, 0x0318, 0x831D, 0x8317, 0x0312,
+    0x0330, 0x8335, 0x833F, 0x033A, 0x832B, 0x032E, 0x0324, 0x8321,
+    0x0360, 0x8365, 0x836F, 0x036A, 0x837B, 0x037E, 0x0374, 0x8371,
+    0x8353, 0x0356, 0x035C, 0x8359, 0x0348, 0x834D, 0x8347, 0x0342,
+    0x03C0, 0x83C5, 0x83CF, 0x03CA, 0x83DB, 0x03DE, 0x03D4, 0x83D1,
+    0x83F3, 0x03F6, 0x03FC, 0x83F9, 0x03E8, 0x83ED, 0x83E7, 0x03E2,
+    0x83A3, 0x03A6, 0x03AC, 0x83A9, 0x03B8, 0x83BD, 0x83B7, 0x03B2,
+    0x0390, 0x8395, 0x839F, 0x039A, 0x838B, 0x038E, 0x0384, 0x8381,
+    0x0280, 0x8285, 0x828F, 0x028A, 0x829B, 0x029E, 0x0294, 0x8291,
+    0x82B3, 0x02B6, 0x02BC, 0x82B9, 0x02A8, 0x82AD, 0x82A7, 0x02A2,
+    0x82E3, 0x02E6, 0x02EC, 0x82E9, 0x02F8, 0x82FD, 0x82F7, 0x02F2,
+    0x02D0, 0x82D5, 0x82DF, 0x02DA, 0x82CB, 0x02CE, 0x02C4, 0x82C1,
+    0x8243, 0x0246, 0x024C, 0x8249, 0x0258, 0x825D, 0x8257, 0x0252,
+    0x0270, 0x8275, 0x827F, 0x027A, 0x826B, 0x026E, 0x0264, 0x8261,
+    0x0220, 0x8225, 0x822F, 0x022A, 0x823B, 0x023E, 0x0234, 0x8231,
+    0x8213, 0x0216, 0x021C, 0x8219, 0x0208, 0x820D, 0x8207, 0x0202
+};
+
+// CRC-8-MAXIM   G(X)=X8+X5+X4+1
+const uint8_t crc8_31_msb_lut[256] = {
+    0x00, 0x31, 0x62, 0x53, 0xC4, 0xF5, 0xA6, 0x97,
+    0xB9, 0x88, 0xDB, 0xEA, 0x7D, 0x4C, 0x1F, 0x2E,
+    0x43, 0x72, 0x21, 0x10, 0x87, 0xB6, 0xE5, 0xD4,
+    0xFA, 0xCB, 0x98, 0xA9, 0x3E, 0x0F, 0x5C, 0x6D,
+    0x86, 0xB7, 0xE4, 0xD5, 0x42, 0x73, 0x20, 0x11,
+    0x3F, 0x0E, 0x5D, 0x6C, 0xFB, 0xCA, 0x99, 0xA8,
+    0xC5, 0xF4, 0xA7, 0x96, 0x01, 0x30, 0x63, 0x52,
+    0x7C, 0x4D, 0x1E, 0x2F, 0xB8, 0x89, 0xDA, 0xEB,
+    0x3D, 0x0C, 0x5F, 0x6E, 0xF9, 0xC8, 0x9B, 0xAA,
+    0x84, 0xB5, 0xE6, 0xD7, 0x40, 0x71, 0x22, 0x13,
+    0x7E, 0x4F, 0x1C, 0x2D, 0xBA, 0x8B, 0xD8, 0xE9,
+    0xC7, 0xF6, 0xA5, 0x94, 0x03, 0x32, 0x61, 0x50,
+    0xBB, 0x8A, 0xD9, 0xE8, 0x7F, 0x4E, 0x1D, 0x2C,
+    0x02, 0x33, 0x60, 0x51, 0xC6, 0xF7, 0xA4, 0x95,
+    0xF8, 0xC9, 0x9A, 0xAB, 0x3C, 0x0D, 0x5E, 0x6F,
+    0x41, 0x70, 0x23, 0x12, 0x85, 0xB4, 0xE7, 0xD6,
+    0x7A, 0x4B, 0x18, 0x29, 0xBE, 0x8F, 0xDC, 0xED,
+    0xC3, 0xF2, 0xA1, 0x90, 0x07, 0x36, 0x65, 0x54,
+    0x39, 0x08, 0x5B, 0x6A, 0xFD, 0xCC, 0x9F, 0xAE,
+    0x80, 0xB1, 0xE2, 0xD3, 0x44, 0x75, 0x26, 0x17,
+    0xFC, 0xCD, 0x9E, 0xAF, 0x38, 0x09, 0x5A, 0x6B,
+    0x45, 0x74, 0x27, 0x16, 0x81, 0xB0, 0xE3, 0xD2,
+    0xBF, 0x8E, 0xDD, 0xEC, 0x7B, 0x4A, 0x19, 0x28,
+    0x06, 0x37, 0x64, 0x55, 0xC2, 0xF3, 0xA0, 0x91,
+    0x47, 0x76, 0x25, 0x14, 0x83, 0xB2, 0xE1, 0xD0,
+    0xFE, 0xCF, 0x9C, 0xAD, 0x3A, 0x0B, 0x58, 0x69,
+    0x04, 0x35, 0x66, 0x57, 0xC0, 0xF1, 0xA2, 0x93,
+    0xBD, 0x8C, 0xDF, 0xEE, 0x79, 0x48, 0x1B, 0x2A,
+    0xC1, 0xF0, 0xA3, 0x92, 0x05, 0x34, 0x67, 0x56,
+    0x78, 0x49, 0x1A, 0x2B, 0xBC, 0x8D, 0xDE, 0xEF,
+    0x82, 0xB3, 0xE0, 0xD1, 0x46, 0x77, 0x24, 0x15,
+    0x3B, 0x0A, 0x59, 0x68, 0xFF, 0xCE, 0x9D, 0xAC
+};
+#endif
+
+/* CRC lookup table algorithm  
+#define CRC_BIT_NUM 8u/16u/32u/64u
+#define BITS_IN_BYTE 8u
+uint8_t dataBuff[ARRAY_SIZE] = { 0x32, 0x33, …};
+uint8_t/uint16_t/uint32_t crc_val = 0x0;
+// LSB
+for(int i = 0; i < sizeof(dataBuff); i++)
+{
+    crc_val = (crc_val >> BITS_IN_BYTE) ^ crc_lsb_lut[(uint8)(crc_val^dataBuff[i])];
+}
+// MSB
+for(int i = 0; i < sizeof(dataBuff); i++)
+{
+    crc_val = (crc_val << BITS_IN_BYTE) ^ crc_msb_lut[(uint8)((crc_val>>8)^dataBuff[i])];
+}
+*/
+
+/*****************************************************************************/
+/**
+ * @brief	CRC8 generator
+ * 
+ * @param   buffPtr	data buffer pointer.
+ * @param   dataLen	data length
+ * @param	poly	polynomials of crc
+ * @param	crcVal	a pointer to store generated crc value
+ * 
+ * @return  SUCCESS
+ * 			FAILURE
+ * 
+ ******************************************************************************/
+int crc8_gen(uint8_t* buffPtr, uint32_t dataLen, uint16_t poly, uint8_t* crcVal) {
+    uint8_t crc = CRC8_INIT;
+    const uint8_t* crc_lut = NULL;
+
+    switch(poly){
+#ifdef __CRC_LSB
+        case 0x31: 
+            crc_lut = crc8_31_lsb_lut;
+            break;
+        default:
+            return FAILURE;
+#else
+        case 0x31: 
+            crc_lut = crc8_31_msb_lut;
+            break;
+        default:
+            return FAILURE;
+#endif
+    }
+    
+    for(int i = 0; i < dataLen; i++){
+        crc = crc_lut[(uint8_t)(crc^buffPtr[i])];
+    }
+    *crcVal = crc;
+    return SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief	CRC16 generator
+ * 
+ * @param   buffPtr	data buffer pointer.
+ * @param   dataLen	data length
+ * @param	poly	polynomials of crc
+ * @param	crcVal	a pointer to store generated crc value
+ * 
+ * @return  SUCCESS
+ * 			FAILURE
+ * 
+ ******************************************************************************/
+int crc16_gen(uint8_t* buffPtr, uint32_t dataLen, uint16_t poly, uint16_t* crcVal) {
+    uint16_t crc = CRC16_INIT;
+    const uint16_t* crc_lut = NULL;
+    switch(poly){
+#ifdef __CRC_LSB
+        case 0x8005: 
+            crc_lut = crc16_8005_lsb_lut;
+            break;
+        case 0x1021:
+            crc_lut = crc16_1021_lsb_lut;
+            break;
+        default:
+            return FAILURE;
+#else
+        case 0x8005: 
+            crc_lut = crc16_8005_msb_lut;
+            break;
+        case 0x1021:
+            crc_lut = crc16_1021_msb_lut;
+            break;
+        default:
+            return FAILURE;
+#endif
+    }
+    for(int i = 0; i < dataLen; i++){
+#ifdef __CRC_LSB
+    	crc = (crc>>8) ^ crc_lut[(uint8_t)(crc^buffPtr[i])];
+#else
+        crc = (crc<<8) ^ crc_lut[(uint8_t)((crc >> 8)^buffPtr[i])];
+#endif
+    }
+    *crcVal = crc;
+    return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief	CRC8 compare cheker
+ * 
+ * @param   buffPtr	data buffer pointer.
+ * @param   dataLen	data length
+ * @param	crcOffset	byte offset of crc stored position.
+ * @param	poly	polynomials of crc
+ * 
+ * @return	true
+ * 			false
+ * 
+******************************************************************************/
+bool crc8_check(uint8_t* buffPtr, uint32_t dataLen, uint32_t crcOffset, uint16_t poly) {
+    int Status = SUCCESS;
+    uint8_t crc_comp;
+    uint8_t crc;
+    if (dataLen == 0) {
+		return false;
+	}
+    crc_comp = (uint8_t)(*(buffPtr + crcOffset));
+    Status = crc8_gen(buffPtr, dataLen, poly, &crc);
+    if(Status == SUCCESS){
+        if (crc == crc_comp) {
+            return true;
+        }
+        else {
+            return false;
+        }
+    }
+    else{
+        return false;
+    }
+}
+
+
+/*****************************************************************************/
+/**
+ * @brief	CRC16 compare cheker
+ * 
+ * @param   buffPtr	data buffer pointer.
+ * @param   dataLen	data length
+ * @param	crcOffset	byte offset of crc stored position.
+ * @param	poly	polynomials of crc
+ * 
+ * @return	true
+ * 			fasle
+ * 
+******************************************************************************/
+bool crc16_check(uint8_t* buffPtr, uint32_t dataLen, uint32_t crcOffset, uint16_t poly) {
+    int Status = SUCCESS;
+    uint16_t crc_comp;
+    uint16_t crc;
+    if (dataLen == 0) {
+		return false;
+	}
+    crc_comp = (uint16_t)(*(buffPtr + crcOffset));
+    crc_comp |= (uint16_t)((*(buffPtr + crcOffset + 1)) << 8);
+    Status = crc16_gen(buffPtr, dataLen, poly, &crc);
+    if(Status == SUCCESS){
+        if (crc == crc_comp) {
+            return true;
+        }
+        else {
+            return false;
+        }
+    }
+    else{
+        return false;
+    }
+}

datalink814_ge/src/util/tables.txt

@@ -0,0 +1,231 @@
+Generating CRC table for crc8-31-lsb
+
+0x00, 0x5E, 0xBC, 0xE2, 0x61, 0x3F, 0xDD, 0x83,
+0xC2, 0x9C, 0x7E, 0x20, 0xA3, 0xFD, 0x1F, 0x41,
+0x9D, 0xC3, 0x21, 0x7F, 0xFC, 0xA2, 0x40, 0x1E,
+0x5F, 0x01, 0xE3, 0xBD, 0x3E, 0x60, 0x82, 0xDC,
+0x23, 0x7D, 0x9F, 0xC1, 0x42, 0x1C, 0xFE, 0xA0,
+0xE1, 0xBF, 0x5D, 0x03, 0x80, 0xDE, 0x3C, 0x62,
+0xBE, 0xE0, 0x02, 0x5C, 0xDF, 0x81, 0x63, 0x3D,
+0x7C, 0x22, 0xC0, 0x9E, 0x1D, 0x43, 0xA1, 0xFF,
+0x46, 0x18, 0xFA, 0xA4, 0x27, 0x79, 0x9B, 0xC5,
+0x84, 0xDA, 0x38, 0x66, 0xE5, 0xBB, 0x59, 0x07,
+0xDB, 0x85, 0x67, 0x39, 0xBA, 0xE4, 0x06, 0x58,
+0x19, 0x47, 0xA5, 0xFB, 0x78, 0x26, 0xC4, 0x9A,
+0x65, 0x3B, 0xD9, 0x87, 0x04, 0x5A, 0xB8, 0xE6,
+0xA7, 0xF9, 0x1B, 0x45, 0xC6, 0x98, 0x7A, 0x24,
+0xF8, 0xA6, 0x44, 0x1A, 0x99, 0xC7, 0x25, 0x7B,
+0x3A, 0x64, 0x86, 0xD8, 0x5B, 0x05, 0xE7, 0xB9,
+0x8C, 0xD2, 0x30, 0x6E, 0xED, 0xB3, 0x51, 0x0F,
+0x4E, 0x10, 0xF2, 0xAC, 0x2F, 0x71, 0x93, 0xCD,
+0x11, 0x4F, 0xAD, 0xF3, 0x70, 0x2E, 0xCC, 0x92,
+0xD3, 0x8D, 0x6F, 0x31, 0xB2, 0xEC, 0x0E, 0x50,
+0xAF, 0xF1, 0x13, 0x4D, 0xCE, 0x90, 0x72, 0x2C,
+0x6D, 0x33, 0xD1, 0x8F, 0x0C, 0x52, 0xB0, 0xEE,
+0x32, 0x6C, 0x8E, 0xD0, 0x53, 0x0D, 0xEF, 0xB1,
+0xF0, 0xAE, 0x4C, 0x12, 0x91, 0xCF, 0x2D, 0x73,
+0xCA, 0x94, 0x76, 0x28, 0xAB, 0xF5, 0x17, 0x49,
+0x08, 0x56, 0xB4, 0xEA, 0x69, 0x37, 0xD5, 0x8B,
+0x57, 0x09, 0xEB, 0xB5, 0x36, 0x68, 0x8A, 0xD4,
+0x95, 0xCB, 0x29, 0x77, 0xF4, 0xAA, 0x48, 0x16,
+0xE9, 0xB7, 0x55, 0x0B, 0x88, 0xD6, 0x34, 0x6A,
+0x2B, 0x75, 0x97, 0xC9, 0x4A, 0x14, 0xF6, 0xA8,
+0x74, 0x2A, 0xC8, 0x96, 0x15, 0x4B, 0xA9, 0xF7,
+0xB6, 0xE8, 0x0A, 0x54, 0xD7, 0x89, 0x6B, 0x35,
+
+
+Generating CRC table for crc8-31-msb
+
+0x00, 0x31, 0x62, 0x53, 0xC4, 0xF5, 0xA6, 0x97,
+0xB9, 0x88, 0xDB, 0xEA, 0x7D, 0x4C, 0x1F, 0x2E,
+0x43, 0x72, 0x21, 0x10, 0x87, 0xB6, 0xE5, 0xD4,
+0xFA, 0xCB, 0x98, 0xA9, 0x3E, 0x0F, 0x5C, 0x6D,
+0x86, 0xB7, 0xE4, 0xD5, 0x42, 0x73, 0x20, 0x11,
+0x3F, 0x0E, 0x5D, 0x6C, 0xFB, 0xCA, 0x99, 0xA8,
+0xC5, 0xF4, 0xA7, 0x96, 0x01, 0x30, 0x63, 0x52,
+0x7C, 0x4D, 0x1E, 0x2F, 0xB8, 0x89, 0xDA, 0xEB,
+0x3D, 0x0C, 0x5F, 0x6E, 0xF9, 0xC8, 0x9B, 0xAA,
+0x84, 0xB5, 0xE6, 0xD7, 0x40, 0x71, 0x22, 0x13,
+0x7E, 0x4F, 0x1C, 0x2D, 0xBA, 0x8B, 0xD8, 0xE9,
+0xC7, 0xF6, 0xA5, 0x94, 0x03, 0x32, 0x61, 0x50,
+0xBB, 0x8A, 0xD9, 0xE8, 0x7F, 0x4E, 0x1D, 0x2C,
+0x02, 0x33, 0x60, 0x51, 0xC6, 0xF7, 0xA4, 0x95,
+0xF8, 0xC9, 0x9A, 0xAB, 0x3C, 0x0D, 0x5E, 0x6F,
+0x41, 0x70, 0x23, 0x12, 0x85, 0xB4, 0xE7, 0xD6,
+0x7A, 0x4B, 0x18, 0x29, 0xBE, 0x8F, 0xDC, 0xED,
+0xC3, 0xF2, 0xA1, 0x90, 0x07, 0x36, 0x65, 0x54,
+0x39, 0x08, 0x5B, 0x6A, 0xFD, 0xCC, 0x9F, 0xAE,
+0x80, 0xB1, 0xE2, 0xD3, 0x44, 0x75, 0x26, 0x17,
+0xFC, 0xCD, 0x9E, 0xAF, 0x38, 0x09, 0x5A, 0x6B,
+0x45, 0x74, 0x27, 0x16, 0x81, 0xB0, 0xE3, 0xD2,
+0xBF, 0x8E, 0xDD, 0xEC, 0x7B, 0x4A, 0x19, 0x28,
+0x06, 0x37, 0x64, 0x55, 0xC2, 0xF3, 0xA0, 0x91,
+0x47, 0x76, 0x25, 0x14, 0x83, 0xB2, 0xE1, 0xD0,
+0xFE, 0xCF, 0x9C, 0xAD, 0x3A, 0x0B, 0x58, 0x69,
+0x04, 0x35, 0x66, 0x57, 0xC0, 0xF1, 0xA2, 0x93,
+0xBD, 0x8C, 0xDF, 0xEE, 0x79, 0x48, 0x1B, 0x2A,
+0xC1, 0xF0, 0xA3, 0x92, 0x05, 0x34, 0x67, 0x56,
+0x78, 0x49, 0x1A, 0x2B, 0xBC, 0x8D, 0xDE, 0xEF,
+0x82, 0xB3, 0xE0, 0xD1, 0x46, 0x77, 0x24, 0x15,
+0x3B, 0x0A, 0x59, 0x68, 0xFF, 0xCE, 0x9D, 0xAC,
+
+
+Generating CRC table for crc16-8005-lsb
+
+0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
+0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
+0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
+0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
+0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
+0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
+0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
+0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
+0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
+0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
+0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
+0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
+0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
+0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
+0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
+0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
+0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
+0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
+0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
+0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
+0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
+0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
+0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
+0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
+0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
+0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
+0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
+0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
+0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040,
+
+
+Generating CRC table for crc16-8005-msb
+
+0x0000, 0x8005, 0x800F, 0x000A, 0x801B, 0x001E, 0x0014, 0x8011,
+0x8033, 0x0036, 0x003C, 0x8039, 0x0028, 0x802D, 0x8027, 0x0022,
+0x8063, 0x0066, 0x006C, 0x8069, 0x0078, 0x807D, 0x8077, 0x0072,
+0x0050, 0x8055, 0x805F, 0x005A, 0x804B, 0x004E, 0x0044, 0x8041,
+0x80C3, 0x00C6, 0x00CC, 0x80C9, 0x00D8, 0x80DD, 0x80D7, 0x00D2,
+0x00F0, 0x80F5, 0x80FF, 0x00FA, 0x80EB, 0x00EE, 0x00E4, 0x80E1,
+0x00A0, 0x80A5, 0x80AF, 0x00AA, 0x80BB, 0x00BE, 0x00B4, 0x80B1,
+0x8093, 0x0096, 0x009C, 0x8099, 0x0088, 0x808D, 0x8087, 0x0082,
+0x8183, 0x0186, 0x018C, 0x8189, 0x0198, 0x819D, 0x8197, 0x0192,
+0x01B0, 0x81B5, 0x81BF, 0x01BA, 0x81AB, 0x01AE, 0x01A4, 0x81A1,
+0x01E0, 0x81E5, 0x81EF, 0x01EA, 0x81FB, 0x01FE, 0x01F4, 0x81F1,
+0x81D3, 0x01D6, 0x01DC, 0x81D9, 0x01C8, 0x81CD, 0x81C7, 0x01C2,
+0x0140, 0x8145, 0x814F, 0x014A, 0x815B, 0x015E, 0x0154, 0x8151,
+0x8173, 0x0176, 0x017C, 0x8179, 0x0168, 0x816D, 0x8167, 0x0162,
+0x8123, 0x0126, 0x012C, 0x8129, 0x0138, 0x813D, 0x8137, 0x0132,
+0x0110, 0x8115, 0x811F, 0x011A, 0x810B, 0x010E, 0x0104, 0x8101,
+0x8303, 0x0306, 0x030C, 0x8309, 0x0318, 0x831D, 0x8317, 0x0312,
+0x0330, 0x8335, 0x833F, 0x033A, 0x832B, 0x032E, 0x0324, 0x8321,
+0x0360, 0x8365, 0x836F, 0x036A, 0x837B, 0x037E, 0x0374, 0x8371,
+0x8353, 0x0356, 0x035C, 0x8359, 0x0348, 0x834D, 0x8347, 0x0342,
+0x03C0, 0x83C5, 0x83CF, 0x03CA, 0x83DB, 0x03DE, 0x03D4, 0x83D1,
+0x83F3, 0x03F6, 0x03FC, 0x83F9, 0x03E8, 0x83ED, 0x83E7, 0x03E2,
+0x83A3, 0x03A6, 0x03AC, 0x83A9, 0x03B8, 0x83BD, 0x83B7, 0x03B2,
+0x0390, 0x8395, 0x839F, 0x039A, 0x838B, 0x038E, 0x0384, 0x8381,
+0x0280, 0x8285, 0x828F, 0x028A, 0x829B, 0x029E, 0x0294, 0x8291,
+0x82B3, 0x02B6, 0x02BC, 0x82B9, 0x02A8, 0x82AD, 0x82A7, 0x02A2,
+0x82E3, 0x02E6, 0x02EC, 0x82E9, 0x02F8, 0x82FD, 0x82F7, 0x02F2,
+0x02D0, 0x82D5, 0x82DF, 0x02DA, 0x82CB, 0x02CE, 0x02C4, 0x82C1,
+0x8243, 0x0246, 0x024C, 0x8249, 0x0258, 0x825D, 0x8257, 0x0252,
+0x0270, 0x8275, 0x827F, 0x027A, 0x826B, 0x026E, 0x0264, 0x8261,
+0x0220, 0x8225, 0x822F, 0x022A, 0x823B, 0x023E, 0x0234, 0x8231,
+0x8213, 0x0216, 0x021C, 0x8219, 0x0208, 0x820D, 0x8207, 0x0202,
+
+
+Generating CRC table for crc16-1021-lsb
+
+0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
+0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
+0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
+0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
+0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
+0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
+0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
+0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
+0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
+0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
+0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
+0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
+0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
+0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
+0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
+0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
+0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
+0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
+0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
+0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
+0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
+0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
+0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
+0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
+0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
+0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
+0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
+0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
+0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
+0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
+0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
+0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78,
+
+
+Generating CRC table for crc16-1021-msb
+
+0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
+0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
+0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
+0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
+0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
+0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
+0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
+0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
+0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
+0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
+0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
+0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
+0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
+0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
+0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
+0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
+0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
+0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
+0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
+0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
+0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
+0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
+0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
+0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
+0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
+0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
+0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
+0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
+0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
+0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
+0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0,
+
+
+
+#define CRC_BIT_NUM 8u/16u/32u/64u
+#define BITS_IN_BYTE 8u
+uint8_t dataBuff[ARRAY_SIZE] = { 0x32, 0x33, ...;
+uint8_t/uint16_t/uint32_t crc_val = 0x0;
+// LSB
+for(int i = 0; i < sizeof(dataBuff); i++)
+{
+    crc_val = (crc_val >> BITS_IN_BYTE) ^ crc_lsb_lut[(uint8)(crc_val^dataBuff[i])];
+}
+// MSB
+for(int i = 0; i < sizeof(dataBuff); i++)
+{
+    crc_val = (crc_val << BITS_IN_BYTE) ^ crc_msb_lut[(uint8)((crc_val>>8)^dataBuff[i])];
+}

datalink814_ge/src/util/util.c

@@ -0,0 +1,351 @@
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <string.h>
+#include <stdlib.h>
+// #include <arm_acle.h>
+#include "util.h"
+#include "../error.h"
+
+/******************************************************************************/
+/************************** Functions Implementation **************************/
+/******************************************************************************/
+#ifdef __BITSWAP_TABLE
+static uint8_t byte_flipLR[256] = { 
+	0x00, 0x80, 0x40, 0xC0, 0x20, 0xA0, 0x60, 0xE0,
+	0x10, 0x90, 0x50, 0xD0, 0x30, 0xB0, 0x70, 0xF0,
+	0x08, 0x88, 0x48, 0xC8, 0x28, 0xA8, 0x68, 0xE8,
+	0x18, 0x98, 0x58, 0xD8, 0x38, 0xB8, 0x78, 0xF8,
+	0x04, 0x84, 0x44, 0xC4, 0x24, 0xA4, 0x64, 0xE4,
+	0x14, 0x94, 0x54, 0xD4, 0x34, 0xB4, 0x74, 0xF4,
+	0x0C, 0x8C, 0x4C, 0xCC, 0x2C, 0xAC, 0x6C, 0xEC,
+	0x1C, 0x9C, 0x5C, 0xDC, 0x3C, 0xBC, 0x7C, 0xFC,
+	0x02, 0x82, 0x42, 0xC2, 0x22, 0xA2, 0x62, 0xE2,
+	0x12, 0x92, 0x52, 0xD2, 0x32, 0xB2, 0x72, 0xF2,
+	0x0A, 0x8A, 0x4A, 0xCA, 0x2A, 0xAA, 0x6A, 0xEA,
+	0x1A, 0x9A, 0x5A, 0xDA, 0x3A, 0xBA, 0x7A, 0xFA,
+	0x06, 0x86, 0x46, 0xC6, 0x26, 0xA6, 0x66, 0xE6,
+	0x16, 0x96, 0x56, 0xD6, 0x36, 0xB6, 0x76, 0xF6,
+	0x0E, 0x8E, 0x4E, 0xCE, 0x2E, 0xAE, 0x6E, 0xEE,
+	0x1E, 0x9E, 0x5E, 0xDE, 0x3E, 0xBE, 0x7E, 0xFE,
+	0x01, 0x81, 0x41, 0xC1, 0x21, 0xA1, 0x61, 0xE1,
+	0x11, 0x91, 0x51, 0xD1, 0x31, 0xB1, 0x71, 0xF1,
+	0x09, 0x89, 0x49, 0xC9, 0x29, 0xA9, 0x69, 0xE9,
+	0x19, 0x99, 0x59, 0xD9, 0x39, 0xB9, 0x79, 0xF9,
+	0x05, 0x85, 0x45, 0xC5, 0x25, 0xA5, 0x65, 0xE5,
+	0x15, 0x95, 0x55, 0xD5, 0x35, 0xB5, 0x75, 0xF5,
+	0x0D, 0x8D, 0x4D, 0xCD, 0x2D, 0xAD, 0x6D, 0xED,
+	0x1D, 0x9D, 0x5D, 0xDD, 0x3D, 0xBD, 0x7D, 0xFD,
+	0x03, 0x83, 0x43, 0xC3, 0x23, 0xA3, 0x63, 0xE3,
+	0x13, 0x93, 0x53, 0xD3, 0x33, 0xB3, 0x73, 0xF3,
+	0x0B, 0x8B, 0x4B, 0xCB, 0x2B, 0xAB, 0x6B, 0xEB,
+	0x1B, 0x9B, 0x5B, 0xDB, 0x3B, 0xBB, 0x7B, 0xFB,
+	0x07, 0x87, 0x47, 0xC7, 0x27, 0xA7, 0x67, 0xE7,
+	0x17, 0x97, 0x57, 0xD7, 0x37, 0xB7, 0x77, 0xF7,
+	0x0F, 0x8F, 0x4F, 0xCF, 0x2F, 0xAF, 0x6F, 0xEF,
+	0x1F, 0x9F, 0x5F, 0xDF, 0x3F, 0xBF, 0x7F, 0xFF 
+};
+#endif
+
+inline void IO_Out32(uintptr_t addr, uint32_t value){
+	volatile uint32_t *localAddr = (volatile uint32_t *)addr;
+	*localAddr = value;
+}
+
+inline uint32_t IO_In32(uintptr_t addr){
+	return *(volatile uint32_t*) addr;
+}
+
+uint8_t byte_bit_swap(uint8_t byte){
+#ifdef __BITSWAP_TABLE
+	return byte_flipLR[byte];
+#else
+	return bit_swap_constant_8(byte);
+#endif
+}
+
+uint32_t word_bit_swap(uint32_t word){
+#ifdef __BITSWAP_TABLE
+	uint32_t rv_word = (byte_flipLR[word & 0xff] << 24) |
+		    (byte_flipLR[(word >> 8) & 0xff] << 16) |
+		    (byte_flipLR[(word >> 16) & 0xff] << 8) |
+		    (byte_flipLR[(word >> 24) & 0xff]);
+	return rv_word;
+#else
+	word = (((word & 0xaaaaaaaa) >> 1) | ((word & 0x55555555) << 1));
+	word = (((word & 0xcccccccc) >> 2) | ((word & 0x33333333) << 2));
+	word = (((word & 0xf0f0f0f0) >> 4) | ((word & 0x0f0f0f0f) << 4));
+	word = (((word & 0xff00ff00) >> 8) | ((word & 0x00ff00ff) << 8));
+	return((word >> 16) | (word << 16));
+#endif
+}
+
+uint32_t count_ones(uint32_t word){
+#ifdef __GNUC__
+	return __builtin_popcount(word);
+#else
+	uint32_t one_count = 0;
+	while (word) {
+		if (word & 0x00000001)
+			one_count ++;
+		word >>= 1;
+	}
+	return one_count;
+#endif
+}
+
+double fix2double(int32_t val, uint8_t frac_bits){
+	return (((double)val)/(BIT(frac_bits)));
+}
+
+/**
+ * Find first set bit in word.
+ */
+uint32_t find_first_set_bit(uint32_t word)
+{
+#ifdef __GNUC__
+	if(word != 0){
+		return __builtin_ctz(word);
+	}
+	else{
+		return 32;
+	}
+#else
+	uint32_t first_set_bit = 0;
+
+	while (word) {
+		if (word & 0x1)
+			return first_set_bit;
+		word >>= 1;
+		first_set_bit ++;
+	}
+
+	return 32;
+#endif
+}
+
+/**
+ * Find last set bit in word.
+ */
+uint32_t find_last_set_bit(uint32_t word)
+{
+#ifdef __GNUC__
+	if(word != 0){
+		return (31-__builtin_clz(word));
+	}
+	else{
+		return 32;
+	}
+#else
+	uint32_t bit = 0;
+	uint32_t last_set_bit = 32;
+
+	while (word) {
+		if (word & 0x1)
+			last_set_bit = bit;
+		word >>= 1;
+		bit ++;
+	}
+
+	return last_set_bit;
+#endif
+}
+
+/**
+ * Locate the closest element in an array.
+ */
+uint32_t find_closest(int32_t val,
+		      const int32_t *array,
+		      uint32_t size)
+{
+	int32_t diff = abs(array[0] - val);
+	uint32_t ret = 0;
+	uint32_t i;
+
+	for (i = 1; i < size; i++) {
+		if (abs(array[i] - val) < diff) {
+			diff = abs(array[i] - val);
+			ret = i;
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * Shift the value and apply the specified mask.
+ */
+uint32_t field_prep(uint32_t mask, uint32_t val)
+{
+	return (val << find_first_set_bit(mask)) & mask;
+}
+
+/**
+ * Get a field specified by a mask from a word.
+ */
+uint32_t field_get(uint32_t mask, uint32_t word)
+{
+	return (word & mask) >> find_first_set_bit(mask);
+}
+
+/**
+ * Log base 2 of the given number.
+ */
+int32_t log_base_2(uint32_t x)
+{
+	return find_last_set_bit(x);
+}
+
+/**
+ * Find greatest common divisor of the given two numbers.
+ */
+uint32_t greatest_common_divisor(uint32_t a,
+				 uint32_t b)
+{
+	uint32_t div;
+	uint32_t common_div = 1;
+
+	if ((a == 0) || (b == 0))
+		return max(a, b);
+
+	for (div = 1; (div <= a) && (div <= b); div++)
+		if (!(a % div) && !(b % div))
+			common_div = div;
+
+	return common_div;
+}
+
+/**
+ * Calculate best rational approximation for a given fraction.
+ */
+void rational_best_approximation(uint32_t given_numerator,
+				 uint32_t given_denominator,
+				 uint32_t max_numerator,
+				 uint32_t max_denominator,
+				 uint32_t *best_numerator,
+				 uint32_t *best_denominator)
+{
+	uint32_t gcd;
+
+	gcd = greatest_common_divisor(given_numerator, given_denominator);
+
+	*best_numerator = given_numerator / gcd;
+	*best_denominator = given_denominator / gcd;
+
+	if ((*best_numerator > max_numerator) ||
+	    (*best_denominator > max_denominator)) {
+		*best_numerator = 0;
+		*best_denominator = 0;
+	}
+}
+
+/**
+ * Calculate the number of set bits.
+ */
+uint32_t hweight8(uint32_t word)
+{
+	uint32_t count = 0;
+
+	while (word) {
+		if (word & 0x1)
+			count++;
+		word >>= 1;
+	}
+
+	return count;
+}
+
+/**
+ * Calculate the quotient and the remainder of an integer division.
+ */
+uint64_t do_div(uint64_t* n,
+		uint64_t base)
+{
+	uint64_t mod = 0;
+
+	mod = *n % base;
+	*n = *n / base;
+
+	return mod;
+}
+
+/**
+ * Unsigned 64bit divide with 64bit divisor and remainder
+ */
+uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder)
+{
+	*remainder = dividend % divisor;
+
+	return dividend / divisor;
+}
+
+/**
+ * Unsigned 64bit divide with 32bit divisor with remainder
+ */
+uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)
+{
+	*remainder = do_div(&dividend, divisor);
+
+	return dividend;
+}
+
+/**
+ * Signed 64bit divide with 32bit divisor with remainder
+ */
+int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
+ * Unsigned 64bit divide with 32bit divisor
+ */
+uint64_t div_u64(uint64_t dividend, uint32_t divisor)
+{
+	uint32_t remainder;
+
+	return div_u64_rem(dividend, divisor, &remainder);
+}
+
+/**
+ * Signed 64bit divide with 32bit divisor
+ */
+int64_t div_s64(int64_t dividend, int32_t divisor)
+{
+	int32_t remainder;
+	return div_s64_rem(dividend, divisor, &remainder);
+}
+
+/**
+ * Converts from string to int32_t
+ * @param *str
+ * @return int32_t
+ */
+int32_t str_to_int32(const char *str)
+{
+	char *end;
+	int32_t value = strtol(str, &end, 0);
+
+	if (end == str)
+		return FAILURE;
+	else
+		return value;
+}
+
+/**
+ * Converts from string to uint32_t
+ * @param *str
+ * @return uint32_t
+ */
+uint32_t srt_to_uint32(const char *str)
+{
+	char *end;
+	uint32_t value = strtoul(str, &end, 0);
+
+	if (end == str)
+		return FAILURE;
+	else
+		return value;
+}
+

datalink814_ge/src/util/util.h

@@ -0,0 +1,192 @@
+/***************************************************************************//**
+ *   @file   util.h
+ *   @brief  Implementation of utility functions.
+ *   @author DBogdan (dragos.bogdan@analog.com)
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef UTIL_H_
+#define UTIL_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+//#define __CRC_LSB
+#define __BITSWAP_TABLE
+#define __CRC_LSB
+#define CRC16_INIT 0x0000
+#define CRC8_INIT 0x00
+
+#define BIT(x)	(1 << (x))
+
+#define ARRAY_SIZE(x) \
+	(sizeof(x) / sizeof((x)[0]))
+
+#define DIV_ROUND_UP(x,y) \
+	(((x) + (y) - 1) / (y))
+#define DIV_ROUND_CLOSEST(x, y) \
+	(((x) + (y) / 2) / (y))
+#define DIV_ROUND_CLOSEST_ULL(x, y) \
+	DIV_ROUND_CLOSEST(x, y)
+
+#define min(x, y) \
+	(((x) < (y)) ? (x) : (y))
+#define min_t(type, x, y) \
+	(type)min((type)(x), (type)(y))
+
+#define max(x, y) \
+	(((x) > (y)) ? (x) : (y))
+#define max_t(type, x, y) \
+	(type)max((type)(x), (type)(y))
+
+#define clamp(val, min_val, max_val) \
+	(max(min((val), (max_val)), (min_val)))
+#define clamp_t(type, val, min_val, max_val) \
+	(type)clamp((type)(val), (type)(min_val), (type)(max_val))
+
+#define swap(x, y) \
+	{typeof(x) _tmp_ = (x); (x) = (y); (y) = _tmp_;}
+
+#define round_up(x,y) \
+		(((x)+(y)-1)/(y))
+
+#define BITS_PER_LONG 32
+
+#define GENMASK(h, l) ({ 					\
+		uint32_t t = (uint32_t)(~0UL);			\
+		t = t << (BITS_PER_LONG - (h - l + 1));		\
+		t = t >> (BITS_PER_LONG - (h + 1));		\
+		t;						\
+})
+
+#define bswap_constant_32(x) \
+	((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >>  8) | \
+	 (((x) & 0x0000ff00) <<  8) | (((x) & 0x000000ff) << 24))
+
+#define bswap_constant_16(x) ((((x) & (uint16_t)0xff00) >> 8) | \
+				 (((x) & (uint16_t)0x00ff) << 8))
+
+#define bit_swap_constant_8(x) \
+	((((x) & 0x80) >> 7) | \
+	 (((x) & 0x40) >> 5) | \
+	 (((x) & 0x20) >> 3) | \
+	 (((x) & 0x10) >> 1) | \
+	 (((x) & 0x08) << 1) | \
+	 (((x) & 0x04) << 3) | \
+	 (((x) & 0x02) << 5) | \
+	 (((x) & 0x01) << 7))
+
+#define U16_MAX		((uint16_t)~0U)
+#define S16_MAX		((int16_t)(U16_MAX>>1))
+
+#define DIV_U64(x, y) (x / y)
+
+#define UNUSED_PARAM(x) ((void)x)
+
+#define shift_right(x, s) ((x) < 0 ? -(-(x) >> (s)) : (x) >> (s))
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+void IO_Out32(uintptr_t addr, uint32_t value);
+uint32_t IO_In32(uintptr_t addr);
+
+/* flip a byte left to right*/
+uint8_t byte_bit_swap(uint8_t byte);
+
+/* flip a 32bit word left to right */
+uint32_t word_bit_swap(uint32_t word);
+
+/* Returns the number of 1-bits in digit. */
+uint32_t count_ones(uint32_t word);
+
+/* convert a fixed number to a double. */
+double fix2double(int32_t val, uint8_t frac_bits);
+
+/* Find first set bit in word. */
+uint32_t find_first_set_bit(uint32_t word);
+/* Find last set bit in word. */
+uint32_t find_last_set_bit(uint32_t word);
+/* Locate the closest element in an array. */
+uint32_t find_closest(int32_t val,
+		      const int32_t *array,
+		      uint32_t size);
+/* Shift the value and apply the specified mask. */
+uint32_t field_prep(uint32_t mask, uint32_t val);
+/* Get a field specified by a mask from a word. */
+uint32_t field_get(uint32_t mask, uint32_t word);
+/* Log base 2 of the given number. */
+int32_t log_base_2(uint32_t x);
+/* Find greatest common divisor of the given two numbers. */
+uint32_t greatest_common_divisor(uint32_t a,
+				 uint32_t b);
+/* Calculate best rational approximation for a given fraction. */
+void rational_best_approximation(uint32_t given_numerator,
+				 uint32_t given_denominator,
+				 uint32_t max_numerator,
+				 uint32_t max_denominator,
+				 uint32_t *best_numerator,
+				 uint32_t *best_denominator);
+/* Calculate the number of set bits. */
+uint32_t hweight8(uint32_t word);
+/* Calculate the quotient and the remainder of an integer division. */
+uint64_t do_div(uint64_t* n,
+		uint64_t base);
+/* Unsigned 64bit divide with 64bit divisor and remainder */
+uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor,
+		       uint64_t *remainder);
+/* Unsigned 64bit divide with 32bit divisor with remainder */
+uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder);
+int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder);
+/* Unsigned 64bit divide with 32bit divisor */
+uint64_t div_u64(uint64_t dividend, uint32_t divisor);
+int64_t div_s64(int64_t dividend, int32_t divisor);
+/* Converts from string to int32_t */
+int32_t str_to_int32(const char *str);
+/* Converts from string to uint32_t */
+uint32_t srt_to_uint32(const char *str);
+
+int crc16_gen(uint8_t* buffPtr, uint32_t dataLen, uint16_t poly, uint16_t* crcVal);
+bool crc16_check(uint8_t* buffPtr, uint32_t dataLen, uint32_t crcOffset, uint16_t poly);
+int crc8_gen(uint8_t* buffPtr, uint32_t dataLen, uint16_t poly, uint8_t* crcVal);
+bool crc8_check(uint8_t* buffPtr, uint32_t dataLen, uint32_t crcOffset, uint16_t poly);
+#endif // UTIL_H_
+