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datalink814_sp/bsp/microblaze_ps/include/_profile_timer_hw.h
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************
*
* _program_timer_hw.h:
* Timer related functions
*
******************************************************************************/
#ifndef PROFILE_TIMER_HW_H
#define PROFILE_TIMER_HW_H
#include "profile.h"
#ifdef PROC_PPC
#if defined __GNUC__
# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
#elif defined __DCC__
# define SYNCHRONIZE_IO __asm volatile(" eieio")
#else
# define SYNCHRONIZE_IO
#endif
#endif
#ifdef PROC_PPC
#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
#else
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
#endif
#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
(u32)(RegOffset)), (u32)(ValueToWrite))
#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(RegisterValue))
#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
#ifdef __cplusplus
extern "C" {
#endif
#ifdef PROC_PPC
#include "xexception_l.h"
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif /* TIMER_CONNECT_INTC */
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
#ifdef PROC_CORTEXA9
#include "xscutimer_hw.h"
#include "xscugic.h"
#endif
extern u32 timer_clk_ticks ;
/*--------------------------------------------------------------------
* PowerPC Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_PPC
#ifdef PPC_PIT_INTERRUPT
u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
#endif
#ifdef PROC_PPC440
#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
#define XREG_SPR_PIT XREG_SPR_DEC
#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
#endif
/* --------------------------------------------------------------------
* Disable the Timer - During Profiling
*
* For PIT Timer -
* 1. XTime_PITDisableInterrupt() ;
* 2. Store the remaining timer clk tick
* 3. Stop the PIT Timer
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define disable_timer() \
{ \
u32 val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
mtspr(XREG_SPR_PIT, 0); \
}
#else
#define disable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
/* --------------------------------------------------------------------
* Enable the Timer
*
* For PIT Timer -
* 1. Load the remaining timer clk ticks
* 2. XTime_PITEnableInterrupt() ;
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define enable_timer() \
{ \
u32 val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
}
#else
#define enable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
* For PIT Timer -
* 1. Load the timer clk ticks
* 2. Enable AutoReload and Interrupt
* 3. Clear PIT Timer Status bits
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define timer_ack() \
{ \
u32 val; \
mtspr(XREG_SPR_PIT, timer_clk_ticks); \
mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
}
#else
#define timer_ack() \
{ \
u32 csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
#endif
/*-------------------------------------------------------------------- */
#endif /* PROC_PPC */
/* -------------------------------------------------------------------- */
/* --------------------------------------------------------------------
* MicroBlaze Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_MICROBLAZE
/* --------------------------------------------------------------------
* Disable the Timer during Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define disable_timer() \
{ \
u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
Addr += (u32)XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(Addr); \
tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
OutAddr += (u32)XTC_TCSR_OFFSET; \
ProfIo_Out32(OutAddr, (u32)tmp_v); \
}
/* --------------------------------------------------------------------
* Enable the Timer after Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define enable_timer() \
{ \
u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
Addr += (u32)XTC_TCSR_OFFSET; \
u32 tmp_v = (u32)ProfIo_In32(Addr); \
tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
}
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
*-------------------------------------------------------------------- */
#define timer_ack() \
{ \
u32 csr; \
csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
}
/*-------------------------------------------------------------------- */
#endif /* PROC_MICROBLAZE */
/*-------------------------------------------------------------------- */
/* --------------------------------------------------------------------
* Cortex A9 Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_CORTEXA9
/* --------------------------------------------------------------------
* Disable the Timer during Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define disable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
}
/* --------------------------------------------------------------------
* Enable the Timer after Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define enable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
}
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
*-------------------------------------------------------------------- */
#define timer_ack() \
{ \
Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
}
/*-------------------------------------------------------------------- */
#endif /* PROC_CORTEXA9 */
/*-------------------------------------------------------------------- */
#ifdef __cplusplus
}
#endif
#endif
datalink814_sp/bsp/microblaze_ps/include/bspconfig.h
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1.3
* DO NOT EDIT.
*
* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Configurations for Standalone BSP
*
*******************************************************************/
#ifndef BSPCONFIG_H /* prevent circular inclusions */
#define BSPCONFIG_H /* by using protection macros */
#define MICROBLAZE_PVR_NONE
#endif /*end of __BSPCONFIG_H_*/
datalink814_sp/bsp/microblaze_ps/include/fsl.h
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#ifndef FSL_H
#define FSL_H
/*****************************************************************************/
/**
*
* @file fsl.h
*
* @addtogroup microblaze_fsl_macro MicroBlaze Processor FSL Macros
*
* Microblaze BSP includes macros to provide convenient access to accelerators
* connected to the MicroBlaze Fast Simplex Link (FSL) Interfaces.To use these functions,
* include the header file fsl.h in your source code
*
* @{
*
******************************************************************************/
#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
#ifdef __cplusplus
extern "C" {
#endif
/* Extended FSL macros. These now replace all of the previous FSL macros */
#define FSL_DEFAULT
#define FSL_NONBLOCKING n
#define FSL_EXCEPTION e
#define FSL_CONTROL c
#define FSL_ATOMIC a
#define FSL_NONBLOCKING_EXCEPTION ne
#define FSL_NONBLOCKING_CONTROL nc
#define FSL_NONBLOCKING_ATOMIC na
#define FSL_EXCEPTION_CONTROL ec
#define FSL_EXCEPTION_ATOMIC ea
#define FSL_CONTROL_ATOMIC ca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
#define FSL_EXCEPTION_CONTROL_ATOMIC eca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
/**
Performs a get function on an input FSL of the MicroBlaze processor
@param val variable to sink data from get function
@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
/**
Performs a put function on an input FSL of the MicroBlaze processor
@param val variable to source data to put function
@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
/**
Performs a test get function on an input FSL of the MicroBlaze processor
@param val variable to sink data from get function
@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
/**
Performs a put function on an input FSL of the MicroBlaze processor
@param id FSL identifier
@param flags valid FSL macro flags
*/
#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
/**
Performs a getd function on an input FSL of the MicroBlaze processor
@param val variable to sink data from getd function
@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
/**
Performs a putd function on an input FSL of the MicroBlaze processor
@param val variable to source data to putd function
@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
/**
Performs a test getd function on an input FSL of the MicroBlaze processor;
@param val variable to sink data from getd function
@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
/**
Performs a put function on an input FSL of the MicroBlaze processor
@param var FSL identifier
@param flags valid FSL macro flags
*/
#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
#ifdef __cplusplus
}
#endif
#endif /* FSL_H */
/**
* @} End of "addtogroup microblaze_fsl_macro".
*/
datalink814_sp/bsp/microblaze_ps/include/mb_interface.h
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/******************************************************************************
*
* Copyright (C) 2004 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file mb_interface.h
*
* @addtogroup microblaze_pseudo_asm_macro Microblaze Pseudo-asm Macros and Interrupt Handling APIs
*
* Microblaze BSP includes macros to provide convenient access to various registers
* in the MicroBlaze processor. Some of these macros are very useful within
* exception handlers for retrieving information about the exception.Also,
* the interrupt handling functions help manage interrupt handling on MicroBlaze
* processor devices.To use these functions, include the header file
* mb_interface.h in your source code
*
* @{
*
******************************************************************************/
#ifndef _MICROBLAZE_INTERFACE_H_
#define _MICROBLAZE_INTERFACE_H_
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#ifdef __cplusplus
extern "C" {
#endif
extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); /* Register exception handler */
extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
extern void microblaze_invalidate_icache_range(UINTPTR cacheaddr, u32 len); /* Invalidate a part of the icache */
extern void microblaze_invalidate_dcache_range(UINTPTR cacheaddr, u32 len); /* Invalidate a part of the dcache */
extern void microblaze_flush_dcache_range(UINTPTR cacheaddr, u32 len); /* Flush a part of the dcache */
extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */
extern void microblaze_flush_cache_ext(void); /* Flush cache ext */
extern void microblaze_flush_cache_ext_range(UINTPTR cacheaddr,
u32 len); /* Flush cache ext range */
extern void microblaze_invalidate_cache_ext_range(UINTPTR cacheaddr,
u32 len); /* Invalidate cache ext range */
/* Deprecated */
extern void microblaze_update_icache (s32 , s32 , s32 ) __attribute__((deprecated));
extern void microblaze_init_icache_range (s32 , s32 ) __attribute__((deprecated));
extern void microblaze_update_dcache (s32 , s32 , s32 ) __attribute__((deprecated));
extern void microblaze_init_dcache_range (s32 , s32 ) __attribute__((deprecated));
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
/* FSL Access Macros */
/* Blocking Data Read and Write to FSL no. id */
#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Data Read and Write to FSL no. id */
#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
/* Blocking Control Read and Write to FSL no. id */
#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Control Read and Write to FSL no. id */
#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
/* Polling versions of FSL access macros. This makes the FSL access interruptible */
#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
/* FSL valid and error check macros. */
#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
"andi\t%0,%0,0x10" : "=d" (error))
/* Pseudo assembler instructions */
#define clz(v) ({ u32 _rval; \
__asm__ __volatile__ ( \
"clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
); \
_rval; \
})
#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
#define mb_hibernate() ({ __asm__ __volatile__ ("hibernate\t"); })
#define mb_suspend() ({ __asm__ __volatile__ ("suspend\t"); })
#define mb_swapb(v) ({ u32 _rval; \
__asm__ __volatile__ ( \
"swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mb_swaph(v) ({ u32 _rval; \
__asm__ __volatile__ ( \
"swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
/** @name Microblaze pseudo-asm macros
*
* The following is a summary of the MicroBlaze processor pseudo-asm macros.
* @{
*/
/**
Return value from the general purpose register (GPR) rn.
@param rn General purpose register to be read.
*/
#define mfgpr(rn) ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the MSR.
@param None
*/
#define mfmsr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rmsr\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the Exception Address Register (EAR).
@param None
*/
#define mfear() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfeare() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfse\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the Exception Status Register (ESR).
@param None
*/
#define mfesr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,resr\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the Floating Point Status (FPS).
@param None
*/
#define mffsr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rfsr\n" : "=d"(_rval) \
); \
_rval; \
})
/*@}*/
#define mfpvr(rn) ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpvre(rn) ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfse\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfbtr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rbtr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfedr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,redr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpid() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpid\n" : "=d"(_rval)\
); \
_rval; \
})
#define mfzpr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rzpr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbx() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbx\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlblo() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlblo\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbhi() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbhi\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfslr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rslr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfshr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rshr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
"or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
); \
})
#define mtmsr(v) ({ __asm__ __volatile__ ( \
"mts\trmsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtfsr(v) ({ __asm__ __volatile__ ( \
"mts\trfsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtpid(v) ({ __asm__ __volatile__ ( \
"mts\trpid,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtzpr(v) ({ __asm__ __volatile__ ( \
"mts\trzpr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlblo(v) ({ __asm__ __volatile__ ( \
"mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbhi(v) ({ __asm__ __volatile__ ( \
"mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbsx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtslr(v) ({ __asm__ __volatile__ ( \
"mts\trslr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtshr(v) ({ __asm__ __volatile__ ( \
"mts\trshr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define lwx(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lwr(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lwea(lladdr) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lwea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define lhur(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lhuea(lladdr) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lhuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define lbur(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lbuea(lladdr) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lbuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define swx(address, data) ({ __asm__ __volatile__ ( \
"swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define swr(address, data) ({ __asm__ __volatile__ ( \
"swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define swea(lladdr, data) ({ __asm__ __volatile__ ( \
"swea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define shr(address, data) ({ __asm__ __volatile__ ( \
"shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define shea(lladdr, data) ({ __asm__ __volatile__ ( \
"shea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define sbr(address, data) ({ __asm__ __volatile__ ( \
"sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define sbea(lladdr, data) ({ __asm__ __volatile__ ( \
"sbea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define microblaze_getfpex_operand_a() ({ \
extern u32 mb_fpex_op_a; \
mb_fpex_op_a; \
})
#define microblaze_getfpex_operand_b() ({ \
extern u32 mb_fpex_op_b; \
mb_fpex_op_b; \
})
/* Deprecated MicroBlaze FSL macros */
#define microblaze_bread_datafsl(val, id) getfsl(val,id)
#define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
#ifdef __cplusplus
}
#endif
#endif // _MICROBLAZE_INTERFACE_H_
/**
* @} End of "addtogroup microblaze_pseudo_asm_macro".
*/
datalink814_sp/bsp/microblaze_ps/include/mblaze_nt_types.h
+50
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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef _MBLAZE_NT_TYPES_H
#define _MBLAZE_NT_TYPES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef char byte;
typedef short half;
typedef int word;
typedef unsigned char ubyte;
typedef unsigned short uhalf;
typedef unsigned int uword;
typedef ubyte boolean;
#ifdef __cplusplus
}
#endif
#endif
datalink814_sp/bsp/microblaze_ps/include/microblaze_exceptions_g.h
+39
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1.3
* DO NOT EDIT.
*
* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Exception Handling Header for MicroBlaze Processor
*
*******************************************************************/
#define MICROBLAZE_EXCEPTIONS_ENABLED 1
#define MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
datalink814_sp/bsp/microblaze_ps/include/microblaze_exceptions_i.h
+83
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_exceptions_i.h
*
* This header file contains defines for structures used by the microblaze
* hardware exception handler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00a 06/24/04 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */
#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
Xil_ExceptionHandler Handler;
void *CallBackRef;
} MB_ExceptionVectorTableEntry;
/* Exception IDs */
#define XEXC_ID_FSL 0U
#define XEXC_ID_UNALIGNED_ACCESS 1U
#define XEXC_ID_ILLEGAL_OPCODE 2U
#define XEXC_ID_M_AXI_I_EXCEPTION 3U
#define XEXC_ID_IPLB_EXCEPTION 3U
#define XEXC_ID_M_AXI_D_EXCEPTION 4U
#define XEXC_ID_DPLB_EXCEPTION 4U
#define XEXC_ID_DIV_BY_ZERO 5U
#define XEXC_ID_FPU 6U
#define XEXC_ID_STACK_VIOLATION 7U
#define XEXC_ID_MMU 7U
void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
datalink814_sp/bsp/microblaze_ps/include/microblaze_instructions.h
+118
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/******************************************************************************
*
* Copyright (C) 2018-2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_instructions.h
*
* It provides wrapper macros to call 32/64 bit variant of specific
* arithmetic/logical instructions, based on the processor in execution.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.8 mus 10/09/18 First release
*
*
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_INSTRUCTIONS_H /* prevent circular inclusions */
#define MICROBLAZE_INSTRUCTIONS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__arch64__)
#define ADDIK addlik
#define ADDK addlk
#define ADDI addli
#define ADD addl
#define ANDI andli
#define SUBK sublk
#define RSUBK rsublk
#define ORI orli
#define LI lli
#define LOAD ll
#define SI sli
#define STORE sl
#define BRLID brealid
#define BGTID beageid
#define BGEI beagei
#define BNEID beaneid
#define BLTI bealti
#define CMPU cmplu
#define BRID breaid
#define BNEID beaneid
#define BLEI bealei
#define BEQI beaeqi
#define BRI breai
#define XORI xorli
#define BNEI beanei
#define OR orl
#define BRALID brealid
#define XOR xorl
#else
#define ADDIK addik
#define ADDK addk
#define ADDI addi
#define ADD add
#define ANDI andi
#define SUBK subk
#define RSUBK rsubk
#define ORI ori
#define LI lwi
#define LOAD lw
#define SI swi
#define STORE sw
#define BRLID brlid
#define BGTID bgtid
#define BGEI bgei
#define BNEID bneid
#define BLTI blti
#define CMPU cmpu
#define BRID brid
#define BNEID bneid
#define BLEI blei
#define BEQI beqi
#define BRI bri
#define XORI xori
#define BNEI bnei
#define OR or
#define BRALID bralid
#define XOR xor
#endif
#ifdef __cplusplus
}
#endif
#endif /* MICROBLAZE_INSTRUCTIONS_H */
datalink814_sp/bsp/microblaze_ps/include/microblaze_interrupts_i.h
+73
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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_interrupts_i.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* High-level driver functions are defined in xintc.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
XInterruptHandler Handler;
void *CallBackRef;
} MB_InterruptVectorTableEntry;
#define MB_INTERRUPT_VECTOR_TABLE_ENTRIES 1
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
datalink814_sp/bsp/microblaze_ps/include/microblaze_sleep.h
+129
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/******************************************************************************
*
* Copyright (C) 2014-2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_sleep.h
*
* @addtogroup microblaze_sleep_routines Sleep Routines for Microblaze
*
* The microblaze_sleep.h file contains microblaze sleep APIs. These APIs
* provides delay for requested duration.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.1 asa 04/18/14 Add sleep function - first release.
* 6.6 srm 10/18/17 Added the Register offset definitions and Control/Status
* Register bit masks of the Axi timer.
*
* </pre>
*
* @note
* The microblaze_sleep.h file may contain architecture-dependent items.
*
******************************************************************************/
#ifndef MICROBLAZE_SLEEP_H /* prevent circular inclusions */
#define MICROBLAZE_SLEEP_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "mb_interface.h"
#include "xparameters.h"
#include "sleep.h"
/************************** Constant Definitions *****************************/
#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
/** @name Register Offset Definitions
* Register offsets within the Axi timer counter, there are multiple
* timer counters within a single device
* @{
*/
#define XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET 0U /**< Control/Status register */
#define XSLEEP_TIMER_AXITIMER_TLR_OFFSET 4U /**< Load register */
#define XSLEEP_TIMER_AXITIMER_TCR_OFFSET 8U /**< Timer counter register */
/* @} */
/** @name Control Status Register Bit Definitions
* Control Status Register bit masks
* Used to configure the Axi timer counter device.
* @{
*/
#define XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK 0x00000080U
/**< Enables only the specific timer */
#define XSLEEP_TIMER_AXITIMER_CSR_AUTO_RELOAD_MASK 0x00000010U
/**< In compare mode, configures the timer
* counter to reload from the Load Register.
* The default mode causes the timer counter
* to hold when the compare value is hit. In
* capture mode, configures the timer counter
* to not hold the previous capture value if
* a new event occurs. The default mode cause
* the timer counter to hold the capture value
* until recognized.*/
#define XSLEEP_TIMER_AXITIMER_CSR_LOAD_MASK 0x00000020U
/**< Loads the timer using the load value
* provided earlier in the Load Register,
* XSLEEP_TIMER_AXITIMER_TLR_OFFSET. */
#define XSLEEP_TIMER_AXITIMER_CSR_INT_OCCURED_MASK 0x00000100U
/**< If bit is set, an interrupt has occured.
* If set and '1' is written to this bit
* position, bit is cleared.*/
#define XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK 0x00000080U
/**< Enables only the specific timer */
/* @} */
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
static void Xil_SleepAxiTimer(u32 delay, u64 frequency);
static void XTime_StartAxiTimer();
#endif
void MB_Sleep(u32 MilliSeconds) __attribute__((__deprecated__));
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup microblaze_sleep_routines".
*/
datalink814_sp/bsp/microblaze_ps/include/profile.h
+127
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@@ -0,0 +1,127 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef PROFILE_H
#define PROFILE_H 1
#include <stdio.h>
#include "xil_types.h"
#include "profile_config.h"
#ifdef PROC_MICROBLAZE
#include "mblaze_nt_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
void _system_init( void ) ;
void _system_clean( void ) ;
void mcount(u32 frompc, u32 selfpc);
void profile_intr_handler( void ) ;
void _profile_init( void );
/****************************************************************************
* Profiling on hardware - Hash table maintained on hardware and data sent
* to xmd for gmon.out generation.
****************************************************************************/
/*
* histogram counters are unsigned shorts (according to the kernel).
*/
#define HISTCOUNTER u16
struct tostruct {
u32 selfpc;
s32 count;
s16 link;
u16 pad;
};
struct fromstruct {
u32 frompc ;
s16 link ;
u16 pad ;
} ;
/*
* general rounding functions.
*/
#define ROUNDDOWN(x,y) (((x)/(y))*(y))
#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
/*
* The profiling data structures are housed in this structure.
*/
struct gmonparam {
s32 state;
/* Histogram Information */
u16 *kcount; /* No. of bins in histogram */
u32 kcountsize; /* Histogram samples */
/* Call-graph Information */
struct fromstruct *froms;
u32 fromssize;
struct tostruct *tos;
u32 tossize;
/* Initialization I/Ps */
u32 lowpc;
u32 highpc;
u32 textsize;
/* u32 cg_froms, */
/* u32 cg_tos, */
};
extern struct gmonparam *_gmonparam;
extern s32 n_gmon_sections;
/*
* Possible states of profiling.
*/
#define GMON_PROF_ON 0
#define GMON_PROF_BUSY 1
#define GMON_PROF_ERROR 2
#define GMON_PROF_OFF 3
/*
* Sysctl definitions for extracting profiling information from the kernel.
*/
#define GPROF_STATE 0 /* int: profiling enabling variable */
#define GPROF_COUNT 1 /* struct: profile tick count buffer */
#define GPROF_FROMS 2 /* struct: from location hash bucket */
#define GPROF_TOS 3 /* struct: destination/count structure */
#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
#ifdef __cplusplus
}
#endif
#endif /* PROFILE_H */
datalink814_sp/bsp/microblaze_ps/include/pvr.h
+532
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/******************************************************************************
*
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file pvr.h
*
* @addtogroup microblaze_pvr_macros Microblaze PVR access routines and macros
*
* MicroBlaze processor v5.00.a and later versions have configurable
* Processor Version Registers (PVRs). The contents of the PVR are captured
* using the pvr_t data structure, which is defined as an array of 32-bit words,
* with each word corresponding to a PVR register on hardware. The number of PVR
* words is determined by the number of PVRs configured in the hardware. You should
* not attempt to access PVR registers that are not present in hardware, as the
* pvr_t data structure is resized to hold only as many PVRs as are present in
* hardware.
* To access information in the PVR:
* 1. Use the microblaze_get_pvr() function to populate the PVR data into a pvr_t
* data structure.
* 2. In subsequent steps, you can use any one of the PVR access macros list to
* get individual data stored in the PVR.
* 3. pvr.h header file must be included to source to use PVR macros.
*
* @{
*
******************************************************************************/
#ifndef _PVR_H
#define _PVR_H
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "mb_interface.h"
#include "bspconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defs */
typedef struct pvr_s {
#ifdef MICROBLAZE_PVR_FULL
unsigned int pvr[16];
#else
unsigned int pvr[1];
#endif
} pvr_t;
#define getpvr(pvrid, val) asm volatile ("mfs\t%0,rpvr" stringify(pvrid) "\n\t" : "=d" (val))
/* Basic PVR mask */
#define MICROBLAZE_PVR0_PVR_FULL_MASK 0x80000000
#define MICROBLAZE_PVR0_USE_BARREL_MASK 0x40000000
#define MICROBLAZE_PVR0_USE_DIV_MASK 0x20000000
#define MICROBLAZE_PVR0_USE_HW_MUL_MASK 0x10000000
#define MICROBLAZE_PVR0_USE_FPU_MASK 0x08000000
#define MICROBLAZE_PVR0_USE_EXCEPTION_MASK 0x04000000
#define MICROBLAZE_PVR0_USE_ICACHE_MASK 0x02000000
#define MICROBLAZE_PVR0_USE_DCACHE_MASK 0x01000000
#define MICROBLAZE_PVR0_USE_MMU_MASK 0x00800000
#define MICROBLAZE_PVR0_USE_BTC_MASK 0x00400000
#define MICROBLAZE_PVR0_ENDIANNESS_MASK 0x00200000
#define MICROBLAZE_PVR0_FAULT_TOLERANT_MASK 0x00100000
#define MICROBLAZE_PVR0_STACK_PROTECTION_MASK 0x00080000
#define MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK 0x0000FF00
#define MICROBLAZE_PVR0_USER1_MASK 0x000000FF
/* User 2 PVR mask */
#define MICROBLAZE_PVR1_USER2_MASK 0xFFFFFFFF
/* Configuration PVR masks */
#define MICROBLAZE_PVR2_D_AXI_MASK 0x80000000
#define MICROBLAZE_PVR2_D_LMB_MASK 0x40000000
#define MICROBLAZE_PVR2_D_PLB_MASK 0x02000000
#define MICROBLAZE_PVR2_I_AXI_MASK 0x20000000
#define MICROBLAZE_PVR2_I_LMB_MASK 0x10000000
#define MICROBLAZE_PVR2_I_PLB_MASK 0x01000000
#define MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
#define MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
#define MICROBLAZE_PVR2_INTERCONNECT_MASK 0x00800000
#define MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK 0x00400000
#define MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK 0x00080000
#define MICROBLAZE_PVR2_USE_MSR_INSTR_MASK 0x00020000
#define MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK 0x00010000
#define MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK 0x00008000
#define MICROBLAZE_PVR2_USE_BARREL_MASK 0x00004000
#define MICROBLAZE_PVR2_USE_DIV_MASK 0x00002000
#define MICROBLAZE_PVR2_USE_HW_MUL_MASK 0x00001000
#define MICROBLAZE_PVR2_USE_FPU_MASK 0x00000800
#define MICROBLAZE_PVR2_USE_FPU2_MASK 0x00000200
#define MICROBLAZE_PVR2_USE_MUL64_MASK 0x00000400
#define MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK 0x00000040
#define MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK 0x00000020
#define MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK 0x00000010
#define MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK 0x00000008
#define MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK 0x00000004
#define MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK 0x00000100
#define MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK 0x00000080
#define MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK 0x00000002
#define MICROBLAZE_PVR2_FPU_EXCEPTION_MASK 0x00000001
#define MICROBLAZE_PVR2_FSL_EXCEPTION_MASK 0x00040000
/* Debug and exception PVR masks */
#define MICROBLAZE_PVR3_DEBUG_ENABLED_MASK 0x80000000
#define MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
#define MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
#define MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
#define MICROBLAZE_PVR3_FSL_LINKS_MASK 0x00000380
#define MICROBLAZE_PVR3_BTC_SIZE_MASK 0x00000007
/* ICache config PVR masks */
#define MICROBLAZE_PVR4_USE_ICACHE_MASK 0x80000000
#define MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
#define MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
#define MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
#define MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
#define MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK 0x00008000
#define MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK 0x00002000
#define MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK 0x00001C00
#define MICROBLAZE_PVR4_ICACHE_STREAMS_MASK 0x00000300
#define MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
#define MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK 0x00000040
/* DCache config PVR masks */
#define MICROBLAZE_PVR5_USE_DCACHE_MASK 0x80000000
#define MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
#define MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
#define MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
#define MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
#define MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK 0x00008000
#define MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK 0x00004000
#define MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK 0x00002000
#define MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK 0x00001C00
#define MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
#define MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK 0x00000040
#if defined(__arch64__)
/* ICache base address PVR mask */
#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFFFFFFFFFF
/* ICache high address PVR mask */
#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFFFFFFFFFF
/* DCache base address PVR mask */
#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFFFFFFFFFF
/* DCache high address PVR mask */
#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFFFFFFFFFF
#else
/* ICache base address PVR mask */
#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
/* ICache high address PVR mask */
#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
/* DCache base address PVR mask */
#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
/* DCache high address PVR mask */
#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
#endif
/* Target family PVR mask */
#define MICROBLAZE_PVR10_TARGET_FAMILY_MASK 0xFF000000
/* MSR Reset value PVR mask */
#define MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK 0x000007FF
/* MMU value PVR mask */
#define MICROBLAZE_PVR11_MMU_MASK 0xC0000000
#define MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK 0x38000000
#define MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK 0x07000000
#define MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK 0x00C00000
#define MICROBLAZE_PVR11_MMU_ZONES_MASK 0x003E0000
#define MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK 0x00010000
/* PVR access macros */
/**
Return non-zero integer if PVR is of type FULL, 0 if basic
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_IS_FULL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_PVR_FULL_MASK)
/**
Return non-zero integer if hardware barrel shifter present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BARREL_MASK)
/**
Return non-zero integer if hardware divider present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_USE_DIV(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DIV_MASK)
/**
Return non-zero integer if hardware multiplier present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_HW_MUL_MASK)
/**
Return non-zero integer if hardware floating point unit (FPU) present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_USE_FPU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_FPU_MASK)
/**
Return non-zero integer if I-cache present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_ICACHE_MASK)
/**
Return non-zero integer if D-cache present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DCACHE_MASK)
#define MICROBLAZE_PVR_USE_MMU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_MMU_MASK)
#define MICROBLAZE_PVR_USE_BTC(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BTC_MASK)
#define MICROBLAZE_PVR_ENDIANNESS(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_ENDIANNESS_MASK)
#define MICROBLAZE_PVR_FAULT_TOLERANT(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_FAULT_TOLERANT_MASK)
#define MICROBLAZE_PVR_STACK_PROTECTION(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_STACK_PROTECTION_MASK)
/**
Return MicroBlaze processor version encoding. Refer to the MicroBlaze Processor
Reference Guide (UG081) for mappings from encodings to actual hardware versions.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_MICROBLAZE_VERSION(_pvr) ((_pvr.pvr[0] & MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK) >> 8)
/**
Return the USER1 field stored in the PVR.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_USER1(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USER1_MASK)
/**
Return the USER2 field stored in the PVR.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_USER2(_pvr) (_pvr.pvr[1] & MICROBLAZE_PVR1_USER2_MASK)
#define MICROBLAZE_PVR_D_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_AXI_MASK)
/**
Return non-zero integer if Data Side PLB
interface is present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_D_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_LMB_MASK)
/**
Return non-zero integer if Data Side PLB interface is present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_D_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_PLB_MASK)
#define MICROBLAZE_PVR_I_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_AXI_MASK)
/**
Return non-zero integer if Instruction Side Local Memory Bus (LMB) interface present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_I_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_LMB_MASK)
/**
Return non-zero integer if Instruction Side PLB interface present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_I_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_PLB_MASK)
/**
Return non-zero integer if interrupts are configured as edge-triggered.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_INTERRUPT_IS_EDGE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK)
/**
Return non-zero integer if interrupts are configured as positive edge triggered.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_EDGE_IS_POSITIVE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK)
/**
Return non-zero if MicroBlaze processor has PLB interconnect; otherwise return zero.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERCONNECT_MASK)
#define MICROBLAZE_PVR_STREAM_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK)
#define MICROBLAZE_PVR_USE_EXTENDED_FSL_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK)
#define MICROBLAZE_PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MSR_INSTR_MASK)
#define MICROBLAZE_PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK)
#define MICROBLAZE_PVR_AREA_OPTIMIZED(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK)
/**
Return non-zero integer if MicroBlaze processor supports 64-bit products for
multiplies.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MUL64_MASK)
/**
Return non-zero integer if opcode 0x0 is treated as an illegal opcode.
multiplies.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_OPCODE_0x0_ILLEGAL(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK)
/**
Return non-zero integer if unaligned exceptions are supported.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_UNALIGNED_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK)
/**
Return non-zero integer if illegal opcode exceptions are supported.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_ILL_OPCODE_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK)
#define MICROBLAZE_PVR_M_AXI_I_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK)
/**
Return non-zero integer if I-PLB exceptions are supported.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_IPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK)
#define MICROBLAZE_PVR_M_AXI_D_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK)
/**
Return non-zero integer if I-PLB exceptions are supported.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_DPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK)
/**
Return non-zero integer if divide by zero exceptions are supported.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_DIV_ZERO_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK)
/**
Return non-zero integer if FPU exceptions are supported.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FPU_EXCEPTION_MASK)
/**
Return non-zero integer if FSL exceptions are present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FSL_EXCEPTION_MASK)
/**
Return non-zero integer if debug is enabled.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_DEBUG_ENABLED_MASK)
/**
Return the number of hardware PC breakpoints available.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_NUMBER_OF_PC_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
/**
Return the number of read address hardware watchpoints supported.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
/**
Return the number of write address hardware watchpoints supported.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
/**
Return the number of FSL links present.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_FSL_LINKS_MASK) >> 7)
#define MICROBLAZE_PVR_BTC_SIZE(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_BTC_SIZE_MASK)
/**
Return the number of address tag bits for the I-cache.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_ICACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
/**
Return non-zero if writes to I-caches are allowed.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_ICACHE_ALLOW_WR(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK)
/**
Return the length of each I-cache line in bytes.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_ICACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK) >> 21))
/**
Return the size of the D-cache in bytes.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_ICACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
#define MICROBLAZE_PVR_ICACHE_ALWAYS_USED(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK)
#define MICROBLAZE_PVR_ICACHE_INTERFACE(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK)
#define MICROBLAZE_PVR_ICACHE_VICTIMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK) >> 10)
#define MICROBLAZE_PVR_ICACHE_STREAMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_STREAMS_MASK) >> 8)
#define MICROBLAZE_PVR_ICACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK)
#define MICROBLAZE_PVR_ICACHE_DATA_WIDTH(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK)
/**
Return the number of address tag bits for the D-cache.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_DCACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
/**
Return non-zero if writes to D-cache are allowed.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_DCACHE_ALLOW_WR(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK)
/**
Return the length of each line in the D-cache in bytes.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_DCACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK) >> 21))
/**
Return the size of the D-cache in bytes.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_DCACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
#define MICROBLAZE_PVR_DCACHE_ALWAYS_USED(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK)
#define MICROBLAZE_PVR_DCACHE_USE_WRITEBACK(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK)
#define MICROBLAZE_PVR_DCACHE_INTERFACE(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK)
#define MICROBLAZE_PVR_DCACHE_VICTIMS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK) >> 10)
#define MICROBLAZE_PVR_DCACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK)
#define MICROBLAZE_PVR_DCACHE_DATA_WIDTH(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK)
/**
Return the base address of the I-cache.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_ICACHE_BASEADDR(_pvr) (_pvr.pvr[6] & MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK)
/**
Return the high address of the I-cache.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_ICACHE_HIGHADDR(_pvr) (_pvr.pvr[7] & MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK)
/**
Return the base address of the D-cache.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_DCACHE_BASEADDR(_pvr) (_pvr.pvr[8] & MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK)
/**
Return the high address of the D-cache.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_DCACHE_HIGHADDR(_pvr) (_pvr.pvr[9] & MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK)
/**
Return the encoded target family identifier.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_TARGET_FAMILY(_pvr) ((_pvr.pvr[10] & MICROBLAZE_PVR10_TARGET_FAMILY_MASK) >> 24)
/**
Refer to the MicroBlaze Processor Reference Guide (UG081) for mappings from encodings
to target family name strings.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_MSR_RESET_VALUE(_pvr) (_pvr.pvr[11] & MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK)
/**
Returns the value of C_USE_MMU. Refer to the MicroBlaze Processor Reference Guide
(UG081) for mappings from MMU type values to MMU function.
@param _pvr pvr data structure
*/
#define MICROBLAZE_PVR_MMU_TYPE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_MASK) >> 30)
#define MICROBLAZE_PVR_MMU_ITLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK) >> 27)
#define MICROBLAZE_PVR_MMU_DTLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK) >> 24)
#define MICROBLAZE_PVR_MMU_TLB_ACCESS(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK) >> 22)
#define MICROBLAZE_PVR_MMU_ZONES(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ZONES_MASK) >> 17)
#define MICROBLAZE_PVR_MMU_PRIVILEGED_INSTR(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK) >> 16)
/* Protos */
int microblaze_get_pvr (pvr_t *pvr);
#ifdef __cplusplus
}
#endif
#endif /* _PVR_H */
/**
* @} End of "addtogroup microblaze_pvr_macros".
*/
datalink814_sp/bsp/microblaze_ps/include/sleep.h
+115
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@@ -0,0 +1,115 @@
/******************************************************************************
*
* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file sleep.h
*
* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
* related APIs.
*
* <pre>
* MODIFICATION HISTORY :
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 6.6 srm 11/02/17 Added processor specific sleep rountines
* function prototypes.
*
* </pre>
*
******************************************************************************/
#ifndef SLEEP_H
#define SLEEP_H
#include "xil_types.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/*****************************************************************************/
/**
*
* This macro polls an address periodically until a condition is met or till the
* timeout occurs.
* The minimum timeout for calling this macro is 100us. If the timeout is less
* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
* If the timeout is not a multiple of 100us, it waits for a timeout of
* the next usec value which is a multiple of 100us.
*
* @param IO_func - accessor function to read the register contents.
* Depends on the register width.
* @param ADDR - Address to be polled
* @param VALUE - variable to read the value
* @param COND - Condition to checked (usually involves VALUE)
* @param TIMEOUT_US - timeout in micro seconds
*
* @return 0 - when the condition is met
* -1 - when the condition is not met till the timeout period
*
* @note none
*
*****************************************************************************/
#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
( { \
u64 timeout = TIMEOUT_US/100; \
if(TIMEOUT_US%100!=0) \
timeout++; \
for(;;) { \
VALUE = IO_func(ADDR); \
if(COND) \
break; \
else { \
usleep(100); \
timeout--; \
if(timeout==0) \
break; \
} \
} \
(timeout>0) ? 0 : -1; \
} )
void usleep(unsigned long useconds);
void sleep(unsigned int seconds);
int usleep_R5(unsigned long useconds);
unsigned sleep_R5(unsigned int seconds);
int usleep_MB(unsigned long useconds);
unsigned sleep_MB(unsigned int seconds);
int usleep_A53(unsigned long useconds);
unsigned sleep_A53(unsigned int seconds);
int usleep_A9(unsigned long useconds);
unsigned sleep_A9(unsigned int seconds);
#ifdef __cplusplus
}
#endif
#endif
datalink814_sp/bsp/microblaze_ps/include/xaxidma.h
+761
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@@ -0,0 +1,761 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma.h
* @addtogroup axidma_v9_9
* @{
* @details
*
* This is the driver API for the AXI DMA engine.
*
* For a full description of DMA features, please see the hardware spec. This
* driver supports the following features:
*
* - Scatter-Gather DMA (SGDMA)
* - Simple DMA
* - Interrupts
* - Programmable interrupt coalescing for SGDMA
* - APIs to manage Buffer Descriptors (BD) movement to and from the SGDMA
* engine
*
* <b>Simple DMA</b>
*
* Simple DMA allows the application to define a single transaction between DMA
* and Device. It has two channels: one from the DMA to Device and the other
* from Device to DMA. Application has to set the buffer address and
* length fields to initiate the transfer in respective channel.
*
* <b>Transactions</b>
*
* The object used to describe a transaction is referred to as a Buffer
* Descriptor (BD). Buffer descriptors are allocated in the user application.
* The user application needs to set buffer address, transfer length, and
* control information for this transfer. The control information includes
* SOF and EOF. Definition of those masks are in xaxidma_hw.h
*
* <b>Scatter-Gather DMA</b>
*
* SGDMA allows the application to define a list of transactions in memory which
* the hardware will process without further application intervention. During
* this time, the application is free to continue adding more work to keep the
* Hardware busy.
*
* User can check for the completion of transactions through polling the
* hardware, or interrupts.
*
* SGDMA processes whole packets. A packet is defined as a series of
* data bytes that represent a message. SGDMA allows a packet of data to be
* broken up into one or more transactions. For example, take an Ethernet IP
* packet which consists of a 14 byte header followed by a 1 or more bytes of
* payload. With SGDMA, the application may point a BD to the header and another
* BD to the payload, then transfer them as a single message. This strategy can
* make a TCP/IP stack more efficient by allowing it to keep packet header and
* data in different memory regions instead of assembling packets into
* contiguous blocks of memory.
*
* <b>BD Ring Management</b>
*
* BD rings are shared by the software and the hardware.
*
* The hardware expects BDs to be setup as a linked list. The DMA hardware walks
* through the list by following the next pointer field of a completed BD.
* The hardware stops processing when the just completed BD is the same as the
* BD specified in the Tail Ptr register in the hardware.
*
* The last BD in the ring is linked to the first BD in the ring.
*
* All BD management are done inside the driver. The user application should not
* directly modify the BD fields. Modifications to the BD fields should always
* go through the specific API functions.
*
* Within the ring, the driver maintains four groups of BDs. Each group consists
* of 0 or more adjacent BDs:
*
* - Free: The BDs that can be allocated by the application with
* XAxiDma_BdRingAlloc().
*
* - Pre-process: The BDs that have been allocated with
* XAxiDma_BdRingAlloc(). These BDs are under application control. The
* application modifies these BDs through driver API to prepare them
* for DMA transactions.
*
* - Hardware: The BDs that have been enqueued to hardware with
* XAxiDma_BdRingToHw(). These BDs are under hardware control and may be in a
* state of awaiting hardware processing, in process, or processed by
* hardware. It is considered an error for the application to change BDs
* while they are in this group. Doing so can cause data corruption and lead
* to system instability.
*
* - Post-process: The BDs that have been processed by hardware and have
* been extracted from the Hardware group with XAxiDma_BdRingFromHw().
* These BDs are under application control. The application can check the
* transfer status of these BDs. The application use XAxiDma_BdRingFree()
* to put them into the Free group.
*
* BDs are expected to transition in the following way for continuous
* DMA transfers:
* <pre>
*
* XAxiDma_BdRingAlloc() XAxiDma_BdRingToHw()
* Free ------------------------> Pre-process ----------------------> Hardware
* |
* /|\ |
* | XAxiDma_BdRingFree() XAxiDma_BdRingFromHw() |
* +--------------------------- Post-process <----------------------+
*
* </pre>
*
* When a DMA transfer is to be cancelled before enqueuing to hardware,
* application can return the requested BDs to the Free group using
* XAxiDma_BdRingUnAlloc(), as shown below:
* <pre>
*
* XAxiDma_BdRingUnAlloc()
* Free <----------------------- Pre-process
*
* </pre>
*
* The API provides functions for BD list traversal:
* - XAxiDma_BdRingNext()
* - XAxiDma_BdRingPrev()
*
* These functions should be used with care as they do not understand where
* one group ends and another begins.
*
* <b>SGDMA Descriptor Ring Creation</b>
*
* BD ring is created using XAxiDma_BdRingCreate(). The memory for the BD ring
* is allocated by the application, and it has to be contiguous. Physical
* address is required to setup the BD ring.
*
* The applicaiton can use XAxiDma_BdRingMemCalc() to find out the amount of
* memory needed for a certain number of BDs. XAxiDma_BdRingCntCalc() can be
* used to find out how many BDs can be allocated for certain amount of memory.
*
* A helper function, XAxiDma_BdRingClone(), can speed up the BD ring setup if
* the BDs have same types of controls, for example, SOF and EOF. After
* using the XAxiDma_BdRingClone(), the application only needs to setup the
* buffer address and transfer length. Note that certain BDs in one packet,
* for example, the first BD and the last BD, may need to setup special
* control information.
*
* <b>Descriptor Ring State Machine</b>
*
* There are two states of the BD ring:
*
* - HALTED (H), where hardware is not running
*
* - NOT HALTED (NH), where hardware is running
*
* The following diagram shows the state transition for the DMA engine:
*
* <pre>
* _____ XAxiDma_StartBdRingHw(), or XAxiDma_BdRingStart(), ______
* | | or XAxiDma_Resume() | |
* | H |----------------------------------------------------->| NH |
* | |<-----------------------------------------------------| |
* ----- XAxiDma_Pause() or XAxiDma_Reset() ------
* </pre>
*
* <b>Interrupt Coalescing</b>
*
* SGDMA provides control over the frequency of interrupts through interrupt
* coalescing. The DMA engine provides two ways to tune the interrupt
* coalescing:
*
* - The packet threshold counter. Interrupt will fire once the
* programmable number of packets have been processed by the engine.
*
* - The packet delay timer counter. Interrupt will fire once the
* programmable amount of time has passed after processing the last packet,
* and no new packets to process. Note that the interrupt will only fire if
* at least one packet has been processed.
*
* <b> Interrupt </b>
*
* Interrupts are handled by the user application. Each DMA channel has its own
* interrupt ID. The driver provides APIs to enable/disable interrupt,
* and tune the interrupt frequency regarding to packet processing frequency.
*
* <b> Software Initialization </b>
*
*
* To use the Simple mode DMA engine for transfers, the following setup is
* required:
*
* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
* initializes a driver instance for the given DMA engine and resets the
* engine.
*
* - Enable interrupts if chosen to use interrupt mode. The application is
* responsible for setting up the interrupt system, which includes providing
* and connecting interrupt handlers and call back functions, before
* enabling the interrupts.
*
* - Set the buffer address and length field in respective channels to start
* the DMA transfer
*
* To use the SG mode DMA engine for transfers, the following setup are
* required:
*
* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
* initializes a driver instance for the given DMA engine and resets the
* engine.
*
* - BD Ring creation. A BD ring is needed per DMA channel and can be built by
* calling XAxiDma_BdRingCreate().
*
* - Enable interrupts if chose to use interrupt mode. The application is
* responsible for setting up the interrupt system, which includes providing
* and connecting interrupt handlers and call back functions, before
* enabling the interrupts.
*
* - Start a DMA transfer: Call XAxiDma_BdRingStart() to start a transfer for
* the first time or after a reset, and XAxiDma_BdRingToHw() if the channel
* is already started. Calling XAxiDma_BdRingToHw() when a DMA channel is not
* running will not put the BDs to the hardware, and the BDs will be processed
* later when the DMA channel is started through XAxiDma_BdRingStart().
*
* <b> How to start DMA transactions </b>
*
* The user application uses XAxiDma_BdRingToHw() to submit BDs to the hardware
* to start DMA transfers.
*
* For both channels, if the DMA engine is currently stopped (using
* XAxiDma_Pause()), the newly added BDs will be accepted but not processed
* until the DMA engine is started, using XAxiDma_BdRingStart(), or resumed,
* using XAxiDma_Resume().
*
* <b> Software Post-Processing on completed DMA transactions </b>
*
* If the interrupt system has been set up and the interrupts are enabled,
* a DMA channels notifies the software about the completion of a transfer
* through interrupts. Otherwise, the user application can poll for
* completions of the BDs, using XAxiDma_BdRingFromHw() or
* XAxiDma_BdHwCompleted().
*
* - Once BDs are finished by a channel, the application first needs to fetch
* them from the channel using XAxiDma_BdRingFromHw().
*
* - On the TX side, the application now could free the data buffers attached to
* those BDs as the data in the buffers has been transmitted.
*
* - On the RX side, the application now could use the received data in the
* buffers attached to those BDs.
*
* - For both channels, completed BDs need to be put back to the Free group
* using XAxiDma_BdRingFree(), so they can be used for future transactions.
*
* - On the RX side, it is the application's responsibility to have BDs ready
* to receive data at any time. Otherwise, the RX channel refuses to
* accept any data if it has no RX BDs.
*
* <b> Examples </b>
*
* We provide five examples to show how to use the driver API:
* - One for SG interrupt mode (xaxidma_example_sg_intr.c), multiple BD/packets transfer
* - One for SG polling mode (xaxidma_example_sg_poll.c), single BD transfer.
* - One for SG polling mode (xaxidma_poll_multi_pkts.c), multiple BD/packets transfer
* - One for simple polling mode (xaxidma_example_simple_poll.c)
* - One for simple Interrupt mode (xaxidma_example_simple_intr.c)
*
* <b> Address Translation </b>
*
* All buffer addresses and BD addresses for the hardware are physical
* addresses. The user application is responsible to provide physical buffer
* address for the BD upon BD ring creation. The user application accesses BD
* through its virtual addess. The driver maintains the address translation
* between the physical and virtual address for BDs.
*
* <b> Cache Coherency </b>
*
* This driver expects all application buffers attached to BDs to be in cache
* coherent memory. If cache is used in the system, buffers for transmit MUST
* be flushed from the cache before passing the associated BD to this driver.
* Buffers for receive MUST be invalidated before accessing the data.
*
* <b> Alignment </b>
*
* For BDs:
*
* Minimum alignment is defined by the constant XAXIDMA_BD_MINIMUM_ALIGNMENT.
* This is the smallest alignment allowed by both hardware and software for them
* to properly work.
*
* If the descriptor ring is to be placed in cached memory, alignment also MUST
* be at least the processor's cache-line size. Otherwise, system instability
* occurs. For alignment larger than the cache line size, multiple cache line
* size alignment is required.
*
* Aside from the initial creation of the descriptor ring (see
* XAxiDma_BdRingCreate()), there are no other run-time checks for proper
* alignment of BDs.
*
* For application data buffers:
*
* Application data buffers may reside on any alignment if DRE is built into the
* hardware. Otherwise, application data buffer must be word-aligned. The word
* is defined by XPAR_AXIDMA_0_M_AXIS_MM2S_TDATA_WIDTH for transmit and
* XPAR_AXIDMA_0_S_AXIS_S2MM_TDATA_WIDTH for receive.
*
* For scatter gather transfers that have more than one BDs in the chain of BDs,
* Each BD transfer length must be multiple of word too. Otherwise, internal
* error happens in the hardware.
*
* <b> Error Handling </b>
*
* The DMA engine will halt on all error conditions. It requires the software
* to do a reset before it can start process new transfer requests.
*
* <b> Restart After Stopping </b>
*
* After the DMA engine has been stopped (through reset or reset after an error)
* the software keeps track of the current BD pointer when reset happens, and
* processing of BDs can be resumed through XAxiDma_BdRingStart().
*
* <b> Limitations </b>
*
* This driver does not have any mechanisms for mutual exclusion. It is up to
* the application to provide this protection.
*
* <b> Hardware Defaults & Exclusive Use </b>
*
* After the initialization or reset, the DMA engine is in the following
* default mode:
* - All interrupts are disabled.
*
* - Interrupt coalescing counter is 1.
*
* - The DMA engine is not running (halted). Each DMA channel is started
* separately, using XAxiDma_StartBdRingHw() if no BDs are setup for transfer
* yet, or XAxiDma_BdRingStart() otherwise.
*
* The driver has exclusive use of the registers and BDs. All accesses to the
* registers and BDs should go through the driver interface.
*
* <b> Debug Print </b>
*
* To see the debug print for the driver, please put "-DDEBUG" as the extra
* compiler flags in software platform settings. Also comment out the line in
* xdebug.h: "#undef DEBUG".
*
* <b>Changes From v1.00a</b>
*
* . We have changes return type for XAxiDma_BdSetBufAddr() from void to int
* . We added XAxiDma_LookupConfig() so that user does not need to look for the
* hardware settings anymore.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 4.00a rkv 02/22/11 Added support for simple DMA mode
* New API added for simple DMA mode are
* - XAxiDma_Busy
* - XAxiDma_SimpleTransfer
* New Macros added for simple DMA mode are
* - XAxiDma_HasSg
* - XAxiDma_IntrEnable
* - XAxiDma_IntrGetEnabled
* - XAxiDma_IntrDisable
* - XAxiDma_IntrGetIrq
* - XAxiDma_IntrAckIrq
* 5.00a srt 08/25/11 Added support for memory barrier and modified
* Cache Macros to have a common API for Microblaze
* and Zynq.
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA mode.
* - Changed APIs:
* * XAxiDma_GetRxRing(InstancePtr, RingIndex)
* * XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
* u32 BuffAddr, u32 Length,
* int Direction, int RingIndex)
* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
* u32 LenBytes, u32 LengthMask)
* * XAxiDma_BdGetActualLength(BdPtr, LengthMask)
* * XAxiDma_BdGetLength(BdPtr, LengthMask)
* - New APIs
* * XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
* int Direction, int Select)
* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* 7.00a srt 06/18/12 All the APIs changed in v6_00_a are reverted back for
* backward compatibility.
* - New API:
* XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
* 7.01a srt 10/26/12 - Fixed issue with driver as it fails with IP version
* < 6.00a as the parameter C_NUM_*_CHANNELS is not
* applicable.
* - Changed the logic of MCDMA BD fields Set APIs, to
* clear the field first and then set it.
* 7.02a srt 01/23/13 Replaced *_TDATA_WIDTH parameters to *_DATA_WIDTH
* (CR 691867)
* Updated DDR base address for IPI designs (CR 703656).
* 8.0 adk 19/12/13 Updated as per the New Tcl API's
* srt 01/29/14 Added support for Micro DMA Mode and cyclic mode of
* operations.
* - New APIs:
* * XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr,
* int Direction, int Select)
* * XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32)
* 8.1 adk 20/01/15 Added support for peripheral test. Created the self
* test example to include it on peripheral test's(CR#823144).
* 8.1 adk 29/01/15 Added the sefltest api (XAxiDma_Selftest) to the driver source files
* (xaxidma_selftest.c) and called this from the selftest example
* 9.0 adk 27/07/15 Added support for 64-bit Addressing.
* 9.0 adk 19/08/15 Fixed CR#873125 DMA SG Mode example tests are failing on
* HW in 2015.3.
* 9.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* 9.3 adk 26/07/16 Reduce the size of the buffer descriptor to 64 bytes.
* ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed" strings
* are available in all examples. This is a fix for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Modified Comment lines in functions to recognize
* it as documentation block and added tabspace at return
* statements in functions of axidma examples for proper
* documentation while generating doxygen.
* Modified readme file in examples folder.
* 9.4 adk 25/07/17 Added example for cyclic dma mode CR#974218.
* adk 08/08/17 Fixed CR#980607 Can't select individual AXI DMA code examples.
* Fixed compilation warning in the driver
* 9.5 adk 17/10/17 Fixed CR#987026 mulit packet example fails on A53.
* 26/10/17 Fixed CR#987214 Fix race condition in the XAxiDma_Reset().
* rsp 11/01/17 Fixed CR#988210 Add interface to do config lookup based
* on base address.
* adk 13/11/17 Fixed CR#989455 multi-channel interrupt example fails on A53.
* 9.6 rsp 01/11/18 Fixed CR#976392 In XAxiDma struct use UINTPTR for RegBase.
* In XAxiDma_LookupConfigBaseAddr() use UINTPTR for Baseaddr.
* 9.7 rsp 04/25/18 Add SgLengthWidth member in dma config structure. CR #1000474
* </pre>
*
******************************************************************************/
#ifndef XAXIDMA_H_ /* prevent circular inclusions */
#define XAXIDMA_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xaxidma_bdring.h"
#ifdef __MICROBLAZE__
#include "xenv.h"
#else
#include <string.h>
#include "xil_cache.h"
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* The XAxiDma driver instance data. An instance must be allocated for each DMA
* engine in use.
*/
typedef struct XAxiDma {
UINTPTR RegBase; /* Virtual base address of DMA engine */
int HasMm2S; /* Has transmit channel */
int HasS2Mm; /* Has receive channel */
int Initialized; /* Driver has been initialized */
int HasSg;
XAxiDma_BdRing TxBdRing; /* BD container management for TX channel */
XAxiDma_BdRing RxBdRing[16]; /* BD container management for RX channel */
int TxNumChannels;
int RxNumChannels;
int MicroDmaMode;
int AddrWidth; /**< Address Width */
} XAxiDma;
/**
* The configuration structure for AXI DMA engine
*
* This structure passes the hardware building information to the driver
*/
typedef struct {
u32 DeviceId;
UINTPTR BaseAddr;
int HasStsCntrlStrm;
int HasMm2S;
int HasMm2SDRE;
int Mm2SDataWidth;
int HasS2Mm;
int HasS2MmDRE;
int S2MmDataWidth;
int HasSg;
int Mm2sNumChannels;
int S2MmNumChannels;
int Mm2SBurstSize;
int S2MmBurstSize;
int MicroDmaMode;
int AddrWidth; /**< Address Width */
int SgLengthWidth;
} XAxiDma_Config;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Get Transmit (Tx) Ring ptr
*
* Warning: This has a different API than the LLDMA driver. It now returns
* the pointer to the BD ring.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return Pointer to the Tx Ring
*
* @note C-style signature:
* XAxiDma_BdRing * XAxiDma_GetTxRing(XAxiDma * InstancePtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_GetTxRing(InstancePtr) \
(&((InstancePtr)->TxBdRing))
/*****************************************************************************/
/**
* Get Receive (Rx) Ring ptr
*
* Warning: This has a different API than the LLDMA driver. It now returns
* the pointer to the BD ring.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return Pointer to the Rx Ring
*
* @note
* C-style signature:
* XAxiDma_BdRing * XAxiDma_GetRxRing(XAxiDma * InstancePtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_GetRxRing(InstancePtr) \
(&((InstancePtr)->RxBdRing[0]))
/*****************************************************************************/
/**
* Get Receive (Rx) Ring ptr of a Index
*
* Warning: This has a different API than the LLDMA driver. It now returns
* the pointer to the BD ring.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
* @param RingIndex is the channel Index.
*
* @return Pointer to the Rx Ring
*
* @note
* C-style signature:
* XAxiDma_BdRing * XAxiDma_GetRxIndexRing(XAxiDma * InstancePtr,
int RingIndex)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_GetRxIndexRing(InstancePtr, RingIndex) \
(&((InstancePtr)->RxBdRing[RingIndex]))
/*****************************************************************************/
/**
* This function checks whether system is configured as Simple or
* Scatter Gather mode
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return
* - TRUE if configured as SG mode
* - FALSE if configured as simple mode
*
* @note None
*
*****************************************************************************/
#define XAxiDma_HasSg(InstancePtr) ((InstancePtr)->HasSg) ? TRUE : FALSE
/*****************************************************************************/
/**
* This function enables interrupts specified by the Mask in specified
* direction, Interrupts that are not in the mask are not affected.
*
* @param InstancePtr is the driver instance we are working on
* @param Mask is the mask for the interrupts to be enabled
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
* @return None
*
* @note None
*
*****************************************************************************/
#define XAxiDma_IntrEnable(InstancePtr, Mask, Direction) \
XAxiDma_WriteReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
| (Mask & XAXIDMA_IRQ_ALL_MASK))
/*****************************************************************************/
/**
* This function gets the mask for the interrupts that are currently enabled
*
* @param InstancePtr is the driver instance we are working on
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
*
* @return The bit mask for the interrupts that are currently enabled
*
* @note None
*
*****************************************************************************/
#define XAxiDma_IntrGetEnabled(InstancePtr, Direction) \
XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET) &\
XAXIDMA_IRQ_ALL_MASK)
/*****************************************************************************/
/**
* This function disables interrupts specified by the Mask. Interrupts that
* are not in the mask are not affected.
*
* @param InstancePtr is the driver instance we are working on
* @param Mask is the mask for the interrupts to be disabled
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
* @return None
*
* @note None
*
*****************************************************************************/
#define XAxiDma_IntrDisable(InstancePtr, Mask, Direction) \
XAxiDma_WriteReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
& ~(Mask & XAXIDMA_IRQ_ALL_MASK))
/*****************************************************************************/
/**
* This function gets the interrupts that are asserted.
*
* @param InstancePtr is the driver instance we are working on
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
*
* @return The bit mask for the interrupts asserted.
*
* @note None
*
*****************************************************************************/
#define XAxiDma_IntrGetIrq(InstancePtr, Direction) \
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET) &\
XAXIDMA_IRQ_ALL_MASK)
/*****************************************************************************/
/**
* This function acknowledges the interrupts that are specified in Mask
*
* @param InstancePtr is the driver instance we are working on
* @param Mask is the mask for the interrupts to be acknowledge
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
*
* @return None
*
* @note None.
*
*****************************************************************************/
#define XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction) \
XAxiDma_WriteReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET, \
(Mask) & XAXIDMA_IRQ_ALL_MASK)
/************************** Function Prototypes ******************************/
/*
* Initialization and control functions in xaxidma.c
*/
XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
XAxiDma_Config *XAxiDma_LookupConfigBaseAddr(UINTPTR Baseaddr);
int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
void XAxiDma_Reset(XAxiDma * InstancePtr);
int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
int XAxiDma_Pause(XAxiDma * InstancePtr);
int XAxiDma_Resume(XAxiDma * InstancePtr);
u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length,
int Direction);
int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select);
int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select);
int XAxiDma_Selftest(XAxiDma * InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xaxidma_bd.h
+696
View File
@@ -0,0 +1,696 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma_bd.h
* @addtogroup axidma_v9_9
* @{
*
* Buffer descriptor (BD) management API.
*
* <b> Buffer Descriptors </b>
*
* A BD defines a DMA transaction (see "Transaction" section in xaxidma.h).
* All accesses to a BD go through this set of API.
*
* The XAxiDma_Bd structure defines a BD. The first XAXIDMA_BD_HW_NUM_BYTES
* are shared between hardware and software.
*
* <b> Actual Transfer Length </b>
*
* The actual transfer length for receive could be smaller than the requested
* transfer length. The hardware sets the actual transfer length in the
* completed BD. The API to retrieve the actual transfer length is
* XAxiDma_GetActualLength().
*
* <b> User IP words </b>
*
* There are 5 user IP words in each BD.
*
* If hardware does not have the StsCntrl stream built in, then these words
* are not usable. Retrieving these words get a NULL pointer and setting
* these words results an error.
*
* <b> Performance </b>
*
* BDs are typically in a non-cached memory space. Reducing the number of
* I/O operations to BDs can improve overall performance of the DMA channel.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 5.00a srt 08/25/11 Changed Cache Macros to have a common API for Zynq
* and Microblaze.
* 6.00a srt 01/24/12 Added APIs to support Multi-Channel DMA:
* XAxiDma_BdSetTId()
* XAxiDma_BdGetTId()
* XAxiDma_BdSetTDest()
* XAxiDma_BdGetTDest()
* XAxiDma_BdSetTUser()
* XAxiDma_BdGetTUser()
* XAxiDma_BdSetARCache()
* XAxiDma_BdGetARCache()
* XAxiDma_BdSetARUser()
* XAxiDma_BdGetARUser()
* XAxiDma_BdSetStride()
* XAxiDma_BdGetStride()
* XAxiDma_BdSetVSize()
* XAxiDma_BdGetVSize()
* - Changed APIs
* XAxiDma_BdGetActualLength(BdPtr, LengthMask)
* XAxiDma_BdGetLength(BdPtr, LengthMask)
* XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr,
* u32 LenBytes, u32 LengthMask)
* 7.01a srt 10/26/12 Changed the logic of MCDMA BD fields Set APIs, to
* clear the field first and set it.
* 8.0 srt 01/29/14 Added support for Micro DMA Mode.
* 9.2 vak 15/04/16 Fixed compilation warnings in axidma driver
* 9.8 rsp 07/11/18 Fix cppcheck portability warnings. CR #1006164
*
* </pre>
*****************************************************************************/
#ifndef XAXIDMA_BD_H_ /* To prevent circular inclusions */
#define XAXIDMA_BD_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xaxidma_hw.h"
#include "xstatus.h"
#include "xdebug.h"
#include "xil_cache.h"
#ifdef __MICROBLAZE__
#include "xenv.h"
#else
#include <string.h>
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* The XAxiDma_Bd is the type for a buffer descriptor (BD).
*/
typedef u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS];
/***************** Macros (Inline Functions) Definitions *********************/
/******************************************************************************
* Define methods to flush and invalidate cache for BDs should they be
* located in cached memory.
*****************************************************************************/
#ifdef __aarch64__
#define XAXIDMA_CACHE_FLUSH(BdPtr)
#define XAXIDMA_CACHE_INVALIDATE(BdPtr)
#else
#define XAXIDMA_CACHE_FLUSH(BdPtr) \
Xil_DCacheFlushRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES)
#define XAXIDMA_CACHE_INVALIDATE(BdPtr) \
Xil_DCacheInvalidateRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES)
#endif
/*****************************************************************************/
/**
*
* Read the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to read
* @param Offset is the word offset to be read
*
* @return The 32-bit value of the field
*
* @note
* C-style signature:
* u32 XAxiDma_BdRead(u32 BaseAddress, u32 Offset)
*
******************************************************************************/
#define XAxiDma_BdRead(BaseAddress, Offset) \
(*(u32 *)((UINTPTR)(BaseAddress) + (u32)(Offset)))
/*****************************************************************************/
/**
*
* Write the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to write
* @param Offset is the word offset to be written
* @param Data is the 32-bit value to write to the field
*
* @return None.
*
* @note
* C-style signature:
* void XAxiDma_BdWrite(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XAxiDma_BdWrite(BaseAddress, Offset, Data) \
(*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data)
/*****************************************************************************/
/**
*
* Write the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to write
* @param Offset is the word offset to be written
* @param Data is the 64-bit value to write to the field
*
* @return None.
*
* @note
* C-style signature:
* void XAxiDma_BdWrite(u64 BaseAddress, u32 RegOffset, u64 Data)
*
******************************************************************************/
#define XAxiDma_BdWrite64(BaseAddress, Offset, Data) \
(*(u64 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u64)(Data)
/*****************************************************************************/
/**
* Zero out BD specific fields. BD fields that are for the BD ring or for the
* system hardware build information are not touched.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdClear(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdClear(BdPtr) \
memset((void *)(((UINTPTR)(BdPtr)) + XAXIDMA_BD_START_CLEAR), 0, \
XAXIDMA_BD_BYTES_TO_CLEAR)
/*****************************************************************************/
/**
* Get the control bits for the BD
*
* @param BdPtr is the BD to operate on
*
* @return The bit mask for the control of the BD
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetCtrl(BdPtr) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) \
& XAXIDMA_BD_CTRL_ALL_MASK)
/*****************************************************************************/
/**
* Retrieve the status of a BD
*
* @param BdPtr is the BD to operate on
*
* @return Word at offset XAXIDMA_BD_DMASR_OFFSET. Use XAXIDMA_BD_STS_***
* values defined in xaxidma_hw.h to interpret the returned value
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetSts(BdPtr) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
XAXIDMA_BD_STS_ALL_MASK)
/*****************************************************************************/
/**
* Retrieve the length field value from the given BD. The returned value is
* the same as what was written with XAxiDma_BdSetLength(). Note that in the
* this value does not reflect the real length of received data.
* See the comments of XAxiDma_BdSetLength() for more details. To obtain the
* actual transfer length, use XAxiDma_BdGetActualLength().
*
* @param BdPtr is the BD to operate on.
* @param LengthMask is the Maximum Transfer Length.
*
* @return The length value set in the BD.
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetLength(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetLength(BdPtr, LengthMask) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) & \
LengthMask)
/*****************************************************************************/
/**
* Set the ID field of the given BD. The ID is an arbitrary piece of data the
* application can associate with a specific BD.
*
* @param BdPtr is the BD to operate on
* @param Id is a 32 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetId(XAxiDma_Bd* BdPtr, void Id)
*
*****************************************************************************/
#define XAxiDma_BdSetId(BdPtr, Id) \
(XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_ID_OFFSET, (UINTPTR)(Id)))
/*****************************************************************************/
/**
* Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetId(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetId(BdPtr) (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_ID_OFFSET))
/*****************************************************************************/
/**
* Get the BD's buffer address
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetBufAddr(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetBufAddr(BdPtr) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_BUFA_OFFSET))
/*****************************************************************************/
/**
* Check whether a BD has completed in hardware. This BD has been submitted
* to hardware. The application can use this function to poll for the
* completion of the BD.
*
* This function may not work if the BD is in cached memory.
*
* @param BdPtr is the BD to check on
*
* @return
* - 0 if not complete
* - XAXIDMA_BD_STS_COMPLETE_MASK if completed, may contain
* XAXIDMA_BD_STS_*_ERR_MASK bits.
*
* @note
* C-style signature:
* int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdHwCompleted(BdPtr) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
XAXIDMA_BD_STS_COMPLETE_MASK)
/*****************************************************************************/
/**
* Get the actual transfer length of a BD. The BD has completed in hw.
*
* This function may not work if the BD is in cached memory.
*
* @param BdPtr is the BD to check on
* @param LengthMask is the Maximum Transfer Length.
*
* @return None
*
* @note
* C-style signature:
* int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetActualLength(BdPtr, LengthMask) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
LengthMask)
/*****************************************************************************/
/**
* Set the TID field of the TX BD.
* Provides a stream identifier and can be used to differentiate between
* multiple streams of data that are being transferred across the same
* interface.
*
* @param BdPtr is the BD to operate on
* @param TId is a 8 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetTId(XAxiDma_Bd* BdPtr, void TId)
*
*****************************************************************************/
#define XAxiDma_BdSetTId(BdPtr, TId) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_TID_FIELD_MASK); \
val |= ((u32)(TId) << XAXIDMA_BD_TID_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetTId(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetTId(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \
XAXIDMA_BD_TID_FIELD_MASK)
/*****************************************************************************/
/**
* Set the TDEST field of the TX BD.
* Provides coarse routing information for the data stream.
*
* @param BdPtr is the BD to operate on
* @param TDest is a 8 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetTDest(XAxiDma_Bd* BdPtr, void TDest)
*
*****************************************************************************/
#define XAxiDma_BdSetTDest(BdPtr, TDest) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_TDEST_FIELD_MASK); \
val |= ((u32)(TDest) << XAXIDMA_BD_TDEST_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the TDest field of the RX BD previously set with i
* XAxiDma_BdSetTDest.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetTDest(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetTDest(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \
XAXIDMA_BD_TDEST_FIELD_MASK)
/*****************************************************************************/
/**
* Set the TUSER field of the TX BD.
* User defined sideband signaling.
*
* @param BdPtr is the BD to operate on
* @param TUser is a 8 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetTUser(XAxiDma_Bd* BdPtr, void TUser)
*
*****************************************************************************/
#define XAxiDma_BdSetTUser(BdPtr, TUser) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_TUSER_FIELD_MASK); \
val |= ((u32)(TUser) << XAXIDMA_BD_TUSER_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the TUSER field of the RX BD previously set with
* XAxiDma_BdSetTUser.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetTUser(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetTUser(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \
XAXIDMA_BD_TUSER_FIELD_MASK)
/*****************************************************************************/
/**
* Set the ARCACHE field of the given BD.
* This signal provides additional information about the cacheable
* characteristics of the transfer.
*
* @param BdPtr is the BD to operate on
* @param ARCache is a 8 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetARCache(XAxiDma_Bd* BdPtr, void ARCache)
*
*****************************************************************************/
#define XAxiDma_BdSetARCache(BdPtr, ARCache) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_ARCACHE_FIELD_MASK); \
val |= ((u32)(ARCache) << XAXIDMA_BD_ARCACHE_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the ARCACHE field of the given BD previously set with
* XAxiDma_BdSetARCache.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetARCache(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetARCache(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) & \
XAXIDMA_BD_ARCACHE_FIELD_MASK)
/*****************************************************************************/
/**
* Set the ARUSER field of the given BD.
* Sideband signals used for user defined information.
*
* @param BdPtr is the BD to operate on
* @param ARUser is a 8 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetARUser(XAxiDma_Bd* BdPtr, void ARUser)
*
*****************************************************************************/
#define XAxiDma_BdSetARUser(BdPtr, ARUser) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_ARUSER_FIELD_MASK); \
val |= ((u32)(ARUser) << XAXIDMA_BD_ARUSER_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the ARUSER field of the given BD previously set with
* XAxiDma_BdSetARUser.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetARUser(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetARUser(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) & \
XAXIDMA_BD_ARUSER_FIELD_MASK)
/*****************************************************************************/
/**
* Set the STRIDE field of the given BD.
* It is the address distance between the first address of successive
* horizontal reads.
*
* @param BdPtr is the BD to operate on
* @param Stride is a 32 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetStride(XAxiDma_Bd* BdPtr, void Stride)
*
*****************************************************************************/
#define XAxiDma_BdSetStride(BdPtr, Stride) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
~XAXIDMA_BD_STRIDE_FIELD_MASK); \
val |= ((u32)(Stride) << XAXIDMA_BD_STRIDE_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the STRIDE field of the given BD previously set with
* XAxiDma_BdSetStride.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetStride(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetStride(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) & \
XAXIDMA_BD_STRIDE_FIELD_MASK)
/*****************************************************************************/
/**
* Set the VSIZE field of the given BD.
* Number of horizontal lines for strided access.
*
* @param BdPtr is the BD to operate on
* @param VSize is a 32 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetVSize(XAxiDma_Bd* BdPtr, void VSize)
*
*****************************************************************************/
#define XAxiDma_BdSetVSize(BdPtr, VSize) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
~XAXIDMA_BD_VSIZE_FIELD_MASK); \
val |= ((u32)(VSize) << XAXIDMA_BD_VSIZE_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the STRIDE field of the given BD previously set with
* XAxiDma_BdSetVSize.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetVSize(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetVSize(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) & \
XAXIDMA_BD_VSIZE_FIELD_MASK)
/*****************************************************************************/
/************************** Function Prototypes ******************************/
int XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr, u32 LenBytes, u32 LengthMask);
u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr);
u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr);
int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word);
u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid);
void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
/* Debug utility
*/
void XAxiDma_DumpBd(XAxiDma_Bd* BdPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xaxidma_bdring.h
+542
View File
@@ -0,0 +1,542 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma_bdring.h
* @addtogroup axidma_v9_9
* @{
*
* This file contains DMA channel related structure and constant definition
* as well as function prototypes. Each DMA channel is managed by a Buffer
* Descriptor ring, and XAxiDma_BdRing is chosen as the symbol prefix used in
* this file. See xaxidma.h for more information on how a BD ring is managed.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA.
* - New API
* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* - Changed APIs
* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* 7.00a srt 06/18/12 All the APIs changed in v6_00_a are reverted back for
* backward compatibility.
* 9.2 vak 15/04/16 Fixed the compilation warnings in axidma driver
* 9.7 rsp 01/11/18 Use UINTPTR instead of u32 for ChanBase CR#976392
*
* </pre>
*
******************************************************************************/
#ifndef XAXIDMA_BDRING_H_ /* prevent circular inclusions */
#define XAXIDMA_BDRING_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xaxidma_bd.h"
#include <stdlib.h>
/************************** Constant Definitions *****************************/
/* State of a DMA channel
*/
#define AXIDMA_CHANNEL_NOT_HALTED 1
#define AXIDMA_CHANNEL_HALTED 2
/* Argument constant to simplify argument setting
*/
#define XAXIDMA_NO_CHANGE 0xFFFFFFFF
#define XAXIDMA_ALL_BDS 0x0FFFFFFF /* 268 Million */
/**************************** Type Definitions *******************************/
/** Container structure for descriptor storage control. If address translation
* is enabled, then all addresses and pointers excluding FirstBdPhysAddr are
* expressed in terms of the virtual address.
*/
typedef struct {
UINTPTR ChanBase; /**< physical base address*/
int IsRxChannel; /**< Is this a receive channel */
volatile int RunState; /**< Whether channel is running */
int HasStsCntrlStrm; /**< Whether has stscntrl stream */
int HasDRE;
int DataWidth;
int Addr_ext;
u32 MaxTransferLen;
UINTPTR FirstBdPhysAddr; /**< Physical address of 1st BD in list */
UINTPTR FirstBdAddr; /**< Virtual address of 1st BD in list */
UINTPTR LastBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
UINTPTR Separation; /**< Number of bytes between the starting
address of adjacent BDs */
XAxiDma_Bd *FreeHead; /**< First BD in the free group */
XAxiDma_Bd *PreHead; /**< First BD in the pre-work group */
XAxiDma_Bd *HwHead; /**< First BD in the work group */
XAxiDma_Bd *HwTail; /**< Last BD in the work group */
XAxiDma_Bd *PostHead; /**< First BD in the post-work group */
XAxiDma_Bd *BdaRestart; /**< BD to load when channel is started */
XAxiDma_Bd *CyclicBd; /**< Useful for Cyclic DMA operations */
int FreeCnt; /**< Number of allocatable BDs in free group */
int PreCnt; /**< Number of BDs in pre-work group */
int HwCnt; /**< Number of BDs in work group */
int PostCnt; /**< Number of BDs in post-work group */
int AllCnt; /**< Total Number of BDs for channel */
int RingIndex; /**< Ring Index */
int Cyclic; /**< Check for cyclic DMA Mode */
} XAxiDma_BdRing;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many BDs will fit
* within the given memory constraints.
*
* The results of this macro can be provided to XAxiDma_BdRingCreate().
*
* @param Alignment specifies what byte alignment the BDs must fall
* on and must be a power of 2 to get an accurate calculation
* (32, 64, 126,...)
* @param Bytes is the number of bytes to be used to store BDs.
*
* @return Number of BDs that can fit in the given memory area
*
* @note
* C-style signature:
* int XAxiDma_BdRingCntCalc(u32 Alignment, u32 Bytes)
* This function is used only when system is configured as SG mode
*
******************************************************************************/
#define XAxiDma_BdRingCntCalc(Alignment, Bytes) \
(uint32_t)((Bytes)/((sizeof(XAxiDma_Bd)+((Alignment)-1))&~((Alignment)-1)))
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many bytes of memory
* are required to contain a given number of BDs at a given alignment.
*
* @param Alignment specifies what byte alignment the BDs must fall on.
* This parameter must be a power of 2 to get an accurate
* calculation (32, 64,128,...)
* @param NumBd is the number of BDs to calculate memory size
* requirements
*
* @return The number of bytes of memory required to create a BD list
* with the given memory constraints.
*
* @note
* C-style signature:
* int XAxiDma_BdRingMemCalc(u32 Alignment, u32 NumBd)
* This function is used only when system is configured as SG mode
*
******************************************************************************/
#define XAxiDma_BdRingMemCalc(Alignment, NumBd) \
(int)((sizeof(XAxiDma_Bd)+((Alignment)-1)) & ~((Alignment)-1))*(NumBd)
/****************************************************************************/
/**
* Return the total number of BDs allocated by this channel with
* XAxiDma_BdRingCreate().
*
* @param RingPtr is the BD ring to operate on.
*
* @return The total number of BDs allocated for this channel.
*
* @note
* C-style signature:
* int XAxiDma_BdRingGetCnt(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
/****************************************************************************/
/**
* Return the number of BDs allocatable with XAxiDma_BdRingAlloc() for pre-
* processing.
*
* @param RingPtr is the BD ring to operate on.
*
* @return The number of BDs currently allocatable.
*
* @note
* C-style signature:
* int XAxiDma_BdRingGetFreeCnt(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
/****************************************************************************/
/**
* Snap shot the latest BD a BD ring is processing.
*
* @param RingPtr is the BD ring to operate on.
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingSnapShotCurrBd(RingPtr) \
{ \
if (!RingPtr->IsRxChannel) { \
(RingPtr)->BdaRestart = \
(XAxiDma_Bd *)(UINTPTR)XAxiDma_ReadReg( \
(RingPtr)->ChanBase, \
XAXIDMA_CDESC_OFFSET); \
} else { \
if (!RingPtr->RingIndex) { \
(RingPtr)->BdaRestart = \
(XAxiDma_Bd *)(UINTPTR)XAxiDma_ReadReg( \
(RingPtr)->ChanBase, \
XAXIDMA_CDESC_OFFSET); \
} else { \
(RingPtr)->BdaRestart = \
(XAxiDma_Bd *)(UINTPTR)XAxiDma_ReadReg( \
(RingPtr)->ChanBase, \
(XAXIDMA_RX_CDESC0_OFFSET + \
(RingPtr->RingIndex - 1) * \
XAXIDMA_RX_NDESC_OFFSET)); \
} \
} \
}
/****************************************************************************/
/**
* Get the BD a BD ring is processing.
*
* @param RingPtr is the BD ring to operate on.
*
* @return The current BD that the BD ring is working on
*
* @note
* C-style signature:
* XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetCurrBd(RingPtr) \
(XAxiDma_Bd *)XAxiDma_ReadReg((RingPtr)->ChanBase, \
XAXIDMA_CDESC_OFFSET) \
/****************************************************************************/
/**
* Return the next BD in the ring.
*
* @param RingPtr is the BD ring to operate on.
* @param BdPtr is the current BD.
*
* @return The next BD in the ring relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XAxiDma_Bd *XAxiDma_BdRingNext(XAxiDma_BdRing* RingPtr,
* XAxiDma_Bd *BdPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingNext(RingPtr, BdPtr) \
(((UINTPTR)(BdPtr) >= (RingPtr)->LastBdAddr) ? \
(UINTPTR)(RingPtr)->FirstBdAddr : \
(UINTPTR)((UINTPTR)(BdPtr) + (RingPtr)->Separation))
/****************************************************************************/
/**
* Return the previous BD in the ring.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the current BD.
*
* @return The previous BD in the ring relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XAxiDma_Bd *XAxiDma_BdRingPrev(XAxiDma_BdRing* RingPtr,
* XAxiDma_Bd *BdPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingPrev(RingPtr, BdPtr) \
(((u32)(BdPtr) <= (RingPtr)->FirstBdAddr) ? \
(XAxiDma_Bd*)(RingPtr)->LastBdAddr : \
(XAxiDma_Bd*)((u32)(BdPtr) - (RingPtr)->Separation))
/****************************************************************************/
/**
* Retrieve the contents of the channel status register
*
* @param RingPtr is the channel instance to operate on.
*
* @return Current contents of status register
*
* @note
* C-style signature:
* u32 XAxiDma_BdRingGetSr(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetSr(RingPtr) \
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET)
/****************************************************************************/
/**
* Get error bits of a DMA channel
*
* @param RingPtr is the channel instance to operate on.
*
* @return Rrror bits in the status register, they should be interpreted
* with XAXIDMA_ERR_*_MASK defined in xaxidma_hw.h
*
* @note
* C-style signature:
* u32 XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetError(RingPtr) \
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_ERR_ALL_MASK)
/****************************************************************************/
/**
* Check whether a DMA channel is started, meaning the channel is not halted.
*
* @param RingPtr is the channel instance to operate on.
*
* @return
* - 1 if channel is started
* - 0 otherwise
*
* @note
* C-style signature:
* int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr)
*
*****************************************************************************/
#define XAxiDma_BdRingHwIsStarted(RingPtr) \
((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_HALTED_MASK) ? FALSE : TRUE)
/****************************************************************************/
/**
* Check if the current DMA channel is busy with a DMA operation.
*
* @param RingPtr is the channel instance to operate on.
*
* @return
* - 1 if the DMA is busy.
* - 0 otherwise
*
* @note
* C-style signature:
* int XAxiDma_BdRingBusy(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingBusy(RingPtr) \
(XAxiDma_BdRingHwIsStarted(RingPtr) && \
((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_IDLE_MASK) ? FALSE : TRUE))
/****************************************************************************/
/**
* Set interrupt enable bits for a channel. This operation will modify the
* XAXIDMA_CR_OFFSET register.
*
* @param RingPtr is the channel instance to operate on.
* @param Mask consists of the interrupt signals to enable.Bits not
* specified in the mask are not affected.
*
* @note
* C-style signature:
* void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingIntEnable(RingPtr, Mask) \
(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
| ((Mask) & XAXIDMA_IRQ_ALL_MASK)))
/****************************************************************************/
/**
* Get enabled interrupts of a channel. It is in XAXIDMA_CR_OFFSET register.
*
* @param RingPtr is the channel instance to operate on.
* @return Enabled interrupts of a channel. Use XAXIDMA_IRQ_* defined in
* xaxidma_hw.h to interpret this returned value.
*
* @note
* C-style signature:
* u32 XAxiDma_BdRingIntGetEnabled(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingIntGetEnabled(RingPtr) \
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
& XAXIDMA_IRQ_ALL_MASK)
/****************************************************************************/
/**
* Clear interrupt enable bits for a channel. It modifies the
* XAXIDMA_CR_OFFSET register.
*
* @param RingPtr is the channel instance to operate on.
* @param Mask consists of the interrupt signals to disable.Bits not
* specified in the Mask are not affected.
*
* @note
* C-style signature:
* void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr,
* u32 Mask)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingIntDisable(RingPtr, Mask) \
(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) & \
~((Mask) & XAXIDMA_IRQ_ALL_MASK)))
/****************************************************************************/
/**
* Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET. This
* operation can be used to see which interrupts are pending.
*
* @param RingPtr is the channel instance to operate on.
*
* @return Current contents of the IRQ_OFFSET register. Use
* XAXIDMA_IRQ_*** values defined in xaxidma_hw.h to interpret
* the returned value.
*
* @note
* C-style signature:
* u32 XAxiDma_BdRingGetIrq(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetIrq(RingPtr) \
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_IRQ_ALL_MASK)
/****************************************************************************/
/**
* Acknowledge asserted interrupts. It modifies XAXIDMA_SR_OFFSET register.
* A mask bit set for an unasserted interrupt has no effect.
*
* @param RingPtr is the channel instance to operate on.
* @param Mask are the interrupt signals to acknowledge
*
* @note
* C-style signature:
* void XAxiDma_BdRingAckIrq(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingAckIrq(RingPtr, Mask) \
XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET,\
(Mask) & XAXIDMA_IRQ_ALL_MASK)
/****************************************************************************/
/**
* Enable Cyclic DMA Mode.
*
* @param RingPtr is the channel instance to operate on.
*
* @note
* C-style signature:
* void XAxiDma_BdRingEnableCyclicDMA(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingEnableCyclicDMA(RingPtr) \
(RingPtr->Cyclic = 1)
/****************************************************************************/
/************************* Function Prototypes ******************************/
/*
* Descriptor ring functions xaxidma_bdring.c
*/
int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr);
int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr);
u32 XAxiDma_BdRingCreate(XAxiDma_BdRing * RingPtr, UINTPTR PhysAddr,
UINTPTR VirtAddr, u32 Alignment, int BdCount);
int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr);
int XAxiDma_BdRingAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
XAxiDma_Bd ** BdSetPtr);
int XAxiDma_BdRingUnAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
XAxiDma_Bd * BdSetPtr);
int XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, int NumBd,
XAxiDma_Bd * BdSetPtr);
int XAxiDma_BdRingFromHw(XAxiDma_BdRing * RingPtr, int BdLimit,
XAxiDma_Bd ** BdSetPtr);
int XAxiDma_BdRingFree(XAxiDma_BdRing * RingPtr, int NumBd,
XAxiDma_Bd * BdSetPtr);
int XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr);
int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter, u32 Timer);
void XAxiDma_BdRingGetCoalesce(XAxiDma_BdRing * RingPtr,
u32 *CounterPtr, u32 *TimerPtr);
/* The following functions are for debug only
*/
int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr);
void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xaxidma_hw.h
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/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xaxidma_hw.h
* @addtogroup axidma_v9_9
* @{
*
* Hardware definition file. It defines the register interface and Buffer
* Descriptor (BD) definitions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 4.00a rkv 02/22/11 Added support for simple DMA mode
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA mode
* 8.0 srt 01/29/14 Added support for Micro DMA Mode and Cyclic mode of
* operations.
* 9.7 rsp 04/24/18 Added support for 64MB data transfer.Instead of #define
* read max buffer width from IP config.
*
* </pre>
*
*****************************************************************************/
#ifndef XAXIDMA_HW_H_ /* prevent circular inclusions */
#define XAXIDMA_HW_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name DMA Transfer Direction
* @{
*/
#define XAXIDMA_DMA_TO_DEVICE 0x00
#define XAXIDMA_DEVICE_TO_DMA 0x01
/** @name Buffer Descriptor Alignment
* @{
*/
#define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40 /**< Minimum byte alignment
requirement for descriptors to
satisfy both hardware/software
needs */
/*@}*/
/** @name Micro DMA Buffer Address Alignment
* @{
*/
#define XAXIDMA_MICROMODE_MIN_BUF_ALIGN 0xFFF /**< Minimum byte alignment
requirement for buffer address
in Micro DMA mode */
/*@}*/
/** @name Maximum transfer length
* This is determined by hardware
* @{
*/
#define XAXIDMA_MCHAN_MAX_TRANSFER_LEN 0x00FFFF /* Max length MCDMA
hw supports */
/*@}*/
/* Register offset definitions. Register accesses are 32-bit.
*/
/** @name Device registers
* Register sets on TX and RX channels are identical
* @{
*/
#define XAXIDMA_TX_OFFSET 0x00000000 /**< TX channel registers base
* offset */
#define XAXIDMA_RX_OFFSET 0x00000030 /**< RX channel registers base
* offset */
/* This set of registers are applicable for both channels. Add
* XAXIDMA_TX_OFFSET to get to TX channel, and XAXIDMA_RX_OFFSET to get to RX
* channel
*/
#define XAXIDMA_CR_OFFSET 0x00000000 /**< Channel control */
#define XAXIDMA_SR_OFFSET 0x00000004 /**< Status */
#define XAXIDMA_CDESC_OFFSET 0x00000008 /**< Current descriptor pointer */
#define XAXIDMA_CDESC_MSB_OFFSET 0x0000000C /**< Current descriptor pointer */
#define XAXIDMA_TDESC_OFFSET 0x00000010 /**< Tail descriptor pointer */
#define XAXIDMA_TDESC_MSB_OFFSET 0x00000014 /**< Tail descriptor pointer */
#define XAXIDMA_SRCADDR_OFFSET 0x00000018 /**< Simple mode source address
pointer */
#define XAXIDMA_SRCADDR_MSB_OFFSET 0x0000001C /**< Simple mode source address
pointer */
#define XAXIDMA_DESTADDR_OFFSET 0x00000018 /**< Simple mode destination address pointer */
#define XAXIDMA_DESTADDR_MSB_OFFSET 0x0000001C /**< Simple mode destination address pointer */
#define XAXIDMA_BUFFLEN_OFFSET 0x00000028 /**< Tail descriptor pointer */
#define XAXIDMA_SGCTL_OFFSET 0x0000002c /**< SG Control Register */
/** Multi-Channel DMA Descriptor Offsets **/
#define XAXIDMA_RX_CDESC0_OFFSET 0x00000040 /**< Rx Current Descriptor 0 */
#define XAXIDMA_RX_CDESC0_MSB_OFFSET 0x00000044 /**< Rx Current Descriptor 0 */
#define XAXIDMA_RX_TDESC0_OFFSET 0x00000048 /**< Rx Tail Descriptor 0 */
#define XAXIDMA_RX_TDESC0_MSB_OFFSET 0x0000004C /**< Rx Tail Descriptor 0 */
#define XAXIDMA_RX_NDESC_OFFSET 0x00000020 /**< Rx Next Descriptor Offset */
/*@}*/
/** @name Bitmasks of XAXIDMA_CR_OFFSET register
* @{
*/
#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /**< Start/stop DMA channel */
#define XAXIDMA_CR_RESET_MASK 0x00000004 /**< Reset DMA engine */
#define XAXIDMA_CR_KEYHOLE_MASK 0x00000008 /**< Keyhole feature */
#define XAXIDMA_CR_CYCLIC_MASK 0x00000010 /**< Cyclic Mode */
/*@}*/
/** @name Bitmasks of XAXIDMA_SR_OFFSET register
*
* This register reports status of a DMA channel, including
* run/stop/idle state, errors, and interrupts (note that interrupt
* masks are shared with XAXIDMA_CR_OFFSET register, and are defined
* in the _IRQ_ section.
*
* The interrupt coalescing threshold value and delay counter value are
* also shared with XAXIDMA_CR_OFFSET register, and are defined in a
* later section.
* @{
*/
#define XAXIDMA_HALTED_MASK 0x00000001 /**< DMA channel halted */
#define XAXIDMA_IDLE_MASK 0x00000002 /**< DMA channel idle */
#define XAXIDMA_ERR_INTERNAL_MASK 0x00000010 /**< Datamover internal
* err */
#define XAXIDMA_ERR_SLAVE_MASK 0x00000020 /**< Datamover slave err */
#define XAXIDMA_ERR_DECODE_MASK 0x00000040 /**< Datamover decode
* err */
#define XAXIDMA_ERR_SG_INT_MASK 0x00000100 /**< SG internal err */
#define XAXIDMA_ERR_SG_SLV_MASK 0x00000200 /**< SG slave err */
#define XAXIDMA_ERR_SG_DEC_MASK 0x00000400 /**< SG decode err */
#define XAXIDMA_ERR_ALL_MASK 0x00000770 /**< All errors */
/** @name Bitmask for interrupts
* These masks are shared by XAXIDMA_CR_OFFSET register and
* XAXIDMA_SR_OFFSET register
* @{
*/
#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /**< Completion intr */
#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /**< Delay interrupt */
#define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /**< Error interrupt */
#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /**< All interrupts */
/*@}*/
/** @name Bitmask and shift for delay and coalesce
* These masks are shared by XAXIDMA_CR_OFFSET register and
* XAXIDMA_SR_OFFSET register
* @{
*/
#define XAXIDMA_DELAY_MASK 0xFF000000 /**< Delay timeout
* counter */
#define XAXIDMA_COALESCE_MASK 0x00FF0000 /**< Coalesce counter */
#define XAXIDMA_DELAY_SHIFT 24
#define XAXIDMA_COALESCE_SHIFT 16
/*@}*/
/* Buffer Descriptor (BD) definitions
*/
/** @name Buffer Descriptor offsets
* USR* fields are defined by higher level IP.
* setup for EMAC type devices. The first 13 words are used by hardware.
* All words after the 13rd word are for software use only.
* @{
*/
#define XAXIDMA_BD_NDESC_OFFSET 0x00 /**< Next descriptor pointer */
#define XAXIDMA_BD_NDESC_MSB_OFFSET 0x04 /**< Next descriptor pointer */
#define XAXIDMA_BD_BUFA_OFFSET 0x08 /**< Buffer address */
#define XAXIDMA_BD_BUFA_MSB_OFFSET 0x0C /**< Buffer address */
#define XAXIDMA_BD_MCCTL_OFFSET 0x10 /**< Multichannel Control Fields */
#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET 0x14 /**< 2D Transfer Sizes */
#define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /**< Control/buffer length */
#define XAXIDMA_BD_STS_OFFSET 0x1C /**< Status */
#define XAXIDMA_BD_USR0_OFFSET 0x20 /**< User IP specific word0 */
#define XAXIDMA_BD_USR1_OFFSET 0x24 /**< User IP specific word1 */
#define XAXIDMA_BD_USR2_OFFSET 0x28 /**< User IP specific word2 */
#define XAXIDMA_BD_USR3_OFFSET 0x2C /**< User IP specific word3 */
#define XAXIDMA_BD_USR4_OFFSET 0x30 /**< User IP specific word4 */
#define XAXIDMA_BD_ID_OFFSET 0x34 /**< Sw ID */
#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /**< Whether has stscntrl strm */
#define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /**< Whether has DRE */
#define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /**< Whether has DRE mask */
#define XAXIDMA_BD_WORDLEN_MASK 0xFF /**< Whether has DRE mask */
#define XAXIDMA_BD_HAS_DRE_SHIFT 8 /**< Whether has DRE shift */
#define XAXIDMA_BD_WORDLEN_SHIFT 0 /**< Whether has DRE shift */
#define XAXIDMA_BD_START_CLEAR 8 /**< Offset to start clear */
#define XAXIDMA_BD_BYTES_TO_CLEAR 48 /**< BD specific bytes to be
* cleared */
#define XAXIDMA_BD_NUM_WORDS 16U /**< Total number of words for
* one BD*/
#define XAXIDMA_BD_HW_NUM_BYTES 52 /**< Number of bytes hw used */
/* The offset of the last app word.
*/
#define XAXIDMA_LAST_APPWORD 4
/*@}*/
#define XAXIDMA_DESC_LSB_MASK (0xFFFFFFC0U) /**< LSB Address mask */
/** @name Bitmasks of XAXIDMA_BD_CTRL_OFFSET register
* @{
*/
#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /**< First tx packet */
#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /**< Last tx packet */
#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /**< All control bits */
/*@}*/
/** @name Bitmasks of XAXIDMA_BD_STS_OFFSET register
* @{
*/
#define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /**< Completed */
#define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /**< Decode error */
#define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /**< Slave error */
#define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /**< Internal err */
#define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /**< All errors */
#define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /**< First rx pkt */
#define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /**< Last rx pkt */
#define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /**< All status bits */
/*@}*/
/** @name Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register
* @{
*/
#define XAXIDMA_BD_TDEST_FIELD_MASK 0x0000000F
#define XAXIDMA_BD_TID_FIELD_MASK 0x00000F00
#define XAXIDMA_BD_TUSER_FIELD_MASK 0x000F0000
#define XAXIDMA_BD_ARCACHE_FIELD_MASK 0x0F000000
#define XAXIDMA_BD_ARUSER_FIELD_MASK 0xF0000000
#define XAXIDMA_BD_TDEST_FIELD_SHIFT 0
#define XAXIDMA_BD_TID_FIELD_SHIFT 8
#define XAXIDMA_BD_TUSER_FIELD_SHIFT 16
#define XAXIDMA_BD_ARCACHE_FIELD_SHIFT 24
#define XAXIDMA_BD_ARUSER_FIELD_SHIFT 28
/*@}*/
/** @name Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register
* @{
*/
#define XAXIDMA_BD_STRIDE_FIELD_MASK 0x0000FFFF
#define XAXIDMA_BD_VSIZE_FIELD_MASK 0xFFF80000
#define XAXIDMA_BD_STRIDE_FIELD_SHIFT 0
#define XAXIDMA_BD_VSIZE_FIELD_SHIFT 19
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XAxiDma_In32 Xil_In32
#define XAxiDma_Out32 Xil_Out32
/*****************************************************************************/
/**
*
* Read the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define XAxiDma_ReadReg(BaseAddress, RegOffset) \
XAxiDma_In32((BaseAddress) + (RegOffset))
/*****************************************************************************/
/**
*
* Write the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data) \
XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))
#ifdef __cplusplus
}
#endif
#endif
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xaxidma_porting_guide.h
+250
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/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma_porting_guide.h
* @addtogroup axidma_v9_9
* @{
*
* This is a guide on how to move from using the xlldma driver to use xaxidma
* driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 4.00a rkv 02/22/11 Added support for simple DMA mode
* 6.00a srt 03/27/12 Added support for MCDMA mode
* 7.00a srt 06/18/12 API calls are reverted back for backward compatibility.
*
* </pre>
*
* <b>Overview</b>
*
* The API for xaxidma driver is similar to xlldma driver. The prefix for the
* API functions and structures is XAxiDma_ for the xaxidma driver.
*
* Due to hardware feature changes, signatures of some API functions are a
* little bit different from the xlldma API functions.
*
* We present API functions:
* - That only have prefix changes
* - That have different return type
* - That are new API functions
* - That have been removed
*
* Note that data structures have different prefix of XAxiDma_. Those API
* functions, that have data structures with prefix change, are considered as
* prefix change.
*
* <b>API Functions That Only Have Prefix Changes</b>
*
* <pre>
* xlldma driver | xaxidma driver (upto v5_00_a)
* -----------------------------------------------------------------------
* XLlDma_Reset(...) | XAxiDma_Reset(...)
* XLlDma_BdRingSnapShotCurrBd(...)| XAxiDma_BdRingSnapShotCurrBd(...)
* XLlDma_BdRingNext(...) | XAxiDma_BdRingNext(...)
* XLlDma_BdRingPrev(...) | XAxiDma_BdRingPrev(...)
* XLlDma_BdRingGetSr(...) | XAxiDma_BdRingGetSr(...)
* XLlDma_BdRingBusy(...) | XAxiDma_BdRingBusy(...)
* XLlDma_BdRingIntEnable(...) | XAxiDma_BdRingIntEnable(...)
* XLlDma_BdRingIntDisable(...) | XAxiDma_BdRingIntDisable(...)
* XLlDma_BdRingIntGetEnabled(...) | XAxiDma_BdRingIntGetEnabled(...)
* XLlDma_BdRingGetIrq(...) | XAxiDma_BdRingGetIrq(...)
* XLlDma_BdRingAckIrq(...) | XAxiDma_BdRingAckIrq(...)
* XLlDma_BdRingCreate(...) | XAxiDma_BdRingCreate(...)
* XLlDma_BdRingClone(...) | XAxiDma_BdRingClone(...)
* XLlDma_BdRingAlloc(...) | XAxiDma_BdRingAlloc(...)
* XLlDma_BdRingUnAlloc(...) | XAxiDma_BdRingUnAlloc(...)
* XLlDma_BdRingToHw(...) | XAxiDma_BdRingToHw(...)
* XLlDma_BdRingFromHw(...) | XAxiDma_BdRingFromHw(...)
* XLlDma_BdRingFree(...) | XAxiDma_BdRingFree(...)
* XLlDma_BdRingStart(...) | XAxiDma_BdRingStart(...)
* XLlDma_BdRingCheck(...) | XAxiDma_BdRingCheck(...)
* XLlDma_BdRingSetCoalesce(...) | XAxiDma_BdRingSetCoalesce(...)
* XLlDma_BdRingGetCoalesce(...) | XAxiDma_BdRingGetCoalesce(...)
* XLlDma_BdRead(...) | XAxiDma_BdRead(...)
* XLlDma_BdWrite(...) | XAxiDma_BdWrite(...)
* XLlDma_BdClear(...) | XAxiDma_BdClear(...)
* XLlDma_BdSetId(...) | XAxiDma_BdSetId(...)
* XLlDma_BdGetId(...) | XAxiDma_BdGetId(...)
* XLlDma_BdGetLength(...) | XAxiDma_BdGetLength(...)
* XLlDma_BdGetBufAddr(...) | XAxiDma_BdGetBufAddr(...)
*
*</pre>
*
* <b>API Functions That Have Different Return Type</b>
*
* Due to possible hardware failures, The caller should check the return value
* of the following functions.
*
* <pre>
* xlldma driver | xaxidma driver
* -----------------------------------------------------------------------
* void XLlDma_Pause(...) | int XAxiDma_Pause(...)
* void XLlDma_Resume(...) | int XAxiDma_Resume(...)
* </pre>
*
* The following functions have return type changed:
*
* <pre>
* xlldma driver | xaxidma driver
* -----------------------------------------------------------------------
* XLlDma_BdRing XLlDma_GetRxRing(...)| XAxiDma_BdRing * XAxiDma_GetRxRing(...)
* XLlDma_BdRing XLlDma_GetTxRing(...)| XAxiDma_BdRing * XAxiDma_GetTxRing(...)
* u32 XLlDma_BdRingMemCalc(...) | int XAxiDma_BdRingMemCalc(...)
* u32 XLlDma_BdRingCntCalc(...) | int XAxiDma_BdRingCntCalc(...)
* u32 XLlDma_BdRingGetCnt(...) | int XAxiDma_BdRingGetCnt(...)
* u32 XLlDma_BdRingGetFreeCnt(...) | int XAxiDma_BdRingGetFreeCnt(...)
* void XLlDma_BdSetLength(...) | int XAxiDma_BdSetLength(...)
* void XLlDma_BdSetBufAddr(...) | int XAxiDma_BdSetBufAddr(...)
*</pre>
*
* <b>API Functions That Are New API Functions</b>
*
* Now that the AXI DMA core is a standalone core, some new API are intrduced.
* Some other functions are added due to hardware interface change, so to
* replace old API functions.
*
* - XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
* - int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
* - int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
* - XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr);
* - int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr);
* - void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr);
* - int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr);
* - void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
* - u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr);
* - u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr);
* - int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr);
* - int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr);
* - int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word);
* - u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid);
*
* <b>API Functions That Have Been Removed</b>
*
* Please see individual function comments for how to replace the removed API
* function with new API functions.
*
* - void XLlDma_Initialize(XLlDma * InstancePtr, u32 BaseAddress).
* This function is replaced by XAxiDma_LookupConfig()/XAxiDma_CfgInitialize()
*
* - u32 XLlDma_BdRingGetCr(XLlDma_BdRing* RingPtr).
* This is replaced by XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)
*
* - u32 XLlDma_BdRingSetCr(XLlDma_BdRing* RingPtr, u32 Data).
* This function is covered by other API functions:
* - void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)
* - void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr, u32 Mask)
* - int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter,
* u32 Timer)
*
* - u32 XLlDma_BdSetStsCtrl(XLlDma_Bd* BdPtr, u32 Data).
* Replaced by XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
*
* - u32 XLlDma_BdGetStsCtrl(XLlDma_Bd* BdPtr).
* Replaced by XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr) and
* XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr).
*
* <b>API Functions That Have Been Added to support simple DMA mode</b>
*
* - u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
* - int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, int Length,
* int Direction);
* - XAxiDma_HasSg(InstancePtr);
* - XAxiDma_IntrEnable(InstancePtr,Mask,Direction);
* - XAxiDma_IntrGetEnabled(InstancePtr, Direction);
* - XAxiDma_IntrDisable(InstancePtr, Mask, Direction);
* - XAxiDma_IntrGetIrq(InstancePtr, Direction);
* - XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction);
*
* <b> For xaxidma driver v6_00_a Multiple Channel Support
* ---------------------------------------------------
* This driver supports Multi-channel mode and accordingly some APIs are
* changed to index multiple channels. Few new APIs are added.
* - Changed APIs
* * XAxiDma_GetRxRing(InstancePtr, RingIndex)
* * XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
* u32 BuffAddr, u32 Length,
* int Direction, int RingIndex)
* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
* u32 LenBytes, u32 LengthMask)
* * XAxiDma_BdGetActualLength(BdPtr, LengthMask)
* * XAxiDma_BdGetLength(BdPtr, LengthMask)
*
* - New APIs
* * XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
* int Direction, int Select)
* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdSetTId()
* * XAxiDma_BdGetTId()
* * XAxiDma_BdSetTDest()
* * XAxiDma_BdGetTDest()
* * XAxiDma_BdSetTUser()
* * XAxiDma_BdGetTUser()
* * XAxiDma_BdSetARCache()
* * XAxiDma_BdGetARCache()
* * XAxiDma_BdSetARUser()
* * XAxiDma_BdGetARUser()
* * XAxiDma_BdSetStride()
* * XAxiDma_BdGetStride()
* * XAxiDma_BdSetVSize()
* * XAxiDma_BdGetVSize()
* <b> For xaxidma driver v7_00_a
* ---------------------------------------------------
* - New API
* * XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
*
* - Changed APIs
* All the APIs changed in v6_00_a are reverted back for backward
* compatibility.
*</pre>
*
******************************************************************************/
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xbasic_types.h
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/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.h
*
*
* @note Dummy File for backwards compatibility
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
* 7.0 aru 02/06/19 Included stdint.h and stddef.h
* </pre>
*
******************************************************************************/
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
#define XBASIC_TYPES_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
/** @name Legacy types
* Deprecated legacy types.
* @{
*/
typedef uint8_t Xuint8; /**< unsigned 8-bit */
typedef char Xint8; /**< signed 8-bit */
typedef uint16_t Xuint16; /**< unsigned 16-bit */
typedef short Xint16; /**< signed 16-bit */
typedef uint32_t Xuint32; /**< unsigned 32-bit */
typedef long Xint32; /**< signed 32-bit */
typedef float Xfloat32; /**< 32-bit floating point */
typedef double Xfloat64; /**< 64-bit double precision FP */
typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
#if !defined __XUINT64__
typedef struct
{
Xuint32 Upper;
Xuint32 Lower;
} Xuint64;
#endif
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XIL_TYPES_H
typedef Xuint32 u32;
typedef Xuint16 u16;
typedef Xuint8 u8;
#endif
#else
#include <linux/types.h>
#endif
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
/*
* Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
* Please use NULL, TRUE and FALSE
*/
#define XNULL NULL
#define XTRUE TRUE
#define XFALSE FALSE
/*
* This file is deprecated and users
* should use xil_types.h and xil_assert.h\n\r
*/
#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
#warning Please refer the Standalone BSP UG647 for further details
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
datalink814_sp/bsp/microblaze_ps/include/xbram.h
+223
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/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram.h
* @addtogroup bram_v4_2
* @{
* @details
*
* If ECC is not enabled, this driver exists only to allow the tools to
* create a memory test application and to populate xparameters.h with memory
* range constants. In this case there is no source code.
*
* If ECC is enabled, this file contains the software API definition of the
* Xilinx BRAM Interface Controller (XBram) device driver.
*
* The Xilinx BRAM controller is a soft IP core designed for Xilinx
* FPGAs and contains the following general features:
* - LMB v2.0 bus interfaces with byte enable support
* - Used in conjunction with bram_block peripheral to provide fast BRAM
* memory solution for MicroBlaze ILMB and DLMB ports
* - Supports byte, half-word, and word transfers
* - Supports optional BRAM error correction and detection.
*
* The driver provides interrupt management functions. Implementation of
* interrupt handlers is left to the user. Refer to the provided interrupt
* example in the examples directory for details.
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* <b>Initialization & Configuration</b>
*
* The XBram_Config structure is used by the driver to configure
* itself. This configuration structure is typically created by the tool-chain
* based on HW build properties.
*
* To support multiple runtime loading and initialization strategies employed
* by various operating systems, the driver instance can be initialized as
* follows:
*
* - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
* Uses a configuration structure provided by the caller. If running in a
* system with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* @note
*
* This API utilizes 32 bit I/O to the BRAM registers. With less
* than 32 bits, the unused bits from registers are read as zero and written as
* don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 3.00a sa 05/11/10 Added ECC support
* 3.01a sa 01/13/12 Changed Selftest API from
* XBram_SelfTest(XBram *InstancePtr) to
* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
* fixed a problem with interrupt generation for CR 639274
* Modified Selftest example to return XST_SUCCESS when
* ECC is not enabled and return XST_FAILURE when ECC is
* enabled and Control Base Address is zero (CR 636581)
* Modified Selftest to use correct CorrectableCounterBits
* for CR 635655
* Updated to check CorrectableFailingDataRegs in the case
* of LMB BRAM.
* Added CorrectableFailingDataRegs and
* UncorrectableFailingDataRegs to the config structure to
* distinguish between AXI BRAM and LMB BRAM.
* These registers are not present in the current version of
* the AXI BRAM Controller.
* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
* 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
* to support both xps and vivado designs.
* 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
* when ecc is disabled cr:705002.
* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
* flush the Cache after writing to BRAM in InjectErrors
* API(CR #719011)
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XBram_CfgInitialize API.
* ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 4.2 ms 04/18/17 Modified tcl file to add suffix U for all macro
* definitions of bram in xparameters.h
* ms 08/07/17 Fixed compilation warnings in xbram_sinit.c
* 4.3 aru 03/23/19 Used UINTPTR instead of u32 for MemBaseAddress and
* MemHighAddress.
* </pre>
*****************************************************************************/
#ifndef XBRAM_H /* prevent circular inclusions */
#define XBRAM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xbram_hw.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 DataWidth; /**< BRAM data width */
int EccPresent; /**< Is ECC supported in H/W */
int FaultInjectionPresent; /**< Is Fault Injection
* supported in H/W */
int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
* supported in H/W */
int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
* Registers supported in H/W */
int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
* Registers supported in H/W */
int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
* Registers supported in H/W */
int EccStatusInterruptPresent; /**< Are ECC status and interrupts
* supported in H/W */
int CorrectableCounterBits; /**< Number of bits in the
* Correctable Error Counter */
int EccOnOffRegister; /**< Is ECC on/off register supported
* in h/w */
int EccOnOffResetValue; /**< Reset value of the ECC on/off
* register in h/w */
int WriteAccess; /**< Is write access enabled in
* h/w */
UINTPTR MemBaseAddress; /**< Device memory base address */
UINTPTR MemHighAddress; /**< Device memory high address */
UINTPTR CtrlBaseAddress; /**< Device register base address.*/
UINTPTR CtrlHighAddress; /**< Device register base address.*/
} XBram_Config;
/**
* The XBram driver instance data. The user is required to
* allocate a variable of this type for every BRAM device in the
* system. A pointer to a variable of this type is then passed to the driver
* API functions.
*/
typedef struct {
XBram_Config Config; /* BRAM config structure */
u32 IsReady; /* Device is initialized and ready */
} XBram;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
/*
* Functions in xbram_sinit.c
*/
XBram_Config *XBram_LookupConfig(u16 DeviceId);
/*
* Functions implemented in xbram.c
*/
int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
UINTPTR EffectiveAddr);
/*
* Functions implemented in xbram_selftest.c
*/
int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
/*
* Functions implemented in xbram_intr.c
*/
void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
u32 XBram_InterruptGetStatus(XBram *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xbram_hw.h
+405
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/******************************************************************************
*
* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbram_hw.h
* @addtogroup bram_v4_2
* @{
*
* This header file contains identifiers and driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 24/11/10 First release
* </pre>
*
******************************************************************************/
#ifndef XBRAM_HW_H /* prevent circular inclusions */
#define XBRAM_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Registers
*
* Register offsets for this device.
* @{
*/
#define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
#define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
#define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
#define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
#define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
* data Register, 31-0 */
#define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
* data Register, 63-32 */
#define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
* data Register, 95-64 */
#define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
* data Register, 127-96 */
#define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
* data Register, 159-128 */
#define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
* data Register, 191-160 */
#define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
* data Register, 223-192 */
#define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
* data Register, 255-224 */
#define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
* data Register, 287-256 */
#define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
* data Register, 319-288 */
#define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
* data Register, 351-320 */
#define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
* data Register, 383-352 */
#define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
* data Register, 415-384 */
#define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
* data Register, 447-416 */
#define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
* data Register, 479-448 */
#define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
* data Register, 511-480 */
#define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
* data Register, 543-512 */
#define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
* data Register, 575-544 */
#define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
* data Register, 607-576 */
#define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
* data Register, 639-608 */
#define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
* data Register, 671-640 */
#define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
* data Register, 703-672 */
#define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
* data Register, 735-704 */
#define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
* data Register, 767-736 */
#define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
* data Register, 799-768 */
#define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
* data Register, 831-800 */
#define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
* data Register, 863-832 */
#define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
* data Register, 895-864 */
#define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
* data Register, 927-896 */
#define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
* data Register, 959-928 */
#define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
* data Register, 991-960 */
#define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
* data Register, 1023-992 */
#define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
* ECC Register, 31-0 */
#define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
* ECC Register, 63-32 */
#define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
* ECC Register, 95-64 */
#define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
* ECC Register, 127-96 */
#define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
* ECC Register, 159-128 */
#define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
* ECC Register, 191-160 */
#define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
* ECC Register, 223-192 */
#define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
* ECC Register, 255-224 */
#define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
* address Register 31-0 */
#define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
* address Register 63-32 */
#define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
* data Register, 31-0 */
#define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
* data Register, 63-32 */
#define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
* data Register, 95-64 */
#define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
* data Register, 127-96 */
#define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
* data Register, 159-128 */
#define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
* data Register, 191-160 */
#define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
* data Register, 223-192 */
#define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
* data Register, 255-224 */
#define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
* data Register, 287-256 */
#define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
* data Register, 319-288 */
#define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
* data Register, 351-320 */
#define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
* data Register, 383-352 */
#define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
* data Register, 415-384 */
#define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
* data Register, 447-416 */
#define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
* data Register, 479-448 */
#define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
* data Register, 511-480 */
#define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
* data Register, 543-512 */
#define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
* data Register, 575-544 */
#define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
* data Register, 607-576 */
#define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
* data Register, 639-608 */
#define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
* data Register, 671-640 */
#define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
* data Register, 703-672 */
#define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
* data Register, 735-704 */
#define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
* data Register, 767-736 */
#define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
* data Register, 799-768 */
#define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
* data Register, 831-800 */
#define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
* data Register, 863-832 */
#define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
* data Register, 895-864 */
#define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
* data Register, 927-896 */
#define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
* data Register, 959-928 */
#define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
* data Register, 991-960 */
#define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
* data Register, 1023-992 */
#define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
* ECC Register, 31-0 */
#define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
* ECC Register, 63-32 */
#define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
* ECC Register, 95-64 */
#define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
* ECC Register, 127-96 */
#define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
* ECC Register, 159-128 */
#define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
* ECC Register, 191-160 */
#define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
* ECC Register, 223-192 */
#define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
* ECC Register, 255-224 */
#define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
* address Register 31-0 */
#define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
* address Register 63-32 */
#define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
* 31-0 */
#define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
* 63-32 */
#define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
* 95-64 */
#define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
* 127-96 */
#define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
* 159-128 */
#define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
* 191-160 */
#define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
* 223-192 */
#define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
* 255-224 */
#define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
* 287-256 */
#define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
* 319-288 */
#define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
* 351-320 */
#define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
* 383-352 */
#define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
* 415-384 */
#define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
* 447-416 */
#define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
* 479-448 */
#define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
* 511-480 */
#define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
* 543-512 */
#define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
* 575-544 */
#define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
* 607-576 */
#define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
* 639-608 */
#define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
* 671-640 */
#define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
* 703-672 */
#define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
* 735-704 */
#define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
* 767-736 */
#define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
* 799-768 */
#define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
* 831-800 */
#define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
* 863-832 */
#define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
* 895-864 */
#define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
* 927-896 */
#define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
* 959-928 */
#define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
* 991-960 */
#define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
* 1023-992 */
#define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
* 31-0 */
#define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
* 63-32 */
#define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
* 95-64 */
#define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
* 127-96 */
#define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
* 159-128 */
#define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
* 191-160 */
#define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
* 223-192 */
#define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
* 255-224 */
/* @} */
/** @name Interrupt Status and Enable Register bitmaps and masks
*
* Bit definitions for the ECC status register and ECC interrupt enable register.
* @{
*/
#define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
#define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
#define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XBram_In32 Xil_In32
#define XBram_Out32 Xil_Out32
#define XBram_In16 Xil_In16
#define XBram_Out16 Xil_Out16
#define XBram_In8 Xil_In8
#define XBram_Out8 Xil_Out8
/****************************************************************************/
/**
*
* Write a value to a BRAM register. A 32 bit write is performed.
*
* @param BaseAddress is the base address of the BRAM device register.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note C-style signature:
* void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
****************************************************************************/
#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/****************************************************************************/
/**
*
* Read a value from a BRAM register. A 32 bit read is performed.
*
* @param BaseAddress is the base address of the BRAM device registers.
* @param RegOffset is the register offset from the base to read from.
*
* @return Data read from the register.
*
* @note C-style signature:
* u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
*
****************************************************************************/
#define XBram_ReadReg(BaseAddress, RegOffset) \
XBram_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xdebug.h
+40
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@@ -0,0 +1,40 @@
#ifndef XDEBUG /* prevent circular inclusions */
#define XDEBUG /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#if defined(DEBUG) && !defined(NDEBUG)
#ifndef XDEBUG_WARNING
#define XDEBUG_WARNING
#warning DEBUG is enabled
#endif
int printf(const char *format, ...);
#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
#define xdbg_current_types (XDBG_DEBUG_GENERAL)
#define xdbg_stmnt(x) x
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x)
#define xdbg_printf(...)
#endif /* defined(DEBUG) && !defined(NDEBUG) */
#ifdef __cplusplus
}
#endif
#endif /* XDEBUG */
datalink814_sp/bsp/microblaze_ps/include/xenv.h
+183
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@@ -0,0 +1,183 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv.h
*
* Defines common services that are typically found in a host operating.
* environment. This include file simply includes an OS specific file based
* on the compile-time constant BUILD_ENV_*, where * is the name of the target
* environment.
*
* All services are defined as macros.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b ch 10/24/02 Added XENV_LINUX
* 1.00a rmm 04/17/02 First release
* </pre>
*
******************************************************************************/
#ifndef XENV_H /* prevent circular inclusions */
#define XENV_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/*
* Select which target environment we are operating under
*/
/* VxWorks target environment */
#if defined XENV_VXWORKS
#include "xenv_vxworks.h"
/* Linux target environment */
#elif defined XENV_LINUX
#include "xenv_linux.h"
/* Unit test environment */
#elif defined XENV_UNITTEST
#include "ut_xenv.h"
/* Integration test environment */
#elif defined XENV_INTTEST
#include "int_xenv.h"
/* Standalone environment selected */
#else
#include "xenv_standalone.h"
#endif
/*
* The following comments specify the types and macro wrappers that are
* expected to be defined by the target specific header files
*/
/**************************** Type Definitions *******************************/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP
*
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
* Samples the processor's or external timer's time base counter.
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of microseconds.
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of milliseconds.
*/
/*****************************************************************************//**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None
*/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
datalink814_sp/bsp/microblaze_ps/include/xenv_standalone.h
+364
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@@ -0,0 +1,364 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_standalone.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
* used under Xilinx standalone BSP.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a rmm 03/21/02 First release
* 1.00a wgr 03/22/07 Converted to new coding style.
* 1.00a rpm 06/29/07 Added udelay macro for standalone
* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
* to in MICROBLAZE section
* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
*
* </pre>
*
*
******************************************************************************/
#ifndef XENV_STANDALONE_H
#define XENV_STANDALONE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/******************************************************************************
*
* Get the processor dependent includes
*
******************************************************************************/
#include <string.h>
#if defined __MICROBLAZE__
# include "mb_interface.h"
# include "xparameters.h" /* XPAR constants used below in MB section */
#elif defined __PPC__
# include "sleep.h"
# include "xcache_l.h" /* also include xcache_l.h for caching macros */
#endif
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* The following are straight forward implementations of memset and memcpy.
*
* NOTE: memcpy may not work if source and target memory area are overlapping.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
* @note
* This implemention MAY BREAK work if source and target memory
* area are overlapping.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef s32 XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#ifdef __PPC__
#define XENV_USLEEP(delay) usleep(delay)
#define udelay(delay) usleep(delay)
#else
#define XENV_USLEEP(delay)
#define udelay(delay)
#endif
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* Processor independent macros
*
******************************************************************************/
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
/******************************************************************************
*
* MicroBlaze case
*
* NOTE: Currently the following macros will only work on systems that contain
* only ONE MicroBlaze processor. Also, the macros will only be enabled if the
* system is built using a xparameters.h file.
*
******************************************************************************/
#if defined __MICROBLAZE__
/* Check if MicroBlaze data cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
#else
# define XCACHE_ENABLE_DCACHE()
# define XCACHE_DISABLE_DCACHE()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
/* Check if MicroBlaze instruction cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_ENABLE_ICACHE()
# define XCACHE_DISABLE_ICACHE()
#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
/******************************************************************************
*
* PowerPC case
*
* Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
* specific memory region (0x80000001). Each bit (0-30) in the regions
* bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
* range.
*
* regions --> cached address range
* ------------|--------------------------------------------------
* 0x80000000 | [0, 0x7FFFFFF]
* 0x00000001 | [0xF8000000, 0xFFFFFFFF]
* 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
*
******************************************************************************/
#elif defined __PPC__
#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifndef XENV_STANDALONE_H */
datalink814_sp/bsp/microblaze_ps/include/xgpio.h
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/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio.h
* @addtogroup gpio_v4_4
* @{
* @details
*
* This file contains the software API definition of the Xilinx General Purpose
* I/O (XGpio) device driver.
*
* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
* contains the following general features:
* - Support for up to 32 I/O discretes for each channel (64 bits total).
* - Each of the discretes can be configured for input or output.
* - Configurable support for dual channels and interrupt generation.
*
* The driver provides interrupt management functions. Implementation of
* interrupt handlers is left to the user. Refer to the provided interrupt
* example in the examples directory for details.
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* <b>Initialization & Configuration</b>
*
* The XGpio_Config structure is used by the driver to configure itself. This
* configuration structure is typically created by the tool-chain based on HW
* build properties.
*
* To support multiple runtime loading and initialization strategies employed
* by various operating systems, the driver instance can be initialized in one
* of the following ways:
*
* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
* configuration structure created by the tool-chain based on an ID provided
* by the tool-chain.
*
* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* @note
*
* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
* the unused bits from registers are read as zero and written as don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/13/02 First release
* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
* 2.01a jvb 12/14/05 I separated dependency on the static config table and
* xparameters.h from the driver initialization by moving
* _Initialize and _LookupConfig to _sinit.c. I also added
* the new _CfgInitialize routine.
* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
* to properly update the Interrupt Enable register
* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
* file
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
* XGpio_mSetDataDirection, XGpio_mGetDataReg and
* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
* XGpio_ReadReg to achieve the same functionality.
* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
* xparameters.h. CR#698589
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
* 4.1 lks 11/18/15 Updated to use cannonical xparameters in examples and
* clean up of the comments, removed support for DCR bridge
* and removed xgpio_intr_example for CR 900381
* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
* adding 64 bit support. CR# 867425.
* Changed the prototype of XGpio_CfgInitialize API.
* 4.3 sk 09/29/16 Modified the example to make it work when LED_bits are
* configured as an output. CR# 958644
* ms 01/23/17 Added xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 4.4 sne 04/25/19 Updated Makefile for IAR compier (CR-1029421).
*
* </pre>
*****************************************************************************/
#ifndef XGPIO_H /* prevent circular inclusions */
#define XGPIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xgpio_l.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /* Unique ID of device */
UINTPTR BaseAddress; /* Device base address */
int InterruptPresent; /* Are interrupts supported in h/w */
int IsDual; /* Are 2 channels supported in h/w */
} XGpio_Config;
/**
* The XGpio driver instance data. The user is required to allocate a
* variable of this type for every GPIO device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
UINTPTR BaseAddress; /* Device base address */
u32 IsReady; /* Device is initialized and ready */
int InterruptPresent; /* Are interrupts supported in h/w */
int IsDual; /* Are 2 channels supported in h/w */
} XGpio;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
/*
* Initialization functions in xgpio_sinit.c
*/
int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
/*
* API Basic functions implemented in xgpio.c
*/
int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
UINTPTR EffectiveAddr);
void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
u32 DirectionMask);
u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
/*
* API Functions implemented in xgpio_extra.c
*/
void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
/*
* API Functions implemented in xgpio_selftest.c
*/
int XGpio_SelfTest(XGpio *InstancePtr);
/*
* API Functions implemented in xgpio_intr.c
*/
void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xgpio_i.h
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/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************/
/**
* @file xgpio_i.h
* @addtogroup gpio_v4_3
* @{
*
* This header file contains internal identifiers, which are those shared
* between the files of the driver. It is intended for internal use only.
*
* NOTES:
*
* None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/13/02 First release
* 2.11a mta 03/21/07 Updated to new coding style
* </pre>
******************************************************************************/
#ifndef XGPIO_I_H /* prevent circular inclusions */
#define XGPIO_I_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xgpio.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions ****************************/
extern XGpio_Config XGpio_ConfigTable[];
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xgpio_l.h
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/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpio_l.h
* @addtogroup gpio_v4_4
* @{
*
* This header file contains identifiers and driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
* The macros that are available in this file use a multiply to calculate the
* addresses of registers. The user can control whether that multiply is done
* at run time or at compile time. A constant passed as the channel parameter
* will cause the multiply to be done at compile time. A variable passed as the
* channel parameter will cause it to occur at run time.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a jhl 04/24/02 First release of low level driver
* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
* change required the functions to be changed such that
* the interface is not compatible with previous versions.
* See the examples in the example directory for macros
* to help compile an application that was designed for
* previous versions of the driver. The interrupt registers
* are accessible using the ReadReg and WriteReg macros and
* a channel parameter was added to the other macros.
* 2.11a mta 03/21/07 Updated to new coding style
* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
* XGpio_mReadReg to XGpio_ReadReg.
* Removed the macros XGpio_mSetDataDirection,
* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
* same functionality.
* 4.1 lks 11/18/15 Removed support for DCR bridge
* </pre>
*
******************************************************************************/
#ifndef XGPIO_L_H /* prevent circular inclusions */
#define XGPIO_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Registers
*
* Register offsets for this device.
* @{
*/
#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
/* @} */
/* The following constant describes the offset of each channels data and
* tristate register from the base address.
*/
#define XGPIO_CHAN_OFFSET 8
/** @name Interrupt Status and Enable Register bitmaps and masks
*
* Bit definitions for the interrupt status register and interrupt enable
* registers.
* @{
*/
#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
/*@}*/
/** @name Global Interrupt Enable Register bitmaps and masks
*
* Bit definitions for the Global Interrupt Enable register
* @{
*/
#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XGpio_In32 Xil_In32
#define XGpio_Out32 Xil_Out32
/****************************************************************************/
/**
*
* Write a value to a GPIO register. A 32 bit write is performed. If the
* GPIO core is implemented in a smaller width, only the least significant data
* is written.
*
* @param BaseAddress is the base address of the GPIO device.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note C-style signature:
* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
****************************************************************************/
#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/****************************************************************************/
/**
*
* Read a value from a GPIO register. A 32 bit read is performed. If the
* GPIO core is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the GPIO device.
* @param RegOffset is the register offset from the base to read from.
*
* @return Data read from the register.
*
* @note C-style signature:
* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
*
****************************************************************************/
#define XGpio_ReadReg(BaseAddress, RegOffset) \
XGpio_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xil_assert.h
+191
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/******************************************************************************
*
* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.h
*
* @addtogroup common_assert_apis Assert APIs and Macros
*
* The xil_assert.h file contains assert related functions and macros.
* Assert APIs/Macros specifies that a application program satisfies certain
* conditions at particular points in its execution. These function can be
* used by application programs to ensure that, application code is satisfying
* certain conditions.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
* </pre>
*
******************************************************************************/
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
#define XIL_ASSERT_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define XIL_ASSERT_NONE 0U
#define XIL_ASSERT_OCCURRED 1U
#define XNULL NULL
extern u32 Xil_AssertStatus;
extern s32 Xil_AssertWait;
extern void Xil_Assert(const char8 *File, s32 Line);
void XNullHandler(void *NullParameter);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef NDEBUG
/*****************************************************************************/
/**
* @brief This assert macro is to be used for void functions. This in
* conjunction with the Xil_AssertWait boolean can be used to
* accomodate tests so that asserts which fail allow execution to
* continue.
*
* @param Expression: expression to be evaluated. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertVoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* @brief This assert macro is to be used for functions that do return a
* value. This in conjunction with the Xil_AssertWait boolean can be
* used to accomodate tests so that asserts which fail allow execution
* to continue.
*
* @param Expression: expression to be evaluated. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertNonvoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* @brief Always assert. This assert macro is to be used for void functions.
* Use for instances where an assert should always occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertVoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* @brief Always assert. This assert macro is to be used for functions that
* do return a value. Use for instances where an assert should always
* occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertNonvoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
}
#else
#define Xil_AssertVoid(Expression)
#define Xil_AssertVoidAlways()
#define Xil_AssertNonvoid(Expression)
#define Xil_AssertNonvoidAlways()
#endif
/************************** Function Prototypes ******************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_assert_apis".
*/
datalink814_sp/bsp/microblaze_ps/include/xil_cache.h
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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.h
*
* The xil_cache.h file contains cache related driver functions (or macros)
* that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* The functions in this header file can be used across all Xilinx supported
* processors.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 hbm 07/28/09 Initial release
* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that
* the correct cache flush routines are used based on
* whether the write-back or write-through caches are
* used (cr #630532).
* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system
* cache/L2 cache. The existing/old APIs/macros in this
* file are renamed to imply that they deal with L1 cache.
* New macros/APIs are added to address similar features for
* L2 cache. Users can include this file in their application
* to use the various cache related APIs. These changes are
* done for implementing PR #697214.
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
#if defined XENV_VXWORKS
/* VxWorks environment */
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#else
/* standalone environment */
#include "mb_interface.h"
#include "xil_types.h"
#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
#endif
/****************************************************************************/
/**
*
* @brief Invalidate the entire L1 data cache. If the cacheline is modified
* (dirty), the modified contents are lost.
*
* @param None.
*
* @return None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
/****************************************************************************/
/**
*
* @brief Invalidate the entire L2 data cache. If the cacheline is modified
* (dirty),the modified contents are lost.
*
* @param None.
*
* @return None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
/****************************************************************************/
/**
*
* @brief Invalidate the L1 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the L1
* data cache, the cacheline containing that byte is invalidated.If
* the cacheline is modified (dirty), the modified contents are lost.
*
* @param Addr is address of ragne to be invalidated.
* @param Len is the length in bytes to be invalidated.
*
* @return None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L1DCacheInvalidateRange(Addr, Len) \
microblaze_invalidate_dcache_range((Addr), (Len))
/****************************************************************************/
/**
*
* @brief Invalidate the L1 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the
* L1 data cache, the cacheline containing that byte is invalidated.
* If the cacheline is modified (dirty), the modified contents are lost.
*
* @param Addr: address of ragne to be invalidated.
* @param Len: length in bytes to be invalidated.
*
* @return None.
*
* @note
* Processor must be in real mode.
****************************************************************************/
#define Xil_L2CacheInvalidateRange(Addr, Len) \
microblaze_invalidate_cache_ext_range((Addr), (Len))
/****************************************************************************/
/**
* @brief Flush the L1 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the
* data cache, and is modified (dirty), the cacheline will be written
* to system memory.The cacheline will also be invalidated.
*
* @param Addr: the starting address of the range to be flushed.
* @param Len: length in byte to be flushed.
*
* @return None.
*
****************************************************************************/
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define Xil_L1DCacheFlushRange(Addr, Len) \
microblaze_flush_dcache_range((Addr), (Len))
#else
# define Xil_L1DCacheFlushRange(Addr, Len) \
microblaze_invalidate_dcache_range((Addr), (Len))
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
/****************************************************************************/
/**
* @brief Flush the L2 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the
* data cache, and is modified (dirty), the cacheline will be
* written to system memory. The cacheline will also be invalidated.
*
* @param Addr: the starting address of the range to be flushed.
* @param Len: length in byte to be flushed.
*
* @return None.
*
****************************************************************************/
#define Xil_L2CacheFlushRange(Addr, Len) \
microblaze_flush_cache_ext_range((Addr), (Len))
/****************************************************************************/
/**
* @brief Flush the entire L1 data cache. If any cacheline is dirty, the
* cacheline will be written to system memory. The entire data cache
* will be invalidated.
*
* @return None.
*
****************************************************************************/
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define Xil_L1DCacheFlush() microblaze_flush_dcache()
#else
# define Xil_L1DCacheFlush() microblaze_invalidate_dcache()
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
/****************************************************************************/
/**
* @brief Flush the entire L2 data cache. If any cacheline is dirty, the
* cacheline will be written to system memory. The entire data cache
* will be invalidated.
*
* @return None.
*
****************************************************************************/
#define Xil_L2CacheFlush() microblaze_flush_cache_ext()
/****************************************************************************/
/**
*
* @brief Invalidate the instruction cache for the given address range.
*
* @param Addr is address of ragne to be invalidated.
* @param Len is the length in bytes to be invalidated.
*
* @return None.
*
****************************************************************************/
#define Xil_L1ICacheInvalidateRange(Addr, Len) \
microblaze_invalidate_icache_range((Addr), (Len))
/****************************************************************************/
/**
*
* @brief Invalidate the entire instruction cache.
*
* @param None
*
* @return None.
*
****************************************************************************/
#define Xil_L1ICacheInvalidate() \
microblaze_invalidate_icache()
/****************************************************************************/
/**
*
* @brief Enable the L1 data cache.
*
* @return None.
*
* @note This is processor specific.
*
****************************************************************************/
#define Xil_L1DCacheEnable() \
microblaze_enable_dcache()
/****************************************************************************/
/**
*
* @brief Disable the L1 data cache.
*
* @return None.
*
* @note This is processor specific.
*
****************************************************************************/
#define Xil_L1DCacheDisable() \
microblaze_disable_dcache()
/****************************************************************************/
/**
*
* @brief Enable the instruction cache.
*
* @return None.
*
* @note This is processor specific.
*
****************************************************************************/
#define Xil_L1ICacheEnable() \
microblaze_enable_icache()
/****************************************************************************/
/**
*
* @brief Disable the L1 Instruction cache.
*
* @return None.
*
* @note This is processor specific.
*
****************************************************************************/
#define Xil_L1ICacheDisable() \
microblaze_disable_icache()
/****************************************************************************/
/**
*
* @brief Enable the data cache.
*
* @param None
*
* @return None.
*
****************************************************************************/
#define Xil_DCacheEnable() Xil_L1DCacheEnable()
/****************************************************************************/
/**
*
* @brief Enable the instruction cache.
*
* @param None
*
* @return None.
*
* @note
*
*
****************************************************************************/
#define Xil_ICacheEnable() Xil_L1ICacheEnable()
/****************************************************************************
*
* @brief Invalidate the entire Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
#define Xil_DCacheInvalidate() \
Xil_L2CacheInvalidate(); \
Xil_L1DCacheInvalidate();
/****************************************************************************
*
* @brief Invalidate the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the
* Data cache, the cacheline containing that byte is invalidated.
* If the cacheline is modified (dirty), the modified contents are
* lost and are NOT written to system memory before the line is
* invalidated.
*
* @param Addr: Start address of ragne to be invalidated.
* @param Len: Length of range to be invalidated in bytes.
*
* @return None.
*
****************************************************************************/
#define Xil_DCacheInvalidateRange(Addr, Len) \
Xil_L2CacheInvalidateRange((Addr), (Len)); \
Xil_L1DCacheInvalidateRange((Addr), (Len));
/****************************************************************************
*
* @brief Flush the entire Data cache.
*
* @param None.
*
* @return None.
*
****************************************************************************/
#define Xil_DCacheFlush() \
Xil_L2CacheFlush(); \
Xil_L1DCacheFlush();
/****************************************************************************
* @brief Flush the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the
* Data cache, the cacheline containing that byte is invalidated.
* If the cacheline is modified (dirty), the written to system
* memory first before the before the line is invalidated.
*
* @param Addr: Start address of range to be flushed.
* @param Len: Length of range to be flushed in bytes.
*
* @return None.
*
****************************************************************************/
#define Xil_DCacheFlushRange(Addr, Len) \
Xil_L2CacheFlushRange((Addr), (Len)); \
Xil_L1DCacheFlushRange((Addr), (Len));
/****************************************************************************
*
* @brief Invalidate the entire instruction cache.
*
* @param None.
*
* @return None.
*
****************************************************************************/
#define Xil_ICacheInvalidate() \
Xil_L2CacheInvalidate(); \
Xil_L1ICacheInvalidate();
/****************************************************************************
*
* @brief Invalidate the instruction cache for the given address range.
* If the bytes specified by the address (adr) are cached by the
* Data cache, the cacheline containing that byte is invalidated.
* If the cacheline is modified (dirty), the modified contents are
* lost and are NOT written to system memory before the line is
* invalidated.
*
* @param Addr: Start address of ragne to be invalidated.
* @param Len: Length of range to be invalidated in bytes.
*
* @return None.
*
****************************************************************************/
#define Xil_ICacheInvalidateRange(Addr, Len) \
Xil_L2CacheInvalidateRange((Addr), (Len)); \
Xil_L1ICacheInvalidateRange((Addr), (Len));
void Xil_DCacheDisable(void);
void Xil_ICacheDisable(void);
#ifdef __cplusplus
}
#endif
#endif
#endif
/**
* @} End of "addtogroup microblaze_cache_apis".
*/
datalink814_sp/bsp/microblaze_ps/include/xil_cache_vxworks.h
+89
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/******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_vxworks.h
*
* Contains the cache related functions for VxWorks that is wrapped by
* xil_cache.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 12/11/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_CACHE_VXWORKS_H
#define XIL_CACHE_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#if (CPU_FAMILY==PPC)
#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
#define Xil_DCacheInvalidateRange(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_DCacheFlushRange(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
#define Xil_ICacheInvalidateRange(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif
datalink814_sp/bsp/microblaze_ps/include/xil_exception.h
+127
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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_exception.h
*
* @addtogroup microblaze_exception_apis Microblaze Exception APIs
*
* The xil_exception.h file contains Microblaze specific exception
* related APIs and macros. Application programs can use these APIs/Macros
* for various exception related operations (i.e. enable exception, disable
* exception, register exception hander etc.)
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 hbm 07/28/09 Initial release
*
* </pre>
*
* @note
* To use exception related functions, the xil_exception.h file must be added in
* source code
*
******************************************************************************/
#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
#define XIL_EXCEPTION_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/*
* These constants are specific to Microblaze processor.
*/
#define XIL_EXCEPTION_ID_FIRST 0U
#define XIL_EXCEPTION_ID_FSL 0U
#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1U
#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2U
#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3U
#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3U
#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4U
#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4U
#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5U
#define XIL_EXCEPTION_ID_FPU 6U
#define XIL_EXCEPTION_ID_STACK_VIOLATION 7U
#define XIL_EXCEPTION_ID_MMU 7U
#define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU
/*
* XIL_EXCEPTION_ID_INT is defined for all processors, but with different value.
*/
#define XIL_EXCEPTION_ID_INT 16U /**
* exception ID for interrupt
*/
/**************************** Type Definitions *******************************/
/**
* This typedef is the exception handler function.
*/
typedef void (*Xil_ExceptionHandler)(void *Data);
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler) (void *InstancePtr);
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern void Xil_ExceptionRegisterHandler(u32 Id,
Xil_ExceptionHandler Handler,
void *Data);
extern void Xil_ExceptionRemoveHandler(u32 Id);
extern void Xil_ExceptionInit(void);
extern void Xil_ExceptionEnable(void);
extern void Xil_ExceptionDisable(void);
#ifdef __cplusplus
}
#endif
#endif
/**
* @} End of "addtogroup microblaze_exception_apis".
*/
datalink814_sp/bsp/microblaze_ps/include/xil_hal.h
+65
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@@ -0,0 +1,65 @@
/******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_hal.h
*
* Contains all the HAL header files.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/28/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_HAL_H
#define XIL_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_cache.h"
#include "xil_io.h"
#include "xil_assert.h"
#include "xil_exception.h"
#include "xil_types.h"
#ifdef __cplusplus
}
#endif
#endif
datalink814_sp/bsp/microblaze_ps/include/xil_io.h
+341
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/******************************************************************************
*
* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_io.h
*
* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
*
* The xil_io.h file contains the interface for the general I/O component, which
* encapsulates the Input/Output functions for the processors that do not
* require any special I/O handling.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
* ARM processors
* </pre>
******************************************************************************/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_printf.h"
#if defined (__MICROBLAZE__)
#include "mb_interface.h"
#else
#include "xpseudo_asm.h"
#endif
/************************** Function Prototypes ******************************/
u16 Xil_EndianSwap16(u16 Data);
u32 Xil_EndianSwap32(u32 Data);
#ifdef ENABLE_SAFETY
extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
#endif
/***************** Macros (Inline Functions) Definitions *********************/
#if defined __GNUC__
#if defined (__MICROBLAZE__)
# define INST_SYNC mbar(0)
# define DATA_SYNC mbar(1)
# else
# define SYNCHRONIZE_IO dmb()
# define INST_SYNC isb()
# define DATA_SYNC dsb()
# endif
#else
# define SYNCHRONIZE_IO
# define INST_SYNC
# define DATA_SYNC
# define INST_SYNC
# define DATA_SYNC
#endif
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
#define INLINE inline
#else
#define INLINE __inline
#endif
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading
* from the specified address and returning the 8 bit Value read from
* that address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 8 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u8 Xil_In8(UINTPTR Addr)
{
return *(volatile u8 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading from
* the specified address and returning the 16 bit Value read from that
* address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 16 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u16 Xil_In16(UINTPTR Addr)
{
return *(volatile u16 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by
* reading from the specified address and returning the 32 bit Value
* read from that address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 32 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u32 Xil_In32(UINTPTR Addr)
{
return *(volatile u32 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading the
* 64 bit Value read from that address.
*
*
* @param Addr: contains the address to perform the input operation
*
* @return The 64 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u64 Xil_In64(UINTPTR Addr)
{
return *(volatile u64 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for an memory location by
* writing the 8 bit Value to the the specified address.
*
* @param Addr: contains the address to perform the output operation
* @param Value: contains the 8 bit Value to be written at the specified
* address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
{
volatile u8 *LocalAddr = (volatile u8 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 16 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the Value to be written at the specified address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
{
volatile u16 *LocalAddr = (volatile u16 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 32 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the 32 bit Value to be written at the specified
* address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
#ifndef ENABLE_SAFETY
volatile u32 *LocalAddr = (volatile u32 *)Addr;
*LocalAddr = Value;
#else
XStl_RegUpdate(Addr, Value);
#endif
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 64 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains 64 bit Value to be written at the specified address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
{
volatile u64 *LocalAddr = (volatile u64 *)Addr;
*LocalAddr = Value;
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
# else
# define Xil_In16BE Xil_In16
# define Xil_In32BE Xil_In32
# define Xil_Out16BE Xil_Out16
# define Xil_Out32BE Xil_Out32
# define Xil_Htons(Data) (Data)
# define Xil_Htonl(Data) (Data)
# define Xil_Ntohs(Data) (Data)
# define Xil_Ntohl(Data) (Data)
#endif
#else
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
#endif
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#else
static INLINE u16 Xil_In16LE(UINTPTR Addr)
#endif
#else
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#endif
{
u16 value = Xil_In16(Addr);
return Xil_EndianSwap16(value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#else
static INLINE u32 Xil_In32LE(UINTPTR Addr)
#endif
#else
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#endif
{
u32 value = Xil_In32(Addr);
return Xil_EndianSwap32(value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#else
static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
#endif
#else
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#endif
{
Value = Xil_EndianSwap16(Value);
Xil_Out16(Addr, Value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#else
static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
#endif
#else
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#endif
{
Value = Xil_EndianSwap32(Value);
Xil_Out32(Addr, Value);
}
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_io_interfacing_apis".
*/
datalink814_sp/bsp/microblaze_ps/include/xil_macroback.h
+1056
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datalink814_sp/bsp/microblaze_ps/include/xil_mem.h
+68
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@@ -0,0 +1,68 @@
/******************************************************************************/
/**
* Copyright (C) 2015 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
* @file xil_mem.h
*
* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
*
* The xil_mem.h file contains prototype for functions related
* to memory operations. These APIs are applicable for all processors supported
* by Xilinx.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.1 nsk 11/07/16 First release.
* 7.0 mus 01/07/19 Add cpp extern macro
*
* </pre>
*
*****************************************************************************/
#ifndef XIL_MEM_H /* prevent circular inclusions */
#define XIL_MEM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/************************** Function Prototypes *****************************/
void Xil_MemCpy(void* dst, const void* src, u32 cnt);
#ifdef __cplusplus
}
#endif
#endif /* XIL_MEM_H */
/**
* @} End of "addtogroup common_mem_operation_api".
*/
datalink814_sp/bsp/microblaze_ps/include/xil_misc_psreset_api.h
+273
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/******************************************************************************
*
* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_misc_psreset_api.h
*
* This file contains the various register defintions and function prototypes for
* implementing the reset functionality of zynq ps devices
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b kpc 03/07/13 First release.
* </pre>
*
******************************************************************************/
#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
#define XIL_MISC_RESET_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
#define XDDRC_CTRL_BASEADDR 0xF8006000U
#define XSLCR_BASEADDR 0xF8000000U
/**< OCM configuration register */
#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
/**< SLCR unlock register */
#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
/**< SLCR GEM0 rx clock control register */
#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
/**< SLCR GEM1 rx clock control register */
#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
/**< SLCR GEM0 clock control register */
#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
/**< SLCR GEM1 clock control register */
#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
/**< SLCR SMC clock control register */
#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
/**< SLCR GEM reset control register */
#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
/**< SLCR USB0 clock control register */
#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
/**< SLCR USB1 clock control register */
#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
/**< SLCR USB1 reset control register */
#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
/**< SLCR SMC reset control register */
#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
/**< SLCR Level shifter enable register */
#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
/**< SLCR ARM pll control register */
#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
/**< SLCR DDR pll control register */
#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
/**< SLCR IO pll control register */
#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
/**< SLCR ARM pll configuration register */
#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
/**< SLCR DDR pll configuration register */
#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
/**< SLCR IO pll configuration register */
#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
/**< SLCR ARM clock control register */
#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
/**< SLCR DDR clock control register */
#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
/**< SLCR MIO pin address register */
#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
/**< SLCR DMAC reset control address register */
#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
/**< SLCR USB reset control address register */
/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
/**< SLCR GEM reset control address register */
/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
/**< SLCR SDIO reset control address register */
#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
/**< SLCR SPI reset control address register */
#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
/**< SLCR CAN reset control address register */
#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
/**< SLCR I2C reset control address register */
#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
/**< SLCR UART reset control address register */
#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
/**< SLCR GPIO reset control address register */
#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
/**< SLCR LQSPI reset control address register */
#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
/**< SLCR SMC reset control address register */
/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
/**< SLCR OCM reset control address register */
#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
/**< SMC mem controller clear config register */
#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
/**< SMC idlecount configuration register */
#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
/**< SMC ECC configuration register */
#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
/**< SMC ECC command 1 register */
#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
/**< SMC ECC command 2 register */
#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
/**< SLCR unlock code */
#define XSLCR_UNLOCK_CODE 0x0000DF0DU
/**< SMC mem clear configuration mask */
#define XSMC_MEMC_CLR_CONFIG_MASK 0x0000005FU
/**< SMC ECC memconfig 1 reset value */
#define XSMC_ECC_MEMCFG1_RESET_VAL 0x00000043U
/**< SMC ECC memcommand 1 reset value */
#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
/**< SMC ECC memcommand 2 reset value */
#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
/**< DDR controller reset bit mask */
#define XDDRPS_CTRL_RESET_MASK 0x00000001U
/**< SLCR OCM configuration reset value*/
#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
/**< SLCR OCM bank selection mask*/
#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
/**< SLCR level shifter enable mask*/
#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
/**< SLCR PLL register reset values */
#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
/**< SLCR MIO register default values */
#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
/**< SLCR Reset control registers default values */
#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
/**************************** Type Definitions *******************************/
/* the following data type is used to hold a null terminated version string
* consisting of the following format, "X.YYX"
*/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Performs reset operation to the ddr interface
*/
void XDdr_ResetHw(void);
/*
* Map the ocm region to post bootrom state
*/
void XOcm_Remap(void);
/*
* Performs the smc interface reset
*/
void XSmc_ResetHw(u32 BaseAddress);
/*
* updates the MIO registers with reset values
*/
void XSlcr_MioWriteResetValues(void);
/*
* updates the PLL and clock registers with reset values
*/
void XSlcr_PllWriteResetValues(void);
/*
* Disables the level shifters
*/
void XSlcr_DisableLevelShifters(void);
/*
* provides softreset to the GPIO interface
*/
void XSlcr_GpioPsReset(void);
/*
* provides softreset to the DMA interface
*/
void XSlcr_DmaPsReset(void);
/*
* provides softreset to the SMC interface
*/
void XSlcr_SmcPsReset(void);
/*
* provides softreset to the CAN interface
*/
void XSlcr_CanPsReset(void);
/*
* provides softreset to the Uart interface
*/
void XSlcr_UartPsReset(void);
/*
* provides softreset to the I2C interface
*/
void XSlcr_I2cPsReset(void);
/*
* provides softreset to the SPI interface
*/
void XSlcr_SpiPsReset(void);
/*
* provides softreset to the QSPI interface
*/
void XSlcr_QspiPsReset(void);
/*
* provides softreset to the USB interface
*/
void XSlcr_UsbPsReset(void);
/*
* provides softreset to the GEM interface
*/
void XSlcr_EmacPsReset(void);
/*
* provides softreset to the OCM interface
*/
void XSlcr_OcmReset(void);
#ifdef __cplusplus
}
#endif
#endif /* XIL_MISC_RESET_H */
datalink814_sp/bsp/microblaze_ps/include/xil_printf.h
+48
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@@ -0,0 +1,48 @@
#ifndef XIL_PRINTF_H
#define XIL_PRINTF_H
#ifdef __cplusplus
extern "C" {
#endif
#include <ctype.h>
#include <string.h>
#include <stdarg.h>
#include "xil_types.h"
#include "xparameters.h"
#include "bspconfig.h"
#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
#include "xen_console.h"
#endif
/*----------------------------------------------------*/
/* Use the following parameter passing structure to */
/* make xil_printf re-entrant. */
/*----------------------------------------------------*/
struct params_s;
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
/* same as the standard printf function without the */
/* overhead most run-time libraries involve. Usually */
/* the printf brings in many kilobytes of code and */
/* that is unacceptable in most embedded systems. */
/*---------------------------------------------------*/
typedef char8* charptr;
typedef s32 (*func_ptr)(int c);
/* */
void xil_printf( const char8 *ctrl1, ...);
void print( const char8 *ptr);
extern void outbyte (char8 c);
extern char8 inbyte(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
datalink814_sp/bsp/microblaze_ps/include/xil_testcache.h
+67
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@@ -0,0 +1,67 @@
/******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testcache.h
*
* @addtogroup common_test_utils
* <h2>Cache test </h2>
* The xil_testcache.h file contains utility functions to test cache.
*
* @{
* <pre>
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 07/29/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
#define XIL_TESTCACHE_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern s32 Xil_TestDCacheRange(void);
extern s32 Xil_TestDCacheAll(void);
extern s32 Xil_TestICacheRange(void);
extern s32 Xil_TestICacheAll(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_test_utils".
*/
datalink814_sp/bsp/microblaze_ps/include/xil_testio.h
+90
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/******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testio.h
*
* @addtogroup common_test_utils Test Utilities
* <h2>I/O test </h2>
* The xil_testio.h file contains utility functions to test endian related memory
* IO functions.
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00 hbm 08/05/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTIO_H /* prevent circular inclusions */
#define XIL_TESTIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define XIL_TESTIO_DEFAULT 0
#define XIL_TESTIO_LE 1
#define XIL_TESTIO_BE 2
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_test_utils".
*/
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/******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmem.h
* @addtogroup common_test_utils
*
* <h2>Memory test</h2>
*
* The xil_testmem.h file contains utility functions to test memory.
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
* Following list describes the supported memory tests:
*
* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
*
* - XIL_TESTMEM_INCREMENT: This test
* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
* test value for memory.
*
* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
* uses a walking '1' as the test value for memory.
* @code
* location 1 = 0x00000001
* location 2 = 0x00000002
* ...
* @endcode
*
* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
* This test uses the inverse value of the walking ones test
* as the test value for memory.
* @code
* location 1 = 0xFFFFFFFE
* location 2 = 0xFFFFFFFD
* ...
*@endcode
*
* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
* This test uses the inverse of the address of the location under test
* as the test value for memory.
*
* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
* This test uses the provided patters as the test value for memory.
* If zero is provided as the pattern the test uses '0xDEADBEEF".
*
* @warning
* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
* have been set up.
* The address provided to the memory tests is not checked for
* validity except for the NULL case. It is possible to provide a code-space
* pointer for this test to start with and ultimately destroy executable code
* causing random failures.
*
* @note
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
* repeat on a boundry of a power of two making it more difficult to detect
* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
* tests suffer the same problem. Ideally, if large blocks of memory are to be
* tested, break them up into smaller regions of memory to allow the test
* patterns used not to repeat over the region tested.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
#define XIL_TESTMEM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* xutil_memtest defines */
#define XIL_TESTMEM_INIT_VALUE 1U
/** @name Memory subtests
* @{
*/
/**
* See the detailed description of the subtests in the file description.
*/
#define XIL_TESTMEM_ALLMEMTESTS 0x00U
#define XIL_TESTMEM_INCREMENT 0x01U
#define XIL_TESTMEM_WALKONES 0x02U
#define XIL_TESTMEM_WALKZEROS 0x03U
#define XIL_TESTMEM_INVERSEADDR 0x04U
#define XIL_TESTMEM_FIXEDPATTERN 0x05U
#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
/* @} */
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* xutil_testmem prototypes */
extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_test_utils".
*/
datalink814_sp/bsp/microblaze_ps/include/xil_types.h
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/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_types.h
*
* @addtogroup common_types Basic Data types for Xilinx&reg; Software IP
*
* The xil_types.h file contains basic types for Xilinx software IP. These data types
* are applicable for all processors supported by Xilinx.
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
* Define LONG and ULONG datatypes and mask values
* 7.00 mus 01/07/19 Add cpp extern macro
* </pre>
*
******************************************************************************/
#ifndef XIL_TYPES_H /* prevent circular inclusions */
#define XIL_TYPES_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
/************************** Constant Definitions *****************************/
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
assigend to "IsReady" member of driver
instance to indicate that driver
instance is initialized and ready to use. */
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
"IsStarted" member of driver instance
to indicate that driver instance is
started and it can be enabled. */
/* @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XBASIC_TYPES_H
/*
* guarded against xbasic_types.h.
*/
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
/** @}*/
#define __XUINT64__
typedef struct
{
u32 Upper;
u32 Lower;
} Xuint64;
/*****************************************************************************/
/**
* @brief Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The upper 32 bits of the 64 bit word.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
/*****************************************************************************/
/**
* @brief Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The lower 32 bits of the 64 bit word.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
#endif /* XBASIC_TYPES_H */
/*
* xbasic_types.h does not typedef s* or u64
*/
/** @{ */
typedef char char8;
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
typedef int64_t s64;
typedef uint64_t u64;
typedef int sint32;
typedef intptr_t INTPTR;
typedef uintptr_t UINTPTR;
typedef ptrdiff_t PTRDIFF;
/** @}*/
#if !defined(LONG) || !defined(ULONG)
typedef long LONG;
typedef unsigned long ULONG;
#endif
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
#else
#include <linux/types.h>
#endif
/** @{ */
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler) (void *InstancePtr);
/**
* This data type defines an exception handler for a processor.
* The argument points to the instance of the component
*/
typedef void (*XExceptionHandler) (void *InstancePtr);
/**
* @brief Returns 32-63 bits of a number.
* @param n : Number being accessed.
* @return Bits 32-63 of number.
*
* @note A basic shift-right of a 64- or 32-bit quantity.
* Use this to suppress the "right shift count >= width of type"
* warning when that quantity is 32-bits.
*/
#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
/**
* @brief Returns 0-31 bits of a number
* @param n : Number being accessed.
* @return Bits 0-31 of number
*/
#define LOWER_32_BITS(n) ((u32)(n))
/************************** Constant Definitions *****************************/
#ifndef TRUE
#define TRUE 1U
#endif
#ifndef FALSE
#define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_types".
*/
datalink814_sp/bsp/microblaze_ps/include/xil_util.h
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/******************************************************************************/
/**
* Copyright (C) 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
* @file xil_util.h
*
* This file contains xil utility functions declaration
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.4 mmd 04/21/19 First release.
*
* </pre>
*
*****************************************************************************/
#ifndef XIL_UTIL_H_
#define XIL_UTIL_H_
/* Converts input character to nibble */
u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
/* Conver input hex string to array of 32-bits integers */
u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
/* Waits for specified event */
u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
#endif /* XIL_UTIL_H_ */
datalink814_sp/bsp/microblaze_ps/include/xintc.h
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/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc.h
* @addtogroup intc_v3_9
* @{
* @details
*
* The Xilinx interrupt controller driver component. This component supports the
* Xilinx interrupt controller.
*
* The interrupt controller driver uses the idea of priority for the various
* handlers. Priority is an integer within the range of 0 and 31 inclusive with
* 0 being the highest priority interrupt source.
*
* The Xilinx interrupt controller supports the following features:
*
* - specific individual interrupt enabling/disabling
* - specific individual interrupt acknowledging
* - attaching specific callback function to handle interrupt source
* - master enable/disable
* - single callback per interrupt or all pending interrupts handled for
* each interrupt of the processor
*
* The acknowledgement of the interrupt within the interrupt controller is
* selectable, either prior to the device's handler being called or after
* the handler is called. This is necessary to support interrupt signal inputs
* which are either edge or level signals. Edge driven interrupt signals
* require that the interrupt is acknowledged prior to the interrupt being
* serviced in order to prevent the loss of interrupts which are occurring
* extremely close together. A level driven interrupt input signal requires
* the interrupt to acknowledged after servicing the interrupt to ensure that
* the interrupt only generates a single interrupt condition.
*
* Details about connecting the interrupt handler of the driver are contained
* in the source file specific to interrupt processing, xintc_intr.c.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <b>Interrupt Vector Tables</b>
*
* The interrupt vector table for each interrupt controller device is declared
* statically in xintc_g.c within the configuration data for each instance.
* The device ID of the interrupt controller device is used by the driver as a
* direct index into the configuration data table - to retrieve the vector table
* for an instance of the interrupt controller. The user should populate the
* vector table with handlers and callbacks at run-time using the XIntc_Connect()
* and XIntc_Disconnect() functions.
*
* Each vector table entry corresponds to a device that can generate an
* interrupt. Each entry contains an interrupt handler function and an argument
* to be passed to the handler when an interrupt occurs. The tools default this
* argument to the base address of the interrupting device. Note that the
* device driver interrupt handlers given in this file do not take a base
* address as an argument, but instead take a pointer to the driver instance.
* This means that although the table is created statically, the user must still
* use XIntc_Connect() when the interrupt handler takes an argument other than
* the base address. This is only to say that the existence of the static vector
* tables should not mislead the user into thinking they no longer need to
* register/connect interrupt handlers with this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 08/16/01 First release
* 1.00a rpm 01/09/02 Removed the AckLocation argument from XIntc_Connect().
* This information is now internal in xintc_g.c.
* 1.00b jhl 02/13/02 Repartitioned the driver for smaller files
* 1.00b jhl 04/24/02 Made LookupConfig function global and relocated config
* data type
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table. Moved vector
* table and options out of instance structure and into
* the configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed from
* all the macro names/definitions.
* 2.01a sdm 04/27/10 Updated the tcl so that the defintions are generated in
* the xparameters.h to know whether the optional registers
* SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
* This driver doesnot make use of these definitions and does
* not use the optional registers.
* 2.03a hvm 05/24/11 Updated the tcl to generate vector Ids for external
* interrupts. CR565336
* 2.04a bss 01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
* and XIntc_SetNormalIntrMode for setting to normal
* interrupt mode.
* 2.04a asa 03/19/12 Changed the XIntc_Config struct. The order of entries
* declared in the structure now matches with the
* XIntc_ConfigTable generated by the driver tcl.
* 2.05a bss 08/16/12 Updated to support relocatable vectors in Microblaze,
* added IntVectorAddr to XIntc_Config for this.
* Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.06a bss 01/28/13 To support Cascade mode:
* Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
* XIN_INTC_SECONDARY,XIN_INTC_LAST and
* XIN_CONTROLLER_MAX_INTRS macros
* Added NumberofIntrs and IntcType fields in XIntc_Config
* structure.
* Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
* XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
* XIntc_Acknowledge,XIntc_ConnectFastHandler and
* XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
* API in xintc.c
* Modified XIntc_DeviceInterruptHandler,
* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
* XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
* API in xintc_l.c.
* Modified XIntc_SetOptions API in xintc_options.c.
* Modified XIntc_SimulateIntr API in xintc_selftest.c.
* Modified driver tcl:
* to check for Cascade mode and generate XPAR_INTC_TYPE
* for each controller.
* Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
* interrupt sources of all Controllers in Cascade mode.
* 2.07a bss 10/18/13 To support Nested interrupts:
* Modified XIntc_DeviceInterruptHandler API.
* Added XIN_ILR_OFFSET macro in xintc_l.h.
* Modified driver tcl to generate HAS_ILR parameter in
* xparameters.h
* 3.0 bss 01/28/13 Modified xintc.c to initialize IVAR register with
* XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
* CR#765931.
* Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
* correctly(CR#764865).
*
* @note
* For Cascade mode, Interrupt IDs are generated in xparameters.h
* as shown below:
*
* Master/Primary INTC
* ______
* | |-0 Secondary INTC
* | |-. ______
* | |-. | |-32 Last INTC
* | |-. | |-. ______
* |______|<-31------| |-. | |-64
* | |-. | |-.
* |______|<-63-------| |-.
* | |-.
* |______|-95
*
* All driver functions has to be called using DeviceId/
* InstancePtr/BaseAddress of Primary/Master Controller and
* Interrupts IDs generated in xparameters.h only.
* Driver functions takes care of Slave Controllers based on
* Interrupt ID passed. User must not use Interrupt source/ID
* 31 of Primary and Secondary controllers to call driver
* functions.
*
* For nested interrupts, XIntc_DeviceInterruptHandler saves
* microblaze r14 register on entry and restores on exit. This is
* required since compiler does not support nesting. It enables
* Microblaze interrupts after blocking further interrupts from
* the current interrupt number and interrupts below current
* interrupt proirity by writing to Interrupt Level Register of
* INTC on entry. On exit, it disables microblaze interrupts and
* restores ILR register default value(0xFFFFFFFF)back. It is
* recommended to increase STACK_SIZE in linker script for nested
* interrupts.
* 3.0 adk 12/10/13 Updated as per the New Tcl API's
* 3.0 adk 17/02/14 Fixed the CR:771287 Changes are made in the intc
* driver tcl.
* 3.1 adk 8/4/14 Fixed the CR:783248 Changes are made in
* the test-app tcl
* 3.2 bss 4/8/14 Fixed driver tcl to handle external interrupt pins
* correctly (CR#799609).
* 3.3 adk 11/3/14 added generation of C_HAS_ILR parameter to
* xparameters.h.Changes are made in the driver tcl file
* (CR#828046).
* 3.5 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* 3.6 ms 01/23/17 Added xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 3.7 ms 04/18/17 Modified tcl file to add suffix U for macro definitions
* of intc in xparameters.h
* 3.9 adk 19/12/18 If design contains unconnected interrupt pins
* return proper error message(CR#1018878).
* </pre>
*
******************************************************************************/
#ifndef XINTC_H /* prevent circular inclusions */
#define XINTC_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xstatus.h"
#include "xintc_l.h"
/************************** Constant Definitions *****************************/
/**
* @name Configuration options
* These options are used in XIntc_SetOptions() to configure the device.
* @{
*/
/**
* <pre>
* XIN_SVC_SGL_ISR_OPTION Service the highest priority pending interrupt
* and then return.
* XIN_SVC_ALL_ISRS_OPTION Service all of the pending interrupts and then
* return.
* </pre>
*/
#define XIN_SVC_SGL_ISR_OPTION 1UL
#define XIN_SVC_ALL_ISRS_OPTION 2UL
/*@}*/
/**
* @name Start modes
* One of these values is passed to XIntc_Start() to start the device.
* @{
*/
/** Simulation only mode, no hardware interrupts recognized */
#define XIN_SIMULATION_MODE 0
/** Real mode, no simulation allowed, hardware interrupts recognized */
#define XIN_REAL_MODE 1
/*@}*/
/**
* @name Masks to specify Interrupt Controller Mode
* @{
*/
#define XIN_INTC_NOCASCADE 0 /* Normal - No Cascade Mode */
#define XIN_INTC_PRIMARY 1 /* Master/Primary controller */
#define XIN_INTC_SECONDARY 2 /* Secondary Slave Controllers */
#define XIN_INTC_LAST 3 /* Last Slave Controller */
/*@}*/
/**
* @name Mask to specify maximum number of interrupt sources per controller
* @{
*/
#define XIN_CONTROLLER_MAX_INTRS 32 /* Each Controller has 32
interrupt pins */
#define XINTC_STANDARD_VECTOR_ADDRESS_WIDTH 32U
/*@}*/
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress; /**< Register base address */
u32 AckBeforeService; /**< Ack location per interrupt */
int FastIntr; /**< Fast Interrupt enabled */
u32 IntVectorAddr; /**< Interrupt Vector Address */
int NumberofIntrs; /**< Number of Interrupt sources */
u8 VectorAddrWidth; /**< Width of vector address */
u32 Options; /**< Device options */
int IntcType; /**< Intc type 0 - No Cascade Mode
1 - primary instance
2 - secondary instance
3 - last instance */
/** Static vector table of interrupt handlers */
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS];
#else
XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS];
#endif
} XIntc_Config;
/**
* The XIntc driver instance data. The user is required to allocate a
* variable of this type for every intc device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
UINTPTR BaseAddress; /**< Base address of registers */
u32 IsReady; /**< Device is initialized and ready */
u32 IsStarted; /**< Device has been started */
u32 UnhandledInterrupts; /**< Intc Statistics */
XIntc_Config *CfgPtr; /**< Pointer to instance config entry */
} XIntc;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Required functions in xintc.c
*/
int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId);
int XIntc_Start(XIntc * InstancePtr, u8 Mode);
void XIntc_Stop(XIntc * InstancePtr);
int XIntc_Connect(XIntc * InstancePtr, u8 Id,
XInterruptHandler Handler, void *CallBackRef);
void XIntc_Disconnect(XIntc * InstancePtr, u8 Id);
void XIntc_Enable(XIntc * InstancePtr, u8 Id);
void XIntc_Disable(XIntc * InstancePtr, u8 Id);
void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id);
XIntc_Config *XIntc_LookupConfig(u16 DeviceId);
int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
XFastInterruptHandler Handler);
void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id);
/*
* Interrupt functions in xintr_intr.c
*/
void XIntc_VoidInterruptHandler(void);
void XIntc_InterruptHandler(XIntc * InstancePtr);
/*
* Options functions in xintc_options.c
*/
int XIntc_SetOptions(XIntc * InstancePtr, u32 Options);
u32 XIntc_GetOptions(XIntc * InstancePtr);
/*
* Self-test functions in xintc_selftest.c
*/
int XIntc_SelfTest(XIntc * InstancePtr);
int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
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/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_i.h
* @addtogroup intc_v3_9
* @{
*
* This file contains data which is shared between files and internal to the
* XIntc component. It is intended for internal use only.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b jhl 02/06/02 First release
* 1.00b jhl 04/24/02 Moved register definitions to xintc_l.h
* 1.00c rpm 10/17/03 New release. Removed extern of global, single instance
* pointer.
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
* </pre>
*
******************************************************************************/
#ifndef XINTC_I_H /* prevent circular inclusions */
#define XINTC_I_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern u32 XIntc_BitPosMask[];
extern XIntc_Config XIntc_ConfigTable[];
#ifdef __cplusplus
}
#endif
#endif
/** @} */
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/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_l.h
* @addtogroup intc_v3_9
* @{
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
*
* Note that users of the driver interface given in this file can register
* an interrupt handler dynamically (at run-time) using the
* XIntc_RegisterHandler() function.
* User of the driver interface given in xintc.h should still use
* XIntc_Connect(), as always.
* Also see the discussion of the interrupt vector tables in xintc.h.
*
* There are currently two interrupt handlers specified in this interface.
*
* - XIntc_LowLevelInterruptHandler() is a handler without any arguments that
* is used in cases where there is a single interrupt controller device in
* the system and the handler cannot be passed an argument. This function is
* provided mostly for backward compatibility.
*
* - XIntc_DeviceInterruptHandler() is a handler that takes a device ID as an
* argument, indicating which interrupt controller device in the system is
* causing the interrupt - thereby supporting multiple interrupt controllers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00b jhl 04/24/02 First release
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. _m is removed from all
* the macro definitions.
* 2.04a bss 01/13/12 Updated for adding defines for IMR and IVAR for
* the FAST Interrupt
* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.07a bss 10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.
* 3.5 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototypes of XIntc_RegisterFastHandler,
* XIntc_SetIntrSvcOption, XIntc_RegisterHandler APIs.
*
* </pre>
*
******************************************************************************/
#ifndef XINTC_L_H /* prevent circular inclusions */
#define XINTC_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xil_io.h"
/*
* XPAR_XINTC_USE_DCR_BRIDGE has to be set to 1 if the Intc device will be
* accessed through a DCR bus connected to a bridge.
*/
#define XPAR_XINTC_USE_DCR_BRIDGE 0
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#include "xio_dcr.h"
#endif
/************************** Constant Definitions *****************************/
/* define the offsets from the base address for all the registers of the
* interrupt controller, some registers may be optional in the hardware device
*/
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
#define XIN_IPR_OFFSET 1 /* Interrupt Pending Register */
#define XIN_IER_OFFSET 2 /* Interrupt Enable Register */
#define XIN_IAR_OFFSET 3 /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET 4 /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET 5 /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET 6 /* Interrupt Vector Register */
#define XIN_MER_OFFSET 7 /* Master Enable Register */
#define XIN_IMR_OFFSET 8 /* Interrupt Mode Register , this is present
* only for Fast Interrupt */
#define XIN_IVAR_OFFSET 64 /* Interrupt Vector Address Register
* Interrupt 0 Offest, this is present
* only for Fast Interrupt */
#else /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
#define XIN_IPR_OFFSET 4 /* Interrupt Pending Register */
#define XIN_IER_OFFSET 8 /* Interrupt Enable Register */
#define XIN_IAR_OFFSET 12 /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET 16 /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET 20 /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET 24 /* Interrupt Vector Register */
#define XIN_MER_OFFSET 28 /* Master Enable Register */
#define XIN_IMR_OFFSET 32 /* Interrupt Mode Register , this is present
* only for Fast Interrupt */
#define XIN_ILR_OFFSET 36 /* Interrupt level register */
#define XIN_IVAR_OFFSET 0x100 /* Interrupt Vector Address Register
* Interrupt 0 Offest, this is present
* only for Fast Interrupt */
#define XIN_IVEAR_OFFSET 0x200 /* Interrupt Vector Extended Address
Register */
#endif /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
/* Bit definitions for the bits of the MER register */
#define XIN_INT_MASTER_ENABLE_MASK 0x1UL
#define XIN_INT_HARDWARE_ENABLE_MASK 0x2UL /* once set cannot be cleared */
/**************************** Type Definitions *******************************/
/* The following data type defines each entry in an interrupt vector table.
* The callback reference is the base address of the interrupting device
* for the driver interface given in this file and an instance pointer for the
* driver interface given in xintc.h file.
*/
typedef struct {
XInterruptHandler Handler;
void *CallBackRef;
} XIntc_VectorTableEntry;
typedef void (*XFastInterruptHandler) (void);
/***************** Macros (Inline Functions) Definitions *********************/
/*
* Define the appropriate I/O access method to memory mapped I/O or DCR.
*/
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#define XIntc_In32 XIo_DcrIn
#define XIntc_Out32 XIo_DcrOut
#else
#define XIntc_In32 Xil_In32
#define XIntc_Out32 Xil_Out32
#define XIntc_Out64 Xil_Out64
#endif
/****************************************************************************/
/**
*
* Enable all interrupts in the Master Enable register of the interrupt
* controller. The interrupt controller defaults to all interrupts disabled
* from reset such that this macro must be used to enable interrupts.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note C-style signature:
* void XIntc_MasterEnable(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_MasterEnable(BaseAddress) \
XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \
XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK)
/****************************************************************************/
/**
*
* Disable all interrupts in the Master Enable register of the interrupt
* controller.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note C-style signature:
* void XIntc_MasterDisable(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_MasterDisable(BaseAddress) \
XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)
/****************************************************************************/
/**
*
* Enable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param EnableMask is the 32-bit value to write to the enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only the bits which are set in the mask will enable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask);
*
*****************************************************************************/
#define XIntc_EnableIntr(BaseAddress, EnableMask) \
XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
/****************************************************************************/
/**
*
* Disable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param DisableMask is the 32-bit value to write to the enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only the bits which are set in the mask will disable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask);
*
*****************************************************************************/
#define XIntc_DisableIntr(BaseAddress, DisableMask) \
XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
/****************************************************************************/
/**
*
* Acknowledge specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param AckMask is the 32-bit value to write to the acknowledge
* register. Each bit of the mask corresponds to an interrupt input
* signal that is connected to the interrupt controller (INT0 =
* LSB). Only the bits which are set in the mask will acknowledge
* interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_AckIntr(u32 BaseAddress, u32 AckMask);
*
*****************************************************************************/
#define XIntc_AckIntr(BaseAddress, AckMask) \
XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
/****************************************************************************/
/**
*
* Get the interrupt status from the interrupt controller which indicates
* which interrupts are active and enabled.
*
* @param BaseAddress is the base address of the device
*
* @return The 32-bit contents of the interrupt status register. Each bit
* corresponds to an interrupt input signal that is connected to
* the interrupt controller (INT0 = LSB). Bits which are set
* indicate an active interrupt which is also enabled.
*
* @note C-style signature:
* u32 XIntc_GetIntrStatus(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_GetIntrStatus(BaseAddress) \
(XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) & \
XIntc_In32((BaseAddress) + XIN_IER_OFFSET))
/************************** Function Prototypes ******************************/
/*
* Interrupt controller handlers, to be connected to processor exception
* handling code.
*/
void XIntc_LowLevelInterruptHandler(void);
void XIntc_DeviceInterruptHandler(void *DeviceId);
/* Various configuration functions */
void XIntc_SetIntrSvcOption(UINTPTR BaseAddress, int Option);
void XIntc_RegisterHandler(UINTPTR BaseAddress, int InterruptId,
XInterruptHandler Handler, void *CallBackRef);
void XIntc_RegisterFastHandler(UINTPTR BaseAddress, u8 Id,
XFastInterruptHandler FastHandler);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xio.h
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/******************************************************************************
*
* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xio.h
* @addtogroup cpu_v2_9
* @{
* @details
*
* This file contains the interface for the XIo component, which encapsulates
* the Input/Output functions for processors that do not require any special
* I/O handling.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
* 1.00a xd 11/04/04 Improved support for doxygen
* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
* and bumped version to 1.01.a.
* 1.11a mta 03/21/07 Updated to new coding style.
* 1.11b va 04/17/08 Updated Tcl for better CORE_CLOCK_FREQ_HZ definition
* 1.11a sdm 03/12/09 Updated Tcl to define correct value for CORE_CLOCK_FREQ_HZ
* (CR #502010)
* 1.13a sdm 03/12/09 Updated the Tcl to pull appropriate libraries for Little
* Endian Microblaze
* 2.0 adk 19/12/13 Updated as per the New Tcl API's
* 2.1 bss 04/14/14 Updated tcl to copy libgloss.a and libgcc.a libraries
* 2.1 bss 04/29/14 Updated to copy libgloss.a if exists otherwise libxil.a
* CR#794205
* 2.2 bss 08/04/14 Updated driver tcl to add protection macros for
* xparameters.h (CR#802257).
* 2.3 sk 12/15/14 Updated mdd file to delete �ffunction-sections &
* -fdata-sections flags from extra compiler flags CR#838648
* Changed default os to latest version in mdd file.
* 2.4 nsk 11/05/15 Updated generate and post_generate procs in driver tcl
* not to generate cpu macros, when microblaze is connected
* as one of the streaming slaves to itself. CR#876604
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent items (memory-mapped or
* non-memory-mapped I/O).
*
******************************************************************************/
#ifndef XIO_H /* prevent circular inclusions */
#define XIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* Typedef for an I/O address. Typically correlates to the width of the
* address bus.
*/
typedef u32 XIo_Address;
/***************** Macros (Inline Functions) Definitions *********************/
/*
* The following macros allow optimized I/O operations for memory mapped I/O.
* It should be noted that macros cannot be used if synchronization of the I/O
* operation is needed as it will likely break some code.
*/
/*****************************************************************************/
/**
*
* Performs an input operation for an 8-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In8(InputPtr) (*(volatile u8 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In16(InputPtr) (*(volatile u16 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In32(InputPtr) (*(volatile u32 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an output operation for an 8-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out8(OutputPtr, Value) \
(*(volatile u8 *)((OutputPtr)) = (Value))
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out16(OutputPtr, Value) \
(*(volatile u16 *)((OutputPtr)) = (Value))
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out32(OutputPtr, Value) \
(*(volatile u32 *)((OutputPtr)) = (Value))
/* The following macros allow the software to be transportable across
* processors which use big or little endian memory models.
*
* Defined first is a no-op endian conversion macro. This macro is not to
* be used directly by software. Instead, the XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX macros below are to be used to allow the endian
* conversion to only be performed when necessary
*/
#define XIo_EndianNoop(Source, DestPtr) (*DestPtr = Source)
#ifdef XLITTLE_ENDIAN
#define XIo_ToLittleEndian16 XIo_EndianNoop
#define XIo_ToLittleEndian32 XIo_EndianNoop
#define XIo_FromLittleEndian16 XIo_EndianNoop
#define XIo_FromLittleEndian32 XIo_EndianNoop
#define XIo_ToBigEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToBigEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromBigEndian16 XIo_ToBigEndian16
#define XIo_FromBigEndian32 XIo_ToBigEndian32
#else
#define XIo_ToLittleEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToLittleEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromLittleEndian16 XIo_ToLittleEndian16
#define XIo_FromLittleEndian32 XIo_ToLittleEndian32
#define XIo_ToBigEndian16 XIo_EndianNoop
#define XIo_ToBigEndian32 XIo_EndianNoop
#define XIo_FromBigEndian16 XIo_EndianNoop
#define XIo_FromBigEndian32 XIo_EndianNoop
#endif
/************************** Function Prototypes ******************************/
/* The following functions allow the software to be transportable across
* processors which use big or little endian memory models. These functions
* should not be directly called, but the macros XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX should be used to allow the endian conversion to only
* be performed when necessary.
*/
void XIo_EndianSwap16(u16 Source, u16 *DestPtr);
void XIo_EndianSwap32(u32 Source, u32 *DestPtr);
/* The following functions handle IO addresses where data must be swapped
* They cannot be implemented as macros
*/
u16 XIo_InSwap16(XIo_Address InAddress);
u32 XIo_InSwap32(XIo_Address InAddress);
void XIo_OutSwap16(XIo_Address OutAddress, u16 Value);
void XIo_OutSwap32(XIo_Address OutAddress, u32 Value);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
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#ifndef XPARAMETERS_H /* prevent circular inclusions */
#define XPARAMETERS_H /* by using protection macros */
/* Definitions for bus frequencies */
#define XPAR_CPU_M_AXI_DP_FREQ_HZ 150000000
/******************************************************************/
/* Canonical definitions for bus frequencies */
/******************************************************************/
#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 150000000
#define XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ 150000000
/******************************************************************/
/* Definitions for peripheral MICROBLAZE_PS */
#define XPAR_MICROBLAZE_PS_ADDR_SIZE 32
#define XPAR_MICROBLAZE_PS_ADDR_TAG_BITS 17
#define XPAR_MICROBLAZE_PS_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_PS_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_PS_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_PS_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_PS_ASYNC_WAKEUP 3
#define XPAR_MICROBLAZE_PS_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_PS_BASE_VECTORS 0x0000000000000000
#define XPAR_MICROBLAZE_PS_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_PS_CACHE_BYTE_SIZE 16384
#define XPAR_MICROBLAZE_PS_DADDR_SIZE 32
#define XPAR_MICROBLAZE_PS_DATA_SIZE 32
#define XPAR_MICROBLAZE_PS_DCACHE_ADDR_TAG 17
#define XPAR_MICROBLAZE_PS_DCACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_PS_DCACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_PS_DCACHE_BYTE_SIZE 16384
#define XPAR_MICROBLAZE_PS_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_PS_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_PS_DCACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_PS_DCACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_PS_DCACHE_USE_WRITEBACK 1
#define XPAR_MICROBLAZE_PS_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_PS_DC_AXI_MON 0
#define XPAR_MICROBLAZE_PS_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_PS_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_PS_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_PS_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_PS_DEBUG_INTERFACE 0
#define XPAR_MICROBLAZE_PS_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_PS_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_PS_DEBUG_TRACE_ASYNC_RESET 0
#define XPAR_MICROBLAZE_PS_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_PS_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_PS_DP_AXI_MON 0
#define XPAR_MICROBLAZE_PS_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_PS_D_AXI 1
#define XPAR_MICROBLAZE_PS_D_LMB 1
#define XPAR_MICROBLAZE_PS_D_LMB_MON 0
#define XPAR_MICROBLAZE_PS_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_PS_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_PS_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_PS_ENDIANNESS 1
#define XPAR_MICROBLAZE_PS_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_PS_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_PS_FREQ 150000000
#define XPAR_MICROBLAZE_PS_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_PS_FSL_LINKS 0
#define XPAR_MICROBLAZE_PS_IADDR_SIZE 32
#define XPAR_MICROBLAZE_PS_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_PS_ICACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_PS_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_PS_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_PS_ICACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_PS_ICACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_PS_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_PS_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_PS_IC_AXI_MON 0
#define XPAR_MICROBLAZE_PS_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_PS_IMPRECISE_EXCEPTIONS 0
#define XPAR_MICROBLAZE_PS_INSTR_SIZE 32
#define XPAR_MICROBLAZE_PS_INTERCONNECT 2
#define XPAR_MICROBLAZE_PS_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_PS_INTERRUPT_MON 0
#define XPAR_MICROBLAZE_PS_IP_AXI_MON 0
#define XPAR_MICROBLAZE_PS_I_AXI 0
#define XPAR_MICROBLAZE_PS_I_LMB 1
#define XPAR_MICROBLAZE_PS_I_LMB_MON 0
#define XPAR_MICROBLAZE_PS_LMB_DATA_SIZE 32
#define XPAR_MICROBLAZE_PS_LOCKSTEP_MASTER 0
#define XPAR_MICROBLAZE_PS_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_PS_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_PS_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_MMU_DTLB_SIZE 2
#define XPAR_MICROBLAZE_PS_MMU_ITLB_SIZE 1
#define XPAR_MICROBLAZE_PS_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_PS_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_PS_MMU_ZONES 2
#define XPAR_MICROBLAZE_PS_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_PS_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_PS_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_PS_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_DC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_PS_M_AXI_DC_USER_VALUE 31
#define XPAR_MICROBLAZE_PS_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_PS_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_PS_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_PS_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_PS_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_IC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_PS_M_AXI_IC_USER_VALUE 31
#define XPAR_MICROBLAZE_PS_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_I_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_PS_NUMBER_OF_PC_BRK 2
#define XPAR_MICROBLAZE_PS_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_PS_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_CLK 2
#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_DBG_TRACE_CLK 2
#define XPAR_MICROBLAZE_PS_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_PS_OPTIMIZATION 0
#define XPAR_MICROBLAZE_PS_PC_WIDTH 32
#define XPAR_MICROBLAZE_PS_PIADDR_SIZE 32
#define XPAR_MICROBLAZE_PS_PVR 0
#define XPAR_MICROBLAZE_PS_PVR_USER1 0x00
#define XPAR_MICROBLAZE_PS_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_PS_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_PS_RESET_MSR_BIP 0
#define XPAR_MICROBLAZE_PS_RESET_MSR_DCE 0
#define XPAR_MICROBLAZE_PS_RESET_MSR_EE 0
#define XPAR_MICROBLAZE_PS_RESET_MSR_EIP 0
#define XPAR_MICROBLAZE_PS_RESET_MSR_ICE 0
#define XPAR_MICROBLAZE_PS_RESET_MSR_IE 0
#define XPAR_MICROBLAZE_PS_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_SCO 0
#define XPAR_MICROBLAZE_PS_TRACE 0
#define XPAR_MICROBLAZE_PS_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_PS_USE_BARREL 1
#define XPAR_MICROBLAZE_PS_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_PS_USE_CONFIG_RESET 0
#define XPAR_MICROBLAZE_PS_USE_DCACHE 1
#define XPAR_MICROBLAZE_PS_USE_DIV 1
#define XPAR_MICROBLAZE_PS_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_PS_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_PS_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_PS_USE_FPU 0
#define XPAR_MICROBLAZE_PS_USE_HW_MUL 1
#define XPAR_MICROBLAZE_PS_USE_ICACHE 1
#define XPAR_MICROBLAZE_PS_USE_INTERRUPT 1
#define XPAR_MICROBLAZE_PS_USE_MMU 0
#define XPAR_MICROBLAZE_PS_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_PS_USE_NON_SECURE 0
#define XPAR_MICROBLAZE_PS_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_PS_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_PS_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_PS_COMPONENT_NAME system_microblaze_ps_0
#define XPAR_MICROBLAZE_PS_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_PS_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_PS_G_TEMPLATE_LIST 9
#define XPAR_MICROBLAZE_PS_G_USE_EXCEPTIONS 1
/******************************************************************/
#define XPAR_CPU_ID 0
#define XPAR_MICROBLAZE_ID 0
#define XPAR_MICROBLAZE_ADDR_SIZE 32
#define XPAR_MICROBLAZE_ADDR_TAG_BITS 17
#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_ASYNC_WAKEUP 3
#define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_BASE_VECTORS 0x0000000000000000
#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 16384
#define XPAR_MICROBLAZE_DADDR_SIZE 32
#define XPAR_MICROBLAZE_DATA_SIZE 32
#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 17
#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 16384
#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 1
#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_DC_AXI_MON 0
#define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_DEBUG_INTERFACE 0
#define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_DEBUG_TRACE_ASYNC_RESET 0
#define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_DP_AXI_MON 0
#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_D_AXI 1
#define XPAR_MICROBLAZE_D_LMB 1
#define XPAR_MICROBLAZE_D_LMB_MON 0
#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_ENDIANNESS 1
#define XPAR_MICROBLAZE_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_FREQ 150000000
#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_FSL_LINKS 0
#define XPAR_MICROBLAZE_IADDR_SIZE 32
#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_IC_AXI_MON 0
#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_IMPRECISE_EXCEPTIONS 0
#define XPAR_MICROBLAZE_INSTR_SIZE 32
#define XPAR_MICROBLAZE_INTERCONNECT 2
#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_INTERRUPT_MON 0
#define XPAR_MICROBLAZE_IP_AXI_MON 0
#define XPAR_MICROBLAZE_I_AXI 0
#define XPAR_MICROBLAZE_I_LMB 1
#define XPAR_MICROBLAZE_I_LMB_MON 0
#define XPAR_MICROBLAZE_LMB_DATA_SIZE 32
#define XPAR_MICROBLAZE_LOCKSTEP_MASTER 0
#define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MMU_DTLB_SIZE 2
#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 1
#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_MMU_ZONES 2
#define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_M_AXI_DC_USER_VALUE 31
#define XPAR_MICROBLAZE_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_M_AXI_IC_USER_VALUE 31
#define XPAR_MICROBLAZE_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 2
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_TRACE_CLK 2
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_OPTIMIZATION 0
#define XPAR_MICROBLAZE_PC_WIDTH 32
#define XPAR_MICROBLAZE_PIADDR_SIZE 32
#define XPAR_MICROBLAZE_PVR 0
#define XPAR_MICROBLAZE_PVR_USER1 0x00
#define XPAR_MICROBLAZE_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_RESET_MSR_BIP 0
#define XPAR_MICROBLAZE_RESET_MSR_DCE 0
#define XPAR_MICROBLAZE_RESET_MSR_EE 0
#define XPAR_MICROBLAZE_RESET_MSR_EIP 0
#define XPAR_MICROBLAZE_RESET_MSR_ICE 0
#define XPAR_MICROBLAZE_RESET_MSR_IE 0
#define XPAR_MICROBLAZE_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_SCO 0
#define XPAR_MICROBLAZE_TRACE 0
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_USE_BARREL 1
#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_USE_CONFIG_RESET 0
#define XPAR_MICROBLAZE_USE_DCACHE 1
#define XPAR_MICROBLAZE_USE_DIV 1
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_USE_FPU 0
#define XPAR_MICROBLAZE_USE_HW_MUL 1
#define XPAR_MICROBLAZE_USE_ICACHE 1
#define XPAR_MICROBLAZE_USE_INTERRUPT 1
#define XPAR_MICROBLAZE_USE_MMU 0
#define XPAR_MICROBLAZE_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_USE_NON_SECURE 0
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_COMPONENT_NAME system_microblaze_ps_0
#define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 9
#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1
/******************************************************************/
/* Definitions for interface PHYC */
#define XPAR_PHYC_BASEADDR 0x44A10000
#define XPAR_PHYC_HIGHADDR 0x44A1FFFF
/* Definitions for interface PHYC */
#define XPAR_PHYC_BASEADDR 0x44A10000
#define XPAR_PHYC_HIGHADDR 0x44A1FFFF
/******************************************************************/
/* Platform specific definitions */
#define PLATFORM_MB
/* Definitions for sleep timer configuration */
#define XSLEEP_TIMER_IS_DEFAULT_TIMER
/******************************************************************/
/* Definitions for driver AXIDMA */
#define XPAR_XAXIDMA_NUM_INSTANCES 1
/* Definitions for peripheral AXI_DMA_C2C */
#define XPAR_AXI_DMA_C2C_DEVICE_ID 0
#define XPAR_AXI_DMA_C2C_BASEADDR 0x41E00000
#define XPAR_AXI_DMA_C2C_HIGHADDR 0x41E0FFFF
#define XPAR_AXI_DMA_C2C_SG_INCLUDE_STSCNTRL_STRM 0
#define XPAR_AXI_DMA_C2C_INCLUDE_MM2S_DRE 1
#define XPAR_AXI_DMA_C2C_INCLUDE_S2MM_DRE 1
#define XPAR_AXI_DMA_C2C_INCLUDE_MM2S 1
#define XPAR_AXI_DMA_C2C_INCLUDE_S2MM 1
#define XPAR_AXI_DMA_C2C_M_AXI_MM2S_DATA_WIDTH 32
#define XPAR_AXI_DMA_C2C_M_AXI_S2MM_DATA_WIDTH 32
#define XPAR_AXI_DMA_C2C_INCLUDE_SG 0
#define XPAR_AXI_DMA_C2C_ENABLE_MULTI_CHANNEL 0
#define XPAR_AXI_DMA_C2C_NUM_MM2S_CHANNELS 1
#define XPAR_AXI_DMA_C2C_NUM_S2MM_CHANNELS 1
#define XPAR_AXI_DMA_C2C_MM2S_BURST_SIZE 64
#define XPAR_AXI_DMA_C2C_S2MM_BURST_SIZE 64
#define XPAR_AXI_DMA_C2C_MICRO_DMA 0
#define XPAR_AXI_DMA_C2C_ADDR_WIDTH 32
#define XPAR_AXI_DMA_C2C_SG_LENGTH_WIDTH 14
/******************************************************************/
/* Canonical definitions for peripheral AXI_DMA_C2C */
#define XPAR_AXIDMA_0_DEVICE_ID XPAR_AXI_DMA_C2C_DEVICE_ID
#define XPAR_AXIDMA_0_BASEADDR 0x41E00000
#define XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM 0
#define XPAR_AXIDMA_0_INCLUDE_MM2S 1
#define XPAR_AXIDMA_0_INCLUDE_MM2S_DRE 1
#define XPAR_AXIDMA_0_M_AXI_MM2S_DATA_WIDTH 32
#define XPAR_AXIDMA_0_INCLUDE_S2MM 1
#define XPAR_AXIDMA_0_INCLUDE_S2MM_DRE 1
#define XPAR_AXIDMA_0_M_AXI_S2MM_DATA_WIDTH 32
#define XPAR_AXIDMA_0_INCLUDE_SG 0
#define XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL 0
#define XPAR_AXIDMA_0_NUM_MM2S_CHANNELS 1
#define XPAR_AXIDMA_0_NUM_S2MM_CHANNELS 1
#define XPAR_AXIDMA_0_MM2S_BURST_SIZE 64
#define XPAR_AXIDMA_0_S2MM_BURST_SIZE 64
#define XPAR_AXIDMA_0_MICRO_DMA 0
#define XPAR_AXIDMA_0_c_addr_width 32
#define XPAR_AXIDMA_0_c_sg_length_width 14
/******************************************************************/
/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 7U
/* Definitions for peripheral ANT_CONFIG_BRAM_CTRL */
#define XPAR_ANT_CONFIG_BRAM_CTRL_DEVICE_ID 0U
#define XPAR_ANT_CONFIG_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_ANT_CONFIG_BRAM_CTRL_ECC 0U
#define XPAR_ANT_CONFIG_BRAM_CTRL_FAULT_INJECT 0U
#define XPAR_ANT_CONFIG_BRAM_CTRL_CE_FAILING_REGISTERS 0U
#define XPAR_ANT_CONFIG_BRAM_CTRL_UE_FAILING_REGISTERS 0U
#define XPAR_ANT_CONFIG_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
#define XPAR_ANT_CONFIG_BRAM_CTRL_CE_COUNTER_WIDTH 0U
#define XPAR_ANT_CONFIG_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
#define XPAR_ANT_CONFIG_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_ANT_CONFIG_BRAM_CTRL_WRITE_ACCESS 0U
#define XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_BASEADDR 0xC0000000U
#define XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_HIGHADDR 0xC0001FFFU
#define XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/* Definitions for peripheral C2C_RX_AXI_BRAM_CTRL */
#define XPAR_C2C_RX_AXI_BRAM_CTRL_DEVICE_ID 1U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_ECC 0U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_FAULT_INJECT 0U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_CE_FAILING_REGISTERS 0U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_UE_FAILING_REGISTERS 0U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_CE_COUNTER_WIDTH 0U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_WRITE_ACCESS 0U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_BASEADDR 0xC6000000U
#define XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_HIGHADDR 0xC6001FFFU
#define XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/* Definitions for peripheral C2C_TX_AXI_BRAM_CTRL */
#define XPAR_C2C_TX_AXI_BRAM_CTRL_DEVICE_ID 2U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_ECC 0U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_FAULT_INJECT 0U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_CE_FAILING_REGISTERS 0U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_UE_FAILING_REGISTERS 0U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_CE_COUNTER_WIDTH 0U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_WRITE_ACCESS 0U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_BASEADDR 0xC8000000U
#define XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_HIGHADDR 0xC8001FFFU
#define XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/* Definitions for peripheral MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID 3U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH 32U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 2U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x00000000U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFFU
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/* Definitions for peripheral MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID 4U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH 32U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS 2U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR 0x00000000U
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFFU
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/* Definitions for peripheral RX_FRAME_BRAM_CTRL */
#define XPAR_RX_FRAME_BRAM_CTRL_DEVICE_ID 5U
#define XPAR_RX_FRAME_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_RX_FRAME_BRAM_CTRL_ECC 0U
#define XPAR_RX_FRAME_BRAM_CTRL_FAULT_INJECT 0U
#define XPAR_RX_FRAME_BRAM_CTRL_CE_FAILING_REGISTERS 0U
#define XPAR_RX_FRAME_BRAM_CTRL_UE_FAILING_REGISTERS 0U
#define XPAR_RX_FRAME_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
#define XPAR_RX_FRAME_BRAM_CTRL_CE_COUNTER_WIDTH 0U
#define XPAR_RX_FRAME_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
#define XPAR_RX_FRAME_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_RX_FRAME_BRAM_CTRL_WRITE_ACCESS 0U
#define XPAR_RX_FRAME_BRAM_CTRL_S_AXI_BASEADDR 0xC4000000U
#define XPAR_RX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0xC4000FFFU
#define XPAR_RX_FRAME_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_RX_FRAME_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/* Definitions for peripheral TX_FRAME_BRAM_CTRL */
#define XPAR_TX_FRAME_BRAM_CTRL_DEVICE_ID 6U
#define XPAR_TX_FRAME_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_TX_FRAME_BRAM_CTRL_ECC 0U
#define XPAR_TX_FRAME_BRAM_CTRL_FAULT_INJECT 0U
#define XPAR_TX_FRAME_BRAM_CTRL_CE_FAILING_REGISTERS 0U
#define XPAR_TX_FRAME_BRAM_CTRL_UE_FAILING_REGISTERS 0U
#define XPAR_TX_FRAME_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
#define XPAR_TX_FRAME_BRAM_CTRL_CE_COUNTER_WIDTH 0U
#define XPAR_TX_FRAME_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
#define XPAR_TX_FRAME_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_TX_FRAME_BRAM_CTRL_WRITE_ACCESS 0U
#define XPAR_TX_FRAME_BRAM_CTRL_S_AXI_BASEADDR 0xC2000000U
#define XPAR_TX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0xC2000FFFU
#define XPAR_TX_FRAME_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_TX_FRAME_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/******************************************************************/
/* Canonical definitions for peripheral ANT_CONFIG_BRAM_CTRL */
#define XPAR_BRAM_0_DEVICE_ID XPAR_ANT_CONFIG_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32U
#define XPAR_BRAM_0_ECC 0U
#define XPAR_BRAM_0_FAULT_INJECT 0U
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_0_WRITE_ACCESS 0U
#define XPAR_BRAM_0_BASEADDR 0xC0000000U
#define XPAR_BRAM_0_HIGHADDR 0xC0001FFFU
#define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU
/* Canonical definitions for peripheral C2C_RX_AXI_BRAM_CTRL */
#define XPAR_BRAM_1_DEVICE_ID XPAR_C2C_RX_AXI_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_1_DATA_WIDTH 32U
#define XPAR_BRAM_1_ECC 0U
#define XPAR_BRAM_1_FAULT_INJECT 0U
#define XPAR_BRAM_1_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_1_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_1_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_1_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_1_WRITE_ACCESS 0U
#define XPAR_BRAM_1_BASEADDR 0xC6000000U
#define XPAR_BRAM_1_HIGHADDR 0xC6001FFFU
#define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU
/* Canonical definitions for peripheral C2C_TX_AXI_BRAM_CTRL */
#define XPAR_BRAM_2_DEVICE_ID XPAR_C2C_TX_AXI_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_2_DATA_WIDTH 32U
#define XPAR_BRAM_2_ECC 0U
#define XPAR_BRAM_2_FAULT_INJECT 0U
#define XPAR_BRAM_2_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_2_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_2_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_2_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_2_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_2_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_2_WRITE_ACCESS 0U
#define XPAR_BRAM_2_BASEADDR 0xC8000000U
#define XPAR_BRAM_2_HIGHADDR 0xC8001FFFU
#define XPAR_BRAM_2_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_2_CTRL_HIGHADDR 0xFFFFFFFEU
/* Canonical definitions for peripheral MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
#define XPAR_BRAM_3_DEVICE_ID XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID
#define XPAR_BRAM_3_DATA_WIDTH 32U
#define XPAR_BRAM_3_ECC 0U
#define XPAR_BRAM_3_FAULT_INJECT 0U
#define XPAR_BRAM_3_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_3_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_3_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_3_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_3_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_3_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_BRAM_3_WRITE_ACCESS 2U
#define XPAR_BRAM_3_BASEADDR 0x00000000U
#define XPAR_BRAM_3_HIGHADDR 0x0003FFFFU
#define XPAR_BRAM_3_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_3_CTRL_HIGHADDR 0xFFFFFFFEU
/* Canonical definitions for peripheral MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
#define XPAR_BRAM_4_DEVICE_ID XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID
#define XPAR_BRAM_4_DATA_WIDTH 32U
#define XPAR_BRAM_4_ECC 0U
#define XPAR_BRAM_4_FAULT_INJECT 0U
#define XPAR_BRAM_4_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_4_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_4_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_4_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_4_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_4_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_BRAM_4_WRITE_ACCESS 2U
#define XPAR_BRAM_4_BASEADDR 0x00000000U
#define XPAR_BRAM_4_HIGHADDR 0x0003FFFFU
#define XPAR_BRAM_4_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_4_CTRL_HIGHADDR 0xFFFFFFFEU
/* Canonical definitions for peripheral RX_FRAME_BRAM_CTRL */
#define XPAR_BRAM_5_DEVICE_ID XPAR_RX_FRAME_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_5_DATA_WIDTH 32U
#define XPAR_BRAM_5_ECC 0U
#define XPAR_BRAM_5_FAULT_INJECT 0U
#define XPAR_BRAM_5_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_5_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_5_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_5_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_5_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_5_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_5_WRITE_ACCESS 0U
#define XPAR_BRAM_5_BASEADDR 0xC4000000U
#define XPAR_BRAM_5_HIGHADDR 0xC4000FFFU
#define XPAR_BRAM_5_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_5_CTRL_HIGHADDR 0xFFFFFFFEU
/* Canonical definitions for peripheral TX_FRAME_BRAM_CTRL */
#define XPAR_BRAM_6_DEVICE_ID XPAR_TX_FRAME_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_6_DATA_WIDTH 32U
#define XPAR_BRAM_6_ECC 0U
#define XPAR_BRAM_6_FAULT_INJECT 0U
#define XPAR_BRAM_6_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_6_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_6_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_6_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_6_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_6_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_6_WRITE_ACCESS 0U
#define XPAR_BRAM_6_BASEADDR 0xC2000000U
#define XPAR_BRAM_6_HIGHADDR 0xC2000FFFU
#define XPAR_BRAM_6_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_6_CTRL_HIGHADDR 0xFFFFFFFEU
/******************************************************************/
/* Definitions for peripheral AXI_SPI_ENGINE_AXI_SPI_ENGINE */
#define XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR 0x44A00000
#define XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_HIGHADDR 0x44A0FFFF
/******************************************************************/
/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 3
/* Definitions for peripheral AXI_GPIO */
#define XPAR_AXI_GPIO_BASEADDR 0x40000000
#define XPAR_AXI_GPIO_HIGHADDR 0x4000FFFF
#define XPAR_AXI_GPIO_DEVICE_ID 0
#define XPAR_AXI_GPIO_INTERRUPT_PRESENT 0
#define XPAR_AXI_GPIO_IS_DUAL 1
/* Definitions for peripheral STATUS_GPIO_I */
#define XPAR_STATUS_GPIO_I_BASEADDR 0x40010000
#define XPAR_STATUS_GPIO_I_HIGHADDR 0x4001FFFF
#define XPAR_STATUS_GPIO_I_DEVICE_ID 1
#define XPAR_STATUS_GPIO_I_INTERRUPT_PRESENT 0
#define XPAR_STATUS_GPIO_I_IS_DUAL 1
/* Definitions for peripheral STATUS_GPIO_O */
#define XPAR_STATUS_GPIO_O_BASEADDR 0x40020000
#define XPAR_STATUS_GPIO_O_HIGHADDR 0x4002FFFF
#define XPAR_STATUS_GPIO_O_DEVICE_ID 2
#define XPAR_STATUS_GPIO_O_INTERRUPT_PRESENT 0
#define XPAR_STATUS_GPIO_O_IS_DUAL 1
/******************************************************************/
/* Canonical definitions for peripheral AXI_GPIO */
#define XPAR_GPIO_0_BASEADDR 0x40000000
#define XPAR_GPIO_0_HIGHADDR 0x4000FFFF
#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_DEVICE_ID
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_GPIO_0_IS_DUAL 1
/* Canonical definitions for peripheral STATUS_GPIO_I */
#define XPAR_GPIO_1_BASEADDR 0x40010000
#define XPAR_GPIO_1_HIGHADDR 0x4001FFFF
#define XPAR_GPIO_1_DEVICE_ID XPAR_STATUS_GPIO_I_DEVICE_ID
#define XPAR_GPIO_1_INTERRUPT_PRESENT 0
#define XPAR_GPIO_1_IS_DUAL 1
/* Canonical definitions for peripheral STATUS_GPIO_O */
#define XPAR_GPIO_2_BASEADDR 0x40020000
#define XPAR_GPIO_2_HIGHADDR 0x4002FFFF
#define XPAR_GPIO_2_DEVICE_ID XPAR_STATUS_GPIO_O_DEVICE_ID
#define XPAR_GPIO_2_INTERRUPT_PRESENT 0
#define XPAR_GPIO_2_IS_DUAL 1
/******************************************************************/
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 6
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_HAS_SIE 1
#define XPAR_XINTC_HAS_CIE 1
#define XPAR_XINTC_HAS_IVR 1
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1
/* Definitions for peripheral AXI_INTC */
#define XPAR_AXI_INTC_DEVICE_ID 0
#define XPAR_AXI_INTC_BASEADDR 0x41200000
#define XPAR_AXI_INTC_HIGHADDR 0x4120FFFF
#define XPAR_AXI_INTC_KIND_OF_INTR 0xFFFFFFC0
#define XPAR_AXI_INTC_HAS_FAST 0
#define XPAR_AXI_INTC_IVAR_RESET_VALUE 0x0000000000000010
#define XPAR_AXI_INTC_NUM_INTR_INPUTS 6
#define XPAR_AXI_INTC_ADDR_WIDTH 32
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_AXI_INTC_DEVICE_ID
#define XPAR_AXI_INTC_TYPE 0U
#define XPAR_SYSTEM_PHY_IRQ_MASK 0X000001U
#define XPAR_AXI_INTC_SYSTEM_PHY_IRQ_INTR 0U
#define XPAR_AXI_DMA_C2C_MM2S_INTROUT_MASK 0X000002U
#define XPAR_AXI_INTC_AXI_DMA_C2C_MM2S_INTROUT_INTR 1U
#define XPAR_AXI_DMA_C2C_S2MM_INTROUT_MASK 0X000004U
#define XPAR_AXI_INTC_AXI_DMA_C2C_S2MM_INTROUT_INTR 2U
#define XPAR_SYSTEM_PHY_5MS_MASK 0X000008U
#define XPAR_AXI_INTC_SYSTEM_PHY_5MS_INTR 3U
#define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000010U
#define XPAR_AXI_INTC_AXI_TIMER_0_INTERRUPT_INTR 4U
#define XPAR_XADC_WIZ_0_IP2INTC_IRPT_MASK 0X000020U
#define XPAR_AXI_INTC_XADC_WIZ_0_IP2INTC_IRPT_INTR 5U
/******************************************************************/
/* Canonical definitions for peripheral AXI_INTC */
#define XPAR_INTC_0_DEVICE_ID XPAR_AXI_INTC_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0x41200000U
#define XPAR_INTC_0_HIGHADDR 0x4120FFFFU
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFC0U
#define XPAR_INTC_0_HAS_FAST 0U
#define XPAR_INTC_0_IVAR_RESET_VALUE 0x0000000000000010U
#define XPAR_INTC_0_NUM_INTR_INPUTS 6U
#define XPAR_INTC_0_ADDR_WIDTH 32U
#define XPAR_INTC_0_INTC_TYPE 0U
#define XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID XPAR_AXI_INTC_AXI_DMA_C2C_MM2S_INTROUT_INTR
#define XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID XPAR_AXI_INTC_AXI_DMA_C2C_S2MM_INTROUT_INTR
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_AXI_INTC_AXI_TIMER_0_INTERRUPT_INTR
#define XPAR_INTC_0_SYSMON_0_VEC_ID XPAR_AXI_INTC_XADC_WIZ_0_IP2INTC_IRPT_INTR
/******************************************************************/
/* Definitions for driver SYSMON */
#define XPAR_XSYSMON_NUM_INSTANCES 1U
/* Definitions for peripheral XADC_WIZ_0 */
#define XPAR_XADC_WIZ_0_IP_TYPE 0U
#define XPAR_XADC_WIZ_0_DEVICE_ID 0U
#define XPAR_XADC_WIZ_0_BASEADDR 0x44A20000U
#define XPAR_XADC_WIZ_0_HIGHADDR 0x44A2FFFFU
#define XPAR_XADC_WIZ_0_INCLUDE_INTR 1U
/******************************************************************/
/* Canonical definitions for peripheral XADC_WIZ_0 */
#define XPAR_SYSMON_0_IP_TYPE 0U
#define XPAR_SYSMON_0_DEVICE_ID XPAR_XADC_WIZ_0_DEVICE_ID
#define XPAR_SYSMON_0_BASEADDR 0x44A20000U
#define XPAR_SYSMON_0_HIGHADDR 0x44A2FFFFU
#define XPAR_SYSMON_0_INCLUDE_INTR 1U
/******************************************************************/
/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1U
/* Definitions for peripheral AXI_TIMER_0 */
#define XPAR_AXI_TIMER_0_DEVICE_ID 0U
#define XPAR_AXI_TIMER_0_BASEADDR 0x41C00000U
#define XPAR_AXI_TIMER_0_HIGHADDR 0x41C0FFFFU
#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 150000000U
/******************************************************************/
/* Canonical definitions for peripheral AXI_TIMER_0 */
#define XPAR_TMRCTR_0_DEVICE_ID 0U
#define XPAR_TMRCTR_0_BASEADDR 0x41C00000U
#define XPAR_TMRCTR_0_HIGHADDR 0x41C0FFFFU
#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ
/******************************************************************/
#endif /* end of protection macro */
datalink814_sp/bsp/microblaze_ps/include/xplatform_info.h
+120
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/******************************************************************************
*
* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xplatform_info.h
*
* @addtogroup common_platform_info APIs to Get Platform Information
*
* The xplatform_info.h file contains definitions for various available Xilinx&reg;
* platforms. Also, it contains prototype of APIs, which can be used to get the
* platform information.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- --------- -------------------------------------------------------
* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
* function for PMUFW.
* </pre>
*
******************************************************************************/
#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
#define XPLATFORM_INFO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#if defined (versal)
#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
XPAR_PMC_TAP_VERSION_OFFSET)
#else
#define XPAR_CSU_BASEADDR 0xFFCA0000U
#define XPAR_CSU_VER_OFFSET 0x00000044U
#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
XPAR_CSU_VER_OFFSET)
#endif
#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
#define XPLAT_ZYNQ_ULTRA_MP 0x1
#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
#define XPLAT_ZYNQ 0x4
#define XPLAT_MICROBLAZE 0x5
#define XPLAT_versal 0x6U
#define XPS_VERSION_1 0x0
#define XPS_VERSION_2 0x1
#define XPLAT_INFO_MASK (0xF)
#if defined (versal)
#define XPS_VERSION_INFO_MASK 0xFF00U
#define XPS_VERSION_INFO_SHIFT 0x8U
#define XPLAT_INFO_SHIFT 0x18U
#else
#define XPS_VERSION_INFO_MASK (0xF)
#define XPS_VERSION_INFO_SHIFT 0x0U
#define XPLAT_INFO_SHIFT 0xCU
#endif
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
u32 XGetPlatform_Info(void);
#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
u32 XGetPSVersion_Info();
#endif
#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
u32 XGet_Zynq_UltraMp_Platform_info();
#endif
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_platform_info".
*/
datalink814_sp/bsp/microblaze_ps/include/xstatus.h
+533
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/******************************************************************************
*
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xstatus.h
*
* @addtogroup common_status_codes Xilinx&reg; software status codes
*
* The xstatus.h file contains the Xilinx&reg; software status codes.These codes are
* used throughout the Xilinx device drivers.
*
* @{
******************************************************************************/
#ifndef XSTATUS_H /* prevent circular inclusions */
#define XSTATUS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/*********************** Common statuses 0 - 500 *****************************/
/**
@name Common Status Codes for All Device Drivers
@{
*/
#define XST_SUCCESS 0L
#define XST_FAILURE 1L
#define XST_DEVICE_NOT_FOUND 2L
#define XST_DEVICE_BLOCK_NOT_FOUND 3L
#define XST_INVALID_VERSION 4L
#define XST_DEVICE_IS_STARTED 5L
#define XST_DEVICE_IS_STOPPED 6L
#define XST_FIFO_ERROR 7L /*!< An error occurred during an
operation with a FIFO such as
an underrun or overrun, this
error requires the device to
be reset */
#define XST_RESET_ERROR 8L /*!< An error occurred which requires
the device to be reset */
#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
typically requires the device
using the DMA to be reset */
#define XST_NOT_POLLED 10L /*!< The device is not configured for
polled mode operation */
#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
the specified data into */
#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
to hold the expected data */
#define XST_NO_DATA 13L /*!< There was no data available */
#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
expected value */
#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
into the function */
#define XST_NOT_SGDMA 16L /*!< The device is not configured for
scatter-gather DMA operation */
#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
registered */
#define XST_NO_FEATURE 19L /*!< Device is not configured with
the requested feature */
#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
interrupt mode operation */
#define XST_DEVICE_BUSY 21L /*!< Device is busy */
#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
have maxed out */
#define XST_IS_STARTED 23L /*!< Used when part of device is
already started i.e.
sub channel */
#define XST_IS_STOPPED 24L /*!< Used when part of device is
already stopped i.e.
sub channel */
#define XST_DATA_LOST 26L /*!< Driver defined error */
#define XST_RECV_ERROR 27L /*!< Generic receive error */
#define XST_SEND_ERROR 28L /*!< Generic transmit error */
#define XST_NOT_ENABLED 29L /*!< A requested service is not
available because it has not
been enabled */
#define XST_NO_ACCESS 30L /* Generic access error */
/** @} */
/***************** Utility Component statuses 401 - 500 *********************/
/**
@name Utility Component Status Codes 401 - 500
@{
*/
#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
/** @} */
/***************** Common Components statuses 501 - 1000 *********************/
/**
@name Packet Fifo Status Codes 501 - 510
@{
*/
/********************* Packet Fifo statuses 501 - 510 ************************/
#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
was invalid after reset */
#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
* empty and full simultaneously
*/
/** @} */
/**
@name DMA Status Codes 511 - 530
@{
*/
/************************** DMA statuses 511 - 530 ***************************/
#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
failed */
#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
was invalid after reset */
#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
no buffer descriptors ready
to be processed */
#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of
the scatter gather list are
being used */
#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
descriptor which is to be
copied over in the scatter
list is locked */
#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
put into the scatter gather
list to be commited */
#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
specified was larger than the
total # of buffer descriptors
in the scatter gather list */
#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
already been created */
#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
been created */
#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
being started was not committed
to the list */
#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
has already been used by the
hardware so it can't be reused
*/
#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
error */
#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
error */
/** @} */
/**
@name IPIF Status Codes Codes 531 - 550
@{
*/
/************************** IPIF statuses 531 - 550 ***************************/
#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
was passed into the function */
#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
reset was not valid */
#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
status register did not read
back correctly */
#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
register did not reset when
acked */
#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
register was not updated when
other registers changed */
#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
status register did not read
back correctly */
#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
did not reset when acked */
#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
not updated correctly when other
registers changed */
#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
register did not indicate the
expected value */
#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
did not indicate the expected
value */
#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
/** @} */
/****************** Device specific statuses 1001 - 4095 *********************/
/**
@name Ethernet Status Codes 1001 - 1050
@{
*/
/********************* Ethernet statuses 1001 - 1050 *************************/
#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
* to hold the minimum number of
* buffers or descriptors */
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
* collision on polled send */
/** @} */
/**
@name UART Status Codes 1051 - 1075
@{
*/
/*********************** UART statuses 1051 - 1075 ***************************/
#define XST_UART
#define XST_UART_INIT_ERROR 1051L
#define XST_UART_START_ERROR 1052L
#define XST_UART_CONFIG_ERROR 1053L
#define XST_UART_TEST_FAIL 1054L
#define XST_UART_BAUD_ERROR 1055L
#define XST_UART_BAUD_RANGE 1056L
/** @} */
/**
@name IIC Status Codes 1076 - 1100
@{
*/
/************************ IIC statuses 1076 - 1100 ***************************/
#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
/* general call address */
#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
/* value after reset not valid */
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
/* value after reset not valid */
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
/* value after reset not valid */
#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
/* value after reset not valid */
#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
/* didn't return value written */
#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
/* didn't return value written */
#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
/* didn't return written value */
#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */
/** @} */
/**
@name ATMC Status Codes 1101 - 1125
@{
*/
/*********************** ATMC statuses 1101 - 1125 ***************************/
#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
controller hit the max value
which requires the statistics
to be cleared */
/** @} */
/**
@name Flash Status Codes 1126 - 1150
@{
*/
/*********************** Flash statuses 1126 - 1150 **************************/
#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
*/
#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
error. Use XFlash_DeviceControl
to retrieve device specific codes
*/
#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
*/
#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
*/
#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
driver */
#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
aborted due to a timeout */
#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
addressible range */
#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
write/erase function with
XFL_NON_BLOCKING_WRITE/ERASE
option cleared */
#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
/** @} */
/**
@name SPI Status Codes 1151 - 1175
@{
*/
/*********************** SPI statuses 1151 - 1175 ****************************/
#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
* selected */
#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
*/
#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
device for status */
/** @} */
/**
@name OPB Arbiter Status Codes 1176 - 1200
@{
*/
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
* one master assigned to two or more
* priorities, or one master not
* assigned to any priority
*/
#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
* priority levels without first
* suspending the use of priority
* levels
*/
#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
* bus parking was not enabled
*/
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
* priority mode to allow the
* priorities to be changed
*/
/** @} */
/**
@name INTC Status Codes 1201 - 1225
@{
*/
/************************ Intc statuses 1201 - 1225 **************************/
#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
/** @} */
/**
@name TmrCtr Status Codes 1226 - 1250
@{
*/
/********************** TmrCtr statuses 1226 - 1250 **************************/
#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
/** @} */
/**
@name WdtTb Status Codes 1251 - 1275
@{
*/
/********************** WdtTb statuses 1251 - 1275 ***************************/
#define XST_WDTTB_TIMER_FAILED 1251L
/** @} */
/**
@name PlbArb status Codes 1276 - 1300
@{
*/
/********************** PlbArb statuses 1276 - 1300 **************************/
#define XST_PLBARB_FAIL_SELFTEST 1276L
/** @} */
/**
@name Plb2Opb Status Codes 1301 - 1325
@{
*/
/********************** Plb2Opb statuses 1301 - 1325 *************************/
#define XST_PLB2OPB_FAIL_SELFTEST 1301L
/** @} */
/**
@name Opb2Plb Status 1326 - 1350
@{
*/
/********************** Opb2Plb statuses 1326 - 1350 *************************/
#define XST_OPB2PLB_FAIL_SELFTEST 1326L
/** @} */
/**
@name SysAce Status Codes 1351 - 1360
@{
*/
/********************** SysAce statuses 1351 - 1360 **************************/
#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
/** @} */
/**
@name PCI Bridge Status Codes 1361 - 1375
@{
*/
/********************** PCI Bridge statuses 1361 - 1375 **********************/
#define XST_PCI_INVALID_ADDRESS 1361L
/** @} */
/**
@name FlexRay Constants 1400 - 1409
@{
*/
/********************** FlexRay constants 1400 - 1409 *************************/
#define XST_FR_TX_ERROR 1400
#define XST_FR_TX_BUSY 1401
#define XST_FR_BUF_LOCKED 1402
#define XST_FR_NO_BUF 1403
/** @} */
/**
@name USB constants 1410 - 1420
@{
*/
/****************** USB constants 1410 - 1420 *******************************/
#define XST_USB_ALREADY_CONFIGURED 1410
#define XST_USB_BUF_ALIGN_ERROR 1411
#define XST_USB_NO_DESC_AVAILABLE 1412
#define XST_USB_BUF_TOO_BIG 1413
#define XST_USB_NO_BUF 1414
/** @} */
/**
@name HWICAP constants 1421 - 1429
@{
*/
/****************** HWICAP constants 1421 - 1429 *****************************/
#define XST_HWICAP_WRITE_DONE 1421
/** @} */
/**
@name AXI VDMA constants 1430 - 1440
@{
*/
/****************** AXI VDMA constants 1430 - 1440 *****************************/
#define XST_VDMA_MISMATCH_ERROR 1430
/** @} */
/**
@name NAND Flash Status Codes 1441 - 1459
@{
*/
/*********************** NAND Flash statuses 1441 - 1459 *********************/
#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
* programming
*/
#define XST_NAND_READY 1442L /*!< Flash is ready for commands
*/
#define XST_NAND_ERROR 1443L /*!< Flash had detected an
* internal error.
*/
#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
* driver
*/
#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
*/
#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
* operation aborted due to a
* timeout
*/
#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
* addressible range
*/
#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
*/
#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
* page of the device
*/
#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
*/
#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
*/
/** @} */
/**************************** Type Definitions *******************************/
typedef s32 XStatus;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_status_codes".
*/
datalink814_sp/bsp/microblaze_ps/include/xsysmon.h
+654
View File
@@ -0,0 +1,654 @@
/******************************************************************************
*
* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xsysmon.h
* @addtogroup sysmon_v7_5
* @{
* @details
*
* The XSysMon driver supports the Xilinx System Monitor/ADC device.
*
* The System Monitor/ADC device has the following features:
* - 10-bit, 200-KSPS (kilo samples per second)
* Analog-to-Digital Converter (ADC)
* - Monitoring of on-chip supply voltages and temperature
* - 1 dedicated differential analog-input pair and
* 16 auxiliary differential analog-input pairs
* - Automatic alarms based on user defined limits for the on-chip
* supply voltages and temperature
* - Automatic Channel Sequencer, programmable averaging, programmable
* acquisition time for the external inputs, unipolar or differential
* input selection for the external inputs
* - Inbuilt Calibration
* - Optional interrupt request generation
* - External Mux (7 Series and Zynq XADC)
*
*
* The user should refer to the hardware device specification for detailed
* information about the device.
*
* This header file contains the prototypes of driver functions that can
* be used to access the System Monitor/ADC device.
*
*
* <b> System Monitor Channel Sequencer Modes </b>
*
* The System Monitor Channel Sequencer supports the following operating modes:
*
* - <b> Default </b>: This is the default mode after power up.
* In this mode of operation the System Monitor operates in
* a sequence mode, monitoring the on chip sensors:
* Temperature, VCCINT, and VCCAUX.
* - <b> One pass through sequence </b>: In this mode the System Monitor
* converts the channels enabled in the Sequencer Channel Enable
* registers for a single pass and then stops.
* - <b> Continuous cycling of sequence </b>: In this mode the System Monitor
* converts the channels enabled in the Sequencer Channel Enable
* registers continuously.
* - <b> Single channel mode</b>: In this mode the System Monitor Channel
* Sequencer is disabled and the System Monitor operates in a
* Single Channel Mode.
* The System Monitor can operate either in a Continuous or Event
* driven sampling mode in the single channel mode.
* - <b> Simultaneous sampling mode</b>: This mode is available only in
* 7 Series and Zynq XADC devices. In this mode both ADCs sample and
* digitizes two different analog input signals at the same time.
* - <b> Independent ADC mode</b>: This mode is available only in 7 Series and
* Zynq XADC devices. In this mode ADC A is used to implement a
* fixed monitoring mode which is similar to default mode, but the
* fixed alarm functions are enabled. ADC B is available to be used
* with the external analog input channels only.
*
* <b> Initialization and Configuration </b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the System Monitor/ADC device.
*
* XSysMon_CfgInitialize() API is used to initialize the System Monitor/ADC
* device. The user needs to first call the XSysMon_LookupConfig() API which
* returns the Configuration structure pointer which is passed as a parameter to
* the XSysMon_CfgInitialize() API.
*
*
* <b>Interrupts</b>
*
* The System Monitor/ADC device supports interrupt driven mode and the default
* operation mode is polling mode.
*
* The interrupt mode is available only if hardware is configured to support
* interrupts.
*
* This driver does not provide a Interrupt Service Routine (ISR) for the device.
* It is the responsibility of the application to provide one if needed. Refer to
* the interrupt example provided with this driver for details on using the
* device in interrupt mode.
*
*
* <b> Virtual Memory </b>
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
*
* <b> Threads </b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
*
* <b> Asserts </b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
*
* <b> Building the driver </b>
*
* The XSysMon driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* <b> Limitations of the driver </b>
*
* System Monitor/ADC device can be accessed through the JTAG port and the AXI
* interface. The driver implementation does not support the simultaneous access
* of the device by both these interfaces. The user has to care of this situation
* in the user application code.
*
*
*
* <br><br>
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a xd/sv 05/22/07 First release
* 2.00a sv 07/07/08 Added bit definitions for new Alarm Interrupts in the
* Interrupt Registers. Changed the ADC data functions
* to return 16 bits of data. Added macros for conversion
* from Raw Data to Temperature/Voltage and vice-versa.
* 3.00a sdm 02/09/09 Added APIs and bit definitions for V6 SysMon.
* 4.00a ktn 10/22/09 Updated the driver to use the HAL Processor APIs/macros.
* The macros have been renamed to remove _m from the name
* in all the driver files.
* 5.00a sdm 06/15/11 Added support for XADC 7 Series.
* 5.01a bss 02/28/12 Added support for Zynq,
* renamed XSM_ATR_BRAM_UPPER to XSM_ATR_VBRAM_UPPER
* renamed XSM_ATR_BRAM_LOWER to XSM_ATR_VBRAM_LOWER
* 5.02a bss 11/23/12 Added APIs and Macros to support Temperature Updation
* over TEMP_OUT port(CR #679872)
* 5.03a bss 04/25/13 Modified XSysMon_SetSeqChEnables,
* XSysMon_SetSeqAvgEnables, XSysMon_SetSeqInputMode
* and XSysMon_SetSeqAcqTime APIs to check for Safe Mode
* instead of Single Channel mode(CR #703729) in xsysmon.c
* Modified examples: xsysmon_polled_example.c,
* xsysmon_low_level_example.c,
* xsysmon_intr_printf_example.c, xsysmon_intr_example.c
* xsysmon_extmux_example.c and
* xsysmon_polled_printf_example.c to set Sequencer Mode
* as Safe mode instead of Single channel mode before
* configuring Sequencer registers.
* 6.0 adk 19/12/13 Updated as per the New Tcl API's
* 7.0 bss 7/25/14 To support Ultrascale:
* Added XSM_CH_VUSR0 - XSMXSM_CH_VUSR3,XSM_MAX_VUSR0 -
* XSM_MIN_VUSR3,XSM_ATR_VUSR0_UPPER -
* XSM_ATR_VUSR3_LOWER macros.
* Added XSM_IP_OFFSET macro(since register
* offsets are different for Ultrascale comapared to
* earlier familes),Offsets,Masks for VUSER0 to
* VUSER3 channels, Configuration Register 3 and
* Sequence Registers 8 and 9 in xsysmon_hw.h.
* Modified XSysMon_GetAdcData,
* XSysMon_GetMinMaxMeasurement,
* XSysMon_SetSingleChParams, XSysMon_SetAlarmEnables,
* XSysMon_GetAlarmEnables,XSysMon_SetSeqChEnables,
* XSysMon_GetSeqChEnables,XSysMon_SetSeqAvgEnables,
* XSysMon_GetSeqAvgEnables,XSysMon_SetAlarmThreshold
* and XSysMon_GetAlarmThreshold in xsysmon.c.
* Modified driver tcl to generate XPAR_SYSMON_0_IP_TYPE
* parameter.
* 7.1 bss 05/06/15 Modified temperature transfer function for
* for Ultrascale CR#859369
* 7.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XSysMon_CfgInitialize API.
* 7.2 adk 29/02/16 Updated interrupt example to support Zynq and ZynqMP
* CR#938326.
* 7.2 asa 11/03/16 Made changes to use configuration register 3 only for
* Ultrascale. This fixes the CR#910905.
* 7.2 adk 14/03/16 Fix compilation issues when sysmon is configured
* with streaming interface CR#940976.
* 7.3 vns 15/04/16 Corrected Ultrascale conversion formulae CR#949949
* ms 01/23/17 Added xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Modified Comment lines in functions of sysmon
* examples to recognize it as documentation block
* for doxygen generation.
* 7.4 ms 04/18/17 Modified tcl file to add suffix U for all macros
* definitions of sysmon in xparameters.h
* </pre>
*
*****************************************************************************/
#ifndef XSYSMON_H /* Prevent circular inclusions */
#define XSYSMON_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xsysmon_hw.h"
/************************** Constant Definitions ****************************/
/**
* @name Indexes for the different channels.
* @{
*/
#define XSM_CH_TEMP 0x0 /**< On Chip Temperature */
#define XSM_CH_VCCINT 0x1 /**< VCCINT */
#define XSM_CH_VCCAUX 0x2 /**< VCCAUX */
#define XSM_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */
#define XSM_CH_VREFP 0x4 /**< VREFP */
#define XSM_CH_VREFN 0x5 /**< VREFN */
#define XSM_CH_VBRAM 0x6 /**< VBRAM - 7 Series and Zynq */
#define XSM_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */
#define XSM_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */
#define XSM_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */
#define XSM_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel, Zynq */
#define XSM_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel, Zynq */
#define XSM_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel, Zynq */
#define XSM_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */
#define XSM_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */
#define XSM_CH_VUSR0 32 /**< VUSER0 Supply - UltraScale */
#define XSM_CH_VUSR1 33 /**< VUSER1 Supply - UltraScale */
#define XSM_CH_VUSR2 34 /**< VUSER2 Supply - UltraScale */
#define XSM_CH_VUSR3 35 /**< VUSER3 Supply - UltraScale */
/*@}*/
/**
* @name Indexes for reading the Calibration Coefficient Data.
* @{
*/
#define XSM_CALIB_SUPPLY_OFFSET_COEFF 0 /**< Supply Offset Calib Coefficient */
#define XSM_CALIB_ADC_OFFSET_COEFF 1 /**< ADC Offset Calib Coefficient */
#define XSM_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
/*@}*/
/**
* @name Indexes for reading the Minimum/Maximum Measurement Data.
* @{
*/
#define XSM_MAX_TEMP 0 /**< Maximum Temperature Data */
#define XSM_MAX_VCCINT 1 /**< Maximum VCCINT Data */
#define XSM_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */
#define XSM_MAX_VCCBRAM 3 /**< Maximum VCCBRAM Data, 7 Series/Zynq */
#define XSM_MIN_TEMP 4 /**< Minimum Temperature Data */
#define XSM_MIN_VCCINT 5 /**< Minimum VCCINT Data */
#define XSM_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */
#define XSM_MIN_VCCBRAM 7 /**< Minimum VCCBRAM Data, 7 Series/Zynq */
#define XSM_MAX_VCCPINT 8 /**< Maximum VCCPINT Data, Zynq */
#define XSM_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Data, Zynq */
#define XSM_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Data, Zynq */
#define XSM_MIN_VCCPINT 0xC /**< Minimum VCCPINT Data, Zynq */
#define XSM_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Data, Zynq */
#define XSM_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Data, Zynq */
#define XSM_MAX_VUSR0 0x80 /**< Maximum VUSR0 Data, Ultrascale */
#define XSM_MAX_VUSR1 0x81 /**< Maximum VUSR1 Data, Ultrascale */
#define XSM_MAX_VUSR2 0x82 /**< Maximum VUSR2 Data, Ultrascale */
#define XSM_MAX_VUSR3 0x83 /**< Maximum VUSR3 Data, Ultrascale */
#define XSM_MIN_VUSR0 0x88 /**< Minimum VUSR0 Data, Ultrascale */
#define XSM_MIN_VUSR1 0x89 /**< Minimum VUSR1 Data, Ultrascale */
#define XSM_MIN_VUSR2 0x8A /**< Minimum VUSR2 Data, Ultrascale */
#define XSM_MIN_VUSR3 0x8B /**< Minimum VUSR3 Data, Ultrascale */
/*@}*/
/**
* @name Alarm Threshold(Limit) Register (ATR) indexes.
* @{
*/
#define XSM_ATR_TEMP_UPPER 0 /**< High user Temperature */
#define XSM_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit */
#define XSM_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit */
#define XSM_ATR_OT_UPPER 3 /**< Lower Over Temperature limit */
#define XSM_ATR_TEMP_LOWER 4 /**< Low user Temperature */
#define XSM_ATR_VCCINT_LOWER 5 /**< VCCINT low voltage limit */
#define XSM_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit */
#define XSM_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */
#define XSM_ATR_VBRAM_UPPER 8 /**< VBRAM high voltage limit */
#define XSM_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm, Zynq */
#define XSM_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm, Zynq */
#define XSM_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm, Zynq */
#define XSM_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm, 7 Series and Zynq*/
#define XSM_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm, Zynq */
#define XSM_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm, Zynq */
#define XSM_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm, Zynq */
#define XSM_ATR_VUSR0_UPPER 0x10 /**< VUSER0 Upper Alarm, Ultrascale */
#define XSM_ATR_VUSR1_UPPER 0x11 /**< VUSER1 Upper Alarm, Ultrascale */
#define XSM_ATR_VUSR2_UPPER 0x12 /**< VUSER2 Upper Alarm, Ultrascale */
#define XSM_ATR_VUSR3_UPPER 0x13 /**< VUSER3 Upper Alarm, Ultrascale */
#define XSM_ATR_VUSR0_LOWER 0x18 /**< VUSER0 Lower Alarm, Ultrascale */
#define XSM_ATR_VUSR1_LOWER 0x19 /**< VUSER1 Lower Alarm, Ultrascale */
#define XSM_ATR_VUSR2_LOWER 0x1A /**< VUSER2 Lower Alarm, Ultrascale */
#define XSM_ATR_VUSR3_LOWER 0x1B /**< VUSER3 Lower Alarm, Ultrascale */
/*@}*/
/**
* @name Averaging to be done for the channels.
* @{
*/
#define XSM_AVG_0_SAMPLES 0 /**< No Averaging */
#define XSM_AVG_16_SAMPLES 1 /**< Average 16 samples */
#define XSM_AVG_64_SAMPLES 2 /**< Average 64 samples */
#define XSM_AVG_256_SAMPLES 3 /**< Average 256 samples */
/*@}*/
/**
* @name Channel Sequencer Modes of operation.
* @{
*/
#define XSM_SEQ_MODE_SAFE 0 /**< Default Safe Mode */
#define XSM_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */
#define XSM_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Seqquencer */
#define XSM_SEQ_MODE_SINGCHAN 3 /**< Single channel - No Sequencing */
#define XSM_SEQ_MODE_SIMUL 4 /**< Simultaneous Cycling Sequencer,
* 7 Series and Zynq XADC only */
#define XSM_SEQ_MODE_INDEPENDENT 8 /**< Independent ADC Sequencer,
* 7 Series and Zynq XADC only */
/*@}*/
/* For backwards compatabilty */
#define XSM_CH_CALIBRATION XSM_CH_ADC_CALIB
#define XSM_ATR_BRAM_UPPER XSM_ATR_VBRAM_UPPER
#define XSM_ATR_BRAM_LOWER XSM_ATR_VBRAM_LOWER
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the System Monitor/ADC
* device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress; /**< Device base address */
int IncludeInterrupt; /**< Supports Interrupt driven mode */
u8 IpType; /**< 1 - System Management */
/**< 0 - XADC/System Monoitor */
} XSysMon_Config;
/**
* The driver's instance data. The user is required to allocate a variable
* of this type for every System Monitor/ADC device in the system. A pointer to
* a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XSysMon_Config Config; /**< XSysMon_Config of current device */
u32 IsReady; /**< Device is initialized and ready */
u32 Mask; /**< Store the previously written value
in CONVST register */
} XSysMon;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
*
* This macro checks if the SysMonitor/ADC device is in Event Sampling mode.
*
* @param InstancePtr is a pointer to the XSysMon instance.
*
* @return
* - TRUE if the device is in Event Sampling Mode.
* - FALSE if the device is in Continuous Sampling Mode.
*
* @note C-Style signature:
* int XSysMon_IsEventSamplingMode(XSysMon *InstancePtr);
*
*****************************************************************************/
#define XSysMon_IsEventSamplingModeSet(InstancePtr) \
(((XSysMon_ReadReg((InstancePtr)->Config.BaseAddress, \
XSM_CFR0_OFFSET) & XSM_CFR0_EC_MASK) ? \
TRUE : FALSE))
/****************************************************************************/
/**
*
* This macro checks if the Dynamic Reconfiguration Port (DRP) transaction from
* the JTAG is in progress.
*
* @param InstancePtr is a pointer to the XSysMon instance.
*
* @return
* - TRUE if the DRP transaction from JTAG is in Progress.
* - FALSE if there is no DRP transaction from the JTAG.
*
* @note C-Style signature:
* int XSysMon_IsDrpBusy(XSysMon *InstancePtr);
*
*****************************************************************************/
#define XSysMon_IsDrpBusy(InstancePtr) \
((XSysMon_ReadReg((InstancePtr)->Config.BaseAddress, \
XSM_SR_OFFSET) & XSM_SR_JTAG_BUSY_MASK) ? \
TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro checks if the Dynamic Reconfiguration Port (DRP) is locked by the
* JTAG.
*
* @param InstancePtr is a pointer to the XSysMon instance.
*
* @return
* - TRUE if the DRP is locked by the JTAG.
* - FALSE if the DRP is not locked by the JTAG.
*
* @note C-Style signature:
* int XSysMon_IsDrpLocked(XSysMon *InstancePtr);
*
*****************************************************************************/
#define XSysMon_IsDrpLocked(InstancePtr) \
(((XSysMon_ReadReg((InstancePtr)->Config.BaseAddress, \
XSM_SR_OFFSET) & XSM_SR_JTAG_LOCKED_MASK) ? \
TRUE : FALSE))
/****************************************************************************/
/**
*
* This macro converts System Monitor/ADC Raw Data to Temperature(centigrades).
*
* @param AdcData is the SysMon Raw ADC Data.
*
* @return The Temperature in centigrades.
*
* @note C-Style signature:
* float XSysMon_RawToTemperature(u32 AdcData);
*
*****************************************************************************/
#if XPAR_SYSMON_0_IP_TYPE == SYSTEM_MANAGEMENT
#define XSysMon_RawToTemperature(AdcData) \
((((float)(AdcData)/65536.0f)/0.00199451786f ) - 273.67f)
#else
#define XSysMon_RawToTemperature(AdcData) \
((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
#endif
/****************************************************************************/
/**
*
* This macro converts System Monitor/ADC Raw Data to Voltage(volts).
*
* @param AdcData is the System Monitor/ADC Raw Data.
*
* @return The Voltage in volts.
*
* @note C-Style signature:
* float XSysMon_RawToVoltage(u32 AdcData);
*
*****************************************************************************/
#define XSysMon_RawToVoltage(AdcData) \
((((float)(AdcData))* (3.0f))/65536.0f)
/****************************************************************************/
/**
*
* This macro converts Temperature in centigrades to System Monitor/ADC Raw Data.
*
* @param Temperature is the Temperature in centigrades to be
* converted to System Monitor/ADC Raw Data.
*
* @return The System Monitor/ADC Raw Data.
*
* @note C-Style signature:
* int XSysMon_TemperatureToRaw(float Temperature);
*
*****************************************************************************/
#if XPAR_SYSMON_0_IP_TYPE == SYSTEM_MANAGEMENT
#define XSysMon_TemperatureToRaw(Temperature) \
((int)(((Temperature) + 273.67f)*65536.0f*0.00199451786f))
#else
#define XSysMon_TemperatureToRaw(Temperature) \
((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
#endif
/****************************************************************************/
/**
*
* This macro converts Voltage in Volts to System Monitor/ADC Raw Data.
*
* @param Voltage is the Voltage in volts to be converted to
* System Monitor/ADC Raw Data.
*
* @return The System Monitor/ADC Raw Data.
*
* @note C-Style signature:
* int XSysMon_VoltageToRaw(float Voltage);
*
*****************************************************************************/
#define XSysMon_VoltageToRaw(Voltage) \
((int)((Voltage)*65536.0f/3.0f))
/************************** Function Prototypes *****************************/
/**
* Functions in xsysmon_sinit.c
*/
XSysMon_Config *XSysMon_LookupConfig(u16 DeviceId);
/**
* Functions in xsysmon.c
*/
int XSysMon_CfgInitialize(XSysMon *InstancePtr,
XSysMon_Config *ConfigPtr, UINTPTR EffectiveAddr);
void XSysMon_Reset(XSysMon *InstancePtr);
u32 XSysMon_GetStatus(XSysMon *InstancePtr);
u32 XSysMon_GetAlarmOutputStatus(XSysMon *InstancePtr);
void XSysMon_StartAdcConversion(XSysMon *InstancePtr);
void XSysMon_ResetAdc(XSysMon *InstancePtr);
u16 XSysMon_GetAdcData(XSysMon *InstancePtr, u8 Channel);
u16 XSysMon_GetCalibCoefficient(XSysMon *InstancePtr, u8 CoeffType);
u16 XSysMon_GetMinMaxMeasurement(XSysMon *InstancePtr, u8 MeasurementType);
void XSysMon_SetAvg(XSysMon *InstancePtr, u8 Average);
u8 XSysMon_GetAvg(XSysMon *InstancePtr);
int XSysMon_SetSingleChParams(XSysMon *InstancePtr, u8 Channel,
int IncreaseAcqCycles, int IsEventMode,
int IsDifferentialMode);
void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u32 AlmEnableMask);
u32 XSysMon_GetAlarmEnables(XSysMon *InstancePtr);
void XSysMon_SetCalibEnables(XSysMon *InstancePtr, u16 Calibration);
u16 XSysMon_GetCalibEnables(XSysMon *InstancePtr);
void XSysMon_SetSequencerMode(XSysMon *InstancePtr, u8 SequencerMode);
u8 XSysMon_GetSequencerMode(XSysMon *InstancePtr);
void XSysMon_SetSequencerEvent(XSysMon *InstancePtr, int IsEventMode);
void XSysMon_SetExtenalMux(XSysMon *InstancePtr, u8 Channel);
void XSysMon_SetAdcClkDivisor(XSysMon *InstancePtr, u8 Divisor);
u8 XSysMon_GetAdcClkDivisor(XSysMon *InstancePtr);
int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u64 ChEnableMask);
u64 XSysMon_GetSeqChEnables(XSysMon *InstancePtr);
int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u64 AvgEnableChMask);
u64 XSysMon_GetSeqAvgEnables(XSysMon *InstancePtr);
int XSysMon_SetSeqInputMode(XSysMon *InstancePtr, u32 InputModeChMask);
u32 XSysMon_GetSeqInputMode(XSysMon *InstancePtr);
int XSysMon_SetSeqAcqTime(XSysMon *InstancePtr, u32 AcqCyclesChMask);
u32 XSysMon_GetSeqAcqTime(XSysMon *InstancePtr);
void XSysMon_SetAlarmThreshold(XSysMon *InstancePtr, u8 AlarmThrReg, u16 Value);
u16 XSysMon_GetAlarmThreshold(XSysMon *InstancePtr, u8 AlarmThrReg);
void XSysMon_SetOverTemp(XSysMon *InstancePtr, u16 Value);
u16 XSysMon_GetOverTemp(XSysMon *InstancePtr);
void XSysMon_EnableUserOverTemp(XSysMon *InstancePtr);
void XSysMon_DisableUserOverTemp(XSysMon *InstancePtr);
void XSysMon_EnableTempUpdate(XSysMon *InstancePtr);
void XSysMon_DisableTempUpdate(XSysMon *InstancePtr);
void XSysMon_SetTempWaitCycles(XSysMon *InstancePtr, u16 WaitCycles);
/**
* Functions in xsysmon_selftest.c
*/
int XSysMon_SelfTest(XSysMon *InstancePtr);
/**
* Functions in xsysmon_intr.c
*/
void XSysMon_IntrGlobalEnable(XSysMon *InstancePtr);
void XSysMon_IntrGlobalDisable(XSysMon *InstancePtr);
void XSysMon_IntrEnable(XSysMon *InstancePtr, u32 Mask);
void XSysMon_IntrDisable(XSysMon *InstancePtr, u32 Mask);
u32 XSysMon_IntrGetEnabled(XSysMon *InstancePtr);
u32 XSysMon_IntrGetStatus(XSysMon *InstancePtr);
void XSysMon_IntrClear(XSysMon *InstancePtr, u32 Mask);
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xsysmon_hw.h
+686
View File
@@ -0,0 +1,686 @@
/******************************************************************************
*
* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xsysmon_hw.h
* @addtogroup sysmon_v7_5
* @{
*
* This header file contains identifiers and basic driver functions (or
* macros) that can be used to access the System Monitor/ADC device or XADC.
*
* Refer to the device specification for more information about this driver.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a xd/sv 05/22/07 First release
* 2.00a sv 07/07/08 Added bit definitions for new Alarm Interrupts in the
* Interrupt Registers.
* 3.00a sdm 02/09/09 Added register and bit definitions for V6 SysMon.
* 4.00a ktn 10/22/09 The macros have been renamed to remove _m from the name
* of the macro.
* 5.00a sdm 06/15/11 Added new definitions for XADC.
* 5.01a bss 02/15/12 Updated for Zynq.
* 5.02a bss 11/23/12 Added macros XSM_CONVST_TEMPUPDT_MASK,
* XSM_CONVST_WAITCYCLES_MASK and
* XSM_CONVST_WAITCYCLES_SHIFT (CR #679872)
* 7.0 bss 7/25/14 To support Ultrascale:
* Added XSM_IP_OFFSET macro.
* Added Offsets and Masks for VUSER0 to VUSER3 channels.
* Added Configuration Register 3 and Sequence Registers
* 8 and 9.
* 7.2 asa 03/11/16 Made changes so that XSM_CFR3_OFFSET is
* visible only for Ultrasacle. Fix for CR#910905.
*
* </pre>
*
*****************************************************************************/
#ifndef XSYSMON_HW_H /* Prevent circular inclusions */
#define XSYSMON_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "xparameters.h"
/************************** Constant Definitions ****************************/
#define SYSTEM_MANAGEMENT 1 /* Ultrascale */
#define XADC 0 /* 7 Series, Zynq */
#if XPAR_SYSMON_0_IP_TYPE == SYSTEM_MANAGEMENT
#define XSM_IP_OFFSET 0x200
#else
#define XSM_IP_OFFSET 0x00
#endif
/**@name Register offsets
*
* The following constants provide access to each of the registers of the
* System Monitor/ADC device.
* @{
*/
/*
* System Monitor/ADC Local Registers
*/
#define XSM_SRR_OFFSET 0x00 /**< Software Reset Register */
#define XSM_SR_OFFSET 0x04 /**< Status Register */
#define XSM_AOR_OFFSET 0x08 /**< Alarm Output Register */
#define XSM_CONVST_OFFSET 0x0C /**< ADC Convert Start Register */
#define XSM_ARR_OFFSET 0x10 /**< ADC Reset Register */
/*
* System Monitor/ADC Interrupt Registers
*/
#define XSM_GIER_OFFSET 0x5C /**< Global Interrupt Enable */
#define XSM_IPISR_OFFSET 0x60 /**< Interrupt Status Register */
#define XSM_IPIER_OFFSET 0x68 /**< Interrupt Enable register */
/*
* System Monitor/ADC Internal Channel Registers
*/
#define XSM_TEMP_OFFSET (XSM_IP_OFFSET + 0x200)
/**< On-chip Temperature Reg */
#define XSM_VCCINT_OFFSET (XSM_IP_OFFSET + 0x204)
/**< On-chip VCCINT Data Reg */
#define XSM_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x208)
/**< On-chip VCCAUX Data Reg */
#define XSM_VPVN_OFFSET (XSM_IP_OFFSET + 0x20C)
/**< ADC out of VP/VN */
#define XSM_VREFP_OFFSET (XSM_IP_OFFSET + 0x210)
/**< On-chip VREFP Data Reg */
#define XSM_VREFN_OFFSET (XSM_IP_OFFSET + 0x214)
/**< On-chip VREFN Data Reg */
#define XSM_VBRAM_OFFSET (XSM_IP_OFFSET + 0x218)
/**< On-chip VBRAM Data,7-series/Zynq */
#define XSM_SUPPLY_CALIB_OFFSET (XSM_IP_OFFSET + 0x220)
/**< Supply Offset Data Reg */
#define XSM_ADC_CALIB_OFFSET (XSM_IP_OFFSET + 0x224)
/**< ADC Offset Data Reg */
#define XSM_GAINERR_CALIB_OFFSET (XSM_IP_OFFSET + 0x228)
/**< Gain Error Data Reg */
#define XSM_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x22C)
/**< PS VCCPINT Data Reg - Zynq */
#define XSM_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x230)
/**< PS VCCPAUX Data Reg - Zynq */
#define XSM_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x234)
/**< PS VCCPDRO Data Reg - Zynq */
#define XSM_VUSR0_OFFSET (XSM_IP_OFFSET + 0x400)
/**< VUSER0 Supply - Ultrascale */
#define XSM_VUSR1_OFFSET (XSM_IP_OFFSET + 0x404)
/**< VUSER0 Supply - Ultrascale */
#define XSM_VUSR2_OFFSET (XSM_IP_OFFSET + 0x408)
/**< VUSER0 Supply - Ultrascale */
#define XSM_VUSR3_OFFSET (XSM_IP_OFFSET + 0x40C)
/**< VUSER0 Supply - Ultrascale */
/*
* System Monitor/ADC External Channel Registers
*/
#define XSM_AUX00_OFFSET (XSM_IP_OFFSET + 0x240)
/**< ADC out of VAUXP0/VAUXN0 */
#define XSM_AUX01_OFFSET (XSM_IP_OFFSET + 0x244)
/**< ADC out of VAUXP1/VAUXN1 */
#define XSM_AUX02_OFFSET (XSM_IP_OFFSET + 0x248)
/**< ADC out of VAUXP2/VAUXN2 */
#define XSM_AUX03_OFFSET (XSM_IP_OFFSET + 0x24C)
/**< ADC out of VAUXP3/VAUXN3 */
#define XSM_AUX04_OFFSET (XSM_IP_OFFSET + 0x250)
/**< ADC out of VAUXP4/VAUXN4 */
#define XSM_AUX05_OFFSET (XSM_IP_OFFSET + 0x254)
/**< ADC out of VAUXP5/VAUXN5 */
#define XSM_AUX06_OFFSET (XSM_IP_OFFSET + 0x258)
/**< ADC out of VAUXP6/VAUXN6 */
#define XSM_AUX07_OFFSET (XSM_IP_OFFSET + 0x25C)
/**< ADC out of VAUXP7/VAUXN7 */
#define XSM_AUX08_OFFSET (XSM_IP_OFFSET + 0x260)
/**< ADC out of VAUXP8/VAUXN8 */
#define XSM_AUX09_OFFSET (XSM_IP_OFFSET + 0x264)
/**< ADC out of VAUXP9/VAUXN9 */
#define XSM_AUX10_OFFSET (XSM_IP_OFFSET + 0x268)
/**< ADC out of VAUXP10/VAUXN10 */
#define XSM_AUX11_OFFSET (XSM_IP_OFFSET + 0x26C)
/**< ADC out of VAUXP11/VAUXN11 */
#define XSM_AUX12_OFFSET (XSM_IP_OFFSET + 0x270)
/**< ADC out of VAUXP12/VAUXN12 */
#define XSM_AUX13_OFFSET (XSM_IP_OFFSET + 0x274)
/**< ADC out of VAUXP13/VAUXN13 */
#define XSM_AUX14_OFFSET (XSM_IP_OFFSET + 0x278)
/**< ADC out of VAUXP14/VAUXN14 */
#define XSM_AUX15_OFFSET (XSM_IP_OFFSET + 0x27C)
/**< ADC out of VAUXP15/VAUXN15 */
/*
* System Monitor/ADC Registers for Maximum/Minimum data captured for the
* on chip Temperature/VCCINT/VCCAUX data.
*/
#define XSM_MAX_TEMP_OFFSET (XSM_IP_OFFSET + 0x280)
/**< Maximum Temperature Reg */
#define XSM_MAX_VCCINT_OFFSET (XSM_IP_OFFSET + 0x284)
/**< Maximum VCCINT Register */
#define XSM_MAX_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x288)
/**< Maximum VCCAUX Register */
#define XSM_MAX_VBRAM_OFFSET (XSM_IP_OFFSET + 0x28C)
/**< Maximum VBRAM Reg, 7 Series/Zynq */
#define XSM_MIN_TEMP_OFFSET (XSM_IP_OFFSET + 0x290)
/**< Minimum Temperature Reg */
#define XSM_MIN_VCCINT_OFFSET (XSM_IP_OFFSET + 0x294)
/**< Minimum VCCINT Register */
#define XSM_MIN_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x298)
/**< Minimum VCCAUX Register */
#define XSM_MIN_VBRAM_OFFSET (XSM_IP_OFFSET + 0x29C)
/**< Maximum VBRAM Reg, 7 Series/Zynq */
#define XSM_MAX_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2A0)
/**< Max VCCPINT Register, Zynq */
#define XSM_MAX_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2A4)
/**< Max VCCPAUX Register, Zynq */
#define XSM_MAX_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2A8)
/**< Max VCCPDRO Register, Zynq */
#define XSM_MIN_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2AC)
/**< Min VCCPINT Register, Zynq */
#define XSM_MIN_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2B0)
/**< Min VCCPAUX Register, Zynq */
#define XSM_MIN_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2B4)
/**< Min VCCPDRO Register, Zynq */
#define XSM_MAX_VUSR0_OFFSET (XSM_IP_OFFSET + 0x480)
/**< Maximum VUSER0 Supply Reg */
#define XSM_MAX_VUSR1_OFFSET (XSM_IP_OFFSET + 0x484)
/**< Maximum VUSER1 Supply Reg */
#define XSM_MAX_VUSR2_OFFSET (XSM_IP_OFFSET + 0x488)
/**< Maximum VUSER2 Supply Reg */
#define XSM_MAX_VUSR3_OFFSET (XSM_IP_OFFSET + 0x48C)
/**< Maximum VUSER3 Supply Reg */
#define XSM_MIN_VUSR0_OFFSET (XSM_IP_OFFSET + 0x4A0)
/**< Minimum VUSER0 Supply Reg */
#define XSM_MIN_VUSR1_OFFSET (XSM_IP_OFFSET + 0x4A4)
/**< Minimum VUSER1 Supply Reg */
#define XSM_MIN_VUSR2_OFFSET (XSM_IP_OFFSET + 0x4A8)
/**< Minimum VUSER2 Supply Reg */
#define XSM_MIN_VUSR3_OFFSET (XSM_IP_OFFSET + 0x4AC)
/**< Minimum VUSER3 Supply Reg */
#define XSM_FLAG_REG_OFFSET (XSM_IP_OFFSET + 0x2FC) /**< General Status */
/*
* System Monitor/ADC Configuration Registers
*/
#define XSM_CFR0_OFFSET (XSM_IP_OFFSET + 0x300)
/**< Configuration Register 0 */
#define XSM_CFR1_OFFSET (XSM_IP_OFFSET + 0x304)
/**< Configuration Register 1 */
#define XSM_CFR2_OFFSET (XSM_IP_OFFSET + 0x308)
/**< Configuration Register 2 */
#if XPAR_SYSMON_0_IP_TYPE == SYSTEM_MANAGEMENT
#define XSM_CFR3_OFFSET (XSM_IP_OFFSET + 0x30C)
/**< Configuration Register 3 */
#endif
/*
* System Monitor/ADC Sequence Registers
*/
#define XSM_SEQ00_OFFSET (XSM_IP_OFFSET + 0x320)
/**< Seq Reg 00 Adc Channel Selection */
#define XSM_SEQ01_OFFSET (XSM_IP_OFFSET + 0x324)
/**< Seq Reg 01 Adc Channel Selection */
#define XSM_SEQ02_OFFSET (XSM_IP_OFFSET + 0x328)
/**< Seq Reg 02 Adc Average Enable */
#define XSM_SEQ03_OFFSET (XSM_IP_OFFSET + 0x32C)
/**< Seq Reg 03 Adc Average Enable */
#define XSM_SEQ04_OFFSET (XSM_IP_OFFSET + 0x330)
/**< Seq Reg 04 Adc Input Mode Select */
#define XSM_SEQ05_OFFSET (XSM_IP_OFFSET + 0x334)
/**< Seq Reg 05 Adc Input Mode Select */
#define XSM_SEQ06_OFFSET (XSM_IP_OFFSET + 0x338)
/**< Seq Reg 06 Adc Acquisition Select */
#define XSM_SEQ07_OFFSET (XSM_IP_OFFSET + 0x33C)
/**< Seq Reg 07 Adc Acquisition Select */
#define XSM_SEQ08_OFFSET (XSM_IP_OFFSET + 0x318)
/**< Seq Reg 08 Adc Channel Selection */
#define XSM_SEQ09_OFFSET (XSM_IP_OFFSET + 0x31C)
/**< Seq Reg 09 Adc Average Enable */
/*
* System Monitor/ADC Alarm Threshold/Limit Registers (ATR)
*/
#define XSM_ATR_TEMP_UPPER_OFFSET (XSM_IP_OFFSET + 0x340)
/**< Temp Upper Alarm Register */
#define XSM_ATR_VCCINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x344)
/**< VCCINT Upper Alarm Reg */
#define XSM_ATR_VCCAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x348)
/**< VCCAUX Upper Alarm Reg */
#define XSM_ATR_OT_UPPER_OFFSET (XSM_IP_OFFSET + 0x34C)
/**< Over Temp Upper Alarm Reg */
#define XSM_ATR_TEMP_LOWER_OFFSET (XSM_IP_OFFSET + 0x350)
/**< Temp Lower Alarm Register */
#define XSM_ATR_VCCINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x354)
/**< VCCINT Lower Alarm Reg */
#define XSM_ATR_VCCAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x358)
/**< VCCAUX Lower Alarm Reg */
#define XSM_ATR_OT_LOWER_OFFSET (XSM_IP_OFFSET + 0x35C)
/**< Over Temp Lower Alarm Reg */
#define XSM_ATR_VBRAM_UPPER_OFFSET (XSM_IP_OFFSET + 0x360)
/**< VBBAM Upper Alarm,7 Series */
#define XSM_ATR_VCCPINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x364)
/**< VCCPINT Upper Alarm, Zynq */
#define XSM_ATR_VCCPAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x368)
/**< VCCPAUX Upper Alarm, Zynq */
#define XSM_ATR_VCCPDRO_UPPER_OFFSET (XSM_IP_OFFSET + 0x36C)
/**< VCCPDRO Upper Alarm, Zynq */
#define XSM_ATR_VBRAM_LOWER_OFFSET (XSM_IP_OFFSET + 0x370)
/**< VRBAM Lower Alarm, 7 Series*/
#define XSM_ATR_VCCPINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x374)
/**< VCCPINT Lower Alarm, Zynq */
#define XSM_ATR_VCCPAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x378)
/**< VCCPAUX Lower Alarm, Zynq */
#define XSM_ATR_VCCPDRO_LOWER_OFFSET (XSM_IP_OFFSET + 0x37C)
/**< VCCPDRO Lower Alarm, Zynq */
#define XSM_ATR_VUSR0_UPPER_OFFSET (XSM_IP_OFFSET + 0x380)
/**< VUSER0 Upper Alarm Reg */
#define XSM_ATR_VUSR1_UPPER_OFFSET (XSM_IP_OFFSET + 0x384)
/**< VUSER1 Upper Alarm Reg */
#define XSM_ATR_VUSR2_UPPER_OFFSET (XSM_IP_OFFSET + 0x388)
/**< VUSER2 Upper Alarm Reg */
#define XSM_ATR_VUSR3_UPPER_OFFSET (XSM_IP_OFFSET + 0x38C)
/**< VUSER3 Upper Alarm Reg */
#define XSM_ATR_VUSR0_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A0)
/**< VUSER0 Lower Alarm Reg */
#define XSM_ATR_VUSR1_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A4)
/**< VUSER1 Lower Alarm Reg */
#define XSM_ATR_VUSR2_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A8)
/**< VUSER2 Lower Alarm Reg */
#define XSM_ATR_VUSR3_LOWER_OFFSET (XSM_IP_OFFSET + 0x3AC)
/**< VUSER3 Lower Alarm Reg */
/*@}*/
/**
* @name System Monitor/ADC Software Reset Register (SRR) mask(s)
* @{
*/
#define XSM_SRR_IPRST_MASK 0x0000000A /**< Device Reset Mask */
/*@}*/
/**
* @name System Monitor/ADC Status Register (SR) mask(s)
* @{
*/
#define XSM_SR_JTAG_BUSY_MASK 0x00000400 /**< JTAG is busy */
#define XSM_SR_JTAG_MODIFIED_MASK 0x00000200 /**< JTAG Write has occurred */
#define XSM_SR_JTAG_LOCKED_MASK 0x00000100 /**< JTAG is locked */
#define XSM_SR_BUSY_MASK 0x00000080 /**< ADC is busy in conversion */
#define XSM_SR_EOS_MASK 0x00000040 /**< End of Sequence */
#define XSM_SR_EOC_MASK 0x00000020 /**< End of Conversion */
#define XSM_SR_CH_MASK 0x0000001F /**< Input ADC channel */
/*@}*/
/**
* @name System Monitor/ADC Alarm Output Register (AOR) mask(s)
* @{
*/
#define XSM_AOR_ALARM_ALL_MASK 0x00001FFF /**< Mask for all Alarms */
#define XSM_AOR_VUSR3_MASK 0x00001000 /**< ALM11 - VUSER3 Alarm Mask */
#define XSM_AOR_VUSR2_MASK 0x00000800 /**< ALM10 - VUSER2 Alarm Mask */
#define XSM_AOR_VUSR1_MASK 0x00000400 /**< ALM9 - VUSER1 Alarm Mask */
#define XSM_AOR_VUSR0_MASK 0x00000200 /**< ALM8 - VUSER0 Alarm Mask */
#define XSM_AOR_ALL_MASK 0x00000100 /**< ALM7 - All Alarms 0 to 6 */
#define XSM_AOR_VCCPDRO_MASK 0x00000080 /**< ALM6 - VCCPDRO Mask, Zynq */
#define XSM_AOR_VCCPAUX_MASK 0x00000040 /**< ALM5 - VCCPAUX Mask, Zynq */
#define XSM_AOR_VCCPINT_MASK 0x00000020 /**< ALM4 - VCCPINT Mask, Zynq */
#define XSM_AOR_VBRAM_MASK 0x00000010 /**< ALM3 - VBRAM Output Mask
* - 7 Series and Zynq */
#define XSM_AOR_VCCAUX_MASK 0x00000008 /**< ALM2 - VCCAUX Output Mask */
#define XSM_AOR_VCCINT_MASK 0x00000004 /**< ALM1 - VCCINT Alarm Mask */
#define XSM_AOR_TEMP_MASK 0x00000002 /**< ALM0 - Temp sensor Alarm Mask */
#define XSM_AOR_OT_MASK 0x00000001 /**< Over Temp Alarm Output */
/*@}*/
/**
* @name System Monitor/ADC CONVST Register (CONVST) mask(s)
* @{
*/
#define XSM_CONVST_CONVST_MASK 0x00000001
/**< Conversion Start Mask */
#define XSM_CONVST_TEMPUPDT_MASK 0x00000002
/**< Temperature Update
Enable Mask */
#define XSM_CONVST_WAITCYCLES_SHIFT 2 /**< Wait Cycles Shift */
#define XSM_CONVST_WAITCYCLES_MASK 0x0003FFFC /**< Wait Cycles Mask */
#define XSM_CONVST_WAITCYCLES_DEFAULT 0x03E8 /**< Wait Cycles
default value */
/*@}*/
/**
* @name System Monitor/ADC Reset Register (ARR) mask(s)
* @{
*/
#define XSM_ARR_RST_MASK 0x00000001 /**< ADC Reset bit mask */
/*@}*/
/**
* @name Global Interrupt Enable Register (GIER) mask(s)
* @{
*/
#define XSM_GIER_GIE_MASK 0x80000000 /**< Global interrupt enable */
/*@}*/
/**
* @name System Monitor/ADC device Interrupt Status/Enable Registers
*
* <b> Interrupt Status Register (IPISR) </b>
*
* This register holds the interrupt status flags for the device.
*
* <b> Interrupt Enable Register (IPIER) </b>
*
* This register is used to enable interrupt sources for the device.
* Writing a '1' to a bit in this register enables the corresponding Interrupt.
* Writing a '0' to a bit in this register disables the corresponding Interrupt
*
* IPISR/IPIER registers have the same bit definitions and are only defined
* once.
* @{
*/
#define XSM_IPIXR_VBRAM_MASK 0x00000400 /**< ALM3 - VBRAM Output Mask
* - 7 Series and Zynq */
#define XSM_IPIXR_TEMP_DEACTIVE_MASK 0x00000200 /**< Alarm 0 DEACTIVE */
#define XSM_IPIXR_OT_DEACTIVE_MASK 0x00000100 /**< Over Temp DEACTIVE */
#define XSM_IPIXR_JTAG_MODIFIED_MASK 0x00000080 /**< JTAG Modified */
#define XSM_IPIXR_JTAG_LOCKED_MASK 0x00000040 /**< JTAG Locked */
#define XSM_IPIXR_EOC_MASK 0x00000020 /**< End Of Conversion */
#define XSM_IPIXR_EOS_MASK 0x00000010 /**< End Of Sequence */
#define XSM_IPIXR_VCCAUX_MASK 0x00000008 /**< Alarm 2 - VCCAUX */
#define XSM_IPIXR_VCCINT_MASK 0x00000004 /**< Alarm 1 - VCCINT */
#define XSM_IPIXR_TEMP_MASK 0x00000002 /**< Alarm 0 - Temp ACTIVE */
#define XSM_IPIXR_OT_MASK 0x00000001 /**< Over Temperature ACTIVE */
#define XSM_IPIXR_VUSR0_MASK 0x00004000 /**< Alarm 8 VUSER0 */
#define XSM_IPIXR_VUSR1_MASK 0x00008000 /**< Alarm 9 VUSER1 */
#define XSM_IPIXR_VUSR2_MASK 0x00010000 /**< Alarm 10 VUSER2 */
#define XSM_IPIXR_VUSR3_MASK 0x00020000 /**< Alarm 11 VUSER3 */
#define XSM_IPIXR_ALL_MASK 0x0003C7FF /**< Mask of all interrupts */
/*@}*/
/**
* @name Mask for all ADC converted data including Minimum/Maximum Measurements
* and Threshold data.
* @{
*/
#define XSM_ADCDATA_MAX_MASK 0x03FF
/*@}*/
/**
* @name Configuration Register 0 (CFR0) mask(s)
* @{
*/
#define XSM_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */
#define XSM_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */
#define XSM_CFR0_AVG1_MASK 0x0000 /**< No Averaging */
#define XSM_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */
#define XSM_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */
#define XSM_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */
#define XSM_CFR0_AVG_SHIFT 12 /**< Shift for the Averaging bits */
#define XSM_CFR0_MUX_MASK 0x0800 /**< External Mux Mask Enable
* - 7 Series and Zynq */
#define XSM_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */
#define XSM_CFR0_EC_MASK 0x0200 /**< Event driven/Continuous mode */
#define XSM_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */
#define XSM_CFR0_CHANNEL_MASK 0x003F /**< Channel number bit Mask */
/*@}*/
/**
* @name Configuration Register 1 (CFR1) mask(s)
* @{
*/
#define XSM_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */
#define XSM_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */
#define XSM_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */
#define XSM_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */
#define XSM_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */
#define XSM_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling
* Mask */
#define XSM_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */
#define XSM_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */
#define XSM_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alarm 6 - VCCPDRO, Zynq */
#define XSM_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alarm 5 - VCCPAUX, Zynq */
#define XSM_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alarm 4 - VCCPINT, Zynq */
#define XSM_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alarm 3 - VBRAM Enable
* 7 Series and Zynq */
#define XSM_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */
#define XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power
Supply Gain/Offset
Enable */
#define XSM_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power
Supply Offset Enable */
#define XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
Offset Enable */
#define XSM_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset
Enable */
#define XSM_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */
#define XSM_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */
#define XSM_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
#define XSM_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
#define XSM_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
#define XSM_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */
/*@}*/
/**
* @name Configuration Register 2 (CFR2) mask(s)
* @{
*/
#define XSM_CFR2_CD_VALID_MASK 0xFF00 /**<Clock Divisor bit Mask */
#define XSM_CFR2_CD_SHIFT 8 /**<Num of shift on division */
#define XSM_CFR2_CD_MIN 8 /**<Minimum value of divisor */
#define XSM_CFR2_CD_MAX 255 /**<Maximum value of divisor */
#define XSM_CFR2_PD_MASK 0x0030 /**<Power Down Mask */
#define XSM_CFR2_PD_XADC_MASK 0x0030 /**<Power Down XADC Mask */
#define XSM_CFR2_PD_ADC1_MASK 0x0020 /**<Power Down XADC Mask */
#define XSM_CFR2_PD_SHIFT 4 /**<Power Down Shift */
/*@}*/
/**
* @name Configuration Register 3 (CFR3) mask(s)
* @{
*/
#define XSM_CFR3_ALM_ALL_MASK 0x000F /**< Mask for all alarms */
#define XSM_CFR3_ALM_VUSR3_MASK 0x0008 /**< VUSER 0 Supply */
#define XSM_CFR3_ALM_VUSR2_MASK 0x0004 /**< VUSER 1 Supply */
#define XSM_CFR3_ALM_VUSR1_MASK 0x0002 /**< VUSER 2 Supply */
#define XSM_CFR3_ALM_VUSR0_MASK 0x0001 /**< VUSER 3 Supply */
/* Mask for all Alarms in CFR1 and CFR3 */
#define XSM_CFR_ALM_ALL_MASK 0xF0F0F
/*@}*/
/**
* @name Alarm masks for channels in Configuration registers 1 and 3
* @{
*/
#define XSM_CFR_ALM_VUSR3_MASK 0x00080000 /**< VUSER 0 Supply */
#define XSM_CFR_ALM_VUSR2_MASK 0x00040000 /**< VUSER 1 Supply */
#define XSM_CFR_ALM_VUSR1_MASK 0x00020000 /**< VUSER 2 Supply */
#define XSM_CFR_ALM_VUSR0_MASK 0x00010000 /**< VUSER 3 Supply */
#define XSM_CFR_ALM_VCCPDRO_MASK 0x0800 /**< Alarm 6 - VCCPDRO, Zynq */
#define XSM_CFR_ALM_VCCPAUX_MASK 0x0400 /**< Alarm 5 - VCCPAUX, Zynq */
#define XSM_CFR_ALM_VCCPINT_MASK 0x0200 /**< Alarm 4 - VCCPINT, Zynq */
#define XSM_CFR_ALM_VBRAM_MASK 0x0100 /**< Alarm 3 - VBRAM Enable
* 7 Series and Zynq */
#define XSM_CFR_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
#define XSM_CFR_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
#define XSM_CFR_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
#define XSM_CFR_OT_MASK 0x0001 /**< Over Temperature Enable */
/**
* @name Sequence Register (SEQ) Bit Definitions
* @{
*/
#define XSM_SEQ_CH_CALIB 0x00000001 /**< ADC Calibration Channel */
#define XSM_SEQ_CH_VCCPINT 0x00000020 /**< VCCPINT, Zynq Only */
#define XSM_SEQ_CH_VCCPAUX 0x00000040 /**< VCCPAUX, Zynq Only */
#define XSM_SEQ_CH_VCCPDRO 0x00000080 /**< VCCPDRO, Zynq Only */
#define XSM_SEQ_CH_TEMP 0x00000100 /**< On Chip Temperature Channel */
#define XSM_SEQ_CH_VCCINT 0x00000200 /**< VCCINT Channel */
#define XSM_SEQ_CH_VCCAUX 0x00000400 /**< VCCAUX Channel */
#define XSM_SEQ_CH_VPVN 0x00000800 /**< VP/VN analog inputs Channel */
#define XSM_SEQ_CH_VREFP 0x00001000 /**< VREFP Channel */
#define XSM_SEQ_CH_VREFN 0x00002000 /**< VREFN Channel */
#define XSM_SEQ_CH_VBRAM 0x00004000 /**< VBRAM Channel, 7 series/Zynq */
#define XSM_SEQ_CH_AUX00 0x00010000 /**< 1st Aux Channel */
#define XSM_SEQ_CH_AUX01 0x00020000 /**< 2nd Aux Channel */
#define XSM_SEQ_CH_AUX02 0x00040000 /**< 3rd Aux Channel */
#define XSM_SEQ_CH_AUX03 0x00080000 /**< 4th Aux Channel */
#define XSM_SEQ_CH_AUX04 0x00100000 /**< 5th Aux Channel */
#define XSM_SEQ_CH_AUX05 0x00200000 /**< 6th Aux Channel */
#define XSM_SEQ_CH_AUX06 0x00400000 /**< 7th Aux Channel */
#define XSM_SEQ_CH_AUX07 0x00800000 /**< 8th Aux Channel */
#define XSM_SEQ_CH_AUX08 0x01000000 /**< 9th Aux Channel */
#define XSM_SEQ_CH_AUX09 0x02000000 /**< 10th Aux Channel */
#define XSM_SEQ_CH_AUX10 0x04000000 /**< 11th Aux Channel */
#define XSM_SEQ_CH_AUX11 0x08000000 /**< 12th Aux Channel */
#define XSM_SEQ_CH_AUX12 0x10000000 /**< 13th Aux Channel */
#define XSM_SEQ_CH_AUX13 0x20000000 /**< 14th Aux Channel */
#define XSM_SEQ_CH_AUX14 0x40000000 /**< 15th Aux Channel */
#define XSM_SEQ_CH_AUX15 0x80000000 /**< 16th Aux Channel */
#define XSM_SEQ_CH_VUSR0 0x100000000 /**< VUSER0 Channel */
#define XSM_SEQ_CH_VUSR1 0x200000000 /**< VUSER1 Channel */
#define XSM_SEQ_CH_VUSR2 0x400000000 /**< VUSER2 Channel */
#define XSM_SEQ_CH_VUSR3 0x800000000 /**< VUSER3 Channel */
#define XSM_SEQ00_CH_VALID_MASK 0x7FE1 /**< Mask for the valid channels */
#define XSM_SEQ01_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
#define XSM_SEQ02_CH_VALID_MASK 0x7FE0 /**< Mask for the valid channels */
#define XSM_SEQ03_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
#define XSM_SEQ04_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */
#define XSM_SEQ05_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
#define XSM_SEQ06_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */
#define XSM_SEQ07_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
#define XSM_SEQ08_CH_VALID_MASK 0x000F /**< Mask for the valid channels */
#define XSM_SEQ09_CH_VALID_MASK 0x000F /**< Mask for the valid channels */
#define XSM_SEQ_CH_AUX_SHIFT 16 /**< Shift for the Aux Channel */
#define XSM_SEQ_CH_VUSR_SHIFT 32 /**< Shift for the Aux Channel */
/*@}*/
/**
* @name OT Upper Alarm Threshold Register Bit Definitions
* @{
*/
#define XSM_ATR_OT_UPPER_ENB_MASK 0x000F /**< Mask for OT enable */
#define XSM_ATR_OT_UPPER_VAL_MASK 0xFFF0 /**< Mask for OT value */
#define XSM_ATR_OT_UPPER_VAL_SHIFT 4 /**< Shift for OT value */
#define XSM_ATR_OT_UPPER_ENB_VAL 0x0003 /**< Value for OT enable */
#define XSM_ATR_OT_UPPER_VAL_MAX 0x0FFF /**< Max OT value */
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* Read a register of the System Monitor/ADC device. This macro provides register
* access to all registers using the register offsets defined above.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset is the offset of the register to read.
*
* @return The contents of the register.
*
* @note C-style Signature:
* u32 XSysMon_ReadReg(u32 BaseAddress, u32 RegOffset);
*
******************************************************************************/
#define XSysMon_ReadReg(BaseAddress, RegOffset) \
(Xil_In32((BaseAddress) + (RegOffset)))
/*****************************************************************************/
/**
*
* Write a register of the System Monitor/ADC device. This macro provides
* register access to all registers using the register offsets defined above.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset is the offset of the register to write.
* @param Data is the value to write to the register.
*
* @return None.
*
* @note C-style Signature:
* void XSysMon_WriteReg(u32 BaseAddress,
* u32 RegOffset,u32 Data)
*
******************************************************************************/
#define XSysMon_WriteReg(BaseAddress, RegOffset, Data) \
(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xtmrctr.h
+326
View File
@@ -0,0 +1,326 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xtmrctr.h
* @addtogroup tmrctr_v4_6
* @{
* @details
*
* The Xilinx timer/counter component. This component supports the Xilinx
* timer/counter. More detailed description of the driver operation can
* be found in the xtmrctr.c file.
*
* The Xilinx timer/counter supports the following features:
* - Polled mode.
* - Interrupt driven mode
* - enabling and disabling specific timers
* - PWM operation
* - Cascade Operation (This is to be used for getting a 64 bit timer and this
* feature is present in the latest versions of the axi_timer IP)
*
* The timer counter operates in 2 primary modes, compare and capture. In
* either mode, the timer counter may count up or down, with up being the
* default.
*
* Compare mode is typically used for creating a single time period or multiple
* repeating time periods in the auto reload mode, such as a periodic interrupt.
* When started, the timer counter loads an initial value, referred to as the
* compare value, into the timer counter and starts counting down or up. The
* timer counter expires when it rolls over/under depending upon the mode of
* counting. An external compare output signal may be configured such that a
* pulse is generated with this signal when it hits the compare value.
*
* Capture mode is typically used for measuring the time period between
* external events. This mode uses an external capture input signal to cause
* the value of the timer counter to be captured. When started, the timer
* counter loads an initial value, referred to as the compare value,
* The timer can be configured to either cause an interrupt when the count
* reaches the compare value in compare mode or latch the current count
* value in the capture register when an external input is asserted
* in capture mode. The external capture input can be enabled/disabled using the
* XTmrCtr_SetOptions function. While in compare mode, it is also possible to
* drive an external output when the compare value is reached in the count
* register The external compare output can be enabled/disabled using the
* XTmrCtr_SetOptions function.
*
* <b>Interrupts</b>
*
* It is the responsibility of the application to connect the interrupt
* handler of the timer/counter to the interrupt source. The interrupt
* handler function, XTmrCtr_InterruptHandler, is visible such that the user
* can connect it to the interrupt source. Note that this interrupt handler
* does not provide interrupt context save and restore processing, the user
* must perform this processing.
*
* The driver services interrupts and passes timeouts to the upper layer
* software through callback functions. The upper layer software must register
* its callback functions during initialization. The driver requires callback
* functions for timers.
*
* @note
* The default settings for the timers are:
* - Interrupt generation disabled
* - Count up mode
* - Compare mode
* - Hold counter (will not reload the timer)
* - External compare output disabled
* - External capture input disabled
* - Pulse width modulation disabled
* - Timer disabled, waits for Start function to be called
* <br><br>
* A timer counter device may contain multiple timer counters. The symbol
* XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device.
* The device currently contains 2 timer counters.
* <br><br>
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 08/16/01 First release
* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
* 1.10b mta 03/21/07 Updated to new coding style.
* 1.11a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
* file
* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
* definitions.
* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
* for naming consistency (CR 559142).
* 2.02a sdm 09/28/10 Updated the driver tcl to generate the xparameters
* for the timer clock frequency (CR 572679).
* 2.03a rvo 11/30/10 Added check to see if interrupt is enabled before further
* processing for CR 584557.
* 2.04a sdm 07/12/11 Added support for cascade mode operation.
* The cascade mode of operation is present in the latest
* versions of the axi_timer IP. Please check the HW
* Datasheet to see whether this feature is present in the
* version of the IP that you are using.
* 2.05a adk 15/05/13 Fixed the CR:693066
* Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
* XTmrCtr instance structure.
* The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
* the XTmrCtr_Start function.
* The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
* There will be no Initialization done in the
* XTmrCtr_Initialize if both the timers have already started and
* the XST_DEVICE_IS_STARTED Status is returned.
* Removed the logic in the XTmrCtr_Initialize function
* which was checking the Register Value to know whether
* a timer has started or not.
* 3.0 adk 19/12/13 Updated as per the New Tcl API's
* 4.0 als 09/30/15 Updated initialization API.
* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XTmrCtr_CfgInitialize API.
* 4.2 nsk 15/09/16 Updated tcl, to get correct device id for canonical defines,
* when there exist more than one timer perepheral
* ms 01/23/17 Added xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 4.4 ms 04/18/17 Modified tcl file to add suffix U for all macros
* definitions of tmrctr in xparameters.h
* 4.5 cjp 03/22/18 Added APIs to support PWM feature. XTmrCtr_PwmConfigure
* is used to configure PWM to operate for specific period
* and high time. XTmrCtr_PwmEnable and XTmrCtr_PwmDisable
* are used to enable/disable the PWM output.
* 4.6 mus 03/13/19 tmrctr_tapp tcl is updated to support scenario where
* AXI TIMER is interrupting ARM processor through more
* than one interrupt pin. Fix for CR#1024699
* </pre>
*
******************************************************************************/
#ifndef XTMRCTR_H /* prevent circular inclusions */
#define XTMRCTR_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xtmrctr_l.h"
/************************** Constant Definitions *****************************/
/**
* @name Configuration options
* These options are used in XTmrCtr_SetOptions() and XTmrCtr_GetOptions()
* @{
*/
/**
* Used to configure the timer counter device.
* <pre>
* XTC_CASCADE_MODE_OPTION Enables the Cascade Mode only valid for TCSRO.
* XTC_ENABLE_ALL_OPTION Enables all timer counters at once.
* XTC_DOWN_COUNT_OPTION Configures the timer counter to count down from
* start value, the default is to count up.
* XTC_CAPTURE_MODE_OPTION Configures the timer to capture the timer
* counter value when the external capture line is
* asserted. The default mode is compare mode.
* XTC_INT_MODE_OPTION Enables the timer counter interrupt output.
* XTC_AUTO_RELOAD_OPTION In compare mode, configures the timer counter to
* reload from the compare value. The default mode
* causes the timer counter to hold when the
* compare value is hit.
* In capture mode, configures the timer counter to
* not hold the previous capture value if a new
* event occurs. The default mode cause the timer
* counter to hold the capture value until
* recognized.
* XTC_EXT_COMPARE_OPTION Enables the external compare output signal.
* </pre>
*/
#define XTC_CASCADE_MODE_OPTION 0x00000080UL
#define XTC_ENABLE_ALL_OPTION 0x00000040UL
#define XTC_DOWN_COUNT_OPTION 0x00000020UL
#define XTC_CAPTURE_MODE_OPTION 0x00000010UL
#define XTC_INT_MODE_OPTION 0x00000008UL
#define XTC_AUTO_RELOAD_OPTION 0x00000004UL
#define XTC_EXT_COMPARE_OPTION 0x00000002UL
/*@}*/
/* Round division */
#define XTC_ROUND_DIV(a, b) ((a + (b / 2)) / b)
/* Convert clock frequency in hertz to period in nano seconds */
#define XTC_HZ_TO_NS(Hz) XTC_ROUND_DIV(1000000000, Hz)
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress; /**< Register base address */
u32 SysClockFreqHz; /**< The AXI bus clock frequency */
} XTmrCtr_Config;
/**
* Signature for the callback function.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the
* upper layer when the callback is invoked. Its type is
* unimportant to the driver, so it is a void pointer.
* @param TmrCtrNumber is the number of the timer/counter within the
* device. The device typically contains at least two
* timer/counters. The timer number is a zero based number with a
* range of 0 to (XTC_DEVICE_TIMER_COUNT - 1).
*/
typedef void (*XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber);
/**
* Timer/Counter statistics
*/
typedef struct {
u32 Interrupts; /**< The number of interrupts that have occurred */
} XTmrCtrStats;
/**
* The XTmrCtr driver instance data. The user is required to allocate a
* variable of this type for every timer/counter device in the system. A
* pointer to a variable of this type is then passed to the driver API
* functions.
*/
typedef struct {
XTmrCtr_Config Config; /**< Core configuration. */
XTmrCtrStats Stats; /**< Component Statistics */
UINTPTR BaseAddress; /**< Base address of registers */
u32 IsReady; /**< Device is initialized and ready */
u32 IsStartedTmrCtr0; /**< Is Timer Counter 0 started */
u32 IsStartedTmrCtr1; /**< Is Timer Counter 1 started */
u32 IsPwmEnabled; /**< Is PWM Enabled */
XTmrCtr_Handler Handler; /**< Callback function */
void *CallBackRef; /**< Callback reference for handler */
} XTmrCtr;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* Required functions, in file xtmrctr.c */
void XTmrCtr_CfgInitialize(XTmrCtr *InstancePtr, XTmrCtr_Config *ConfigPtr,
UINTPTR EffectiveAddr);
int XTmrCtr_InitHw(XTmrCtr *InstancePtr);
int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId);
void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber,
u32 ResetValue);
u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
u8 XTmrCtr_PwmConfigure(XTmrCtr *InstancePtr, u32 PwmPeriod, u32 PwmHighTime);
void XTmrCtr_PwmEnable(XTmrCtr *InstancePtr);
void XTmrCtr_PwmDisable(XTmrCtr *InstancePtr);
/* Lookup configuration in xtmrctr_sinit.c */
XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId);
/* Functions for options, in file xtmrctr_options.c */
void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options);
u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
/* Functions for statistics, in file xtmrctr_stats.c */
void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr);
void XTmrCtr_ClearStats(XTmrCtr * InstancePtr);
/* Functions for self-test, in file xtmrctr_selftest.c */
int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
/* Functions for interrupts, in file xtmrctr_intr.c */
void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr,
void *CallBackRef);
void XTmrCtr_InterruptHandler(void *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xtmrctr_i.h
+76
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@@ -0,0 +1,76 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xtmrctr_i.h
* @addtogroup tmrctr_v4_6
* @{
*
* This file contains data which is shared between files internal to the
* XTmrCtr component. It is intended for internal use only.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b jhl 02/06/02 First release
* 1.10b mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/30/09 _m is removed from all the macro definitions.
* </pre>
*
******************************************************************************/
#ifndef XTMRCTR_I_H /* prevent circular inclusions */
#define XTMRCTR_I_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern u8 XTmrCtr_Offsets[];
#ifdef __cplusplus
}
#endif
#endif
/** @} */
datalink814_sp/bsp/microblaze_ps/include/xtmrctr_l.h
+437
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@@ -0,0 +1,437 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xtmrctr_l.h
* @addtogroup tmrctr_v4_6
* @{
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* High-level driver functions are defined in xtmrctr.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b jhl 04/24/02 First release
* 1.10b mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
* definitions.
* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
* for naming consistency (CR 559142).
* 2.04a sdm 07/12/11 Added the CASC mode bit in the TCSRO register for the
* cascade mode operation.
* The cascade mode of operation is present in the latest
* versions of the axi_timer IP. Please check the HW
* Datasheet to see whether this feature is present in the
* version of the IP that you are using.
* 4.4 mus 07/21/17 Updated XTmrCtr_DisableIntr macro to not to clear
* T0INT flag
* 4.5 cjp 03/22/18 Added macros for timer/counter instance number and max
* load value.
* </pre>
*
******************************************************************************/
#ifndef XTMRCTR_L_H /* prevent circular inclusions */
#define XTMRCTR_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/**
* Defines the number of timer counters within a single hardware device. This
* number is not currently parameterized in the hardware but may be in the
* future.
*/
#define XTC_DEVICE_TIMER_COUNT 2
/* Each timer counter consumes 16 bytes of address space */
#define XTC_TIMER_COUNTER_OFFSET 16
/* Timer counter instance number used for PWM */
#define XTC_TIMER_0 0
#define XTC_TIMER_1 1
/* Max supported load value for timer/counter */
#define XTC_MAX_LOAD_VALUE 0xFFFFFFFF
/** @name Register Offset Definitions
* Register offsets within a timer counter, there are multiple
* timer counters within a single device
* @{
*/
#define XTC_TCSR_OFFSET 0 /**< Control/Status register */
#define XTC_TLR_OFFSET 4 /**< Load register */
#define XTC_TCR_OFFSET 8 /**< Timer counter register */
/* @} */
/** @name Control Status Register Bit Definitions
* Control Status Register bit masks
* Used to configure the timer counter device.
* @{
*/
#define XTC_CSR_CASC_MASK 0x00000800 /**< Cascade Mode */
#define XTC_CSR_ENABLE_ALL_MASK 0x00000400 /**< Enables all timer
counters */
#define XTC_CSR_ENABLE_PWM_MASK 0x00000200 /**< Enables the Pulse Width
Modulation */
#define XTC_CSR_INT_OCCURED_MASK 0x00000100 /**< If bit is set, an
interrupt has occured.
If set and '1' is
written to this bit
position, bit is
cleared. */
#define XTC_CSR_ENABLE_TMR_MASK 0x00000080 /**< Enables only the
specific timer */
#define XTC_CSR_ENABLE_INT_MASK 0x00000040 /**< Enables the interrupt
output. */
#define XTC_CSR_LOAD_MASK 0x00000020 /**< Loads the timer using
the load value provided
earlier in the Load
Register,
XTC_TLR_OFFSET. */
#define XTC_CSR_AUTO_RELOAD_MASK 0x00000010 /**< In compare mode,
configures
the timer counter to
reload from the
Load Register. The
default mode
causes the timer counter
to hold when the compare
value is hit. In capture
mode, configures the
timer counter to not
hold the previous
capture value if a new
event occurs. The
default mode cause the
timer counter to hold
the capture value until
recognized. */
#define XTC_CSR_EXT_CAPTURE_MASK 0x00000008 /**< Enables the
external input
to the timer counter. */
#define XTC_CSR_EXT_GENERATE_MASK 0x00000004 /**< Enables the
external generate output
for the timer. */
#define XTC_CSR_DOWN_COUNT_MASK 0x00000002 /**< Configures the timer
counter to count down
from start value, the
default is to count
up.*/
#define XTC_CSR_CAPTURE_MODE_MASK 0x00000001 /**< Enables the timer to
capture the timer
counter value when the
external capture line is
asserted. The default
mode is compare mode.*/
/* @} */
/**************************** Type Definitions *******************************/
extern u8 XTmrCtr_Offsets[];
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Read one of the timer counter registers.
*
* @param BaseAddress contains the base address of the timer counter
* device.
* @param TmrCtrNumber contains the specific timer counter within the
* device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
* @param RegOffset contains the offset from the 1st register of the timer
* counter to select the specific register of the timer counter.
*
* @return The value read from the register, a 32 bit value.
*
* @note C-Style signature:
* u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber,
unsigned RegOffset);
******************************************************************************/
#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
(RegOffset))
#ifndef XTimerCtr_ReadReg
#define XTimerCtr_ReadReg XTmrCtr_ReadReg
#endif
/*****************************************************************************/
/**
* Write a specified value to a register of a timer counter.
*
* @param BaseAddress is the base address of the timer counter device.
* @param TmrCtrNumber is the specific timer counter within the device, a
* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
* @param RegOffset contain the offset from the 1st register of the timer
* counter to select the specific register of the timer counter.
* @param ValueToWrite is the 32 bit value to be written to the register.
*
* @note C-Style signature:
* void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber,
* unsigned RegOffset, u32 ValueToWrite);
******************************************************************************/
#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
(RegOffset)), (ValueToWrite))
/****************************************************************************/
/**
*
* Set the Control Status Register of a timer counter to the specified value.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device, a
* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
* @param RegisterValue is the 32 bit value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XTmrCtr_SetControlStatusReg(u32 BaseAddress,
* u8 TmrCtrNumber,u32 RegisterValue);
*****************************************************************************/
#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(RegisterValue))
/****************************************************************************/
/**
*
* Get the Control Status Register of a timer counter.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device,
* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return The value read from the register, a 32 bit value.
*
* @note C-Style signature:
* u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress,
* u8 TmrCtrNumber);
*****************************************************************************/
#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber) \
XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
/****************************************************************************/
/**
*
* Get the Timer Counter Register of a timer counter.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device,
* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return The value read from the register, a 32 bit value.
*
* @note C-Style signature:
* u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress,
* u8 TmrCtrNumber);
*****************************************************************************/
#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber) \
XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \
/****************************************************************************/
/**
*
* Set the Load Register of a timer counter to the specified value.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device, a
* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
* @param RegisterValue is the 32 bit value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber,
* u32 RegisterValue);
*****************************************************************************/
#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue) \
XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \
(RegisterValue))
/****************************************************************************/
/**
*
* Get the Load Register of a timer counter.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device, a
* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return The value read from the register, a 32 bit value.
*
* @note C-Style signature:
* u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber);
*****************************************************************************/
#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber) \
XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET)
/****************************************************************************/
/**
*
* Enable a timer counter such that it starts running.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device, a
* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return None.
*
* @note C-Style signature:
* void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber);
*****************************************************************************/
#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber) \
XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \
XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK))
/****************************************************************************/
/**
*
* Disable a timer counter such that it stops running.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device,
* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return None.
*
* @note C-Style signature:
* void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber);
*****************************************************************************/
#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber) \
XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK))
/****************************************************************************/
/**
*
* Enable the interrupt for a timer counter.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device, a
* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return None.
*
* @note C-Style signature:
* void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber);
*****************************************************************************/
#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber) \
XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK))
/****************************************************************************/
/**
*
* Disable the interrupt for a timer counter.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device, a
* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return None.
*
* @note C-Style signature:
* void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber);
*****************************************************************************/
#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber) \
XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
XTC_TCSR_OFFSET) & ~ (XTC_CSR_ENABLE_INT_MASK \
| XTC_CSR_INT_OCCURED_MASK)))
/****************************************************************************/
/**
*
* Cause the timer counter to load it's Timer Counter Register with the value
* in the Load Register.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device, a
* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return None.
*
* @note C-Style signature:
* void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress,
u8 TmrCtrNumber);
*****************************************************************************/
#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber) \
XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK))
/****************************************************************************/
/**
*
* Determine if a timer counter event has occurred. Events are defined to be
* when a capture has occurred or the counter has roller over.
*
* @param BaseAddress is the base address of the device.
* @param TmrCtrNumber is the specific timer counter within the device, a
* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
*
* @note C-Style signature:
* int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber);
*****************************************************************************/
#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber) \
((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) == \
XTC_CSR_INT_OCCURED_MASK)
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */