Initial version.
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/******************************************************************************
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*
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* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xil_cache.h
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*
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* The xil_cache.h file contains cache related driver functions (or macros)
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* that can be used to access the device. The user should refer to the
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* hardware device specification for more details of the device operation.
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* The functions in this header file can be used across all Xilinx supported
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* processors.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00 hbm 07/28/09 Initial release
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* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that
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* the correct cache flush routines are used based on
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* whether the write-back or write-through caches are
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* used (cr #630532).
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* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system
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* cache/L2 cache. The existing/old APIs/macros in this
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* file are renamed to imply that they deal with L1 cache.
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* New macros/APIs are added to address similar features for
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* L2 cache. Users can include this file in their application
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* to use the various cache related APIs. These changes are
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* done for implementing PR #697214.
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*
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* </pre>
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*
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* @note
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*
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******************************************************************************/
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#ifndef XIL_CACHE_H
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#define XIL_CACHE_H
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#if defined XENV_VXWORKS
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/* VxWorks environment */
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#error "Unknown processor / architecture. Must be PPC for VxWorks."
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#else
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/* standalone environment */
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#include "mb_interface.h"
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#include "xil_types.h"
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#include "xparameters.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/****************************************************************************/
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/**
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*
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* @brief Invalidate the entire L1 data cache. If the cacheline is modified
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* (dirty), the modified contents are lost.
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*
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* @param None.
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*
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* @return None.
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*
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* @note
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*
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* Processor must be in real mode.
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****************************************************************************/
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#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
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/****************************************************************************/
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/**
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*
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* @brief Invalidate the entire L2 data cache. If the cacheline is modified
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* (dirty),the modified contents are lost.
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*
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* @param None.
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*
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* @return None.
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*
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* @note
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*
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* Processor must be in real mode.
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****************************************************************************/
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#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
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/****************************************************************************/
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/**
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*
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* @brief Invalidate the L1 data cache for the given address range.
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* If the bytes specified by the address (Addr) are cached by the L1
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* data cache, the cacheline containing that byte is invalidated.If
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* the cacheline is modified (dirty), the modified contents are lost.
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*
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* @param Addr is address of ragne to be invalidated.
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* @param Len is the length in bytes to be invalidated.
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*
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* @return None.
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*
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* @note
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*
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* Processor must be in real mode.
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****************************************************************************/
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#define Xil_L1DCacheInvalidateRange(Addr, Len) \
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microblaze_invalidate_dcache_range((Addr), (Len))
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/****************************************************************************/
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/**
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*
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* @brief Invalidate the L1 data cache for the given address range.
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* If the bytes specified by the address (Addr) are cached by the
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* L1 data cache, the cacheline containing that byte is invalidated.
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* If the cacheline is modified (dirty), the modified contents are lost.
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*
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* @param Addr: address of ragne to be invalidated.
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* @param Len: length in bytes to be invalidated.
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*
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* @return None.
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*
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* @note
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* Processor must be in real mode.
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****************************************************************************/
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#define Xil_L2CacheInvalidateRange(Addr, Len) \
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microblaze_invalidate_cache_ext_range((Addr), (Len))
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/****************************************************************************/
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/**
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* @brief Flush the L1 data cache for the given address range.
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* If the bytes specified by the address (Addr) are cached by the
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* data cache, and is modified (dirty), the cacheline will be written
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* to system memory.The cacheline will also be invalidated.
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*
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* @param Addr: the starting address of the range to be flushed.
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* @param Len: length in byte to be flushed.
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*
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* @return None.
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*
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****************************************************************************/
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#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
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# define Xil_L1DCacheFlushRange(Addr, Len) \
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microblaze_flush_dcache_range((Addr), (Len))
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#else
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# define Xil_L1DCacheFlushRange(Addr, Len) \
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microblaze_invalidate_dcache_range((Addr), (Len))
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#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
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/****************************************************************************/
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/**
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* @brief Flush the L2 data cache for the given address range.
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* If the bytes specified by the address (Addr) are cached by the
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* data cache, and is modified (dirty), the cacheline will be
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* written to system memory. The cacheline will also be invalidated.
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*
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* @param Addr: the starting address of the range to be flushed.
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* @param Len: length in byte to be flushed.
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_L2CacheFlushRange(Addr, Len) \
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microblaze_flush_cache_ext_range((Addr), (Len))
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/****************************************************************************/
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/**
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* @brief Flush the entire L1 data cache. If any cacheline is dirty, the
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* cacheline will be written to system memory. The entire data cache
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* will be invalidated.
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*
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* @return None.
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*
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****************************************************************************/
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#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
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# define Xil_L1DCacheFlush() microblaze_flush_dcache()
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#else
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# define Xil_L1DCacheFlush() microblaze_invalidate_dcache()
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#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
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/****************************************************************************/
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/**
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* @brief Flush the entire L2 data cache. If any cacheline is dirty, the
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* cacheline will be written to system memory. The entire data cache
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* will be invalidated.
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_L2CacheFlush() microblaze_flush_cache_ext()
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/****************************************************************************/
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/**
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*
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* @brief Invalidate the instruction cache for the given address range.
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*
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* @param Addr is address of ragne to be invalidated.
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* @param Len is the length in bytes to be invalidated.
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_L1ICacheInvalidateRange(Addr, Len) \
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microblaze_invalidate_icache_range((Addr), (Len))
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/****************************************************************************/
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/**
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*
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* @brief Invalidate the entire instruction cache.
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*
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* @param None
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_L1ICacheInvalidate() \
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microblaze_invalidate_icache()
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/****************************************************************************/
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/**
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*
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* @brief Enable the L1 data cache.
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*
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* @return None.
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*
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* @note This is processor specific.
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*
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****************************************************************************/
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#define Xil_L1DCacheEnable() \
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microblaze_enable_dcache()
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/****************************************************************************/
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/**
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*
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* @brief Disable the L1 data cache.
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*
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* @return None.
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*
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* @note This is processor specific.
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*
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****************************************************************************/
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#define Xil_L1DCacheDisable() \
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microblaze_disable_dcache()
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/****************************************************************************/
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/**
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*
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* @brief Enable the instruction cache.
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*
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* @return None.
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*
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* @note This is processor specific.
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*
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****************************************************************************/
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#define Xil_L1ICacheEnable() \
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microblaze_enable_icache()
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/****************************************************************************/
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/**
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*
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* @brief Disable the L1 Instruction cache.
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*
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* @return None.
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*
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* @note This is processor specific.
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*
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****************************************************************************/
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#define Xil_L1ICacheDisable() \
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microblaze_disable_icache()
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/****************************************************************************/
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/**
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*
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* @brief Enable the data cache.
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*
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* @param None
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_DCacheEnable() Xil_L1DCacheEnable()
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/****************************************************************************/
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/**
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*
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* @brief Enable the instruction cache.
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*
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* @param None
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*
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* @return None.
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*
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* @note
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*
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*
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****************************************************************************/
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#define Xil_ICacheEnable() Xil_L1ICacheEnable()
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/****************************************************************************
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*
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* @brief Invalidate the entire Data cache.
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*
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* @param None.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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#define Xil_DCacheInvalidate() \
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Xil_L2CacheInvalidate(); \
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Xil_L1DCacheInvalidate();
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/****************************************************************************
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*
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* @brief Invalidate the Data cache for the given address range.
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* If the bytes specified by the address (adr) are cached by the
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* Data cache, the cacheline containing that byte is invalidated.
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* If the cacheline is modified (dirty), the modified contents are
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* lost and are NOT written to system memory before the line is
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* invalidated.
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*
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* @param Addr: Start address of ragne to be invalidated.
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* @param Len: Length of range to be invalidated in bytes.
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_DCacheInvalidateRange(Addr, Len) \
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Xil_L2CacheInvalidateRange((Addr), (Len)); \
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Xil_L1DCacheInvalidateRange((Addr), (Len));
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/****************************************************************************
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*
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* @brief Flush the entire Data cache.
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*
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* @param None.
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_DCacheFlush() \
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Xil_L2CacheFlush(); \
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Xil_L1DCacheFlush();
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/****************************************************************************
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* @brief Flush the Data cache for the given address range.
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* If the bytes specified by the address (adr) are cached by the
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* Data cache, the cacheline containing that byte is invalidated.
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* If the cacheline is modified (dirty), the written to system
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* memory first before the before the line is invalidated.
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*
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* @param Addr: Start address of range to be flushed.
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* @param Len: Length of range to be flushed in bytes.
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_DCacheFlushRange(Addr, Len) \
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Xil_L2CacheFlushRange((Addr), (Len)); \
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Xil_L1DCacheFlushRange((Addr), (Len));
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/****************************************************************************
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*
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* @brief Invalidate the entire instruction cache.
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*
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* @param None.
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_ICacheInvalidate() \
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Xil_L2CacheInvalidate(); \
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Xil_L1ICacheInvalidate();
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/****************************************************************************
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*
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* @brief Invalidate the instruction cache for the given address range.
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* If the bytes specified by the address (adr) are cached by the
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* Data cache, the cacheline containing that byte is invalidated.
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* If the cacheline is modified (dirty), the modified contents are
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* lost and are NOT written to system memory before the line is
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* invalidated.
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*
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* @param Addr: Start address of ragne to be invalidated.
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* @param Len: Length of range to be invalidated in bytes.
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_ICacheInvalidateRange(Addr, Len) \
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Xil_L2CacheInvalidateRange((Addr), (Len)); \
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Xil_L1ICacheInvalidateRange((Addr), (Len));
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void Xil_DCacheDisable(void);
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void Xil_ICacheDisable(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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/**
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* @} End of "addtogroup microblaze_cache_apis".
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||||
*/
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Reference in New Issue
Block a user