Initial version.
This commit is contained in:
Gatsby Van
@@ -0,0 +1,437 @@
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/******************************************************************************
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*
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* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xtmrctr_l.h
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* @addtogroup tmrctr_v4_6
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* @{
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*
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* This header file contains identifiers and low-level driver functions (or
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* macros) that can be used to access the device. The user should refer to the
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* hardware device specification for more details of the device operation.
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* High-level driver functions are defined in xtmrctr.h.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00b jhl 04/24/02 First release
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* 1.10b mta 03/21/07 Updated to new coding style
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* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
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* definitions.
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* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
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* for naming consistency (CR 559142).
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* 2.04a sdm 07/12/11 Added the CASC mode bit in the TCSRO register for the
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* cascade mode operation.
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* The cascade mode of operation is present in the latest
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* versions of the axi_timer IP. Please check the HW
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* Datasheet to see whether this feature is present in the
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* version of the IP that you are using.
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* 4.4 mus 07/21/17 Updated XTmrCtr_DisableIntr macro to not to clear
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* T0INT flag
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* 4.5 cjp 03/22/18 Added macros for timer/counter instance number and max
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* load value.
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* </pre>
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*
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******************************************************************************/
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#ifndef XTMRCTR_L_H /* prevent circular inclusions */
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#define XTMRCTR_L_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/**
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* Defines the number of timer counters within a single hardware device. This
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* number is not currently parameterized in the hardware but may be in the
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* future.
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*/
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#define XTC_DEVICE_TIMER_COUNT 2
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/* Each timer counter consumes 16 bytes of address space */
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#define XTC_TIMER_COUNTER_OFFSET 16
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/* Timer counter instance number used for PWM */
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#define XTC_TIMER_0 0
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#define XTC_TIMER_1 1
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/* Max supported load value for timer/counter */
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#define XTC_MAX_LOAD_VALUE 0xFFFFFFFF
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/** @name Register Offset Definitions
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* Register offsets within a timer counter, there are multiple
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* timer counters within a single device
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* @{
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*/
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#define XTC_TCSR_OFFSET 0 /**< Control/Status register */
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#define XTC_TLR_OFFSET 4 /**< Load register */
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#define XTC_TCR_OFFSET 8 /**< Timer counter register */
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/* @} */
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/** @name Control Status Register Bit Definitions
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* Control Status Register bit masks
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* Used to configure the timer counter device.
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* @{
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*/
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#define XTC_CSR_CASC_MASK 0x00000800 /**< Cascade Mode */
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#define XTC_CSR_ENABLE_ALL_MASK 0x00000400 /**< Enables all timer
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counters */
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#define XTC_CSR_ENABLE_PWM_MASK 0x00000200 /**< Enables the Pulse Width
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Modulation */
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#define XTC_CSR_INT_OCCURED_MASK 0x00000100 /**< If bit is set, an
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interrupt has occured.
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If set and '1' is
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written to this bit
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position, bit is
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cleared. */
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#define XTC_CSR_ENABLE_TMR_MASK 0x00000080 /**< Enables only the
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specific timer */
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#define XTC_CSR_ENABLE_INT_MASK 0x00000040 /**< Enables the interrupt
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output. */
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#define XTC_CSR_LOAD_MASK 0x00000020 /**< Loads the timer using
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the load value provided
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earlier in the Load
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Register,
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XTC_TLR_OFFSET. */
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#define XTC_CSR_AUTO_RELOAD_MASK 0x00000010 /**< In compare mode,
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configures
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the timer counter to
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reload from the
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Load Register. The
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default mode
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causes the timer counter
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to hold when the compare
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value is hit. In capture
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mode, configures the
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timer counter to not
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hold the previous
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capture value if a new
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event occurs. The
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default mode cause the
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timer counter to hold
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the capture value until
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recognized. */
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#define XTC_CSR_EXT_CAPTURE_MASK 0x00000008 /**< Enables the
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external input
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to the timer counter. */
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#define XTC_CSR_EXT_GENERATE_MASK 0x00000004 /**< Enables the
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external generate output
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for the timer. */
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#define XTC_CSR_DOWN_COUNT_MASK 0x00000002 /**< Configures the timer
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counter to count down
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from start value, the
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default is to count
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up.*/
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#define XTC_CSR_CAPTURE_MODE_MASK 0x00000001 /**< Enables the timer to
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capture the timer
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counter value when the
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external capture line is
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asserted. The default
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mode is compare mode.*/
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/* @} */
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/**************************** Type Definitions *******************************/
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extern u8 XTmrCtr_Offsets[];
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/***************** Macros (Inline Functions) Definitions *********************/
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/*****************************************************************************/
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/**
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* Read one of the timer counter registers.
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*
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* @param BaseAddress contains the base address of the timer counter
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* device.
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* @param TmrCtrNumber contains the specific timer counter within the
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* device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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* @param RegOffset contains the offset from the 1st register of the timer
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* counter to select the specific register of the timer counter.
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*
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* @return The value read from the register, a 32 bit value.
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*
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* @note C-Style signature:
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* u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber,
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unsigned RegOffset);
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******************************************************************************/
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#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
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Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
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(RegOffset))
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#ifndef XTimerCtr_ReadReg
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#define XTimerCtr_ReadReg XTmrCtr_ReadReg
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#endif
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/*****************************************************************************/
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/**
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* Write a specified value to a register of a timer counter.
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*
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* @param BaseAddress is the base address of the timer counter device.
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* @param TmrCtrNumber is the specific timer counter within the device, a
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* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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* @param RegOffset contain the offset from the 1st register of the timer
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* counter to select the specific register of the timer counter.
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* @param ValueToWrite is the 32 bit value to be written to the register.
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*
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* @note C-Style signature:
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* void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber,
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* unsigned RegOffset, u32 ValueToWrite);
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******************************************************************************/
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#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
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Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
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(RegOffset)), (ValueToWrite))
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/****************************************************************************/
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/**
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*
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* Set the Control Status Register of a timer counter to the specified value.
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*
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* @param BaseAddress is the base address of the device.
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* @param TmrCtrNumber is the specific timer counter within the device, a
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* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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* @param RegisterValue is the 32 bit value to be written to the register.
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XTmrCtr_SetControlStatusReg(u32 BaseAddress,
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* u8 TmrCtrNumber,u32 RegisterValue);
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*****************************************************************************/
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#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
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XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
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(RegisterValue))
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/****************************************************************************/
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/**
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*
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* Get the Control Status Register of a timer counter.
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*
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* @param BaseAddress is the base address of the device.
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* @param TmrCtrNumber is the specific timer counter within the device,
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* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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*
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* @return The value read from the register, a 32 bit value.
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*
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* @note C-Style signature:
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* u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress,
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* u8 TmrCtrNumber);
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*****************************************************************************/
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#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber) \
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XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
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/****************************************************************************/
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/**
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*
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* Get the Timer Counter Register of a timer counter.
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*
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* @param BaseAddress is the base address of the device.
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* @param TmrCtrNumber is the specific timer counter within the device,
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* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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*
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* @return The value read from the register, a 32 bit value.
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*
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* @note C-Style signature:
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* u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress,
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* u8 TmrCtrNumber);
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*****************************************************************************/
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#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber) \
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XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \
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/****************************************************************************/
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/**
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*
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* Set the Load Register of a timer counter to the specified value.
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*
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* @param BaseAddress is the base address of the device.
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* @param TmrCtrNumber is the specific timer counter within the device, a
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* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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* @param RegisterValue is the 32 bit value to be written to the register.
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber,
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* u32 RegisterValue);
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*****************************************************************************/
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#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue) \
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XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \
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(RegisterValue))
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/****************************************************************************/
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/**
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*
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* Get the Load Register of a timer counter.
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*
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* @param BaseAddress is the base address of the device.
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* @param TmrCtrNumber is the specific timer counter within the device, a
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* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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*
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* @return The value read from the register, a 32 bit value.
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*
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* @note C-Style signature:
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* u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber);
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*****************************************************************************/
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#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber) \
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XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET)
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/****************************************************************************/
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/**
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*
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* Enable a timer counter such that it starts running.
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*
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* @param BaseAddress is the base address of the device.
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* @param TmrCtrNumber is the specific timer counter within the device, a
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* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber);
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*****************************************************************************/
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#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber) \
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XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
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(XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \
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XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK))
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/****************************************************************************/
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/**
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*
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* Disable a timer counter such that it stops running.
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*
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* @param BaseAddress is the base address of the device.
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* @param TmrCtrNumber is the specific timer counter within the device,
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* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber);
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*****************************************************************************/
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#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber) \
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XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
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(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
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XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK))
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/****************************************************************************/
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/**
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*
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* Enable the interrupt for a timer counter.
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*
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* @param BaseAddress is the base address of the device.
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* @param TmrCtrNumber is the specific timer counter within the device, a
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* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber);
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*****************************************************************************/
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#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber) \
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XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
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(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
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XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK))
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/****************************************************************************/
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/**
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*
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* Disable the interrupt for a timer counter.
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*
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* @param BaseAddress is the base address of the device.
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* @param TmrCtrNumber is the specific timer counter within the device, a
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* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber);
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*****************************************************************************/
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#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber) \
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XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
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(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
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XTC_TCSR_OFFSET) & ~ (XTC_CSR_ENABLE_INT_MASK \
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| XTC_CSR_INT_OCCURED_MASK)))
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/****************************************************************************/
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/**
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*
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* Cause the timer counter to load it's Timer Counter Register with the value
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* in the Load Register.
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*
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* @param BaseAddress is the base address of the device.
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* @param TmrCtrNumber is the specific timer counter within the device, a
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* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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*
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* @return None.
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*
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||||
* @note C-Style signature:
|
||||
* void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress,
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u8 TmrCtrNumber);
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*****************************************************************************/
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#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber) \
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XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
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(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
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XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK))
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||||
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/****************************************************************************/
|
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/**
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||||
*
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* Determine if a timer counter event has occurred. Events are defined to be
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* when a capture has occurred or the counter has roller over.
|
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*
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* @param BaseAddress is the base address of the device.
|
||||
* @param TmrCtrNumber is the specific timer counter within the device, a
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* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
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||||
*
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||||
* @note C-Style signature:
|
||||
* int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber);
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||||
*****************************************************************************/
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#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber) \
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((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
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XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) == \
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XTC_CSR_INT_OCCURED_MASK)
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
/************************** Variable Definitions *****************************/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
Reference in New Issue
Block a user