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Gatsby Van
2023-12-20 00:11:03 +08:00
commit 416bd53733
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datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/Makefile
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I${INCLUDEDIR}
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
LIBSOURCES=*.c
INCLUDEFILES=*.h
libs:
echo "Compiling axidma"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OBJECTS)
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf $(OBJECTS)
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma.c
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/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma.c
* @addtogroup axidma_v9_9
* @{
*
* This file implements DMA engine-wise initialization and control functions.
* For more information on the implementation of this driver, see xaxidma.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 4.00a rkv 02/22/11 Added support for simple DMA mode
* New API added for simple DMA mode are
* - XAxiDma_Busy
* - XAxiDma_SimpleTransfer
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA mode.
* - Changed APIs:
* * XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
* u32 BuffAddr, u32 Length,
* int Direction, int RingIndex)
* - New API:
* * XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
* int Direction, int Select)
* 7.00a srt 06/18/12 All the APIs changed in v6_00_a are reverted back for
* backward compatibility.
* 7.01a srt 10/26/12 Fixed issue with driver as it fails with IP version
* < 6.00a as the parameter C_NUM_*_CHANNELS is not
* applicable.
* 8.0 srt 01/29/14 Added support for Micro DMA Mode and Cyclic mode of
* operations.
* - New API:
* * XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr,
* int Direction, int Select)
* 9.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
*
* 9.1 vak 11/18/15 Removed warnings in the driver and examples (CR# 911664)
* 9.5 adk 26/10/17 Fix race condition in the XAxiDma_Reset() API. This API
* assumes a tx channel is always present it may be configured
* for rx only.
* 9.6 rsp 01/11/18 In XAxiDma_Reset() use UINTPTR for storing RegBase CR#976392
* 9.7 rsp 04/25/18 Add support for 64MB data transfer. Read max buffer length
* width from config structure. CR #1000474
* 9.8 rsp 07/11/18 Fix cppcheck style warnings. CR #1006164
*
* </pre>
******************************************************************************/
/***************************** Include Files *********************************/
#include "xaxidma.h"
/************************** Constant Definitions *****************************/
/* Loop counter to check reset done
*/
#define XAXIDMA_RESET_TIMEOUT 500
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static int XAxiDma_Start(XAxiDma * InstancePtr);
static int XAxiDma_Started(XAxiDma * InstancePtr);
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* This function initializes a DMA engine. This function must be called
* prior to using a DMA engine. Initializing a engine includes setting
* up the register base address, setting up the instance data, and ensuring the
* hardware is in a quiescent state.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
* @param Config is a pointer to an XAxiDma_Config structure. It contains
* the information about the hardware build, including base
* address,and whether status control stream (StsCntrlStrm), MM2S
* and S2MM are included in the build.
*
* @return
* - XST_SUCCESS for successful initialization
* - XST_INVALID_PARAM if pointer to the configuration structure
* is NULL
* - XST_DMA_ERROR if reset operation failed at the end of
* initialization
*
* @note We assume the hardware building tool will check and error out
* for a hardware build that has no transfer channels.
*****************************************************************************/
int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config)
{
UINTPTR BaseAddr;
int TimeOut;
int Index;
u32 MaxTransferLen;
InstancePtr->Initialized = 0;
if(!Config) {
return XST_INVALID_PARAM;
}
BaseAddr = Config->BaseAddr;
/* Setup the instance */
memset(InstancePtr, 0, sizeof(XAxiDma));
InstancePtr->RegBase = BaseAddr;
/* Get hardware setting information from the configuration structure
*/
InstancePtr->HasMm2S = Config->HasMm2S;
InstancePtr->HasS2Mm = Config->HasS2Mm;
InstancePtr->HasSg = Config->HasSg;
InstancePtr->MicroDmaMode = Config->MicroDmaMode;
InstancePtr->AddrWidth = Config->AddrWidth;
/* Get the number of channels */
InstancePtr->TxNumChannels = Config->Mm2sNumChannels;
InstancePtr->RxNumChannels = Config->S2MmNumChannels;
/* This condition is for IP version < 6.00a */
if (!InstancePtr->TxNumChannels)
InstancePtr->TxNumChannels = 1;
if (!InstancePtr->RxNumChannels)
InstancePtr->RxNumChannels = 1;
if ((InstancePtr->RxNumChannels > 1) ||
(InstancePtr->TxNumChannels > 1)) {
MaxTransferLen =
XAXIDMA_MCHAN_MAX_TRANSFER_LEN;
}
else {
MaxTransferLen = (1U << Config->SgLengthWidth) - 1;
}
/* Initialize the ring structures */
InstancePtr->TxBdRing.RunState = AXIDMA_CHANNEL_HALTED;
InstancePtr->TxBdRing.IsRxChannel = 0;
if (!InstancePtr->MicroDmaMode) {
InstancePtr->TxBdRing.MaxTransferLen = MaxTransferLen;
}
else {
/* In MicroDMA mode, Maximum length that can be transferred
* is '(Memory Data Width / 4) * Burst Size'
*/
InstancePtr->TxBdRing.MaxTransferLen =
((Config->Mm2SDataWidth / 4) *
Config->Mm2SBurstSize);
}
InstancePtr->TxBdRing.RingIndex = 0;
for (Index = 0; Index < InstancePtr->RxNumChannels; Index++) {
InstancePtr->RxBdRing[Index].RunState
= AXIDMA_CHANNEL_HALTED;
InstancePtr->RxBdRing[Index].IsRxChannel = 1;
InstancePtr->RxBdRing[Index].RingIndex = Index;
}
if (InstancePtr->HasMm2S) {
InstancePtr->TxBdRing.ChanBase =
BaseAddr + XAXIDMA_TX_OFFSET;
InstancePtr->TxBdRing.HasStsCntrlStrm =
Config->HasStsCntrlStrm;
if (InstancePtr->AddrWidth > 32)
InstancePtr->TxBdRing.Addr_ext = 1;
else
InstancePtr->TxBdRing.Addr_ext = 0;
InstancePtr->TxBdRing.HasDRE = Config->HasMm2SDRE;
InstancePtr->TxBdRing.DataWidth =
((unsigned int)Config->Mm2SDataWidth >> 3);
}
if (InstancePtr->HasS2Mm) {
for (Index = 0;
Index < InstancePtr->RxNumChannels; Index++) {
InstancePtr->RxBdRing[Index].ChanBase =
BaseAddr + XAXIDMA_RX_OFFSET;
InstancePtr->RxBdRing[Index].HasStsCntrlStrm =
Config->HasStsCntrlStrm;
InstancePtr->RxBdRing[Index].HasDRE =
Config->HasS2MmDRE;
InstancePtr->RxBdRing[Index].DataWidth =
((unsigned int)Config->S2MmDataWidth >> 3);
if (!InstancePtr->MicroDmaMode) {
InstancePtr->RxBdRing[Index].MaxTransferLen =
MaxTransferLen;
}
else {
/* In MicroDMA mode, Maximum length that can be transferred
* is '(Memory Data Width / 4) * Burst Size'
*/
InstancePtr->RxBdRing[Index].MaxTransferLen =
((Config->S2MmDataWidth / 4) *
Config->S2MmBurstSize);
}
if (InstancePtr->AddrWidth > 32)
InstancePtr->RxBdRing[Index].Addr_ext = 1;
else
InstancePtr->RxBdRing[Index].Addr_ext = 0;
}
}
/* Reset the engine so the hardware starts from a known state
*/
XAxiDma_Reset(InstancePtr);
/* At the initialization time, hardware should finish reset quickly
*/
TimeOut = XAXIDMA_RESET_TIMEOUT;
while (TimeOut) {
if(XAxiDma_ResetIsDone(InstancePtr)) {
break;
}
TimeOut -= 1;
}
if (!TimeOut) {
xdbg_printf(XDBG_DEBUG_ERROR, "Failed reset in"
"initialize\r\n");
/* Need system hard reset to recover
*/
InstancePtr->Initialized = 0;
return XST_DMA_ERROR;
}
/* Initialization is successful
*/
InstancePtr->Initialized = 1;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* Reset both TX and RX channels of a DMA engine.
*
* Reset one channel resets the whole AXI DMA engine.
*
* Any DMA transaction in progress will finish gracefully before engine starts
* reset. Any other transactions that have been submitted to hardware will be
* discarded by the hardware.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return None
*
* @note After the reset:
* - All interrupts are disabled.
* - Engine is halted
*
******************************************************************************/
void XAxiDma_Reset(XAxiDma * InstancePtr)
{
UINTPTR RegBase;
XAxiDma_BdRing *TxRingPtr;
XAxiDma_BdRing *RxRingPtr;
int RingIndex;
if (InstancePtr->HasMm2S) {
TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
/* Save the locations of current BDs both rings are working on
* before the reset so later we can resume the rings smoothly.
*/
if(XAxiDma_HasSg(InstancePtr)){
XAxiDma_BdRingSnapShotCurrBd(TxRingPtr);
for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels;
RingIndex++) {
RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr,
RingIndex);
XAxiDma_BdRingSnapShotCurrBd(RxRingPtr);
}
}
}
/* Reset
*/
if (InstancePtr->HasMm2S) {
RegBase = InstancePtr->RegBase + XAXIDMA_TX_OFFSET;
}
else {
RegBase = InstancePtr->RegBase + XAXIDMA_RX_OFFSET;
}
XAxiDma_WriteReg(RegBase, XAXIDMA_CR_OFFSET, XAXIDMA_CR_RESET_MASK);
/* Set TX/RX Channel state */
if (InstancePtr->HasMm2S) {
TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
TxRingPtr->RunState = AXIDMA_CHANNEL_HALTED;
}
if (InstancePtr->HasS2Mm) {
for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels;
RingIndex++) {
RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, RingIndex);
if (InstancePtr->HasS2Mm) {
RxRingPtr->RunState = AXIDMA_CHANNEL_HALTED;
}
}
}
}
/*****************************************************************************/
/**
*
* Check whether reset is done
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return
* - 1 if reset is done.
* - 0 if reset is not done
*
* @note None
*
******************************************************************************/
int XAxiDma_ResetIsDone(XAxiDma * InstancePtr)
{
u32 RegisterValue;
XAxiDma_BdRing *TxRingPtr;
XAxiDma_BdRing *RxRingPtr;
TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
RxRingPtr = XAxiDma_GetRxRing(InstancePtr);
/* Check transmit channel
*/
if (InstancePtr->HasMm2S) {
RegisterValue = XAxiDma_ReadReg(TxRingPtr->ChanBase,
XAXIDMA_CR_OFFSET);
/* Reset is done when the reset bit is low
*/
if(RegisterValue & XAXIDMA_CR_RESET_MASK) {
return 0;
}
}
/* Check receive channel
*/
if (InstancePtr->HasS2Mm) {
RegisterValue = XAxiDma_ReadReg(RxRingPtr->ChanBase,
XAXIDMA_CR_OFFSET);
/* Reset is done when the reset bit is low
*/
if(RegisterValue & XAXIDMA_CR_RESET_MASK) {
return 0;
}
}
return 1;
}
/*****************************************************************************/
/*
* Start the DMA engine.
*
* Start a halted engine. Processing of BDs is not started.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return
* - XST_SUCCESS for success
* - XST_NOT_SGDMA if the driver instance has not been initialized
* - XST_DMA_ERROR if starting the hardware channel fails
*
* @note None
*
*****************************************************************************/
static int XAxiDma_Start(XAxiDma * InstancePtr)
{
int Status;
if (!InstancePtr->Initialized) {
xdbg_printf(XDBG_DEBUG_ERROR, "Start: Driver not initialized "
"%d\r\n", InstancePtr->Initialized);
return XST_NOT_SGDMA;
}
if (InstancePtr->HasMm2S) {
XAxiDma_BdRing *TxRingPtr;
TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
if (TxRingPtr->RunState == AXIDMA_CHANNEL_HALTED) {
/* Start the channel
*/
if(XAxiDma_HasSg(InstancePtr)) {
Status = XAxiDma_BdRingStart(TxRingPtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Start hw tx channel failed %d\r\n",
Status);
return XST_DMA_ERROR;
}
}
else {
XAxiDma_WriteReg(TxRingPtr->ChanBase,
XAXIDMA_CR_OFFSET,
XAxiDma_ReadReg(TxRingPtr->ChanBase,
XAXIDMA_CR_OFFSET)
| XAXIDMA_CR_RUNSTOP_MASK);
}
TxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;
}
}
if (InstancePtr->HasS2Mm) {
int RingIndex = 0;
for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels;
RingIndex++) {
XAxiDma_BdRing *RxRingPtr;
RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr,
RingIndex);
if (RxRingPtr->RunState != AXIDMA_CHANNEL_HALTED) {
return XST_SUCCESS;
}
/* Start the channel
*/
if(XAxiDma_HasSg(InstancePtr)) {
Status = XAxiDma_BdRingStart(RxRingPtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Start hw tx channel failed %d\r\n",
Status);
return XST_DMA_ERROR;
}
}
else {
XAxiDma_WriteReg(RxRingPtr->ChanBase,
XAXIDMA_CR_OFFSET,
XAxiDma_ReadReg(RxRingPtr->ChanBase,
XAXIDMA_CR_OFFSET) |
XAXIDMA_CR_RUNSTOP_MASK);
}
RxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;
}
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* Pause DMA transactions on both channels.
*
* If the engine is running and doing transfers, this function does not stop
* the DMA transactions immediately, because then hardware will throw away
* our previously queued transfers. All submitted transfers will finish.
* Transfers submitted after this function will not start until
* XAxiDma_BdRingStart() or XAxiDma_Resume() is called.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return
* - XST_SUCCESS if successful
* - XST_NOT_SGDMA, if the driver instance is not initialized
*
* @note None
*
*****************************************************************************/
int XAxiDma_Pause(XAxiDma * InstancePtr)
{
if (!InstancePtr->Initialized) {
xdbg_printf(XDBG_DEBUG_ERROR, "Pause: Driver not initialized"
" %d\r\n",InstancePtr->Initialized);
return XST_NOT_SGDMA;
}
if (InstancePtr->HasMm2S) {
XAxiDma_BdRing *TxRingPtr;
TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
/* If channel is halted, then we do not need to do anything
*/
if(!XAxiDma_HasSg(InstancePtr)) {
XAxiDma_WriteReg(TxRingPtr->ChanBase,
XAXIDMA_CR_OFFSET,
XAxiDma_ReadReg(TxRingPtr->ChanBase,
XAXIDMA_CR_OFFSET)
& ~XAXIDMA_CR_RUNSTOP_MASK);
}
TxRingPtr->RunState = AXIDMA_CHANNEL_HALTED;
}
if (InstancePtr->HasS2Mm) {
int RingIndex = 0;
for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels;
RingIndex++) {
XAxiDma_BdRing *RxRingPtr;
RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, RingIndex);
/* If channel is halted, then we do not need to do anything
*/
if(!XAxiDma_HasSg(InstancePtr) && !RingIndex) {
XAxiDma_WriteReg(RxRingPtr->ChanBase,
XAXIDMA_CR_OFFSET,
XAxiDma_ReadReg(RxRingPtr->ChanBase,
XAXIDMA_CR_OFFSET)
& ~XAXIDMA_CR_RUNSTOP_MASK);
}
RxRingPtr->RunState = AXIDMA_CHANNEL_HALTED;
}
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* Resume DMA transactions on both channels.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return
* - XST_SUCCESS for success
* - XST_NOT_SGDMA if the driver instance has not been initialized
* - XST_DMA_ERROR if one of the channels fails to start
*
* @note None
*
*****************************************************************************/
int XAxiDma_Resume(XAxiDma * InstancePtr)
{
int Status;
if (!InstancePtr->Initialized) {
xdbg_printf(XDBG_DEBUG_ERROR, "Resume: Driver not initialized"
" %d\r\n",InstancePtr->Initialized);
return XST_NOT_SGDMA;
}
/* If the DMA engine is not running, start it. Start may fail.
*/
if (!XAxiDma_Started(InstancePtr)) {
Status = XAxiDma_Start(InstancePtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Resume: failed to start"
" engine %d\r\n", Status);
return Status;
}
}
/* Mark the state to be not halted
*/
if (InstancePtr->HasMm2S) {
XAxiDma_BdRing *TxRingPtr;
TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
if(XAxiDma_HasSg(InstancePtr)) {
Status = XAxiDma_BdRingStart(TxRingPtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Resume: failed"
" to start tx ring %d\r\n", Status);
return XST_DMA_ERROR;
}
}
TxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;
}
if (InstancePtr->HasS2Mm) {
int RingIndex = 0;
for (RingIndex = 0 ; RingIndex < InstancePtr->RxNumChannels;
RingIndex++) {
XAxiDma_BdRing *RxRingPtr;
RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, RingIndex);
if(XAxiDma_HasSg(InstancePtr)) {
Status = XAxiDma_BdRingStart(RxRingPtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Resume: failed"
"to start rx ring %d\r\n", Status);
return XST_DMA_ERROR;
}
}
RxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;
}
}
return XST_SUCCESS;
}
/*****************************************************************************/
/*
* Check whether the DMA engine is started.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return
* - 1 if engine is started
* - 0 otherwise.
*
* @note None
*
*****************************************************************************/
static int XAxiDma_Started(XAxiDma * InstancePtr)
{
if (!InstancePtr->Initialized) {
xdbg_printf(XDBG_DEBUG_ERROR, "Started: Driver not initialized"
" %d\r\n",InstancePtr->Initialized);
return 0;
}
if (InstancePtr->HasMm2S) {
XAxiDma_BdRing *TxRingPtr;
TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
if (!XAxiDma_BdRingHwIsStarted(TxRingPtr)) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Started: tx ring not started\r\n");
return 0;
}
}
if (InstancePtr->HasS2Mm) {
XAxiDma_BdRing *RxRingPtr;
RxRingPtr = XAxiDma_GetRxRing(InstancePtr);
if (!XAxiDma_BdRingHwIsStarted(RxRingPtr)) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Started: rx ring not started\r\n");
return 0;
}
}
return 1;
}
/*****************************************************************************/
/**
* This function checks whether specified DMA channel is busy
*
* @param InstancePtr is the driver instance we are working on
*
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
*
* @return - TRUE if channel is busy
* - FALSE if channel is idle
*
* @note None.
*
*****************************************************************************/
u32 XAxiDma_Busy(XAxiDma *InstancePtr, int Direction)
{
return ((XAxiDma_ReadReg(InstancePtr->RegBase +
(XAXIDMA_RX_OFFSET * Direction),
XAXIDMA_SR_OFFSET) &
XAXIDMA_IDLE_MASK) ? FALSE : TRUE);
}
/*****************************************************************************/
/**
* This function Enable or Disable KeyHole Feature
*
* @param InstancePtr is the driver instance we are working on
*
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
* @param Select is the option to enable (TRUE) or disable (FALSE).
*
* @return - XST_SUCCESS for success
*
* @note None.
*
*****************************************************************************/
int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select)
{
u32 Value;
Value = XAxiDma_ReadReg(InstancePtr->RegBase +
(XAXIDMA_RX_OFFSET * Direction),
XAXIDMA_CR_OFFSET);
if (Select)
Value |= XAXIDMA_CR_KEYHOLE_MASK;
else
Value &= ~XAXIDMA_CR_KEYHOLE_MASK;
XAxiDma_WriteReg(InstancePtr->RegBase +
(XAXIDMA_RX_OFFSET * Direction),
XAXIDMA_CR_OFFSET, Value);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function Enable or Disable Cyclic Mode Feature
*
* @param InstancePtr is the driver instance we are working on
*
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
* @param Select is the option to enable (TRUE) or disable (FALSE).
*
* @return - XST_SUCCESS for success
*
* @note None.
*
*****************************************************************************/
int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select)
{
u32 Value;
Value = XAxiDma_ReadReg(InstancePtr->RegBase +
(XAXIDMA_RX_OFFSET * Direction),
XAXIDMA_CR_OFFSET);
if (Select)
Value |= XAXIDMA_CR_CYCLIC_MASK;
else
Value &= ~XAXIDMA_CR_CYCLIC_MASK;
XAxiDma_WriteReg(InstancePtr->RegBase +
(XAXIDMA_RX_OFFSET * Direction),
XAXIDMA_CR_OFFSET, Value);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function does one simple transfer submission
*
* It checks in the following sequence:
* - if engine is busy, cannot submit
* - if engine is in SG mode , cannot submit
*
* @param InstancePtr is the pointer to the driver instance
* @param BuffAddr is the address of the source/destination buffer
* @param Length is the length of the transfer
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
* @return
* - XST_SUCCESS for success of submission
* - XST_FAILURE for submission failure, maybe caused by:
* Another simple transfer is still going
* - XST_INVALID_PARAM if:Length out of valid range [1:8M]
* Or, address not aligned when DRE is not built in
*
* @note This function is used only when system is configured as
* Simple mode.
*
*****************************************************************************/
u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length,
int Direction)
{
u32 WordBits;
int RingIndex = 0;
/* If Scatter Gather is included then, cannot submit
*/
if (XAxiDma_HasSg(InstancePtr)) {
xdbg_printf(XDBG_DEBUG_ERROR, "Simple DMA mode is not"
" supported\r\n");
return XST_FAILURE;
}
if(Direction == XAXIDMA_DMA_TO_DEVICE){
if ((Length < 1) ||
(Length > InstancePtr->TxBdRing.MaxTransferLen)) {
return XST_INVALID_PARAM;
}
if (!InstancePtr->HasMm2S) {
xdbg_printf(XDBG_DEBUG_ERROR, "MM2S channel is not"
"supported\r\n");
return XST_FAILURE;
}
/* If the engine is doing transfer, cannot submit
*/
if(!(XAxiDma_ReadReg(InstancePtr->TxBdRing.ChanBase,
XAXIDMA_SR_OFFSET) & XAXIDMA_HALTED_MASK)) {
if (XAxiDma_Busy(InstancePtr,Direction)) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Engine is busy\r\n");
return XST_FAILURE;
}
}
if (!InstancePtr->MicroDmaMode) {
WordBits = (u32)((InstancePtr->TxBdRing.DataWidth) - 1);
}
else {
WordBits = XAXIDMA_MICROMODE_MIN_BUF_ALIGN;
}
if ((BuffAddr & WordBits)) {
if (!InstancePtr->TxBdRing.HasDRE) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Unaligned transfer without"
" DRE %x\r\n",(unsigned int)BuffAddr);
return XST_INVALID_PARAM;
}
}
XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase,
XAXIDMA_SRCADDR_OFFSET, LOWER_32_BITS(BuffAddr));
if (InstancePtr->AddrWidth > 32)
XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase,
XAXIDMA_SRCADDR_MSB_OFFSET,
UPPER_32_BITS(BuffAddr));
XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase,
XAXIDMA_CR_OFFSET,
XAxiDma_ReadReg(
InstancePtr->TxBdRing.ChanBase,
XAXIDMA_CR_OFFSET)| XAXIDMA_CR_RUNSTOP_MASK);
/* Writing to the BTT register starts the transfer
*/
XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase,
XAXIDMA_BUFFLEN_OFFSET, Length);
}
else if(Direction == XAXIDMA_DEVICE_TO_DMA){
if ((Length < 1) ||
(Length >
InstancePtr->RxBdRing[RingIndex].MaxTransferLen)) {
return XST_INVALID_PARAM;
}
if (!InstancePtr->HasS2Mm) {
xdbg_printf(XDBG_DEBUG_ERROR, "S2MM channel is not"
" supported\r\n");
return XST_FAILURE;
}
if(!(XAxiDma_ReadReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
XAXIDMA_SR_OFFSET) & XAXIDMA_HALTED_MASK)) {
if (XAxiDma_Busy(InstancePtr,Direction)) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Engine is busy\r\n");
return XST_FAILURE;
}
}
if (!InstancePtr->MicroDmaMode) {
WordBits =
(u32)((InstancePtr->RxBdRing[RingIndex].DataWidth) - 1);
}
else {
WordBits = XAXIDMA_MICROMODE_MIN_BUF_ALIGN;
}
if ((BuffAddr & WordBits)) {
if (!InstancePtr->RxBdRing[RingIndex].HasDRE) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Unaligned transfer without"
" DRE %x\r\n", (unsigned int)BuffAddr);
return XST_INVALID_PARAM;
}
}
XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
XAXIDMA_DESTADDR_OFFSET, LOWER_32_BITS(BuffAddr));
if (InstancePtr->AddrWidth > 32)
XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
XAXIDMA_DESTADDR_MSB_OFFSET,
UPPER_32_BITS(BuffAddr));
XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
XAXIDMA_CR_OFFSET,
XAxiDma_ReadReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
XAXIDMA_CR_OFFSET)| XAXIDMA_CR_RUNSTOP_MASK);
/* Writing to the BTT register starts the transfer
*/
XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
XAXIDMA_BUFFLEN_OFFSET, Length);
}
return XST_SUCCESS;
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma.h
+761
View File
@@ -0,0 +1,761 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma.h
* @addtogroup axidma_v9_9
* @{
* @details
*
* This is the driver API for the AXI DMA engine.
*
* For a full description of DMA features, please see the hardware spec. This
* driver supports the following features:
*
* - Scatter-Gather DMA (SGDMA)
* - Simple DMA
* - Interrupts
* - Programmable interrupt coalescing for SGDMA
* - APIs to manage Buffer Descriptors (BD) movement to and from the SGDMA
* engine
*
* <b>Simple DMA</b>
*
* Simple DMA allows the application to define a single transaction between DMA
* and Device. It has two channels: one from the DMA to Device and the other
* from Device to DMA. Application has to set the buffer address and
* length fields to initiate the transfer in respective channel.
*
* <b>Transactions</b>
*
* The object used to describe a transaction is referred to as a Buffer
* Descriptor (BD). Buffer descriptors are allocated in the user application.
* The user application needs to set buffer address, transfer length, and
* control information for this transfer. The control information includes
* SOF and EOF. Definition of those masks are in xaxidma_hw.h
*
* <b>Scatter-Gather DMA</b>
*
* SGDMA allows the application to define a list of transactions in memory which
* the hardware will process without further application intervention. During
* this time, the application is free to continue adding more work to keep the
* Hardware busy.
*
* User can check for the completion of transactions through polling the
* hardware, or interrupts.
*
* SGDMA processes whole packets. A packet is defined as a series of
* data bytes that represent a message. SGDMA allows a packet of data to be
* broken up into one or more transactions. For example, take an Ethernet IP
* packet which consists of a 14 byte header followed by a 1 or more bytes of
* payload. With SGDMA, the application may point a BD to the header and another
* BD to the payload, then transfer them as a single message. This strategy can
* make a TCP/IP stack more efficient by allowing it to keep packet header and
* data in different memory regions instead of assembling packets into
* contiguous blocks of memory.
*
* <b>BD Ring Management</b>
*
* BD rings are shared by the software and the hardware.
*
* The hardware expects BDs to be setup as a linked list. The DMA hardware walks
* through the list by following the next pointer field of a completed BD.
* The hardware stops processing when the just completed BD is the same as the
* BD specified in the Tail Ptr register in the hardware.
*
* The last BD in the ring is linked to the first BD in the ring.
*
* All BD management are done inside the driver. The user application should not
* directly modify the BD fields. Modifications to the BD fields should always
* go through the specific API functions.
*
* Within the ring, the driver maintains four groups of BDs. Each group consists
* of 0 or more adjacent BDs:
*
* - Free: The BDs that can be allocated by the application with
* XAxiDma_BdRingAlloc().
*
* - Pre-process: The BDs that have been allocated with
* XAxiDma_BdRingAlloc(). These BDs are under application control. The
* application modifies these BDs through driver API to prepare them
* for DMA transactions.
*
* - Hardware: The BDs that have been enqueued to hardware with
* XAxiDma_BdRingToHw(). These BDs are under hardware control and may be in a
* state of awaiting hardware processing, in process, or processed by
* hardware. It is considered an error for the application to change BDs
* while they are in this group. Doing so can cause data corruption and lead
* to system instability.
*
* - Post-process: The BDs that have been processed by hardware and have
* been extracted from the Hardware group with XAxiDma_BdRingFromHw().
* These BDs are under application control. The application can check the
* transfer status of these BDs. The application use XAxiDma_BdRingFree()
* to put them into the Free group.
*
* BDs are expected to transition in the following way for continuous
* DMA transfers:
* <pre>
*
* XAxiDma_BdRingAlloc() XAxiDma_BdRingToHw()
* Free ------------------------> Pre-process ----------------------> Hardware
* |
* /|\ |
* | XAxiDma_BdRingFree() XAxiDma_BdRingFromHw() |
* +--------------------------- Post-process <----------------------+
*
* </pre>
*
* When a DMA transfer is to be cancelled before enqueuing to hardware,
* application can return the requested BDs to the Free group using
* XAxiDma_BdRingUnAlloc(), as shown below:
* <pre>
*
* XAxiDma_BdRingUnAlloc()
* Free <----------------------- Pre-process
*
* </pre>
*
* The API provides functions for BD list traversal:
* - XAxiDma_BdRingNext()
* - XAxiDma_BdRingPrev()
*
* These functions should be used with care as they do not understand where
* one group ends and another begins.
*
* <b>SGDMA Descriptor Ring Creation</b>
*
* BD ring is created using XAxiDma_BdRingCreate(). The memory for the BD ring
* is allocated by the application, and it has to be contiguous. Physical
* address is required to setup the BD ring.
*
* The applicaiton can use XAxiDma_BdRingMemCalc() to find out the amount of
* memory needed for a certain number of BDs. XAxiDma_BdRingCntCalc() can be
* used to find out how many BDs can be allocated for certain amount of memory.
*
* A helper function, XAxiDma_BdRingClone(), can speed up the BD ring setup if
* the BDs have same types of controls, for example, SOF and EOF. After
* using the XAxiDma_BdRingClone(), the application only needs to setup the
* buffer address and transfer length. Note that certain BDs in one packet,
* for example, the first BD and the last BD, may need to setup special
* control information.
*
* <b>Descriptor Ring State Machine</b>
*
* There are two states of the BD ring:
*
* - HALTED (H), where hardware is not running
*
* - NOT HALTED (NH), where hardware is running
*
* The following diagram shows the state transition for the DMA engine:
*
* <pre>
* _____ XAxiDma_StartBdRingHw(), or XAxiDma_BdRingStart(), ______
* | | or XAxiDma_Resume() | |
* | H |----------------------------------------------------->| NH |
* | |<-----------------------------------------------------| |
* ----- XAxiDma_Pause() or XAxiDma_Reset() ------
* </pre>
*
* <b>Interrupt Coalescing</b>
*
* SGDMA provides control over the frequency of interrupts through interrupt
* coalescing. The DMA engine provides two ways to tune the interrupt
* coalescing:
*
* - The packet threshold counter. Interrupt will fire once the
* programmable number of packets have been processed by the engine.
*
* - The packet delay timer counter. Interrupt will fire once the
* programmable amount of time has passed after processing the last packet,
* and no new packets to process. Note that the interrupt will only fire if
* at least one packet has been processed.
*
* <b> Interrupt </b>
*
* Interrupts are handled by the user application. Each DMA channel has its own
* interrupt ID. The driver provides APIs to enable/disable interrupt,
* and tune the interrupt frequency regarding to packet processing frequency.
*
* <b> Software Initialization </b>
*
*
* To use the Simple mode DMA engine for transfers, the following setup is
* required:
*
* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
* initializes a driver instance for the given DMA engine and resets the
* engine.
*
* - Enable interrupts if chosen to use interrupt mode. The application is
* responsible for setting up the interrupt system, which includes providing
* and connecting interrupt handlers and call back functions, before
* enabling the interrupts.
*
* - Set the buffer address and length field in respective channels to start
* the DMA transfer
*
* To use the SG mode DMA engine for transfers, the following setup are
* required:
*
* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
* initializes a driver instance for the given DMA engine and resets the
* engine.
*
* - BD Ring creation. A BD ring is needed per DMA channel and can be built by
* calling XAxiDma_BdRingCreate().
*
* - Enable interrupts if chose to use interrupt mode. The application is
* responsible for setting up the interrupt system, which includes providing
* and connecting interrupt handlers and call back functions, before
* enabling the interrupts.
*
* - Start a DMA transfer: Call XAxiDma_BdRingStart() to start a transfer for
* the first time or after a reset, and XAxiDma_BdRingToHw() if the channel
* is already started. Calling XAxiDma_BdRingToHw() when a DMA channel is not
* running will not put the BDs to the hardware, and the BDs will be processed
* later when the DMA channel is started through XAxiDma_BdRingStart().
*
* <b> How to start DMA transactions </b>
*
* The user application uses XAxiDma_BdRingToHw() to submit BDs to the hardware
* to start DMA transfers.
*
* For both channels, if the DMA engine is currently stopped (using
* XAxiDma_Pause()), the newly added BDs will be accepted but not processed
* until the DMA engine is started, using XAxiDma_BdRingStart(), or resumed,
* using XAxiDma_Resume().
*
* <b> Software Post-Processing on completed DMA transactions </b>
*
* If the interrupt system has been set up and the interrupts are enabled,
* a DMA channels notifies the software about the completion of a transfer
* through interrupts. Otherwise, the user application can poll for
* completions of the BDs, using XAxiDma_BdRingFromHw() or
* XAxiDma_BdHwCompleted().
*
* - Once BDs are finished by a channel, the application first needs to fetch
* them from the channel using XAxiDma_BdRingFromHw().
*
* - On the TX side, the application now could free the data buffers attached to
* those BDs as the data in the buffers has been transmitted.
*
* - On the RX side, the application now could use the received data in the
* buffers attached to those BDs.
*
* - For both channels, completed BDs need to be put back to the Free group
* using XAxiDma_BdRingFree(), so they can be used for future transactions.
*
* - On the RX side, it is the application's responsibility to have BDs ready
* to receive data at any time. Otherwise, the RX channel refuses to
* accept any data if it has no RX BDs.
*
* <b> Examples </b>
*
* We provide five examples to show how to use the driver API:
* - One for SG interrupt mode (xaxidma_example_sg_intr.c), multiple BD/packets transfer
* - One for SG polling mode (xaxidma_example_sg_poll.c), single BD transfer.
* - One for SG polling mode (xaxidma_poll_multi_pkts.c), multiple BD/packets transfer
* - One for simple polling mode (xaxidma_example_simple_poll.c)
* - One for simple Interrupt mode (xaxidma_example_simple_intr.c)
*
* <b> Address Translation </b>
*
* All buffer addresses and BD addresses for the hardware are physical
* addresses. The user application is responsible to provide physical buffer
* address for the BD upon BD ring creation. The user application accesses BD
* through its virtual addess. The driver maintains the address translation
* between the physical and virtual address for BDs.
*
* <b> Cache Coherency </b>
*
* This driver expects all application buffers attached to BDs to be in cache
* coherent memory. If cache is used in the system, buffers for transmit MUST
* be flushed from the cache before passing the associated BD to this driver.
* Buffers for receive MUST be invalidated before accessing the data.
*
* <b> Alignment </b>
*
* For BDs:
*
* Minimum alignment is defined by the constant XAXIDMA_BD_MINIMUM_ALIGNMENT.
* This is the smallest alignment allowed by both hardware and software for them
* to properly work.
*
* If the descriptor ring is to be placed in cached memory, alignment also MUST
* be at least the processor's cache-line size. Otherwise, system instability
* occurs. For alignment larger than the cache line size, multiple cache line
* size alignment is required.
*
* Aside from the initial creation of the descriptor ring (see
* XAxiDma_BdRingCreate()), there are no other run-time checks for proper
* alignment of BDs.
*
* For application data buffers:
*
* Application data buffers may reside on any alignment if DRE is built into the
* hardware. Otherwise, application data buffer must be word-aligned. The word
* is defined by XPAR_AXIDMA_0_M_AXIS_MM2S_TDATA_WIDTH for transmit and
* XPAR_AXIDMA_0_S_AXIS_S2MM_TDATA_WIDTH for receive.
*
* For scatter gather transfers that have more than one BDs in the chain of BDs,
* Each BD transfer length must be multiple of word too. Otherwise, internal
* error happens in the hardware.
*
* <b> Error Handling </b>
*
* The DMA engine will halt on all error conditions. It requires the software
* to do a reset before it can start process new transfer requests.
*
* <b> Restart After Stopping </b>
*
* After the DMA engine has been stopped (through reset or reset after an error)
* the software keeps track of the current BD pointer when reset happens, and
* processing of BDs can be resumed through XAxiDma_BdRingStart().
*
* <b> Limitations </b>
*
* This driver does not have any mechanisms for mutual exclusion. It is up to
* the application to provide this protection.
*
* <b> Hardware Defaults & Exclusive Use </b>
*
* After the initialization or reset, the DMA engine is in the following
* default mode:
* - All interrupts are disabled.
*
* - Interrupt coalescing counter is 1.
*
* - The DMA engine is not running (halted). Each DMA channel is started
* separately, using XAxiDma_StartBdRingHw() if no BDs are setup for transfer
* yet, or XAxiDma_BdRingStart() otherwise.
*
* The driver has exclusive use of the registers and BDs. All accesses to the
* registers and BDs should go through the driver interface.
*
* <b> Debug Print </b>
*
* To see the debug print for the driver, please put "-DDEBUG" as the extra
* compiler flags in software platform settings. Also comment out the line in
* xdebug.h: "#undef DEBUG".
*
* <b>Changes From v1.00a</b>
*
* . We have changes return type for XAxiDma_BdSetBufAddr() from void to int
* . We added XAxiDma_LookupConfig() so that user does not need to look for the
* hardware settings anymore.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 4.00a rkv 02/22/11 Added support for simple DMA mode
* New API added for simple DMA mode are
* - XAxiDma_Busy
* - XAxiDma_SimpleTransfer
* New Macros added for simple DMA mode are
* - XAxiDma_HasSg
* - XAxiDma_IntrEnable
* - XAxiDma_IntrGetEnabled
* - XAxiDma_IntrDisable
* - XAxiDma_IntrGetIrq
* - XAxiDma_IntrAckIrq
* 5.00a srt 08/25/11 Added support for memory barrier and modified
* Cache Macros to have a common API for Microblaze
* and Zynq.
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA mode.
* - Changed APIs:
* * XAxiDma_GetRxRing(InstancePtr, RingIndex)
* * XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
* u32 BuffAddr, u32 Length,
* int Direction, int RingIndex)
* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
* u32 LenBytes, u32 LengthMask)
* * XAxiDma_BdGetActualLength(BdPtr, LengthMask)
* * XAxiDma_BdGetLength(BdPtr, LengthMask)
* - New APIs
* * XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
* int Direction, int Select)
* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* 7.00a srt 06/18/12 All the APIs changed in v6_00_a are reverted back for
* backward compatibility.
* - New API:
* XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
* 7.01a srt 10/26/12 - Fixed issue with driver as it fails with IP version
* < 6.00a as the parameter C_NUM_*_CHANNELS is not
* applicable.
* - Changed the logic of MCDMA BD fields Set APIs, to
* clear the field first and then set it.
* 7.02a srt 01/23/13 Replaced *_TDATA_WIDTH parameters to *_DATA_WIDTH
* (CR 691867)
* Updated DDR base address for IPI designs (CR 703656).
* 8.0 adk 19/12/13 Updated as per the New Tcl API's
* srt 01/29/14 Added support for Micro DMA Mode and cyclic mode of
* operations.
* - New APIs:
* * XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr,
* int Direction, int Select)
* * XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32)
* 8.1 adk 20/01/15 Added support for peripheral test. Created the self
* test example to include it on peripheral test's(CR#823144).
* 8.1 adk 29/01/15 Added the sefltest api (XAxiDma_Selftest) to the driver source files
* (xaxidma_selftest.c) and called this from the selftest example
* 9.0 adk 27/07/15 Added support for 64-bit Addressing.
* 9.0 adk 19/08/15 Fixed CR#873125 DMA SG Mode example tests are failing on
* HW in 2015.3.
* 9.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* 9.3 adk 26/07/16 Reduce the size of the buffer descriptor to 64 bytes.
* ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed" strings
* are available in all examples. This is a fix for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Modified Comment lines in functions to recognize
* it as documentation block and added tabspace at return
* statements in functions of axidma examples for proper
* documentation while generating doxygen.
* Modified readme file in examples folder.
* 9.4 adk 25/07/17 Added example for cyclic dma mode CR#974218.
* adk 08/08/17 Fixed CR#980607 Can't select individual AXI DMA code examples.
* Fixed compilation warning in the driver
* 9.5 adk 17/10/17 Fixed CR#987026 mulit packet example fails on A53.
* 26/10/17 Fixed CR#987214 Fix race condition in the XAxiDma_Reset().
* rsp 11/01/17 Fixed CR#988210 Add interface to do config lookup based
* on base address.
* adk 13/11/17 Fixed CR#989455 multi-channel interrupt example fails on A53.
* 9.6 rsp 01/11/18 Fixed CR#976392 In XAxiDma struct use UINTPTR for RegBase.
* In XAxiDma_LookupConfigBaseAddr() use UINTPTR for Baseaddr.
* 9.7 rsp 04/25/18 Add SgLengthWidth member in dma config structure. CR #1000474
* </pre>
*
******************************************************************************/
#ifndef XAXIDMA_H_ /* prevent circular inclusions */
#define XAXIDMA_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xaxidma_bdring.h"
#ifdef __MICROBLAZE__
#include "xenv.h"
#else
#include <string.h>
#include "xil_cache.h"
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* The XAxiDma driver instance data. An instance must be allocated for each DMA
* engine in use.
*/
typedef struct XAxiDma {
UINTPTR RegBase; /* Virtual base address of DMA engine */
int HasMm2S; /* Has transmit channel */
int HasS2Mm; /* Has receive channel */
int Initialized; /* Driver has been initialized */
int HasSg;
XAxiDma_BdRing TxBdRing; /* BD container management for TX channel */
XAxiDma_BdRing RxBdRing[16]; /* BD container management for RX channel */
int TxNumChannels;
int RxNumChannels;
int MicroDmaMode;
int AddrWidth; /**< Address Width */
} XAxiDma;
/**
* The configuration structure for AXI DMA engine
*
* This structure passes the hardware building information to the driver
*/
typedef struct {
u32 DeviceId;
UINTPTR BaseAddr;
int HasStsCntrlStrm;
int HasMm2S;
int HasMm2SDRE;
int Mm2SDataWidth;
int HasS2Mm;
int HasS2MmDRE;
int S2MmDataWidth;
int HasSg;
int Mm2sNumChannels;
int S2MmNumChannels;
int Mm2SBurstSize;
int S2MmBurstSize;
int MicroDmaMode;
int AddrWidth; /**< Address Width */
int SgLengthWidth;
} XAxiDma_Config;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Get Transmit (Tx) Ring ptr
*
* Warning: This has a different API than the LLDMA driver. It now returns
* the pointer to the BD ring.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return Pointer to the Tx Ring
*
* @note C-style signature:
* XAxiDma_BdRing * XAxiDma_GetTxRing(XAxiDma * InstancePtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_GetTxRing(InstancePtr) \
(&((InstancePtr)->TxBdRing))
/*****************************************************************************/
/**
* Get Receive (Rx) Ring ptr
*
* Warning: This has a different API than the LLDMA driver. It now returns
* the pointer to the BD ring.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return Pointer to the Rx Ring
*
* @note
* C-style signature:
* XAxiDma_BdRing * XAxiDma_GetRxRing(XAxiDma * InstancePtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_GetRxRing(InstancePtr) \
(&((InstancePtr)->RxBdRing[0]))
/*****************************************************************************/
/**
* Get Receive (Rx) Ring ptr of a Index
*
* Warning: This has a different API than the LLDMA driver. It now returns
* the pointer to the BD ring.
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
* @param RingIndex is the channel Index.
*
* @return Pointer to the Rx Ring
*
* @note
* C-style signature:
* XAxiDma_BdRing * XAxiDma_GetRxIndexRing(XAxiDma * InstancePtr,
int RingIndex)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_GetRxIndexRing(InstancePtr, RingIndex) \
(&((InstancePtr)->RxBdRing[RingIndex]))
/*****************************************************************************/
/**
* This function checks whether system is configured as Simple or
* Scatter Gather mode
*
* @param InstancePtr is a pointer to the DMA engine instance to be
* worked on.
*
* @return
* - TRUE if configured as SG mode
* - FALSE if configured as simple mode
*
* @note None
*
*****************************************************************************/
#define XAxiDma_HasSg(InstancePtr) ((InstancePtr)->HasSg) ? TRUE : FALSE
/*****************************************************************************/
/**
* This function enables interrupts specified by the Mask in specified
* direction, Interrupts that are not in the mask are not affected.
*
* @param InstancePtr is the driver instance we are working on
* @param Mask is the mask for the interrupts to be enabled
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
* @return None
*
* @note None
*
*****************************************************************************/
#define XAxiDma_IntrEnable(InstancePtr, Mask, Direction) \
XAxiDma_WriteReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
| (Mask & XAXIDMA_IRQ_ALL_MASK))
/*****************************************************************************/
/**
* This function gets the mask for the interrupts that are currently enabled
*
* @param InstancePtr is the driver instance we are working on
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
*
* @return The bit mask for the interrupts that are currently enabled
*
* @note None
*
*****************************************************************************/
#define XAxiDma_IntrGetEnabled(InstancePtr, Direction) \
XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET) &\
XAXIDMA_IRQ_ALL_MASK)
/*****************************************************************************/
/**
* This function disables interrupts specified by the Mask. Interrupts that
* are not in the mask are not affected.
*
* @param InstancePtr is the driver instance we are working on
* @param Mask is the mask for the interrupts to be disabled
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
* @return None
*
* @note None
*
*****************************************************************************/
#define XAxiDma_IntrDisable(InstancePtr, Mask, Direction) \
XAxiDma_WriteReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
& ~(Mask & XAXIDMA_IRQ_ALL_MASK))
/*****************************************************************************/
/**
* This function gets the interrupts that are asserted.
*
* @param InstancePtr is the driver instance we are working on
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
*
* @return The bit mask for the interrupts asserted.
*
* @note None
*
*****************************************************************************/
#define XAxiDma_IntrGetIrq(InstancePtr, Direction) \
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET) &\
XAXIDMA_IRQ_ALL_MASK)
/*****************************************************************************/
/**
* This function acknowledges the interrupts that are specified in Mask
*
* @param InstancePtr is the driver instance we are working on
* @param Mask is the mask for the interrupts to be acknowledge
* @param Direction is DMA transfer direction, valid values are
* - XAXIDMA_DMA_TO_DEVICE.
* - XAXIDMA_DEVICE_TO_DMA.
*
* @return None
*
* @note None.
*
*****************************************************************************/
#define XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction) \
XAxiDma_WriteReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET, \
(Mask) & XAXIDMA_IRQ_ALL_MASK)
/************************** Function Prototypes ******************************/
/*
* Initialization and control functions in xaxidma.c
*/
XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
XAxiDma_Config *XAxiDma_LookupConfigBaseAddr(UINTPTR Baseaddr);
int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
void XAxiDma_Reset(XAxiDma * InstancePtr);
int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
int XAxiDma_Pause(XAxiDma * InstancePtr);
int XAxiDma_Resume(XAxiDma * InstancePtr);
u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length,
int Direction);
int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select);
int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select);
int XAxiDma_Selftest(XAxiDma * InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma_bd.c
+346
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@@ -0,0 +1,346 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma_bd.c
* @addtogroup axidma_v9_9
* @{
*
* Buffer descriptor (BD) management API implementation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA.
* - Changed APIs
* * XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
* u32 LenBytes, u32 LengthMask)
* * XAxiDma_BdGetActualLength(BdPtr, LengthMask)
* * XAxiDma_BdGetLength(BdPtr, LengthMask)
* 8.0 srt 01/29/14 Added support for Micro DMA Mode:
* - New API
* XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32)
* 9.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X
*
* </pre>
*
*****************************************************************************/
#include "xaxidma_bd.h"
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* Set the length field for the given BD.
*
* Length has to be non-zero and less than LengthMask.
*
* For TX channels, the value passed in should be the number of bytes to
* transmit from the TX buffer associated with the given BD.
*
* For RX channels, the value passed in should be the size of the RX buffer
* associated with the given BD in bytes. This is to notify the RX channel
* the capability of the RX buffer to avoid buffer overflow.
*
* The actual receive length can be equal or smaller than the specified length.
* The actual transfer length will be updated by the hardware in the
* XAXIDMA_BD_STS_OFFSET word in the BD.
*
* @param BdPtr is the BD to operate on.
* @param LenBytes is the requested transfer length
* @param LengthMask is the maximum transfer length
*
* @returns
* - XST_SUCCESS for success
* - XST_INVALID_PARAM for invalid BD length
*
* @note This function can be used only when DMA is in SG mode
*
*****************************************************************************/
int XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr, u32 LenBytes, u32 LengthMask)
{
if (LenBytes <= 0 || (LenBytes > LengthMask)) {
xdbg_printf(XDBG_DEBUG_ERROR, "invalid length %d\n",
(int)LenBytes);
return XST_INVALID_PARAM;
}
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET,
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) & \
~LengthMask)) | LenBytes);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* Set the BD's buffer address.
*
* @param BdPtr is the BD to operate on
* @param Addr is the address to set
*
* @return
* - XST_SUCCESS if buffer address set successfully
* - XST_INVALID_PARAM if hardware has no DRE and address is not
* aligned
*
* @note This function can be used only when DMA is in SG mode
*
*****************************************************************************/
u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr)
{
u32 HasDRE;
u8 WordLen;
HasDRE = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_DRE_OFFSET);
WordLen = HasDRE & XAXIDMA_BD_WORDLEN_MASK;
if (Addr & (WordLen - 1)) {
if ((HasDRE & XAXIDMA_BD_HAS_DRE_MASK) == 0) {
xil_printf("Error set buf addr %x with %x and %x,"
" %x\r\n",Addr, HasDRE, (WordLen - 1),
Addr & (WordLen - 1));
return XST_INVALID_PARAM;
}
}
#if defined(__aarch64__) || defined(__arch64__)
XAxiDma_BdWrite64(BdPtr, XAXIDMA_BD_BUFA_OFFSET, Addr);
#else
XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_OFFSET, Addr);
#endif
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* Set the BD's buffer address when configured for Micro Mode. The buffer
* address should be 4K aligned.
*
* @param BdPtr is the BD to operate on
* @param Addr is the address to set
*
* @return
* - XST_SUCCESS if buffer address set successfully
* - XST_INVALID_PARAM if hardware has no DRE and address is not
* aligned
*
* @note This function can be used only when DMA is in SG mode
*
*****************************************************************************/
u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr)
{
if (Addr & XAXIDMA_MICROMODE_MIN_BUF_ALIGN) {
xil_printf("Error set buf addr %x and %x,"
" %x\r\n", Addr, XAXIDMA_MICROMODE_MIN_BUF_ALIGN,
Addr & XAXIDMA_MICROMODE_MIN_BUF_ALIGN);
return XST_INVALID_PARAM;
}
#if defined(__aarch64__) || defined(__arch64__)
XAxiDma_BdWrite64(BdPtr, XAXIDMA_BD_BUFA_OFFSET, Addr);
#else
XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_OFFSET, Addr);
#endif
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* Set the APP word at the specified APP word offset for a BD.
*
* @param BdPtr is the BD to operate on.
* @param Offset is the offset inside the APP word, it is valid from
* 0 to 4
* @param Word is the value to set
*
* @returns
* - XST_SUCCESS for success
* - XST_INVALID_PARAM under following error conditions:
* 1) StsCntrlStrm is not built in hardware
* 2) Offset is not in valid range
*
* @note
* If the hardware build has C_SG_USE_STSAPP_LENGTH set to 1,
* then the last APP word, XAXIDMA_LAST_APPWORD, must have
* non-zero value when AND with 0x7FFFFF. Not doing so will cause
* the hardware to stall.
* This function can be used only when DMA is in SG mode
*
*****************************************************************************/
int XAxiDma_BdSetAppWord(XAxiDma_Bd* BdPtr, int Offset, u32 Word)
{
if (XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET) == 0) {
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetAppWord: no sts cntrl"
"stream in hardware build, cannot set app word\r\n");
return XST_INVALID_PARAM;
}
if ((Offset < 0) || (Offset > XAXIDMA_LAST_APPWORD)) {
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetAppWord: invalid"
"offset %d",Offset);
return XST_INVALID_PARAM;
}
XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_USR0_OFFSET + Offset * 4, Word);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* Get the APP word at the specified APP word offset for a BD.
*
* @param BdPtr is the BD to operate on.
* @param Offset is the offset inside the APP word, it is valid from
* 0 to 4
* @param Valid is to tell the caller whether parameters are valid
*
* @returns
* The APP word. Passed in parameter Valid holds 0 for failure,
* and 1 for success.
*
* @note This function can be used only when DMA is in SG mode
*
*****************************************************************************/
u32 XAxiDma_BdGetAppWord(XAxiDma_Bd* BdPtr, int Offset, int *Valid)
{
*Valid = 0;
if (XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET) == 0) {
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingGetAppWord: no sts cntrl "
"stream in hardware build, no app word available\r\n");
return (u32)0;
}
if((Offset < 0) || (Offset > XAXIDMA_LAST_APPWORD)) {
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingGetAppWord: invalid"
" offset %d", Offset);
return (u32)0;
}
*Valid = 1;
return XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR0_OFFSET + Offset * 4);
}
/*****************************************************************************/
/**
* Set the control bits for a BD.
*
* @param BdPtr is the BD to operate on.
* @param Data is the bit value to set
*
* @return None
*
* @note This function can be used only when DMA is in SG mode
*
*****************************************************************************/
void XAxiDma_BdSetCtrl(XAxiDma_Bd* BdPtr, u32 Data)
{
u32 RegValue = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET);
RegValue &= ~XAXIDMA_BD_CTRL_ALL_MASK;
RegValue |= (Data & XAXIDMA_BD_CTRL_ALL_MASK);
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET, RegValue);
return;
}
/*****************************************************************************/
/**
* Dump the fields of a BD.
*
* @param BdPtr is the BD to operate on.
*
* @return None
*
* @note This function can be used only when DMA is in SG mode
*
*****************************************************************************/
void XAxiDma_DumpBd(XAxiDma_Bd* BdPtr)
{
xil_printf("Dump BD %x:\r\n", (UINTPTR)BdPtr);
xil_printf("\tNext Bd Ptr: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_NDESC_OFFSET));
xil_printf("\tBuff addr: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_BUFA_OFFSET));
xil_printf("\tMCDMA Fields: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_MCCTL_OFFSET));
xil_printf("\tVSIZE_STRIDE: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr,
XAXIDMA_BD_STRIDE_VSIZE_OFFSET));
xil_printf("\tContrl len: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET));
xil_printf("\tStatus: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_STS_OFFSET));
xil_printf("\tAPP 0: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR0_OFFSET));
xil_printf("\tAPP 1: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR1_OFFSET));
xil_printf("\tAPP 2: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR2_OFFSET));
xil_printf("\tAPP 3: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR3_OFFSET));
xil_printf("\tAPP 4: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR4_OFFSET));
xil_printf("\tSW ID: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_ID_OFFSET));
xil_printf("\tStsCtrl: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr,
XAXIDMA_BD_HAS_STSCNTRL_OFFSET));
xil_printf("\tDRE: %x\r\n",
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_DRE_OFFSET));
xil_printf("\r\n");
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma_bd.h
+696
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@@ -0,0 +1,696 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma_bd.h
* @addtogroup axidma_v9_9
* @{
*
* Buffer descriptor (BD) management API.
*
* <b> Buffer Descriptors </b>
*
* A BD defines a DMA transaction (see "Transaction" section in xaxidma.h).
* All accesses to a BD go through this set of API.
*
* The XAxiDma_Bd structure defines a BD. The first XAXIDMA_BD_HW_NUM_BYTES
* are shared between hardware and software.
*
* <b> Actual Transfer Length </b>
*
* The actual transfer length for receive could be smaller than the requested
* transfer length. The hardware sets the actual transfer length in the
* completed BD. The API to retrieve the actual transfer length is
* XAxiDma_GetActualLength().
*
* <b> User IP words </b>
*
* There are 5 user IP words in each BD.
*
* If hardware does not have the StsCntrl stream built in, then these words
* are not usable. Retrieving these words get a NULL pointer and setting
* these words results an error.
*
* <b> Performance </b>
*
* BDs are typically in a non-cached memory space. Reducing the number of
* I/O operations to BDs can improve overall performance of the DMA channel.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 5.00a srt 08/25/11 Changed Cache Macros to have a common API for Zynq
* and Microblaze.
* 6.00a srt 01/24/12 Added APIs to support Multi-Channel DMA:
* XAxiDma_BdSetTId()
* XAxiDma_BdGetTId()
* XAxiDma_BdSetTDest()
* XAxiDma_BdGetTDest()
* XAxiDma_BdSetTUser()
* XAxiDma_BdGetTUser()
* XAxiDma_BdSetARCache()
* XAxiDma_BdGetARCache()
* XAxiDma_BdSetARUser()
* XAxiDma_BdGetARUser()
* XAxiDma_BdSetStride()
* XAxiDma_BdGetStride()
* XAxiDma_BdSetVSize()
* XAxiDma_BdGetVSize()
* - Changed APIs
* XAxiDma_BdGetActualLength(BdPtr, LengthMask)
* XAxiDma_BdGetLength(BdPtr, LengthMask)
* XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr,
* u32 LenBytes, u32 LengthMask)
* 7.01a srt 10/26/12 Changed the logic of MCDMA BD fields Set APIs, to
* clear the field first and set it.
* 8.0 srt 01/29/14 Added support for Micro DMA Mode.
* 9.2 vak 15/04/16 Fixed compilation warnings in axidma driver
* 9.8 rsp 07/11/18 Fix cppcheck portability warnings. CR #1006164
*
* </pre>
*****************************************************************************/
#ifndef XAXIDMA_BD_H_ /* To prevent circular inclusions */
#define XAXIDMA_BD_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xaxidma_hw.h"
#include "xstatus.h"
#include "xdebug.h"
#include "xil_cache.h"
#ifdef __MICROBLAZE__
#include "xenv.h"
#else
#include <string.h>
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* The XAxiDma_Bd is the type for a buffer descriptor (BD).
*/
typedef u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS];
/***************** Macros (Inline Functions) Definitions *********************/
/******************************************************************************
* Define methods to flush and invalidate cache for BDs should they be
* located in cached memory.
*****************************************************************************/
#ifdef __aarch64__
#define XAXIDMA_CACHE_FLUSH(BdPtr)
#define XAXIDMA_CACHE_INVALIDATE(BdPtr)
#else
#define XAXIDMA_CACHE_FLUSH(BdPtr) \
Xil_DCacheFlushRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES)
#define XAXIDMA_CACHE_INVALIDATE(BdPtr) \
Xil_DCacheInvalidateRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES)
#endif
/*****************************************************************************/
/**
*
* Read the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to read
* @param Offset is the word offset to be read
*
* @return The 32-bit value of the field
*
* @note
* C-style signature:
* u32 XAxiDma_BdRead(u32 BaseAddress, u32 Offset)
*
******************************************************************************/
#define XAxiDma_BdRead(BaseAddress, Offset) \
(*(u32 *)((UINTPTR)(BaseAddress) + (u32)(Offset)))
/*****************************************************************************/
/**
*
* Write the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to write
* @param Offset is the word offset to be written
* @param Data is the 32-bit value to write to the field
*
* @return None.
*
* @note
* C-style signature:
* void XAxiDma_BdWrite(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XAxiDma_BdWrite(BaseAddress, Offset, Data) \
(*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data)
/*****************************************************************************/
/**
*
* Write the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to write
* @param Offset is the word offset to be written
* @param Data is the 64-bit value to write to the field
*
* @return None.
*
* @note
* C-style signature:
* void XAxiDma_BdWrite(u64 BaseAddress, u32 RegOffset, u64 Data)
*
******************************************************************************/
#define XAxiDma_BdWrite64(BaseAddress, Offset, Data) \
(*(u64 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u64)(Data)
/*****************************************************************************/
/**
* Zero out BD specific fields. BD fields that are for the BD ring or for the
* system hardware build information are not touched.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdClear(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdClear(BdPtr) \
memset((void *)(((UINTPTR)(BdPtr)) + XAXIDMA_BD_START_CLEAR), 0, \
XAXIDMA_BD_BYTES_TO_CLEAR)
/*****************************************************************************/
/**
* Get the control bits for the BD
*
* @param BdPtr is the BD to operate on
*
* @return The bit mask for the control of the BD
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetCtrl(BdPtr) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) \
& XAXIDMA_BD_CTRL_ALL_MASK)
/*****************************************************************************/
/**
* Retrieve the status of a BD
*
* @param BdPtr is the BD to operate on
*
* @return Word at offset XAXIDMA_BD_DMASR_OFFSET. Use XAXIDMA_BD_STS_***
* values defined in xaxidma_hw.h to interpret the returned value
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetSts(BdPtr) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
XAXIDMA_BD_STS_ALL_MASK)
/*****************************************************************************/
/**
* Retrieve the length field value from the given BD. The returned value is
* the same as what was written with XAxiDma_BdSetLength(). Note that in the
* this value does not reflect the real length of received data.
* See the comments of XAxiDma_BdSetLength() for more details. To obtain the
* actual transfer length, use XAxiDma_BdGetActualLength().
*
* @param BdPtr is the BD to operate on.
* @param LengthMask is the Maximum Transfer Length.
*
* @return The length value set in the BD.
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetLength(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetLength(BdPtr, LengthMask) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) & \
LengthMask)
/*****************************************************************************/
/**
* Set the ID field of the given BD. The ID is an arbitrary piece of data the
* application can associate with a specific BD.
*
* @param BdPtr is the BD to operate on
* @param Id is a 32 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetId(XAxiDma_Bd* BdPtr, void Id)
*
*****************************************************************************/
#define XAxiDma_BdSetId(BdPtr, Id) \
(XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_ID_OFFSET, (UINTPTR)(Id)))
/*****************************************************************************/
/**
* Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetId(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetId(BdPtr) (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_ID_OFFSET))
/*****************************************************************************/
/**
* Get the BD's buffer address
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetBufAddr(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetBufAddr(BdPtr) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_BUFA_OFFSET))
/*****************************************************************************/
/**
* Check whether a BD has completed in hardware. This BD has been submitted
* to hardware. The application can use this function to poll for the
* completion of the BD.
*
* This function may not work if the BD is in cached memory.
*
* @param BdPtr is the BD to check on
*
* @return
* - 0 if not complete
* - XAXIDMA_BD_STS_COMPLETE_MASK if completed, may contain
* XAXIDMA_BD_STS_*_ERR_MASK bits.
*
* @note
* C-style signature:
* int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdHwCompleted(BdPtr) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
XAXIDMA_BD_STS_COMPLETE_MASK)
/*****************************************************************************/
/**
* Get the actual transfer length of a BD. The BD has completed in hw.
*
* This function may not work if the BD is in cached memory.
*
* @param BdPtr is the BD to check on
* @param LengthMask is the Maximum Transfer Length.
*
* @return None
*
* @note
* C-style signature:
* int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetActualLength(BdPtr, LengthMask) \
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
LengthMask)
/*****************************************************************************/
/**
* Set the TID field of the TX BD.
* Provides a stream identifier and can be used to differentiate between
* multiple streams of data that are being transferred across the same
* interface.
*
* @param BdPtr is the BD to operate on
* @param TId is a 8 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetTId(XAxiDma_Bd* BdPtr, void TId)
*
*****************************************************************************/
#define XAxiDma_BdSetTId(BdPtr, TId) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_TID_FIELD_MASK); \
val |= ((u32)(TId) << XAXIDMA_BD_TID_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetTId(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetTId(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \
XAXIDMA_BD_TID_FIELD_MASK)
/*****************************************************************************/
/**
* Set the TDEST field of the TX BD.
* Provides coarse routing information for the data stream.
*
* @param BdPtr is the BD to operate on
* @param TDest is a 8 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetTDest(XAxiDma_Bd* BdPtr, void TDest)
*
*****************************************************************************/
#define XAxiDma_BdSetTDest(BdPtr, TDest) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_TDEST_FIELD_MASK); \
val |= ((u32)(TDest) << XAXIDMA_BD_TDEST_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the TDest field of the RX BD previously set with i
* XAxiDma_BdSetTDest.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetTDest(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetTDest(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \
XAXIDMA_BD_TDEST_FIELD_MASK)
/*****************************************************************************/
/**
* Set the TUSER field of the TX BD.
* User defined sideband signaling.
*
* @param BdPtr is the BD to operate on
* @param TUser is a 8 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetTUser(XAxiDma_Bd* BdPtr, void TUser)
*
*****************************************************************************/
#define XAxiDma_BdSetTUser(BdPtr, TUser) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_TUSER_FIELD_MASK); \
val |= ((u32)(TUser) << XAXIDMA_BD_TUSER_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the TUSER field of the RX BD previously set with
* XAxiDma_BdSetTUser.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetTUser(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetTUser(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \
XAXIDMA_BD_TUSER_FIELD_MASK)
/*****************************************************************************/
/**
* Set the ARCACHE field of the given BD.
* This signal provides additional information about the cacheable
* characteristics of the transfer.
*
* @param BdPtr is the BD to operate on
* @param ARCache is a 8 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetARCache(XAxiDma_Bd* BdPtr, void ARCache)
*
*****************************************************************************/
#define XAxiDma_BdSetARCache(BdPtr, ARCache) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_ARCACHE_FIELD_MASK); \
val |= ((u32)(ARCache) << XAXIDMA_BD_ARCACHE_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the ARCACHE field of the given BD previously set with
* XAxiDma_BdSetARCache.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetARCache(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetARCache(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) & \
XAXIDMA_BD_ARCACHE_FIELD_MASK)
/*****************************************************************************/
/**
* Set the ARUSER field of the given BD.
* Sideband signals used for user defined information.
*
* @param BdPtr is the BD to operate on
* @param ARUser is a 8 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetARUser(XAxiDma_Bd* BdPtr, void ARUser)
*
*****************************************************************************/
#define XAxiDma_BdSetARUser(BdPtr, ARUser) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_ARUSER_FIELD_MASK); \
val |= ((u32)(ARUser) << XAXIDMA_BD_ARUSER_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the ARUSER field of the given BD previously set with
* XAxiDma_BdSetARUser.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetARUser(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetARUser(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) & \
XAXIDMA_BD_ARUSER_FIELD_MASK)
/*****************************************************************************/
/**
* Set the STRIDE field of the given BD.
* It is the address distance between the first address of successive
* horizontal reads.
*
* @param BdPtr is the BD to operate on
* @param Stride is a 32 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetStride(XAxiDma_Bd* BdPtr, void Stride)
*
*****************************************************************************/
#define XAxiDma_BdSetStride(BdPtr, Stride) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
~XAXIDMA_BD_STRIDE_FIELD_MASK); \
val |= ((u32)(Stride) << XAXIDMA_BD_STRIDE_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the STRIDE field of the given BD previously set with
* XAxiDma_BdSetStride.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetStride(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetStride(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) & \
XAXIDMA_BD_STRIDE_FIELD_MASK)
/*****************************************************************************/
/**
* Set the VSIZE field of the given BD.
* Number of horizontal lines for strided access.
*
* @param BdPtr is the BD to operate on
* @param VSize is a 32 bit quantity to set in the BD
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdSetVSize(XAxiDma_Bd* BdPtr, void VSize)
*
*****************************************************************************/
#define XAxiDma_BdSetVSize(BdPtr, VSize) \
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
~XAXIDMA_BD_VSIZE_FIELD_MASK); \
val |= ((u32)(VSize) << XAXIDMA_BD_VSIZE_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
}
/*****************************************************************************/
/**
* Retrieve the STRIDE field of the given BD previously set with
* XAxiDma_BdSetVSize.
*
* @param BdPtr is the BD to operate on
*
* @return None
*
* @note
* C-style signature:
* u32 XAxiDma_BdGetVSize(XAxiDma_Bd* BdPtr)
*
*****************************************************************************/
#define XAxiDma_BdGetVSize(BdPtr) \
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) & \
XAXIDMA_BD_VSIZE_FIELD_MASK)
/*****************************************************************************/
/************************** Function Prototypes ******************************/
int XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr, u32 LenBytes, u32 LengthMask);
u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr);
u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr);
int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word);
u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid);
void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
/* Debug utility
*/
void XAxiDma_DumpBd(XAxiDma_Bd* BdPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma_bdring.c
+1615
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datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma_bdring.h
+542
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@@ -0,0 +1,542 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma_bdring.h
* @addtogroup axidma_v9_9
* @{
*
* This file contains DMA channel related structure and constant definition
* as well as function prototypes. Each DMA channel is managed by a Buffer
* Descriptor ring, and XAxiDma_BdRing is chosen as the symbol prefix used in
* this file. See xaxidma.h for more information on how a BD ring is managed.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA.
* - New API
* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* - Changed APIs
* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* 7.00a srt 06/18/12 All the APIs changed in v6_00_a are reverted back for
* backward compatibility.
* 9.2 vak 15/04/16 Fixed the compilation warnings in axidma driver
* 9.7 rsp 01/11/18 Use UINTPTR instead of u32 for ChanBase CR#976392
*
* </pre>
*
******************************************************************************/
#ifndef XAXIDMA_BDRING_H_ /* prevent circular inclusions */
#define XAXIDMA_BDRING_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xaxidma_bd.h"
#include <stdlib.h>
/************************** Constant Definitions *****************************/
/* State of a DMA channel
*/
#define AXIDMA_CHANNEL_NOT_HALTED 1
#define AXIDMA_CHANNEL_HALTED 2
/* Argument constant to simplify argument setting
*/
#define XAXIDMA_NO_CHANGE 0xFFFFFFFF
#define XAXIDMA_ALL_BDS 0x0FFFFFFF /* 268 Million */
/**************************** Type Definitions *******************************/
/** Container structure for descriptor storage control. If address translation
* is enabled, then all addresses and pointers excluding FirstBdPhysAddr are
* expressed in terms of the virtual address.
*/
typedef struct {
UINTPTR ChanBase; /**< physical base address*/
int IsRxChannel; /**< Is this a receive channel */
volatile int RunState; /**< Whether channel is running */
int HasStsCntrlStrm; /**< Whether has stscntrl stream */
int HasDRE;
int DataWidth;
int Addr_ext;
u32 MaxTransferLen;
UINTPTR FirstBdPhysAddr; /**< Physical address of 1st BD in list */
UINTPTR FirstBdAddr; /**< Virtual address of 1st BD in list */
UINTPTR LastBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
UINTPTR Separation; /**< Number of bytes between the starting
address of adjacent BDs */
XAxiDma_Bd *FreeHead; /**< First BD in the free group */
XAxiDma_Bd *PreHead; /**< First BD in the pre-work group */
XAxiDma_Bd *HwHead; /**< First BD in the work group */
XAxiDma_Bd *HwTail; /**< Last BD in the work group */
XAxiDma_Bd *PostHead; /**< First BD in the post-work group */
XAxiDma_Bd *BdaRestart; /**< BD to load when channel is started */
XAxiDma_Bd *CyclicBd; /**< Useful for Cyclic DMA operations */
int FreeCnt; /**< Number of allocatable BDs in free group */
int PreCnt; /**< Number of BDs in pre-work group */
int HwCnt; /**< Number of BDs in work group */
int PostCnt; /**< Number of BDs in post-work group */
int AllCnt; /**< Total Number of BDs for channel */
int RingIndex; /**< Ring Index */
int Cyclic; /**< Check for cyclic DMA Mode */
} XAxiDma_BdRing;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many BDs will fit
* within the given memory constraints.
*
* The results of this macro can be provided to XAxiDma_BdRingCreate().
*
* @param Alignment specifies what byte alignment the BDs must fall
* on and must be a power of 2 to get an accurate calculation
* (32, 64, 126,...)
* @param Bytes is the number of bytes to be used to store BDs.
*
* @return Number of BDs that can fit in the given memory area
*
* @note
* C-style signature:
* int XAxiDma_BdRingCntCalc(u32 Alignment, u32 Bytes)
* This function is used only when system is configured as SG mode
*
******************************************************************************/
#define XAxiDma_BdRingCntCalc(Alignment, Bytes) \
(uint32_t)((Bytes)/((sizeof(XAxiDma_Bd)+((Alignment)-1))&~((Alignment)-1)))
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many bytes of memory
* are required to contain a given number of BDs at a given alignment.
*
* @param Alignment specifies what byte alignment the BDs must fall on.
* This parameter must be a power of 2 to get an accurate
* calculation (32, 64,128,...)
* @param NumBd is the number of BDs to calculate memory size
* requirements
*
* @return The number of bytes of memory required to create a BD list
* with the given memory constraints.
*
* @note
* C-style signature:
* int XAxiDma_BdRingMemCalc(u32 Alignment, u32 NumBd)
* This function is used only when system is configured as SG mode
*
******************************************************************************/
#define XAxiDma_BdRingMemCalc(Alignment, NumBd) \
(int)((sizeof(XAxiDma_Bd)+((Alignment)-1)) & ~((Alignment)-1))*(NumBd)
/****************************************************************************/
/**
* Return the total number of BDs allocated by this channel with
* XAxiDma_BdRingCreate().
*
* @param RingPtr is the BD ring to operate on.
*
* @return The total number of BDs allocated for this channel.
*
* @note
* C-style signature:
* int XAxiDma_BdRingGetCnt(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
/****************************************************************************/
/**
* Return the number of BDs allocatable with XAxiDma_BdRingAlloc() for pre-
* processing.
*
* @param RingPtr is the BD ring to operate on.
*
* @return The number of BDs currently allocatable.
*
* @note
* C-style signature:
* int XAxiDma_BdRingGetFreeCnt(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
/****************************************************************************/
/**
* Snap shot the latest BD a BD ring is processing.
*
* @param RingPtr is the BD ring to operate on.
*
* @return None
*
* @note
* C-style signature:
* void XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingSnapShotCurrBd(RingPtr) \
{ \
if (!RingPtr->IsRxChannel) { \
(RingPtr)->BdaRestart = \
(XAxiDma_Bd *)(UINTPTR)XAxiDma_ReadReg( \
(RingPtr)->ChanBase, \
XAXIDMA_CDESC_OFFSET); \
} else { \
if (!RingPtr->RingIndex) { \
(RingPtr)->BdaRestart = \
(XAxiDma_Bd *)(UINTPTR)XAxiDma_ReadReg( \
(RingPtr)->ChanBase, \
XAXIDMA_CDESC_OFFSET); \
} else { \
(RingPtr)->BdaRestart = \
(XAxiDma_Bd *)(UINTPTR)XAxiDma_ReadReg( \
(RingPtr)->ChanBase, \
(XAXIDMA_RX_CDESC0_OFFSET + \
(RingPtr->RingIndex - 1) * \
XAXIDMA_RX_NDESC_OFFSET)); \
} \
} \
}
/****************************************************************************/
/**
* Get the BD a BD ring is processing.
*
* @param RingPtr is the BD ring to operate on.
*
* @return The current BD that the BD ring is working on
*
* @note
* C-style signature:
* XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetCurrBd(RingPtr) \
(XAxiDma_Bd *)XAxiDma_ReadReg((RingPtr)->ChanBase, \
XAXIDMA_CDESC_OFFSET) \
/****************************************************************************/
/**
* Return the next BD in the ring.
*
* @param RingPtr is the BD ring to operate on.
* @param BdPtr is the current BD.
*
* @return The next BD in the ring relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XAxiDma_Bd *XAxiDma_BdRingNext(XAxiDma_BdRing* RingPtr,
* XAxiDma_Bd *BdPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingNext(RingPtr, BdPtr) \
(((UINTPTR)(BdPtr) >= (RingPtr)->LastBdAddr) ? \
(UINTPTR)(RingPtr)->FirstBdAddr : \
(UINTPTR)((UINTPTR)(BdPtr) + (RingPtr)->Separation))
/****************************************************************************/
/**
* Return the previous BD in the ring.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the current BD.
*
* @return The previous BD in the ring relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XAxiDma_Bd *XAxiDma_BdRingPrev(XAxiDma_BdRing* RingPtr,
* XAxiDma_Bd *BdPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingPrev(RingPtr, BdPtr) \
(((u32)(BdPtr) <= (RingPtr)->FirstBdAddr) ? \
(XAxiDma_Bd*)(RingPtr)->LastBdAddr : \
(XAxiDma_Bd*)((u32)(BdPtr) - (RingPtr)->Separation))
/****************************************************************************/
/**
* Retrieve the contents of the channel status register
*
* @param RingPtr is the channel instance to operate on.
*
* @return Current contents of status register
*
* @note
* C-style signature:
* u32 XAxiDma_BdRingGetSr(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetSr(RingPtr) \
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET)
/****************************************************************************/
/**
* Get error bits of a DMA channel
*
* @param RingPtr is the channel instance to operate on.
*
* @return Rrror bits in the status register, they should be interpreted
* with XAXIDMA_ERR_*_MASK defined in xaxidma_hw.h
*
* @note
* C-style signature:
* u32 XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetError(RingPtr) \
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_ERR_ALL_MASK)
/****************************************************************************/
/**
* Check whether a DMA channel is started, meaning the channel is not halted.
*
* @param RingPtr is the channel instance to operate on.
*
* @return
* - 1 if channel is started
* - 0 otherwise
*
* @note
* C-style signature:
* int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr)
*
*****************************************************************************/
#define XAxiDma_BdRingHwIsStarted(RingPtr) \
((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_HALTED_MASK) ? FALSE : TRUE)
/****************************************************************************/
/**
* Check if the current DMA channel is busy with a DMA operation.
*
* @param RingPtr is the channel instance to operate on.
*
* @return
* - 1 if the DMA is busy.
* - 0 otherwise
*
* @note
* C-style signature:
* int XAxiDma_BdRingBusy(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingBusy(RingPtr) \
(XAxiDma_BdRingHwIsStarted(RingPtr) && \
((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_IDLE_MASK) ? FALSE : TRUE))
/****************************************************************************/
/**
* Set interrupt enable bits for a channel. This operation will modify the
* XAXIDMA_CR_OFFSET register.
*
* @param RingPtr is the channel instance to operate on.
* @param Mask consists of the interrupt signals to enable.Bits not
* specified in the mask are not affected.
*
* @note
* C-style signature:
* void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingIntEnable(RingPtr, Mask) \
(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
| ((Mask) & XAXIDMA_IRQ_ALL_MASK)))
/****************************************************************************/
/**
* Get enabled interrupts of a channel. It is in XAXIDMA_CR_OFFSET register.
*
* @param RingPtr is the channel instance to operate on.
* @return Enabled interrupts of a channel. Use XAXIDMA_IRQ_* defined in
* xaxidma_hw.h to interpret this returned value.
*
* @note
* C-style signature:
* u32 XAxiDma_BdRingIntGetEnabled(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingIntGetEnabled(RingPtr) \
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
& XAXIDMA_IRQ_ALL_MASK)
/****************************************************************************/
/**
* Clear interrupt enable bits for a channel. It modifies the
* XAXIDMA_CR_OFFSET register.
*
* @param RingPtr is the channel instance to operate on.
* @param Mask consists of the interrupt signals to disable.Bits not
* specified in the Mask are not affected.
*
* @note
* C-style signature:
* void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr,
* u32 Mask)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingIntDisable(RingPtr, Mask) \
(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) & \
~((Mask) & XAXIDMA_IRQ_ALL_MASK)))
/****************************************************************************/
/**
* Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET. This
* operation can be used to see which interrupts are pending.
*
* @param RingPtr is the channel instance to operate on.
*
* @return Current contents of the IRQ_OFFSET register. Use
* XAXIDMA_IRQ_*** values defined in xaxidma_hw.h to interpret
* the returned value.
*
* @note
* C-style signature:
* u32 XAxiDma_BdRingGetIrq(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingGetIrq(RingPtr) \
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_IRQ_ALL_MASK)
/****************************************************************************/
/**
* Acknowledge asserted interrupts. It modifies XAXIDMA_SR_OFFSET register.
* A mask bit set for an unasserted interrupt has no effect.
*
* @param RingPtr is the channel instance to operate on.
* @param Mask are the interrupt signals to acknowledge
*
* @note
* C-style signature:
* void XAxiDma_BdRingAckIrq(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingAckIrq(RingPtr, Mask) \
XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET,\
(Mask) & XAXIDMA_IRQ_ALL_MASK)
/****************************************************************************/
/**
* Enable Cyclic DMA Mode.
*
* @param RingPtr is the channel instance to operate on.
*
* @note
* C-style signature:
* void XAxiDma_BdRingEnableCyclicDMA(XAxiDma_BdRing* RingPtr)
* This function is used only when system is configured as SG mode
*
*****************************************************************************/
#define XAxiDma_BdRingEnableCyclicDMA(RingPtr) \
(RingPtr->Cyclic = 1)
/****************************************************************************/
/************************* Function Prototypes ******************************/
/*
* Descriptor ring functions xaxidma_bdring.c
*/
int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr);
int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr);
u32 XAxiDma_BdRingCreate(XAxiDma_BdRing * RingPtr, UINTPTR PhysAddr,
UINTPTR VirtAddr, u32 Alignment, int BdCount);
int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr);
int XAxiDma_BdRingAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
XAxiDma_Bd ** BdSetPtr);
int XAxiDma_BdRingUnAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
XAxiDma_Bd * BdSetPtr);
int XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, int NumBd,
XAxiDma_Bd * BdSetPtr);
int XAxiDma_BdRingFromHw(XAxiDma_BdRing * RingPtr, int BdLimit,
XAxiDma_Bd ** BdSetPtr);
int XAxiDma_BdRingFree(XAxiDma_BdRing * RingPtr, int NumBd,
XAxiDma_Bd * BdSetPtr);
int XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr);
int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter, u32 Timer);
void XAxiDma_BdRingGetCoalesce(XAxiDma_BdRing * RingPtr,
u32 *CounterPtr, u32 *TimerPtr);
/* The following functions are for debug only
*/
int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr);
void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma_g.c
+66
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@@ -0,0 +1,66 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1.3
* DO NOT EDIT.
*
* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xaxidma.h"
/*
* The configuration table for devices
*/
XAxiDma_Config XAxiDma_ConfigTable[XPAR_XAXIDMA_NUM_INSTANCES] =
{
{
XPAR_AXI_DMA_C2C_DEVICE_ID,
XPAR_AXI_DMA_C2C_BASEADDR,
XPAR_AXI_DMA_C2C_SG_INCLUDE_STSCNTRL_STRM,
XPAR_AXI_DMA_C2C_INCLUDE_MM2S,
XPAR_AXI_DMA_C2C_INCLUDE_MM2S_DRE,
XPAR_AXI_DMA_C2C_M_AXI_MM2S_DATA_WIDTH,
XPAR_AXI_DMA_C2C_INCLUDE_S2MM,
XPAR_AXI_DMA_C2C_INCLUDE_S2MM_DRE,
XPAR_AXI_DMA_C2C_M_AXI_S2MM_DATA_WIDTH,
XPAR_AXI_DMA_C2C_INCLUDE_SG,
XPAR_AXI_DMA_C2C_NUM_MM2S_CHANNELS,
XPAR_AXI_DMA_C2C_NUM_S2MM_CHANNELS,
XPAR_AXI_DMA_C2C_MM2S_BURST_SIZE,
XPAR_AXI_DMA_C2C_S2MM_BURST_SIZE,
XPAR_AXI_DMA_C2C_MICRO_DMA,
XPAR_AXI_DMA_C2C_ADDR_WIDTH,
XPAR_AXI_DMA_C2C_SG_LENGTH_WIDTH
}
};
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma_hw.h
+342
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@@ -0,0 +1,342 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xaxidma_hw.h
* @addtogroup axidma_v9_9
* @{
*
* Hardware definition file. It defines the register interface and Buffer
* Descriptor (BD) definitions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 4.00a rkv 02/22/11 Added support for simple DMA mode
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA mode
* 8.0 srt 01/29/14 Added support for Micro DMA Mode and Cyclic mode of
* operations.
* 9.7 rsp 04/24/18 Added support for 64MB data transfer.Instead of #define
* read max buffer width from IP config.
*
* </pre>
*
*****************************************************************************/
#ifndef XAXIDMA_HW_H_ /* prevent circular inclusions */
#define XAXIDMA_HW_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name DMA Transfer Direction
* @{
*/
#define XAXIDMA_DMA_TO_DEVICE 0x00
#define XAXIDMA_DEVICE_TO_DMA 0x01
/** @name Buffer Descriptor Alignment
* @{
*/
#define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40 /**< Minimum byte alignment
requirement for descriptors to
satisfy both hardware/software
needs */
/*@}*/
/** @name Micro DMA Buffer Address Alignment
* @{
*/
#define XAXIDMA_MICROMODE_MIN_BUF_ALIGN 0xFFF /**< Minimum byte alignment
requirement for buffer address
in Micro DMA mode */
/*@}*/
/** @name Maximum transfer length
* This is determined by hardware
* @{
*/
#define XAXIDMA_MCHAN_MAX_TRANSFER_LEN 0x00FFFF /* Max length MCDMA
hw supports */
/*@}*/
/* Register offset definitions. Register accesses are 32-bit.
*/
/** @name Device registers
* Register sets on TX and RX channels are identical
* @{
*/
#define XAXIDMA_TX_OFFSET 0x00000000 /**< TX channel registers base
* offset */
#define XAXIDMA_RX_OFFSET 0x00000030 /**< RX channel registers base
* offset */
/* This set of registers are applicable for both channels. Add
* XAXIDMA_TX_OFFSET to get to TX channel, and XAXIDMA_RX_OFFSET to get to RX
* channel
*/
#define XAXIDMA_CR_OFFSET 0x00000000 /**< Channel control */
#define XAXIDMA_SR_OFFSET 0x00000004 /**< Status */
#define XAXIDMA_CDESC_OFFSET 0x00000008 /**< Current descriptor pointer */
#define XAXIDMA_CDESC_MSB_OFFSET 0x0000000C /**< Current descriptor pointer */
#define XAXIDMA_TDESC_OFFSET 0x00000010 /**< Tail descriptor pointer */
#define XAXIDMA_TDESC_MSB_OFFSET 0x00000014 /**< Tail descriptor pointer */
#define XAXIDMA_SRCADDR_OFFSET 0x00000018 /**< Simple mode source address
pointer */
#define XAXIDMA_SRCADDR_MSB_OFFSET 0x0000001C /**< Simple mode source address
pointer */
#define XAXIDMA_DESTADDR_OFFSET 0x00000018 /**< Simple mode destination address pointer */
#define XAXIDMA_DESTADDR_MSB_OFFSET 0x0000001C /**< Simple mode destination address pointer */
#define XAXIDMA_BUFFLEN_OFFSET 0x00000028 /**< Tail descriptor pointer */
#define XAXIDMA_SGCTL_OFFSET 0x0000002c /**< SG Control Register */
/** Multi-Channel DMA Descriptor Offsets **/
#define XAXIDMA_RX_CDESC0_OFFSET 0x00000040 /**< Rx Current Descriptor 0 */
#define XAXIDMA_RX_CDESC0_MSB_OFFSET 0x00000044 /**< Rx Current Descriptor 0 */
#define XAXIDMA_RX_TDESC0_OFFSET 0x00000048 /**< Rx Tail Descriptor 0 */
#define XAXIDMA_RX_TDESC0_MSB_OFFSET 0x0000004C /**< Rx Tail Descriptor 0 */
#define XAXIDMA_RX_NDESC_OFFSET 0x00000020 /**< Rx Next Descriptor Offset */
/*@}*/
/** @name Bitmasks of XAXIDMA_CR_OFFSET register
* @{
*/
#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /**< Start/stop DMA channel */
#define XAXIDMA_CR_RESET_MASK 0x00000004 /**< Reset DMA engine */
#define XAXIDMA_CR_KEYHOLE_MASK 0x00000008 /**< Keyhole feature */
#define XAXIDMA_CR_CYCLIC_MASK 0x00000010 /**< Cyclic Mode */
/*@}*/
/** @name Bitmasks of XAXIDMA_SR_OFFSET register
*
* This register reports status of a DMA channel, including
* run/stop/idle state, errors, and interrupts (note that interrupt
* masks are shared with XAXIDMA_CR_OFFSET register, and are defined
* in the _IRQ_ section.
*
* The interrupt coalescing threshold value and delay counter value are
* also shared with XAXIDMA_CR_OFFSET register, and are defined in a
* later section.
* @{
*/
#define XAXIDMA_HALTED_MASK 0x00000001 /**< DMA channel halted */
#define XAXIDMA_IDLE_MASK 0x00000002 /**< DMA channel idle */
#define XAXIDMA_ERR_INTERNAL_MASK 0x00000010 /**< Datamover internal
* err */
#define XAXIDMA_ERR_SLAVE_MASK 0x00000020 /**< Datamover slave err */
#define XAXIDMA_ERR_DECODE_MASK 0x00000040 /**< Datamover decode
* err */
#define XAXIDMA_ERR_SG_INT_MASK 0x00000100 /**< SG internal err */
#define XAXIDMA_ERR_SG_SLV_MASK 0x00000200 /**< SG slave err */
#define XAXIDMA_ERR_SG_DEC_MASK 0x00000400 /**< SG decode err */
#define XAXIDMA_ERR_ALL_MASK 0x00000770 /**< All errors */
/** @name Bitmask for interrupts
* These masks are shared by XAXIDMA_CR_OFFSET register and
* XAXIDMA_SR_OFFSET register
* @{
*/
#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /**< Completion intr */
#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /**< Delay interrupt */
#define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /**< Error interrupt */
#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /**< All interrupts */
/*@}*/
/** @name Bitmask and shift for delay and coalesce
* These masks are shared by XAXIDMA_CR_OFFSET register and
* XAXIDMA_SR_OFFSET register
* @{
*/
#define XAXIDMA_DELAY_MASK 0xFF000000 /**< Delay timeout
* counter */
#define XAXIDMA_COALESCE_MASK 0x00FF0000 /**< Coalesce counter */
#define XAXIDMA_DELAY_SHIFT 24
#define XAXIDMA_COALESCE_SHIFT 16
/*@}*/
/* Buffer Descriptor (BD) definitions
*/
/** @name Buffer Descriptor offsets
* USR* fields are defined by higher level IP.
* setup for EMAC type devices. The first 13 words are used by hardware.
* All words after the 13rd word are for software use only.
* @{
*/
#define XAXIDMA_BD_NDESC_OFFSET 0x00 /**< Next descriptor pointer */
#define XAXIDMA_BD_NDESC_MSB_OFFSET 0x04 /**< Next descriptor pointer */
#define XAXIDMA_BD_BUFA_OFFSET 0x08 /**< Buffer address */
#define XAXIDMA_BD_BUFA_MSB_OFFSET 0x0C /**< Buffer address */
#define XAXIDMA_BD_MCCTL_OFFSET 0x10 /**< Multichannel Control Fields */
#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET 0x14 /**< 2D Transfer Sizes */
#define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /**< Control/buffer length */
#define XAXIDMA_BD_STS_OFFSET 0x1C /**< Status */
#define XAXIDMA_BD_USR0_OFFSET 0x20 /**< User IP specific word0 */
#define XAXIDMA_BD_USR1_OFFSET 0x24 /**< User IP specific word1 */
#define XAXIDMA_BD_USR2_OFFSET 0x28 /**< User IP specific word2 */
#define XAXIDMA_BD_USR3_OFFSET 0x2C /**< User IP specific word3 */
#define XAXIDMA_BD_USR4_OFFSET 0x30 /**< User IP specific word4 */
#define XAXIDMA_BD_ID_OFFSET 0x34 /**< Sw ID */
#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /**< Whether has stscntrl strm */
#define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /**< Whether has DRE */
#define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /**< Whether has DRE mask */
#define XAXIDMA_BD_WORDLEN_MASK 0xFF /**< Whether has DRE mask */
#define XAXIDMA_BD_HAS_DRE_SHIFT 8 /**< Whether has DRE shift */
#define XAXIDMA_BD_WORDLEN_SHIFT 0 /**< Whether has DRE shift */
#define XAXIDMA_BD_START_CLEAR 8 /**< Offset to start clear */
#define XAXIDMA_BD_BYTES_TO_CLEAR 48 /**< BD specific bytes to be
* cleared */
#define XAXIDMA_BD_NUM_WORDS 16U /**< Total number of words for
* one BD*/
#define XAXIDMA_BD_HW_NUM_BYTES 52 /**< Number of bytes hw used */
/* The offset of the last app word.
*/
#define XAXIDMA_LAST_APPWORD 4
/*@}*/
#define XAXIDMA_DESC_LSB_MASK (0xFFFFFFC0U) /**< LSB Address mask */
/** @name Bitmasks of XAXIDMA_BD_CTRL_OFFSET register
* @{
*/
#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /**< First tx packet */
#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /**< Last tx packet */
#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /**< All control bits */
/*@}*/
/** @name Bitmasks of XAXIDMA_BD_STS_OFFSET register
* @{
*/
#define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /**< Completed */
#define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /**< Decode error */
#define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /**< Slave error */
#define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /**< Internal err */
#define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /**< All errors */
#define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /**< First rx pkt */
#define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /**< Last rx pkt */
#define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /**< All status bits */
/*@}*/
/** @name Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register
* @{
*/
#define XAXIDMA_BD_TDEST_FIELD_MASK 0x0000000F
#define XAXIDMA_BD_TID_FIELD_MASK 0x00000F00
#define XAXIDMA_BD_TUSER_FIELD_MASK 0x000F0000
#define XAXIDMA_BD_ARCACHE_FIELD_MASK 0x0F000000
#define XAXIDMA_BD_ARUSER_FIELD_MASK 0xF0000000
#define XAXIDMA_BD_TDEST_FIELD_SHIFT 0
#define XAXIDMA_BD_TID_FIELD_SHIFT 8
#define XAXIDMA_BD_TUSER_FIELD_SHIFT 16
#define XAXIDMA_BD_ARCACHE_FIELD_SHIFT 24
#define XAXIDMA_BD_ARUSER_FIELD_SHIFT 28
/*@}*/
/** @name Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register
* @{
*/
#define XAXIDMA_BD_STRIDE_FIELD_MASK 0x0000FFFF
#define XAXIDMA_BD_VSIZE_FIELD_MASK 0xFFF80000
#define XAXIDMA_BD_STRIDE_FIELD_SHIFT 0
#define XAXIDMA_BD_VSIZE_FIELD_SHIFT 19
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XAxiDma_In32 Xil_In32
#define XAxiDma_Out32 Xil_Out32
/*****************************************************************************/
/**
*
* Read the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define XAxiDma_ReadReg(BaseAddress, RegOffset) \
XAxiDma_In32((BaseAddress) + (RegOffset))
/*****************************************************************************/
/**
*
* Write the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data) \
XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))
#ifdef __cplusplus
}
#endif
#endif
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma_porting_guide.h
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/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma_porting_guide.h
* @addtogroup axidma_v9_9
* @{
*
* This is a guide on how to move from using the xlldma driver to use xaxidma
* driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 05/18/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 4.00a rkv 02/22/11 Added support for simple DMA mode
* 6.00a srt 03/27/12 Added support for MCDMA mode
* 7.00a srt 06/18/12 API calls are reverted back for backward compatibility.
*
* </pre>
*
* <b>Overview</b>
*
* The API for xaxidma driver is similar to xlldma driver. The prefix for the
* API functions and structures is XAxiDma_ for the xaxidma driver.
*
* Due to hardware feature changes, signatures of some API functions are a
* little bit different from the xlldma API functions.
*
* We present API functions:
* - That only have prefix changes
* - That have different return type
* - That are new API functions
* - That have been removed
*
* Note that data structures have different prefix of XAxiDma_. Those API
* functions, that have data structures with prefix change, are considered as
* prefix change.
*
* <b>API Functions That Only Have Prefix Changes</b>
*
* <pre>
* xlldma driver | xaxidma driver (upto v5_00_a)
* -----------------------------------------------------------------------
* XLlDma_Reset(...) | XAxiDma_Reset(...)
* XLlDma_BdRingSnapShotCurrBd(...)| XAxiDma_BdRingSnapShotCurrBd(...)
* XLlDma_BdRingNext(...) | XAxiDma_BdRingNext(...)
* XLlDma_BdRingPrev(...) | XAxiDma_BdRingPrev(...)
* XLlDma_BdRingGetSr(...) | XAxiDma_BdRingGetSr(...)
* XLlDma_BdRingBusy(...) | XAxiDma_BdRingBusy(...)
* XLlDma_BdRingIntEnable(...) | XAxiDma_BdRingIntEnable(...)
* XLlDma_BdRingIntDisable(...) | XAxiDma_BdRingIntDisable(...)
* XLlDma_BdRingIntGetEnabled(...) | XAxiDma_BdRingIntGetEnabled(...)
* XLlDma_BdRingGetIrq(...) | XAxiDma_BdRingGetIrq(...)
* XLlDma_BdRingAckIrq(...) | XAxiDma_BdRingAckIrq(...)
* XLlDma_BdRingCreate(...) | XAxiDma_BdRingCreate(...)
* XLlDma_BdRingClone(...) | XAxiDma_BdRingClone(...)
* XLlDma_BdRingAlloc(...) | XAxiDma_BdRingAlloc(...)
* XLlDma_BdRingUnAlloc(...) | XAxiDma_BdRingUnAlloc(...)
* XLlDma_BdRingToHw(...) | XAxiDma_BdRingToHw(...)
* XLlDma_BdRingFromHw(...) | XAxiDma_BdRingFromHw(...)
* XLlDma_BdRingFree(...) | XAxiDma_BdRingFree(...)
* XLlDma_BdRingStart(...) | XAxiDma_BdRingStart(...)
* XLlDma_BdRingCheck(...) | XAxiDma_BdRingCheck(...)
* XLlDma_BdRingSetCoalesce(...) | XAxiDma_BdRingSetCoalesce(...)
* XLlDma_BdRingGetCoalesce(...) | XAxiDma_BdRingGetCoalesce(...)
* XLlDma_BdRead(...) | XAxiDma_BdRead(...)
* XLlDma_BdWrite(...) | XAxiDma_BdWrite(...)
* XLlDma_BdClear(...) | XAxiDma_BdClear(...)
* XLlDma_BdSetId(...) | XAxiDma_BdSetId(...)
* XLlDma_BdGetId(...) | XAxiDma_BdGetId(...)
* XLlDma_BdGetLength(...) | XAxiDma_BdGetLength(...)
* XLlDma_BdGetBufAddr(...) | XAxiDma_BdGetBufAddr(...)
*
*</pre>
*
* <b>API Functions That Have Different Return Type</b>
*
* Due to possible hardware failures, The caller should check the return value
* of the following functions.
*
* <pre>
* xlldma driver | xaxidma driver
* -----------------------------------------------------------------------
* void XLlDma_Pause(...) | int XAxiDma_Pause(...)
* void XLlDma_Resume(...) | int XAxiDma_Resume(...)
* </pre>
*
* The following functions have return type changed:
*
* <pre>
* xlldma driver | xaxidma driver
* -----------------------------------------------------------------------
* XLlDma_BdRing XLlDma_GetRxRing(...)| XAxiDma_BdRing * XAxiDma_GetRxRing(...)
* XLlDma_BdRing XLlDma_GetTxRing(...)| XAxiDma_BdRing * XAxiDma_GetTxRing(...)
* u32 XLlDma_BdRingMemCalc(...) | int XAxiDma_BdRingMemCalc(...)
* u32 XLlDma_BdRingCntCalc(...) | int XAxiDma_BdRingCntCalc(...)
* u32 XLlDma_BdRingGetCnt(...) | int XAxiDma_BdRingGetCnt(...)
* u32 XLlDma_BdRingGetFreeCnt(...) | int XAxiDma_BdRingGetFreeCnt(...)
* void XLlDma_BdSetLength(...) | int XAxiDma_BdSetLength(...)
* void XLlDma_BdSetBufAddr(...) | int XAxiDma_BdSetBufAddr(...)
*</pre>
*
* <b>API Functions That Are New API Functions</b>
*
* Now that the AXI DMA core is a standalone core, some new API are intrduced.
* Some other functions are added due to hardware interface change, so to
* replace old API functions.
*
* - XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
* - int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
* - int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
* - XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr);
* - int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr);
* - void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr);
* - int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr);
* - void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
* - u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr);
* - u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr);
* - int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr);
* - int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr);
* - int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word);
* - u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid);
*
* <b>API Functions That Have Been Removed</b>
*
* Please see individual function comments for how to replace the removed API
* function with new API functions.
*
* - void XLlDma_Initialize(XLlDma * InstancePtr, u32 BaseAddress).
* This function is replaced by XAxiDma_LookupConfig()/XAxiDma_CfgInitialize()
*
* - u32 XLlDma_BdRingGetCr(XLlDma_BdRing* RingPtr).
* This is replaced by XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)
*
* - u32 XLlDma_BdRingSetCr(XLlDma_BdRing* RingPtr, u32 Data).
* This function is covered by other API functions:
* - void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)
* - void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr, u32 Mask)
* - int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter,
* u32 Timer)
*
* - u32 XLlDma_BdSetStsCtrl(XLlDma_Bd* BdPtr, u32 Data).
* Replaced by XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
*
* - u32 XLlDma_BdGetStsCtrl(XLlDma_Bd* BdPtr).
* Replaced by XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr) and
* XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr).
*
* <b>API Functions That Have Been Added to support simple DMA mode</b>
*
* - u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
* - int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, int Length,
* int Direction);
* - XAxiDma_HasSg(InstancePtr);
* - XAxiDma_IntrEnable(InstancePtr,Mask,Direction);
* - XAxiDma_IntrGetEnabled(InstancePtr, Direction);
* - XAxiDma_IntrDisable(InstancePtr, Mask, Direction);
* - XAxiDma_IntrGetIrq(InstancePtr, Direction);
* - XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction);
*
* <b> For xaxidma driver v6_00_a Multiple Channel Support
* ---------------------------------------------------
* This driver supports Multi-channel mode and accordingly some APIs are
* changed to index multiple channels. Few new APIs are added.
* - Changed APIs
* * XAxiDma_GetRxRing(InstancePtr, RingIndex)
* * XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
* * XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
* u32 BuffAddr, u32 Length,
* int Direction, int RingIndex)
* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
* u32 LenBytes, u32 LengthMask)
* * XAxiDma_BdGetActualLength(BdPtr, LengthMask)
* * XAxiDma_BdGetLength(BdPtr, LengthMask)
*
* - New APIs
* * XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
* int Direction, int Select)
* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
* int RingIndex)
* * XAxiDma_BdSetTId()
* * XAxiDma_BdGetTId()
* * XAxiDma_BdSetTDest()
* * XAxiDma_BdGetTDest()
* * XAxiDma_BdSetTUser()
* * XAxiDma_BdGetTUser()
* * XAxiDma_BdSetARCache()
* * XAxiDma_BdGetARCache()
* * XAxiDma_BdSetARUser()
* * XAxiDma_BdGetARUser()
* * XAxiDma_BdSetStride()
* * XAxiDma_BdGetStride()
* * XAxiDma_BdSetVSize()
* * XAxiDma_BdGetVSize()
* <b> For xaxidma driver v7_00_a
* ---------------------------------------------------
* - New API
* * XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
*
* - Changed APIs
* All the APIs changed in v6_00_a are reverted back for backward
* compatibility.
*</pre>
*
******************************************************************************/
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma_selftest.c
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/******************************************************************************
*
* Copyright (C) 2015 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma_selftest.c
* @addtogroup axidma_v9_9
* @{
*
* Contains diagnostic/self-test functions for the XAxiDma component.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 8.1 adk 29/01/15 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "xaxidma.h"
/************************** Constant Definitions *****************************/
#define XAXIDMA_RESET_TIMEOUT 500
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Runs a self-test on the driver/device. This test perform a
* reset of the DMA device and checks the device is coming out of reset or not
*
* @param InstancePtr is a pointer to the XAxiDma instance.
*
* @return
* - XST_SUCCESS if self-test was successful
* - XST_FAILURE if the device is not coming out of reset.
*
* @note
* None.
*
******************************************************************************/
int XAxiDma_Selftest(XAxiDma * InstancePtr)
{
int TimeOut;
Xil_AssertNonvoid(InstancePtr != NULL);
XAxiDma_Reset(InstancePtr);
/* At the initialization time, hardware should finish reset quickly
*/
TimeOut = XAXIDMA_RESET_TIMEOUT;
while (TimeOut) {
if(XAxiDma_ResetIsDone(InstancePtr)) {
break;
}
TimeOut -= 1;
}
if (!TimeOut)
return XST_FAILURE;
return XST_SUCCESS;
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xaxidma_sinit.c
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/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxidma_sinit.c
* @addtogroup axidma_v9_9
* @{
*
* Look up the hardware settings using device ID. The hardware setting is inside
* the configuration table in xaxidma_g.c, generated automatically by XPS or
* manually by the user.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 08/16/10 First release
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
* updated tcl file, added xaxidma_porting_guide.h
* 3.00a jz 11/22/10 Support IP core parameters change
* 5.00a srt 08/29/11 Removed a compiler warning
* 9.5 rsp 11/01/17 Add interface to do config lookup based on base address.
* 9.6 rsp 01/11/18 In LookupConfig use UINTPTR for Baseaddr CR#976392
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xaxidma.h"
/*****************************************************************************/
/**
* Look up the hardware configuration for a device instance
*
* @param DeviceId is the unique device ID of the device to lookup for
*
* @return
* The configuration structure for the device. If the device ID is
* not found,a NULL pointer is returned.
*
* @note None
*
******************************************************************************/
XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId)
{
extern XAxiDma_Config XAxiDma_ConfigTable[];
XAxiDma_Config *CfgPtr;
u32 Index;
CfgPtr = NULL;
for (Index = 0; Index < XPAR_XAXIDMA_NUM_INSTANCES; Index++) {
if (XAxiDma_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XAxiDma_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/*****************************************************************************/
/**
* Look up the hardware configuration for a device instance based on base address
*
* @param Baseaddr is the base address of the device to lookup for
*
* @return
* The configuration structure for the device. If the device base
* address is not found,a NULL pointer is returned.
*
* @note None
*
******************************************************************************/
XAxiDma_Config *XAxiDma_LookupConfigBaseAddr(UINTPTR Baseaddr)
{
extern XAxiDma_Config XAxiDma_ConfigTable[];
XAxiDma_Config *CfgPtr;
u32 Index;
CfgPtr = NULL;
for (Index = 0; Index < XPAR_XAXIDMA_NUM_INSTANCES; Index++) {
if (XAxiDma_ConfigTable[Index].BaseAddr == Baseaddr) {
CfgPtr = &XAxiDma_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/axidma_v9_9/src/xdebug.h
+89
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@@ -0,0 +1,89 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef _XDEBUG_H
#define _XDEBUG_H
#if defined(DEBUG) && !defined(NDEBUG)
#include <stdio.h>
#ifndef XDEBUG_WARNING
#define XDEBUG_WARNING
#warning DEBUG is enabled
#endif
#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */
#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */
#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */
#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */
#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */
#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */
#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */
#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */
#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */
#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */
#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */
#define xdbg_current_types (XDBG_DEBUG_ERROR)
#define xdbg_stmnt(x) x
/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
* macros that accept variable number of arguments
*/
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
#else /* ANSI Syntax */
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
#endif
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x)
/* See VxWorks comments above */
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...)
#else /* ANSI Syntax */
#define xdbg_printf(...)
#endif
#endif /* defined(DEBUG) && !defined(NDEBUG) */
#endif /* _XDEBUG_H */
datalink814_sp/bsp/microblaze_ps/libsrc/bram_v4_3/src/Makefile
+28
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@@ -0,0 +1,28 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs:
echo "Compiling bram"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OBJECTS)
make clean
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}
datalink814_sp/bsp/microblaze_ps/libsrc/bram_v4_3/src/xbram.c
+145
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@@ -0,0 +1,145 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/**
* @file xbram.c
* @addtogroup bram_v4_2
* @{
*
* The implementation of the XBram driver's basic functionality.
* See xbram.h for more information about the driver.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 05/11/10 First release
* 3.01a sa 13/01/12 Added CorrectableFailingDataRegs and
* UncorrectableFailingDataRegs in
* XBram_CfgInitialize API.
* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XBram_CfgInitialize API.
*</pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xbram.h"
#include "xstatus.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Initialize the XBram instance provided by the caller based on the given
* configuration data.
*
* Nothing is done except to initialize the InstancePtr.
*
* @param InstancePtr is a pointer to an XBram instance.
* The memory the pointer references must be pre-allocated by
* the caller. Further calls to manipulate the driver through
* the XBram API must be made with this pointer.
* @param Config is a reference to a structure containing information
* about a specific BRAM device. This function
* initializes an InstancePtr object for a specific device
* specified by the contents of Config. This function can
* initialize multiple instance objects with the use of multiple
* calls giving different Config information on each call.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. The caller is responsible for keeping the
* address mapping from EffectiveAddr to the device physical base
* address unchanged once this function is invoked. Unexpected
* errors may occur if the address mapping changes after this
* function is called. If address translation is not used, use
* Config->BaseAddress for this parameters, passing the physical
* address instead.
*
* @return
* - XST_SUCCESS Initialization was successful.
*
* @note None.
*
*****************************************************************************/
int XBram_CfgInitialize(XBram *InstancePtr,
XBram_Config *Config,
UINTPTR EffectiveAddr)
{
/*
* Assert arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Set some default values.
*/
InstancePtr->Config.CtrlBaseAddress = EffectiveAddr;
InstancePtr->Config.MemBaseAddress = Config->MemBaseAddress;
InstancePtr->Config.MemHighAddress = Config->MemHighAddress;
InstancePtr->Config.DataWidth = Config->DataWidth;
InstancePtr->Config.EccPresent = Config->EccPresent;
InstancePtr->Config.FaultInjectionPresent =
Config->FaultInjectionPresent;
InstancePtr->Config.CorrectableFailingRegisters =
Config->CorrectableFailingRegisters;
InstancePtr->Config.CorrectableFailingDataRegs =
Config->CorrectableFailingDataRegs;
InstancePtr->Config.UncorrectableFailingRegisters =
Config->UncorrectableFailingRegisters;
InstancePtr->Config.UncorrectableFailingDataRegs =
Config->UncorrectableFailingDataRegs;
InstancePtr->Config.EccStatusInterruptPresent =
Config->EccStatusInterruptPresent;
InstancePtr->Config.CorrectableCounterBits =
Config->CorrectableCounterBits;
InstancePtr->Config.WriteAccess = Config->WriteAccess;
/*
* Indicate the instance is now ready to use, initialized without error
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return (XST_SUCCESS);
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/bram_v4_3/src/xbram.h
+223
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@@ -0,0 +1,223 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram.h
* @addtogroup bram_v4_2
* @{
* @details
*
* If ECC is not enabled, this driver exists only to allow the tools to
* create a memory test application and to populate xparameters.h with memory
* range constants. In this case there is no source code.
*
* If ECC is enabled, this file contains the software API definition of the
* Xilinx BRAM Interface Controller (XBram) device driver.
*
* The Xilinx BRAM controller is a soft IP core designed for Xilinx
* FPGAs and contains the following general features:
* - LMB v2.0 bus interfaces with byte enable support
* - Used in conjunction with bram_block peripheral to provide fast BRAM
* memory solution for MicroBlaze ILMB and DLMB ports
* - Supports byte, half-word, and word transfers
* - Supports optional BRAM error correction and detection.
*
* The driver provides interrupt management functions. Implementation of
* interrupt handlers is left to the user. Refer to the provided interrupt
* example in the examples directory for details.
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* <b>Initialization & Configuration</b>
*
* The XBram_Config structure is used by the driver to configure
* itself. This configuration structure is typically created by the tool-chain
* based on HW build properties.
*
* To support multiple runtime loading and initialization strategies employed
* by various operating systems, the driver instance can be initialized as
* follows:
*
* - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
* Uses a configuration structure provided by the caller. If running in a
* system with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* @note
*
* This API utilizes 32 bit I/O to the BRAM registers. With less
* than 32 bits, the unused bits from registers are read as zero and written as
* don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 3.00a sa 05/11/10 Added ECC support
* 3.01a sa 01/13/12 Changed Selftest API from
* XBram_SelfTest(XBram *InstancePtr) to
* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
* fixed a problem with interrupt generation for CR 639274
* Modified Selftest example to return XST_SUCCESS when
* ECC is not enabled and return XST_FAILURE when ECC is
* enabled and Control Base Address is zero (CR 636581)
* Modified Selftest to use correct CorrectableCounterBits
* for CR 635655
* Updated to check CorrectableFailingDataRegs in the case
* of LMB BRAM.
* Added CorrectableFailingDataRegs and
* UncorrectableFailingDataRegs to the config structure to
* distinguish between AXI BRAM and LMB BRAM.
* These registers are not present in the current version of
* the AXI BRAM Controller.
* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
* 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
* to support both xps and vivado designs.
* 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
* when ecc is disabled cr:705002.
* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
* flush the Cache after writing to BRAM in InjectErrors
* API(CR #719011)
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XBram_CfgInitialize API.
* ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 4.2 ms 04/18/17 Modified tcl file to add suffix U for all macro
* definitions of bram in xparameters.h
* ms 08/07/17 Fixed compilation warnings in xbram_sinit.c
* 4.3 aru 03/23/19 Used UINTPTR instead of u32 for MemBaseAddress and
* MemHighAddress.
* </pre>
*****************************************************************************/
#ifndef XBRAM_H /* prevent circular inclusions */
#define XBRAM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xbram_hw.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 DataWidth; /**< BRAM data width */
int EccPresent; /**< Is ECC supported in H/W */
int FaultInjectionPresent; /**< Is Fault Injection
* supported in H/W */
int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
* supported in H/W */
int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
* Registers supported in H/W */
int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
* Registers supported in H/W */
int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
* Registers supported in H/W */
int EccStatusInterruptPresent; /**< Are ECC status and interrupts
* supported in H/W */
int CorrectableCounterBits; /**< Number of bits in the
* Correctable Error Counter */
int EccOnOffRegister; /**< Is ECC on/off register supported
* in h/w */
int EccOnOffResetValue; /**< Reset value of the ECC on/off
* register in h/w */
int WriteAccess; /**< Is write access enabled in
* h/w */
UINTPTR MemBaseAddress; /**< Device memory base address */
UINTPTR MemHighAddress; /**< Device memory high address */
UINTPTR CtrlBaseAddress; /**< Device register base address.*/
UINTPTR CtrlHighAddress; /**< Device register base address.*/
} XBram_Config;
/**
* The XBram driver instance data. The user is required to
* allocate a variable of this type for every BRAM device in the
* system. A pointer to a variable of this type is then passed to the driver
* API functions.
*/
typedef struct {
XBram_Config Config; /* BRAM config structure */
u32 IsReady; /* Device is initialized and ready */
} XBram;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
/*
* Functions in xbram_sinit.c
*/
XBram_Config *XBram_LookupConfig(u16 DeviceId);
/*
* Functions implemented in xbram.c
*/
int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
UINTPTR EffectiveAddr);
/*
* Functions implemented in xbram_selftest.c
*/
int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
/*
* Functions implemented in xbram_intr.c
*/
void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
u32 XBram_InterruptGetStatus(XBram *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/bram_v4_3/src/xbram_g.c
+180
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@@ -0,0 +1,180 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1.3
* DO NOT EDIT.
*
* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xbram.h"
/*
* The configuration table for devices
*/
XBram_Config XBram_ConfigTable[] =
{
{
XPAR_ANT_CONFIG_BRAM_CTRL_DEVICE_ID,
XPAR_ANT_CONFIG_BRAM_CTRL_DATA_WIDTH,
XPAR_ANT_CONFIG_BRAM_CTRL_ECC,
XPAR_ANT_CONFIG_BRAM_CTRL_FAULT_INJECT,
XPAR_ANT_CONFIG_BRAM_CTRL_CE_FAILING_REGISTERS,
0,
XPAR_ANT_CONFIG_BRAM_CTRL_UE_FAILING_REGISTERS,
0,
XPAR_ANT_CONFIG_BRAM_CTRL_ECC_STATUS_REGISTERS,
XPAR_ANT_CONFIG_BRAM_CTRL_CE_COUNTER_WIDTH,
XPAR_ANT_CONFIG_BRAM_CTRL_ECC_ONOFF_REGISTER,
XPAR_ANT_CONFIG_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
XPAR_ANT_CONFIG_BRAM_CTRL_WRITE_ACCESS,
XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_BASEADDR,
XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_HIGHADDR,
XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
},
{
XPAR_C2C_RX_AXI_BRAM_CTRL_DEVICE_ID,
XPAR_C2C_RX_AXI_BRAM_CTRL_DATA_WIDTH,
XPAR_C2C_RX_AXI_BRAM_CTRL_ECC,
XPAR_C2C_RX_AXI_BRAM_CTRL_FAULT_INJECT,
XPAR_C2C_RX_AXI_BRAM_CTRL_CE_FAILING_REGISTERS,
0,
XPAR_C2C_RX_AXI_BRAM_CTRL_UE_FAILING_REGISTERS,
0,
XPAR_C2C_RX_AXI_BRAM_CTRL_ECC_STATUS_REGISTERS,
XPAR_C2C_RX_AXI_BRAM_CTRL_CE_COUNTER_WIDTH,
XPAR_C2C_RX_AXI_BRAM_CTRL_ECC_ONOFF_REGISTER,
XPAR_C2C_RX_AXI_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
XPAR_C2C_RX_AXI_BRAM_CTRL_WRITE_ACCESS,
XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_BASEADDR,
XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_HIGHADDR,
XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
},
{
XPAR_C2C_TX_AXI_BRAM_CTRL_DEVICE_ID,
XPAR_C2C_TX_AXI_BRAM_CTRL_DATA_WIDTH,
XPAR_C2C_TX_AXI_BRAM_CTRL_ECC,
XPAR_C2C_TX_AXI_BRAM_CTRL_FAULT_INJECT,
XPAR_C2C_TX_AXI_BRAM_CTRL_CE_FAILING_REGISTERS,
0,
XPAR_C2C_TX_AXI_BRAM_CTRL_UE_FAILING_REGISTERS,
0,
XPAR_C2C_TX_AXI_BRAM_CTRL_ECC_STATUS_REGISTERS,
XPAR_C2C_TX_AXI_BRAM_CTRL_CE_COUNTER_WIDTH,
XPAR_C2C_TX_AXI_BRAM_CTRL_ECC_ONOFF_REGISTER,
XPAR_C2C_TX_AXI_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
XPAR_C2C_TX_AXI_BRAM_CTRL_WRITE_ACCESS,
XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_BASEADDR,
XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_HIGHADDR,
XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
},
{
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR
},
{
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR,
XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR
},
{
XPAR_RX_FRAME_BRAM_CTRL_DEVICE_ID,
XPAR_RX_FRAME_BRAM_CTRL_DATA_WIDTH,
XPAR_RX_FRAME_BRAM_CTRL_ECC,
XPAR_RX_FRAME_BRAM_CTRL_FAULT_INJECT,
XPAR_RX_FRAME_BRAM_CTRL_CE_FAILING_REGISTERS,
0,
XPAR_RX_FRAME_BRAM_CTRL_UE_FAILING_REGISTERS,
0,
XPAR_RX_FRAME_BRAM_CTRL_ECC_STATUS_REGISTERS,
XPAR_RX_FRAME_BRAM_CTRL_CE_COUNTER_WIDTH,
XPAR_RX_FRAME_BRAM_CTRL_ECC_ONOFF_REGISTER,
XPAR_RX_FRAME_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
XPAR_RX_FRAME_BRAM_CTRL_WRITE_ACCESS,
XPAR_RX_FRAME_BRAM_CTRL_S_AXI_BASEADDR,
XPAR_RX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR,
XPAR_RX_FRAME_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
XPAR_RX_FRAME_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
},
{
XPAR_TX_FRAME_BRAM_CTRL_DEVICE_ID,
XPAR_TX_FRAME_BRAM_CTRL_DATA_WIDTH,
XPAR_TX_FRAME_BRAM_CTRL_ECC,
XPAR_TX_FRAME_BRAM_CTRL_FAULT_INJECT,
XPAR_TX_FRAME_BRAM_CTRL_CE_FAILING_REGISTERS,
0,
XPAR_TX_FRAME_BRAM_CTRL_UE_FAILING_REGISTERS,
0,
XPAR_TX_FRAME_BRAM_CTRL_ECC_STATUS_REGISTERS,
XPAR_TX_FRAME_BRAM_CTRL_CE_COUNTER_WIDTH,
XPAR_TX_FRAME_BRAM_CTRL_ECC_ONOFF_REGISTER,
XPAR_TX_FRAME_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
XPAR_TX_FRAME_BRAM_CTRL_WRITE_ACCESS,
XPAR_TX_FRAME_BRAM_CTRL_S_AXI_BASEADDR,
XPAR_TX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR,
XPAR_TX_FRAME_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
XPAR_TX_FRAME_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
}
};
datalink814_sp/bsp/microblaze_ps/libsrc/bram_v4_3/src/xbram_hw.h
+405
View File
@@ -0,0 +1,405 @@
/******************************************************************************
*
* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbram_hw.h
* @addtogroup bram_v4_2
* @{
*
* This header file contains identifiers and driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 24/11/10 First release
* </pre>
*
******************************************************************************/
#ifndef XBRAM_HW_H /* prevent circular inclusions */
#define XBRAM_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Registers
*
* Register offsets for this device.
* @{
*/
#define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
#define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
#define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
#define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
#define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
* data Register, 31-0 */
#define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
* data Register, 63-32 */
#define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
* data Register, 95-64 */
#define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
* data Register, 127-96 */
#define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
* data Register, 159-128 */
#define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
* data Register, 191-160 */
#define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
* data Register, 223-192 */
#define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
* data Register, 255-224 */
#define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
* data Register, 287-256 */
#define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
* data Register, 319-288 */
#define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
* data Register, 351-320 */
#define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
* data Register, 383-352 */
#define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
* data Register, 415-384 */
#define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
* data Register, 447-416 */
#define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
* data Register, 479-448 */
#define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
* data Register, 511-480 */
#define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
* data Register, 543-512 */
#define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
* data Register, 575-544 */
#define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
* data Register, 607-576 */
#define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
* data Register, 639-608 */
#define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
* data Register, 671-640 */
#define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
* data Register, 703-672 */
#define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
* data Register, 735-704 */
#define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
* data Register, 767-736 */
#define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
* data Register, 799-768 */
#define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
* data Register, 831-800 */
#define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
* data Register, 863-832 */
#define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
* data Register, 895-864 */
#define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
* data Register, 927-896 */
#define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
* data Register, 959-928 */
#define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
* data Register, 991-960 */
#define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
* data Register, 1023-992 */
#define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
* ECC Register, 31-0 */
#define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
* ECC Register, 63-32 */
#define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
* ECC Register, 95-64 */
#define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
* ECC Register, 127-96 */
#define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
* ECC Register, 159-128 */
#define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
* ECC Register, 191-160 */
#define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
* ECC Register, 223-192 */
#define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
* ECC Register, 255-224 */
#define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
* address Register 31-0 */
#define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
* address Register 63-32 */
#define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
* data Register, 31-0 */
#define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
* data Register, 63-32 */
#define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
* data Register, 95-64 */
#define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
* data Register, 127-96 */
#define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
* data Register, 159-128 */
#define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
* data Register, 191-160 */
#define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
* data Register, 223-192 */
#define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
* data Register, 255-224 */
#define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
* data Register, 287-256 */
#define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
* data Register, 319-288 */
#define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
* data Register, 351-320 */
#define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
* data Register, 383-352 */
#define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
* data Register, 415-384 */
#define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
* data Register, 447-416 */
#define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
* data Register, 479-448 */
#define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
* data Register, 511-480 */
#define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
* data Register, 543-512 */
#define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
* data Register, 575-544 */
#define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
* data Register, 607-576 */
#define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
* data Register, 639-608 */
#define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
* data Register, 671-640 */
#define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
* data Register, 703-672 */
#define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
* data Register, 735-704 */
#define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
* data Register, 767-736 */
#define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
* data Register, 799-768 */
#define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
* data Register, 831-800 */
#define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
* data Register, 863-832 */
#define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
* data Register, 895-864 */
#define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
* data Register, 927-896 */
#define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
* data Register, 959-928 */
#define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
* data Register, 991-960 */
#define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
* data Register, 1023-992 */
#define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
* ECC Register, 31-0 */
#define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
* ECC Register, 63-32 */
#define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
* ECC Register, 95-64 */
#define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
* ECC Register, 127-96 */
#define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
* ECC Register, 159-128 */
#define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
* ECC Register, 191-160 */
#define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
* ECC Register, 223-192 */
#define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
* ECC Register, 255-224 */
#define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
* address Register 31-0 */
#define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
* address Register 63-32 */
#define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
* 31-0 */
#define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
* 63-32 */
#define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
* 95-64 */
#define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
* 127-96 */
#define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
* 159-128 */
#define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
* 191-160 */
#define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
* 223-192 */
#define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
* 255-224 */
#define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
* 287-256 */
#define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
* 319-288 */
#define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
* 351-320 */
#define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
* 383-352 */
#define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
* 415-384 */
#define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
* 447-416 */
#define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
* 479-448 */
#define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
* 511-480 */
#define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
* 543-512 */
#define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
* 575-544 */
#define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
* 607-576 */
#define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
* 639-608 */
#define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
* 671-640 */
#define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
* 703-672 */
#define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
* 735-704 */
#define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
* 767-736 */
#define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
* 799-768 */
#define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
* 831-800 */
#define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
* 863-832 */
#define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
* 895-864 */
#define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
* 927-896 */
#define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
* 959-928 */
#define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
* 991-960 */
#define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
* 1023-992 */
#define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
* 31-0 */
#define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
* 63-32 */
#define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
* 95-64 */
#define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
* 127-96 */
#define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
* 159-128 */
#define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
* 191-160 */
#define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
* 223-192 */
#define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
* 255-224 */
/* @} */
/** @name Interrupt Status and Enable Register bitmaps and masks
*
* Bit definitions for the ECC status register and ECC interrupt enable register.
* @{
*/
#define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
#define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
#define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XBram_In32 Xil_In32
#define XBram_Out32 Xil_Out32
#define XBram_In16 Xil_In16
#define XBram_Out16 Xil_Out16
#define XBram_In8 Xil_In8
#define XBram_Out8 Xil_Out8
/****************************************************************************/
/**
*
* Write a value to a BRAM register. A 32 bit write is performed.
*
* @param BaseAddress is the base address of the BRAM device register.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note C-style signature:
* void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
****************************************************************************/
#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/****************************************************************************/
/**
*
* Read a value from a BRAM register. A 32 bit read is performed.
*
* @param BaseAddress is the base address of the BRAM device registers.
* @param RegOffset is the register offset from the base to read from.
*
* @return Data read from the register.
*
* @note C-style signature:
* u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
*
****************************************************************************/
#define XBram_ReadReg(BaseAddress, RegOffset) \
XBram_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/bram_v4_3/src/xbram_intr.c
+234
View File
@@ -0,0 +1,234 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram_intr.c
* @addtogroup bram_v4_2
* @{
*
* Implements BRAM interrupt processing functions for the
* XBram driver. See xbram.h for more information
* about the driver.
*
* The functions in this file require the hardware device to be built with
* interrupt capabilities. The functions will assert if called using hardware
* that does not have interrupt capabilities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 05/11/10 Initial release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xbram.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Enable interrupts. This function will assert if the hardware device has not
* been built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to enable. Bit positions of 1 are enabled.
* This mask is formed by OR'ing bits from XBRAM_IR*
* bits which are contained in xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt enable register and only enable the specified
* interrupts without disabling or enabling any others.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET,
Register | Mask);
}
/****************************************************************************/
/**
* Disable interrupts. This function allows each specific interrupt to be
* disabled. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to disable. Bits set to 1 are disabled. This
* mask is formed by OR'ing bits from XBRAM_IR* bits
* which are contained in xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt enable register and only disable the specified
* interrupts without enabling or disabling any others.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET,
Register & (~Mask));
}
/****************************************************************************/
/**
* Clear pending interrupts with the provided mask. This function should be
* called after the software has serviced the interrupts that are pending.
* This function will assert if the hardware device has not been built with
* interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to clear pending interrupts for. Bit positions
* of 1 are cleared. This mask is formed by OR'ing bits from
* XBRAM_IR* bits which are contained in
* xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptClear(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt status register and only clear the interrupts
* that are specified without affecting any others. Since the register
* is a toggle on write, make sure any bits to be written are already
* set.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_STATUS_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_STATUS_OFFSET,
Register & Mask);
}
/****************************************************************************/
/**
* Returns the interrupt enable mask. This function will assert if the
* hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
*
* @return A mask of bits made from XBRAM_IR* bits which
* are contained in xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
u32 XBram_InterruptGetEnabled(XBram * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
}
/****************************************************************************/
/**
* Returns the status of interrupt signals. Any bit in the mask set to 1
* indicates that the channel associated with the bit has asserted an interrupt
* condition. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
*
* @return A pointer to a mask of bits made from XBRAM_IR*
* bits which are contained in xbram_hw.h.
*
* @note
*
* The interrupt status indicates the status of the device irregardless if
* the interrupts from the devices have been enabled or not through
* XBram_InterruptEnable().
*
*****************************************************************************/
u32 XBram_InterruptGetStatus(XBram * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/bram_v4_3/src/xbram_selftest.c
+557
View File
@@ -0,0 +1,557 @@
/******************************************************************************
*
* Copyright (C) 2011 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram_selftest.c
* @addtogroup bram_v4_2
* @{
*
* The implementation of the XBram driver's self test function. This SelfTest
* is only applicable if ECC is enabled.
* If ECC is not enabled then this function will return XST_SUCCESS.
* See xbram.h for more information about the driver.
* Temp change
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 11/24/10 First release
* 3.01a sa 01/13/12 Changed Selftest API from
* XBram_SelfTest(XBram *InstancePtr) to
* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
* fixed a problem with interrupt generation for CR 639274
* Modified Selftest example to return XST_SUCCESS when
* ECC is not enabled and return XST_FAILURE when ECC is
* enabled and Control Base Address is zero (CR 636581)
* Modified Selftest to use correct CorrectableCounterBits
* for CR 635655
* Updated to check CorrectableFailingDataRegs in the case
* of LMB BRAM.
* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in InjectErrors API to
* flush the Cache after writing to BRAM (CR #719011)
* 4.3 aru 04/09/19 Used UINTPTR instead of u32 for Addr in XBram_SelfTest()
*
* </pre>
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xbram.h"
#include "xil_cache.h"
/************************** Constant Definitions ****************************/
#define TOTAL_BITS 39
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
#define RD(reg) XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress, \
XBRAM_ ## reg)
#define WR(reg, data) XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress, \
XBRAM_ ## reg, data)
#define CHECK(reg, data, result) if (result!=XST_SUCCESS || RD(reg)!=data) \
result = XST_FAILURE;
/************************** Variable Definitions ****************************/
static u32 PrngResult;
/************************** Function Prototypes *****************************/
static inline u32 PrngData(u32 *PrngResult);
static inline u32 CalculateEcc(u32 Data);
static void InjectErrors(XBram * InstancePtr, UINTPTR Addr,
int Index1, int Index2, int Width,
u32 *ActualData, u32 *ActualEcc);
/*****************************************************************************/
/**
* Generate a pseudo random number.
*
* @param The PrngResult is the previous random number in the pseudo
* random sequence, also knwon as the seed. It is modified to
* the calculated pseudo random number by the function.
*
* @return The generated pseudo random number
*
* @note None.
*
******************************************************************************/
static inline u32 PrngData(u32 *PrngResult)
{
*PrngResult = *PrngResult * 0x77D15E25 + 0x3617C161;
return *PrngResult;
}
/*****************************************************************************/
/**
* Calculate ECC from Data.
*
* @param The Data Value
*
* @return The calculated ECC
*
* @note None.
*
******************************************************************************/
static inline u32 CalculateEcc(u32 Data)
{
unsigned char c[7], d[32];
u32 Result = 0;
int Index;
for (Index = 0; Index < 32; Index++) {
d[31 - Index] = Data & 1;
Data = Data >> 1;
}
c[0] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[8] ^ d[10] ^ d[11] ^
d[13] ^ d[15] ^ d[17] ^ d[19] ^ d[21] ^ d[23] ^ d[25] ^ d[26] ^
d[28] ^ d[30];
c[1] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[9] ^ d[10] ^ d[12] ^
d[13] ^ d[16] ^ d[17] ^ d[20] ^ d[21] ^ d[24] ^ d[25] ^ d[27] ^
d[28] ^ d[31];
c[2] = d[1] ^ d[2] ^ d[3] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[14] ^
d[15] ^ d[16] ^ d[17] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[29] ^
d[30] ^ d[31];
c[3] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[18] ^
d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
c[4] = d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^
d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
c[5] = d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
c[6] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^
d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^
d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^
d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] ^
c[5] ^ c[4] ^ c[3] ^ c[2] ^ c[1] ^ c[0];
for (Index = 0; Index < 7; Index++) {
Result = Result << 1;
Result |= c[Index] & 1;
}
return Result;
}
/*****************************************************************************/
/**
* Get the expected actual data read in case of uncorrectable errors.
*
* @param The injected data value including errors (if any)
* @param The syndrome (calculated ecc ^ actual ecc read)
*
* @return The actual data value read
*
* @note None.
*
******************************************************************************/
static inline u32 UncorrectableData(u32 Data, u8 Syndrome)
{
switch (Syndrome) {
case 0x03: return Data ^ 0x00000034;
case 0x05: return Data ^ 0x001a2000;
case 0x09: return Data ^ 0x0d000000;
case 0x0d: return Data ^ 0x00001a00;
case 0x11: return Data ^ 0x60000000;
case 0x13: return Data ^ 0x00000003;
case 0x15: return Data ^ 0x00018000;
case 0x19: return Data ^ 0x00c00000;
case 0x1d: return Data ^ 0x00000180;
case 0x21: return Data ^ 0x80000000;
case 0x23: return Data ^ 0x00000008;
case 0x25: return Data ^ 0x00040000;
case 0x29: return Data ^ 0x02000000;
case 0x2d: return Data ^ 0x00000400;
case 0x31: return Data ^ 0x10000000;
case 0x35: return Data ^ 0x00004000;
case 0x39: return Data ^ 0x00200000;
case 0x3d: return Data ^ 0x00000040;
}
return Data;
}
/*****************************************************************************/
/**
* Inject errors using the hardware fault injection functionality, and write
* random data and read it back using the indicated location.
*
* @param InstancePtr is a pointer to the XBram instance to
* be worked on.
* @param The Addr is the indicated memory location to use
* @param The Index1 is the bit location of the first injected error
* @param The Index2 is the bit location of the second injected error
* @param The Width is the data byte width
* @param The ActualData is filled in with expected data for checking
* @param The ActualEcc is filled in with expected ECC for checking
*
* @return None
*
* @note None.
*
******************************************************************************/
static void InjectErrors(XBram * InstancePtr, UINTPTR Addr,
int Index1, int Index2, int Width,
u32 *ActualData, u32 *ActualEcc)
{
u32 InjectedData = 0;
u32 InjectedEcc = 0;
u32 RandomData = PrngData(&PrngResult);
if (Index1 < 32) {
InjectedData = 1 << Index1;
} else {
InjectedEcc = 1 << (Index1 - 32);
}
if (Index2 < 32) {
InjectedData |= (1 << Index2);
} else {
InjectedEcc |= 1 << (Index2 - 32);
}
WR(FI_D_0_OFFSET, InjectedData);
WR(FI_ECC_0_OFFSET, InjectedEcc);
XBram_Out32(Addr, RandomData);
Xil_DCacheFlushRange(Addr, 4);
switch (Width) {
case 1: /* Byte - Write to do Read-Modify-Write */
XBram_Out8(Addr, PrngData(&PrngResult) & 0xFF);
break;
case 2: /* Halfword - Write to do Read-Modify-Write */
XBram_Out16(Addr, PrngData(&PrngResult) & 0xFFFF);
break;
case 4: /* Word - Read */
(void) XBram_In32(Addr);
break;
}
*ActualData = InjectedData ^ RandomData;
*ActualEcc = InjectedEcc ^ CalculateEcc(RandomData);
}
/*****************************************************************************/
/**
* Run a self-test on the driver/device. Unless fault injection is implemented
* in hardware, this function only does a minimal test in which available
* registers (if any) are written and read.
*
* With fault injection, all possible single-bit and double-bit errors are
* injected, and checked to the extent possible, given the implemented hardware.
*
* @param InstancePtr is a pointer to the XBram instance.
* @param IntMask is the interrupt mask to use. When testing
* with interrupts, this should be set to allow interrupt
* generation, otherwise it should be 0.
*
* @return
* - XST_SUCCESS if fault injection/detection is working properly OR
* if ECC is Not Enabled in the HW.
* - XST_FAILURE if the injected fault is not correctly detected or
* the Control Base Address is Zero when ECC is enabled.
* .
*
* If the BRAM device is not present in the
* hardware a bus error could be generated. Other indicators of a
* bus error, such as registers in bridges or buses, may be
* necessary to determine if this function caused a bus error.
*
* @note None.
*
******************************************************************************/
int XBram_SelfTest(XBram *InstancePtr, u8 IntMask)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.EccPresent == 0) {
return (XST_SUCCESS);
}
if (InstancePtr->Config.CtrlBaseAddress == 0) {
return (XST_SUCCESS);
}
/*
* Only 32-bit data width is supported as of yet. 64-bit and 128-bit
* widths will be supported in future.
*/
if (InstancePtr->Config.DataWidth != 32)
return (XST_SUCCESS);
/*
* Read from the implemented readable registers in the hardware device.
*/
if (InstancePtr->Config.CorrectableFailingRegisters) {
(void) RD(CE_FFA_0_OFFSET);
}
if (InstancePtr->Config.CorrectableFailingDataRegs) {
(void) RD(CE_FFD_0_OFFSET);
(void) RD(CE_FFE_0_OFFSET);
}
if (InstancePtr->Config.UncorrectableFailingRegisters) {
(void) RD(UE_FFA_0_OFFSET);
}
if (InstancePtr->Config.UncorrectableFailingDataRegs) {
(void) RD(UE_FFD_0_OFFSET);
(void) RD(UE_FFE_0_OFFSET);
}
/*
* Write and read the implemented read/write registers in the hardware
* device.
*/
if (InstancePtr->Config.EccStatusInterruptPresent) {
WR(ECC_EN_IRQ_OFFSET, 0);
if (RD(ECC_EN_IRQ_OFFSET) != 0) {
return (XST_FAILURE);
}
}
if (InstancePtr->Config.CorrectableCounterBits > 0) {
u32 Value;
/* Calculate counter max value */
if (InstancePtr->Config.CorrectableCounterBits == 32) {
Value = 0xFFFFFFFF;
} else {
Value = (1 <<
InstancePtr->Config.CorrectableCounterBits) - 1;
}
WR(CE_CNT_OFFSET, Value);
if (RD(CE_CNT_OFFSET) != Value) {
return (XST_FAILURE);
}
WR(CE_CNT_OFFSET, 0);
if (RD(CE_CNT_OFFSET) != 0) {
return (XST_FAILURE);
}
}
/*
* If fault injection is implemented, inject all possible single-bit
* and double-bit errors, and check all observable effects.
*/
if (InstancePtr->Config.FaultInjectionPresent &&
InstancePtr->Config.WriteAccess != 0) {
const UINTPTR Addr[2] = {InstancePtr->Config.MemBaseAddress &
(UINTPTR)0xfffffffffffffffc,
InstancePtr->Config.MemHighAddress &
(UINTPTR)0xfffffffffffffffc};
u32 SavedWords[2];
u32 ActualData;
u32 ActualEcc;
u32 CounterValue = 0;
u32 CounterMax;
int WordIndex = 0;
int Result = XST_SUCCESS;
int Index1;
int Index2;
int Width;
PrngResult = 42; /* Random seed */
/* Save two words in BRAM used for test */
SavedWords[0] = XBram_In32(Addr[0]);
SavedWords[1] = XBram_In32(Addr[1]);
for (Width = 1; Width <= 4; Width <<= 1) {
/* Calculate counter max value */
if (InstancePtr->Config.CorrectableCounterBits == 32) {
CounterMax = 0xFFFFFFFF;
} else {
CounterMax =(1 <<
InstancePtr->Config.CorrectableCounterBits) - 1;
}
/* Inject and check all single bit errors */
for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
/* Save counter value */
if (InstancePtr->Config.CorrectableCounterBits > 0) {
CounterValue = RD(CE_CNT_OFFSET);
}
/* Inject single bit error */
InjectErrors(InstancePtr, Addr[WordIndex], Index1,
Index1, Width, &ActualData, &ActualEcc);
/* Check that CE is set */
if (InstancePtr->Config.EccStatusInterruptPresent) {
CHECK(ECC_STATUS_OFFSET,
XBRAM_IR_CE_MASK, Result);
}
/* Check that address, data, ECC are correct */
if (InstancePtr->Config.CorrectableFailingRegisters) {
CHECK(CE_FFA_0_OFFSET, Addr[WordIndex], Result);
}
/* Checks are only for LMB BRAM */
if (InstancePtr->Config.CorrectableFailingDataRegs) {
CHECK(CE_FFD_0_OFFSET, ActualData, Result);
CHECK(CE_FFE_0_OFFSET, ActualEcc, Result);
}
/* Check that counter has incremented */
if (InstancePtr->Config.CorrectableCounterBits > 0 &&
CounterValue < CounterMax) {
CHECK(CE_CNT_OFFSET,
CounterValue + 1, Result);
}
/* Restore correct data in the used word */
XBram_Out32(Addr[WordIndex], SavedWords[WordIndex]);
/* Allow interrupts to occur */
/* Clear status register */
if (InstancePtr->Config.EccStatusInterruptPresent) {
WR(ECC_EN_IRQ_OFFSET, IntMask);
WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
WR(ECC_EN_IRQ_OFFSET, 0);
}
/* Switch to the other word */
WordIndex = WordIndex ^ 1;
if (Result != XST_SUCCESS) break;
}
if (Result != XST_SUCCESS) {
return XST_FAILURE;
}
for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
for (Index2 = 0; Index2 < TOTAL_BITS; Index2++) {
if (Index1 != Index2) {
/* Inject double bit error */
InjectErrors(InstancePtr,
Addr[WordIndex],
Index1, Index2, Width,
&ActualData,
&ActualEcc);
/* Check that UE is set */
if (InstancePtr->Config.
EccStatusInterruptPresent) {
CHECK(ECC_STATUS_OFFSET,
XBRAM_IR_UE_MASK,
Result);
}
/* Check that address, data, ECC are correct */
if (InstancePtr->Config.
UncorrectableFailingRegisters) {
CHECK(UE_FFA_0_OFFSET, Addr[WordIndex],
Result);
CHECK(UE_FFD_0_OFFSET,
ActualData, Result);
CHECK(UE_FFE_0_OFFSET, ActualEcc,
Result);
}
/* Restore correct data in the used word */
XBram_Out32(Addr[WordIndex],
SavedWords[WordIndex]);
/* Allow interrupts to occur */
/* Clear status register */
if (InstancePtr->Config.
EccStatusInterruptPresent) {
WR(ECC_EN_IRQ_OFFSET, IntMask);
WR(ECC_STATUS_OFFSET,
XBRAM_IR_ALL_MASK);
WR(ECC_EN_IRQ_OFFSET, 0);
}
/* Switch to the other word */
WordIndex = WordIndex ^ 1;
}
if (Result != XST_SUCCESS) break;
}
if (Result != XST_SUCCESS) break;
}
/* Check saturation of correctable error counter */
if (InstancePtr->Config.CorrectableCounterBits > 0 &&
Result == XST_SUCCESS) {
WR(CE_CNT_OFFSET, CounterMax);
InjectErrors(InstancePtr, Addr[WordIndex], 0, 0,
4, &ActualData, &ActualEcc);
CHECK(CE_CNT_OFFSET, CounterMax, Result);
}
/* Restore the two words used for test */
XBram_Out32(Addr[0], SavedWords[0]);
XBram_Out32(Addr[1], SavedWords[1]);
/* Clear the Status Register. */
if (InstancePtr->Config.EccStatusInterruptPresent) {
WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
}
/* Set Correctable Counter to zero */
if (InstancePtr->Config.CorrectableCounterBits > 0) {
WR(CE_CNT_OFFSET, 0);
}
if (Result != XST_SUCCESS) break;
} /* Width loop */
return (Result);
}
return (XST_SUCCESS);
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/bram_v4_3/src/xbram_sinit.c
+101
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@@ -0,0 +1,101 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram_sinit.c
* @addtogroup bram_v4_2
* @{
*
* The implementation of the XBram driver's static initialzation
* functionality.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 2.01a jvb 10/13/05 First release
* 2.11a mta 03/21/07 Updated to new coding style
* 4.2 ms 08/07/17 Fixed compilation warnings.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xstatus.h"
#include "xparameters.h"
#include "xbram.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
extern XBram_Config XBram_ConfigTable[];
/************************** Function Prototypes *****************************/
/*****************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* ConfigTable contains the configuration info for each device in the system.
*
* @param DeviceId is the device identifier to lookup.
*
* @return
* - A pointer of data type XBram_Config which
* points to the device configuration if DeviceID is found.
* - NULL if DeviceID is not found.
*
* @note None.
*
******************************************************************************/
XBram_Config *XBram_LookupConfig(u16 DeviceId)
{
XBram_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; Index < XPAR_XBRAM_NUM_INSTANCES; Index++) {
if (XBram_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XBram_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/cpu_v2_9/src/Makefile
+27
View File
@@ -0,0 +1,27 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I${INCLUDEDIR}
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
LIBSOURCES=*.c
INCLUDEFILES=xio.h
libs:
echo "Compiling cpu"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OBJECTS)
make clean
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}
datalink814_sp/bsp/microblaze_ps/libsrc/cpu_v2_9/src/fsl.h
+168
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@@ -0,0 +1,168 @@
/******************************************************************************
*
* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file fsl.h
* @addtogroup cpu_v2_9
* @{
*
* This file contains macros for interfacing to the Fast Simplex Link (FSL)
* interface..
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 06/20/07 Initial version, moved over from bsp area
* 1.11c ecm 08/26/08 Fixed the missing 'FSL_DEFAULT' define that was causing
* assembly errors.
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _FSL_H
#define _FSL_H
/***************************** Include Files *********************************/
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/* if these have not been defined already, define here */
#ifndef stringify
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
#endif /* stringify */
/* Extended FSL macros. These now replace all of the previous FSL macros */
#define FSL_DEFAULT
#define FSL_NONBLOCKING n
#define FSL_EXCEPTION e
#define FSL_CONTROL c
#define FSL_ATOMIC a
#define FSL_NONBLOCKING_EXCEPTION ne
#define FSL_NONBLOCKING_CONTROL nc
#define FSL_NONBLOCKING_ATOMIC na
#define FSL_EXCEPTION_CONTROL ec
#define FSL_EXCEPTION_ATOMIC ea
#define FSL_CONTROL_ATOMIC ca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
#define FSL_EXCEPTION_CONTROL_ATOMIC eca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
/* if the mb_interface.h file has been included already, the following are not needed and will not be defined */
/* Legacy FSL Access Macros */
#ifndef getfsl
/* Blocking Data Read and Write to FSL no. id */
#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Data Read and Write to FSL no. id */
#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
/* Blocking Control Read and Write to FSL no. id */
#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Control Read and Write to FSL no. id */
#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
/* Polling versions of FSL access macros. This makes the FSL access interruptible */
#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
/* FSL valid and error check macros. */
#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
"andi\t%0,%0,0x10" : "=d" (error))
#endif /* legacy FSL defines */
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* _FSL_H */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/cpu_v2_9/src/xio.c
+226
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/******************************************************************************
*
* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xio.c
* @addtogroup cpu_v2_9
* @{
*
* Contains I/O functions for memory-mapped or non-memory-mapped I/O
* architectures. These functions encapsulate generic CPU I/O requirements.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
* and bumped version to 1.01.a.
* 2.11a mta 03/21/07 Updated to new coding style.
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent code.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xio.h"
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Performs a 16-bit endian converion.
*
* @param Source contains the value to be converted.
* @param DestPtr contains a pointer to the location to put the
* converted value.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_EndianSwap16(u16 Source, u16 *DestPtr)
{
*DestPtr = (u16) (((Source & 0xFF00) >> 8) | ((Source & 0x00FF) << 8));
}
/*****************************************************************************/
/**
*
* Performs a 32-bit endian converion.
*
* @param Source contains the value to be converted.
* @param DestPtr contains a pointer to the location to put the
* converted value.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_EndianSwap32(u32 Source, u32 *DestPtr)
{
/* get each of the half words from the 32 bit word */
u16 LoWord = (u16) (Source & 0x0000FFFF);
u16 HiWord = (u16) ((Source & 0xFFFF0000) >> 16);
/* byte swap each of the 16 bit half words */
LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8));
HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8));
/* swap the half words before returning the value */
*DestPtr = (u32) ((LoWord << 16) | HiWord);
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the byte-swapped value read from that
* address.
*
* @param InAddress contains the address to perform the input
* operation at.
*
* @return The byte-swapped value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u16 XIo_InSwap16(XIo_Address InAddress)
{
u16 InData;
/* get the data then swap it */
InData = XIo_In16(InAddress);
return (u16) (((InData & 0xFF00) >> 8) | ((InData & 0x00FF) << 8));
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the byte-swapped value read from that
* address.
*
* @param InAddress contains the address to perform the input
* operation at.
*
* @return The byte-swapped value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u32 XIo_InSwap32(XIo_Address InAddress)
{
u32 InData;
u32 SwapData;
/* get the data then swap it */
InData = XIo_In32(InAddress);
XIo_EndianSwap32(InData, &SwapData);
return SwapData;
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified value to the the specified address. The value is byte-swapped
* before being written.
*
* @param OutAddress contains the address to perform the output
* operation at.
* @param Value contains the value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_OutSwap16(XIo_Address OutAddress, u16 Value)
{
u16 OutData;
/* swap the data then output it */
OutData = (u16) (((Value & 0xFF00) >> 8) | ((Value & 0x00FF) << 8));
XIo_Out16(OutAddress, OutData);
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address. The value is byte-swapped
* before being written.
*
* @param OutAddress contains the address at which the
* output operation has to be done.
* @param Value contains the value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_OutSwap32(XIo_Address OutAddress, u32 Value)
{
u32 OutData;
/* swap the data then output it */
XIo_EndianSwap32(Value, &OutData);
XIo_Out32(OutAddress, OutData);
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/cpu_v2_9/src/xio.h
+269
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/******************************************************************************
*
* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xio.h
* @addtogroup cpu_v2_9
* @{
* @details
*
* This file contains the interface for the XIo component, which encapsulates
* the Input/Output functions for processors that do not require any special
* I/O handling.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
* 1.00a xd 11/04/04 Improved support for doxygen
* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
* and bumped version to 1.01.a.
* 1.11a mta 03/21/07 Updated to new coding style.
* 1.11b va 04/17/08 Updated Tcl for better CORE_CLOCK_FREQ_HZ definition
* 1.11a sdm 03/12/09 Updated Tcl to define correct value for CORE_CLOCK_FREQ_HZ
* (CR #502010)
* 1.13a sdm 03/12/09 Updated the Tcl to pull appropriate libraries for Little
* Endian Microblaze
* 2.0 adk 19/12/13 Updated as per the New Tcl API's
* 2.1 bss 04/14/14 Updated tcl to copy libgloss.a and libgcc.a libraries
* 2.1 bss 04/29/14 Updated to copy libgloss.a if exists otherwise libxil.a
* CR#794205
* 2.2 bss 08/04/14 Updated driver tcl to add protection macros for
* xparameters.h (CR#802257).
* 2.3 sk 12/15/14 Updated mdd file to delete �ffunction-sections &
* -fdata-sections flags from extra compiler flags CR#838648
* Changed default os to latest version in mdd file.
* 2.4 nsk 11/05/15 Updated generate and post_generate procs in driver tcl
* not to generate cpu macros, when microblaze is connected
* as one of the streaming slaves to itself. CR#876604
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent items (memory-mapped or
* non-memory-mapped I/O).
*
******************************************************************************/
#ifndef XIO_H /* prevent circular inclusions */
#define XIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* Typedef for an I/O address. Typically correlates to the width of the
* address bus.
*/
typedef u32 XIo_Address;
/***************** Macros (Inline Functions) Definitions *********************/
/*
* The following macros allow optimized I/O operations for memory mapped I/O.
* It should be noted that macros cannot be used if synchronization of the I/O
* operation is needed as it will likely break some code.
*/
/*****************************************************************************/
/**
*
* Performs an input operation for an 8-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In8(InputPtr) (*(volatile u8 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In16(InputPtr) (*(volatile u16 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In32(InputPtr) (*(volatile u32 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an output operation for an 8-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out8(OutputPtr, Value) \
(*(volatile u8 *)((OutputPtr)) = (Value))
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out16(OutputPtr, Value) \
(*(volatile u16 *)((OutputPtr)) = (Value))
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out32(OutputPtr, Value) \
(*(volatile u32 *)((OutputPtr)) = (Value))
/* The following macros allow the software to be transportable across
* processors which use big or little endian memory models.
*
* Defined first is a no-op endian conversion macro. This macro is not to
* be used directly by software. Instead, the XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX macros below are to be used to allow the endian
* conversion to only be performed when necessary
*/
#define XIo_EndianNoop(Source, DestPtr) (*DestPtr = Source)
#ifdef XLITTLE_ENDIAN
#define XIo_ToLittleEndian16 XIo_EndianNoop
#define XIo_ToLittleEndian32 XIo_EndianNoop
#define XIo_FromLittleEndian16 XIo_EndianNoop
#define XIo_FromLittleEndian32 XIo_EndianNoop
#define XIo_ToBigEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToBigEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromBigEndian16 XIo_ToBigEndian16
#define XIo_FromBigEndian32 XIo_ToBigEndian32
#else
#define XIo_ToLittleEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToLittleEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromLittleEndian16 XIo_ToLittleEndian16
#define XIo_FromLittleEndian32 XIo_ToLittleEndian32
#define XIo_ToBigEndian16 XIo_EndianNoop
#define XIo_ToBigEndian32 XIo_EndianNoop
#define XIo_FromBigEndian16 XIo_EndianNoop
#define XIo_FromBigEndian32 XIo_EndianNoop
#endif
/************************** Function Prototypes ******************************/
/* The following functions allow the software to be transportable across
* processors which use big or little endian memory models. These functions
* should not be directly called, but the macros XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX should be used to allow the endian conversion to only
* be performed when necessary.
*/
void XIo_EndianSwap16(u16 Source, u16 *DestPtr);
void XIo_EndianSwap32(u32 Source, u32 *DestPtr);
/* The following functions handle IO addresses where data must be swapped
* They cannot be implemented as macros
*/
u16 XIo_InSwap16(XIo_Address InAddress);
u32 XIo_InSwap32(XIo_Address InAddress);
void XIo_OutSwap16(XIo_Address OutAddress, u16 Value);
void XIo_OutSwap32(XIo_Address OutAddress, u32 Value);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/gpio_v4_4/src/Makefile
+40
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@@ -0,0 +1,40 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES:=*.c
INCLUDEFILES:=*.h
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs: banner xgpio_libs clean
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling gpio"
xgpio_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: xgpio_includes
xgpio_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}
datalink814_sp/bsp/microblaze_ps/libsrc/gpio_v4_4/src/xgpio.c
+251
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@@ -0,0 +1,251 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio.c
* @addtogroup gpio_v4_4
* @{
*
* The implementation of the XGpio driver's basic functionality. See xgpio.h
* for more information about the driver.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
* 2.01a jvb 12/13/05 Changed Initialize() into CfgInitialize(), and made
* CfgInitialize() take a pointer to a config structure
* instead of a device id. Moved Initialize() into
* xgpio_sinit.c, and had Initialize() call CfgInitialize()
* after it retrieved the config structure using the device
* id. Removed include of xparameters.h along with any
* dependencies on xparameters.h and the _g.c config table.
* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the
* macros to remove _m from the name.
* 4.1 lks 11/18/15 Clean up of the comments in the code and
* removed support for DCR bridge
* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
* adding 64 bit support. CR# 867425.
* Changed the prototype of XGpio_CfgInitialize API.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
#include "xstatus.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Initialize the XGpio instance provided by the caller based on the
* given configuration data.
*
* Nothing is done except to initialize the InstancePtr.
*
* @param InstancePtr is a pointer to an XGpio instance. The memory the
* pointer references must be pre-allocated by the caller. Further
* calls to manipulate the driver through the XGpio API must be
* made with this pointer.
* @param Config is a reference to a structure containing information
* about a specific GPIO device. This function initializes an
* InstancePtr object for a specific device specified by the
* contents of Config. This function can initialize multiple
* instance objects with the use of multiple calls giving different
* Config information on each call.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. The caller is responsible for keeping the address
* mapping from EffectiveAddr to the device physical base address
* unchanged once this function is invoked. Unexpected errors may
* occur if the address mapping changes after this function is
* called. If address translation is not used, use
* Config->BaseAddress for this parameters, passing the physical
* address instead.
*
* @return
* - XST_SUCCESS if the initialization is successfull.
*
* @note None.
*
*****************************************************************************/
int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config,
UINTPTR EffectiveAddr)
{
/* Assert arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Set some default values. */
InstancePtr->BaseAddress = EffectiveAddr;
InstancePtr->InterruptPresent = Config->InterruptPresent;
InstancePtr->IsDual = Config->IsDual;
/*
* Indicate the instance is now ready to use, initialized without error
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return (XST_SUCCESS);
}
/****************************************************************************/
/**
* Set the input/output direction of all discrete signals for the specified
* GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param DirectionMask is a bitmask specifying which discretes are input
* and which are output. Bits set to 0 are output and bits set to 1
* are input.
*
* @return None.
*
* @note The hardware must be built for dual channels if this function
* is used with any channel other than 1. If it is not, this
* function will assert.
*
*****************************************************************************/
void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
u32 DirectionMask)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
XGpio_WriteReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET,
DirectionMask);
}
/****************************************************************************/
/**
* Get the input/output direction of all discrete signals for the specified
* GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
*
* @return Bitmask specifying which discretes are input and
* which are output. Bits set to 0 are output and bits set to 1 are
* input.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
*****************************************************************************/
u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->IsDual == TRUE)));
return XGpio_ReadReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET);
}
/****************************************************************************/
/**
* Read state of discretes for the specified GPIO channnel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
*
* @return Current copy of the discretes register.
*
* @note The hardware must be built for dual channels if this function
* is used with any channel other than 1. If it is not, this
* function will assert.
*
*****************************************************************************/
u32 XGpio_DiscreteRead(XGpio * InstancePtr, unsigned Channel)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
return XGpio_ReadReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) +
XGPIO_DATA_OFFSET);
}
/****************************************************************************/
/**
* Write to discretes register for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Data is the value to be written to the discretes register.
*
* @return None.
*
* @note The hardware must be built for dual channels if this function
* is used with any channel other than 1. If it is not, this
* function will assert. See also XGpio_DiscreteSet() and
* XGpio_DiscreteClear().
*
*****************************************************************************/
void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
XGpio_WriteReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
Data);
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/gpio_v4_4/src/xgpio.h
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/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio.h
* @addtogroup gpio_v4_4
* @{
* @details
*
* This file contains the software API definition of the Xilinx General Purpose
* I/O (XGpio) device driver.
*
* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
* contains the following general features:
* - Support for up to 32 I/O discretes for each channel (64 bits total).
* - Each of the discretes can be configured for input or output.
* - Configurable support for dual channels and interrupt generation.
*
* The driver provides interrupt management functions. Implementation of
* interrupt handlers is left to the user. Refer to the provided interrupt
* example in the examples directory for details.
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* <b>Initialization & Configuration</b>
*
* The XGpio_Config structure is used by the driver to configure itself. This
* configuration structure is typically created by the tool-chain based on HW
* build properties.
*
* To support multiple runtime loading and initialization strategies employed
* by various operating systems, the driver instance can be initialized in one
* of the following ways:
*
* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
* configuration structure created by the tool-chain based on an ID provided
* by the tool-chain.
*
* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* @note
*
* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
* the unused bits from registers are read as zero and written as don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/13/02 First release
* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
* 2.01a jvb 12/14/05 I separated dependency on the static config table and
* xparameters.h from the driver initialization by moving
* _Initialize and _LookupConfig to _sinit.c. I also added
* the new _CfgInitialize routine.
* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
* to properly update the Interrupt Enable register
* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
* file
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
* XGpio_mSetDataDirection, XGpio_mGetDataReg and
* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
* XGpio_ReadReg to achieve the same functionality.
* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
* xparameters.h. CR#698589
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
* 4.1 lks 11/18/15 Updated to use cannonical xparameters in examples and
* clean up of the comments, removed support for DCR bridge
* and removed xgpio_intr_example for CR 900381
* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
* adding 64 bit support. CR# 867425.
* Changed the prototype of XGpio_CfgInitialize API.
* 4.3 sk 09/29/16 Modified the example to make it work when LED_bits are
* configured as an output. CR# 958644
* ms 01/23/17 Added xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 4.4 sne 04/25/19 Updated Makefile for IAR compier (CR-1029421).
*
* </pre>
*****************************************************************************/
#ifndef XGPIO_H /* prevent circular inclusions */
#define XGPIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xgpio_l.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /* Unique ID of device */
UINTPTR BaseAddress; /* Device base address */
int InterruptPresent; /* Are interrupts supported in h/w */
int IsDual; /* Are 2 channels supported in h/w */
} XGpio_Config;
/**
* The XGpio driver instance data. The user is required to allocate a
* variable of this type for every GPIO device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
UINTPTR BaseAddress; /* Device base address */
u32 IsReady; /* Device is initialized and ready */
int InterruptPresent; /* Are interrupts supported in h/w */
int IsDual; /* Are 2 channels supported in h/w */
} XGpio;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
/*
* Initialization functions in xgpio_sinit.c
*/
int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
/*
* API Basic functions implemented in xgpio.c
*/
int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
UINTPTR EffectiveAddr);
void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
u32 DirectionMask);
u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
/*
* API Functions implemented in xgpio_extra.c
*/
void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
/*
* API Functions implemented in xgpio_selftest.c
*/
int XGpio_SelfTest(XGpio *InstancePtr);
/*
* API Functions implemented in xgpio_intr.c
*/
void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/gpio_v4_4/src/xgpio_extra.c
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/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio_extra.c
* @addtogroup gpio_v4_4
* @{
*
* The implementation of the XGpio driver's advanced discrete functions.
* See xgpio.h for more information about the driver.
*
* @note
*
* These APIs can only be used if the GPIO_IO ports in the IP are used for
* connecting to the external output ports.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
* 2.11a mta 03/21/07 Updated to new coding style
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
* to XGpio_ReadReg.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
#include "xgpio_i.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Set output discrete(s) to logic 1 for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Mask is the set of bits that will be set to 1 in the discrete
* data register. All other bits in the data register are
* unaffected.
*
* @return None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
* This API can only be used if the GPIO_IO ports in the IP are used for
* connecting to the external output ports.
*
*****************************************************************************/
void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask)
{
u32 Current;
unsigned DataOffset;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
/* Calculate the offset to the data register of the GPIO */
DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
/*
* Read the contents of the data register, merge in Mask and write
* back results
*/
Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
Current |= Mask;
XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
}
/****************************************************************************/
/**
* Set output discrete(s) to logic 0 for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Mask is the set of bits that will be set to 0 in the discrete
* data register. All other bits in the data register are
* unaffected.
*
* @return None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
* This API can only be used if the GPIO_IO ports in the IP are used for
* connecting to the external output ports.
*
*****************************************************************************/
void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask)
{
u32 Current;
unsigned DataOffset;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
/* Calculate the offset to the data register of the GPIO */
DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
/*
* Read the contents of the data register, merge in Mask and write
* back results
*/
Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
Current &= ~Mask;
XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/gpio_v4_4/src/xgpio_g.c
+65
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1.3
* DO NOT EDIT.
*
* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xgpio.h"
/*
* The configuration table for devices
*/
XGpio_Config XGpio_ConfigTable[XPAR_XGPIO_NUM_INSTANCES] =
{
{
XPAR_AXI_GPIO_DEVICE_ID,
XPAR_AXI_GPIO_BASEADDR,
XPAR_AXI_GPIO_INTERRUPT_PRESENT,
XPAR_AXI_GPIO_IS_DUAL
},
{
XPAR_STATUS_GPIO_I_DEVICE_ID,
XPAR_STATUS_GPIO_I_BASEADDR,
XPAR_STATUS_GPIO_I_INTERRUPT_PRESENT,
XPAR_STATUS_GPIO_I_IS_DUAL
},
{
XPAR_STATUS_GPIO_O_DEVICE_ID,
XPAR_STATUS_GPIO_O_BASEADDR,
XPAR_STATUS_GPIO_O_INTERRUPT_PRESENT,
XPAR_STATUS_GPIO_O_IS_DUAL
}
};
datalink814_sp/bsp/microblaze_ps/libsrc/gpio_v4_4/src/xgpio_i.h
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/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************/
/**
* @file xgpio_i.h
* @addtogroup gpio_v4_3
* @{
*
* This header file contains internal identifiers, which are those shared
* between the files of the driver. It is intended for internal use only.
*
* NOTES:
*
* None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/13/02 First release
* 2.11a mta 03/21/07 Updated to new coding style
* </pre>
******************************************************************************/
#ifndef XGPIO_I_H /* prevent circular inclusions */
#define XGPIO_I_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xgpio.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions ****************************/
extern XGpio_Config XGpio_ConfigTable[];
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/gpio_v4_4/src/xgpio_intr.c
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/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio_intr.c
* @addtogroup gpio_v4_4
* @{
*
* Implements GPIO interrupt processing functions for the XGpio driver.
* See xgpio.h for more information about the driver.
*
* The functions in this file require the hardware device to be built with
* interrupt capabilities. The functions will assert if called using hardware
* that does not have interrupt capabilities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 2.00a jhl 11/26/03 Initial release
* 2.11a mta 03/21/07 Updated to new coding style
* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
* to properly update the Interrupt Enable register
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
* to XGpio_ReadReg.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Enable the interrupt output signal. Interrupts enabled through
* XGpio_InterruptEnable() will not be passed through until the global enable
* bit is set by this function. This function is designed to allow all
* interrupts (both channels) to be enabled easily for exiting a critical
* section. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpio_InterruptGlobalEnable(XGpio *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET,
XGPIO_GIE_GINTR_ENABLE_MASK);
}
/****************************************************************************/
/**
* Disable the interrupt output signal. Interrupts enabled through
* XGpio_InterruptEnable() will no longer be passed through until the global
* enable bit is set by XGpio_InterruptGlobalEnable(). This function is
* designed to allow all interrupts (both channels) to be disabled easily for
* entering a critical section. This function will assert if the hardware
* device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpio_InterruptGlobalDisable(XGpio *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, 0x0);
}
/****************************************************************************/
/**
* Enable interrupts. The global interrupt must also be enabled by calling
* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
* assert if the hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
* @param Mask is the mask to enable. Bit positions of 1 are enabled.
* This mask is formed by OR'ing bits from XGPIO_IR* bits which
* are contained in xgpio_l.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
/*
* Read the interrupt enable register and only enable the specified
* interrupts without disabling or enabling any others.
*/
Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
Register | Mask);
}
/****************************************************************************/
/**
* Disable interrupts. This function allows specific interrupts for each
* channel to be disabled. This function will assert if the hardware device
* has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
* @param Mask is the mask to disable. Bits set to 1 are disabled. This
* mask is formed by OR'ing bits from XGPIO_IR* bits which are
* contained in xgpio_l.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
/*
* Read the interrupt enable register and only disable the specified
* interrupts without enabling or disabling any others.
*/
Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
Register & (~Mask));
}
/****************************************************************************/
/**
* Clear pending interrupts with the provided mask. This function should be
* called after the software has serviced the interrupts that are pending.
* This function will assert if the hardware device has not been built with
* interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
* @param Mask is the mask to clear pending interrupts for. Bit positions
* of 1 are cleared. This mask is formed by OR'ing bits from
* XGPIO_IR* bits which are contained in xgpio_l.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpio_InterruptClear(XGpio * InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
/*
* Read the interrupt status register and only clear the interrupts
* that are specified without affecting any others. Since the register
* is a toggle on write, make sure any bits to be written are already
* set.
*/
Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET,
Register & Mask);
}
/****************************************************************************/
/**
* Returns the interrupt enable mask. This function will assert if the
* hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
*
* @return A mask of bits made from XGPIO_IR* bits which are contained in
* xgpio_l.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
u32 XGpio_InterruptGetEnabled(XGpio * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
}
/****************************************************************************/
/**
* Returns the status of interrupt signals. Any bit in the mask set to 1
* indicates that the channel associated with the bit has asserted an interrupt
* condition. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
*
* @return A pointer to a mask of bits made from XGPIO_IR* bits which are
* contained in xgpio_l.h.
*
* @note
*
* The interrupt status indicates the status of the device irregardless if
* the interrupts from the devices have been enabled or not through
* XGpio_InterruptEnable().
*
*****************************************************************************/
u32 XGpio_InterruptGetStatus(XGpio * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/gpio_v4_4/src/xgpio_l.h
+189
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@@ -0,0 +1,189 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpio_l.h
* @addtogroup gpio_v4_4
* @{
*
* This header file contains identifiers and driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
* The macros that are available in this file use a multiply to calculate the
* addresses of registers. The user can control whether that multiply is done
* at run time or at compile time. A constant passed as the channel parameter
* will cause the multiply to be done at compile time. A variable passed as the
* channel parameter will cause it to occur at run time.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a jhl 04/24/02 First release of low level driver
* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
* change required the functions to be changed such that
* the interface is not compatible with previous versions.
* See the examples in the example directory for macros
* to help compile an application that was designed for
* previous versions of the driver. The interrupt registers
* are accessible using the ReadReg and WriteReg macros and
* a channel parameter was added to the other macros.
* 2.11a mta 03/21/07 Updated to new coding style
* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
* XGpio_mReadReg to XGpio_ReadReg.
* Removed the macros XGpio_mSetDataDirection,
* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
* same functionality.
* 4.1 lks 11/18/15 Removed support for DCR bridge
* </pre>
*
******************************************************************************/
#ifndef XGPIO_L_H /* prevent circular inclusions */
#define XGPIO_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Registers
*
* Register offsets for this device.
* @{
*/
#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
/* @} */
/* The following constant describes the offset of each channels data and
* tristate register from the base address.
*/
#define XGPIO_CHAN_OFFSET 8
/** @name Interrupt Status and Enable Register bitmaps and masks
*
* Bit definitions for the interrupt status register and interrupt enable
* registers.
* @{
*/
#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
/*@}*/
/** @name Global Interrupt Enable Register bitmaps and masks
*
* Bit definitions for the Global Interrupt Enable register
* @{
*/
#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XGpio_In32 Xil_In32
#define XGpio_Out32 Xil_Out32
/****************************************************************************/
/**
*
* Write a value to a GPIO register. A 32 bit write is performed. If the
* GPIO core is implemented in a smaller width, only the least significant data
* is written.
*
* @param BaseAddress is the base address of the GPIO device.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note C-style signature:
* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
****************************************************************************/
#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/****************************************************************************/
/**
*
* Read a value from a GPIO register. A 32 bit read is performed. If the
* GPIO core is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the GPIO device.
* @param RegOffset is the register offset from the base to read from.
*
* @return Data read from the register.
*
* @note C-style signature:
* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
*
****************************************************************************/
#define XGpio_ReadReg(BaseAddress, RegOffset) \
XGpio_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/gpio_v4_4/src/xgpio_selftest.c
+106
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@@ -0,0 +1,106 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio_selftest.c
* @addtogroup gpio_v4_4
* @{
*
* The implementation of the XGpio driver's self test function.
* See xgpio.h for more information about the driver.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 01/13/04 Addition of dual channels and interrupts.
* 2.11a mta 03/21/07 Updated to new coding style
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/******************************************************************************/
/**
* Run a self-test on the driver/device. This function does a minimal test
* in which the data register is read. It only does a read without any kind
* of test because the hardware has been parameterized such that it may be only
* an input such that the state of the inputs won't be known.
*
* All other hardware features of the device are not guaranteed to be in the
* hardware since they are parameterizable.
*
*
* @param InstancePtr is a pointer to the XGpio instance to be worked on.
* This parameter must have been previously initialized with
* XGpio_Initialize().
*
* @return XST_SUCCESS always. If the GPIO device was not present in the
* hardware a bus error could be generated. Other indicators of a
* bus error, such as registers in bridges or buses, may be
* necessary to determine if this function caused a bus error.
*
* @note None.
*
******************************************************************************/
int XGpio_SelfTest(XGpio * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Read from the data register of channel 1 which is always guaranteed
* to be in the hardware device. Since the data may be configured as
* all inputs, there is not way to guarantee the value read so don't
* test it.
*/
(void) XGpio_DiscreteRead(InstancePtr, 1);
return (XST_SUCCESS);
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/gpio_v4_4/src/xgpio_sinit.c
+155
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@@ -0,0 +1,155 @@
/******************************************************************************
*
* Copyright (C) 2003 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio_sinit.c
* @addtogroup gpio_v4_4
* @{
*
* The implementation of the XGpio driver's static initialzation
* functionality.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 2.01a jvb 10/13/05 First release
* 2.11a mta 03/21/07 Updated to new coding style
* 4.0 sha 07/15/15 Defined macro XPAR_XGPIO_NUM_INSTANCES if not
* defined in xparameters.h
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xstatus.h"
#include "xparameters.h"
#include "xgpio_i.h"
/************************** Constant Definitions ****************************/
#ifndef XPAR_XGPIO_NUM_INSTANCES
#define XPAR_XGPIO_NUM_INSTANCES 0
#endif
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/******************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* ConfigTable contains the configuration info for each device in the system.
*
* @param DeviceId is the device identifier to lookup.
*
* @return
* - A pointer of data type XGpio_Config which points to the
* device configuration if DeviceID is found.
* - NULL if DeviceID is not found.
*
* @note None.
*
******************************************************************************/
XGpio_Config *XGpio_LookupConfig(u16 DeviceId)
{
XGpio_Config *CfgPtr = NULL;
int Index;
for (Index = 0; Index < XPAR_XGPIO_NUM_INSTANCES; Index++) {
if (XGpio_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XGpio_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/****************************************************************************/
/**
* Initialize the XGpio instance provided by the caller based on the
* given DeviceID.
*
* Nothing is done except to initialize the InstancePtr.
*
* @param InstancePtr is a pointer to an XGpio instance. The memory the
* pointer references must be pre-allocated by the caller. Further
* calls to manipulate the instance/driver through the XGpio API
* must be made with this pointer.
* @param DeviceId is the unique id of the device controlled by this XGpio
* instance. Passing in a device id associates the generic XGpio
* instance to a specific device, as chosen by the caller or
* application developer.
*
* @return
* - XST_SUCCESS if the initialization was successfull.
* - XST_DEVICE_NOT_FOUND if the device configuration data was not
* found for a device with the supplied device ID.
*
* @note None.
*
*****************************************************************************/
int XGpio_Initialize(XGpio * InstancePtr, u16 DeviceId)
{
XGpio_Config *ConfigPtr;
/*
* Assert arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Lookup configuration data in the device configuration table.
* Use this configuration info down below when initializing this
* driver.
*/
ConfigPtr = XGpio_LookupConfig(DeviceId);
if (ConfigPtr == (XGpio_Config *) NULL) {
InstancePtr->IsReady = 0;
return (XST_DEVICE_NOT_FOUND);
}
return XGpio_CfgInitialize(InstancePtr, ConfigPtr,
ConfigPtr->BaseAddress);
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/intc_v3_9/src/Makefile
+28
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@@ -0,0 +1,28 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
LEVEL=0
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs:
echo "Compiling intc"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OBJECTS)
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OBJECTS}
datalink814_sp/bsp/microblaze_ps/libsrc/intc_v3_9/src/xintc.c
+1166
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File diff suppressed because it is too large Load Diff
datalink814_sp/bsp/microblaze_ps/libsrc/intc_v3_9/src/xintc.h
+379
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@@ -0,0 +1,379 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc.h
* @addtogroup intc_v3_9
* @{
* @details
*
* The Xilinx interrupt controller driver component. This component supports the
* Xilinx interrupt controller.
*
* The interrupt controller driver uses the idea of priority for the various
* handlers. Priority is an integer within the range of 0 and 31 inclusive with
* 0 being the highest priority interrupt source.
*
* The Xilinx interrupt controller supports the following features:
*
* - specific individual interrupt enabling/disabling
* - specific individual interrupt acknowledging
* - attaching specific callback function to handle interrupt source
* - master enable/disable
* - single callback per interrupt or all pending interrupts handled for
* each interrupt of the processor
*
* The acknowledgement of the interrupt within the interrupt controller is
* selectable, either prior to the device's handler being called or after
* the handler is called. This is necessary to support interrupt signal inputs
* which are either edge or level signals. Edge driven interrupt signals
* require that the interrupt is acknowledged prior to the interrupt being
* serviced in order to prevent the loss of interrupts which are occurring
* extremely close together. A level driven interrupt input signal requires
* the interrupt to acknowledged after servicing the interrupt to ensure that
* the interrupt only generates a single interrupt condition.
*
* Details about connecting the interrupt handler of the driver are contained
* in the source file specific to interrupt processing, xintc_intr.c.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <b>Interrupt Vector Tables</b>
*
* The interrupt vector table for each interrupt controller device is declared
* statically in xintc_g.c within the configuration data for each instance.
* The device ID of the interrupt controller device is used by the driver as a
* direct index into the configuration data table - to retrieve the vector table
* for an instance of the interrupt controller. The user should populate the
* vector table with handlers and callbacks at run-time using the XIntc_Connect()
* and XIntc_Disconnect() functions.
*
* Each vector table entry corresponds to a device that can generate an
* interrupt. Each entry contains an interrupt handler function and an argument
* to be passed to the handler when an interrupt occurs. The tools default this
* argument to the base address of the interrupting device. Note that the
* device driver interrupt handlers given in this file do not take a base
* address as an argument, but instead take a pointer to the driver instance.
* This means that although the table is created statically, the user must still
* use XIntc_Connect() when the interrupt handler takes an argument other than
* the base address. This is only to say that the existence of the static vector
* tables should not mislead the user into thinking they no longer need to
* register/connect interrupt handlers with this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 08/16/01 First release
* 1.00a rpm 01/09/02 Removed the AckLocation argument from XIntc_Connect().
* This information is now internal in xintc_g.c.
* 1.00b jhl 02/13/02 Repartitioned the driver for smaller files
* 1.00b jhl 04/24/02 Made LookupConfig function global and relocated config
* data type
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table. Moved vector
* table and options out of instance structure and into
* the configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed from
* all the macro names/definitions.
* 2.01a sdm 04/27/10 Updated the tcl so that the defintions are generated in
* the xparameters.h to know whether the optional registers
* SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
* This driver doesnot make use of these definitions and does
* not use the optional registers.
* 2.03a hvm 05/24/11 Updated the tcl to generate vector Ids for external
* interrupts. CR565336
* 2.04a bss 01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
* and XIntc_SetNormalIntrMode for setting to normal
* interrupt mode.
* 2.04a asa 03/19/12 Changed the XIntc_Config struct. The order of entries
* declared in the structure now matches with the
* XIntc_ConfigTable generated by the driver tcl.
* 2.05a bss 08/16/12 Updated to support relocatable vectors in Microblaze,
* added IntVectorAddr to XIntc_Config for this.
* Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.06a bss 01/28/13 To support Cascade mode:
* Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
* XIN_INTC_SECONDARY,XIN_INTC_LAST and
* XIN_CONTROLLER_MAX_INTRS macros
* Added NumberofIntrs and IntcType fields in XIntc_Config
* structure.
* Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
* XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
* XIntc_Acknowledge,XIntc_ConnectFastHandler and
* XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
* API in xintc.c
* Modified XIntc_DeviceInterruptHandler,
* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
* XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
* API in xintc_l.c.
* Modified XIntc_SetOptions API in xintc_options.c.
* Modified XIntc_SimulateIntr API in xintc_selftest.c.
* Modified driver tcl:
* to check for Cascade mode and generate XPAR_INTC_TYPE
* for each controller.
* Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
* interrupt sources of all Controllers in Cascade mode.
* 2.07a bss 10/18/13 To support Nested interrupts:
* Modified XIntc_DeviceInterruptHandler API.
* Added XIN_ILR_OFFSET macro in xintc_l.h.
* Modified driver tcl to generate HAS_ILR parameter in
* xparameters.h
* 3.0 bss 01/28/13 Modified xintc.c to initialize IVAR register with
* XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
* CR#765931.
* Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
* correctly(CR#764865).
*
* @note
* For Cascade mode, Interrupt IDs are generated in xparameters.h
* as shown below:
*
* Master/Primary INTC
* ______
* | |-0 Secondary INTC
* | |-. ______
* | |-. | |-32 Last INTC
* | |-. | |-. ______
* |______|<-31------| |-. | |-64
* | |-. | |-.
* |______|<-63-------| |-.
* | |-.
* |______|-95
*
* All driver functions has to be called using DeviceId/
* InstancePtr/BaseAddress of Primary/Master Controller and
* Interrupts IDs generated in xparameters.h only.
* Driver functions takes care of Slave Controllers based on
* Interrupt ID passed. User must not use Interrupt source/ID
* 31 of Primary and Secondary controllers to call driver
* functions.
*
* For nested interrupts, XIntc_DeviceInterruptHandler saves
* microblaze r14 register on entry and restores on exit. This is
* required since compiler does not support nesting. It enables
* Microblaze interrupts after blocking further interrupts from
* the current interrupt number and interrupts below current
* interrupt proirity by writing to Interrupt Level Register of
* INTC on entry. On exit, it disables microblaze interrupts and
* restores ILR register default value(0xFFFFFFFF)back. It is
* recommended to increase STACK_SIZE in linker script for nested
* interrupts.
* 3.0 adk 12/10/13 Updated as per the New Tcl API's
* 3.0 adk 17/02/14 Fixed the CR:771287 Changes are made in the intc
* driver tcl.
* 3.1 adk 8/4/14 Fixed the CR:783248 Changes are made in
* the test-app tcl
* 3.2 bss 4/8/14 Fixed driver tcl to handle external interrupt pins
* correctly (CR#799609).
* 3.3 adk 11/3/14 added generation of C_HAS_ILR parameter to
* xparameters.h.Changes are made in the driver tcl file
* (CR#828046).
* 3.5 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* 3.6 ms 01/23/17 Added xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 3.7 ms 04/18/17 Modified tcl file to add suffix U for macro definitions
* of intc in xparameters.h
* 3.9 adk 19/12/18 If design contains unconnected interrupt pins
* return proper error message(CR#1018878).
* </pre>
*
******************************************************************************/
#ifndef XINTC_H /* prevent circular inclusions */
#define XINTC_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xstatus.h"
#include "xintc_l.h"
/************************** Constant Definitions *****************************/
/**
* @name Configuration options
* These options are used in XIntc_SetOptions() to configure the device.
* @{
*/
/**
* <pre>
* XIN_SVC_SGL_ISR_OPTION Service the highest priority pending interrupt
* and then return.
* XIN_SVC_ALL_ISRS_OPTION Service all of the pending interrupts and then
* return.
* </pre>
*/
#define XIN_SVC_SGL_ISR_OPTION 1UL
#define XIN_SVC_ALL_ISRS_OPTION 2UL
/*@}*/
/**
* @name Start modes
* One of these values is passed to XIntc_Start() to start the device.
* @{
*/
/** Simulation only mode, no hardware interrupts recognized */
#define XIN_SIMULATION_MODE 0
/** Real mode, no simulation allowed, hardware interrupts recognized */
#define XIN_REAL_MODE 1
/*@}*/
/**
* @name Masks to specify Interrupt Controller Mode
* @{
*/
#define XIN_INTC_NOCASCADE 0 /* Normal - No Cascade Mode */
#define XIN_INTC_PRIMARY 1 /* Master/Primary controller */
#define XIN_INTC_SECONDARY 2 /* Secondary Slave Controllers */
#define XIN_INTC_LAST 3 /* Last Slave Controller */
/*@}*/
/**
* @name Mask to specify maximum number of interrupt sources per controller
* @{
*/
#define XIN_CONTROLLER_MAX_INTRS 32 /* Each Controller has 32
interrupt pins */
#define XINTC_STANDARD_VECTOR_ADDRESS_WIDTH 32U
/*@}*/
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress; /**< Register base address */
u32 AckBeforeService; /**< Ack location per interrupt */
int FastIntr; /**< Fast Interrupt enabled */
u32 IntVectorAddr; /**< Interrupt Vector Address */
int NumberofIntrs; /**< Number of Interrupt sources */
u8 VectorAddrWidth; /**< Width of vector address */
u32 Options; /**< Device options */
int IntcType; /**< Intc type 0 - No Cascade Mode
1 - primary instance
2 - secondary instance
3 - last instance */
/** Static vector table of interrupt handlers */
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS];
#else
XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS];
#endif
} XIntc_Config;
/**
* The XIntc driver instance data. The user is required to allocate a
* variable of this type for every intc device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
UINTPTR BaseAddress; /**< Base address of registers */
u32 IsReady; /**< Device is initialized and ready */
u32 IsStarted; /**< Device has been started */
u32 UnhandledInterrupts; /**< Intc Statistics */
XIntc_Config *CfgPtr; /**< Pointer to instance config entry */
} XIntc;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Required functions in xintc.c
*/
int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId);
int XIntc_Start(XIntc * InstancePtr, u8 Mode);
void XIntc_Stop(XIntc * InstancePtr);
int XIntc_Connect(XIntc * InstancePtr, u8 Id,
XInterruptHandler Handler, void *CallBackRef);
void XIntc_Disconnect(XIntc * InstancePtr, u8 Id);
void XIntc_Enable(XIntc * InstancePtr, u8 Id);
void XIntc_Disable(XIntc * InstancePtr, u8 Id);
void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id);
XIntc_Config *XIntc_LookupConfig(u16 DeviceId);
int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
XFastInterruptHandler Handler);
void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id);
/*
* Interrupt functions in xintr_intr.c
*/
void XIntc_VoidInterruptHandler(void);
void XIntc_InterruptHandler(XIntc * InstancePtr);
/*
* Options functions in xintc_options.c
*/
int XIntc_SetOptions(XIntc * InstancePtr, u32 Options);
u32 XIntc_GetOptions(XIntc * InstancePtr);
/*
* Self-test functions in xintc_selftest.c
*/
int XIntc_SelfTest(XIntc * InstancePtr);
int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/intc_v3_9/src/xintc_g.c
+87
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1.3
* DO NOT EDIT.
*
* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xintc.h"
extern void XNullHandler (void *);
/*
* The configuration table for devices
*/
XIntc_Config XIntc_ConfigTable[] =
{
{
XPAR_AXI_INTC_DEVICE_ID,
XPAR_AXI_INTC_BASEADDR,
XPAR_AXI_INTC_KIND_OF_INTR,
XPAR_AXI_INTC_HAS_FAST,
XPAR_AXI_INTC_IVAR_RESET_VALUE,
XPAR_AXI_INTC_NUM_INTR_INPUTS,
XPAR_AXI_INTC_ADDR_WIDTH,
XIN_SVC_SGL_ISR_OPTION,
XPAR_AXI_INTC_TYPE,
{
{
XNullHandler,
(void *) XNULL
},
{
XNullHandler,
(void *) XNULL
},
{
XNullHandler,
(void *) XNULL
},
{
XNullHandler,
(void *) XNULL
},
{
XNullHandler,
(void *) XNULL
},
{
XNullHandler,
(void *) XNULL
}
}
}
};
datalink814_sp/bsp/microblaze_ps/libsrc/intc_v3_9/src/xintc_i.h
+89
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/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_i.h
* @addtogroup intc_v3_9
* @{
*
* This file contains data which is shared between files and internal to the
* XIntc component. It is intended for internal use only.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b jhl 02/06/02 First release
* 1.00b jhl 04/24/02 Moved register definitions to xintc_l.h
* 1.00c rpm 10/17/03 New release. Removed extern of global, single instance
* pointer.
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
* </pre>
*
******************************************************************************/
#ifndef XINTC_I_H /* prevent circular inclusions */
#define XINTC_I_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern u32 XIntc_BitPosMask[];
extern XIntc_Config XIntc_ConfigTable[];
#ifdef __cplusplus
}
#endif
#endif
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/intc_v3_9/src/xintc_intr.c
+172
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@@ -0,0 +1,172 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_intr.c
* @addtogroup intc_v3_9
* @{
*
* This file contains the interrupt processing for the XIntc component which
* is the driver for the Xilinx Interrupt Controller. The interrupt
* processing is partitioned seperately such that users are not required to
* use the provided interrupt processing. This file requires other files of
* the driver to be linked in also.
*
* Two different interrupt handlers are provided for this driver such that the
* user must select the appropriate handler for the application. The first
* interrupt handler, XIntc_VoidInterruptHandler, is provided for systems
* which use only a single interrupt controller or for systems that cannot
* otherwise provide an argument to the XIntc interrupt handler (e.g., the RTOS
* interrupt vector handler may not provide such a facility). The constant
* XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in
* the driver. The second interrupt handler, XIntc_InterruptHandler, uses an
* input argument which is an instance pointer to an interrupt controller driver
* such that multiple interrupt controllers can be supported. This handler
* requires the calling function to pass it the appropriate argument, so another
* level of indirection may be required.
*
* Note that both of these handlers are now only provided for backward
* compatibility. The handler defined in xintc_l.c is the recommended handler.
*
* The interrupt processing may be used by connecting one of the interrupt
* handlers to the interrupt system. These handlers do not save and restore
* the processor context but only handle the processing of the Interrupt
* Controller. The two handlers are provided as working examples. The user is
* encouraged to supply their own interrupt handler when performance tuning is
* deemed necessary.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.00b jhl 02/13/02 First release
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table. Collapse handlers
* to use the XIntc_DeviceInterruptHandler() in xintc_l.c.
* 1.00c rpm 04/09/04 Added conditional compilation around the old handler
* XIntc_VoidInterruptHandler(). This handler will only be
* include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is defined.
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
*
* </pre>
*
* @internal
*
* This driver assumes that the context of the processor has been saved prior to
* the calling of the Interrupt Controller interrupt handler and then restored
* after the handler returns. This requires either the running RTOS to save the
* state of the machine or that a wrapper be used as the destination of the
* interrupt vector to save the state of the processor and restore the state
* after the interrupt handler returns.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xintc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Interrupt handler for the driver used when there can be no argument passed
* to the handler. This function is provided mostly for backward compatibility.
* The user should use XIntc_DeviceInterruptHandler(), defined in xintc_l.c,
* if possible.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @return None.
*
* @note
*
* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
* to be included in the driver compilation.
*
******************************************************************************/
#ifdef XPAR_INTC_SINGLE_DEVICE_ID
void XIntc_VoidInterruptHandler(void)
{
/* Use the single instance to call the main interrupt handler */
XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
}
#endif
/*****************************************************************************/
/**
*
* The interrupt handler for the driver. This function is provided mostly for
* backward compatibility. The user should use XIntc_DeviceInterruptHandler(),
* defined in xintc_l.c when possible and pass the device ID of the interrupt
* controller device as its argument.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIntc_InterruptHandler(XIntc * InstancePtr)
{
/* Assert that the pointer to the instance is valid
*/
Xil_AssertVoid(InstancePtr != NULL);
/* Use the instance's device ID to call the main interrupt handler.
* (the casts are to avoid a compiler warning)
*/
XIntc_DeviceInterruptHandler((void *)
((u32) (InstancePtr->CfgPtr->DeviceId)));
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/intc_v3_9/src/xintc_l.c
+677
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@@ -0,0 +1,677 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_l.c
* @addtogroup intc_v3_9
* @{
*
* This file contains low-level driver functions that can be used to access the
* device. The user should refer to the hardware device specification for more
* details of the device operation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b jhl 04/24/02 First release
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table.
* 1.00c rpm 04/09/04 Added conditional compilation around the old handler
* XIntc_LowLevelInterruptHandler(). This handler will only
* be include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is
* defined.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.10c ecm 07/09/07 Read the ISR after the Acknowledge in the interrupt
* handler to support architectures with posted write bus
* access issues.
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed
* from all the macro definitions.
* 2.04a bss 01/13/12 Removed the unused Register variable for warnings.
* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.06a bss 01/28/13 To support Cascade mode:
* Modified XIntc_DeviceInterruptHandler,
* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
* XIntc_RegisterFastHandler APIs.
* Added XIntc_CascadeHandler API.
* 2.07a bss 10/18/13 Modified XIntc_DeviceInterruptHandler to support
* nested interrupts.
* 3.5 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototypes of LookupConfigByBaseAddress,
* XIntc_SetIntrSvcOption, XIntc_RegisterHandler,
* XIntc_RegisterFastHandler APIs.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
#include "xintc_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static XIntc_Config *LookupConfigByBaseAddress(UINTPTR BaseAddress);
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
static void XIntc_CascadeHandler(void *DeviceId);
#endif
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* This is the interrupt handler for the driver interface provided in this file
* when there can be no argument passed to the handler. In this case, we just
* use the globally defined device ID for the interrupt controller. This function
* is provided mostly for backward compatibility. The user should use
* XIntc_DeviceInterruptHandler() if possible.
*
* This function does not support multiple interrupt controller instances to be
* handled.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @return None.
*
* @note
*
* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
* to be included in the driver compilation.
*
******************************************************************************/
#ifdef XPAR_INTC_SINGLE_DEVICE_ID
void XIntc_LowLevelInterruptHandler(void)
{
/*
* A level of indirection here because the interrupt handler used with
* the driver interface given in this file needs to remain void - no
* arguments. So we need the globally defined device ID of THE
* interrupt controller.
*/
XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
}
#endif
/*****************************************************************************/
/**
*
* This function is the primary interrupt handler for the driver. It must be
* connected to the interrupt source such that is called when an interrupt of
* the interrupt controller is active. It will resolve which interrupts are
* active and enabled and call the appropriate interrupt handler. It uses
* the AckBeforeService flag in the configuration data to determine when to
* acknowledge the interrupt. Highest priority interrupts are serviced first.
* This function assumes that an interrupt vector table has been previously
* initialized.It does not verify that entries in the table are valid before
* calling an interrupt handler. In Cascade mode this function calls
* XIntc_CascadeHandler to handle interrupts of Master and Slave controllers.
* This functions also handles interrupts nesting by saving and restoring link
* register of Microblaze and Interrupt Level register of interrupt controller
* properly.
* @param DeviceId is the zero-based device ID defined in xparameters.h
* of the interrupting interrupt controller. It is used as a direct
* index into the configuration data, which contains the vector
* table for the interrupt controller. Note that even though the
* argument is a void pointer, the value is not a pointer but the
* actual device ID. The void pointer type is necessary to meet
* the XInterruptHandler typedef for interrupt handlers.
*
* @return None.
*
* @note For nested interrupts, this function saves microblaze r14
* register on entry and restores on exit. This is required since
* compiler does not support nesting. This function enables
* Microblaze interrupts after blocking further interrupts
* from the current interrupt number and interrupts below current
* interrupt proirity by writing to Interrupt Level Register of
* INTC on entry. On exit, it disables microblaze interrupts and
* restores ILR register default value(0xFFFFFFFF)back. It is
* recommended to increase STACK_SIZE in linker script for nested
* interrupts.
*
******************************************************************************/
void XIntc_DeviceInterruptHandler(void *DeviceId)
{
u32 IntrStatus;
u32 IntrMask = 1;
int IntrNumber;
XIntc_Config *CfgPtr;
u32 Imr;
/* Get the configuration data using the device ID */
CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
XIntc_CascadeHandler(DeviceId);
}
else
#endif
{ /* This extra brace is required for compilation in Cascade Mode */
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
volatile u32 R14_register;
/* Save r14 register */
R14_register = mfgpr(r14);
#endif
volatile u32 ILR_reg;
/* Save ILR register */
ILR_reg = Xil_In32(CfgPtr->BaseAddress + XIN_ILR_OFFSET);
#endif
/* Get the interrupts that are waiting to be serviced */
IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/* Mask the Fast Interrupts */
if (CfgPtr->FastIntr == TRUE) {
Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
IntrStatus &= ~Imr;
}
/* Service each interrupt that is active and enabled by
* checking each bit in the register from LSB to MSB which
* corresponds to an interrupt input signal
*/
for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs;
IntrNumber++) {
if (IntrStatus & 1) {
XIntc_VectorTableEntry *TablePtr;
#if XPAR_XINTC_HAS_ILR == TRUE
/* Write to ILR the current interrupt
* number
*/
Xil_Out32(CfgPtr->BaseAddress +
XIN_ILR_OFFSET, IntrNumber);
/* Read back ILR to ensure the value
* has been updated and it is safe to
* enable interrupts
*/
Xil_In32(CfgPtr->BaseAddress +
XIN_ILR_OFFSET);
/* Enable interrupts */
Xil_ExceptionEnable();
#endif
/* If the interrupt has been setup to
* acknowledge it before servicing the
* interrupt, then ack it */
if (CfgPtr->AckBeforeService & IntrMask) {
XIntc_AckIntr(CfgPtr->BaseAddress,
IntrMask);
}
/* The interrupt is active and enabled, call
* the interrupt handler that was setup with
* the specified parameter
*/
TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
TablePtr->Handler(TablePtr->CallBackRef);
/* If the interrupt has been setup to
* acknowledge it after it has been serviced
* then ack it
*/
if ((CfgPtr->AckBeforeService &
IntrMask) == 0) {
XIntc_AckIntr(CfgPtr->BaseAddress,
IntrMask);
}
#if XPAR_XINTC_HAS_ILR == TRUE
/* Disable interrupts */
Xil_ExceptionDisable();
/* Restore ILR */
Xil_Out32(CfgPtr->BaseAddress + XIN_ILR_OFFSET,
ILR_reg);
#endif
/*
* Read the ISR again to handle architectures
* with posted write bus access issues.
*/
(void) XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/*
* If only the highest priority interrupt is to
* be serviced, exit loop and return after
* servicing
* the interrupt
*/
if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
/* Restore r14 */
mtgpr(r14, R14_register);
#endif
#endif
return;
}
}
/* Move to the next interrupt to check */
IntrMask <<= 1;
IntrStatus >>= 1;
/* If there are no other bits set indicating that all
* interrupts have been serviced, then exit the loop
*/
if (IntrStatus == 0) {
break;
}
}
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
/* Restore r14 */
mtgpr(r14, R14_register);
#endif
#endif
}
}
/*****************************************************************************/
/**
*
* Set the interrupt service option, which can configure the driver so that it
* services only a single interrupt at a time when an interrupt occurs, or
* services all pending interrupts when an interrupt occurs. The default
* behavior when using the driver interface given in xintc.h file is to service
* only a single interrupt, whereas the default behavior when using the driver
* interface given in this file is to service all outstanding interrupts when an
* interrupt occurs. In Cascade mode same Option is set to Slave controllers.
*
* @param BaseAddress is the unique identifier for a device.
* @param Option is XIN_SVC_SGL_ISR_OPTION if you want only a single
* interrupt serviced when an interrupt occurs, or
* XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts
* serviced when an interrupt occurs.
*
* @return None.
*
* @note
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIntc_SetIntrSvcOption(UINTPTR BaseAddress, int Option)
{
XIntc_Config *CfgPtr;
CfgPtr = LookupConfigByBaseAddress(BaseAddress);
if (CfgPtr != NULL) {
CfgPtr->Options = Option;
/* If Cascade mode set the option for all Slaves */
if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
int Index;
for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
Index++) {
CfgPtr = XIntc_LookupConfig(Index);
CfgPtr->Options = Option;
}
}
}
}
/*****************************************************************************/
/**
*
* Register a handler function for a specific interrupt ID. The vector table
* of the interrupt controller is updated, overwriting any previous handler.
* The handler function will be called when an interrupt occurs for the given
* interrupt ID.
*
* This function can also be used to remove a handler from the vector table
* by passing in the XIntc_DefaultHandler() as the handler and NULL as the
* callback reference.
* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
* Controller
*
* @param BaseAddress is the base address of the interrupt controller
* whose vector table will be modified.
* @param InterruptId is the interrupt ID to be associated with the input
* handler.
* @param Handler is the function pointer that will be added to
* the vector table for the given interrupt ID.
* @param CallBackRef is the argument that will be passed to the new
* handler function when it is called. This is user-specific.
*
* @return None.
*
* @note
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIntc_RegisterHandler(UINTPTR BaseAddress, int InterruptId,
XInterruptHandler Handler, void *CallBackRef)
{
XIntc_Config *CfgPtr;
CfgPtr = LookupConfigByBaseAddress(BaseAddress);
if (CfgPtr != NULL) {
if (InterruptId > 31) {
CfgPtr = XIntc_LookupConfig(InterruptId/32);
CfgPtr->HandlerTable[InterruptId%32].Handler = Handler;
CfgPtr->HandlerTable[InterruptId%32].CallBackRef =
CallBackRef;
}
else {
CfgPtr->HandlerTable[InterruptId].Handler = Handler;
CfgPtr->HandlerTable[InterruptId].CallBackRef =
CallBackRef;
}
}
}
/*****************************************************************************/
/**
*
* Looks up the device configuration based on the base address of the device.
* A table contains the configuration info for each device in the system.
*
* @param BaseAddress is the unique identifier for a device.
*
* @return
*
* A pointer to the configuration structure for the specified device, or
* NULL if the device was not found.
*
* @note None.
*
******************************************************************************/
static XIntc_Config *LookupConfigByBaseAddress(UINTPTR BaseAddress)
{
XIntc_Config *CfgPtr = NULL;
int Index;
for (Index = 0; Index < XPAR_XINTC_NUM_INSTANCES; Index++) {
if (XIntc_ConfigTable[Index].BaseAddress == BaseAddress) {
CfgPtr = &XIntc_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/*****************************************************************************/
/**
*
* Register a fast handler function for a specific interrupt ID. The handler
* function will be called when an interrupt occurs for the given interrupt ID.
* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
* Controller
*
* @param BaseAddress is the base address of the interrupt controller
* whose vector table will be modified.
* @param InterruptId is the interrupt ID to be associated with the input
* handler.
* @param FastHandler is the function pointer that will be called when
* interrupt occurs
*
* @return None.
*
* @note
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIntc_RegisterFastHandler(UINTPTR BaseAddress, u8 Id,
XFastInterruptHandler FastHandler)
{
u32 CurrentIER;
u32 Mask;
u32 Imr;
XIntc_Config *CfgPtr;
if (Id > 31) {
/* Enable user required Id in Slave controller */
CfgPtr = XIntc_LookupConfig(Id/32);
/* Get the Enabled Interrupts */
CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
/* Convert from integer id to bit mask */
Mask = XIntc_BitPosMask[(Id%32)];
/* Disable the Interrupt if it was enabled before calling
* this function
*/
if (CurrentIER & Mask) {
XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
(CurrentIER & ~Mask));
}
if (CfgPtr->VectorAddrWidth >
XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
XIntc_Out64(CfgPtr->BaseAddress + XIN_IVEAR_OFFSET +
((Id%32) * 8), (UINTPTR) FastHandler);
} else {
XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET +
((Id%32) * 4), (u32) FastHandler);
}
/* Slave controllers in Cascade Mode should have all as Fast
* interrupts or Normal interrupts, mixed interrupts are not
* supported
*/
XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF);
/* Enable the Interrupt if it was enabled before calling this
* function
*/
if (CurrentIER & Mask) {
XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
(CurrentIER | Mask));
}
}
else {
CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
/* Convert from integer id to bit mask */
Mask = XIntc_BitPosMask[Id];
if (CurrentIER & Mask) {
/* Disable Interrupt if it was enabled */
CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
(CurrentIER & ~Mask));
}
CfgPtr = XIntc_LookupConfig(Id/32);
if (CfgPtr->VectorAddrWidth >
XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
XIntc_Out64(BaseAddress + XIN_IVEAR_OFFSET +
(Id * 8), (UINTPTR) FastHandler);
} else {
XIntc_Out32(BaseAddress + XIN_IVAR_OFFSET + (Id * 4),
(u32) FastHandler);
}
Imr = XIntc_In32(BaseAddress + XIN_IMR_OFFSET);
XIntc_Out32(BaseAddress + XIN_IMR_OFFSET, Imr | Mask);
/* Enable Interrupt if it was enabled before calling
* this function
*/
if (CurrentIER & Mask) {
CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
(CurrentIER | Mask));
}
}
}
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
/*****************************************************************************/
/**
*
* This function is called by primary interrupt handler for the driver to handle
* all Controllers in Cascade mode.It will resolve which interrupts are active
* and enabled and call the appropriate interrupt handler. It uses the
* AckBeforeService flag in the configuration data to determine when to
* acknowledge the interrupt. Highest priority interrupts are serviced first.
* This function assumes that an interrupt vector table has been previously
* initialized. It does not verify that entries in the table are valid before
* calling an interrupt handler.This function calls itself recursively to handle
* all interrupt controllers.
*
* @param DeviceId is the zero-based device ID defined in xparameters.h
* of the interrupting interrupt controller. It is used as a direct
* index into the configuration data, which contains the vector
* table for the interrupt controller.
*
* @return None.
*
* @note
*
******************************************************************************/
static void XIntc_CascadeHandler(void *DeviceId)
{
u32 IntrStatus;
u32 IntrMask = 1;
int IntrNumber;
u32 Imr;
XIntc_Config *CfgPtr;
static int Id = 0;
/* Get the configuration data using the device ID */
CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
/* Get the interrupts that are waiting to be serviced */
IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/* Mask the Fast Interrupts */
if (CfgPtr->FastIntr == TRUE) {
Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
IntrStatus &= ~Imr;
}
/* Service each interrupt that is active and enabled by
* checking each bit in the register from LSB to MSB which
* corresponds to an interrupt input signal
*/
for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs; IntrNumber++) {
if (IntrStatus & 1) {
XIntc_VectorTableEntry *TablePtr;
/* In Cascade mode call this function recursively
* for interrupt id 31 and until interrupts of last
* instance/controller are handled
*/
if ((IntrNumber == 31) &&
(CfgPtr->IntcType != XIN_INTC_LAST) &&
(CfgPtr->IntcType != XIN_INTC_NOCASCADE)) {
XIntc_CascadeHandler((void *)++Id);
Id--;
}
/* If the interrupt has been setup to
* acknowledge it before servicing the
* interrupt, then ack it */
if (CfgPtr->AckBeforeService & IntrMask) {
XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
}
/* Handler of 31 interrupt Id has to be called only
* for Last controller in cascade Mode
*/
if (!((IntrNumber == 31) &&
(CfgPtr->IntcType != XIN_INTC_LAST) &&
(CfgPtr->IntcType != XIN_INTC_NOCASCADE))) {
/* The interrupt is active and enabled, call
* the interrupt handler that was setup with
* the specified parameter
*/
TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
TablePtr->Handler(TablePtr->CallBackRef);
}
/* If the interrupt has been setup to acknowledge it
* after it has been serviced then ack it
*/
if ((CfgPtr->AckBeforeService & IntrMask) == 0) {
XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
}
/*
* Read the ISR again to handle architectures with
* posted write bus access issues.
*/
XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/*
* If only the highest priority interrupt is to be
* serviced, exit loop and return after servicing
* the interrupt
*/
if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
return;
}
}
/* Move to the next interrupt to check */
IntrMask <<= 1;
IntrStatus >>= 1;
/* If there are no other bits set indicating that all interrupts
* have been serviced, then exit the loop
*/
if (IntrStatus == 0) {
break;
}
}
}
#endif
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/intc_v3_9/src/xintc_l.h
+331
View File
@@ -0,0 +1,331 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_l.h
* @addtogroup intc_v3_9
* @{
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
*
* Note that users of the driver interface given in this file can register
* an interrupt handler dynamically (at run-time) using the
* XIntc_RegisterHandler() function.
* User of the driver interface given in xintc.h should still use
* XIntc_Connect(), as always.
* Also see the discussion of the interrupt vector tables in xintc.h.
*
* There are currently two interrupt handlers specified in this interface.
*
* - XIntc_LowLevelInterruptHandler() is a handler without any arguments that
* is used in cases where there is a single interrupt controller device in
* the system and the handler cannot be passed an argument. This function is
* provided mostly for backward compatibility.
*
* - XIntc_DeviceInterruptHandler() is a handler that takes a device ID as an
* argument, indicating which interrupt controller device in the system is
* causing the interrupt - thereby supporting multiple interrupt controllers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00b jhl 04/24/02 First release
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. _m is removed from all
* the macro definitions.
* 2.04a bss 01/13/12 Updated for adding defines for IMR and IVAR for
* the FAST Interrupt
* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.07a bss 10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.
* 3.5 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototypes of XIntc_RegisterFastHandler,
* XIntc_SetIntrSvcOption, XIntc_RegisterHandler APIs.
*
* </pre>
*
******************************************************************************/
#ifndef XINTC_L_H /* prevent circular inclusions */
#define XINTC_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xil_io.h"
/*
* XPAR_XINTC_USE_DCR_BRIDGE has to be set to 1 if the Intc device will be
* accessed through a DCR bus connected to a bridge.
*/
#define XPAR_XINTC_USE_DCR_BRIDGE 0
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#include "xio_dcr.h"
#endif
/************************** Constant Definitions *****************************/
/* define the offsets from the base address for all the registers of the
* interrupt controller, some registers may be optional in the hardware device
*/
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
#define XIN_IPR_OFFSET 1 /* Interrupt Pending Register */
#define XIN_IER_OFFSET 2 /* Interrupt Enable Register */
#define XIN_IAR_OFFSET 3 /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET 4 /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET 5 /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET 6 /* Interrupt Vector Register */
#define XIN_MER_OFFSET 7 /* Master Enable Register */
#define XIN_IMR_OFFSET 8 /* Interrupt Mode Register , this is present
* only for Fast Interrupt */
#define XIN_IVAR_OFFSET 64 /* Interrupt Vector Address Register
* Interrupt 0 Offest, this is present
* only for Fast Interrupt */
#else /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
#define XIN_IPR_OFFSET 4 /* Interrupt Pending Register */
#define XIN_IER_OFFSET 8 /* Interrupt Enable Register */
#define XIN_IAR_OFFSET 12 /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET 16 /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET 20 /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET 24 /* Interrupt Vector Register */
#define XIN_MER_OFFSET 28 /* Master Enable Register */
#define XIN_IMR_OFFSET 32 /* Interrupt Mode Register , this is present
* only for Fast Interrupt */
#define XIN_ILR_OFFSET 36 /* Interrupt level register */
#define XIN_IVAR_OFFSET 0x100 /* Interrupt Vector Address Register
* Interrupt 0 Offest, this is present
* only for Fast Interrupt */
#define XIN_IVEAR_OFFSET 0x200 /* Interrupt Vector Extended Address
Register */
#endif /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
/* Bit definitions for the bits of the MER register */
#define XIN_INT_MASTER_ENABLE_MASK 0x1UL
#define XIN_INT_HARDWARE_ENABLE_MASK 0x2UL /* once set cannot be cleared */
/**************************** Type Definitions *******************************/
/* The following data type defines each entry in an interrupt vector table.
* The callback reference is the base address of the interrupting device
* for the driver interface given in this file and an instance pointer for the
* driver interface given in xintc.h file.
*/
typedef struct {
XInterruptHandler Handler;
void *CallBackRef;
} XIntc_VectorTableEntry;
typedef void (*XFastInterruptHandler) (void);
/***************** Macros (Inline Functions) Definitions *********************/
/*
* Define the appropriate I/O access method to memory mapped I/O or DCR.
*/
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#define XIntc_In32 XIo_DcrIn
#define XIntc_Out32 XIo_DcrOut
#else
#define XIntc_In32 Xil_In32
#define XIntc_Out32 Xil_Out32
#define XIntc_Out64 Xil_Out64
#endif
/****************************************************************************/
/**
*
* Enable all interrupts in the Master Enable register of the interrupt
* controller. The interrupt controller defaults to all interrupts disabled
* from reset such that this macro must be used to enable interrupts.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note C-style signature:
* void XIntc_MasterEnable(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_MasterEnable(BaseAddress) \
XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \
XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK)
/****************************************************************************/
/**
*
* Disable all interrupts in the Master Enable register of the interrupt
* controller.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note C-style signature:
* void XIntc_MasterDisable(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_MasterDisable(BaseAddress) \
XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)
/****************************************************************************/
/**
*
* Enable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param EnableMask is the 32-bit value to write to the enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only the bits which are set in the mask will enable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask);
*
*****************************************************************************/
#define XIntc_EnableIntr(BaseAddress, EnableMask) \
XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
/****************************************************************************/
/**
*
* Disable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param DisableMask is the 32-bit value to write to the enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only the bits which are set in the mask will disable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask);
*
*****************************************************************************/
#define XIntc_DisableIntr(BaseAddress, DisableMask) \
XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
/****************************************************************************/
/**
*
* Acknowledge specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param AckMask is the 32-bit value to write to the acknowledge
* register. Each bit of the mask corresponds to an interrupt input
* signal that is connected to the interrupt controller (INT0 =
* LSB). Only the bits which are set in the mask will acknowledge
* interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_AckIntr(u32 BaseAddress, u32 AckMask);
*
*****************************************************************************/
#define XIntc_AckIntr(BaseAddress, AckMask) \
XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
/****************************************************************************/
/**
*
* Get the interrupt status from the interrupt controller which indicates
* which interrupts are active and enabled.
*
* @param BaseAddress is the base address of the device
*
* @return The 32-bit contents of the interrupt status register. Each bit
* corresponds to an interrupt input signal that is connected to
* the interrupt controller (INT0 = LSB). Bits which are set
* indicate an active interrupt which is also enabled.
*
* @note C-style signature:
* u32 XIntc_GetIntrStatus(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_GetIntrStatus(BaseAddress) \
(XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) & \
XIntc_In32((BaseAddress) + XIN_IER_OFFSET))
/************************** Function Prototypes ******************************/
/*
* Interrupt controller handlers, to be connected to processor exception
* handling code.
*/
void XIntc_LowLevelInterruptHandler(void);
void XIntc_DeviceInterruptHandler(void *DeviceId);
/* Various configuration functions */
void XIntc_SetIntrSvcOption(UINTPTR BaseAddress, int Option);
void XIntc_RegisterHandler(UINTPTR BaseAddress, int InterruptId,
XInterruptHandler Handler, void *CallBackRef);
void XIntc_RegisterFastHandler(UINTPTR BaseAddress, u8 Id,
XFastInterruptHandler FastHandler);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/intc_v3_9/src/xintc_options.c
+145
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/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_options.c
* @addtogroup intc_v3_9
* @{
*
* Contains option functions for the XIntc driver. These functions allow the
* user to configure an instance of the XIntc driver. This file requires other
* files of the component to be linked in also.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00b jhl 02/21/02 First release
* 1.00c rpm 10/17/03 New release. Support the relocation of the options flag
* from the instance structure to the xintc_g.c
* configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs
* 2.06a bss 01/28/13 To support Cascade mode:
* Modified XIntc_SetOptions API.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Set the options for the interrupt controller driver. In Cascade mode same
* Option is set to Slave controllers.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
* @param Options to be set. The available options are described in
* xintc.h.
*
* @return
* - XST_SUCCESS if the options were set successfully
* - XST_INVALID_PARAM if the specified option was not valid
*
* @note None.
*
****************************************************************************/
int XIntc_SetOptions(XIntc * InstancePtr, u32 Options)
{
XIntc_Config *CfgPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Make sure option request is valid
*/
if ((Options == XIN_SVC_SGL_ISR_OPTION) ||
(Options == XIN_SVC_ALL_ISRS_OPTION)) {
InstancePtr->CfgPtr->Options = Options;
/* If Cascade mode set the option for all Slaves */
if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
int Index;
for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
Index++) {
CfgPtr = XIntc_LookupConfig(Index);
CfgPtr->Options = Options;
}
}
return XST_SUCCESS;
}
else {
return XST_INVALID_PARAM;
}
}
/*****************************************************************************/
/**
*
* Return the currently set options.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return The currently set options. The options are described in xintc.h.
*
* @note None.
*
****************************************************************************/
u32 XIntc_GetOptions(XIntc * InstancePtr)
{
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return InstancePtr->CfgPtr->Options;
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/intc_v3_9/src/xintc_selftest.c
+251
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/******************************************************************************
*
* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_selftest.c
* @addtogroup intc_v3_9
* @{
*
* Contains diagnostic self-test functions for the XIntc component. This file
* requires other files of the component to be linked in also.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b jhl 02/21/02 First release
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs
* 2.04a bss 01/16/12 Removed CurrentMIE variable and reading of the
* MER register to remove warnings
* 2.06a bss 01/28/13 To support Cascade mode:
* Modified XIntc_SimulateIntr API.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
#include "xintc_i.h"
/************************** Constant Definitions *****************************/
#define XIN_TEST_MASK 1
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Run a self-test on the driver/device. This is a destructive test.
*
* This involves forcing interrupts into the controller and verifying that they
* are recognized and can be acknowledged. This test will not succeed if the
* interrupt controller has been started in real mode such that interrupts
* cannot be forced.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return
* - XST_SUCCESS if self-test is successful.
* - XST_INTC_FAIL_SELFTEST if the Interrupt controller fails the
* self-test. It will fail the self test if the device has
* previously been started in real mode.
*
* @note None.
*
******************************************************************************/
int XIntc_SelfTest(XIntc * InstancePtr)
{
u32 CurrentISR;
u32 Temp;
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Acknowledge all pending interrupts by reading the interrupt status
* register and writing the value to the acknowledge register
*/
Temp = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Temp);
/*
* Verify that there are no interrupts by reading the interrupt status
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
/*
* ISR should be zero after all interrupts are acknowledged
*/
if (CurrentISR != 0) {
return XST_INTC_FAIL_SELFTEST;
}
/*
* Set a bit in the ISR which simulates an interrupt
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, XIN_TEST_MASK);
/*
* Verify that it was set
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
if (CurrentISR != XIN_TEST_MASK) {
return XST_INTC_FAIL_SELFTEST;
}
/*
* Acknowledge the interrupt
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, XIN_TEST_MASK);
/*
* Read back the ISR to verify that the interrupt is gone
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
if (CurrentISR != 0) {
return XST_INTC_FAIL_SELFTEST;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Allows software to simulate an interrupt in the interrupt controller. This
* function will only be successful when the interrupt controller has been
* started in simulation mode. Once it has been started in real mode,
* interrupts cannot be simulated. A simulated interrupt allows the interrupt
* controller to be tested without any device to drive an interrupt input
* signal into it. In Cascade mode writes to ISR of appropraite Slave
* controller depending on Id.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
* @param Id is the interrupt ID for which to simulate an interrupt.
*
* @return
* - XST_SUCCESS if successful
* - XST_FAILURE if the interrupt could not be
* simulated because the interrupt controller is or
* has previously been in real mode.
*
* @note None.
*
******************************************************************************/
int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id)
{
u32 Mask;
u32 MasterEnable;
XIntc_Config *CfgPtr;
int Index;
int DeviceId;
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
/* Get the contents of the master enable register and determine if
* hardware interrupts have already been enabled, if so, this is a write
* once bit such that simulation can't be done at this point because
* the ISR register is no longer writable by software
*/
MasterEnable = XIntc_In32(InstancePtr->BaseAddress + XIN_MER_OFFSET);
if (MasterEnable & XIN_INT_HARDWARE_ENABLE_MASK) {
return XST_FAILURE;
}
if (Id > 31) {
DeviceId = Id/32;
CfgPtr = XIntc_LookupConfig(Id/32);
Mask = XIntc_BitPosMask[Id%32];
XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET, Mask);
/* Generate interrupt for 31 by writing to Interrupt Status
* register of parent controllers. Primary controller ISR
* will be written last in the loop
*/
Mask = XIntc_BitPosMask[31];
for (Index = DeviceId - 1; Index >= 0; Index--)
{
CfgPtr = XIntc_LookupConfig(Index);
XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET,
Mask);
}
}
else {
/*
* The Id is used to create the appropriate mask for the
* desired bit position.
*/
Mask = XIntc_BitPosMask[Id];
/*
* Enable the selected interrupt source by reading the interrupt
* enable register and then modifying only the specified
* interrupt id enable
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, Mask);
}
/* indicate the interrupt was successfully simulated */
return XST_SUCCESS;
}
/** @} */
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/Makefile
+75
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###############################################################################
#
# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
# The following are defined in config.make
# LIBSOURCES - Based on if MicroBlaze support Exceptions
# LIBS - Do Build Profile Libraries
include config.make
AS=mb-as
CC=$(CC)
AR=mb-ar
CP=cp
COMPILER_FLAGS=-O2 -c
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S)))
INCLUDEFILES=*.h
libs: $(LIBS)
standalone_libs: $(LIBSOURCES)
echo "Compiling standalone";
$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
$(AR) -r ${RELEASEDIR}/${LIB} ${OBJECTS} ${ASSEMBLY_OBJECTS}
profile_libs:
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" libs
include: standalone_includes profile_includes
standalone_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
profile_includes:
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" include
clean:
rm -rf ${OBJECTS}
rm -rf ${ASSEMBLY_OBJECTS}
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" clean
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/_exit.c
+42
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@@ -0,0 +1,42 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <unistd.h>
#include "xil_types.h"
void _exit (sint32 status);
/* _exit - Simple implementation. Does not return.
*/
void _exit (sint32 status)
{
(void) status;
while (1)
{
;
}
}
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/bspconfig.h
+41
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@@ -0,0 +1,41 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1.3
* DO NOT EDIT.
*
* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Configurations for Standalone BSP
*
*******************************************************************/
#ifndef BSPCONFIG_H /* prevent circular inclusions */
#define BSPCONFIG_H /* by using protection macros */
#define MICROBLAZE_PVR_NONE
#endif /*end of __BSPCONFIG_H_*/
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/changelog.txt
+593
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@@ -0,0 +1,593 @@
/*****************************************************************************
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
* 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
* cacheable regions
* Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
* generated by the cpu driver, for enabling caches
* 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
* write-thru caches
* 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
* Updated the MMU table to mark OCM in high address space
* as inner cacheable and reserved space as Invalid
* 3.03a sdm 08/20/11 Changes to support FreeRTOS
* Updated the MMU table to mark upper half of the DDR as
* non-cacheable
* Setup supervisor and abort mode stacks
* Do not initialize/enable L2CC in case of AMP
* Initialize UART1 for 9600bps in case of AMP
* 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
* in case of AMP
* 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
* counters
* 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
* xparameters.h file for CR630532 - Xil_DCacheFlush()/
* Xil_DCacheFlushRange() functions in standalone BSP v3_02a
* for MicroBlaze will invalidate data in the cache instead
* of flushing it for writeback caches
* 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
* Remove redundant dsb/dmb instructions in cache maintenance
* APIs
* Remove redundant dsb in mcr instruction
* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
* 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl in xparameters.h. Update the gcc/translationtable.s
* for the QSPI complete address range - DT644567
* Removed profile directory for armcc compiler and changed
* profiling setting to false in standalone_v2_1_0.tcl file
* Deleting boot.S file after preprocessing for armcc compiler
* 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
* invalidate the caches before enabling back the MMU and
* D cache.
* 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
* xil_mmu.c. Now we invalidate UTLB, Branch predictor
* array, flush the D-cache before changing the attributes
* in translation table. The user need not call Xil_DisableMMU
* before calling Xil_SetTlbAttributes.
* 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
* sgd initialization is present. Changes for this were done in
* uart.c and xil-crt0.s.
* Made changes in xil_io.c to use volatile pointers.
* Made changes in xil_mmu.c to correct the function
* Xil_SetTlbAttributes.
* Changes are made xil-crt0.s to initialize the static
* C++ constructors.
* Changes are made in boot.s, to fix the TTBR settings,
* correct the L2 Cache Auxiliary register settings, L2 cache
* latency settings.
* 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
* sgd usleep.c to use global timer intstead of CP15.
* Made changes in cortexa9/gcc/translation_table.s to map
* the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/xil-crt0.s to initialize
* the global timer.
* Made changes in cortexa9/armcc/boot.S to initialize
* the global timer.
* Made changes in cortexa9/armcc/translation_table.s to
* map the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/boot.S to optimize the
* L2 cache settings. Changes the section properties for
* ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
* and cortexa9/gcc/translation_table.S.
* Made changes in cortexa9/xil_cache.c to change the
* cache invalidation order.
* 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
* compilation/linking issues for C++ compiler.
* Made changes in mb_interface.h to remove compilation/
* linking issues for C++ compiler.
* Added macros for swapb and swaph microblaze instructions
* mb_interface.h
* Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
* for CortexA9.
* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
* 3.07a asa 08/31/12 Added xil_printf.h include
* 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
* Corrected L2 cache sequence disable sequence
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
* 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
* irq/fiq handling.
* Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
* fixes the CR #692094.
* 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
* 3.10a srt 04/18/13 Implemented ARM Erratas.
* Cortex A9 Errata - 742230, 743622, 775420, 794073
* L2Cache PL310 Errata - 588369, 727915, 759370
* Please refer to file 'xil_errata.h' for errata
* description.
* 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
* cache APIs were corresponding to only Layer 1 cache
* memories. New APIs were now added and the existing cache
* related APIs were changed to provide a uniform interface
* to flush/invalidate/enable/disable the complete cache
* system which includes both L1 and L2 caches. The changes
* for these were done in:
* src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
* files.
* Four new files were added for supporting L2 cache. They are:
* microblaze_flush_cache_ext.S-> Flushes L2 cache
* microblaze_flush_cache_ext_range.S -> Flushes a range of
* memory in L2 cache.
* microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
* microblaze_invalidate_cache_ext_range -> Invalidates a
* range of memory in L2 cache.
* These changes are done to implement PR #697214.
* 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
* fix the CR #706464. L2 cache disabling happens independent
* of L1 data cache disable operation. Changes are done in the
* same file in cache handling APIs to do a L2 cache sync
* (poll reg7_?cache_?sync). This fixes CR #700542.
* 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
* interrupts for ARM. These are done to fix the CR#699680.
* 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
* sync operation. This fixes the CR# 716781.
* 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
* for armcc toolchain.
* Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
* fix issues related to NEON context saving. The assembly
* routines for IRQ and FIQ handling are modified.
* Deprecated the older BSP (3.10a).
* 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
* various potential issues. Made changes in the function
* Xil_SetAttributes in file xil_mmu.c.
* 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
* in src\cortexa9 and src\microblaze folders.
* 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
* L2 cache sync operation and to fix issues around complete
* L2 cache flush/invalidation by ways.
* 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
* to fix linking issues with armcc/DS-5. Modified the armcc
* makefile to fix issues.
* 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
* 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
* 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
* and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
* src\cortexa9\armcc\) to fix CR#767251
* 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
* Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
* Few cache lines were missed to invalidate when unaligned address
* invalidation was accommodated in Xil_DCacheInvalidateRange.
* In Xil_L1DCacheInvalidate, while invalidating all L1D cache
* stack memory (which contains return address) was invalidated. So
* stack memory is flushed first and then L1D cache is invalidated.
* This is done to fix CR #763829
* 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
* mblaze_nt_types.h file and replace uint32_t with u32 in the
* profile_hist.c to fix the above CR.
* 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
* instead of libxil.a and added prototypes for
* microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
* mb_interface.h
* 4.1 hk 04/18/14 Add sleep function.
* 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
* some of the *.s files inMB BSP source to *.S.
* 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
* 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
* CR#794205
* 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
* common/xil_testcache.c
* Fix for CR#764881.
* 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
* output the DEBUG logs when -DDEBUG flag is enabled in BSP.
* 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
* Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
* 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
* cortexa9/armcc/boot.s. Added default exception handlers for data
* abort and prefetch abort using handlers called
* DataAbortHandler and PrefetchAbortHandler respectively in
* cortexa9/xil_exception.c to fix CR#802862.
* 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
* issue of improper linking of translation_table.s
* 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
* in tool chain to avoid conflicts into some special cases
* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
* Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
* 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
* containing type def u32 defined in xil_types.g to resolve issue of
* CR#805869
* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
* it is not possible to generate timer in nanosecond due to limited
* cpu frequency
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
* uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
* and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
* removed function definition of XSmc_NorInit and XSmc_NorInit from
* cortexa9/smc.h
* 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
* cache_ext_range declarations in mb_interface.h CR#783821.
* Modified profile_mcount_mb.S to fix CR#808412.
* 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
* cortexa9/iccarm to fix CR#816701
* 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
* armcc/translation_table.s and iccarm/translation_table.s
* to properly defined reserved entries according to address map for
* fixing CR#820146
* 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
* and cortexa9/armcc/translation_table.s to resolve compilation
* error for solving CR#822897
* 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for
* MISRA-C:2012 compliance.
* 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
* adding src/common/xplatform_info.*s
* 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
* removed incorrect initialization of TLB lockdown register to fix
* CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
* and iccarm/boot.s
* 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
* for iccarm and armcc compiler of cortexA9
* 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
* and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
* caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
* of L2Cache is done later.
* 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
* Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
* taking long time to fix CR#853097. L2CacheSync is added into
* Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
* Xil_L2CacheInvalidate APIs are modified to flush the complete stack
* instead of just System Stack
* 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
* to update ECC_FLAGS and also take the compiler and archiver as specified
* in settings instead of hardcoding it.
* 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for
* XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
* accordingly generate the translation table
* 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
* to update ECC_FLAGS to fix a bug introduced during new version creation
* of BSP.
* 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
* functionalities are avoided for the OpenAMP slave application(when
* USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
* cache for its operation. Also file operations such as read, write,
* close, open are also avoided for OpenAMP support(when USE_AMP flag is
* defined for BSP) because XilOpenAMP library contains own file operation.
* The xil-crt0.S file is modified for not initializing global timer for
* OpenAMP application as it might be already in use by master CPU
* 5.3 pkp 10/09/15 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
* definition for dsb, isb and dmb to fix the compilation error when used
* kvn 16/10/15 Encapsulated assembly code into macros for R5 xil_cache file.
* 5.4 pkp 09/11/15 Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
* R5 deadlock for errata 780125
* 5.4 pkp 09/11/15 Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
* 32 bit BSP in the initialization
* 5.4 pkp 09/11/15 Modified cortexa9/xil_misc_psreset_api.c file to change the description
* for XOcm_Remap function
* 5.4 pkp 16/11/15 Modified microblaze/xil_misc_psreset_api.c file to change the description
* for XOcm_Remap function
* kvn 21/11/15 Added volatile keyword for ADDR varibles in Xil_Out API
* kvn 21/11/15 Changed ADDR variable type from u32 to UINTPTR. This is
* required for MISRA-C:2012 Compliance.
* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
* in cortexa9/xil_mmu.h
* 5.4 pkp 23/11/15 Added default undefined exception handler for Cortex-A9
* 5.4 pkp 11/12/15 Modified common/xplatform_info.h to add #defines for silicon for
* checking the current executing platform
* 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
* to initialize global constructor for C++ applications
* 5.4 pkp 18/12/15 Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
* C++ applications
* 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
* translation_table.S to update the translation table according to proper
* address map
* 5.4 pkp 18/12/15 Modified cortexar5/mpu.c to initialize the MPU according to proper
* address map
* 5.4 pkp 05/01/16 Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
* equivalent to vector table base address
* 5.4 pkp 08/01/16 Modified cortexa9/gcc/Makefile to update the extra compiler flag
* as per the toolchain update
* 5.4 pkp 12/01/16 Changed common/xplatform_info.* to add platform information support
* for Cortex-A53 32bit mode
* 5.4 pkp 28/01/16 Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
* and usleep.c to correct routines to avoid hardcoding the timer frequency,
* instead take it from xparameters.h to properly configure the timestamp
* clock frequency
* 5.4 asa 29/01/16 Modified microblaze/mb_interface.h to add macros that support the
* new instructions for MB address extension feature
* 5.4 kvn 30/01/16 Modified xparameters_ps.h file to add interrupt ID number for
* system monitor.
* 5.4 pkp 04/02/16 Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
* 5.4 pkp 19/02/16 Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
* cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
* cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
* use set of assembly instructions to provide required delay to fix
* CR#913249.
* 5.4 asa 25/02/16 Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
* _exit with exit. We should not be directly calling _exit and should
* always use the library exit. This fixes the CR#937036.
* 5.4 pkp 25/02/16 Made change to cortexr5/gcc/boot.S to initialize the floating point
* registers, banked registers for various modes and enabled
* the cache ECC check before enabling the fault log for lock step mode
* Also modified the cortexr5/gcc/Makefile to support floating point
* registers initialization in boot code.
* 5.4 pkp 03/01/16 Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
* logic in case of lock-step mode when fault log is enabled to fix
* CR#938281
* 5.4 pkp 03/02/16 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
* header file instrinsics.h which contains assembly instructions
* definitions which can be used by C
* 5.4 asa 03/02/16 Added print.c in MB BSP. Made other cosmetic changes to have uniform
* proto for all print.c across the BSPs. This patch fixes CR#938738.
* 5.4 pkp 03/09/16 Modified cortexr5/sleep.c and usleep.c to avoid disabling the
* interrupts when sleep/usleep is being executed using assembly
* instructions to fix CR#913249.
* 5.4 pkp 03/11/16 Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
* instead modified cortexr5/sleep.c and usleep.c to poll the counter
* value and compare it with previous value to detect the overflow
* to fix CR#940209.
* 5.4 pkp 03/24/16 Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
* the fault log to avoid intervention for lock-step mode and cortexr5/
* _exit.c to enable the dbg_lpd_reset once the fault log is disabled
* to fix CR#947335
* 5.5 pkp 04/11/16 Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
* in lock-step to avoid resetting the debug logic which restricts the
* access for debugger and removed enabling back of debug modules in
* cortexr5/_exit.c
* 5.5 pkp 04/13/16 Modified cortexa9/gcc/read.c to return correct number of bytes when
* read buffer is filled and removed the redundant NULL checking for
* buffer to simplify the code
* 5.5 pkp 04/13/16 Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
* to return correct number of bytes when read buffer is filled and
* removed the redundant NULL checking for buffer to simplify the code
* 5.5 pkp 04/13/16 Modified cortexr5/gcc/read.c to return correct number of bytes when
* read buffer is filled and removed the redundant NULL checking for
* buffer to simplify the code
* 5.5 pkp 04/13/16 Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
* instruction macros to disable certain optimizations which may move
* code out of loops if optimizers believe that the code will always
* return the same result or discard asm statements if optimizers
* determine there is no need for the output variables
* 5.5 pkp 04/13/16 Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
* starts the timer if it is disabled and modified XTime_GetTime to
* enable the timer if it is not enabled. Also modified cortexa53/64bit/
* sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
* disabled and read the counter value directly from register instead
* of using XTime_GetTime for optimization
* 5.5 pkp 04/13/16 Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
* starts the timer if it is disabled and modified XTime_GetTime to
* enable the timer if it is not enabled. Also modified cortexa53/32bit/
* sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
* disabled and read the counter value directly from register instead
* of using XTime_GetTime for optimization
* 5.5 pkp 04/13/16 Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
* to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
* Xil_DCacheInvalidateRange functions description for proper
* explaination to fix CR#949801
* 5.5 asa 04/20/16 Added missing macros for hibernate and suspend in Microblaze BSP
* file mb_interface.h. This fixes the CR#949503.
* 5.5 asa 04/29/16 Fix for CR#951080. Updated cache APIs for HW designs where cache
* memory is not included for MicroBlaze.
* 5.5 pkp 05/06/16 Modified the cortexa9/xil_exception.h to update the macros
* Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
* the issue of lr being corrupted to resolve CR#950468
* 5.5 pkp 05/06/16 Modified the cortexr5/xil_exception.h to update the macros
* Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
* the issue of lr being corrupted to resolve CR#950468
* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
* 6.0 pkp 06/27/16 Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
* section since it is part of boot process to fix CR#949555
* hk 07/12/16 Correct masks for IOU SLCR GEM registers
* 6.0 pkp 07/25/16 Program the counter frequency in boot code for CortexA53
* 6.0 asa 08/03/16 Updated sleep_common function in microblaze_sleep.c to improve the
* the accuracy of MB sleep functionality. This fixes the CR#954191.
* 6.0 mus 08/03/16 Restructured the BSP to avoid code duplication across all BSPs.
* Source code directories specific to ARM processor's are moved to src/arm
* directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
* src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
* print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
* consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
* xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
* into common file each and consolidated files are kept at src/arm/common directory.
* GCC source files related to file operations are consolidated and kept
* at src/arm/common/gcc directory.
* All io interfacing functions (i.e. All variants of xil_out, xil_in )
* are made as static inline and implementation is kept in consolidated common/xil_io.h,
* xil_io.h must be included as a header file to access io interfacing functions.
* Added undefined exception handler for A53 32 bit and R5 processor
* 6.0 mus 08/11/16 Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
* TTC counter value register is read only.
* 6.0 asa 08/15/16 Modified the signatures for functions sleep and usleep. This fixes
* the CR#956899.
* 6.0 mus 08/18/16 Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
* in cortexr5/xparameters_ps.h
* 6.0 mus 08/18/16 Added support for the the Zynq 7000s devices
* 6.0 mus 08/18/16 Removed unused variables from xil_printf.c and xplatform_info.c
* 6.0 mus 08/19/16 Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
* 6.1 mus 11/03/16 Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
* ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
* these APIs and modifications are done on top of it to handle stdout/stdin
* parameters for design which doesnt have UART.It fixes CR#953681
* 6.1 nsk 11/07/16 Added two new files xil_mem.c and xil_mem.h for xil_memcpy
* 6.2 pkp 12/14/16 Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 -
* 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf
* and rest of the memory in that 32GB region is marked as reserved to avoid
* any speculative access
* 6.2 pkp 12/23/16 Added support for floating point operation to Cortex-A53 64bit mode. It modified
* asm_vectors.S to implement lazy floating point context saving i.e. floating point
* access is enabled if there is any floating point operation, it is disabled by
* default. Also FPU is initally disabled for IRQ and none of the floating point
* registers are saved during normal context saving. If IRQ handler does not require
* floating point operation, the floating point registers are untouched and no need
* for saving/restoring. If IRQ handler uses any floating point operation, then floating
* point registers are saved and FPU is enabled for IRQ handler. Then floating point
* registers are restored back after servicing IRQ during normal context restoring.
* 6.2 mus 01/01/17 Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean
* target.It fixes the CR#966900
* 6.2 pkp 01/22/17 Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53
* 64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built
* for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is
* as false i.e. default bsp is EL3.
* 6.2 pkp 01/24/17 Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it
* contains initial status of FPU i.e. disabled. In case of a warm restart execution
* when bss sections are not cleared, it may contain previously updated value which
* does not hold true once processor resumes. This fixes CR#966826.
* 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the
* D caches and then disables it. The problem with that is,
* potentially there will be a small window after the cache
* flush operation and before the we disable D caches where
* we might have valid data in cache lines. In such a
* scenario disabling the D cache can lead to unknown behavior.
* The ideal solution to this is to use assembly code for
* the complete API and avoid any memory accesses. But with
* that we will end up having a huge amount on assembly code
* which is not maintainable. Changes are done to use a mix
* of assembly and C code. All local variables are put in
* registers. Also function calls are avoided in the API to
* avoid using stack memory.
* 6.2 mus 02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are
* scenarios when an invalidated cache line can get pre fetched to cache.
* If that happens, the coherency between cache and memory is lost
* resulting in lost data. To avoid this kind of issue either
* user has to use dsb() or disable pre-fetching for L1 cache
* or else reduce maximum number of outstanding data prefetches allowed.
* Using dsb() while comparing data costing more performance compared to
* disabling pre-fetching/reducing maximum number of outstanding data
* prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added
* to disable pre-fetching/configure maximum number of outstanding data
* prefetches allowed in L1 cache system.This fixes CR#967864.
* 6.2 pkp 02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be
* used by cortex-A53 64bit EL1 Non-secure application.
* 6.2 kvn 03/03/17 Added support thumb mode
* 6.2 mus 03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.
* It fixes CR#970543
* 6.2 asa 03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive
* profiling we see a crash. That is because the the tcl uses invalid
* HSI command. This change fixes it.
* 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
* any FPD peripheral is configured to use CCI.It fixes CR#972638
* 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support.
* 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in
* the HW coherency enablement. It fixes the CR#973287
* 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the
* L2CTLR_EL1 register. It fixes the CR#974698
* 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers
* of ARM 32 bit processor's.
* 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code
* snippet, which checks for the FPEN bit of CPACR_EL1 register.
* 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support
* XGetPSVersion_Info function for PMUFW.
* ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info
* function for PMUFW.
* 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740.
* 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point
* operations.Now,VFP is being enabled in FPEXC register, through boot code
* and FPU registers are being saved/restored when irq/fiq vector is invoked.
* 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT,
* if h/w design configured with HPC port.
* 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for
* EL1 NS execution. This change has been done to support CCI enabled IP's.
* 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes
* CR#982209.
* 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to
* make RPU MPU handling user-friendly. This also fixes the CR-981028.
* 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read
* version register through SMC call, over EL1 NS mode. This change has been done to
* support these APIs over EL1 NS mode.
* 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc,
* it fixes CR#987464.
* 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970.
* It fixes CR#989132.
* srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines
* will use the timer specified by the user to provide delay. A9 and A53 can use
* Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use
* machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files
* to support the sleep configuration Added new API's for the Axi timer in
* microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and
* xil_sleeptimer.h in ARM for the common sleep routines and 1 new file,
* xil_sleepcommon.c in Standalone-common for sleep/usleep API's.
* 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor.
* 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache
* or L2 cache only when the respective caches are enabled. This fixes CR-922023.
* 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
* after writing to cpacr_el1/cptr_el3 registers. It would ensure
* disabling/enabling of floating-point unit, before any subsequent
* instruction.
* 6.6 hk 12/15/17 Export platform macros to xparameters.h based on the processor.
* 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache
* or L2 cache only when the respective caches are enabled.This fixes CR-922023.
*
* 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
* after writing to cpacr_el1/cptr_el3 registers. It would ensure
* disabling/enabling of floating-point unit, before any subsequent
* instruction.
* 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console
* support. Now, xil_printf would use PV console instead of UART in case of
* hypervisor enabled BSP.
* 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port
* configured with smart interconnect.It fixes CR#990318.
* 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229
* 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932.
* 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc,
* CR#995014.
* 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in
* non-JTAG boot mode, when processor is in lockstep configuration.
* This behavior is restricting application debugging in non-JTAG boot
* mode. To get rid of this restriction, added new mld parameter
* "lockstep_mode_debug", to enable/disable debug logic from BSP
* settings. Now, debug logic can be enabled through BSP settings,
* by modifying value of parameter "lockstep_mode_debug" as "true".
* It fixes CR#993896.
* 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and
* Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug
* in handling upper DDR addresses.It fixes CR#995581.
* 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory
* in the list of include paths. This change allows applications/BSP
* files to include .h files in include_ps directory.
* 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it
* results into abort if accessed from EL1 non secure privilege
* level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP
* to avoid CPUACTLR_EL1 access from privile levels other than EL3.
* 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the
* XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would
* use UART console, PV console can be enabled by appending
* "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags.
* 6.7 asa 04/26/18 Added API Xil_GetExceptionRegisterHandler for obtaining information
* on an already registered exception vector.
* 6.7 asa 05/18/18 Fixed bugss in the API Xil_GetExceptionRegisterHandler.
* 6.8 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now, saving/restoring of of HW
* floating point register would be done through newly introduced flag
* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be configured based on
* the -mfpu-abi option in extra compiler flags.. This change has
* been done to avoid saving/restoring of HW floating point registers,
* when BSP is not compiled with HW floating point configuration.
* 6.8 aru 06/15/18 Removed unused variable in xil_cache.c for A53-32. It
* fixes CR1005118.
* 6.8 aru 07/02/18 Returned the pointer instead of address of that pointer in xil_mpu.c
* for R5 processor.It Fixes CR#1005119.
* 6.8 mus 07/12/18 Updated Cortexa9 translation table to mark DDR memory as inner cacheable,
* if BSP is built with the USE_AMP flag. It fixes CR#1006745.
*
* 6.8 aru 07/04/18 Optimized the code to use a loop and to remove redundant code
* in Xil_DCacheFlush() and Xil_DCacheInvalidate()
* of xil_cache.c for A53-32.
* 6.8 aru 07/26/18 added support in xil_printf.c to print u64 variabbles
* correctly in 32 bit processor.It fixes CR#1007207.
* 6.8 aru 09/03/18 Optimized the code to use a single function and removed
* code redundancy in xil_printf.c . It Fixes CR#1009654.
* 6.8 aru 09/06/18 Removed the compiler warnings for ARMCC toolchain.
* It fixes CR#1008309.
* 6.8 mus 09/20/18 Updated CortexR5 boot code to initialize CortexR5 core with LOVEC
* on reset. It fixes CR#1010656.
* 6.8 mus 10/04/18 Updated microblaze sleep functinality to execute default method of
* sleep implementation, incase of FreeRTOS BSP.
* 6.8 mus 10/25/18 Updated assembly code for cache APIs and inline assemby macros to
* to support 64 bit addresses.
* 6.8 asa 10/11/18 Updated the A53 32 bit cache APIs for Xil_DCacheFlush and
* Xil_DCacheInvalidate to fix various issues. These issues were not
* present in the previous releases but got introduced as part of
* optimization patches that got applied for 6.8 BSP version. These
* changes fix the CR#1016012.
* 7.0 rp 10/25/18 Added XST_NO_ACCESS status macros for generic access error.
* 7.0 mus 02/01/19 Added support for Versal. Cortea53 BSP will be re-used by Cortexa72,
* re-named cortexa53 directory as ARMv8, since files are generic for
* ARMv8 based processors. Created "platform" directory to place
* SoC based files.
* 7.0 mus 02/05/19 Updated Xil_MemCpy API to copy two bytes at a time from source to
* destination if byte count is <= 2.
* 7.0 mus 02/28/19 Added armclang complier support to the Cortexa53 64 bit BSP.
* 7.0 mus 04/08/19 Fix microblaze_disable_dcache for 64 bit microblaze
* 7.0 mus 04/26/19 Added frequently used functions in common area in xil_utils.c,
* so that other modules can make use of it.
*****************************************************************************************/
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/config.make
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LIBSOURCES = *.c *.S
PROFILE_ARCH_OBJS = profile_mcount_mb.o
LIBS = standalone_libs
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/errno.c
+14
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@@ -0,0 +1,14 @@
/* The errno variable is stored in the reentrancy structure. This
function returns its address for use by the macro errno defined in
errno.h. */
#include <errno.h>
#include <reent.h>
#include "xil_types.h"
sint32 * __errno (void);
sint32 *
__errno (void)
{
return &_REENT->_errno;
}
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/fcntl.c
+15
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@@ -0,0 +1,15 @@
#include <stdio.h>
#include "xil_types.h"
sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg);
/*
* fcntl -- Manipulate a file descriptor.
* We don't have a filesystem, so we do nothing.
*/
sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg)
{
(void) fd;
(void) cmd;
(void) arg;
return 0;
}
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/fsl.h
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#ifndef FSL_H
#define FSL_H
/*****************************************************************************/
/**
*
* @file fsl.h
*
* @addtogroup microblaze_fsl_macro MicroBlaze Processor FSL Macros
*
* Microblaze BSP includes macros to provide convenient access to accelerators
* connected to the MicroBlaze Fast Simplex Link (FSL) Interfaces.To use these functions,
* include the header file fsl.h in your source code
*
* @{
*
******************************************************************************/
#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
#ifdef __cplusplus
extern "C" {
#endif
/* Extended FSL macros. These now replace all of the previous FSL macros */
#define FSL_DEFAULT
#define FSL_NONBLOCKING n
#define FSL_EXCEPTION e
#define FSL_CONTROL c
#define FSL_ATOMIC a
#define FSL_NONBLOCKING_EXCEPTION ne
#define FSL_NONBLOCKING_CONTROL nc
#define FSL_NONBLOCKING_ATOMIC na
#define FSL_EXCEPTION_CONTROL ec
#define FSL_EXCEPTION_ATOMIC ea
#define FSL_CONTROL_ATOMIC ca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
#define FSL_EXCEPTION_CONTROL_ATOMIC eca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
/**
Performs a get function on an input FSL of the MicroBlaze processor
@param val variable to sink data from get function
@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
/**
Performs a put function on an input FSL of the MicroBlaze processor
@param val variable to source data to put function
@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
/**
Performs a test get function on an input FSL of the MicroBlaze processor
@param val variable to sink data from get function
@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
/**
Performs a put function on an input FSL of the MicroBlaze processor
@param id FSL identifier
@param flags valid FSL macro flags
*/
#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
/**
Performs a getd function on an input FSL of the MicroBlaze processor
@param val variable to sink data from getd function
@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
/**
Performs a putd function on an input FSL of the MicroBlaze processor
@param val variable to source data to putd function
@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
/**
Performs a test getd function on an input FSL of the MicroBlaze processor;
@param val variable to sink data from getd function
@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
@param flags valid FSL macro flags
*/
#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
/**
Performs a put function on an input FSL of the MicroBlaze processor
@param var FSL identifier
@param flags valid FSL macro flags
*/
#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
#ifdef __cplusplus
}
#endif
#endif /* FSL_H */
/**
* @} End of "addtogroup microblaze_fsl_macro".
*/
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/hw_exception_handler.S
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/******************************************************************************
*
* Copyright (C) 2004 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
* Microblaze HW Exception Handler
* - Non self-modifying exception handler for the following exception conditions
* - Unalignment
* - Instruction bus error
* - Data bus error
* - Illegal instruction opcode
* - Divide-by-zero
* - Stack protection violation
*******************************************************************************/
#include "microblaze_exceptions_g.h"
#include "xparameters.h"
#include "microblaze_instructions.h"
/* 64-bit definitions */
#if defined (__arch64__)
#define INTPTR_DATAITEM .quad
#define REGSIZE 8
#define DATAALIGN 4
#else
#define INTPTR_DATAITEM .long
#define REGSIZE 4
#define DATAALIGN 2
#endif /* 64-bit definitions */
/* Helpful Macros */
#define EX_HANDLER_STACK_SIZ (REGSIZE*21)
#define RMSR_OFFSET (20 * REGSIZE)
#define R17_OFFSET (0)
#define REG_OFFSET(regnum) (REGSIZE * (regnum + 1))
#define NUM_TO_REG(num) r ## num
#define R3_TO_STACK(regnum) SI r3, r1, REG_OFFSET(regnum)
#define R3_FROM_STACK(regnum) LI r3, r1, REG_OFFSET(regnum)
#define PUSH_REG(regnum) SI NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
#define POP_REG(regnum) LI NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
/* Uses r5 */
#define PUSH_MSR \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET;
#define PUSH_MSR_AND_ENABLE_EXC \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET; \
ori r5, r5, 0x100; /* Turn ON the EE bit*/ \
mts rmsr, r5;
/* Uses r5 */
#define POP_MSR \
lwi r5, r1, RMSR_OFFSET; \
mts rmsr, r5;
/* Push r17 */
#define PUSH_R17 SI r17, r1, R17_OFFSET
/* Pop r17 */
#define POP_R17 LI r17, r1, R17_OFFSET
#define LWREG_NOP \
BRI ex_handler_unhandled; \
nop;
#define SWREG_NOP \
BRI ex_handler_unhandled; \
nop;
/* r3 is the source */
#define R3_TO_LWREG_V(regnum) \
R3_TO_STACK (regnum); \
BRI ex_handler_done;
/* r3 is the source */
#define R3_TO_LWREG(regnum) \
OR NUM_TO_REG (regnum), r0, r3; \
BRI ex_handler_done;
/* r3 is the target */
#define SWREG_TO_R3_V(regnum) \
R3_FROM_STACK (regnum); \
BRI ex_sw_tail;
/* r3 is the target */
#define SWREG_TO_R3(regnum) \
OR r3, r0, NUM_TO_REG (regnum); \
BRI ex_sw_tail;
/* regnum is the source */
#define FP_EX_OPB_SAVE(regnum) \
SI NUM_TO_REG (regnum), r0, mb_fpex_op_b; \
nop; \
BRI handle_fp_ex_opa;
/* regnum is the source */
#define FP_EX_OPB_SAVE_V(regnum) \
R3_FROM_STACK (regnum); \
SI r3, r0, mb_fpex_op_b; \
BRI handle_fp_ex_opa;
/* regnum is the source */
#define FP_EX_OPA_SAVE(regnum) \
SI NUM_TO_REG (regnum), r0, mb_fpex_op_a; \
nop; \
BRI handle_fp_ex_done;
/* regnum is the source */
#define FP_EX_OPA_SAVE_V(regnum) \
R3_FROM_STACK (regnum); \
SI r3, r0, mb_fpex_op_a; \
BRI handle_fp_ex_done;
#define FP_EX_UNHANDLED \
BRI fp_ex_unhandled; \
nop; \
nop;
/* ESR masks */
#define ESR_EXC_MASK 0x0000001F
#define ESR_REG_MASK 0x000003E0
#define ESR_LW_SW_MASK 0x00000400
#define ESR_WORD_MASK 0x00000800
#define ESR_DS_MASK 0x00001000
/* Extern declarations */
.extern XNullHandler
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
/*
* hw_exception_handler - Handler for unaligned exceptions
* Exception handler notes:
* - Does not handle exceptions other than unaligned exceptions
* - Does not handle exceptions during load into r17, r1, r0.
* - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case)
*
* Relevant register structures
*
* EAR - |----|----|----|----|----|----|----|----|
* - < ## 32 or 64 bit faulting address ## >
*
* ESR - |----|----|----|----|----| - | - |-----|-----|
* - W S REG EXC
*
*
* STACK FRAME STRUCTURE
* ---------------------
*
* +-------------+ + 0
* | r17 |
* +-------------+ + 4 (32-bit) + 8 (64-bit)
* | Args for |
* | next func |
* +-------------+ + 8 (32-bit) + 16 (64-bit)
* | r1 |
* | . |
* | . |
* | . |
* | . |
* | r18 |
* +-------------+ + 80 (32-bit) + 160 (64-bit)
* | MSR |
* +-------------+ + 84 (32-bit) + 168 (64-bit)
* | . |
* | . |
*/
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
.type _hw_exception_handler, @function
_hw_exception_handler:
#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
/* Immediately halt for stack protection violation exception without using any stack */
SI r3, r0, mb_sp_save_r3; /* Save temporary register */
mfs r3, resr; /* Extract ESR[DS] */
andi r3, r3, ESR_EXC_MASK;
xori r3, r3, 0x7; /* Check for stack protection violation */
BNEI r3, ex_handler_not_sp_violation;
ex_handler_sp_violation:
bri 0; /* Halt here if stack protection violation */
ex_handler_not_sp_violation:
LI r3, r0, mb_sp_save_r3; /* Restore temporary register */
#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
ADDIK r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
PUSH_REG(3);
PUSH_REG(4);
PUSH_REG(5);
PUSH_REG(6);
#ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
mfs r6, resr;
andi r6, r6, ESR_DS_MASK;
BEQI r6, ex_handler_no_ds;
mfs r17, rbtr;
ex_handler_no_ds:
#endif
PUSH_R17;
PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */
mfs r3, resr;
andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */
#ifndef NO_UNALIGNED_EXCEPTIONS
xori r6, r5, 1; /* 00001 = Unaligned Exception */
BNEI r6, handle_ex_regular;
ADDIK r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */
LI r4, r4, 8;
ADDIK r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */
XOR r6, r4, r6; /* the default exception handler */
BEQI r6, handle_unaligned_ex ;
handle_ex_regular:
#endif /* ! NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
xori r6, r5, 6; /* 00110 = FPU exception */
BEQI r6, handle_fp_ex; /* Go and decode the FP exception */
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
handle_other_ex: /* Handle Other exceptions here */
ori r6, r0, 20;
cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */
BLEI r6, ex_handler_unhandled;
ori r6, r0, 7;
cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */
BGTI r6, handle_other_ex_tail;
ori r5, r0, 0x7;
handle_other_ex_tail:
PUSH_REG(7); /* Save other volatiles before we make procedure calls below */
PUSH_REG(8);
PUSH_REG(9);
PUSH_REG(10);
PUSH_REG(11);
PUSH_REG(12);
PUSH_REG(15);
PUSH_REG(18);
ADDIK r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */
ADDK r7, r5, r5; /* Calculate exception vector offset = r5 * 8 (32-bit) */
ADDK r7, r7, r7;
ADDK r7, r7, r7;
#if defined (__arch64__)
ADDK r7, r7, r7; /* or r5 * 16 (64-bit) */
#endif
ADDK r7, r7, r4; /* Get pointer to exception vector */
LI r5, r7, REGSIZE; /* Load argument to exception handler from table */
LOAD r7, r7, r0; /* Load vector itself here */
brald r15, r7; /* Branch to handler */
nop;
POP_REG(7); /* Restore other volatiles */
POP_REG(8);
POP_REG(9);
POP_REG(10);
POP_REG(11);
POP_REG(12);
POP_REG(15);
POP_REG(18);
BRI ex_handler_done; /* Complete exception handling */
#ifndef NO_UNALIGNED_EXCEPTIONS
handle_unaligned_ex:
andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */
srl r6, r6; /* r6 >> 5 */
srl r6, r6;
srl r6, r6;
srl r6, r6;
srl r6, r6;
sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */
mfs r4, rear;
andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */
BNEI r6, ex_sw;
ex_lw:
andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */
BEQI r6, ex_lhw;
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lbui r5, r4, 2;
sbi r5, r0, ex_tmp_data_loc_2;
lbui r5, r4, 3;
sbi r5, r0, ex_tmp_data_loc_3;
lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
BRI ex_lw_tail;
ex_lhw:
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
ex_lw_tail:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
ADDIK r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */
ADDK r5, r5, r5;
ADDK r5, r5, r5;
ADDK r5, r5, r5;
ADDK r5, r5, r6;
bra r5;
ex_lw_end: /* Exception handling of load word, ends */
ex_sw:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
ADDIK r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */
ADDK r5, r5, r5;
ADDK r5, r5, r5;
ADDK r5, r5, r5;
ADDK r5, r5, r6;
bra r5;
ex_sw_tail:
mfs r6, resr;
andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */
BEQI r6, ex_shw;
swi r3, r0, ex_tmp_data_loc_0;
lbui r3, r0, ex_tmp_data_loc_0; /* Store the word, byte-by-byte into destination address */
sbi r3, r4, 0;
lbui r3, r0, ex_tmp_data_loc_1;
sbi r3, r4, 1;
lbui r3, r0, ex_tmp_data_loc_2;
sbi r3, r4, 2;
lbui r3, r0, ex_tmp_data_loc_3;
sbi r3, r4, 3;
BRI ex_handler_done;
ex_shw:
swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */
#ifdef __LITTLE_ENDIAN__
lbui r3, r0, ex_tmp_data_loc_0;
#else
lbui r3, r0, ex_tmp_data_loc_2;
#endif
sbi r3, r4, 0;
#ifdef __LITTLE_ENDIAN__
lbui r3, r0, ex_tmp_data_loc_1;
#else
lbui r3, r0, ex_tmp_data_loc_3;
#endif
sbi r3, r4, 1;
ex_sw_end: /* Exception handling of store word, ends. */
BRI ex_handler_done;
#endif /* !NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
handle_fp_ex:
ADDIK r3, r17, -4; /* r17 contains (addr of exception causing FP instruction + 4) */
lw r4, r0, r3; /* We might find ourselves in a spot here. Unguaranteed load */
handle_fp_ex_opb:
ADDIK r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
andi r3, r4, 0x1F;
ADDK r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
ADDK r3, r3, r3;
ADDK r5, r3, r3;
ADDK r5, r5, r3;
ADDK r5, r5, r6;
bra r5;
handle_fp_ex_opa:
ADDIK r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
andi r3, r4, 0x1F;
ADDK r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
ADDK r3, r3, r3;
ADDK r5, r3, r3;
ADDK r5, r5, r3;
ADDK r5, r5, r6;
bra r5;
handle_fp_ex_done:
ori r5, r0, 6; /* Set exception number back to 6 */
BRI handle_other_ex_tail;
fp_ex_unhandled:
bri 0;
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
ex_handler_done:
POP_R17;
POP_MSR;
POP_REG(3);
POP_REG(4);
POP_REG(5);
POP_REG(6);
ADDIK r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
rted r17, 0
nop
ex_handler_unhandled:
bri 0 /* UNHANDLED. TRAP HERE */
.end _hw_exception_handler
#ifndef NO_UNALIGNED_EXCEPTIONS
/*
* hw_exception_handler Jump Table
* - Contains code snippets for each register that caused the unaligned exception.
* - Hence exception handler is NOT self-modifying
* - Separate table for load exceptions and store exceptions.
* - Each table is of size: (8 * 32) = 256 bytes
*/
.section .text
.align 4
lw_table:
lw_r0: R3_TO_LWREG (0);
lw_r1: LWREG_NOP;
lw_r2: R3_TO_LWREG (2);
lw_r3: R3_TO_LWREG_V (3);
lw_r4: R3_TO_LWREG_V (4);
lw_r5: R3_TO_LWREG_V (5);
lw_r6: R3_TO_LWREG_V (6);
lw_r7: R3_TO_LWREG (7);
lw_r8: R3_TO_LWREG (8);
lw_r9: R3_TO_LWREG (9);
lw_r10: R3_TO_LWREG (10);
lw_r11: R3_TO_LWREG (11);
lw_r12: R3_TO_LWREG (12);
lw_r13: R3_TO_LWREG (13);
lw_r14: R3_TO_LWREG (14);
lw_r15: R3_TO_LWREG (15);
lw_r16: R3_TO_LWREG (16);
lw_r17: LWREG_NOP;
lw_r18: R3_TO_LWREG (18);
lw_r19: R3_TO_LWREG (19);
lw_r20: R3_TO_LWREG (20);
lw_r21: R3_TO_LWREG (21);
lw_r22: R3_TO_LWREG (22);
lw_r23: R3_TO_LWREG (23);
lw_r24: R3_TO_LWREG (24);
lw_r25: R3_TO_LWREG (25);
lw_r26: R3_TO_LWREG (26);
lw_r27: R3_TO_LWREG (27);
lw_r28: R3_TO_LWREG (28);
lw_r29: R3_TO_LWREG (29);
lw_r30: R3_TO_LWREG (30);
lw_r31: R3_TO_LWREG (31);
sw_table:
sw_r0: SWREG_TO_R3 (0);
sw_r1: SWREG_NOP;
sw_r2: SWREG_TO_R3 (2);
sw_r3: SWREG_TO_R3_V (3);
sw_r4: SWREG_TO_R3_V (4);
sw_r5: SWREG_TO_R3_V (5);
sw_r6: SWREG_TO_R3_V (6);
sw_r7: SWREG_TO_R3 (7);
sw_r8: SWREG_TO_R3 (8);
sw_r9: SWREG_TO_R3 (9);
sw_r10: SWREG_TO_R3 (10);
sw_r11: SWREG_TO_R3 (11);
sw_r12: SWREG_TO_R3 (12);
sw_r13: SWREG_TO_R3 (13);
sw_r14: SWREG_TO_R3 (14);
sw_r15: SWREG_TO_R3 (15);
sw_r16: SWREG_TO_R3 (16);
sw_r17: SWREG_NOP;
sw_r18: SWREG_TO_R3 (18);
sw_r19: SWREG_TO_R3 (19);
sw_r20: SWREG_TO_R3 (20);
sw_r21: SWREG_TO_R3 (21);
sw_r22: SWREG_TO_R3 (22);
sw_r23: SWREG_TO_R3 (23);
sw_r24: SWREG_TO_R3 (24);
sw_r25: SWREG_TO_R3 (25);
sw_r26: SWREG_TO_R3 (26);
sw_r27: SWREG_TO_R3 (27);
sw_r28: SWREG_TO_R3 (28);
sw_r29: SWREG_TO_R3 (29);
sw_r30: SWREG_TO_R3 (30);
sw_r31: SWREG_TO_R3 (31);
/* Temporary data structures used in the handler */
.section .data
.align DATAALIGN
ex_tmp_data_loc_0:
.byte 0
ex_tmp_data_loc_1:
.byte 0
ex_tmp_data_loc_2:
.byte 0
ex_tmp_data_loc_3:
.byte 0
ex_reg_op:
.byte 0
#endif /* ! NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
/*
* FP exception decode jump table.
* - Contains code snippets for each register that could have been a source operand for an excepting FP instruction
* - Hence exception handler is NOT self-modifying
* - Separate table for opA and opB
* - Each table is of size: (12 * 32) = 384 bytes
*/
.section .text
.align 4
fp_table_opa:
opa_r0: FP_EX_OPA_SAVE (0);
opa_r1: FP_EX_UNHANDLED;
opa_r2: FP_EX_OPA_SAVE (2);
opa_r3: FP_EX_OPA_SAVE_V (3);
opa_r4: FP_EX_OPA_SAVE_V (4);
opa_r5: FP_EX_OPA_SAVE_V (5);
opa_r6: FP_EX_OPA_SAVE_V (6);
opa_r7: FP_EX_OPA_SAVE (7);
opa_r8: FP_EX_OPA_SAVE (8);
opa_r9: FP_EX_OPA_SAVE (9);
opa_r10: FP_EX_OPA_SAVE (10);
opa_r11: FP_EX_OPA_SAVE (11);
opa_r12: FP_EX_OPA_SAVE (12);
opa_r13: FP_EX_OPA_SAVE (13);
opa_r14: FP_EX_UNHANDLED;
opa_r15: FP_EX_UNHANDLED;
opa_r16: FP_EX_UNHANDLED;
opa_r17: FP_EX_UNHANDLED;
opa_r18: FP_EX_OPA_SAVE (18);
opa_r19: FP_EX_OPA_SAVE (19);
opa_r20: FP_EX_OPA_SAVE (20);
opa_r21: FP_EX_OPA_SAVE (21);
opa_r22: FP_EX_OPA_SAVE (22);
opa_r23: FP_EX_OPA_SAVE (23);
opa_r24: FP_EX_OPA_SAVE (24);
opa_r25: FP_EX_OPA_SAVE (25);
opa_r26: FP_EX_OPA_SAVE (26);
opa_r27: FP_EX_OPA_SAVE (27);
opa_r28: FP_EX_OPA_SAVE (28);
opa_r29: FP_EX_OPA_SAVE (29);
opa_r30: FP_EX_OPA_SAVE (30);
opa_r31: FP_EX_OPA_SAVE (31);
fp_table_opb:
opb_r0: FP_EX_OPB_SAVE (0);
opb_r1: FP_EX_UNHANDLED;
opb_r2: FP_EX_OPB_SAVE (2);
opb_r3: FP_EX_OPB_SAVE_V (3);
opb_r4: FP_EX_OPB_SAVE_V (4);
opb_r5: FP_EX_OPB_SAVE_V (5);
opb_r6: FP_EX_OPB_SAVE_V (6);
opb_r7: FP_EX_OPB_SAVE (7);
opb_r8: FP_EX_OPB_SAVE (8);
opb_r9: FP_EX_OPB_SAVE (9);
opb_r10: FP_EX_OPB_SAVE (10);
opb_r11: FP_EX_OPB_SAVE (11);
opb_r12: FP_EX_OPB_SAVE (12);
opb_r13: FP_EX_OPB_SAVE (13);
opb_r14: FP_EX_UNHANDLED;
opb_r15: FP_EX_UNHANDLED;
opb_r16: FP_EX_UNHANDLED;
opb_r17: FP_EX_UNHANDLED;
opb_r18: FP_EX_OPB_SAVE (18);
opb_r19: FP_EX_OPB_SAVE (19);
opb_r20: FP_EX_OPB_SAVE (20);
opb_r21: FP_EX_OPB_SAVE (21);
opb_r22: FP_EX_OPB_SAVE (22);
opb_r23: FP_EX_OPB_SAVE (23);
opb_r24: FP_EX_OPB_SAVE (24);
opb_r25: FP_EX_OPB_SAVE (25);
opb_r26: FP_EX_OPB_SAVE (26);
opb_r27: FP_EX_OPB_SAVE (27);
opb_r28: FP_EX_OPB_SAVE (28);
opb_r29: FP_EX_OPB_SAVE (29);
opb_r30: FP_EX_OPB_SAVE (30);
opb_r31: FP_EX_OPB_SAVE (31);
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
#if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE)
/* This is where we store the opA and opB of the last excepting FP instruction */
.section .data
.align DATAALIGN
.global mb_fpex_op_a
.global mb_fpex_op_b
mb_fpex_op_a:
INTPTR_DATAITEM 0
mb_fpex_op_b:
INTPTR_DATAITEM 0
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
/* This is where we store the register used to check which exception occurred */
.section .data
.align DATAALIGN
mb_sp_save_r3:
INTPTR_DATAITEM 0
#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
/* The exception vector table */
.section .data
.align DATAALIGN
.global MB_ExceptionVectorTable
MB_ExceptionVectorTable:
INTPTR_DATAITEM XNullHandler
INTPTR_DATAITEM 0 /* -- FSL Exception -- */
INTPTR_DATAITEM XNullHandler
INTPTR_DATAITEM 1 /* -- Unaligned Access Exception -- */
INTPTR_DATAITEM XNullHandler
INTPTR_DATAITEM 2 /* -- Illegal Opcode Exception -- */
INTPTR_DATAITEM XNullHandler
INTPTR_DATAITEM 3 /* -- Instruction Bus Exception -- */
INTPTR_DATAITEM XNullHandler
INTPTR_DATAITEM 4 /* -- Data Bus Exception -- */
INTPTR_DATAITEM XNullHandler
INTPTR_DATAITEM 5 /* -- Div-by-0 Exception -- */
INTPTR_DATAITEM XNullHandler
INTPTR_DATAITEM 6 /* -- FPU Exception -- */
INTPTR_DATAITEM XNullHandler
INTPTR_DATAITEM 7 /* -- MMU Exceptions -- */
#else /* Dummy exception handler, in case exceptions are not present in the processor */
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
_hw_exception_handler:
bri 0;
.end _hw_exception_handler
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/inbyte.c
+11
View File
@@ -0,0 +1,11 @@
#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
#endif
char inbyte(void);
#ifdef __cplusplus
}
#endif
char inbyte(void) {
}
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/mb_interface.h
+470
View File
@@ -0,0 +1,470 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file mb_interface.h
*
* @addtogroup microblaze_pseudo_asm_macro Microblaze Pseudo-asm Macros and Interrupt Handling APIs
*
* Microblaze BSP includes macros to provide convenient access to various registers
* in the MicroBlaze processor. Some of these macros are very useful within
* exception handlers for retrieving information about the exception.Also,
* the interrupt handling functions help manage interrupt handling on MicroBlaze
* processor devices.To use these functions, include the header file
* mb_interface.h in your source code
*
* @{
*
******************************************************************************/
#ifndef _MICROBLAZE_INTERFACE_H_
#define _MICROBLAZE_INTERFACE_H_
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#ifdef __cplusplus
extern "C" {
#endif
extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); /* Register exception handler */
extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
extern void microblaze_invalidate_icache_range(UINTPTR cacheaddr, u32 len); /* Invalidate a part of the icache */
extern void microblaze_invalidate_dcache_range(UINTPTR cacheaddr, u32 len); /* Invalidate a part of the dcache */
extern void microblaze_flush_dcache_range(UINTPTR cacheaddr, u32 len); /* Flush a part of the dcache */
extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */
extern void microblaze_flush_cache_ext(void); /* Flush cache ext */
extern void microblaze_flush_cache_ext_range(UINTPTR cacheaddr,
u32 len); /* Flush cache ext range */
extern void microblaze_invalidate_cache_ext_range(UINTPTR cacheaddr,
u32 len); /* Invalidate cache ext range */
/* Deprecated */
extern void microblaze_update_icache (s32 , s32 , s32 ) __attribute__((deprecated));
extern void microblaze_init_icache_range (s32 , s32 ) __attribute__((deprecated));
extern void microblaze_update_dcache (s32 , s32 , s32 ) __attribute__((deprecated));
extern void microblaze_init_dcache_range (s32 , s32 ) __attribute__((deprecated));
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
/* FSL Access Macros */
/* Blocking Data Read and Write to FSL no. id */
#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Data Read and Write to FSL no. id */
#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
/* Blocking Control Read and Write to FSL no. id */
#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Control Read and Write to FSL no. id */
#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
/* Polling versions of FSL access macros. This makes the FSL access interruptible */
#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
/* FSL valid and error check macros. */
#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
"andi\t%0,%0,0x10" : "=d" (error))
/* Pseudo assembler instructions */
#define clz(v) ({ u32 _rval; \
__asm__ __volatile__ ( \
"clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
); \
_rval; \
})
#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
#define mb_hibernate() ({ __asm__ __volatile__ ("hibernate\t"); })
#define mb_suspend() ({ __asm__ __volatile__ ("suspend\t"); })
#define mb_swapb(v) ({ u32 _rval; \
__asm__ __volatile__ ( \
"swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mb_swaph(v) ({ u32 _rval; \
__asm__ __volatile__ ( \
"swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
/** @name Microblaze pseudo-asm macros
*
* The following is a summary of the MicroBlaze processor pseudo-asm macros.
* @{
*/
/**
Return value from the general purpose register (GPR) rn.
@param rn General purpose register to be read.
*/
#define mfgpr(rn) ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the MSR.
@param None
*/
#define mfmsr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rmsr\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the Exception Address Register (EAR).
@param None
*/
#define mfear() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfeare() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfse\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the Exception Status Register (ESR).
@param None
*/
#define mfesr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,resr\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the Floating Point Status (FPS).
@param None
*/
#define mffsr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rfsr\n" : "=d"(_rval) \
); \
_rval; \
})
/*@}*/
#define mfpvr(rn) ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpvre(rn) ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfse\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfbtr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rbtr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfedr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,redr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpid() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpid\n" : "=d"(_rval)\
); \
_rval; \
})
#define mfzpr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rzpr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbx() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbx\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlblo() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlblo\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbhi() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbhi\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfslr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rslr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfshr() ({ UINTPTR _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rshr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
"or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
); \
})
#define mtmsr(v) ({ __asm__ __volatile__ ( \
"mts\trmsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtfsr(v) ({ __asm__ __volatile__ ( \
"mts\trfsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtpid(v) ({ __asm__ __volatile__ ( \
"mts\trpid,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtzpr(v) ({ __asm__ __volatile__ ( \
"mts\trzpr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlblo(v) ({ __asm__ __volatile__ ( \
"mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbhi(v) ({ __asm__ __volatile__ ( \
"mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbsx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtslr(v) ({ __asm__ __volatile__ ( \
"mts\trslr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtshr(v) ({ __asm__ __volatile__ ( \
"mts\trshr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define lwx(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lwr(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lwea(lladdr) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lwea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define lhur(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lhuea(lladdr) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lhuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define lbur(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lbuea(lladdr) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lbuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define swx(address, data) ({ __asm__ __volatile__ ( \
"swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define swr(address, data) ({ __asm__ __volatile__ ( \
"swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define swea(lladdr, data) ({ __asm__ __volatile__ ( \
"swea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define shr(address, data) ({ __asm__ __volatile__ ( \
"shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define shea(lladdr, data) ({ __asm__ __volatile__ ( \
"shea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define sbr(address, data) ({ __asm__ __volatile__ ( \
"sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define sbea(lladdr, data) ({ __asm__ __volatile__ ( \
"sbea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define microblaze_getfpex_operand_a() ({ \
extern u32 mb_fpex_op_a; \
mb_fpex_op_a; \
})
#define microblaze_getfpex_operand_b() ({ \
extern u32 mb_fpex_op_b; \
mb_fpex_op_b; \
})
/* Deprecated MicroBlaze FSL macros */
#define microblaze_bread_datafsl(val, id) getfsl(val,id)
#define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
#ifdef __cplusplus
}
#endif
#endif // _MICROBLAZE_INTERFACE_H_
/**
* @} End of "addtogroup microblaze_pseudo_asm_macro".
*/
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_disable_dcache.S
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/******************************************************************************
*
* Copyright (C) 2008 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
* File : microblaze_disable_dcache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Disable the L1 dcache on the microblaze.
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
.text
.globl microblaze_disable_dcache
.ent microblaze_disable_dcache
.align 2
microblaze_disable_dcache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
ADDIK r1, r1, -8
SI r15, r1, 0
BRLID r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/
nop
LI r15, r1, 0
ADDIK r1, r1, 8
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
rtsd r15, 8
msrclr r0, 0x80
#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */
ADDIK r1, r1, -8
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
SI r15, r1, 0
BRLID r15, microblaze_flush_dcache
nop
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
mfs r11, rmsr
andi r11, r11, ~(0x80)
mts rmsr, r11
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
LI r15, r1, 0
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
ADDIK r1, r1, 8
rtsd r15, 8
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_disable_dcache
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_disable_exceptions.S
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* Disable exceptions on microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
.text
.globl microblaze_disable_exceptions
.ent microblaze_disable_exceptions
.align 2
microblaze_disable_exceptions:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrclr r0, 0x100
#else
mfs r4, rmsr;
andi r4, r4, ~(0x100); /* Turn OFF the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
#endif
.end microblaze_disable_exceptions
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_disable_icache.S
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* File : microblaze_disable_icache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Disable L1 icache on the microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
.text
.globl microblaze_disable_icache
.ent microblaze_disable_icache
.align 2
microblaze_disable_icache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrclr r0, 0x20
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
#Read the MSR register
mfs r8, rmsr
#Clear the icache enable bit
andi r8, r8, ~(0x20)
#Save the MSR register
mts rmsr, r8
#Return
rtsd r15, 8
nop
#endif
.end microblaze_disable_icache
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_disable_interrupts.S
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
* @file microblaze_disable_interrupts.S
*
* @addtogroup microblaze_pseudo_asm_macro
* @{
* <h2> microblaze_disable_interrupts.S </h2>
* - API to disable Interrupts: void microblaze_disable_interrupts(void)
*
* This API Disables interrupts on the MicroBlaze processor. It can be
* called when entering a critical section of code where a context switch is
* undesirable.
*
* <pre>
* File : microblaze_disable_interrupts.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Disable interrupts on the microblaze.
* </pre>
*
******************************************************************************/
#include "xparameters.h"
.text
.globl microblaze_disable_interrupts
.ent microblaze_disable_interrupts
.align 2
microblaze_disable_interrupts:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrclr r0, 0x2
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
#Read the MSR register
mfs r12, rmsr
#Clear the interrupt enable bit
andi r12, r12, ~(0x2)
#Save the MSR register
mts rmsr, r12
#Return
rtsd r15, 8
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_disable_interrupts
/**
* @} End of "addtogroup microblaze_pseudo_asm_macro".
*/
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_enable_dcache.S
+63
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* File : microblaze_enable_dcache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Enable L1 dcache on the microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
.text
.globl microblaze_enable_dcache
.ent microblaze_enable_dcache
.align 2
microblaze_enable_dcache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrset r0, 0x80
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
#Read the MSR register
mfs r8, rmsr
#Set the interrupt enable bit
ori r8, r8, 0x80
#Save the MSR register
mts rmsr, r8
#Return
rtsd r15, 8
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_dcache
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_enable_exceptions.S
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* Enable exceptions on microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
.text
.globl microblaze_enable_exceptions
.ent microblaze_enable_exceptions
.align 2
microblaze_enable_exceptions:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8;
msrset r0, 0x100
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
mfs r4, rmsr;
ori r4, r4, 0x100; /* Turn ON the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_exceptions
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_enable_icache.S
+61
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* File : microblaze_enable_icache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Enable icache on the microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
.text
.globl microblaze_enable_icache
.ent microblaze_enable_icache
.align 2
microblaze_enable_icache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrset r0, 0x20
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
#Read the MSR register
mfs r8, rmsr
#Set the interrupt enable bit
ori r8, r8, 0x20
#Save the MSR register
mts rmsr, r8
#Return
rtsd r15, 8
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_icache
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_enable_interrupts.S
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/******************************************************************************
*
* Copyright (C) 2004 - 2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
* @file microblaze_enable_interrupts.S
*
* @addtogroup microblaze_pseudo_asm_macro
* @{
* <h2> microblaze_enable_interrupts.S </h2>
* - API to Enable Interrupts: void microblaze_enable_interrupts(void)
*
* This API Enables interrupts on the MicroBlaze processor. When the MicroBlaze
* processor starts up, interrupts are disabled. Interrupts must be explicitly
* turned on using this function.
*
* <pre>
*
* File : microblaze_enable_interrupts.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Enable interrupts on the microblaze.
* </pre>
*
******************************************************************************/
#include "xparameters.h"
.text
.globl microblaze_enable_interrupts
.ent microblaze_enable_interrupts
.align 2
microblaze_enable_interrupts:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrset r0, 0x2
nop
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
#Read the MSR register
mfs r12, rmsr
#Set the interrupt enable bit
ori r12, r12, 0x2
#Save the MSR register
mts rmsr, r12
#Return
rtsd r15, 8
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_interrupts
/**
* @} End of "addtogroup microblaze_pseudo_asm_macro".
*/
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_exception_handler.c
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_exception_handler.c
*
* This file contains exception handler registration routines for
* the MicroBlaze processor.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 06/24/04 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "microblaze_exceptions_i.h"
#include "microblaze_exceptions_g.h"
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[];
/****************************************************************************/
/*****************************************************************************/
/**
*
* Registers an exception handler for the MicroBlaze. The
* argument provided in this call as the DataPtr is used as the argument
* for the handler when it is called.
*
* @param ExceptionId is the id of the exception to register this handler
* for.
* @param Top level handler.
* @param DataPtr is a reference to data that will be passed to the handler
* when it gets called.
* @return None.
*
* @note
*
* None.
*
****************************************************************************/
void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr)
{
MB_ExceptionVectorTable[ExceptionId].Handler = Handler;
MB_ExceptionVectorTable[ExceptionId].CallBackRef = DataPtr;
}
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_exceptions_g.h
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1.3
* DO NOT EDIT.
*
* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Exception Handling Header for MicroBlaze Processor
*
*******************************************************************/
#define MICROBLAZE_EXCEPTIONS_ENABLED 1
#define MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_exceptions_i.h
+83
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_exceptions_i.h
*
* This header file contains defines for structures used by the microblaze
* hardware exception handler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00a 06/24/04 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */
#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
Xil_ExceptionHandler Handler;
void *CallBackRef;
} MB_ExceptionVectorTableEntry;
/* Exception IDs */
#define XEXC_ID_FSL 0U
#define XEXC_ID_UNALIGNED_ACCESS 1U
#define XEXC_ID_ILLEGAL_OPCODE 2U
#define XEXC_ID_M_AXI_I_EXCEPTION 3U
#define XEXC_ID_IPLB_EXCEPTION 3U
#define XEXC_ID_M_AXI_D_EXCEPTION 4U
#define XEXC_ID_DPLB_EXCEPTION 4U
#define XEXC_ID_DIV_BY_ZERO 5U
#define XEXC_ID_FPU 6U
#define XEXC_ID_STACK_VIOLATION 7U
#define XEXC_ID_MMU 7U
void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_flush_cache_ext.S
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/******************************************************************************
*
* Copyright (C) 2008 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_flush_cache_ext()
*
* Flush the entire L2 Cache
*
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
#define CACHEABLE_REGION_SIZE (XPAR_MICROBLAZE_DCACHE_HIGHADDR - XPAR_MICROBLAZE_DCACHE_BASEADDR)
.text
.globl microblaze_flush_cache_ext
.ent microblaze_flush_cache_ext
.align 2
microblaze_flush_cache_ext:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
ADDIK r6, r0, CACHEABLE_REGION_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
ANDI r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_start:
wdc.ext.flush r5, r6
#if defined (__arch64__)
addlik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
beagei r6, Loop_start
#else
bgtid r6,Loop_start
addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
#endif
#endif
rtsd r15, 8
nop
.end microblaze_flush_cache_ext
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_flush_cache_ext_range.S
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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len)
*
*Flush a L2 Cache range
*
*Parameters:
* 'cacheaddr' - address in the L2 cache where the flush begins
* 'len ' - length (in bytes) worth of L2 cache to be flushed
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
.text
.globl microblaze_flush_cache_ext_range
.ent microblaze_flush_cache_ext_range
.align 2
microblaze_flush_cache_ext_range:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
beqi r6, Loop_done
ADDIK r6, r6, -1
ADD r6, r5, r6
ANDI r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
ANDI r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
RSUBK r6, r5, r6
Loop_start:
wdc.ext.flush r5, r6
#if defined (__arch64__ )
addlik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
beagei r6, Loop_start
#else
bneid r6, Loop_start
addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
#endif
Loop_done:
#endif
rtsd r15, 8
nop
.end microblaze_flush_cache_ext_range
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_flush_dcache.S
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/******************************************************************************
*
* Copyright (C) 2008 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* microblaze_flush_dcache()
*
* Flush the L1 DCache
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_flush_dcache
.ent microblaze_flush_dcache
.align 2
microblaze_flush_dcache:
#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */
ADDIK r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
L_start:
wdc.flush r5, r0 /* Flush the Cache */
CMPU r18, r5, r6 /* Are we at the end? */
BLEI r18, L_done
#if defined (__arch64__ )
addlik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
BRI L_start
#else
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#endif
L_done:
#endif
rtsd r15, 8 /* Return */
nop
.end microblaze_flush_dcache
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_flush_dcache_range.S
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/******************************************************************************
*
* Copyright (C) 2008 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_flush_dcache_range (unsigned int cacheaddr, unsigned int len)
*
* Flush a L1 DCache range
*
* Parameters:
* 'cacheaddr' - address in the Dcache where the flush begins
* 'len ' - length (in bytes) worth of Dcache to be flushed
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#define MB_HAS_WRITEBACK_SET 0
#else
#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#endif
.text
.globl microblaze_flush_dcache_range
.ent microblaze_flush_dcache_range
.align 2
microblaze_flush_dcache_range:
#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
beqi r6, L_done /* Skip loop if size is zero */
ADD r6, r5, r6 /* Compute end address */
ADDIK r6, r6, -1
ANDI r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
ANDI r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
L_start:
CMPU r18, r5, r6 /* Are we at the end? */
BLTI r18, L_done
wdc r5, r0 /* Invalidate the cache line */
#if defined (__arch64__ )
addlik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
breai L_start /* Branch to the beginning of the loop */
#else
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#endif
#else
RSUBK r6, r5, r6
/* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
L_start:
wdc.flush r5, r6 /* Flush the cache line */
#if defined (__arch64__ )
addlik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
beagei r6, L_start
#else
bneid r6, L_start
addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#endif
#endif
L_done:
rtsd r15, 8
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
#else
rtsd r15, 8 /* Return */
nop
#endif
.end microblaze_flush_dcache_range
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_init_dcache_range.S
+82
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/******************************************************************************
*
* Copyright (C) 2006 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_init_dcache_range (unsigned int cache_start, unsigned int cache_len)
*
* Invalidate dcache on the microblaze
*
* Parameters:
* 'cache_start' - address in the Dcache where invalidation begins
* 'cache_len' - length (in bytes) worth of Dcache to be invalidated
*
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_init_dcache_range
.ent microblaze_init_dcache_range
.align 2
microblaze_init_dcache_range:
#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
mfs r9, rmsr /* Disable Dcache and interrupts before invalidating */
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
add r6, r5, r6 /* Compute end */
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
L_start:
wdc r5, r0 /* Invalidate the Cache (delay slot) */
cmpu r18, r5, r6 /* Are we at the end ? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
mts rmsr, r9
#else
rtsd r15, 8 /* Return */
nop
#endif
.end microblaze_init_dcache_range
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_init_icache_range.S
+83
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/******************************************************************************
*
* Copyright (C) 2006 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* microblaze_init_icache_range (unsigned int cache_start, unsigned int cache_len)
*
* Invalidate icache on the microblaze
*
* Parameters:
* 'cache_start' - address in the Icache where invalidation begins
* 'cache_len' - length (in bytes) worth of Icache to be invalidated
*
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
.text
.globl microblaze_init_icache_range
.ent microblaze_init_icache_range
.align 2
microblaze_init_icache_range:
#if (XPAR_MICROBLAZE_USE_ICACHE==1) && (XPAR_MICROBLAZE_ALLOW_ICACHE_WR==1)
mfs r9, rmsr /* Disable Icache and interrupts before invalidating */
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
add r6, r5, r6 /* Compute end */
andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
L_start:
wic r5, r0 /* Invalidate the Cache (delay slot) */
cmpu r18, r5, r6 /* Are we at the end ? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
mts rmsr, r9
#else
rtsd r15, 8 /* Return */
nop
#endif
.end microblaze_init_icache_range
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_instructions.h
+118
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/******************************************************************************
*
* Copyright (C) 2018-2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_instructions.h
*
* It provides wrapper macros to call 32/64 bit variant of specific
* arithmetic/logical instructions, based on the processor in execution.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.8 mus 10/09/18 First release
*
*
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_INSTRUCTIONS_H /* prevent circular inclusions */
#define MICROBLAZE_INSTRUCTIONS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__arch64__)
#define ADDIK addlik
#define ADDK addlk
#define ADDI addli
#define ADD addl
#define ANDI andli
#define SUBK sublk
#define RSUBK rsublk
#define ORI orli
#define LI lli
#define LOAD ll
#define SI sli
#define STORE sl
#define BRLID brealid
#define BGTID beageid
#define BGEI beagei
#define BNEID beaneid
#define BLTI bealti
#define CMPU cmplu
#define BRID breaid
#define BNEID beaneid
#define BLEI bealei
#define BEQI beaeqi
#define BRI breai
#define XORI xorli
#define BNEI beanei
#define OR orl
#define BRALID brealid
#define XOR xorl
#else
#define ADDIK addik
#define ADDK addk
#define ADDI addi
#define ADD add
#define ANDI andi
#define SUBK subk
#define RSUBK rsubk
#define ORI ori
#define LI lwi
#define LOAD lw
#define SI swi
#define STORE sw
#define BRLID brlid
#define BGTID bgtid
#define BGEI bgei
#define BNEID bneid
#define BLTI blti
#define CMPU cmpu
#define BRID brid
#define BNEID bneid
#define BLEI blei
#define BEQI beqi
#define BRI bri
#define XORI xori
#define BNEI bnei
#define OR or
#define BRALID bralid
#define XOR xor
#endif
#ifdef __cplusplus
}
#endif
#endif /* MICROBLAZE_INSTRUCTIONS_H */
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_interrupt_handler.c
+115
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_interrupt_handler.c
*
* This file contains the standard interrupt handler for the MicroBlaze processor.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_exception.h"
#include "microblaze_interrupts_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void __interrupt_handler (void) __attribute__ ((interrupt_handler));
void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr);
/************************** Variable Definitions *****************************/
extern MB_InterruptVectorTableEntry MB_InterruptVectorTable[MB_INTERRUPT_VECTOR_TABLE_ENTRIES];
/*****************************************************************************/
/**
*
* This function is the standard interrupt handler used by the MicroBlaze processor.
* It saves all volatile registers, calls the users top level interrupt handler.
* When this returns, it restores all registers, and returns using a rtid instruction.
*
* @param
*
* None
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void __interrupt_handler(void)
{
/* The compiler saves all volatiles and the MSR */
(void)MB_InterruptVectorTable[0].Handler(MB_InterruptVectorTable[0].CallBackRef);
/* The compiler restores all volatiles and MSR, and returns from interrupt */
}
/*****************************************************************************/
/**
*
* Registers a top-level interrupt handler for the MicroBlaze. The
* argument provided in this call as the DataPtr is used as the argument
* for the handler when it is called.
*
* @param Handler: Top level handler.
* @param DataPtr: a reference to data that will be passed to the handler
* when it gets called.
* @return None.
*
*
****************************************************************************/
void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr)
{
MB_InterruptVectorTable[0].Handler = Handler;
MB_InterruptVectorTable[0].CallBackRef = DataPtr;
}
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_interrupts_g.c
+51
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1.3
* DO NOT EDIT.
*
* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Interrupt Handler Table for MicroBlaze Processor
*
*******************************************************************/
#include "microblaze_interrupts_i.h"
#include "xparameters.h"
extern void XIntc_DeviceInterruptHandler (void *);
/*
* The interrupt handler table for microblaze processor
*/
MB_InterruptVectorTableEntry MB_InterruptVectorTable[] =
{
{ XIntc_DeviceInterruptHandler,
(void*) XPAR_AXI_INTC_DEVICE_ID}
};
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_interrupts_i.h
+73
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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_interrupts_i.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* High-level driver functions are defined in xintc.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
XInterruptHandler Handler;
void *CallBackRef;
} MB_InterruptVectorTableEntry;
#define MB_INTERRUPT_VECTOR_TABLE_ENTRIES 1
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_invalidate_cache_ext.S
+69
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/******************************************************************************
*
* Copyright (C) 2008 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_invalidate_cache_ext()
*
*Invalidate the entire L2 Cache
*
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
#define CACHEABLE_REGION_SIZE (XPAR_MICROBLAZE_DCACHE_HIGHADDR - XPAR_MICROBLAZE_DCACHE_BASEADDR)
.text
.globl microblaze_invalidate_cache_ext
.ent microblaze_invalidate_cache_ext
.align 2
microblaze_invalidate_cache_ext:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN))
ADDIK r6, r0, CACHEABLE_REGION_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
ANDI r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_start:
wdc.ext.clear r5, r6
#if defined (__arch64__ )
addlik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
beagei r6, Loop_start
#else
bgtid r6,Loop_start
addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
#endif
#endif
rtsd r15, 8
nop
.end microblaze_invalidate_cache_ext
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_invalidate_cache_ext_range.S
+77
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/******************************************************************************
*
* Copyright (C) 2008 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len)
*
*Invalidate an L2 cache range
*
*Parameters:
* 'cacheaddr' - address in the L2 cache where invalidation begins
* 'len ' - length (in bytes) worth of Dcache to be invalidated
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
.text
.globl microblaze_invalidate_cache_ext_range
.ent microblaze_invalidate_cache_ext_range
.align 2
microblaze_invalidate_cache_ext_range:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
beqi r6, Loop_done
ADD r6, r5, r6
ADDIK r6, r6, -1
ANDI r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
ANDI r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
RSUBK r6, r5, r6
Loop_start:
wdc.ext.clear r5, r6
#if defined (__arch64__ )
addlik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
beagei r6, Loop_start
#else
bneid r6, Loop_start
addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
#endif
Loop_done:
#endif
rtsd r15, 8
nop
.end microblaze_invalidate_cache_ext_range
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_invalidate_dcache.S
+92
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@@ -0,0 +1,92 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_invalidate_dcache()
*
* Invalidate the entire L1 DCache
*
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_dcache
.ent microblaze_invalidate_dcache
.align 2
microblaze_invalidate_dcache:
#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
ADDIK r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
L_start:
wdc r5, r0 /* Invalidate the Cache */
CMPU r18, r5, r6 /* Are we at the end? */
BLEI r18, L_done
#if defined (__arch64__ )
addlik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
breai L_start
#else
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#endif
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
#else
rtsd r15, 8 /* Return */
nop
#endif
.end microblaze_invalidate_dcache
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_invalidate_dcache_range.S
+124
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/******************************************************************************
*
* Copyright (C) 2008 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
*
* Invalidate a Dcache range
*
* Parameters:
* 'cacheaddr' - address in the Dcache where invalidation begins
* 'len ' - length (in bytes) worth of Dcache to be invalidated
*
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#define MB_HAS_WRITEBACK_SET 0
#else
#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#endif
.text
.globl microblaze_invalidate_dcache_range
.ent microblaze_invalidate_dcache_range
.align 2
microblaze_invalidate_dcache_range:
#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
BEQI r6, L_done /* Skip loop if size is zero */
ADD r6, r5, r6 /* Compute end address */
ADDIK r6, r6, -1
ANDI r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
ANDI r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
L_start:
CMPU r18, r5, r6 /* Are we at the end? */
BLTI r18, L_done
wdc r5, r0
#if defined (__arch64__ )
addlik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
breai L_start /* Branch to the beginning of the loop */
#else
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#endif
#else
RSUBK r6, r5, r6
/* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
L_start:
wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */
#if defined (__arch64__ )
addlik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
beagei r6, L_start
#else
bneid r6, L_start
addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#endif
#endif
L_done:
rtsd r15, 8
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
#else
rtsd r15, 8
nop
#endif
.end microblaze_invalidate_dcache_range
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_invalidate_icache.S
+93
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/******************************************************************************
*
* Copyright (C) 2008 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* microblaze_invalidate_icache()
*
* Invalidate the entire ICache
*
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_icache
.ent microblaze_invalidate_icache
.align 2
microblaze_invalidate_icache:
#if (XPAR_MICROBLAZE_USE_ICACHE==1) && (XPAR_MICROBLAZE_ALLOW_ICACHE_WR==1)
#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
ADDIK r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */
ADDIK r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */
L_start:
wic r5, r0 /* Invalidate the Cache */
CMPU r18, r5, r6 /* Are we at the end? */
BLEI r18, L_done
#if defined (__arch64__ )
addlik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the address by 4 */
breai L_start
#else
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#endif
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
#else
rtsd r15, 8 /* Return */
nop
#endif
.end microblaze_invalidate_icache
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_invalidate_icache_range.S
+103
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/******************************************************************************
*
* Copyright (C) 2008 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len)
*
* Invalidate an ICache range
*
* Parameters:
* 'cacheaddr' - address in the Icache where invalidation begins
* 'len' - length (in bytes) worth of Icache to be invalidated
*
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_icache_range
.ent microblaze_invalidate_icache_range
.align 2
microblaze_invalidate_icache_range:
#if (XPAR_MICROBLAZE_USE_ICACHE==1) && (XPAR_MICROBLAZE_ALLOW_ICACHE_WR==1)
#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
BEQI r6, L_done /* Skip loop if size is zero */
ADD r6, r5, r6 /* Compute end address */
ADDIK r6, r6, -1
ANDI r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */
ANDI r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */
L_start:
CMPU r18, r5, r6 /* Are we at the end? */
BLTI r18, L_done
wic r5, r0 /* Invalidate the cache line */
#if defined (__arch64__ )
addlik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the address by 4 */
breai L_start /* Branch to the beginning of the loop */
#else
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#endif
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
#else
rtsd r15, 8 /* Return */
nop
#endif
.end microblaze_invalidate_icache_range
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_scrub.S
+207
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_scrub ()
*
* Scrub LMB memory and all internal BRAMs (data cache, instruction cache,
* MMU UTLB and branch target cache) in MicroBlaze to reduce the possibility
* of an uncorrectable error when fault tolerance support is enabled.
*
* This routine assumes that the processor is in privileged mode when it is
* called, if the MMU is enabled.
*
* Call this routine regularly from a timer interrupt.
*
* Parameters:
* None
*
*
*******************************************************************************/
#include "xparameters.h"
/* Define if fault tolerance is used */
#ifdef XPAR_MICROBLAZE_FAULT_TOLERANT
#if XPAR_MICROBLAZE_FAULT_TOLERANT > 0
#define FAULT_TOLERANT
#endif
#endif
/* Define if LMB is used and can be scrubbed */
#if defined(XPAR_MICROBLAZE_D_LMB) && \
defined(XPAR_DLMB_CNTLR_BASEADDR) && \
defined(XPAR_DLMB_CNTLR_HIGHADDR)
#if XPAR_MICROBLAZE_D_LMB == 1
#define HAS_SCRUBBABLE_LMB
#define DLMB_MASK (XPAR_DLMB_CNTLR_HIGHADDR - XPAR_DLMB_CNTLR_BASEADDR)
#endif
#endif
/* Set default cache line lengths */
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
#endif
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
#endif
/* Define if internal Data Cache BRAMs are used */
#if defined(XPAR_MICROBLAZE_USE_DCACHE) && defined(XPAR_MICROBLAZE_DCACHE_BYTE_SIZE)
#if XPAR_MICROBLAZE_USE_DCACHE == 1 && XPAR_MICROBLAZE_DCACHE_BYTE_SIZE > 1024
#define HAS_BRAM_DCACHE
#define DCACHE_INCREMENT (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#define DCACHE_MASK (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE - 1)
#endif
#endif
/* Define if internal Instruction Cache BRAMs are used */
#if defined(XPAR_MICROBLAZE_USE_ICACHE) && defined(XPAR_MICROBLAZE_CACHE_BYTE_SIZE)
#if XPAR_MICROBLAZE_USE_ICACHE == 1 && XPAR_MICROBLAZE_CACHE_BYTE_SIZE > 1024
#define HAS_BRAM_ICACHE
#define ICACHE_INCREMENT (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
#define ICACHE_MASK (XPAR_MICROBLAZE_CACHE_BYTE_SIZE - 1)
#endif
#endif
/* Define if internal MMU UTLB BRAM is used */
#ifdef XPAR_MICROBLAZE_USE_MMU
#if XPAR_MICROBLAZE_USE_MMU > 1
#define HAS_BRAM_MMU_UTLB
#endif
#endif
/* Define if internal BTC BRAM is used, and match BTC clear to a complete cache scrub */
#if defined(XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE) && \
defined(XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE)
#if XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE == 1
#if XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE == 0 || \
XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE > 4
#define HAS_BRAM_BRANCH_TARGET_CACHE
#ifdef HAS_BRAM_DCACHE
#define BTC_MASK_D (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE/DCACHE_INCREMENT-1)
#else
#define BTC_MASK_D 256
#endif
#ifdef HAS_BRAM_ICACHE
#define BTC_MASK_I (XPAR_MICROBLAZE_CACHE_BYTE_SIZE/ICACHE_INCREMENT-1)
#else
#define BTC_MASK_I 256
#endif
#if BTC_MASK_D > BTC_MASK_I
#define BTC_MASK BTC_MASK_D
#else
#define BTC_MASK BTC_MASK_I
#endif
#endif
#endif
#endif
/* Define index offsets to persistent data used by this routine */
#define DLMB_INDEX_OFFSET 0
#define DCACHE_INDEX_OFFSET 4
#define ICACHE_INDEX_OFFSET 8
#define MMU_INDEX_OFFSET 12
#define BTC_CALL_COUNT_OFFSET 16
.text
.globl microblaze_scrub
.ent microblaze_scrub
.align 2
microblaze_scrub:
#ifdef FAULT_TOLERANT
la r6, r0, L_persistent_data /* Get pointer to data */
#ifdef HAS_SCRUBBABLE_LMB
L_dlmb:
lwi r5, r6, DLMB_INDEX_OFFSET /* Get dlmb index */
lw r7, r5, r0 /* Load and store */
sw r7, r5, r0
addik r5, r5, 4 /* Increment and save dlmb index */
andi r5, r5, DLMB_MASK
swi r5, r6, DLMB_INDEX_OFFSET
#endif /* HAS_SCRUBBABLE_LMB */
#ifdef HAS_BRAM_DCACHE
L_dcache:
lwi r5, r6, DCACHE_INDEX_OFFSET /* Get dcache line index */
wdc r5, r0 /* Invalidate data cache line */
addik r5, r5, DCACHE_INCREMENT /* Increment and save entry index */
andi r5, r5, DCACHE_MASK
swi r5, r6, DCACHE_INDEX_OFFSET
#endif /* HAS_BRAM_DCACHE */
#ifdef HAS_BRAM_ICACHE
L_icache:
lwi r5, r6, ICACHE_INDEX_OFFSET /* Get icache line index */
wic r5, r0 /* Invalidate data cache line */
addik r5, r5, ICACHE_INCREMENT /* Increment and save entry index */
andi r5, r5, ICACHE_MASK
swi r5, r6, ICACHE_INDEX_OFFSET
#endif /* HAS_BRAM_ICACHE */
#ifdef HAS_BRAM_MMU_UTLB
L_mmu:
lwi r5, r6, MMU_INDEX_OFFSET /* Get UTLB entry index */
mts rtlbx, r5 /* Access next entry in UTLB */
mts rtlbhi, r0 /* Clear the UTLB entry */
addik r5, r5, 1 /* Increment and save entry index */
andi r5, r5, 0x3F
swi r5, r6, MMU_INDEX_OFFSET
#endif /* HAS_BRAM_MMU_UTLB */
#ifdef HAS_BRAM_BRANCH_TARGET_CACHE
L_btc:
lwi r5, r6, BTC_CALL_COUNT_OFFSET /* Get BTC call count offset */
addik r5, r5, 1 /* Increment and save call count */
andi r5, r5, BTC_MASK
swi r5, r6, BTC_CALL_COUNT_OFFSET
bnei r5, L_skip_btc_scrub /* Skip scrub unless count wrap */
bri 4 /* Clear branch target cache */
L_skip_btc_scrub:
#endif /* HAS_BRAM_BRANCH_TARGET_CACHE */
#endif /* FAULT_TOLERANT */
L_done:
rtsd r15, 8 /* Return */
nop
.end microblaze_scrub
/* Persistent data used by this routine */
.data
.align 2
L_persistent_data:
.long 0 /* dlmb index */
.long 0 /* dcache index */
.long 0 /* icache index */
.long 0 /* mmu entry index */
.long 0 /* btc call count */
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_sleep.c
+241
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@@ -0,0 +1,241 @@
/******************************************************************************
*
* Copyright (C) 2014-2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_sleep.c
*
* Contains implementation of microblaze sleep function.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.1 hk 04/18/14 Add sleep function.
* 6.0 asa 08/15/16 Updated the sleep/usleep signature. Fix for CR#956899.
* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
* implementation. Now sleep routines will use Axi Timer
* or machine cycles as specified by the user.
* 6.8 mus 10/04/18 FreeRTOS BSP alway use default method for sleep
* implementation, It does not have user configurable sleep
* implementation support, that is why FreeRTOS tcl does not
* export XSLEEP_TIMER_IS_DEFAULT_TIMER macro to
* xparameters.h. Modified code to always use default timer
* path for FreeRTOS BSP, based on the "FREERTOS_BSP" macro.
* It fixes CR#1012363.
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent code.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "microblaze_sleep.h"
#include "bspconfig.h"
/***************** Macros (Inline Functions) Definitions *********************/
#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
#define COUNTS_PER_MSECOND (COUNTS_PER_SECOND / 1000)
#define COUNTS_PER_USECOND (COUNTS_PER_SECOND / 1000000)
#warning "May wait for more than the specified delay"
#elif defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
#define ITERS_PER_SEC (XPAR_CPU_CORE_CLOCK_FREQ_HZ / 4)
#define ITERS_PER_MSEC (ITERS_PER_SEC / 1000)
#define ITERS_PER_USEC (ITERS_PER_MSEC / 1000)
#pragma message ("For the sleep routines, assembly instructions are used")
#endif
#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
static void sleep_common(u32 n, u32 iters)
{
asm volatile (
"1: \n\t"
"addik %1, %1, -1 \n\t"
"add r7, r0, %0 \n\t"
"2: \n\t"
"addik r7, r7, -1 \n\t"
"bneid r7, 2b \n\t"
"or r0, r0, r0 \n\t"
"bneid %1, 1b \n\t"
"or r0, r0, r0 \n\t"
:
: "r"(iters), "r"(n)
: "r0", "r7"
);
}
#endif
/*****************************************************************************/
/**
* @brief Provides delay for requested duration.
* @param useconds- time in useconds.
* @return 0
*
* @note Instruction cache should be enabled for this to work.
*
******************************************************************************/
int usleep_MB(unsigned long useconds)
{
#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
sleep_common((u32)useconds, ITERS_PER_USEC);
#elif defined (XSLEEP_TIMER_IS_AXI_TIMER)
/* Start Axi timer */
XTime_StartAxiTimer();
Xil_SleepAxiTimer(useconds, COUNTS_PER_USECOND);
#endif
return 0;
}
/*****************************************************************************/
/**
* @brief Provides delay for requested duration.
* @param seconds- time in useconds.
* @return 0
*
* @note Instruction cache should be enabled for this to work.
*
******************************************************************************/
unsigned sleep_MB(unsigned int seconds)
{
#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
sleep_common(seconds, ITERS_PER_SEC);
#elif defined (XSLEEP_TIMER_IS_AXI_TIMER)
/* Start Axi timer */
XTime_StartAxiTimer();
Xil_SleepAxiTimer(seconds, COUNTS_PER_SECOND);
#endif
return 0;
}
/*****************************************************************************/
/**
*
* @brief Provides delay for requested duration..
*
* @param MilliSeconds- Delay time in milliseconds.
*
* @return None.
*
* @note Instruction cache should be enabled for this to work.
*
******************************************************************************/
void MB_Sleep(u32 MilliSeconds)
{
#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
sleep_common(MilliSeconds, ITERS_PER_MSEC);
#elif defined (XSLEEP_TIMER_IS_AXI_TIMER)
/* Start Axi timer */
XTime_StartAxiTimer();
Xil_SleepAxiTimer(MilliSeconds, COUNTS_PER_MSECOND);
#endif
}
/*****************************************************************************/
/**
*
* @brief Provides delay for requested duration by using Axi Timer.
*
* @param delay - delay time in seconds/milli seconds/micro seconds.
* frequency - Number of counts per
* second/milli second/micro second.
*
* @return None.
*
*
******************************************************************************/
#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
static void Xil_SleepAxiTimer(u32 delay, u64 frequency)
{
u64 tEnd = 0U;
u64 tCur = 0U;
u32 TimeHighVal = 0U;
u32 TimeLowVal1 = 0U;
u32 TimeLowVal2 = 0U;
TimeLowVal1 = Xil_In32((SLEEP_TIMER_BASEADDR) +
(XSLEEP_TIMER_AXITIMER_TCR_OFFSET));
tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
do
{
TimeLowVal2 = Xil_In32((SLEEP_TIMER_BASEADDR) +
(XSLEEP_TIMER_AXITIMER_TCR_OFFSET));
if (TimeLowVal2 < TimeLowVal1) {
TimeHighVal++;
}
TimeLowVal1 = TimeLowVal2;
tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
}while (tCur < tEnd);
}
/*****************************************************************************/
/**
*
* @brief This API starts the Axi Timer only when the timer is not enabled.
*
* @param None.
*
* @return None.
*
* @note Instruction cache should be enabled for this to work.
*
******************************************************************************/
static void XTime_StartAxiTimer()
{
u32 ControlStatusReg;
/* Checking if the timer is enabled */
if(Xil_In32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET) &&
XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK)
{
return;
}
/*
* Read the current register contents such that only the necessary bits
* of the register are modified in the following operations
*/
ControlStatusReg = Xil_In32(SLEEP_TIMER_BASEADDR +
XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET);
/*
* Remove the reset condition such that the timer counter starts running
* with the value loaded from the compare register
*/
Xil_Out32((SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET),
(ControlStatusReg | XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK |
XSLEEP_TIMER_AXITIMER_CSR_AUTO_RELOAD_MASK));
}
#endif
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_sleep.h
+129
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/******************************************************************************
*
* Copyright (C) 2014-2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_sleep.h
*
* @addtogroup microblaze_sleep_routines Sleep Routines for Microblaze
*
* The microblaze_sleep.h file contains microblaze sleep APIs. These APIs
* provides delay for requested duration.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.1 asa 04/18/14 Add sleep function - first release.
* 6.6 srm 10/18/17 Added the Register offset definitions and Control/Status
* Register bit masks of the Axi timer.
*
* </pre>
*
* @note
* The microblaze_sleep.h file may contain architecture-dependent items.
*
******************************************************************************/
#ifndef MICROBLAZE_SLEEP_H /* prevent circular inclusions */
#define MICROBLAZE_SLEEP_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "mb_interface.h"
#include "xparameters.h"
#include "sleep.h"
/************************** Constant Definitions *****************************/
#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
/** @name Register Offset Definitions
* Register offsets within the Axi timer counter, there are multiple
* timer counters within a single device
* @{
*/
#define XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET 0U /**< Control/Status register */
#define XSLEEP_TIMER_AXITIMER_TLR_OFFSET 4U /**< Load register */
#define XSLEEP_TIMER_AXITIMER_TCR_OFFSET 8U /**< Timer counter register */
/* @} */
/** @name Control Status Register Bit Definitions
* Control Status Register bit masks
* Used to configure the Axi timer counter device.
* @{
*/
#define XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK 0x00000080U
/**< Enables only the specific timer */
#define XSLEEP_TIMER_AXITIMER_CSR_AUTO_RELOAD_MASK 0x00000010U
/**< In compare mode, configures the timer
* counter to reload from the Load Register.
* The default mode causes the timer counter
* to hold when the compare value is hit. In
* capture mode, configures the timer counter
* to not hold the previous capture value if
* a new event occurs. The default mode cause
* the timer counter to hold the capture value
* until recognized.*/
#define XSLEEP_TIMER_AXITIMER_CSR_LOAD_MASK 0x00000020U
/**< Loads the timer using the load value
* provided earlier in the Load Register,
* XSLEEP_TIMER_AXITIMER_TLR_OFFSET. */
#define XSLEEP_TIMER_AXITIMER_CSR_INT_OCCURED_MASK 0x00000100U
/**< If bit is set, an interrupt has occured.
* If set and '1' is written to this bit
* position, bit is cleared.*/
#define XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK 0x00000080U
/**< Enables only the specific timer */
/* @} */
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
static void Xil_SleepAxiTimer(u32 delay, u64 frequency);
static void XTime_StartAxiTimer();
#endif
void MB_Sleep(u32 MilliSeconds) __attribute__((__deprecated__));
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup microblaze_sleep_routines".
*/
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_update_dcache.S
+107
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@@ -0,0 +1,107 @@
/******************************************************************************
*
* Copyright (C) 2006 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* File : microblaze_update_dcache.s
* Date : 2003, September 24
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Update dcache on the microblaze.
* Takes in three parameters
* r5 : Cache Tag Line
* r6 : Cache Data
* r7 : Lock/Valid information
* Bit 30 is Lock [ 1 indicates locked ]
* Bit 31 is Valid [ 1 indicates valid ]
*
* --------------------------------------------------------------
* | Lock | Valid | Effect
* --------------------------------------------------------------
* | 0 | 0 | Invalidate Cache
* | 0 | 1 | Valid, but unlocked cacheline
* | 1 | 0 | Invalidate Cache, No effect of lock
* | 1 | 1 | Valid cache. Locked to a
* | | | particular addrees
* --------------------------------------------------------------
*
*
**********************************************************************************/
#include "xparameters.h"
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_update_dcache
.ent microblaze_update_dcache
.align 2
microblaze_update_dcache:
#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
#if XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1
/* Read the MSR register into a temp register */
mfs r18, rmsr
/* Clear the dcache enable bit to disable the cache
Register r10,r18 are volatile registers and hence do not need to be saved before use */
andi r10, r18, ~128
mts rmsr, r10
/* Update the lock and valid info */
andi r5, r5, 0xfffffffc
or r5, r5, r7
/* Update dcache */
wdc r5, r6
/* Return */
rtsd r15, 8
mts rmsr, r18
#else
/* The only valid usage of this routine for larger cache line lengths is to invalidate a data cache line
So call microblaze_init_dcache_range appropriately to do the job */
brid microblaze_init_dcache_range
addik r6, r0, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
/* We don't have a return instruction here. This is tail call optimization :) */
#endif /* XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 */
#else
rtsd r15, 8
nop
#endif
.end microblaze_update_dcache
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/microblaze_update_icache.S
+106
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/******************************************************************************
*
* Copyright (C) 2006 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* File : microblaze_update_icache.s
* Date : 2003, September 24
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Update icache on the microblaze.
* Takes in three parameters
* r5 : Cache Tag Line
* r6 : Cache Data
* r7 : Lock/Valid information
* Bit 30 is Lock [ 1 indicates locked ]
* Bit 31 is Valid [ 1 indicates valid ]
*
* --------------------------------------------------------------
* | Lock | Valid | Effect
* --------------------------------------------------------------
* | 0 | 0 | Invalidate Cache
* | 0 | 1 | Valid, but unlocked cacheline
* | 1 | 0 | Invalidate Cache, No effect of lock
* | 1 | 1 | Valid cache. Locked to a
* | | | particular addrees
* --------------------------------------------------------------
*
*
**********************************************************************************/
#include "xparameters.h"
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
.text
.globl microblaze_update_icache
.ent microblaze_update_icache
.align 2
microblaze_update_icache:
#if (XPAR_MICROBLAZE_USE_ICACHE==1) && (XPAR_MICROBLAZE_ALLOW_ICACHE_WR==1)
#if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1
/* Read the MSR register into a temp register */
mfs r18, rmsr
/* Clear the icache enable bit to disable the cache
Register r10,r18 are volatile registers and hence do not need to be saved before use */
andi r10, r18, ~32
mts rmsr, r10
/* Update the lock and valid info */
andi r5, r5, 0xfffffffc
or r5, r5, r7
/* Update icache */
wic r5, r6
/* Return */
rtsd r15, 8
mts rmsr, r18
#else
/* The only valid usage of this routine for larger cache line lengths is to invalidate an instruction cache line
So call microblaze_init_icache_range appropriately to do the job */
brid microblaze_init_icache_range
addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
/* We don't have a return instruction here. This is tail call optimization :) */
#endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */
#else
rtsd r15, 8
nop
#endif
.end microblaze_update_icache
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/outbyte.c
+12
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#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
#endif
void outbyte(char c);
#ifdef __cplusplus
}
#endif
void outbyte(char c) {
}
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/print.c
+36
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@@ -0,0 +1,36 @@
/* print.c -- print a string on the output device.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
*/
/*
* print -- do a raw print of a string
*/
#include "xil_printf.h"
void print(const char8 *ptr)
{
#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
XPVXenConsole_Write(ptr);
#else
#ifdef STDOUT_BASEADDRESS
while (*ptr != (char8)0) {
outbyte (*ptr);
ptr++;
}
#else
(void)ptr;
#endif
#endif
}
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/profile/Makefile
+74
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@@ -0,0 +1,74 @@
###############################################################################
#
# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
#
# Makefile for profiler
#
#######################################################################
# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
include ../config.make
AS=mb-as
COMPILER = $(CC)
ARCHIVER = mb-ar
CP = cp
COMPILER_FLAGS=-O2
EXTRA_COMPILER_FLAGS=
LIB = libxil.a
DUMMYLIB = libxilprofile.a
CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
RELEASEDIR = ../../../../lib
INCLUDEDIR = ../../../../include
INCLUDES = -I./. -I${INCLUDEDIR}
OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
DUMMYOBJ = dummy.o
INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
libs : reallibs dummylibs
reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
$(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
dummylibs : $(DUMMYOBJ)
$(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
%.o:%.c
$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
%.o:%.S
$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
include:
$(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/profile/_profile_clean.c
+43
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@@ -0,0 +1,43 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "profile.h"
#include "_profile_timer_hw.h"
#include "xil_exception.h"
void _profile_clean( void );
/*
* This function is the exit routine and is called by the crtinit, when the
* program terminates. The name needs to be changed later..
*/
void _profile_clean( void )
{
Xil_ExceptionDisable();
disable_timer();
}
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/profile/_profile_init.c
+86
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@@ -0,0 +1,86 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************
*
* _program_init.c:
* Initialize the Profiling Structures.
*
******************************************************************************/
#include "profile.h"
/* XMD Initializes the following Global Variables Value during Program
* Download with appropriate values. */
#ifdef PROC_MICROBLAZE
extern s32 microblaze_init(void);
#elif defined PROC_PPC
extern s32 powerpc405_init(void);
#else
extern s32 cortexa9_init(void);
#endif
s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */
u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */
u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */
u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */
u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
/* Structure for Storing the Profiling Data */
struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
s32 n_gmon_sections = 1;
/* This is the initialization code, which is called from the crtinit. */
void _profile_init( void )
{
/* print("Gmon Init called....\r\n") */
/* putnum(n_gmon_sections) , print("\r\n") */
/* if( _gmonparam == 0xffffffff ) */
/* printf("Gmonparam is NULL !!\r\n") */
/* for( i = 0, i < n_gmon_sections, i++ )[ */
/* putnum( _gmonparam[i].lowpc) , print("\t") */
/* putnum( _gmonparam[i].highpc) , print("\r\n") */
/* putnum( _gmonparam[i].textsize ), print("\r\n") */
/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */
/* ] */
#ifdef PROC_MICROBLAZE
(void)microblaze_init();
#elif defined PROC_PPC
powerpc405_init();
#else
(void)cortexa9_init();
#endif
}
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/profile/_profile_timer_hw.c
+383
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@@ -0,0 +1,383 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************
*
* _program_timer_hw.c:
* Timer related functions
*
******************************************************************************/
#include "profile.h"
#include "_profile_timer_hw.h"
#include "xil_exception.h"
#ifdef PROC_PPC
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif /* TIMER_CONNECT_INTC */
/* #ifndef PPC_PIT_INTERRUPT */
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
/* extern u32 timer_clk_ticks, */
#ifdef PROC_PPC405
#ifdef PPC_PIT_INTERRUPT
s32 ppc_pit_init( void );
#endif
s32 powerpc405_init()
#endif /* PROC_CORTEXA9 */
#ifdef PROC_PPC440
#ifdef PPC_PIT_INTERRUPT
s32 ppc_dec_init( void );
#endif
s32 powerpc405_init(void);
#endif /* PROC_PPC440 */
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
s32 opb_timer_init( void );
#endif
#ifdef PROC_MICROBLAZE
s32 microblaze_init(void);
#endif /* PROC_MICROBLAZE */
#ifdef PROC_CORTEXA9
s32 scu_timer_init( void );
s32 cortexa9_init(void);
#endif /* PROC_CORTEXA9 */
/*--------------------------------------------------------------------
* PowerPC Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_PPC405
/*--------------------------------------------------------------------
* PowerPC PIT Timer Init.
* Defined only if PIT Timer is used for Profiling
*
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
int ppc_pit_init( void )
{
/* 1. Register Profile_intr_handler as Interrupt handler */
/* 2. Set PIT Timer Interrupt and Enable it. */
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
(Xil_ExceptionHandler)profile_intr_handler,NULL);
XTime_PITSetInterval( timer_clk_ticks ) ;
XTime_PITEnableAutoReload() ;
return 0;
}
#endif
/* --------------------------------------------------------------------
* PowerPC Timer Initialization functions.
* For PowerPC, PIT and opb_timer can be used for Profiling. This
* is selected by the user in standalone BSP
*
*-------------------------------------------------------------------- */
s32 powerpc405_init()
{
Xil_ExceptionInit() ;
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
/* Initialize the Timer.
* 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
* 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
#ifdef PPC_PIT_INTERRUPT
ppc_pit_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,NULL);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,NULL);
#endif
/* Initialize the timer with Timer Ticks */
opb_timer_init() ;
#endif
/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
* in the System. */
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_PITEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
#endif
return 0;
}
#endif /* PROC_PPC */
/*--------------------------------------------------------------------
* PowerPC440 Target - Timer related functions
* -------------------------------------------------------------------- */
#ifdef PROC_PPC440
/*--------------------------------------------------------------------
* PowerPC DEC Timer Init.
* Defined only if DEC Timer is used for Profiling
*
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
s32 ppc_dec_init( void )
{
/* 1. Register Profile_intr_handler as Interrupt handler */
/* 2. Set DEC Timer Interrupt and Enable it. */
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
(Xil_ExceptionHandler)profile_intr_handler,NULL);
XTime_DECSetInterval( timer_clk_ticks ) ;
XTime_DECEnableAutoReload() ;
return 0;
}
#endif
/*--------------------------------------------------------------------
* PowerPC Timer Initialization functions.
* For PowerPC, DEC and opb_timer can be used for Profiling. This
* is selected by the user in standalone BSP
*
*-------------------------------------------------------------------- */
s32 powerpc405_init(void)
{
Xil_ExceptionInit();
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
/* Initialize the Timer.
* 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
* 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
#ifdef PPC_PIT_INTERRUPT
ppc_dec_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,NULL);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,NULL);
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,NULL);
#endif
/* Initialize the timer with Timer Ticks */
opb_timer_init() ;
#endif
/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
* in the System. */
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_DECEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
#endif
return 0;
}
#endif /* PROC_PPC440 */
/* --------------------------------------------------------------------
* opb_timer Initialization for PowerPC and MicroBlaze. This function
* is not needed if DEC timer is used in PowerPC
*
*-------------------------------------------------------------------- */
/* #ifndef PPC_PIT_INTERRUPT */
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
s32 opb_timer_init( void )
{
/* set the number of cycles the timer counts before interrupting */
XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
/* reset the timers, and clear interrupts */
XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
(u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
/* start the timers */
XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
| (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
return 0;
}
#endif
/*--------------------------------------------------------------------
* MicroBlaze Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_MICROBLAZE
/* --------------------------------------------------------------------
* Initialize the Profile Timer for MicroBlaze Target.
* For MicroBlaze, opb_timer is used. The opb_timer can be directly
* connected to MicroBlaze or connected through Interrupt Controller.
*
*-------------------------------------------------------------------- */
s32 microblaze_init(void)
{
/* Register profile_intr_handler
* 1. If timer is connected to Interrupt Controller, register the handler
* to Interrupt Controllers vector table.
* 2. If timer is directly connected to MicroBlaze, register the handler
* as Interrupt handler */
Xil_ExceptionInit();
#ifdef TIMER_CONNECT_INTC
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,NULL);
#else
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)profile_intr_handler,
NULL) ;
#endif
/* Initialize the timer with Timer Ticks */
(void)opb_timer_init() ;
/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
* in the System. */
#ifdef ENABLE_SYS_INTR
#ifdef TIMER_CONNECT_INTC
XIntc_MasterEnable((u32)INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
#endif
#endif
Xil_ExceptionEnable();
return 0;
}
#endif /* PROC_MICROBLAZE */
/* --------------------------------------------------------------------
* Cortex A9 Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_CORTEXA9
/* --------------------------------------------------------------------
* Initialize the Profile Timer for Cortex A9 Target.
* The scu private timer is connected to the Scu GIC controller.
*
*-------------------------------------------------------------------- */
s32 scu_timer_init( void )
{
/* set the number of cycles the timer counts before interrupting
* scu timer runs at half the cpu clock */
XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
/* clear any pending interrupts */
XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
/* enable interrupts, auto-reload mode and start the timer */
XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
return 0;
}
s32 cortexa9_init(void)
{
Xil_ExceptionInit();
XScuGic_DeviceInitialize(0);
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
NULL);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
PROFILE_TIMER_INTR_ID,
(Xil_ExceptionHandler)profile_intr_handler,
NULL);
/*
* Enable the interrupt for scu timer.
*/
XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
/*
* Initialize the timer with Timer Ticks
*/
(void)scu_timer_init() ;
Xil_ExceptionEnable();
return 0;
}
#endif /* PROC_CORTEXA9 */
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/profile/_profile_timer_hw.h
+308
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@@ -0,0 +1,308 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************
*
* _program_timer_hw.h:
* Timer related functions
*
******************************************************************************/
#ifndef PROFILE_TIMER_HW_H
#define PROFILE_TIMER_HW_H
#include "profile.h"
#ifdef PROC_PPC
#if defined __GNUC__
# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
#elif defined __DCC__
# define SYNCHRONIZE_IO __asm volatile(" eieio")
#else
# define SYNCHRONIZE_IO
#endif
#endif
#ifdef PROC_PPC
#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
#else
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
#endif
#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
(u32)(RegOffset)), (u32)(ValueToWrite))
#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(RegisterValue))
#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
#ifdef __cplusplus
extern "C" {
#endif
#ifdef PROC_PPC
#include "xexception_l.h"
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif /* TIMER_CONNECT_INTC */
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
#ifdef PROC_CORTEXA9
#include "xscutimer_hw.h"
#include "xscugic.h"
#endif
extern u32 timer_clk_ticks ;
/*--------------------------------------------------------------------
* PowerPC Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_PPC
#ifdef PPC_PIT_INTERRUPT
u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
#endif
#ifdef PROC_PPC440
#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
#define XREG_SPR_PIT XREG_SPR_DEC
#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
#endif
/* --------------------------------------------------------------------
* Disable the Timer - During Profiling
*
* For PIT Timer -
* 1. XTime_PITDisableInterrupt() ;
* 2. Store the remaining timer clk tick
* 3. Stop the PIT Timer
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define disable_timer() \
{ \
u32 val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
mtspr(XREG_SPR_PIT, 0); \
}
#else
#define disable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
/* --------------------------------------------------------------------
* Enable the Timer
*
* For PIT Timer -
* 1. Load the remaining timer clk ticks
* 2. XTime_PITEnableInterrupt() ;
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define enable_timer() \
{ \
u32 val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
}
#else
#define enable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
* For PIT Timer -
* 1. Load the timer clk ticks
* 2. Enable AutoReload and Interrupt
* 3. Clear PIT Timer Status bits
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define timer_ack() \
{ \
u32 val; \
mtspr(XREG_SPR_PIT, timer_clk_ticks); \
mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
}
#else
#define timer_ack() \
{ \
u32 csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
#endif
/*-------------------------------------------------------------------- */
#endif /* PROC_PPC */
/* -------------------------------------------------------------------- */
/* --------------------------------------------------------------------
* MicroBlaze Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_MICROBLAZE
/* --------------------------------------------------------------------
* Disable the Timer during Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define disable_timer() \
{ \
u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
Addr += (u32)XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(Addr); \
tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
OutAddr += (u32)XTC_TCSR_OFFSET; \
ProfIo_Out32(OutAddr, (u32)tmp_v); \
}
/* --------------------------------------------------------------------
* Enable the Timer after Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define enable_timer() \
{ \
u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
Addr += (u32)XTC_TCSR_OFFSET; \
u32 tmp_v = (u32)ProfIo_In32(Addr); \
tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
}
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
*-------------------------------------------------------------------- */
#define timer_ack() \
{ \
u32 csr; \
csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
}
/*-------------------------------------------------------------------- */
#endif /* PROC_MICROBLAZE */
/*-------------------------------------------------------------------- */
/* --------------------------------------------------------------------
* Cortex A9 Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_CORTEXA9
/* --------------------------------------------------------------------
* Disable the Timer during Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define disable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
}
/* --------------------------------------------------------------------
* Enable the Timer after Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define enable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
}
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
*-------------------------------------------------------------------- */
#define timer_ack() \
{ \
Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
}
/*-------------------------------------------------------------------- */
#endif /* PROC_CORTEXA9 */
/*-------------------------------------------------------------------- */
#ifdef __cplusplus
}
#endif
#endif
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/profile/dummy.S
+60
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@@ -0,0 +1,60 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
.globl dummy_f
#ifdef PROC_MICROBLAZE
.text
.align 2
.ent dummy_f
dummy_f:
nop
.end dummy_f
#endif
#ifdef PROC_PPC
.section .text
.align 2
.type dummy_f@function
dummy_f:
b dummy_f
#endif
#ifdef PROC_CORTEXA9
.section .text
.align 2
.type dummy_f, %function
dummy_f:
b dummy_f
#endif
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/profile/mblaze_nt_types.h
+50
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@@ -0,0 +1,50 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef _MBLAZE_NT_TYPES_H
#define _MBLAZE_NT_TYPES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef char byte;
typedef short half;
typedef int word;
typedef unsigned char ubyte;
typedef unsigned short uhalf;
typedef unsigned int uword;
typedef ubyte boolean;
#ifdef __cplusplus
}
#endif
#endif
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/profile/profile.h
+127
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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef PROFILE_H
#define PROFILE_H 1
#include <stdio.h>
#include "xil_types.h"
#include "profile_config.h"
#ifdef PROC_MICROBLAZE
#include "mblaze_nt_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
void _system_init( void ) ;
void _system_clean( void ) ;
void mcount(u32 frompc, u32 selfpc);
void profile_intr_handler( void ) ;
void _profile_init( void );
/****************************************************************************
* Profiling on hardware - Hash table maintained on hardware and data sent
* to xmd for gmon.out generation.
****************************************************************************/
/*
* histogram counters are unsigned shorts (according to the kernel).
*/
#define HISTCOUNTER u16
struct tostruct {
u32 selfpc;
s32 count;
s16 link;
u16 pad;
};
struct fromstruct {
u32 frompc ;
s16 link ;
u16 pad ;
} ;
/*
* general rounding functions.
*/
#define ROUNDDOWN(x,y) (((x)/(y))*(y))
#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
/*
* The profiling data structures are housed in this structure.
*/
struct gmonparam {
s32 state;
/* Histogram Information */
u16 *kcount; /* No. of bins in histogram */
u32 kcountsize; /* Histogram samples */
/* Call-graph Information */
struct fromstruct *froms;
u32 fromssize;
struct tostruct *tos;
u32 tossize;
/* Initialization I/Ps */
u32 lowpc;
u32 highpc;
u32 textsize;
/* u32 cg_froms, */
/* u32 cg_tos, */
};
extern struct gmonparam *_gmonparam;
extern s32 n_gmon_sections;
/*
* Possible states of profiling.
*/
#define GMON_PROF_ON 0
#define GMON_PROF_BUSY 1
#define GMON_PROF_ERROR 2
#define GMON_PROF_OFF 3
/*
* Sysctl definitions for extracting profiling information from the kernel.
*/
#define GPROF_STATE 0 /* int: profiling enabling variable */
#define GPROF_COUNT 1 /* struct: profile tick count buffer */
#define GPROF_FROMS 2 /* struct: from location hash bucket */
#define GPROF_TOS 3 /* struct: destination/count structure */
#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
#ifdef __cplusplus
}
#endif
#endif /* PROFILE_H */
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/profile/profile_cg.c
+167
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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "profile.h"
#include "_profile_timer_hw.h"
#ifdef PROC_MICROBLAZE
#include "mblaze_nt_types.h"
#endif
/*
* The mcount fucntion is excluded from the library, if the user defines
* PROFILE_NO_GRAPH.
*/
#ifndef PROFILE_NO_GRAPH
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#ifdef PROFILE_NO_FUNCPTR
s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
#else
s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
#endif
/*extern struct gmonparam *_gmonparam, */
#ifdef PROFILE_NO_FUNCPTR
s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
{
s32 index = 0 ;
while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
index++ ;
}
if( index == cgtable_size ) {
return -1 ;
} else {
return index ;
}
}
#else
s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
{
s32 index = 0 ;
s32 Status;
while( (index < fromssize) && (froms[index].frompc != frompc) ){
index++ ;
}
if( index == fromssize ) {
Status = -1 ;
} else {
Status = index ;
}
return Status;
}
#endif /* PROFILE_NO_FUNCPTR */
void mcount( u32 frompc, u32 selfpc )
{
register struct gmonparam *p = NULL;
register s32 toindex, fromindex;
s32 j;
disable_timer();
/*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
* check that frompcindex is a reasonable pc value.
* for example: signal catchers get called from the stack,
* not from text space. too bad.
*/
for(j = 0; j < n_gmon_sections; j++ ){
if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
p = &_gmonparam[j];
break;
}
}
if( j == n_gmon_sections ) {
goto done;
}
#ifdef PROFILE_NO_FUNCPTR
fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
if( fromindex == -1 ) {
fromindex = p->cgtable_size ;
p->cgtable_size++ ;
p->cgtable[fromindex].frompc = frompc ;
p->cgtable[fromindex].selfpc = selfpc ;
p->cgtable[fromindex].count = 1 ;
goto done ;
}
p->cgtable[fromindex].count++ ;
#else
fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
if( fromindex == -1 ) {
fromindex = (s32)p->fromssize ;
p->fromssize++ ;
/*if( fromindex >= N_FROMS ) {
* print("Error : From PC table overflow\r\n")
* goto overflow
*}*/
p->froms[fromindex].frompc = frompc ;
p->froms[fromindex].link = -1 ;
}else {
toindex = ((s32)(p->froms[fromindex].link));
while(toindex != -1) {
toindex = (((s32)p->tossize) - toindex)-1 ;
if( p->tos[toindex].selfpc == selfpc ) {
p->tos[toindex].count++ ;
goto done ;
}
toindex = ((s32)(p->tos[toindex].link)) ;
}
}
/*if( toindex == -1 ) { */
p->tos-- ;
p->tossize++ ;
/* if( toindex >= N_TOS ) {
* print("Error : To PC table overflow\r\n")
* goto overflow
*} */
p->tos[0].selfpc = selfpc ;
p->tos[0].count = 1 ;
p->tos[0].link = p->froms[fromindex].link ;
p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
#endif
done:
p->state = GMON_PROF_ON;
goto enable_timer_label ;
/* overflow: */
/*p->state = GMON_PROF_ERROR */
enable_timer_label:
enable_timer();
return ;
}
#endif /* PROFILE_NO_GRAPH */
datalink814_sp/bsp/microblaze_ps/libsrc/standalone_v7_0/src/profile/profile_config.h
+52
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@@ -0,0 +1,52 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef _PROFILE_CONFIG_H
#define _PROFILE_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif
#define BINSIZE 4U
#define SAMPLE_FREQ_HZ 100000U
#define TIMER_CLK_TICKS 1000U
#define PROFILE_NO_FUNCPTR_FLAG 0
#define PROFILE_TIMER_BASEADDR 0x00608000U
#define PROFILE_TIMER_INTR_ID 0U
#define TIMER_CONNECT_INTC
#ifdef __cplusplus
}
#endif
#endif

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