152 lines
4.7 KiB
C
152 lines
4.7 KiB
C
/*****************************************************************************/
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/**
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* Description: Global configurations.
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*
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* Date: 2021-04-28 13:19
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* Last Edit Time: 2022-05-23 20:32
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*
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* Revisions: Rev 0.0
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* History:
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* [2021-04-28]: Initial edition.
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*
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* Copyright(c) 2021 Beijing Institute of Technology.
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* Lab of Communication and Networking
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*
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******************************************************************************/
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#ifndef CONFIG_H_
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#define CONFIG_H_
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#define XILINX_PLATFORM
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#include "xparameters.h"
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#include "../util/util.h"
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/*********** Indoor Test Mode ************/
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/************ Hardware Configs ************/
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#define CPU_CLK_HZ XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ
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#define FCLK_CLK0_HZ XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ
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/********* Zynq Platform Configs **********/
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// Check crc validation by computing crc value and comparing.
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#define CRC_COMPARE
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//Hardware Parameter
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#define SPI_INTERFACE_SPI_ENGINE
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#define HAVE_SPLIT_GAIN_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
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#define HAVE_TDD_SYNTH_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
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#define AD9361_DEVICE 1 /* set it 1 if AD9361 device is used, 0 otherwise */
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#define AD9364_DEVICE 0 /* set it 1 if AD9364 device is used, 0 otherwise */
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#define AD9363A_DEVICE 0 /* set it 1 if AD9363A device is used, 0 otherwise */
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#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */
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//#define HAVE_DEBUG_MESSAGES /* For Debug purposes only */
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#define GPIO_DEVICE_ID XPAR_AXI_GPIO_DEVICE_ID
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#define GPIO_OFFSET 54
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#define GPIO_INPUT 0
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#define GPIO_OUTPUT 1
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#define GPIO_DISABLE 0
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#define GPIO_ENABLE 1
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#define AD9516_POWEDOWN_B 0
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#define AD9516_RESET_B 1
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#define AD9516_SYNC_B 2
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#define AD9361_1_TXNRX 3
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#define AD9361_1_ENABLE 4
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#define AD9361_1_EN_AGC 5
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#define AD9361_1_RESET_B 6
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#define AD9361_1_CTRL_IN_0 7
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#define AD9361_1_CTRL_IN_1 8
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#define AD9361_1_CTRL_IN_2 9
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#define AD9361_1_CTRL_IN_3 10
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#define AD9361_2_TXNRX 11
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#define AD9361_2_ENABLE 12
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#define AD9361_2_EN_AGC 13
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#define AD9361_2_RESET_B 14
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#define AD9361_2_CTRL_IN_0 15
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#define AD9361_2_CTRL_IN_1 16
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#define AD9361_2_CTRL_IN_2 17
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#define AD9361_2_CTRL_IN_3 18
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#define AD9361_SYNC 19
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#define AD9361_RX_FIFO_RST 20
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#define AD9361_1_CTRL_OUT_0 0
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#define AD9361_1_CTRL_OUT_1 1
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#define AD9361_1_CTRL_OUT_2 2
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#define AD9361_1_CTRL_OUT_3 3
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#define AD9361_1_CTRL_OUT_4 4
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#define AD9361_1_CTRL_OUT_5 5
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#define AD9361_1_CTRL_OUT_6 6
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#define AD9361_1_CTRL_OUT_7 7
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#define AD9361_2_CTRL_OUT_0 8
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#define AD9361_2_CTRL_OUT_1 9
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#define AD9361_2_CTRL_OUT_2 10
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#define AD9361_2_CTRL_OUT_3 11
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#define AD9361_2_CTRL_OUT_4 12
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#define AD9361_2_CTRL_OUT_5 13
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#define AD9361_2_CTRL_OUT_6 14
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#define AD9361_2_CTRL_OUT_7 15
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#define AD9516_REFMON 16
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#define AD9516_LOCKDETECT 17
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#define AD9516_STARUS 18
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#define GPIO_BANK_OUT 1
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#define GPIO_BANK_IN 2
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#define SPI_DEVICE_ID 0
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#define SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
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#define SPI_ENGINE_MAX_SPEED 5000000
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#define SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
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#define SPI_ENGINE_DATA_WIDTH 8
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#define SPI_ENGINE_CS_DELAY 3
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#define SPI_CS_AD9516 0x00
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#define SPI_CS_AD9361_1 0x01
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#define SPI_CS_AD9361_2 0x02
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// Interrupt Configs
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#define INTC_DEVICE_ID XPAR_AXI_INTC_DEVICE_ID
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#define PHY_INTR_ID XPAR_AXI_INTC_SYSTEM_PHY_IRQ_INTR
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#define C2C_TX_INTR_ID XPAR_AXI_INTC_AXI_DMA_C2C_MM2S_INTROUT_INTR
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#define C2C_RX_INTR_ID XPAR_AXI_INTC_AXI_DMA_C2C_S2MM_INTROUT_INTR
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#define SCUTIMER_INTR_ID XPAR_AXI_INTC_AXI_TIMER_0_INTERRUPT_INTR
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// C2C configure
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#define C2C_AXI_DMA_DEVICE_ID XPAR_AXI_DMA_C2C_DEVICE_ID
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#define C2C_RXBUFF_ADDR_BASE XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_BASEADDR
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#define C2C_TXBUFF_ADDR_BASE XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_BASEADDR
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#define C2C_BUFF_NUM 4
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#define C2C_BUFF_SIZE 1024
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// Physical configure
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#define PHY_CTRL_BASEADDR XPAR_PHYC_BASEADDR
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#define PHY_RX_BRAM_BUFF_ID XPAR_RX_FRAME_BRAM_CTRL_DEVICE_ID
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#define PHY_TX_BRAM_BUFF_ID XPAR_TX_FRAME_BRAM_CTRL_DEVICE_ID
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#define PHY_ANT_CONFIG_BRAM_ID XPAR_ANT_CONFIG_BRAM_CTRL_DEVICE_ID
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#define PHY_RX_BUFF_BASEADDR XPAR_RX_FRAME_BRAM_CTRL_S_AXI_BASEADDR
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#define PHY_TX_BUFF_BASEADDR XPAR_TX_FRAME_BRAM_CTRL_S_AXI_BASEADDR
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//Remote Test
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#define GLINK_REMOTE_TEST_ENABLE
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#define TIMER_COUNT_MAX 150000000
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#define SCUTIMER_DEVICE_ID XPAR_AXI_TIMER_0_DEVICE_ID
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//ANT ID
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#define ANT_DEVICE_ID 0x0000
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#if defined(GLINK_REMOTE_TEST_ENABLE) && !defined(TIMER_COUNT_MAX)
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#define TIMER_COUNT_MAX 150000000
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#warning Must set a remote test interval after enable remote test.
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#warning Use default interval 150000000...
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#endif
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//XADC ID
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#define SYSMON_DEVICE_ID XPAR_XADC_WIZ_0_DEVICE_ID
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#endif
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