add ground emulator code.

df_datalink_ge/src/Xilinx.spec

@@ -0,0 +1,2 @@
+*startfile:
+crti%O%s crtbegin%O%s

df_datalink_ge/src/config/app_config.h

@@ -0,0 +1,98 @@
+/*****************************************************************************/
+/**
+ * Description: Global configurations.
+ *
+ * Date: 2021-04-28 13:19
+ * Last Editors: Fan Hao
+ * Last Edit Time: [2022-05-23 20:32]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2021-04-28]: Initial edition.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+#ifndef CONFIG_H_
+#define CONFIG_H_
+
+#define XILINX_PLATFORM
+
+#include "xparameters.h"
+
+/******** Software Version ********/
+#define _APP_VER	0x00010008
+
+#define _APP_VER_MAIN	((_APP_VER & 0xFF000000) >> 24)
+#define _APP_VER_MINOR	((_APP_VER & 0x00FF0000) >> 16)
+#define _APP_VER_PATCH	(_APP_VER & 0x0000FFFF)
+
+/*********** Debug Info Level ************/
+ #define _DEBUG_LEVEL 1
+// 3 - print all debug info
+// 2 - print warnings and errors
+// 1 - print only errors
+// other - print nothing
+//#define DATALINK_ENABLE_AUTORECONNECT
+#define DATALINK_ENABLE_AUTOTIMESYNC
+//#define DATALINK_ENABLE_BERTEST
+
+
+/************ Hardware Configs ************/
+#define CPU_CLK_HZ 			XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define GLOBAL_TIMER_CLK_HZ (CPU_CLK_HZ/2)
+#define SCU_TIMER_CLK_HZ 	(CPU_CLK_HZ/2)
+#define FCLK_CLK0_HZ 		100000000
+
+/********* Zynq Platform Configs **********/
+// SCU Timer (for logging)
+#define SCUTIMER_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
+#define SCUTIMER_INTR_ID XPAR_SCUTIMER_INTR
+
+// Physical Layer Configs
+#define PHY_DEVICE_ID 0
+#define PHY_BASEADDR	XPAR_PHYC_BASEADDR
+#define PHY_BEAM_SET_PRESET
+#define PHY_BEAM_FORMING_ENABLE
+// -- Antenna Bram Configs
+#define PHY_ANTCONFIG_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID
+// -- Buffers
+#define PHY_TXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
+#define PHY_RXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID
+// -- Xadc
+#define PHY_HW_XADC_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
+// -- Interrupt id
+#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
+#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
+
+// System Bus Configs
+//#define SYSBUS_BASE_ADDR	XPAR_SYSTEMBUS_BASEADDR
+//#define SYSBUS_TX_INTR_ID	XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
+//#define SYSBUS_RX_INTR_ID	XPAR_FABRIC_SYSTEMBUS_RX_DONE_INTR
+
+// Global Timer config
+#define GLOBAL_TIMER_DEVICE_ID	XPAR_GLOBAL_TMR_DEVICE_ID
+#define GLOBAL_TIMER_BASEADDR	XPAR_GLOBAL_TMR_BASEADDR
+#define GLOBAL_TIMER_INTR_ID	XPAR_GLOBAL_TMR_INTR
+
+// INTC configis
+#define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
+
+// Configuration Check
+#if defined(PHY_BEAM_SET_PRESET) && !defined(PHY_BEAM_FORMING_ENABLE)
+#define PHY_BEAM_FORMING_ENABLE
+#warning To impliment beam scan must enable beam forming...
+#endif
+
+#if defined(DATALINK_ENABLE_BERTEST)
+#if !defined(DATALINK_ENABLE_AUTOTIMESYNC)
+	#warning To enbale bit error rate test, auto time-sync should be enabled...
+#endif
+#if defined(DATALINK_ENABLE_AUTORECONNECT)
+	#error Do not support auto reconnnect in bit error rate test mode...
+#endif
+#endif
+
+#endif

df_datalink_ge/src/config/platform.c

@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_cache.h"
+#include "platform_config.h"
+
+/*
+ * Uncomment one of the following two lines, depending on the target,
+ * if ps7/psu init source files are added in the source directory for
+ * compiling example outside of SDK.
+ */
+/*#include "ps7_init.h"*/
+/*#include "psu_init.h"*/
+
+#ifdef STDOUT_IS_16550
+ #include "xuartns550_l.h"
+
+ #define UART_BAUD 9600
+#endif
+
+void
+enable_caches()
+{
+#ifdef __PPC__
+    Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
+    Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
+#elif __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+    Xil_ICacheEnable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+    Xil_DCacheEnable();
+#endif
+#endif
+}
+
+void
+disable_caches()
+{
+#ifdef __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+    Xil_DCacheDisable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+    Xil_ICacheDisable();
+#endif
+#endif
+}
+
+void
+init_uart()
+{
+#ifdef STDOUT_IS_16550
+    XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
+    XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
+#endif
+    /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
+}
+
+void
+init_platform()
+{
+    /*
+     * If you want to run this example outside of SDK,
+     * uncomment one of the following two lines and also #include "ps7_init.h"
+     * or #include "ps7_init.h" at the top, depending on the target.
+     * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
+     * along with this example source files for compilation.
+     */
+    /* ps7_init();*/
+    /* psu_init();*/
+    enable_caches();
+    init_uart();
+}
+
+void
+cleanup_platform()
+{
+    disable_caches();
+}

df_datalink_ge/src/config/platform.h

@@ -0,0 +1,41 @@
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef __PLATFORM_H_
+#define __PLATFORM_H_
+
+#include "platform_config.h"
+
+void init_platform();
+void cleanup_platform();
+
+#endif

df_datalink_ge/src/config/platform_config.h

@@ -0,0 +1,7 @@
+#ifndef __PLATFORM_CONFIG_H_
+#define __PLATFORM_CONFIG_H_
+
+#define STDOUT_IS_PS7_UART
+#define UART_DEVICE_ID 0
+
+#endif

df_datalink_ge/src/dev_profile/dev_profile.h

@@ -0,0 +1,13 @@
+#ifndef _DEV_PROFILE_H_
+#define _DEV_PROFILE_H_
+
+#include "irq.h"
+#include "error.h"
+#include "../config/app_config.h"
+
+// device parameters
+extern struct irq_init_param intc_init_param;
+extern struct timer_init_param scutimer_init_param;
+extern struct global_timer_init_param globaltimer_init_param;
+
+#endif /* SRC_DEV_PROFILE_H_ */

df_datalink_ge/src/dev_profile/global_timer_profile.c

@@ -0,0 +1,11 @@
+#include "dev_profile.h"
+#include "global_timer.h"
+#include "../config/app_config.h"
+
+struct global_timer_init_param globaltimer_init_param = {
+	.base_addr = GLOBAL_TIMER_BASEADDR,
+	.id = GLOBAL_TIMER_DEVICE_ID,
+	.freq_hz = GLOBAL_TIMER_CLK_HZ,
+	.load_value = 0x0000000000000000
+};
+

df_datalink_ge/src/dev_profile/intc_profile.c

@@ -0,0 +1,13 @@
+#include "dev_profile.h"
+#include "irq.h"
+#include "../config/app_config.h"
+#include "../drivers/platform/xilinx_irq.h"
+struct xil_irq_init_param xil_intc_init_param = {
+	.type = IRQ_PS
+};
+
+struct irq_init_param intc_init_param = {
+	.irq_ctrl_id = INTC_DEVICE_ID,
+	.platform_ops = &xil_irq_ops,
+	.extra = &xil_intc_init_param
+};

df_datalink_ge/src/dev_profile/timer_profile.c

@@ -0,0 +1,17 @@
+#include "dev_profile.h"
+#include "timer.h"
+#include "../config/app_config.h"
+#include "../drivers/platform/xilinx_timer.h"
+
+struct xil_timer_init_param xil_scutimer_init_param = {
+	.active_tmr = 0,
+	.type = TIMER_PS
+};
+
+struct timer_init_param scutimer_init_param = {
+	.id = SCUTIMER_DEVICE_ID,
+	.freq_hz = SCU_TIMER_CLK_HZ,
+	.ticks_count = (SCU_TIMER_CLK_HZ/10), //update log every 100ms
+	.platform_ops = &xil_timer_ops,
+	.extra = &xil_scutimer_init_param
+};

df_datalink_ge/src/drivers/api/irq.c

@@ -0,0 +1,229 @@
+/***************************************************************************//**
+ *   @file   irq.c
+ *   @brief  Implementation of the IRQ Interface
+ *   @author Andrei Porumb ([email protected])
+********************************************************************************
+ * Copyright 2021(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include "irq.h"
+#include "error.h"
+
+/**
+ * @brief Initialize the IRQ interrupts.
+ * @param desc - The IRQ descriptor.
+ * @param param - The structure that contains the IRQ parameters.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
+			    const struct irq_init_param *param)
+{
+	int32_t ret;
+
+	if (!param || !param->platform_ops)
+		return -EINVAL;
+
+	if (!param->platform_ops->init)
+		return -ENOSYS;
+
+	ret = param->platform_ops->init(desc, param);
+	if (ret)
+		return ret;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return 0;
+}
+
+/**
+ * @brief Free the resources allocated by irq_ctrl_init().
+ * @param desc - The SPI descriptor.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->remove)
+		return -ENOSYS;
+
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Register a callback to handle the irq events.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param callback - Callback descriptor - platform specific type.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_register_callback(struct irq_ctrl_desc *desc,
+				    uint32_t irq_id,
+				    struct callback_desc *callback)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->register_callback)
+		return -ENOSYS;
+
+	return desc->platform_ops->register_callback(desc, irq_id, callback);
+}
+
+/**
+ * @brief Unregisters a generic IRQ handling function.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param callback - Callback descriptor - platform specific type.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_unregister_callback(struct irq_ctrl_desc *desc,
+				      uint32_t irq_id,
+				      struct callback_desc *callback)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->unregister_callback)
+		return -ENOSYS;
+
+	return desc->platform_ops->unregister_callback(desc, irq_id, callback);
+}
+
+/**
+ * @brief Enable global interrupts.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t irq_global_enable(struct irq_ctrl_desc *desc)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->global_enable)
+		return -ENOSYS;
+
+	return desc->platform_ops->global_enable(desc);
+}
+
+/**
+ * @brief Disable global interrupts.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t irq_global_disable(struct irq_ctrl_desc *desc)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->global_disable)
+		return -ENOSYS;
+
+	return desc->platform_ops->global_disable(desc);
+}
+
+/**
+ * @brief Set interrupt trigger level.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param trig - New trigger level for the interrupt.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc,
+				    uint32_t irq_id,
+				    enum irq_trig_level trig)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if(!desc->platform_ops->trigger_level_set)
+		return -ENOSYS;
+
+	return desc->platform_ops->trigger_level_set(desc, irq_id, trig);
+}
+
+/**
+ * @brief Enable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->enable)
+		return -ENOSYS;
+
+	return desc->platform_ops->enable(desc, irq_id);
+}
+
+/**
+ * @brief Disable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->disable)
+		return -ENOSYS;
+
+	return desc->platform_ops->disable(desc, irq_id);
+}
+
+/**
+ * @brief Set the priority for an interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param priority_level - The priority level of the interrupt.
+ * @return 0 in case of success, negative errno error codes.
+ */
+int32_t irq_set_priority(struct irq_ctrl_desc *desc,
+			       uint32_t irq_id,
+			       uint32_t priority_level)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->set_priority)
+		return -ENOSYS;
+
+	return desc->platform_ops->set_priority(desc, irq_id, priority_level);
+}

df_datalink_ge/src/drivers/api/timer.c

@@ -0,0 +1,211 @@
+/***************************************************************************//**
+*   @file   timer.c
+*   @brief  Implementation of the timer Interface
+*   @author RBolboac ([email protected])
+********************************************************************************
+* Copyright 2022(c) Analog Devices, Inc.
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*  - Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*  - Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in
+*    the documentation and/or other materials provided with the
+*    distribution.
+*  - Neither the name of Analog Devices, Inc. nor the names of its
+*    contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*  - The use of this software may or may not infringe the patent rights
+*    of one or more patent holders.  This license does not release you
+*    from the requirement that you obtain separate licenses from these
+*    patent holders to use this software.
+*  - Use of the software either in source or binary form, must be run
+*    on or directly connected to an Analog Devices Inc. component.
+*
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include "error.h"
+#include "timer.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+/**
+ * @brief Initialize hardware timer and the handler structure associated with
+ *        it.
+ * @param [out] desc - Pointer to the reference of the device handler.
+ * @param [in] param - Initialization structure.
+ * @return 0 in case of success, negative error code otherwise
+ */
+int32_t timer_init(struct timer_desc **desc,
+			 struct timer_init_param *param)
+{
+	int32_t ret;
+
+	if (!param || !param->platform_ops)
+		return -EINVAL;
+
+	if (!param->platform_ops->init)
+		return -ENOSYS;
+
+	ret = param->platform_ops->init(desc, param);
+	if (ret)
+		return ret;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return 0;
+}
+
+/**
+ * @brief Free the memory allocated by timer_init().
+ * @param [in] desc - Pointer to the device handler.
+ * @return 0 in case of success, negative error code otherwise
+ */
+int32_t timer_remove(struct timer_desc *desc)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->remove)
+		return -ENOSYS;
+
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Start a timer.
+ * @param [in] desc - Pointer to the device handler.
+ * @return 0 in case of success, negative error code otherwise
+ */
+int32_t timer_start(struct timer_desc *desc)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->start)
+		return -ENOSYS;
+
+	return desc->platform_ops->start(desc);
+}
+
+/**
+ * @brief Stop a timer from counting.
+ * @param [in] desc - Pointer to the device handler.
+ * @return 0 in case of success, negative error code otherwise
+ */
+int32_t timer_stop(struct timer_desc *desc)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->stop)
+		return -ENOSYS;
+
+	return desc->platform_ops->stop(desc);
+}
+
+/**
+ * @brief Get the value of the counter register for the timer.
+ * @param [in]  desc    - Pointer to the device handler.
+ * @param [out] counter - Pointer to the counter value.
+ * @return 0 in case of success, error code otherwise.
+ */
+int32_t timer_counter_get(struct timer_desc *desc,
+				uint32_t *counter)
+{
+	if (!desc || !desc->platform_ops || !counter)
+		return -EINVAL;
+
+	if (!desc->platform_ops->counter_get)
+		return -ENOSYS;
+
+	return desc->platform_ops->counter_get(desc, counter);
+}
+
+/**
+ * @brief Set the timer counter register value.
+ * @param [in] desc    - Pointer to the device handler.
+ * @param [in] new_val - The new value of the counter register.
+ * @return 0 in case of success, error code otherwise.
+ */
+int32_t timer_counter_set(struct timer_desc *desc, uint32_t new_val)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->counter_set)
+		return -ENOSYS;
+
+	return desc->platform_ops->counter_set(desc, new_val);
+}
+
+/**
+ * @brief Get the timer clock frequency.
+ * @param [in]  desc    - Pointer to the device handler.
+ * @param [out] freq_hz - The value in Hz of the timer clock.
+ * @return 0 in case of success, error code otherwise.
+ */
+int32_t timer_count_clk_get(struct timer_desc *desc,
+				  uint32_t *freq_hz)
+{
+	if (!desc || !desc->platform_ops || !freq_hz)
+		return -EINVAL;
+
+	if (!desc->platform_ops->count_clk_get)
+		return -ENOSYS;
+
+	return desc->platform_ops->count_clk_get(desc, freq_hz);
+}
+
+/**
+ * @brief Set the timer clock frequency.
+ * @param [in] desc    - Pointer to the device handler.
+ * @param [in] freq_hz - The value in Hz of the new timer clock.
+ * @return 0 in case of success, error code otherwise.
+ */
+int32_t timer_count_clk_set(struct timer_desc *desc,
+				  uint32_t freq_hz)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->count_clk_set)
+		return -ENOSYS;
+
+	return desc->platform_ops->count_clk_set(desc, freq_hz);
+}
+
+/**
+ * @brief Get the elapsed time in nsec for the timer.
+ * @param [in] desc         - Pointer to the device handler.
+ * @param [in] elapsed_time - The elapsed time in nsec.
+ * @return 0 in case of success, error code otherwise.
+ */
+int32_t timer_get_elapsed_time_nsec(struct timer_desc *desc,
+		uint64_t *elapsed_time)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->get_elapsed_time_nsec)
+		return -ENOSYS;
+
+	return desc->platform_ops->get_elapsed_time_nsec(desc, elapsed_time);
+}

df_datalink_ge/src/drivers/api/trng.c

@@ -0,0 +1,111 @@
+/***************************************************************************//**
+ *   @file   trng.c
+ *   @brief  Implementation of the TRNG Interface
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2023(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <inttypes.h>
+#include "trng.h"
+#include <stdlib.h>
+#include "error.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Initialize the TRNG.
+ * @param desc - The TRNG descriptor.
+ * @param param - The structure that contains the TRNG parameters.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int trng_init(struct trng_desc **desc,
+		    const struct trng_init_param *param)
+{
+	int ret;
+
+	if (!param || !param->platform_ops)
+		return -EINVAL;
+
+	if (!param->platform_ops->init)
+		return -ENOSYS;
+
+	ret = param->platform_ops->init(desc, param);
+	if (ret)
+		return ret;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return 0;
+}
+
+/**
+ * @brief Free the resources allocated by trng_init().
+ * @param desc - The TRNG descriptor.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int trng_remove(struct trng_desc *desc)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->remove)
+		return -ENOSYS;
+
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Fill buffer with rng data.
+ * @param desc - The TRNG descriptor.
+ * @param buff - Buffer to be filled
+ * @param len - Size of the buffer
+ * @return 0 in case of success, -1 otherwise.
+ */
+int trng_fill_buffer(struct trng_desc *desc, uint8_t *buff,
+			   uint32_t len)
+{
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (!desc->platform_ops->fill_buffer)
+		return -ENOSYS;
+
+	return desc->platform_ops->fill_buffer(desc, buff, len);
+}

df_datalink_ge/src/drivers/platform/xilinx_axi_io.c

@@ -0,0 +1,79 @@
+/***************************************************************************//**
+ *   @file   xilinx/xilinx_axi_io.c
+ *   @brief  Implementation of Xilinx AXI IO.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <xil_io.h>
+#include "error.h"
+#include "axi_io.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief AXI IO Xilinx specific read function.
+ * @param base - Base address
+ * @param offset - Address offset
+ * @param data - variable where returned data is stored
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
+{
+	*data = Xil_In32(base + offset);
+
+	return 0;
+}
+
+/**
+ * @brief AXI IO Xilinx specific write function.
+ * @param base - Base address
+ * @param offset - Address offset
+ * @param data - data to be written.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
+{
+	Xil_Out32(base + offset, data);
+
+	return 0;
+}
+

df_datalink_ge/src/drivers/platform/xilinx_irq.c

@@ -0,0 +1,433 @@
+/***************************************************************************//**
+ *   @file   xilinx/xilinx_irq.c
+ *   @brief  Implementation of Xilinx IRQ Generic Driver.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <xparameters.h>
+#include <stdlib.h>
+#include "error.h"
+#include "irq.h"
+#include "xilinx_irq.h"
+#ifdef XPAR_XSCUGIC_NUM_INSTANCES
+#include <xscugic.h>
+#endif
+#ifdef XPAR_XINTC_NUM_INSTANCES
+#include <xintc.h>
+#endif
+#ifdef XPAR_XTMRCTR_NUM_INSTANCES
+#include <xtmrctr.h>
+#endif
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Initialize the IRQ interrupts.
+ * @param desc - The IRQ controller descriptor.
+ * @param param - The structure that contains the IRQ parameters.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t xil_irq_ctrl_init(struct irq_ctrl_desc **desc,
+			  const struct irq_init_param *param)
+{
+	int32_t status;
+	struct irq_ctrl_desc *descriptor;
+	struct xil_irq_desc *xil_dev;
+#ifdef XSCUGIC_H
+	void *config;
+#endif
+
+	descriptor = (struct irq_ctrl_desc *)calloc(1, sizeof *descriptor);
+	if(!descriptor)
+		return -1;
+	xil_dev = (struct xil_irq_desc *)calloc(1, sizeof *xil_dev);
+	if(!xil_dev) {
+		free(descriptor);
+		return -1;
+	}
+
+	Xil_ExceptionInit();
+
+	descriptor->irq_ctrl_id = param->irq_ctrl_id;
+	descriptor->extra = xil_dev;
+	xil_dev->type = ((struct xil_irq_init_param *)param->extra)->type;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		xil_dev->instance = calloc(1, sizeof(XScuGic));
+		if(!xil_dev->instance)
+			goto error;
+
+		config = XScuGic_LookupConfig(descriptor->irq_ctrl_id);
+		if(!config)
+			goto ps_error;
+
+		status = XScuGic_CfgInitialize(xil_dev->instance, config,
+					       ((XScuGic_Config *)config)->CpuBaseAddress);
+		if (status != 0)
+			goto ps_error;
+
+		Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+					     (Xil_ExceptionHandler)XScuGic_InterruptHandler,
+					     xil_dev->instance);
+
+		break;
+ps_error:
+		free(xil_dev->instance);
+#endif
+		goto error;
+	case IRQ_PL:
+#ifdef XINTC_H
+		xil_dev->instance = calloc(1, sizeof(XIntc));
+		if(!xil_dev->instance)
+			goto error;
+
+		status = XIntc_Initialize(xil_dev->instance, descriptor->irq_ctrl_id);
+		if(status != 0)
+			goto pl_error;
+
+		status = XIntc_Start(xil_dev->instance, XIN_REAL_MODE);
+		if(status != 0)
+			goto pl_error;
+
+		break;
+pl_error:
+		free(xil_dev->instance);
+#endif
+		goto error;
+	default:
+		goto error;
+
+		break;
+	}
+
+	*desc = descriptor;
+
+	return 0;
+
+error:
+	free(xil_dev);
+	free(descriptor);
+
+	return -1;
+}
+
+/**
+ * @brief Enable global interrupts.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t xil_irq_global_enable(struct irq_ctrl_desc *desc)
+{
+	/* Enable interrupts */
+	Xil_ExceptionEnable();
+
+	return 0;
+}
+
+/**
+ * @brief Disable global interrupts.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t xil_irq_global_disable(struct irq_ctrl_desc *desc)
+{
+	/* Disable interrupts */
+	Xil_ExceptionDisable();
+
+	return 0;
+}
+
+/**
+ * @brief Enable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t xil_irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		XScuGic_Enable(xil_dev->instance, irq_id);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		XIntc_Enable(xil_dev->instance, irq_id);
+#endif
+		break;
+	default:
+
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Disable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t xil_irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		XScuGic_Disable(xil_dev->instance, irq_id);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		XIntc_Disable(xil_dev->instance, irq_id);
+#endif
+		break;
+	default:
+
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Register a callback to handle the irq events.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param callback_desc - Callback descriptor
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t xil_irq_register_callback(struct irq_ctrl_desc *desc,
+				  uint32_t irq_id,
+				  struct callback_desc *callback_desc)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		return XScuGic_Connect(xil_dev->instance, irq_id,
+				       (Xil_InterruptHandler) callback_desc->callback,
+				       callback_desc->ctx);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		if (irq_id == XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR) {
+			int32_t ret;
+
+			ret = XIntc_Connect(xil_dev->instance, irq_id,
+					    XTmrCtr_InterruptHandler, callback_desc->legacy_config);
+			if (IS_ERR_VALUE(ret))
+				return -1;
+			XTmrCtr_SetHandler(callback_desc->legacy_config,
+					   (XTmrCtr_Handler)callback_desc->callback,
+					   callback_desc->ctx);
+
+			return 0;
+		}
+		return XIntc_Connect(xil_dev->instance, irq_id,
+				     (XInterruptHandler) callback_desc->callback,
+				     callback_desc->ctx);
+#endif
+		break;
+	default:
+		break;
+	}
+
+	return -1;
+}
+
+/**
+ * @brief Set interrupt trigger level.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param trig - New trigger level for the interrupt.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t xil_irq_trigger_level_set(struct irq_ctrl_desc *desc,
+				  uint32_t irq_id,
+				  enum irq_trig_level trig)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	if(trig == IRQ_EDGE_BOTH)
+		return -EINVAL;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		;
+		uint8_t priority, trigger;
+
+		XScuGic_GetPriorityTriggerType(xil_dev->instance, irq_id, &priority,
+					       &trigger);
+		trigger = trig;
+		XScuGic_SetPriorityTriggerType(xil_dev->instance, irq_id, priority,
+					       trigger);
+
+		return 0;
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		/* Interrupt trigger determined in hardware. TODO: verify */
+		return 0;
+#endif
+		break;
+	default:
+		break;
+	}
+
+	return -1;
+}
+
+/**
+ * @brief Set interrupt trigger level.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param priority_level - New priority level for the interrupt.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t xil_irq_set_priority(struct irq_ctrl_desc *desc,
+		uint32_t irq_id,
+		uint32_t priority_level)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	if(priority_level % 8 != 0)
+		return -EINVAL;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		;
+		uint8_t priority, trigger;
+
+		XScuGic_GetPriorityTriggerType(xil_dev->instance, irq_id, &priority,
+					       &trigger);
+		priority = priority_level;
+		XScuGic_SetPriorityTriggerType(xil_dev->instance, irq_id, priority,
+					       trigger);
+
+		return 0;
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		/* Interrupt priority level determined in hardware. TODO: verify */
+		return 0;
+#endif
+		break;
+	default:
+		break;
+	}
+
+	return -1;
+}
+
+/**
+ * @brief Unregisters a generic IRQ handling function.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param cb - Callback descriptor.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t xil_irq_unregister_callback(struct irq_ctrl_desc *desc,
+				    uint32_t irq_id, struct callback_desc *cb)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		XScuGic_Disconnect(xil_dev->instance, irq_id);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		XIntc_Disconnect(xil_dev->instance, irq_id);
+#endif
+		break;
+	default:
+
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Free the resources allocated by irq_ctrl_init().
+ * @param desc - The IRQ control descriptor.
+ * @return 0 in case of success, -1 otherwise.
+ */
+int32_t xil_irq_ctrl_remove(struct irq_ctrl_desc *desc)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+	free(xil_dev->instance);
+	free(desc->extra);
+	free(desc);
+
+	return 0;
+}
+
+/**
+ * @brief Xilinx platform specific IRQ platform ops structure
+ */
+const struct irq_platform_ops xil_irq_ops = {
+	.init = &xil_irq_ctrl_init,
+	.register_callback = &xil_irq_register_callback,
+	.unregister_callback = &xil_irq_unregister_callback,
+	.global_enable = &xil_irq_global_enable,
+	.global_disable = &xil_irq_global_disable,
+	.trigger_level_set = &xil_irq_trigger_level_set,
+	.set_priority = &xil_irq_set_priority,
+	.enable = &xil_irq_enable,
+	.disable = &xil_irq_disable,
+	.remove = &xil_irq_ctrl_remove
+};

df_datalink_ge/src/drivers/platform/xilinx_irq.h

@@ -0,0 +1,91 @@
+/*******************************************************************************
+ *   @file   xilinx_irq.h
+ *   @brief  Header containing types used in the irq driver.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef XILINX_IRQ_H_
+#define XILINX_IRQ_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+#include "irq.h"
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum xil_irq_type
+ * @brief Xilinx platform architecture sections
+ */
+enum xil_irq_type {
+	/** Programmable Logic */
+	IRQ_PL,
+	/** Processing System */
+	IRQ_PS
+};
+
+/**
+ * @struct xil_irq_init_param
+ * @brief Structure holding the initialization parameters for Xilinx platform
+ * specific IRQ parameters.
+ */
+struct xil_irq_init_param {
+	/** Xilinx architecture */
+	enum xil_irq_type	type;
+};
+
+/**
+ * @struct xil_irq_desc
+ * @brief Xilinx platform specific IRQ descriptor
+ */
+struct xil_irq_desc {
+	/** Xilinx architecture */
+	enum xil_irq_type	type;
+	/** Xilinx IRQ Instance */
+	void				*instance;
+};
+
+/**
+ * @brief Xilinx specific IRQ platform ops structure
+ */
+extern const struct irq_platform_ops xil_irq_ops;
+
+#endif

df_datalink_ge/src/drivers/platform/xilinx_timer.c

@@ -0,0 +1,456 @@
+/***************************************************************************//**
+*   @file   xilinx/xilinx_timer.c
+*   @brief  Timer and GIC control module source.
+*   @author Andrei Drimbarean ([email protected])
+********************************************************************************
+* Copyright 2020(c) Analog Devices, Inc.
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*  - Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*  - Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in
+*    the documentation and/or other materials provided with the
+*    distribution.
+*  - Neither the name of Analog Devices, Inc. nor the names of its
+*    contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*  - The use of this software may or may not infringe the patent rights
+*    of one or more patent holders.  This license does not release you
+*    from the requirement that you obtain separate licenses from these
+*    patent holders to use this software.
+*  - Use of the software either in source or binary form, must be run
+*    on or directly connected to an Analog Devices Inc. component.
+*
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdlib.h>
+#include <xparameters.h>
+#include "timer.h"
+#include "xilinx_timer.h"
+#include "error.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#if defined(_XPARAMETERS_PS_H_)
+#define CORE_PRIVATE_TIMER_CLOCK (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / 2)
+#endif
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Set the current counter value of the timer.
+ * @param [in] desc - Pointer to the device handler.
+ * @param [in] new_val - New value for the timer counter.
+ * @return 0 in case of success, -1 otherwise
+ */
+int32_t xilinx_timer_counter_set(struct timer_desc *desc,
+				 uint32_t new_val)
+{
+	struct xil_timer_desc *xdesc;
+
+	if (!desc)
+		return -1;
+
+	xdesc = desc->extra;
+
+	switch (xdesc->type) {
+	case TIMER_PS:
+#ifdef XSCUTIMER_H
+		XScuTimer_LoadTimer((XScuTimer *)xdesc->instance, new_val - 1);
+		break;
+#endif
+		return -1;
+	case TIMER_PL:
+#ifdef XTMRCTR_H
+		XTmrCtr_SetResetValue(xdesc->instance, xdesc->active_tmr, new_val);
+		XTmrCtr_Reset(xdesc->instance, xdesc->active_tmr);
+		break;
+#endif
+		return -1;
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Set the timer clock frequency.
+ * @param [in] desc - Pointer to the device handler.
+ * @param [in] freq_hz - New timer frequency in hertz.
+ * @return 0 in case of success, -1 otherwise
+ */
+int32_t xilinx_timer_count_clk_set(struct timer_desc *desc,
+				   uint32_t freq_hz)
+{
+	struct xil_timer_desc *xdesc;
+
+	if (!desc || !freq_hz)
+		return -1;
+
+	xdesc = desc->extra;
+
+	switch (xdesc->type) {
+	case TIMER_PS:
+#ifdef XSCUTIMER_H
+		;
+		uint32_t prescaler = CORE_PRIVATE_TIMER_CLOCK / freq_hz;
+		if (prescaler == 0 || prescaler >= 256)
+			return -1;
+		XScuTimer_SetPrescaler(xdesc->instance, prescaler - 1);
+		desc->freq_hz = CORE_PRIVATE_TIMER_CLOCK / prescaler;
+		break;
+#endif
+		return -1;
+	case TIMER_PL:
+#ifdef XTMRCTR_H
+		(void *)xdesc;
+		/** Cannot be done. */
+#endif
+		return -1;
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Initialize hardware timer and the handler structure associated with
+ *        it.
+ * @param [out] desc - Pointer to the reference of the device handler.
+ * @param [in] param - Initialization structure.
+ * @return 0 in case of success, -1 otherwise
+ */
+int32_t xilinx_timer_init(struct timer_desc **desc,
+			  const struct timer_init_param *param)
+{
+	int32_t ret;
+	struct timer_desc *dev;
+	struct xil_timer_desc *xdesc;
+	struct xil_timer_init_param *xinit;
+
+	if (!desc || !param)
+		return -1;
+
+	xinit = param->extra;
+
+	dev = (struct timer_desc *)calloc(1, sizeof(*dev));
+	if(!dev)
+		return -1;
+	xdesc = (struct xil_timer_desc *)calloc(1, sizeof(*xdesc));
+	if(!xdesc)
+		goto error_desc;
+
+	dev->id = param->id;
+	dev->freq_hz = param->freq_hz;
+	dev->ticks_count = param->ticks_count;
+	dev->extra = xdesc;
+	xdesc->active_tmr = xinit->active_tmr;
+	xdesc->type = xinit->type;
+
+	switch (xdesc->type) {
+	case TIMER_PS:
+#ifdef XSCUTIMER_H
+		xdesc->config = XScuTimer_LookupConfig(dev->id);
+		xdesc->instance = calloc(1, sizeof(XScuTimer));
+		if (!xdesc->instance)
+			goto error_xdesc;
+		ret = XScuTimer_CfgInitialize(xdesc->instance, xdesc->config,
+					      ((XScuTimer_Config *)xdesc->config)->BaseAddr);
+		if (ret != XST_SUCCESS) {
+			free(xdesc->instance);
+			goto error_xdesc;
+		}
+		ret = xilinx_timer_count_clk_set(dev, param->freq_hz);
+		if (IS_ERR_VALUE(ret))
+			goto error_xdesc;
+
+		ret = xilinx_timer_counter_set(dev, dev->ticks_count);
+		if (IS_ERR_VALUE(ret))
+			goto error_xdesc;
+
+		XScuTimer_EnableAutoReload((XScuTimer *)xdesc->instance);
+		XScuTimer_EnableInterrupt((XScuTimer *)xdesc->instance);
+		break;
+#endif
+		goto error_xdesc;
+	case TIMER_PL:
+#ifdef XTMRCTR_H
+		xdesc->instance = (XTmrCtr *)calloc(1, sizeof(XTmrCtr));
+		if (!xdesc->instance)
+			return -1;
+
+		xdesc->config = XTmrCtr_LookupConfig(dev->id);
+		if (!xdesc->config) {
+			free(xdesc->instance);
+			goto error_desc;
+		}
+		XTmrCtr_CfgInitialize(xdesc->instance, xdesc->config,
+				      ((XTmrCtr_Config *)xdesc->config)->BaseAddress);
+		ret = XTmrCtr_InitHw(xdesc->instance);
+		if (ret != 0) {
+			free(xdesc->instance);
+			goto error_desc;
+		}
+		dev->freq_hz = ((XTmrCtr_Config *)xdesc->config)->SysClockFreqHz;
+
+		ret = XTmrCtr_SelfTest(xdesc->instance, dev->id);
+		if(ret != 0)
+			goto error_desc;
+		XTmrCtr_SetOptions(xdesc->instance, xdesc->active_tmr,
+				   XTC_DOWN_COUNT_OPTION | XTC_INT_MODE_OPTION |
+				   XTC_AUTO_RELOAD_OPTION);
+		XTmrCtr_SetResetValue(xdesc->instance, xdesc->active_tmr,
+				      dev->ticks_count);
+		break;
+#endif
+		goto error_xdesc;
+	default:
+		goto error_xdesc;
+	}
+
+	*desc = dev;
+
+	return 0;
+
+error_xdesc:
+	free(xdesc);
+error_desc:
+	free(dev);
+
+	return -1;
+}
+
+/**
+ * @brief Free the memory allocated by timer_setup().
+ * @param [in] desc - Pointer to the device handler.
+ * @return 0 in case of success, -1 otherwise
+ */
+int32_t xilinx_timer_remove(struct timer_desc *desc)
+{
+	struct xil_timer_desc *xdesc;
+
+	if(!desc)
+		return -1;
+
+	xdesc = desc->extra;
+
+	switch (xdesc->type) {
+	case TIMER_PS:
+#ifdef XSCUTIMER_H
+		XScuTimer_Stop(xdesc->instance);
+		free(xdesc->instance);
+		break;
+#endif
+		return -1;
+	case TIMER_PL:
+#ifdef XTMRCTR_H
+		XTmrCtr_Stop(xdesc->instance, xdesc->active_tmr);
+		break;
+#endif
+		return -1;
+	default:
+		return -1;
+	}
+
+	free(xdesc);
+	free(desc);
+
+	return 0;
+}
+
+/**
+ * @brief Start a timer.
+ * @param [in] desc - Pointer to the device handler.
+ * @return 0 in case of success, -1 otherwise
+ */
+int32_t xilinx_timer_start(struct timer_desc *desc)
+{
+	struct xil_timer_desc *xdesc;
+
+	if (!desc)
+		return -1;
+
+	xdesc = desc->extra;
+
+	switch (xdesc->type) {
+	case TIMER_PS:
+#ifdef XSCUTIMER_H
+		XScuTimer_Start(xdesc->instance);
+		break;
+#endif
+		return -1;
+	case TIMER_PL:
+#ifdef XTMRCTR_H
+		XTmrCtr_Start(xdesc->instance, xdesc->active_tmr);
+		break;
+#endif
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Stop a timer from counting.
+ * @param [in] desc - Pointer to the device handler.
+ * @return 0 in case of success, -1 otherwise
+ */
+int32_t xilinx_timer_stop(struct timer_desc *desc)
+{
+	struct xil_timer_desc *xdesc;
+
+	if (!desc)
+		return -1;
+
+	xdesc = desc->extra;
+
+	switch (xdesc->type) {
+	case TIMER_PS:
+#ifdef XSCUTIMER_H
+		XScuTimer_Stop(xdesc->instance);
+		break;
+#endif
+		return -1;
+	case TIMER_PL:
+#ifdef XTMRCTR_H
+		XTmrCtr_Stop(xdesc->instance, xdesc->active_tmr);
+		break;
+#endif
+		return -1;
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Get the current counter value of the timer.
+ * @param [in] desc - Pointer to the device handler.
+ * @param [out] counter - Pointer to the current counter value.
+ * @return 0 in case of success, -1 otherwise
+ */
+int32_t xilinx_timer_counter_get(struct timer_desc *desc,
+				 uint32_t *counter)
+{
+	struct xil_timer_desc *xdesc;
+
+	if (!desc || !counter)
+		return -1;
+
+	xdesc = desc->extra;
+
+	switch (xdesc->type) {
+	case TIMER_PS:
+#ifdef XSCUTIMER_H
+		*counter = XScuTimer_GetCounterValue((XScuTimer *)xdesc->instance);
+		++(*counter);
+		break;
+#endif
+		return -1;
+	case TIMER_PL:
+#ifdef XTMRCTR_H
+		*counter = XTmrCtr_GetValue(xdesc->instance, xdesc->active_tmr);
+		break;
+#endif
+		return -1;
+	default:
+		*counter = 0;
+
+		return -1;
+	}
+
+	return 0;
+}
+
+
+/**
+ * @brief Get the timer clock frequency.
+ * @param [in] desc - Pointer to the device handler.
+ * @param [out] freq_hz - Pointer to the returned frequency.
+ * @return 0 in case of success, -1 otherwise
+ */
+int32_t xilinx_timer_count_clk_get(struct timer_desc *desc,
+				   uint32_t *freq_hz)
+{
+	struct xil_timer_desc *xdesc;
+
+	if (!desc || !freq_hz)
+		return -1;
+
+	xdesc = desc->extra;
+
+	switch (xdesc->type) {
+	case TIMER_PS:
+#ifdef XSCUTIMER_H
+		*freq_hz = desc->freq_hz;
+		break;
+#endif
+		return -1;
+	case TIMER_PL:
+#ifdef XTMRCTR_H
+		*freq_hz = ((XTmrCtr_Config *)xdesc->config)->SysClockFreqHz;
+		break;
+#endif
+		return -1;
+	default:
+		*freq_hz = 0;
+
+		return -1;
+	}
+
+	return 0;
+}
+
+
+/**
+ * @brief Get the elapsed time in nsec for the timer.
+ * @param [in] desc         - Pointer to the device handler.
+ * @param [in] elapsed_time - The elapsed time in nsec.
+ * @return -ENOSYS.
+ */
+int32_t xilinx_timer_get_elapsed_time_nsec(struct timer_desc *desc,
+		uint64_t *elapsed_time)
+{
+	/* Function not implemented */
+	return -ENOSYS;
+}
+
+/**
+ * @brief Xilinx platform specific timer platform ops structure
+ */
+const struct timer_platform_ops xil_timer_ops = {
+	.init = &xilinx_timer_init,
+	.start = &xilinx_timer_start,
+	.stop = &xilinx_timer_stop,
+	.counter_get = &xilinx_timer_counter_get,
+	.counter_set = &xilinx_timer_counter_set,
+	.count_clk_get = &xilinx_timer_count_clk_get,
+	.count_clk_set = &xilinx_timer_count_clk_set,
+	.get_elapsed_time_nsec = &xilinx_timer_get_elapsed_time_nsec,
+	.remove = &xilinx_timer_remove
+};

df_datalink_ge/src/drivers/platform/xilinx_timer.h

@@ -0,0 +1,101 @@
+/***************************************************************************//**
+*   @file   xilinx_timer.h
+*   @brief  Timer control module header.
+*   @author Andrei Drimbarean ([email protected])
+********************************************************************************
+* Copyright 2020(c) Analog Devices, Inc.
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*  - Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*  - Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in
+*    the documentation and/or other materials provided with the
+*    distribution.
+*  - Neither the name of Analog Devices, Inc. nor the names of its
+*    contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*  - The use of this software may or may not infringe the patent rights
+*    of one or more patent holders.  This license does not release you
+*    from the requirement that you obtain separate licenses from these
+*    patent holders to use this software.
+*  - Use of the software either in source or binary form, must be run
+*    on or directly connected to an Analog Devices Inc. component.
+*
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef XILINX_TIMER_H_
+#define XILINX_TIMER_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <xparameters.h>
+#ifdef XPAR_XSCUTIMER_NUM_INSTANCES
+#include <xscutimer.h>
+#endif
+#ifdef XPAR_XTMRCTR_NUM_INSTANCES
+#include <xtmrctr.h>
+#endif
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum xil_timer_type
+ * @brief Xilinx platform architecture sections
+ */
+enum xil_timer_type {
+	/** Programmable Logic */
+	TIMER_PL,
+	/** Processing System */
+	TIMER_PS
+};
+
+/**
+ * @struct xil_timer_desc
+ * @brief Xilinx specific timer descriptor
+ */
+struct xil_timer_desc {
+	/** Pointer to the BSP driver handler */
+	void *instance;
+	/** Pointer to the BSP driver configuration handler */
+	void *config;
+	/** Timer used from the PL 3-timer core */
+	uint8_t active_tmr;
+	/** Platform selection parameter */
+	enum xil_timer_type type;
+};
+
+/**
+ * @struct xil_timer_init_param
+ * @brief Xilinx specific timer initialization structure
+ */
+struct xil_timer_init_param {
+	/** Timer used from the PL 3-timer core */
+	uint8_t active_tmr;
+	/** Platform selection parameter */
+	enum xil_timer_type type;
+};
+
+/**
+ * @brief Xilinx platform specific timer platform ops structure
+ */
+extern const struct timer_platform_ops xil_timer_ops;
+
+#endif /* XILINX_TIMER_H_ */

df_datalink_ge/src/hardware/common.c

@@ -0,0 +1,275 @@
+/**
+ * \file common.c
+ * \brief Contains Mykonos API common wrapper functions for user hardware platform drivers
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#include <stdio.h>
+#include <time.h>
+#include <errno.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "common.h" 
+#include "platform_drivers.h"
+#include "parameters.h"
+
+ADI_LOGLEVEL CMB_LOGLEVEL = ADIHAL_LOG_NONE;
+
+static uint32_t _desired_time_to_elapse_us = 0;
+struct spi_desc 	*spi_ad_desc;
+struct gpio_desc	*gpio_ad9371_resetb;
+struct gpio_desc	*gpio_ad9528_resetb;
+struct gpio_desc	*gpio_ad9528_sysref_req;
+
+commonErr_t CMB_initPlatform(void)
+{
+	struct spi_init_param spi_param;
+	int32_t status = COMMONERR_OK;
+
+	status |= gpio_get(&gpio_ad9371_resetb, AD9371_RESET_B);
+	status |= gpio_get(&gpio_ad9528_resetb, AD9528_RESET_B);
+	status |= gpio_get(&gpio_ad9528_sysref_req, AD9528_SYSREF_REQ);
+
+	spi_param.id = 0;
+	spi_param.mode = SPI_MODE_0;
+	spi_param.chip_select = AD9371_CS;
+	spi_param.max_speed_hz = 25000000u;
+
+	status |= spi_init(&spi_ad_desc, &spi_param);
+
+	if (status != SUCCESS) {
+		return COMMONERR_FAILED;
+	}
+
+	return COMMONERR_OK;
+}
+
+commonErr_t CMB_closeHardware(void)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_setGPIO(uint32_t GPIO)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex)
+{
+	struct gpio_desc *reset_gpio;
+
+	switch (spiChipSelectIndex) {
+	case AD9371_CS:
+		reset_gpio = gpio_ad9371_resetb;
+		break;
+	case AD9528_CS:
+		reset_gpio = gpio_ad9528_resetb;
+		break;
+	default:
+		return(COMMONERR_FAILED);
+	}
+
+	gpio_direction_output(reset_gpio, 1);
+	CMB_wait_ms(1);
+	gpio_direction_output(reset_gpio, 0);
+	CMB_wait_ms(1);
+	gpio_direction_output(reset_gpio, 1);
+	CMB_wait_ms(1);
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex )
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr,
+			     uint8_t data)
+{
+	uint8_t buf[3];
+
+	spi_ad_desc->chip_select = spiSettings->chipSelectIndex - 1;
+
+	buf[0] = (uint8_t) ((addr >> 8) & 0x7f);
+	buf[1] = (uint8_t) (addr & 0xff);
+	buf[2] = (uint8_t) data;
+
+	spi_write_and_read(spi_ad_desc, buf, 3);
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr,
+			      uint8_t *data, uint32_t count)
+{
+	uint32_t index;
+
+	for (index = 0; index < count; index++)
+		if (CMB_SPIWriteByte(spiSettings, *(addr + index),
+				     *(data + index)) != COMMONERR_OK)
+			return(COMMONERR_FAILED);
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_SPIReadByte(spiSettings_t *spiSettings, uint16_t addr,
+			    uint8_t *readdata)
+{
+	uint8_t buf[3];
+
+	spi_ad_desc->chip_select = spiSettings->chipSelectIndex - 1;
+
+	buf[0] = (uint8_t) ((addr >> 8) | 0x80);
+	buf[1] = (uint8_t) (addr & 0xff);
+	buf[2] = (uint8_t) 0x00;
+
+	spi_write_and_read(spi_ad_desc, buf, 3);
+	*readdata = buf[2];
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr,
+			      uint8_t field_val, uint8_t mask, uint8_t start_bit)
+{
+	uint8_t data;
+
+	if (CMB_SPIReadByte(spiSettings, addr, &data) != COMMONERR_OK)
+		return(COMMONERR_FAILED);
+
+	data = (data & ~mask) | ((field_val << start_bit) & mask);
+
+	if (CMB_SPIWriteByte(spiSettings, addr, data) != COMMONERR_OK)
+		return(COMMONERR_FAILED);
+
+	return(COMMONERR_OK);
+}
+
+/* read a field in a single register space (not multibyte fields) */
+commonErr_t CMB_SPIReadField(spiSettings_t *spiSettings, uint16_t addr,
+			     uint8_t *field_val, uint8_t mask, uint8_t start_bit)
+{
+	uint8_t data;
+
+	if (CMB_SPIReadByte(spiSettings, addr, &data) != COMMONERR_OK)
+		return(COMMONERR_FAILED);
+
+	data = (data & mask) >> start_bit;
+	*field_val = data;
+
+	return(COMMONERR_OK);
+}
+
+
+commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex,
+			   uint32_t errorCode, const char *comment)
+{
+
+	if((CMB_LOGLEVEL & ADIHAL_LOG_ERROR) && (level == ADIHAL_LOG_ERROR)) {
+		printf("ERROR: %d: %s", (int)errorCode, comment);
+	} else if((CMB_LOGLEVEL & ADIHAL_LOG_WARNING)
+		  && (level == ADIHAL_LOG_WARNING)) {
+		printf("WARNING: %d: %s",(int)errorCode, comment);
+	} else if((CMB_LOGLEVEL & ADIHAL_LOG_MESSAGE)
+		  && (level == ADIHAL_LOG_MESSAGE)) {
+		printf("MESSAGE: %d: %s",(int)errorCode, comment);
+	} else if(CMB_LOGLEVEL == ADIHAL_LOG_NONE ) {
+		//printf("MESSAGE: %d: %s",(int)errorCode, comment);
+	} else {
+		printf("Undefined Log Level: 0x%X", level);
+	}
+
+	return(COMMONERR_OK);
+}
+
+/* if filename null, a default path will be used in logging.c */
+commonErr_t CMB_openLog(const char *filename)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_closeLog(void)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_flushLog(void)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_wait_ms(uint32_t time_ms)
+{
+	mdelay(time_ms);
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_wait_us(uint32_t time_us)
+{
+	udelay(time_us);
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms)
+{
+#ifdef _XPARAMETERS_PS_H_
+	_desired_time_to_elapse_us = timeOut_ms * 1000;
+#else
+	_desired_time_to_elapse_us = timeOut_ms * 50;	// FIXME
+#endif
+
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_setTimeout_us(uint32_t timeOut_us)
+{
+	_desired_time_to_elapse_us = timeOut_us;
+
+	return(COMMONERR_OK);
+}
+
+
+commonErr_t CMB_hasTimeoutExpired()
+{
+	udelay(1);
+
+	_desired_time_to_elapse_us--;
+	if (_desired_time_to_elapse_us > 0)
+		return(COMMONERR_OK);
+
+	return(COMMONERR_FAILED);
+}
+
+commonErr_t CMB_regRead(uint32_t offset, uint32_t *data)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_regWrite(uint32_t offset, uint32_t data)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len)
+{
+	return(COMMONERR_OK);
+}
+
+commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len)
+{
+	return(COMMONERR_OK);
+}

df_datalink_ge/src/hardware/common.h

@@ -0,0 +1,131 @@
+/**
+ * \file common.h
+ * \brief Contains type definitions and prototype declarations for common.c
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* build project settings include the path to the desired platform folder for correct includes */
+#include "stdint.h"
+
+#define THROW_ERROR()
+
+#define SPIARRAYSIZE 1024
+
+/* assuming 3 byte SPI message - integer math enforces floor() */
+#define SPIARRAYTRIPSIZE ((SPIARRAYSIZE / 3) * 3)
+
+/*========================================
+ * Enums and structures
+ *=======================================*/
+/* proposed to increase number of error return values to make unique for each return */
+typedef enum
+{
+    ADIERR_OK=0,
+    ADIERR_INV_PARM,
+    ADIERR_FAILED
+} ADI_ERR;
+
+/*!< \brief COMMON layer error reporting enumerated types */
+typedef enum
+{
+    COMMONERR_OK=0,
+    COMMONERR_FAILED
+} commonErr_t;
+
+/* bit 0 is MESSAGE, bit 1 is WARNING, bit 2 is ERROR */
+typedef enum
+{
+    ADIHAL_LOG_NONE    = 0x0,
+    ADIHAL_LOG_MESSAGE = 0x1,
+    ADIHAL_LOG_WARNING = 0x2,
+    ADIHAL_LOG_ERROR   = 0x4,
+	ADIHAL_LOG_SPI     = 0x8,
+	ADIHAL_LOG_AXI_REG = 0x10,
+	ADIHAL_LOG_AXI_MEM = 0x20,
+	ADIHAL_LOG_ALL     = 0x3F
+} ADI_LOGLEVEL;
+
+/**
+ * \brief Data structure to hold SPI settings for all system device types
+ */
+typedef struct
+{
+	uint8_t chipSelectIndex;        ///< valid 1~8
+	uint8_t writeBitPolarity;       ///< the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation
+	uint8_t longInstructionWord;    ///< 1 = 16bit instruction word, 0 = 8bit instruction word
+	uint8_t MSBFirst;               ///< 1 = MSBFirst, 0 = LSBFirst
+	uint8_t CPHA;                   ///< clock phase, sets which clock edge the data updates (valid 0 or 1)
+	uint8_t CPOL;                   ///< clock polarity 0 = clock starts low, 1 = clock starts high
+    uint8_t enSpiStreaming;         ///< Not implemented. SW feature to improve SPI throughput.
+    uint8_t autoIncAddrUp;          ///< Not implemented. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr = addr-1
+    uint8_t fourWireMode;           ///< 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode.
+    uint32_t spiClkFreq_Hz;         ///< SPI Clk frequency in Hz (default 25000000), platform will use next lowest frequency that it's baud rate generator can create */
+
+} spiSettings_t;
+
+/* global variable so application layer can set the log level */
+extern ADI_LOGLEVEL CMB_LOGLEVEL;
+extern struct spi_desc 	*spi_ad_desc;
+extern struct gpio_desc	*gpio_ad9371_resetb;
+extern struct gpio_desc	*gpio_ad9528_resetb;
+extern struct gpio_desc	*gpio_ad9528_sysref_req;
+
+/* initialize hardware platform */
+commonErr_t CMB_initPlatform(void);
+
+/* close hardware pointers */
+commonErr_t CMB_closeHardware(void);
+
+/* GPIO function */
+commonErr_t CMB_setGPIO(uint32_t GPIO);
+
+/* hardware reset function */
+commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex);
+
+/* SPI read/write functions */
+commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings); /* allows the platform HAL to work with devices with various SPI settings */
+commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex );  /* value of 0 deasserts all chip selects */
+commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr, uint8_t data); /* single SPI byte write function */
+commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr, uint8_t *data, uint32_t count);
+commonErr_t CMB_SPIReadByte (spiSettings_t *spiSettings, uint16_t addr, uint8_t *readdata); /* single SPI byte read function */
+commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr, uint8_t  field_val, uint8_t mask, uint8_t start_bit); /* write a field in a single register */
+commonErr_t CMB_SPIReadField (spiSettings_t *spiSettings, uint16_t addr, uint8_t *field_val, uint8_t mask, uint8_t start_bit);	/* read a field in a single register */
+
+/* platform timer functions */
+commonErr_t CMB_wait_ms(uint32_t time_ms);
+commonErr_t CMB_wait_us(uint32_t time_us);
+commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms);
+commonErr_t CMB_setTimeout_us(uint32_t timeOut_us);
+commonErr_t CMB_hasTimeoutExpired();
+
+/* platform logging functions */
+commonErr_t CMB_openLog(const char *filename);
+commonErr_t CMB_closeLog(void);
+commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex, uint32_t errorCode, const char *comment);
+commonErr_t CMB_flushLog(void);
+
+/* platform FPGA AXI register read/write functions */
+commonErr_t CMB_regRead(uint32_t offset, uint32_t *data);
+commonErr_t CMB_regWrite(uint32_t offset, uint32_t data);
+
+/* platform DDR3 memory read/write functions */
+commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len);
+commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

df_datalink_ge/src/hardware/headless.h

@@ -0,0 +1,348 @@
+/*
+ * headless.h
+ *
+ *  Created on: 2021Äê6ÔÂ8ÈÕ
+ *      Author: Josh
+ */
+
+#ifndef SRC_HEADLESS_H_
+#define SRC_HEADLESS_H_
+
+/***************************** Include Files ********************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include "xil_cache.h"
+#include "xscugic.h"
+//#include "xgpio.h"
+
+#include "common.h"
+#include "./mykonos/ad9528.h"
+#include "./mykonos/mykonos.h"
+#include "./mykonos/Mykonos_M3.h"
+#include "./mykonos/mykonos_gpio.h"
+#include "myk_ad9528init.h"
+#include "myk_init.h"
+
+#include "parameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/*
+*
+* This function setups ad9528 and ad9371 via spi.
+*
+* @param	None.
+*
+* @return
+*       - ADIERR_FAILED if successful,
+*       - ADIERR_OK if not succesful
+*
+* @note     None.
+*
+******************************************************************************/
+int HARDWARE_initialize();
+
+int HARDWARE_ad9371Config(void);
+
+/*****************************************************************************/
+/*
+*
+* Setup up Axi Gpio, through which ad9371 can be reconfigured. Axi Gpio
+* instance and interrupt system initialization are included.
+*
+* @param	None.
+*
+* @return
+*       - ADIERR_FAILED if successful,
+*       - ADIERR_OK if not succesful
+*
+* @note     None.
+*
+******************************************************************************/
+int HW_ad9371DynamicCfgInit(void);
+
+/*****************************************************************************/
+/*
+*
+* Setup up interrupt system, initialize exception handlers.
+*
+* @param	DeviceId is the unique identifier for a device.
+* @param	GicPtr is a pointer to the XScuGic instance.
+*
+* @return
+*       - XST_SUCCESS if successful,
+*       - XST_FAILURE if not succesful
+*
+* @note     None.
+*
+******************************************************************************/
+int HW_setupIntrSystem(u16 DeviceId, XScuGic * GicPtr);
+
+/*****************************************************************************/
+/*
+*
+* Make the connection between the Int_Id of the interrupt source and the
+* associated handler. Set the interrupt priority and trigger type  for the
+* specified IRQ source..
+*
+* @param	GicPtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param	Handler to the handler for that interrupt.
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+*           priority, 0xF8(248) is lowest. There are 32 priority levels
+*           supported with a step of 8. Hence the supported priorities are
+*           0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return
+*       - XST_SUCCESS if successful,
+*       - XST_FAILURE if not succesful
+*
+* @note     None.
+*
+******************************************************************************/
+int HW_connectIntr(XScuGic *GicPtr,u32 IntrId,Xil_InterruptHandler Handler,
+		void *CallBackRef, u8 Priority, u8 Trigger);
+
+/*****************************************************************************/
+/*
+*
+* Initialize Analog Device related configuration profile. This is a HARDWARE-
+* ASSOTIATED function, which may differ between different board.
+*
+* @param	None.
+*
+* @return
+*       - ADIERR_OK if configuration profile exists,
+*       - ADIERR_FAILED if onfiguration profile does not exist
+*
+* @note     None.
+*
+******************************************************************************/
+int HW_adiCfgProfileInit(void);
+
+/******************************************************************************/
+/**
+*
+* This function conducts AD9528 device configuration initializing procedure.
+*
+* @param	clockAD9528_device is a pointer to the data structure holding
+* 			AD9528 settings, which contains basic AD9528 settings such as
+* 			spi and gpio.
+*
+* @return
+*       - ADIERR_OK if successful.
+*       - ADIERR_FAILED if not successful.
+*
+* @note		None.
+*
+*******************************************************************************/
+int HW_9528Config(ad9528Device_t *clockAD9528_device);
+
+/******************************************************************************/
+/**
+*
+* This function read AD9528 reg508 status, to check whether ad9528 is locked or
+* not.
+*
+* @param	clockAD9528_device is a pointer to the data structure holding
+* 			AD9528 settings, which contains basic AD9528 settings.
+*
+* @return
+*       - ADIERR_OK if successful.
+*       - ADIERR_FAILED if not successful.
+*
+* @note		None.
+*
+*******************************************************************************/
+int HW_9528GetLockStatus(ad9528Device_t *device, uint8_t *reg508);
+
+/******************************************************************************/
+/**
+*
+* Conduct AD9371 device configuration initializing procedure.
+*
+* @param	clockAD9528_device is a pointer to the data structure holding
+* 			AD9528 settings, which contains basic AD9528 settings.
+* @param	mykDevice is ADI hardware layer settings pointer specific to
+* 			a Mykonos instance which contains basic settings such as spi,
+* 			gpio, tx/rx and jesd configurations.
+*
+* @return
+*       - ADIERR_OK if successful.
+*       - ADIERR_FAILED if not successful.
+*
+* @note		None.
+*
+*******************************************************************************/
+int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice);
+
+/******************************************************************************/
+/**
+*
+* Read AD9371's RX framer, ORX framer and TX deframer status, to check jesd204b
+* sync status.
+*
+* @param	mykDevice is ADI hardware layer settings pointer specific to
+* 			a Mykonos instance which contains basic settings such as spi,
+* 			gpio, tx/rx and jesd configurations.
+* @param	framerStatus is the RX framer status byte read
+* framerStatus |  Description
+* -------------|-----------------------------------------------------------------------------
+*         [7]  | SYSREF phase error ? a new SYSREF had different timing than the first that set the LMFC timing.
+*         [6]  | Framer lane FIFO read/write pointer delta has changed.  Can help debug issues with deterministic latency.
+*         [5]  | Framer has received the SYSREF and has retimed its LMFC
+*       [4:2]  | Framer ILAS state: 0=CGS, 1= 1st Multframe, 2= 2nd Multiframe, 3= 3rd Multiframe, 4= 4th multiframe, 5= Last multiframe, 6=invalid, 7= ILAS complete
+*       [1:0]  | Framer Tx state: 0=CGS, 1= ILAS, 2 = ADC Data
+* @param	obsFramerStatus is the ORX framer status byte read
+* obsFramerStatus |  Description
+* ----------------|-----------------------------------------------------------------------------
+*            [7]  | SYSREF phase error ? a new SYSREF had different timing than the first that set the LMFC timing.
+*            [6]  | Framer lane FIFO read/write pointer delta has changed.  Can help debug issues with deterministic latency.
+*            [5]  | Framer has received the SYSREF and has retimed its LMFC
+*          [4:2]  | Framer ILAS state: 0=CGS, 1= 1st Multframe, 2= 2nd Multiframe, 3= 3rd Multiframe, 4= 4th multiframe, 5= Last multiframe, 6=invalid, 7= ILAS complete
+*          [1:0]  | Framer Tx state: 0=CGS, 1= ILAS, 2 = ADC Data
+* @param	deframerStatus  is the TX deframer status byte read
+* deframerStatus  |  Bit Name                |  Description
+* ----------------|--------------------------|---------------------------------------------
+*            [7]  | Unused                   | Unused
+*            [6]  | Deframer IRQ             | This bit indicates that the IRQ interrupt was asserted.
+*            [5]  | Deframer SYSREF Received | When this bit is set, it indicates that the SYSREF pulse was received by the deframer IP
+*            [4]  | Deframer Receiver Error  | This bit is set when PRBS has received an error.
+*            [3]  | Valid Checksum           | This bit is set when the received ILAS checksum is valid.
+*            [2]  | EOF Event                | This bit captures the internal status of the framer End of Frame event. Value =1 if framing error during ILAS
+*            [1]  | EOMF Event               | This bit captures the internal status of the framer End of Multi-Frame event. Value =1 if framing error during ILAS
+*            [0]  | FS Lost                  | This bit captures the internal status of the framer Frame Symbol event. Value =1 if framing error during ILAS or user data (invalid replacement characters)
+*
+* @return
+*       - ADIERR_OK if successful.
+*       - ADIERR_FAILED if not successful.
+*
+* @note		None.
+*
+*******************************************************************************/
+int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus,
+		uint8_t *obsFramerStatus, uint8_t *deframerStatus);
+
+/******************************************************************************/
+/**
+*
+* This function conducts AD9371/9375 samll RF PLL frequcny change procedure. The
+* procedure is performed as follows:
+*	1. Move the device into the radio off state.
+*	2. Program the new local oscillator (LO) frequency.
+*	3. Reset the external channel.(ignored)
+* 	4. Move the device back into the radio on state.
+*	5. Reenable tracking calibrations.(ignored)
+*
+* @param	mykDevice is ADI hardware layer settings pointer specific to
+* 			a Mykonos instance which contains basic settings such as spi,
+* 			gpio, tx/rx and jesd configurations.
+* @param	freq_Hz is the target frequancy in Hz.
+*
+* @return	None.
+*
+* @note		The procedure is used when a radio frequency (RF) phased-lock loop
+*		(PLL) change is required with the following conditions:
+*		- A desire to change the Rx, Tx, and ORx frequencies.
+* 		- The frequency step change is less than 100 MHz.
+* 		- The frequency step does not cross the divide by 2 boundaries outlined
+*			in AD9371/9375-UG-992-Rev.B-Table 96.
+*
+*******************************************************************************/
+int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz);
+
+/******************************************************************************/
+/**
+*
+* This function conducts AD9371/9375 large RF PLL frequcny change procedure. The
+* procedure is performed as follows:
+*	1. Move the device into the radio off state.
+*	2. Program the new local oscillator (LO) frequency.
+*	3. Rerun the initialization calibrations.
+* 	4. Move the device back into the radio on state.
+*	5. Reenable tracking calibrations.(ignored)
+*
+* @param	mykDevice is ADI hardware layer settings pointer specific to
+* 			a Mykonos instance which contains basic settings such as spi,
+* 			gpio, tx/rx and jesd configurations.
+* @param	freq_Hz is the target frequancy in Hz.
+*
+* @return	None.
+*
+* @note		The procedure is used when a radio frequency (RF) phased-lock loop
+*		(PLL) change is required with the following conditions:
+*		- A desire to change the Rx, Tx, and ORx frequencies.
+* 		- The frequency step change is more than 100 MHz.
+* 		- The frequency step does cross the divide by 2 boundaries outlined
+*			in AD9371/9375-UG-992-Rev.B-Table 96.
+*
+*******************************************************************************/
+int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz);
+
+/******************************************************************************/
+/**
+*
+* Handles AD9371 TX & RX frequency change axi gpio interruput.
+*
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return	None.
+*
+* @note		None.
+*
+*******************************************************************************/
+void FreqIntrHandler(void *CallbackRef);
+
+/******************************************************************************/
+/**
+*
+* Handles AD9371 Rx gain index change axi gpio interruput.
+*
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return	None.
+*
+* @note		None.
+*
+*******************************************************************************/
+void GainIntrHandler(void *CallbackRef);
+
+/******************************************************************************/
+/**
+*
+* Handles AD9371 Tx attenuation change axi gpio interruput.
+*
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return	None.
+*
+* @note		None.
+*
+*******************************************************************************/
+void AttnIntrHandler(void *CallbackRef);
+
+#endif /* SRC_HEADLESS_H_ */

df_datalink_ge/src/hardware/myk_ad9528init.c

@@ -0,0 +1,189 @@
+///*
+// * myk_clock_init.c
+// *
+// */
+//
+///**
+//* \page Disclaimer Legal Disclaimer
+//* Copyright 2015-2017 Analog Devices Inc.
+//* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+//*
+//*/
+//
+//#ifndef MYK_CLOCK_INIT_C_
+//#define MYK_CLOCK_INIT_C_
+//#include <stdint.h>
+//#include <stdlib.h>
+//#include <stddef.h>
+//#include "common.h"
+//
+//#include "ad9528.h"
+//#include "t_ad9528.h"
+//#include "myk_ad9528init.h"
+//#include "parameters.h"
+//
+//static ad9528pll1Settings_t clockPll1Settings =
+//{
+//	.refA_Frequency_Hz  = 30720000,
+//	.refA_Divider       = 1,
+//	.refA_bufferCtrl    = DISABLED,
+//	.refB_Frequency_Hz  = 0,
+//	.refB_Divider       = 1,
+//	.refB_bufferCtrl    = DISABLED,
+//	.vcxo_Frequency_Hz  = 122880000,
+//	.vcxoBufferCtrl     = NEG_SINGLE_ENDED,
+//	.nDivider           = 4,
+//	.bypassPll1			= 0
+//};
+//
+//static ad9528pll2Settings_t clockPll2Settings =
+//{
+//	.rfDivider = 4,
+//	.n2Divider = 10,
+//	.totalNdiv = 30
+//};
+//
+//static ad9528outputSettings_t clockOutputSettings =
+//{
+//	.outPowerDown 		= 53237, // 0xCFF5
+//	.outSource 			= {
+//			CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, SYSREF,
+//			CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV,
+//			CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV,
+//			SYSREF,		 CHANNEL_DIV},
+//	.outBufferCtrl  	= {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+//	.outAnalogDelay 	= {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+//	.outDigitalDelay 	= {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+//	.outChannelDiv 		= {10,10,10,10,10,10,10,10,10,10,10,10,10,10},
+//	.outFrequency_Hz 	= {122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000}
+//};
+//
+//static ad9528sysrefSettings_t clockSysrefSettings =
+//{
+//	.sysrefRequestMethod    = PIN,
+//	.sysrefSource           = INTERNAL,
+//	.sysrefPinEdgeMode      = LEVEL_ACTIVE_HIGH,
+//	.sysrefPinBufferMode    = DISABLED,
+//	.sysrefPatternMode      = NSHOT,
+//	.sysrefNshotMode        = ONE_PULSE,
+//	.sysrefDivide           = 512
+//};
+//
+//static spiSettings_t clockSpiSettings =
+//{
+//	.chipSelectIndex        = AD9528_CS, //chip select Index
+//	.writeBitPolarity       = 0, //Write bit polarity
+//	.longInstructionWord    = 1, //16bit instruction word
+//	.MSBFirst               = 1, //MSB first
+//	.CPHA                   = 0, //Clock phase
+//	.CPOL                   = 0, //Clock polarity
+//	.enSpiStreaming         = 0, //uint8_t enSpiStreaming;
+//	.autoIncAddrUp          = 1, //uint8_t autoIncAddrUp;
+//	.fourWireMode           = 1  //uint8_t fourWireMode;
+//};
+//
+//ad9528Device_t clockAD9528_ =
+//{
+//	&clockSpiSettings,
+//	&clockPll1Settings,
+//	&clockPll2Settings,
+//	&clockOutputSettings,
+//	&clockSysrefSettings
+//};
+//
+//ad9528Device_t *ad9528Init = &clockAD9528_;
+//
+//#endif /* MYK_CLOCK_INIT_C_ */
+
+
+/* AD9528 data structure initialization file */
+#include <stdint.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include "common.h"
+
+#include "./mykonos/ad9528.h"
+#include "./mykonos/t_ad9528.h"
+#include "myk_ad9528init.h"
+#include "parameters.h"
+
+static ad9528pll1Settings_t clockPll1Settings = {
+    .refA_Frequency_Hz  = 122880000,
+    .refA_Divider       = 1,
+    .refA_bufferCtrl    = SINGLE_ENDED,
+    .refB_Frequency_Hz  = 0,
+    .refB_Divider       = 1,
+    .refB_bufferCtrl    = DISABLED,
+    .vcxo_Frequency_Hz  = 122880000,
+    .vcxoBufferCtrl     = DIFFERENTIAL,
+    .nDivider           = 1,
+	.bypassPll1 		= 0
+};
+
+static ad9528pll2Settings_t clockPll2Settings = {
+    .rfDivider = 3,
+    .n2Divider = 10,
+    .totalNdiv = 30
+};
+
+/*******************************************************************
+ * Output Distribution Settings
+ * 9369CE02A uses the following clock outputs
+ * OUT 1: FPGA_REF_CLK
+ * OUT 2: FPGA_AUX_CLK
+ * OUT 3: FPGA_SYSREF
+ * OUT 12: SYSREF_IN
+ * OUT 13: DEV_CLK_IN
+ *******************************************************************
+ */
+static ad9528outputSettings_t clockOutputSettings = {
+    .outPowerDown       = 0x0,
+    .outSource          = {
+    	SYSREF,      SYSREF,      CHANNEL_DIV, SYSREF,
+    	CHANNEL_DIV, CHANNEL_DIV, SYSREF,      SYSREF,
+    	CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV,
+    	SYSREF     , CHANNEL_DIV
+    },
+    .outBufferCtrl      = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+    .outAnalogDelay     = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+    .outDigitalDelay    = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+    .outChannelDiv      = {10,10,10,10,10,10,10,10,10,10,10,10,10,10},
+    .outFrequency_Hz    = {
+    		122880000, 122880000, 122880000, 122880000,
+			122880000, 122880000, 122880000, 122880000,
+			122880000, 122880000, 122880000, 122880000,
+			122880000, 122880000
+    }
+};
+
+static ad9528sysrefSettings_t clockSysrefSettings = {
+    .sysrefRequestMethod    = SPI,
+    .sysrefSource           = INTERNAL,
+    .sysrefPinEdgeMode      = LEVEL_ACTIVE_HIGH,
+    .sysrefPinBufferMode    = DISABLED,
+    .sysrefPatternMode      = CONTINUOUS,
+    .sysrefNshotMode        = FOUR_PULSES,
+    .sysrefDivide           = 512
+};
+
+static spiSettings_t clockSpiSettings = {
+    .chipSelectIndex        = 2, //chip select Index
+    .writeBitPolarity       = 0, //Write bit polarity
+    .longInstructionWord    = 1, //16bit instruction word
+    .MSBFirst               = 1, //MSB first
+    .CPHA                   = 0, //Clock phase
+    .CPOL                   = 0, //Clock polarity
+    .enSpiStreaming         = 0, //uint8_t enSpiStreaming;
+    .autoIncAddrUp          = 1, //uint8_t autoIncAddrUp;
+    .fourWireMode           = 1  //uint8_t fourWireMode;
+};
+
+ad9528Device_t clockAD9528_ = {
+    &clockSpiSettings,
+    &clockPll1Settings,
+    &clockPll2Settings,
+    &clockOutputSettings,
+    &clockSysrefSettings
+};
+
+ad9528Device_t *ad9528Init = &clockAD9528_;

df_datalink_ge/src/hardware/myk_ad9528init.h

@@ -0,0 +1,20 @@
+/*
+ * myk_clock_init.h
+ *
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef MYK_CLOCK_INIT_H_
+#define MYK_CLOCK_INIT_H_
+
+#include "./mykonos/ad9528.h"
+
+extern ad9528Device_t *ad9528Init;
+
+#endif /* MYK_CLOCK_INIT_H_ */

df_datalink_ge/src/hardware/myk_init.c

@@ -0,0 +1,558 @@
+/**
+ * \file myk_init.c
+ *
+ * \brief Contains init setting structure declarations for the _instance API
+ *
+ * The top level structure mykonosDevice_t mykDevice uses keyword
+ * extern to allow the application layer main() to have visibility
+ * to these settings.
+ *
+ * All data structures required for operation have been initialized with values which reflect
+ * these settings:
+ *
+ * Device Clock = $122.88$ Mhz
+ * Rx enabled channels = $2$
+ * Tx enabled channels = $2$
+ *
+ * Mykonos Framer:
+ * Lane Rate = $4915.2$ Mbs
+ * L = $2$
+ * K = $32$
+ * M = $4$
+ * F = $4$
+ *
+ * Mykonos Deframer:
+ * Lane Rate = $4915.2$ Mbs
+ * L = $2$
+ * K = $32$
+ * M = $4$
+ * F = $4$
+ *
+ * Mykonos Observation framer:
+ * Lane Rate = $4915.2$ Mbs
+ * L = $2$
+ * K = $32$
+ * M = $4$
+ * F = $4$
+ *
+ * Using these profiles:
+ * $Rx 100Mhz, IQrate 122.88Mhz, Dec5$
+ * $Tx 100/100Mhz, IQrate 122.88Mhz, Dec5$
+ * $ORX 100Mhz, IQrate 122.88Mhz, Dec5$
+ * $SRx 20Mhz, IQrate 30.72Mhz, Dec5$
+ *
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#include <stddef.h>
+#include "./mykonos/t_mykonos.h"
+#include "myk_init.h"
+#include "parameters.h"
+#include "./mykonos/mykonos_gpio.h"
+
+static int16_t txFirCoefs[] = {-94,-26,282,177,-438,-368,756,732,-1170,-1337,1758,2479,-2648,-5088,4064,16760,16759,4110,-4881,-2247,2888,1917,-1440,-1296,745,828,-358,-474,164,298,-16,-94};
+
+static mykonosFir_t txFir =
+{
+    6,              /* Filter gain in dB*/
+    32,             /* Number of coefficients in the FIR filter*/
+    &txFirCoefs[0]  /* A pointer to an array of filter coefficients*/
+};
+
+static int16_t rxFirCoefs[] = {-20,6,66,22,-128,-54,240,126,-402,-248,634,444,-956,-756,1400,1244,-2028,-2050,2978,3538,-4646,-7046,9536,30880,30880,9536,-7046,-4646,3538,2978,-2050,-2028,1244,1400,-756,-956,444,634,-248,-402,126,240,-54,-128,22,66,6,-20};
+
+static mykonosFir_t rxFir =
+{
+    -6,             /* Filter gain in dB*/
+    48,             /* Number of coefficients in the FIR filter*/
+    &rxFirCoefs[0]  /* A pointer to an array of filter coefficients*/
+};
+
+static int16_t obsrxFirCoefs[] = {-14,-19,44,41,-89,-95,175,178,-303,-317,499,527,-779,-843,1184,1317,-1781,-2059,2760,3350,-4962,-7433,9822,32154,32154,9822,-7433,-4962,3350,2760,-2059,-1781,1317,1184,-843,-779,527,499,-317,-303,178,175,-95,-89,41,44,-19,-14};
+static mykonosFir_t obsrxFir =
+{
+    -6,             /* Filter gain in dB*/
+    48,             /* Number of coefficients in the FIR filter*/
+    &obsrxFirCoefs[0]/* A pointer to an array of filter coefficients*/
+};
+
+static int16_t snifferFirCoefs[] = {-1,-5,-14,-23,-16,24,92,137,80,-120,-378,-471,-174,507,1174,1183,98,-1771,-3216,-2641,942,7027,13533,17738,17738,13533,7027,942,-2641,-3216,-1771,98,1183,1174,507,-174,-471,-378,-120,80,137,92,24,-16,-23,-14,-5,-1};
+static mykonosFir_t snifferRxFir=
+{
+    -6,             /* Filter gain in dB*/
+    48,             /* Number of coefficients in the FIR filter*/
+    &snifferFirCoefs[0]/* A pointer to an array of filter coefficients*/
+};
+
+static mykonosJesd204bFramerConfig_t rxFramer =
+{
+    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
+    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
+    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
+    4,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
+    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
+    0,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
+    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/
+    0x03,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
+    0xE4,           /* serializerLaneCrossbar*/
+    22,             /* serializerAmplitude - default 22 (valid (0-31)*/
+    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/
+    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
+    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
+    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
+    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
+    0,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
+    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
+    0,              /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
+    0               /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/
+};
+
+static mykonosJesd204bFramerConfig_t obsRxFramer =
+{
+    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
+    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
+    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
+    2,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
+    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
+    0,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
+    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/
+    0x04,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
+    0xE4,           /* Lane crossbar to map framer lane outputs to physical lanes*/
+    22,             /* serializerAmplitude - default 22 (valid (0-31)*/
+    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/
+    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
+    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
+    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
+    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
+    1,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
+    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
+    0,              /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
+    0               /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/
+};
+
+static mykonosJesd204bDeframerConfig_t deframer =
+{
+    0,              /* bankId extension to Device ID (Valid 0..15)*/
+    0,              /* deviceId  link identification number. (Valid 0..255)*/
+    0,              /* lane0Id Lane0 ID. (Valid 0..31)*/
+    4,              /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
+    32,             /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)*/
+    0,              /* scramble  scrambling off if scramble= 0.*/
+    1,              /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/
+    0x03,           /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
+    0xE4,           /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */
+    1,              /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/
+    0,              /* PN inversion per each lane.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).*/
+    0,              /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/
+    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set*/
+    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
+    0,              /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
+    0               /* Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used*/
+};
+
+static mykonosRxGainControl_t rxGainControl =
+{
+    MGC,            /* Current Rx gain control mode setting*/
+    255,            /* Rx1 Gain Index, can be used in different ways for manual and AGC gain control*/
+    255,            /* Rx2 Gain Index, can be used in different ways for manual and AGC gain control*/
+    255,            /* Max gain index for the currently loaded Rx1 Gain table*/
+    195,            /* Min gain index for the currently loaded Rx1 Gain table*/
+    255,            /* Max gain index for the currently loaded Rx2 Gain table*/
+    195,            /* Min gain index for the currently loaded Rx2 Gain table*/
+    0,              /* Stores Rx1 RSSI value read back from the Mykonos*/
+    0               /* Stores Rx2 RSSI value read back from the Mykonos*/
+};
+
+
+static mykonosORxGainControl_t orxGainControl =
+{
+    MGC,            /* Current ORx gain control mode setting*/
+    255,            /* ORx1 Gain Index, can be used in different ways for manual and AGC gain control*/
+    255,            /* ORx2 Gain Index, can be used in different ways for manual and AGC gain control*/
+    255,            /* Max gain index for the currently loaded ORx Gain table*/
+    237             /* Min gain index for the currently loaded ORx Gain table*/
+};
+
+static mykonosSnifferGainControl_t snifferGainControl =
+{
+    MGC,            /* Current Sniffer gain control mode setting*/
+    255,            /* Current Sniffer gain index. Can be used differently for MANUAL Gain control/AGC*/
+    255,            /* Max gain index for the currently loaded Sniffer Gain table*/
+    203             /* Min gain index for the currently loaded Sniffer Gain table*/
+};
+
+static mykonosPeakDetAgcCfg_t rxPeakAgc =
+{
+	0x0C,	/* apdHighThresh: */
+	0x08,	/* apdLowThresh */
+	0xB5,	/* hb2HighThresh */
+	0x80,	/* hb2LowThresh */
+	0x40,	/* hb2VeryLowThresh */
+	0x06,	/* apdHighThreshExceededCnt */
+	0x04,	/* apdLowThreshExceededCnt */
+	0x06,	/* hb2HighThreshExceededCnt */
+	0x04,	/* hb2LowThreshExceededCnt */
+	0x04,	/* hb2VeryLowThreshExceededCnt */
+	0x4,	/* apdHighGainStepAttack */
+	0x2,	/* apdLowGainStepRecovery */
+	0x4,	/* hb2HighGainStepAttack */
+	0x2,	/* hb2LowGainStepRecovery */
+	0x4,	/* hb2VeryLowGainStepRecovery */
+	0x1,	/* apdFastAttack */
+	0x1,	/* hb2FastAttack */
+	0x1,	/* hb2OverloadDetectEnable */
+	0x1,	/* hb2OverloadDurationCnt */
+	0x1	/* hb2OverloadThreshCnt */
+};
+
+static mykonosPowerMeasAgcCfg_t rxPwrAgc =
+{
+    0x01,	/* pmdUpperHighThresh */
+    0x03,	/* pmdUpperLowThresh */
+    0x0C,	/* pmdLowerHighThresh */
+    0x00,	/* pmdLowerLowThresh */
+    0x4,	/* pmdUpperHighGainStepAttack */
+    0x2,	/* pmdUpperLowGainStepAttack */
+    0x2,	/* pmdLowerHighGainStepRecovery */
+    0x4,	/* pmdLowerLowGainStepRecovery */
+    0x08,	/* pmdMeasDuration */
+    0x02	/* pmdMeasConfig */
+};
+
+static mykonosAgcCfg_t rxAgcConfig =
+{
+    255,	/* agcRx1MaxGainIndex */
+    195,	/* agcRx1MinGainIndex */
+    255,	/* agcRx2MaxGainIndex */
+    195,	/* agcRx2MinGainIndex: */
+    255,	/* agcObsRxMaxGainIndex */
+    203,	/* agcObsRxMinGainIndex */
+    1,		/* agcObsRxSelect */
+    1,		/* agcPeakThresholdMode */
+    1,		/* agcLowThsPreventGainIncrease */
+	30720,	/* agcGainUpdateCounter */
+    3,	/* agcSlowLoopSettlingDelay */
+    2,	/* agcPeakWaitTime */
+    1,	/* agcResetOnRxEnable */
+    0,	/* agcEnableSyncPulseForGainCounter */
+    &rxPeakAgc,
+    &rxPwrAgc
+};
+
+static mykonosPeakDetAgcCfg_t obsRxPeakAgc =
+{
+	0x1F,	/* apdHighThresh: */
+	0x16,	/* apdLowThresh */
+	0xB5,	/* hb2HighThresh */
+	0x80,	/* hb2LowThresh */
+	0x40,	/* hb2VeryLowThresh */
+	0x06,	/* apdHighThreshExceededCnt */
+	0x04,	/* apdLowThreshExceededCnt */
+	0x06,	/* hb2HighThreshExceededCnt */
+	0x04,	/* hb2LowThreshExceededCnt */
+	0x04,	/* hb2VeryLowThreshExceededCnt */
+	0x4,	/* apdHighGainStepAttack */
+	0x2,	/* apdLowGainStepRecovery */
+	0x4,	/* hb2HighGainStepAttack */
+	0x2,	/* hb2LowGainStepRecovery */
+	0x4,	/* hb2VeryLowGainStepRecovery */
+	0x1,	/* apdFastAttack */
+	0x1,	/* hb2FastAttack */
+	0x1,	/* hb2OverloadDetectEnable */
+	0x1,	/* hb2OverloadDurationCnt */
+	0x1		/* hb2OverloadThreshCnt */
+};
+
+static mykonosPowerMeasAgcCfg_t obsRxPwrAgc =
+{
+    0x01,	/* pmdUpperHighThresh */
+    0x03,	/* pmdUpperLowThresh */
+    0x0C,	/* pmdLowerHighThresh */
+    0x00,	/* pmdLowerLowThresh */
+    0x4,	/* pmdUpperHighGainStepAttack */
+    0x2,	/* pmdUpperLowGainStepAttack */
+    0x2,	/* pmdLowerHighGainStepRecovery */
+    0x4,	/* pmdLowerLowGainStepRecovery */
+    0x08,	/* pmdMeasDuration */
+    0x02	/* pmdMeasConfig */
+};
+
+static mykonosAgcCfg_t obsRxAgcConfig =
+{
+    255,	/* agcRx1MaxGainIndex */
+    195,	/* agcRx1MinGainIndex */
+    255,	/* agcRx2MaxGainIndex */
+    195,	/* agcRx2MinGainIndex: */
+    255,	/* agcObsRxMaxGainIndex */
+    203,	/* agcObsRxMinGainIndex */
+    1,		/* agcObsRxSelect */
+    1,		/* agcPeakThresholdMode */
+    1,		/* agcLowThsPreventGainIncrease */
+	30720,	/* agcGainUpdateCounter */
+    3,		/* agcSlowLoopSettlingDelay */
+    2,		/* agcPeakWaitTime */
+    1,		/* agcResetOnRxEnable */
+    0,		/* agcEnableSyncPulseForGainCounter */
+    &obsRxPeakAgc,
+    &obsRxPwrAgc
+};
+
+
+static mykonosRxProfile_t rxProfile =
+{/* Rx 100MHz, IQrate 122.88MSPS, Dec5 */
+    1,              /* The divider used to generate the ADC clock*/
+    &rxFir,         /* Pointer to Rx FIR filter structure*/
+    2,              /* Rx FIR decimation (1,2,4)*/
+    5,              /* Decimation of Dec5 or Dec4 filter (5,4)*/
+    1,              /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
+    1,              /* RX Half band 1 decimation (1 or 2)*/
+    122880,         /* Rx IQ data rate in kHz*/
+    100000000,      /* The Rx RF passband bandwidth for the profile*/
+    100000,         /* Rx BBF 3dB corner in kHz*/
+    NULL            /* pointer to custom ADC profile*/
+};
+
+static mykonosRxProfile_t orxProfile =
+{/* ORX 100MHz, IQrate 122.88MSPS, Dec5 */
+    1,              /* The divider used to generate the ADC clock*/
+    &obsrxFir,      /* Pointer to Rx FIR filter structure or NULL*/
+    2,              /* Rx FIR decimation (1,2,4)*/
+    5,              /* Decimation of Dec5 or Dec4 filter (5,4)*/
+    0,              /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
+    1,              /* RX Half band 1 decimation (1 or 2)*/
+    122880,         /* Rx IQ data rate in kHz*/
+    100000000,      /* The Rx RF passband bandwidth for the profile*/
+    100000,         /* Rx BBF 3dB corner in kHz*/
+    NULL            /* pointer to custom ADC profile*/
+};
+
+
+static mykonosRxProfile_t snifferProfile =
+{ /* SRx 20MHz, IQrate 30.72MSPS, Dec5 */
+    1,              /* The divider used to generate the ADC clock*/
+    &snifferRxFir,  /* Pointer to Rx FIR filter structure or NULL*/
+    4,              /* Rx FIR decimation (1,2,4)*/
+    5,              /* Decimation of Dec5 or Dec4 filter (5,4)*/
+    0,              /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
+    2,              /* RX Half band 1 decimation (1 or 2)*/
+    30720,          /* Rx IQ data rate in kHz*/
+    10000000,       /* The Rx RF passband bandwidth for the profile*/
+    100000,         /* Rx BBF 3dB corner in kHz*/
+    NULL            /* pointer to custom ADC profile*/
+};
+
+
+
+static mykonosTxProfile_t txProfile =
+{ /* Tx 20/100MHz, IQrate 122.88MSPS, Dec5 */
+    DACDIV_2p5,     /* The divider used to generate the DAC clock*/
+    &txFir,         /* Pointer to Tx FIR filter structure*/
+    2,              /* The Tx digital FIR filter interpolation (1,2,4)*/
+    2,              /* Tx Halfband1 filter interpolation (1,2)*/
+    1,              /* Tx Halfband2 filter interpolation (1,2)*/
+    1,              /* TxInputHbInterpolation (1,2)*/
+    122880,         /* Tx IQ data rate in kHz*/
+	100000000,      /* Primary Signal BW*/
+    100000000,      /* The Tx RF passband bandwidth for the profile*/
+    710539,         /* The DAC filter 3dB corner in kHz*/
+    50000,          /* Tx BBF 3dB corner in kHz*/
+    0               /* Enable DPD, only valid for AD9373*/
+};
+
+static mykonosDigClocks_t mykonosClocks =
+{
+    122880,         /* CLKPLL and device reference clock frequency in kHz*/
+    9830400,        /* CLKPLL VCO frequency in kHz*/
+    VCODIV_2,       /* CLKPLL VCO divider*/
+    4               /* CLKPLL high speed clock divider*/
+};
+
+static mykonosRxSettings_t  rxSettings =
+{
+    &rxProfile,     /* Rx datapath profile, 3dB corner frequencies, and digital filter enables*/
+    &rxFramer,      /* Rx JESD204b framer configuration structure*/
+    &rxGainControl, /* Rx Gain control settings structure*/
+    &rxAgcConfig,   /* Rx AGC control settings structure*/
+	RX1_RX2,        /* The desired Rx Channels to enable during initialization*/
+    0,              /* Internal LO = 0, external LO*2 = 1*/
+    2550000000U,    /* Rx PLL LO Frequency (internal or external LO)*/
+    0               /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data*/
+};
+
+static mykonosDpdConfig_t dpdConfig =
+{
+    5,              /* 1/2^(damping + 8) fraction of power `forgotten' per sample (default: `1/8192' = 5, valid 0 to 15), 0 = infinite damping*/
+    1,              /* number of weights to use for int8_cpx weights weights member of this structure (default = 1)*/
+    2,              /* DPD model version: one of four different generalized polynomial models: 0 = same as R0 silicon, 1-3 are new and the best one depends on the PA (default: 2)*/
+    1,              /* 1 = Update saved model whenever peak Tx digital RMS is within 1dB of historical peak Tx RMS*/
+    20,             /* Determines how much weight the loaded prior model has on DPD modeling (Valid 0 - 32, default 20)*/
+    0,              /* Default off = 0, 1=enables automatic outlier removal during DPD modeling */
+    512,            /* Number of samples to capture (default: 512, valid 64-32768)*/
+    4096,           /* threshold for sample in AM-AM plot outside of 1:1 line to be thrown out. (default: 50% = 8192/2, valid 8192 to 1)*/
+    0,              /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
+    255,            /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range  1 to 8191)*/
+    {{64,0},{0,0},{0,0}}/* DPD model error weighting (real/imag valid from -128 to 127)*/
+};
+
+static mykonosClgcConfig_t clgcConfig =
+{
+    -2000,          /* (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx1 output to ORx1 input in (dB * 100)*/
+    -2000,          /* (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx2 output to ORx2 input in (dB * 100)*/
+    0,              /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx1Atten is not reduced below the limit*/
+    0,              /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx2Atten is not reduced below the limit*/
+    75,             /* valid range 1-100, default 75*/
+    75,             /* valid range 1-100, default 45*/
+    0,              /* 0= allow CLGC to run, but Tx1Atten will not be updated. User can still read back power measurements.  1=CLGC runs, and Tx1Atten automatically updated*/
+    0,              /* 0= allow CLGC to run, but Tx2Atten will not be updated. User can still read back power measurements.  1=CLGC runs, and Tx2Atten automatically updated*/
+    0,              /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
+    255,            /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range  1 to 8191)*/
+    600,            /* Threshold for Tx1 in order to stop tracking, value = 100 * dB, default 6db then value = 600*/
+    600,            /* Threshold for Tx2 in order to stop tracking, value = 100 * dB, default 6db then value = 600*/
+    0,              /* Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0*/
+    0               /* Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0*/
+};
+
+static mykonosVswrConfig_t vswrConfig =
+{
+    0,              /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
+    255,            /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range  1 to 8191)*/
+    0,              /* 3p3V GPIO pin to use to control VSWR switch for Tx1 (valid 0-11) (output from Mykonos)*/
+    1,              /* 3p3V GPIO pin to use to control VSWR switch for Tx2 (valid 0-11) (output from Mykonos)*/
+    0,              /* 3p3v GPIO pin polarity for forward path of Tx1, opposite used for reflection path (1 = high level, 0 = low level)*/
+    0,              /* 3p3v GPIO pin polarity for forward path of Tx2, opposite used for reflection path (1 = high level, 0 = low level)*/
+    50,             /* Delay for Tx1 after flipping the VSWR switch until measurement is made. In us resolution*/
+    50              /* Delay for Tx2 after flipping the VSWR switch until measurement is made. In us resolution*/
+};
+
+static mykonosTxSettings_t txSettings =
+{
+    &txProfile,     /* Tx datapath profile, 3dB corner frequencies, and digital filter enables*/
+    &deframer,      /* Mykonos JESD204b deframer config for the Tx data path*/
+    TX1_TX2,        /* The desired Tx channels to enable during initialization*/
+    0,              /* Internal LO=0, external LO*2 if =1*/
+    2500000000U,    /* Tx PLL LO frequency (internal or external LO)*/
+    TXATTEN_0P05_DB,/* Initial and current Tx1 Attenuation*/
+    10000,          /* Initial and current Tx1 Attenuation mdB*/
+    10000,          /* Initial and current Tx2 Attenuation mdB*/
+    NULL,           /* DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL otherwise*/
+    NULL,           /* CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
+    NULL            /* VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
+};
+
+
+static mykonosObsRxSettings_t obsRxSettings =
+{
+    &orxProfile,    /* ORx datapath profile, 3dB corner frequencies, and digital filter enables*/
+    &orxGainControl,/* ObsRx gain control settings structure*/
+    &obsRxAgcConfig,/* ORx AGC control settings structure*/
+    &snifferProfile,/* Sniffer datapath profile, 3dB corner frequencies, and digital filter enables*/
+    &snifferGainControl,/* SnRx gain control settings structure*/
+    &obsRxFramer,   /* ObsRx JESD204b framer configuration structure */
+    (MYK_ORX1_ORX2 | MYK_SNRXA_B_C),/* obsRxChannel */
+    OBSLO_TX_PLL,   /* (obsRxLoSource) The Obs Rx mixer can use the Tx Synth(TX_PLL) or Sniffer Synth (SNIFFER_PLL) */
+    2600000000U,    /* SnRx PLL LO frequency in Hz */
+    0,              /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where if > 0 = real IF data, '0' = complex data*/
+    NULL,           /* Custom Loopback ADC profile to set the bandwidth of the ADC response */
+    OBS_RXOFF       /* Default ObsRx channel to enter when radioOn called */
+};
+
+static mykonosArmGpioConfig_t armGpio =
+{
+    1,	// useRx2EnablePin; /*!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate RX1_ENABLE/RX2_ENABLE pins */
+    1,	// useTx2EnablePin; /*!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate TX1_ENABLE/TX2_ENABLE pins */
+    1,	// txRxPinMode;     /*!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx chains */
+    0,	// orxPinMode;      /*!< 0= ARM command mode, 1 = Pin mode to power up ObsRx receiver*/
+
+    /*Mykonos ARM input GPIO pins -- Only valid if orxPinMode = 1 */
+    0,	// orxTriggerPin; /*!< Select desired GPIO pin (valid 4-15) */
+    0,	// orxMode2Pin;   /*!< Select desired GPIO pin (valid 0-18) */
+    0,	// orxMode1Pin;   /*!< Select desired GPIO pin (valid 0-18) */
+    0,	// orxMode0Pin;   /*!< Select desired GPIO pin (valid 0-18) */
+
+    /* Mykonos ARM output GPIO pins  --  always available, even when pin mode not enabled*/
+    0,	// rx1EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// rx2EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// tx1EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// tx2EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// orx1EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// orx2EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0,	// srxEnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    0 	// txObsSelect;   /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
+    /* When 2Tx are used with only 1 ORx input, this GPIO tells the BBIC which Tx channel is   */
+    /* active for calibrations, so BBIC can route correct RF Tx path into the single ORx input*/
+};
+
+static mykonosGpio3v3_t gpio3v3 =
+{
+    0,				/*!< Oe per pin, 1=output, 0 = input */
+    GPIO3V3_BITBANG_MODE,	/*!< Mode for GPIO3V3[3:0] */
+    GPIO3V3_BITBANG_MODE,	/*!< Mode for GPIO3V3[7:4] */
+    GPIO3V3_BITBANG_MODE,	/*!< Mode for GPIO3V3[11:8] */
+};
+
+static mykonosGpioLowVoltage_t gpio =
+{
+    0,/* Oe per pin, 1=output, 0 = input */
+    GPIO_MONITOR_MODE,/* Mode for GPIO[3:0] */
+    GPIO_MONITOR_MODE,/* Mode for GPIO[7:4] */
+    GPIO_MONITOR_MODE,/* Mode for GPIO[11:8] */
+    GPIO_MONITOR_MODE,/* Mode for GPIO[15:12] */
+    GPIO_MONITOR_MODE,/* Mode for GPIO[18:16] */
+};
+
+static mykonosAuxIo_t mykonosAuxIo =
+{
+    0,	//auxDacEnableMask uint16_t
+    {0,0,0,0,0,0,0,0,0,0},	 //AuxDacValue uint16[10]
+    {0,0,0,0,0,0,0,0,0,0},	 //AuxDacSlope uint8[10]
+    {0,0,0,0,0,0,0,0,0,0},	 //AuxDacVref uint8[10]
+    &gpio3v3,	//pointer to gpio3v3 struct
+    &gpio,	//pointer to gpio1v8 struct
+    &armGpio
+};
+
+static spiSettings_t mykSpiSettings =
+{
+    1, /* chip select index - valid 1~8 */
+    0, /* the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation */
+    1, /* 1 = 16-bit instruction word, 0 = 8-bit instruction word */
+    1, /* 1 = MSBFirst, 0 = LSBFirst */
+    0, /* clock phase, sets which clock edge the data updates (valid 0 or 1) */
+    0, /* clock polarity 0 = clock starts low, 1 = clock starts high */
+    0, /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
+    1, /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
+    1  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
+};
+
+static mykonosTempSensorConfig_t tempSensor =
+{
+    7,              /* 3-bit value that controls the AuxADC decimation factor when used for temp sensor calculations; AuxADC_decimation = 256 * 2^tempDecimation*/
+    67,             /* 8-bit offset that gets added to temp sensor code internally*/
+    1,              /* this bit overrides the factory-calibrated fuse offset and uses the value stored in the offset member*/
+    15,             /* 4-bit code with a resolution of 1°C/LSB, each time a temperature measurement is performed, the device compares the current temperature against the previous value.*/
+};
+
+static mykonosTempSensorStatus_t tempStatus =
+{
+    0,              /* 16-bit signed temperature value (in deg C) that is read back*/
+    0,              /* If the absolute value of the difference is greater than the value in temperature configuration tempWindow, the windowExceeded flag is set.*/
+    0,              /* when windowExceeded member gets set, this bit is set to 1 if current value is greater than previous value, else reset*/
+    0,              /* when the reading is complete and a valid temperature value stored in tempCode.*/
+};
+
+mykonosDevice_t mykDevice =
+{
+    &mykSpiSettings,    /* SPI settings data structure pointer */
+    &rxSettings,        /* Rx settings data structure pointer */
+    &txSettings,        /* Tx settings data structure pointer */
+    &obsRxSettings,     /* ObsRx settings data structure pointer */
+    &mykonosAuxIo,          /* Auxiliary IO settings data structure pointer */
+    &mykonosClocks,     /* Holds settings for CLKPLL and reference clock */
+    0                   /* Mykonos initialize function uses this as an output to remember which profile data structure pointers are valid */
+};

df_datalink_ge/src/hardware/myk_init.h

@@ -0,0 +1,24 @@
+/**
+ * \file myk_init.h
+ *
+ * \brief Contains structure definitions for myk_init.c
+ *
+ * The top level structure mykonosDevice_t mykDevice uses keyword
+ * extern to allow the application layer main() to have visibility
+ * to these settings.
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef MYK_INIT_H_
+#define MYK_INIT_H_
+
+
+extern mykonosDevice_t mykDevice;
+
+#endif

df_datalink_ge/src/hardware/mykonos/Mykonos_M3.h

@@ -0,0 +1,13 @@
+/**
+SOFTWARE LICENSE AGREEMENT
+20180301-AD937X-CTSLA
+**/
+
+// Version 5.2.2
+#ifndef SRC_MYKONOS_BIN_H_
+#define SRC_MYKONOS_BIN_H_
+
+unsigned char firmware_Mykonos_M3_bin[];
+unsigned int firmware_Mykonos_M3_bin_len;
+
+#endif

df_datalink_ge/src/hardware/mykonos/ad9528.c

@@ -0,0 +1,740 @@
+/**
+ * \file ad9528.c
+ * \brief Contains source code for configuring and initializing AD9528 clock device
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#include "ad9528.h"
+
+/**
+ * \brief Performs a hard reset on the AD9528 DUT
+ *
+ * <B>Dependencies</B>
+ * - device->spiSettings->chipSelectIndex
+ *
+ * \param device is structure pointer to the AD9528 data structure containing settings
+ * \return Returns enum ADI_ERR, ADIERR_OK=pass, !ADIERR_OK=fail
+ */
+ADI_ERR AD9528_resetDevice(ad9528Device_t *device)
+{
+    /* toggle RESETB on device with matching spi chip select index */
+    CMB_hardReset(device->spiSettings->chipSelectIndex);
+    return ADIERR_OK;
+}
+
+/**
+ * \brief Sets the AD9528 device SPI settings (3wire/4wire, MSBFirst, etc).
+ *
+ * This function will use the settings in the device->spiSettings structure
+ * to set SPI stream mode, address auto increment direction, MSBFirst/LSBfirst,
+ * and 3wire/4wire mode.  The AD9528 device always uses SPI MODE 0 (CPHA=0, CPOL=0).
+ * This function will update your device->spiSettings to set CHPA=0 and CPOL=0 and
+ * longInstructionWord =1 to use a 16bit instruction word.
+ *
+ * <B>Dependencies</B>
+ * - writes device->spiSettings->CPHA = 0
+ * - writes device->spiSettings->CPOL = 0
+ * - writes device->spiSettings->longInstructionWord = 1
+ *
+ * - device->spiSettings->MSBFirst
+ * - device->spiSettings->enSpiStreaming
+ * - device->spiSettings->autoIncAddrUp
+ * - device->spiSettings->fourWireMode
+ *
+ * \param device is structure pointer to the AD9528 data structure containing settings
+ *
+ * \return Returns enum ADI_ERR, ADIERR_OK=pass, !ADIERR_OK=fail
+ */
+ADI_ERR AD9528_setSpiSettings(ad9528Device_t *device)
+{
+    //device->spiSettings->enSpiStreaming
+    uint8_t spiReg = 0;
+
+    device->spiSettings->CPHA = 0;
+    device->spiSettings->CPOL = 0;
+    device->spiSettings->longInstructionWord = 1;
+
+    if (device->spiSettings->MSBFirst == 0)
+    {
+        spiReg |= 0x42; /* SPI bit is 1=LSB first */
+    }
+
+    if (device->spiSettings->autoIncAddrUp > 0)
+    {
+        spiReg |= 0x24;
+    }
+
+    if (device->spiSettings->fourWireMode > 0)
+    {
+        spiReg |= 0x18;
+    }
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_A, spiReg);
+
+    if (device->spiSettings->enSpiStreaming > 0)
+    {
+        /* Allow SPI streaming mode: SPI message ends when chip select deasserts */
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x00);
+    }
+    else
+    {
+        /* Force single instruction mode */
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x80);
+    }
+
+    return ADIERR_OK;
+}
+
+
+/**
+ * \brief Helper function for ADI transceiver eval boards to init the AD9528 data structure
+ *
+ * This function inits the AD9528 device data structure with defaults that
+ * are known to work with the ADI AD9369 and AD9371 evaluation boards.  NOTE: This function will
+ * modify the contents of the AD9528 device data structure.
+ *
+ * <B>Dependencies</B>
+ * - spi->chipSelectIndex
+ * - spi
+ *
+ * \param device Pointer to the AD9528 device data structure to initialize
+ * \param vcxoFrequency_Hz The VCXO frequency that is connected to the AD9528
+ * \param refAFrequency_Hz The reference clock frequency being input into the AD9528 REFCLK A input
+ * \param outputDeviceClock_Hz Desired output clock frequency to the FPGA and transceiver device
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+*/
+ADI_ERR AD9528_initDeviceDataStruct(ad9528Device_t *device, uint32_t vcxoFrequency_Hz, uint32_t refAFrequency_Hz, uint32_t outputDeviceClock_Hz)
+{
+//    uint16_t chDiv;
+//    uint8_t i = 0;
+//
+//    uint32_t pll1PfdFreq_Hz = 0;
+//    uint8_t pll1Ndiv = 0;
+//    uint8_t validPll1DivSetting = 0;
+//    uint8_t refAdiv = 1;
+//
+//
+//    uint8_t pll2RfDiv = 3; /* Valid values 3,4,5 */
+//    uint16_t pll2Ndiv = 1; /* Valid values 1-256 */
+//    uint32_t pll2InputFreq_Hz = 0;
+//    uint64_t pll2VcoFreq_Hz = 0;
+//    uint16_t pll2NdivStart = 0;
+//    uint8_t validPll2DivSetting = 0;
+//    uint64_t chDivU64 = 0;
+//
+//    static const uint64_t PLL2_MIN_VCO_FREQ_HZ = 3450000000ULL;
+//    static const uint64_t PLL2_MAX_VCO_FREQ_HZ = 4025000000ULL;
+//    /*******************************************************************
+//     * PLL1 Settings
+//     *******************************************************************
+//     */
+//
+//    /* find valid PLL1 Ndiv and REFA div */
+//    for (pll1Ndiv = 1; pll1Ndiv < 20; pll1Ndiv++)
+//    {
+//        pll1PfdFreq_Hz = vcxoFrequency_Hz / pll1Ndiv;
+//
+//        if ((pll1PfdFreq_Hz <= 110000000) && (pll1PfdFreq_Hz >= 1000000) &&
+//            (pll1PfdFreq_Hz <= refAFrequency_Hz) &&
+//            (refAFrequency_Hz % pll1PfdFreq_Hz == 0)
+//           )
+//        {
+//            validPll1DivSetting = 1;
+//            refAdiv = refAFrequency_Hz / pll1PfdFreq_Hz ;
+//            break;
+//        }
+//    }
+//
+//    if (validPll1DivSetting == 0)
+//    {
+//        return ADIERR_INV_PARM;
+//    }
+//
+//    device->pll1Settings->nDivider = pll1Ndiv; //This init function always runs PLL1 at 30.72MHz Pfd rate
+//    device->pll1Settings->refA_bufferCtrl = DIFFERENTIAL;       //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
+//    device->pll1Settings->refA_Divider = refAdiv;
+//    device->pll1Settings->refA_Frequency_Hz = refAFrequency_Hz;
+//    device->pll1Settings->refB_bufferCtrl = DISABLED;           //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
+//    device->pll1Settings->refB_Divider = 1;
+//    device->pll1Settings->refB_Frequency_Hz = 0;
+//    device->pll1Settings->vcxoBufferCtrl  = NEG_SINGLE_ENDED;   //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
+//    device->pll1Settings->vcxo_Frequency_Hz = vcxoFrequency_Hz;
+//
+//    /*******************************************************************
+//     * PLL2 Settings
+//     *******************************************************************
+//     */
+//
+//    /*******************************************************************
+//     * Output Distribution Settings
+//     * 9369CE02A uses the following clock outputs
+//     * OUT 1: FPGA REFCLK
+//     * OUT 3: FPGA SYSREF
+//     * OUT 12: DUT SYSREF
+//     * OUT 13: DUT REFCLK
+//     *******************************************************************
+//     */
+//
+//    /* PLL 2 input clock can be several different things.  Currently hard coded by this init funciton to use
+//     * PLL 1 output (VCXO Frequency) with no scaling
+//     */
+//    pll2InputFreq_Hz = device->pll1Settings->vcxo_Frequency_Hz;
+//    validPll2DivSetting = 0;
+//
+//    /* Sweep PLL2 Divider settings to find something that has a valid integer divide (3,4,5)*/
+//    for (pll2RfDiv = 3; pll2RfDiv <= 5; pll2RfDiv++)
+//    {
+//
+//        pll2NdivStart = (PLL2_MIN_VCO_FREQ_HZ / pll2RfDiv / pll2InputFreq_Hz);
+//        /* find valid PLL2 Ndiv (1-256) */
+//        for (pll2Ndiv = pll2NdivStart; pll2Ndiv <= 256; pll2Ndiv++)
+//        {
+//            pll2VcoFreq_Hz = (pll2InputFreq_Hz * pll2RfDiv * pll2Ndiv);
+//
+//            if (pll2VcoFreq_Hz < PLL2_MIN_VCO_FREQ_HZ)
+//            {
+//                /* Continue to next PLL2 N div */
+//                continue;
+//            }
+//            else if (pll2VcoFreq_Hz > PLL2_MAX_VCO_FREQ_HZ)
+//            {
+//                /* Break to next PLL2 RF div */
+//                break;
+//            }
+//
+//            if (((pll2VcoFreq_Hz / pll2RfDiv) % outputDeviceClock_Hz) == 0)
+//            {
+//
+//                device->pll2Settings->rfDivider = pll2RfDiv;
+//                device->pll2Settings->n2Divider = pll2Ndiv;
+//                device->pll2Settings->totalNdiv = pll2RfDiv * pll2Ndiv;
+//                chDivU64 = ((pll2VcoFreq_Hz / pll2RfDiv) / outputDeviceClock_Hz);
+//
+//                if ((chDivU64 < 1) || (chDivU64 > 256))
+//                {
+//                    return ADIERR_INV_PARM;
+//                }
+//                else
+//                {
+//                    chDiv = (uint16_t)(chDivU64);
+//                }
+//
+//                validPll2DivSetting = 1;
+//                break;
+//            }
+//        }
+//
+//        if (validPll2DivSetting == 1)
+//        {
+//            break;
+//        }
+//    }
+//
+//    if (validPll2DivSetting == 0)
+//    {
+//        return ADIERR_INV_PARM;
+//    }
+//
+//    device->outputSettings->outPowerDown = (uint16_t)(~0x300A);     //enable outputs 13,12,3 and 1
+//
+//    for (i=0; i<14; i++){
+//        device->outputSettings->outSource[i] = CHANNEL_DIV; //CHANNEL_DIV , PLL1_OUTPUT, SYSREF, INV_PLL1_OUTPUT
+//        device->outputSettings->outBufferCtrl[i] = LVDS;        //LVDS, LVDS_BOOST, HSTL
+//        device->outputSettings->outChannelDiv[i] = chDiv;
+//        device->outputSettings->outFrequency_Hz[i] = outputDeviceClock_Hz;
+//        device->outputSettings->outAnalogDelay[i] = 0;
+//        device->outputSettings->outDigitalDelay[i] = 0;
+//    }
+//
+//
+//    device->outputSettings->outSource[3] = SYSREF;
+//    device->outputSettings->outSource[12] = SYSREF;
+//
+//
+//    device->sysrefSettings->sysrefDivide = 512; //SYSREF frequency = VCXO / 2 / sysrefDivde
+//    device->sysrefSettings->sysrefNshotMode = ONE_PULSE;        //ONE_PULSE=0, TWO_PULSES=2, FOUR_PULSES=3, SIX_PULSES=4, EIGHT_PULSES=5
+//    device->sysrefSettings->sysrefPatternMode = NSHOT;          //NSHOT=0, CONTINUOUS=1, PRBS=2, STOP=3
+//    device->sysrefSettings->sysrefPinBufferMode = DISABLED;     //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
+//    device->sysrefSettings->sysrefPinEdgeMode = LEVEL_ACTIVE_HIGH;  //LEVEL_ACTIVE_HIGH=0, LEVEL_ACTIVE_LOW=1, RISING_EDGE=2, FALLING_EDGE=3
+//    device->sysrefSettings->sysrefRequestMethod = SPI;          //SPI=0,PIN=1
+//    device->sysrefSettings->sysrefSource = INTERNAL;            //EXTERNAL=0, EXT_RESAMPLED=1, INTERNAL=2
+    return ADIERR_OK;
+}
+
+/**
+ * \brief Debug function to print out summary of AD9528 setup
+ *
+ * \param device AD9528 Device data structure describing setup of device.
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+***********************************************************************************/
+ADI_ERR AD9528_reportClockRates(ad9528Device_t *device)
+{
+
+    return ADIERR_OK;
+} //debug function to help verify data structure is setup correctly.
+
+/**
+ * \brief Initializes the AD9528 by writing all SPI registers
+ *
+ * Initializes the AD9528 for use with the AD9369 transceiver.  Designed to work with
+ * a reference clock of 122.88MHz.  Reference clock is expected to be 30.72MHz.
+ * The output clocks from the AD9528 can run at 122.88M, 153.6M, 184.32M, 245.76M, or 307.2M.
+ * Typical setup: REFA frequency = 30.72, VCXO = 122.88MHz
+ * SYNC(SYSREF) pulses output at rate of 120kHz
+ *
+ * <B>Dependencies</B>
+ * - All parameters in device structure
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ */
+ADI_ERR AD9528_initialize(ad9528Device_t *device) { //writes all registers to desired values, leaves clock outputs off, SYSREF output disabled.
+    uint8_t pll2_Adiv=0;
+    uint8_t pll2_Bdiv=0;
+    uint8_t reg108=0;
+    uint8_t reg109=0;
+    uint8_t i = 0;
+    uint8_t j = 0;
+    uint8_t reg508;
+    ADI_ERR retval = ADIERR_OK;
+
+    CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, ADIERR_OK, "\n// AD9528_initialize\n");
+
+    //CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_A, 0x18); //[4] and [3] =1 enable 4 wire SPI
+    //CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x00);
+    retval = AD9528_setSpiSettings(device);
+    if (retval != ADIERR_OK)
+    {
+        return retval;
+    }
+
+    /**********************************************************************
+     * Configure PLL1
+     **********************************************************************
+     */
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_A_DIVIDER_LSB,
+    		device->pll1Settings->refA_Divider & 0xFF);		//REF A div[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_A_DIVIDER_MSB,
+    		(device->pll1Settings->refA_Divider >> 8) & 0x03); //REF A div[9:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_B_DIVIDER_LSB,
+    		device->pll1Settings->refB_Divider & 0xFF);		//REF B div[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_B_DIVIDER_MSB,
+    		(device->pll1Settings->refB_Divider >> 8) & 0x03); //REF B div[9:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_N_DIV_LSB,
+    		device->pll1Settings->nDivider & 0xFF); //PLL1 N div[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_N_DIV_MSB,
+    		(device->pll1Settings->nDivider >> 8) & 0x03); //PLL1 N div[9:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_CHARGEPUMP,
+    		0x0A); //PLL1 Charge Pump control 1
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_CP_CTRL2,
+    		0x03); //PLL1 Charge Pump control 2
+
+    switch (device->pll1Settings->refA_bufferCtrl){
+        case DISABLED:
+        	reg108 &= ~0x28;
+        	reg109 &= ~0x01;
+        	break; //clear all REFA enable bits
+        case SINGLE_ENDED:
+        	reg108 |=  0x08;
+        	reg109 &= ~0x01;
+        	break; //Set REFA receiver enable, clear REFA SE negative input enable
+        case NEG_SINGLE_ENDED:
+        	reg108 |=  0x08;
+        	reg108 &= ~0x10;
+        	reg109 |= 0x01;
+        	break; //Disable REFA diff receiver, enable REFA receiver and use negative REFA input
+        case DIFFERENTIAL:
+        	reg108 |=  0x28;
+        	reg109 &= ~0x01;
+        	break;
+        default:
+        	reg108 |=  0x08;
+        	reg109 &= ~0x01;
+        	break; //default to single ended case
+    }
+    switch (device->pll1Settings->refB_bufferCtrl){
+        case DISABLED:
+        	reg108 &= ~0x50;
+        	reg109 &= ~0x02;
+        	break; //clear all REFB enable bits
+        case SINGLE_ENDED:
+        	reg108 |=  0x10;
+        	reg109 &= ~0x02;
+        	break; //Set REFB receiver enable, clear REFB SE negative input enable
+        case NEG_SINGLE_ENDED:
+        	reg108 |=  0x10;
+        	reg108 &= ~0x40;
+        	reg109 |= 0x02;
+        	break; //Disable REFB diff receiver, enable REFB receiver and use negative REFB input
+        case DIFFERENTIAL:
+        	reg108 |=  0x50;
+        	reg109 &= ~0x02;
+        	break;
+        default:
+        	reg108 |=  0x10;
+        	reg109 &= ~0x02;
+        	break; //default to single ended case
+    }
+    switch (device->pll1Settings->vcxoBufferCtrl){
+        case DISABLED:
+        	reg108 &= ~0x03;
+        	reg108 |=  0x04;
+        	break; //power down VCXO input
+        case SINGLE_ENDED:
+        	reg108 &= ~0x07;
+        	break; //Clear VCXO receiver power down, defaults to Single ended mode
+        case NEG_SINGLE_ENDED:
+        	reg108 &= ~0x07;
+        	reg108 |=  0x02;
+        	break; //Clear VCXO power down, enable Negative single ended mode[1]
+        case DIFFERENTIAL:
+        	reg108 &= ~0x07;
+        	reg108 |=  0x01;
+        	break; //Clear VCXO power down, enable differential input buffer[0]
+        default:
+        	reg108 &= ~0x07;
+        	break; //default to positive single ended case
+    }
+
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS1,
+    		reg108); //Input receiver settings (single ended or differential clock inputs)
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS2,
+    		reg109); //Input receiver settings
+
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS3,
+    		0x0A); //Reference selection mode
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_FASTLOCK,
+    		0x00); //Disable Fast lock
+
+    /**********************************************************************
+     * Configure PLL2
+     **********************************************************************
+     */
+    pll2_Bdiv = device->pll2Settings->totalNdiv / 4;
+    pll2_Adiv = device->pll2Settings->totalNdiv % 4;
+
+    if (pll2_Adiv > 3) {  //A div valid range (0 to 3)
+        CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 A Divider out of range (0 to 3)\n");
+        return ADIERR_INV_PARM;
+    }
+    if (pll2_Bdiv < 3 || pll2_Bdiv > 63) {
+        CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 B Divider out of range (3 to 63)\n");
+        return ADIERR_INV_PARM;
+    }
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_CHARGEPUMP,
+    		0xE6); //PLL2 Charge Pump[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_N_DIV,
+    		((pll2_Adiv & 0x3) << 6) | (pll2_Bdiv & 0x3F)); //PLL2 A and B divider
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_CTRL, 0x03); //PLL2 control
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_VCO_CTRL, 0x01); //Manual VCO CAL
+
+    if (device->pll2Settings->rfDivider < 3 || device->pll2Settings->rfDivider > 5) {
+        CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 RF Divider out of range (3,4, or 5)\n");
+        return ADIERR_INV_PARM;
+    }
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_VCO_DIV,
+    		device->pll2Settings->rfDivider); //VCO divider
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_LF_CTRL1,
+    		0x3A); //PLL2 Loop filter [7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_LF_CTRL2,
+    		0x00); //PLL2 Loop filter [8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_RDIV,
+    		0x00); //R divider
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_REPLICA_CHDIV,
+    		(device->pll2Settings->totalNdiv / device->pll2Settings->rfDivider)
+			-1 ); //Replica channel divider: Ndivider = rfDivider * R divider
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_REPLICA_DIV_PHASE,
+    		0x00); //Replica Channel Divider phase
+
+    /**********************************************************************
+     * Configure Output Distribution
+     **********************************************************************
+     */
+    for (i=0; i<14; i=i+1){
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CTRL1 + j,
+        		((device->outputSettings->outSource[i] & 0x7) << 5) |
+				(device->outputSettings->outAnalogDelay[i] & 0x1F));
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CTRL2 + j,
+        		((device->outputSettings->outBufferCtrl[i] & 0x3) << 6) |
+				(device->outputSettings->outDigitalDelay[i] & 0x3F));
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CHDIV + j,
+        		device->outputSettings->outChannelDiv[i]-1);
+        j = j+3;
+    }
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_OUTPUT_SYNC, 0x00); //Sync outputs
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_MASK_SYNC1, 0x00); //Mask SYNC[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_MASK_SYNC2, 0x00); //Mask SYNC[13:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_EN_OUTPUT_PATH_SEL1,
+    		0x00); //Bypass SYSREF resample [6:0], bit0:Enable VCXO to feed output distrubution
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_EN_OUTPUT_PATH_SEL2,
+    		0x00); //Bypass SYSREF resample [13:7]
+
+    /**********************************************************************
+     * Configure SYSREF operation
+     **********************************************************************
+     */
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSERF_DIV_LSB,
+    		device->sysrefSettings->sysrefDivide & 0xFF); //SYSREF divider [7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSERF_DIV_MSB,
+    		(device->sysrefSettings->sysrefDivide >> 8) & 0xFF); //SYSREF divider [7:0]
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL3,
+    		((device->sysrefSettings->sysrefRequestMethod & 0x1) << 7) |
+    		((device->sysrefSettings->sysrefPinEdgeMode & 0x3) << 5) );
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4,
+    		((device->sysrefSettings->sysrefSource & 0x03) << 6) |
+    		((device->sysrefSettings->sysrefPatternMode & 0x3) << 4 ) |
+    		((device->sysrefSettings->sysrefNshotMode & 0x7) << 1) );
+
+    if(device->sysrefSettings->sysrefPinBufferMode == DISABLED)
+    {
+    	CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
+    			0x04); //power down input buffer for external SYSREF
+    }
+    else if(device->sysrefSettings->sysrefPinBufferMode == SINGLE_ENDED)
+    {
+    	CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
+    			0x00); //enable positive singled ended input
+    }
+    else if(device->sysrefSettings->sysrefPinBufferMode == NEG_SINGLE_ENDED)
+    {
+    	CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
+    			0x02); //enable negative singled ended input
+    }
+    else if(device->sysrefSettings->sysrefPinBufferMode == DIFFERENTIAL)
+    {
+    	CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
+    			0x01); //enable differential input buffer
+    }
+    else
+    {
+    	CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
+    			0x04); //power down input buffer for external SYSREF
+    }
+
+    /**********************************************************************
+     * Power down control
+     **********************************************************************
+     */
+
+    if (device->pll1Settings->bypassPll1 > 0)
+    {
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_POWERDOWN_CTRL,
+        		0x14);// power up PLL2 and output distribution, power down PLL1
+    }
+    else
+    {
+        CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_POWERDOWN_CTRL,
+        		0x10);// power up PLL1, PLL2 and output distribution
+    }
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN1,
+    		device->outputSettings->outPowerDown & 0xFF); //power down out[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN2,
+    		((device->outputSettings->outPowerDown >> 8) & 0x3F)); //power down out[13:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_LDO_ENABLES1,
+    		0xFF); //LDO enable per output channel [7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_LDO_ENABLES2,
+    		0xFF); //LDO enable per output channel [15:8]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS0_CTRL,
+    		0x07); //STATUS 0 outputs REFA present
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS1_CTRL,
+    		0x01); //STATUS 1 outputs PLL1 and PLL2 locked
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS_OE,
+    		0x0C);// Make Status0 and Status1 outputs after reset.
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE,
+    		0x01); //IO update to make all these settings valid in the 9528
+
+    CMB_setTimeout_ms(1000);
+     do{
+         CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
+         if(CMB_hasTimeoutExpired() > 0)
+         {
+             return ADIERR_FAILED;
+         }
+     }while((reg508 & 0xA2) != 0xA2);
+
+    return ADIERR_OK;
+}
+
+/// Send a SPI message to request a SYSREF pulse or continuous SYSREF from the AD9528.
+/*******************************************************************************//**
+ * Requests a SYSREF from the AD9528.  It will use whatever settings for SYSREF
+ * that are current configured in the AD9528.  This could be a single pulse,
+ * multiple pulses, or continuous pulses.
+ * <B>Dependencies</B>
+ * - device->spiSettings
+ * - device->sysrefSettings->sysrefPatternMode
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ * \param enableSYSREF If NSHOT SYSREF mode, this parameter is ignored.  If PRBS/CONTINUOUS SYSREF mode, 1= enable SYSREF, 0= disable SYSREF.
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ ***********************************************************************************/
+ADI_ERR AD9528_requestSysref(ad9528Device_t *device, uint8_t enableSYSREF){
+    uint8_t _enableSYSREF=0;
+
+    if (device->sysrefSettings->sysrefPatternMode == NSHOT || enableSYSREF > 0)
+    {
+        _enableSYSREF = 1;
+    }
+    else
+    {
+        _enableSYSREF = 0;
+    }
+
+    CMB_SPIWriteField(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, _enableSYSREF, 0x01, 0x00); //Set SPI SYSREF request bit
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528
+
+    return ADIERR_OK;
+}
+
+/// Allow changing the 9528 SYSREF frequency and pattern mode(CONTINUOUS, PRBS vs NSHOT mode)
+/*******************************************************************************//**
+ * NOTE: this function will update the device structure with the parameter values passed
+ * into this function. The device->sysrefSettings->sysrefPatternMode, device->sysrefSettings->sysrefNshotMode,
+ * and device->sysrefSettings->sysrefDivide values will be updated in the device structure.
+ *
+ * <B>Dependencies</B>
+ * - device->spiSettings
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ * \param divideFromPll1Out Sets the SYSREF pulse frequency. SYSREF frequency = PLL1_VCXO frequency/divideFromPll1Out
+ * \param sysrefPatternMode Valid settings: NSHOT, CONTINUOUS, PRBS, STOP
+ * \param nShotPulses Valid settings: ONE_PULSE=0, TWO_PULSES=2, FOUR_PULSES=3, SIX_PULSES=4, EIGHT_PULSES=5
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ ***********************************************************************************/
+ADI_ERR AD9528_setupSYSREF(ad9528Device_t *device, uint16_t divideFromPll1Out,  sysrefPatternMode_t sysrefPatternMode, sysrefNshotMode_t nShotPulses)
+{
+    uint8_t reg403=0;
+
+    device->sysrefSettings->sysrefPatternMode = sysrefPatternMode;
+    device->sysrefSettings->sysrefNshotMode = nShotPulses;
+    device->sysrefSettings->sysrefDivide = divideFromPll1Out >> 1;  //SYSREF frequency is (PLL1)VCXO frequency / 2 / device->sysrefSettings->sysrefDivide
+
+    CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, &reg403);
+
+    reg403 = reg403 & ~0x01; //clear bit 0 to stop a continuous sysref if it is on.
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, reg403);
+
+    reg403 = reg403 & ~0x3E; //clear bits for pattern mode and Nshot mode bitfields
+    reg403 = reg403 | ((sysrefPatternMode & 0x3) << 4) | ((nShotPulses & 0x7) << 1);
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, reg403); //update internal sysref pattern mode and Nshot mode (number of pulses)
+
+    //SYSREF request bit x403[0] is left 0.  The next call to AD9528_requestSysref will start the SYSREF
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528
+
+
+    return ADIERR_OK;
+}
+
+/// Update the AD9528 clock outputs that are enabled.
+/*******************************************************************************//**
+ * NOTE: this function will update the device structure with the parameter values passed
+ * into this function. The device->sysrefSettings->sysrefPatternMode, device->sysrefSettings->sysrefNshotMode,
+ * and device->sysrefSettings->sysrefDivide values will be updated in the device structure.
+ *
+ * <B>Dependencies</B>
+ * - device->spiSettings
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ * \param clkEnable Sets which clock outputs are enabled. Bit per clock output. bit0 = out0, etc.
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ ***********************************************************************************/
+ADI_ERR AD9528_enableClockOutputs(ad9528Device_t *device, uint16_t clkEnable)
+{ //clkEnable: bit per clock output
+
+    device->outputSettings->outPowerDown = ~clkEnable;
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN1, device->outputSettings->outPowerDown & 0xFF); //power down out[7:0]
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN2, ((device->outputSettings->outPowerDown >> 8) & 0x3F)); //power down out[13:8]
+
+    CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528
+    return ADIERR_OK;
+}
+
+/// Waits for PLL1 and PLL2 to lock and the REFA and VCXO clocks to be present
+/*******************************************************************************//**
+ * Waits until Reference A clock and VCXO clock input to be detected (present),
+ * and PLL1 and PLL2 to lock.  Will timeout after 1 second and return ADIERR_FAILED.
+ * If clock are detected and PLLs locked, returns ADIERR_OK.
+ *
+ * <B>Dependencies</B>
+ * - device->spiSettings
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ ***********************************************************************************/
+ADI_ERR AD9528_waitForPllLock(ad9528Device_t *device)
+{
+    uint8_t reg508;
+
+    CMB_setTimeout_ms(1000);
+    do{
+        CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
+        if(CMB_hasTimeoutExpired() > 0)
+        {
+            return ADIERR_FAILED;
+        }
+    }while((reg508 & 0x27) != 0x27);
+
+    return ADIERR_OK;
+}
+
+/// Reads the Lock Status of the PLLs and present detect of the reference clocks
+/*******************************************************************************//**
+ * NOTE: This is a non blocking function that reads a register to see if PLL1
+ * and PLL2 are locked and Reference clock A and the VCXO input clock are
+ * detected (present). If the *status parameter is not NULL, the status will
+ * be returned.  If *status is NULL, the error return value will denote if
+ * the PllStatus is locked or not with ADIERR_OK or ADIERR_FAILED.
+ *
+ * <B>Dependencies</B>
+ * - device->spiSettings
+ *
+ * \param device is structure pointer to AD9528 clock device structure
+ *
+ * \return Returns enum ADI_ERR, 0=pass, >0 = fail
+ ***********************************************************************************/
+ADI_ERR AD9528_readPllStatus(ad9528Device_t *device, uint8_t *status)
+{
+    uint8_t reg508;
+
+    //bit5 is VCXO clock detected
+    //bit2 is REFCLK A detected
+    //bit1 is PLL2 lock detect
+    //bit0 is PLL1 lock detect
+
+    /* read twice to refresh status bits */
+    CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
+    CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
+    /* if status is a valid pointer, return the PLL status */
+    if (status > 0)
+    {
+        *status = reg508;
+    }
+
+    /* PLLs 1 and 2 are locked and VCXO and REFA detected if reg508 has bits 5,2,1 and 0 set */
+    if((reg508 & 0x27) == 0x27)
+        return ADIERR_OK;
+    else
+        return ADIERR_FAILED;
+}

df_datalink_ge/src/hardware/mykonos/ad9528.h

@@ -0,0 +1,44 @@
+/**
+ * \file ad9528.h
+ * \brief Contains function declarations and ad9528Device_t structure typedef for ad9528.c
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef _AD9528_LIB_H_
+#define _AD9528_LIB_H_
+
+#include <stdint.h>
+#include "../common.h"
+#include "t_ad9528.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CLEMENTE_TDD_AD9528_CLKOUT_INDEX 13
+
+//Helper function to setup the 9528 device data structure specifically for the ADI transceiver evaluation cards
+ADI_ERR AD9528_initDeviceDataStruct(ad9528Device_t *device, uint32_t vcxoFrequency_Hz, uint32_t refAFrequency_Hz, uint32_t outputDeviceClock_Hz);
+ADI_ERR AD9528_reportClockRates(ad9528Device_t *device); //debug function to help verify data structure is setup correctly.
+
+//AD9528 API functions
+ADI_ERR AD9528_resetDevice(ad9528Device_t *device);
+ADI_ERR AD9528_setSpiSettings(ad9528Device_t *device);
+ADI_ERR AD9528_initialize(ad9528Device_t *device); //writes all registers to desired values, leaves clock outputs off.
+ADI_ERR AD9528_waitForPllLock(ad9528Device_t *device);
+ADI_ERR AD9528_readPllStatus(ad9528Device_t *device, uint8_t *status);
+ADI_ERR AD9528_enableClockOutputs(ad9528Device_t *device, uint16_t clkEnable); //clkEnable: bit per clock output
+ADI_ERR AD9528_setupSYSREF(ad9528Device_t *device, uint16_t divideFromPll1Out,  sysrefPatternMode_t sysrefPatternMode, sysrefNshotMode_t nShotPulses);
+ADI_ERR AD9528_requestSysref(ad9528Device_t *device, uint8_t enableSYSREF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

df_datalink_ge/src/hardware/mykonos/mykonos.h

@@ -0,0 +1,277 @@
+/*!
+ * \file mykonos.h
+ * \brief Contains macro definitions and function prototypes for mykonos.c
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef _MYKONOS_LIB_H_
+#define _MYKONOS_LIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "t_mykonos.h"
+#include "mykonos_version.h"
+
+#define TX_PROFILE_VALID    0x01
+#define RX_PROFILE_VALID    0x02
+#define ORX_PROFILE_VALID   0x04
+#define SNIFF_PROFILE_VALID 0x08
+
+/* 
+ ****************************************************************************
+ * General Initialization functions 
+ ****************************************************************************
+ */
+mykonosErr_t MYKONOS_resetDevice(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getDeviceRev(mykonosDevice_t *device, uint8_t *revision);
+mykonosErr_t MYKONOS_getProductId(mykonosDevice_t *device, uint8_t *productId);
+mykonosErr_t MYKONOS_setSpiSettings(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_verifyDeviceDataStructure(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_verifyProfiles(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_initialize(mykonosDevice_t *device); 
+mykonosErr_t MYKONOS_waitForEvent(mykonosDevice_t *device, waitEvent_t waitEvent, uint32_t timeout_us);
+mykonosErr_t MYKONOS_readEventStatus(mykonosDevice_t *device, waitEvent_t waitEvent, uint8_t *eventDone);
+mykonosErr_t MYKONOS_getApiVersion (mykonosDevice_t *device, uint32_t *siVer, uint32_t *majorVer, uint32_t *minorVer, uint32_t *buildVer);
+
+/*
+ *****************************************************************************
+ * PLL / Synthesizer functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_initDigitalClocks(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setRfPllFrequency(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint64_t rfPllLoFrequency_Hz);
+mykonosErr_t MYKONOS_getRfPllFrequency(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint64_t *rfPllLoFrequency_Hz);
+mykonosErr_t MYKONOS_checkPllsLockStatus(mykonosDevice_t *device, uint8_t *pllLockStatus);
+mykonosErr_t MYKONOS_setRfPllLoopFilter(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint16_t loopBandwidth_kHz, uint8_t stability);
+mykonosErr_t MYKONOS_getRfPllLoopFilter(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint16_t *loopBandwidth_kHz, uint8_t *stability);
+/*
+ *****************************************************************************
+ * ARM Processor Control Functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_initArm(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_loadArmFromBinary(mykonosDevice_t *device, uint8_t *binary, uint32_t count);
+mykonosErr_t MYKONOS_loadArmConcurrent(mykonosDevice_t *device, uint8_t *binary, uint32_t count);
+mykonosErr_t MYKONOS_verifyArmChecksum(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_checkArmState(mykonosDevice_t *device, mykonosArmState_t armStateCheck);
+mykonosErr_t MYKONOS_getArmVersion(mykonosDevice_t *device, uint8_t *majorVer, uint8_t *minorVer, uint8_t *rcVer, mykonosBuild_t *buildType);
+
+mykonosErr_t MYKONOS_configDpd(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getDpdConfig(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getDpdStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdStatus_t *dpdStatus);
+mykonosErr_t MYKONOS_restoreDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes);
+mykonosErr_t MYKONOS_saveDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes);
+mykonosErr_t MYKONOS_setDpdActState(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t actState);
+mykonosErr_t MYKONOS_resetDpd(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdResetMode_t reset);
+mykonosErr_t MYKONOS_setDpdBypassConfig(mykonosDevice_t *device, mykonosDpdBypassConfig_t *actConfig);
+mykonosErr_t MYKONOS_getDpdBypassConfig(mykonosDevice_t *device, mykonosDpdBypassConfig_t *actConfig);
+mykonosErr_t MYKONOS_setDpdActuatorCheck(mykonosDevice_t *device, mykonosDpdActuatorCheck_t *actCheck);
+mykonosErr_t MYKONOS_getDpdActuatorCheck(mykonosDevice_t *device, mykonosDpdActuatorCheck_t *actCheck);
+
+mykonosErr_t MYKONOS_setClgcAttenTuningConfig(mykonosDevice_t *device, mykonosClgcAttenTuningConfig_t *attRangeCfg);
+mykonosErr_t MYKONOS_getClgcAttenTuningConfig(mykonosDevice_t *device, mykonosClgcAttenTuningConfig_t *attRangeCfg);
+
+mykonosErr_t MYKONOS_configClgc(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getClgcConfig(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getClgcStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosClgcStatus_t *clgcStatus);
+mykonosErr_t MYKONOS_setClgcGain(mykonosDevice_t *device, mykonosTxChannels_t txChannel, int16_t gain);
+
+mykonosErr_t MYKONOS_configVswr(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getVswrConfig(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getVswrStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosVswrStatus_t *vswrStatus);
+
+mykonosErr_t MYKONOS_runInitCals(mykonosDevice_t *device, uint32_t calMask);
+mykonosErr_t MYKONOS_waitInitCals(mykonosDevice_t *device, uint32_t timeoutMs, uint8_t *errorFlag, uint8_t *errorCode);
+mykonosErr_t MYKONOS_abortInitCals(mykonosDevice_t *device, uint32_t *calsCompleted);
+mykonosErr_t MYKONOS_getInitCalStatus(mykonosDevice_t *device, mykonosInitCalStatus_t *initCalStatus);
+
+mykonosErr_t MYKONOS_resetExtTxLolChannel(mykonosDevice_t *device, mykonosTxChannels_t channelSel);
+
+mykonosErr_t MYKONOS_radioOn(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_radioOff(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_getRadioState(mykonosDevice_t *device, uint32_t *radioStatus);
+mykonosErr_t MYKONOS_enableTrackingCals(mykonosDevice_t *device, uint32_t enableMask);
+mykonosErr_t MYKONOS_rescheduleTrackingCal(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal);
+mykonosErr_t MYKONOS_setAllTrackCalState(mykonosDevice_t *device, uint32_t trackingCalMask);
+mykonosErr_t MYKONOS_getAllTrackCalState(mykonosDevice_t *device, uint32_t *trackCals);
+mykonosErr_t MYKONOS_setTrackingCalState(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal, uint8_t trackCalState);
+mykonosErr_t MYKONOS_getTrackingCalState(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal, uint8_t *trackCalState);
+mykonosErr_t MYKONOS_getEnabledTrackingCals(mykonosDevice_t *device, uint32_t *enableMask);
+mykonosErr_t MYKONOS_getPendingTrackingCals(mykonosDevice_t *device, uint32_t *pendingCalMask);
+mykonosErr_t MYKONOS_getTxLolStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosTxLolStatus_t *txLolStatus);
+mykonosErr_t MYKONOS_getTxQecStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosTxQecStatus_t *txQecStatus);
+
+mykonosErr_t MYKONOS_getRxQecStatus(mykonosDevice_t *device, mykonosRxChannels_t rxChannel, mykonosRxQecStatus_t *rxQecStatus);
+mykonosErr_t MYKONOS_getOrxQecStatus(mykonosDevice_t *device, mykonosObsRxChannels_t orxChannel, mykonosOrxQecStatus_t *orxQecStatus);
+
+mykonosErr_t MYKONOS_setSnifferChannel(mykonosDevice_t *device, mykonosSnifferChannel_t snifferChannel);
+mykonosErr_t MYKONOS_setRadioControlPinMode(mykonosDevice_t *device);
+
+mykonosErr_t MYKONOS_setPathDelay(mykonosDevice_t *device, mykonosPathdelay_t *pathDelay);
+mykonosErr_t MYKONOS_getPathDelay(mykonosDevice_t *device, mykonosPathDelaySel_t select, mykonosPathdelay_t *pathDelay);
+
+mykonosErr_t MYKONOS_getDpdErrorCounters(mykonosDevice_t *device,  mykonosTxChannels_t txChannel, mykonosDpdErrorCounters_t *dpdErrCnt);
+
+/* Low level ARM functions */
+mykonosErr_t MYKONOS_readArmMem(mykonosDevice_t *device, uint32_t address, uint8_t *returnData, uint32_t bytesToRead, uint8_t autoIncrement);
+mykonosErr_t MYKONOS_writeArmMem(mykonosDevice_t *device, uint32_t address, uint8_t *data, uint32_t byteCount);
+mykonosErr_t MYKONOS_writeArmConfig(mykonosDevice_t *device, uint8_t objectId, uint16_t offset, uint8_t *data, uint8_t byteCount);
+mykonosErr_t MYKONOS_readArmConfig(mykonosDevice_t *device, uint8_t objectId, uint16_t offset, uint8_t *data, uint8_t byteCount);
+mykonosErr_t MYKONOS_sendArmCommand(mykonosDevice_t *device, uint8_t opCode,  uint8_t *extendedData, uint8_t extendedDataNumBytes);
+mykonosErr_t MYKONOS_readArmCmdStatus(mykonosDevice_t *device, uint16_t *errorWord, uint16_t *statusWord);
+mykonosErr_t MYKONOS_readArmCmdStatusByte(mykonosDevice_t *device, uint8_t opCode, uint8_t *cmdStatByte);
+mykonosErr_t MYKONOS_waitArmCmdStatus(mykonosDevice_t *device, uint8_t opCode, uint32_t timeoutMs, uint8_t *cmdStatByte);
+mykonosErr_t MYKONOS_writeArmProfile(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_loadAdcProfiles(mykonosDevice_t *device);
+
+
+/*
+ *****************************************************************************
+ * JESD204B Datapath Functions
+ *****************************************************************************
+ */
+/* Functions to setup the JESD204B IP */
+mykonosErr_t MYKONOS_resetDeframer(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setupSerializers(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setupDeserializers(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setupJesd204bFramer(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setupJesd204bObsRxFramer(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setupJesd204bDeframer(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_enableRxFramerLink(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_enableObsRxFramerLink(mykonosDevice_t *device, uint8_t enable);
+
+/* Functions to initialize the JESD204B link */
+mykonosErr_t MYKONOS_enableMultichipSync(mykonosDevice_t *device, uint8_t enableMcs, uint8_t *mcsStatus);
+mykonosErr_t MYKONOS_enableSysrefToRxFramer(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_enableSysrefToObsRxFramer(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_enableSysrefToDeframer(mykonosDevice_t *device, uint8_t enable);
+
+/* Functions to help debug the JESD204B link */
+mykonosErr_t MYKONOS_readRxFramerStatus(mykonosDevice_t *device, uint8_t *framerStatus);
+mykonosErr_t MYKONOS_readOrxFramerStatus(mykonosDevice_t *device, uint8_t *obsFramerStatus);
+mykonosErr_t MYKONOS_readDeframerStatus(mykonosDevice_t *device, uint8_t *deframerStatus);
+mykonosErr_t MYKONOS_getDeframerFifoDepth(mykonosDevice_t *device, uint8_t *fifoDepth, uint8_t *readEnLmfcCount);
+
+/* PRBS debug functions */
+mykonosErr_t MYKONOS_enableRxFramerPrbs(mykonosDevice_t *device, mykonosPrbsOrder_t polyOrder, uint8_t enable);
+mykonosErr_t MYKONOS_enableObsRxFramerPrbs(mykonosDevice_t *device, mykonosPrbsOrder_t polyOrder, uint8_t enable);
+mykonosErr_t MYKONOS_rxInjectPrbsError(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_obsRxInjectPrbsError(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_enableDeframerPrbsChecker(mykonosDevice_t *device, uint8_t lanes, mykonosPrbsOrder_t polyOrder, uint8_t enable);
+mykonosErr_t MYKONOS_clearDeframerPrbsCounters(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_readDeframerPrbsCounters(mykonosDevice_t *device, uint8_t counterSelect, uint32_t *prbsErrorCount);
+
+/* Miscellaneous debug functions */
+mykonosErr_t MYKONOS_jesd204bIlasCheck(mykonosDevice_t *device, uint16_t *mismatch);
+mykonosErr_t MYKONOS_setRxFramerDataSource(mykonosDevice_t *device, uint8_t dataSource);
+mykonosErr_t MYKONOS_setObsRxFramerDataSource(mykonosDevice_t *device, uint8_t dataSource);
+
+/*
+ *****************************************************************************
+ * Shared Data path functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_programFir(mykonosDevice_t *device, mykonosfirName_t filterToProgram, mykonosFir_t *firFilter);
+mykonosErr_t MYKONOS_readFir(mykonosDevice_t *device, mykonosfirName_t filterToRead, mykonosFir_t *firFilter);
+
+/*
+ *****************************************************************************
+ * Rx Data path functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_programRxGainTable(mykonosDevice_t *device, uint8_t *gainTablePtr, uint8_t numGainIndexesInTable, mykonosGainTable_t rxChannel);
+mykonosErr_t MYKONOS_setRx1ManualGain(mykonosDevice_t *device, uint8_t gainIndex);
+mykonosErr_t MYKONOS_setRx2ManualGain(mykonosDevice_t *device, uint8_t gainIndex);
+mykonosErr_t MYKONOS_getRx1Gain(mykonosDevice_t *device, uint8_t *rx1GainIndex);
+mykonosErr_t MYKONOS_getRx2Gain(mykonosDevice_t *device, uint8_t *rx2GainIndex);
+mykonosErr_t MYKONOS_setupRxAgc(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_resetRxAgc(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setRxAgcMinMaxGainIndex(mykonosDevice_t *device, mykonosRxChannels_t rxChannelSelect, uint8_t maxGainIndex, uint8_t minGainIndex);
+mykonosErr_t MYKONOS_setObsRxAgcMinMaxGainIndex(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxChannelSelect, uint8_t maxGainIndex, uint8_t minGainIndex);
+mykonosErr_t MYKONOS_setRx1TempGainComp(mykonosDevice_t *device, int16_t rx1TempCompGain_mdB);
+mykonosErr_t MYKONOS_getRx1TempGainComp(mykonosDevice_t *device, int16_t *rx1TempCompGain_mdB);
+mykonosErr_t MYKONOS_setRx2TempGainComp(mykonosDevice_t *device, int16_t rx2TempCompGain_mdB);
+mykonosErr_t MYKONOS_getRx2TempGainComp(mykonosDevice_t *device, int16_t *rx2TempCompGain_mdB);
+mykonosErr_t MYKONOS_setObsRxTempGainComp(mykonosDevice_t *device, int16_t obsRxTempCompGain_mdB);
+mykonosErr_t MYKONOS_getObsRxTempGainComp(mykonosDevice_t *device, int16_t *obsRxTempCompGain_mdB);
+mykonosErr_t MYKONOS_enableRxGainCtrSyncPulse(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_setRxGainControlMode(mykonosDevice_t *device, mykonosGainMode_t mode);
+mykonosErr_t MYKONOS_getRx1DecPower(mykonosDevice_t *device, uint16_t *rx1DecPower_mdBFS);
+mykonosErr_t MYKONOS_getRx2DecPower(mykonosDevice_t *device, uint16_t *rx2DecPower_mdBFS);
+
+/*
+ *****************************************************************************
+ * Observation Rx Data path functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_setDefaultObsRxPath(mykonosDevice_t *device,  mykonosObsRxChannels_t defaultObsRxCh);
+mykonosErr_t MYKONOS_setObsRxPathSource(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxCh);
+mykonosErr_t MYKONOS_getObsRxPathSource(mykonosDevice_t *device, mykonosObsRxChannels_t *obsRxCh);
+mykonosErr_t MYKONOS_setObsRxManualGain(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxCh, uint8_t gainIndex);
+mykonosErr_t MYKONOS_getObsRxGain(mykonosDevice_t *device, uint8_t *gainIndex);
+mykonosErr_t MYKONOS_setupObsRxAgc(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_enableObsRxGainCtrSyncPulse(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_setObsRxGainControlMode(mykonosDevice_t *device, mykonosGainMode_t mode);
+mykonosErr_t MYKONOS_getObsRxDecPower(mykonosDevice_t *device, uint16_t *obsRxDecPower_mdBFS);
+
+/*
+ *****************************************************************************
+ * Tx Data path functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_setTx1Attenuation(mykonosDevice_t *device, uint16_t tx1Attenuation_mdB);
+mykonosErr_t MYKONOS_setTx2Attenuation(mykonosDevice_t *device, uint16_t tx2Attenuation_mdB);
+mykonosErr_t MYKONOS_getTx1Attenuation(mykonosDevice_t *device, uint16_t *tx1Attenuation_mdB);
+mykonosErr_t MYKONOS_getTx2Attenuation(mykonosDevice_t *device, uint16_t *tx2Attenuation_mdB);
+mykonosErr_t MYKONOS_getTxFilterOverRangeStatus(mykonosDevice_t *device, uint8_t *txFilterStatus);
+mykonosErr_t MYKONOS_enableTxNco(mykonosDevice_t *device, uint8_t enable, int32_t tx1ToneFreq_kHz, int32_t tx2ToneFreq_kHz);
+
+/*
+ *****************************************************************************
+ * PA Protection Functions
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_setupPaProtection(mykonosDevice_t *device, uint16_t powerThreshold, uint8_t attenStepSize, uint8_t avgDuration, uint8_t stickyFlagEnable, uint8_t txAttenControlEnable);
+mykonosErr_t MYKONOS_enablePaProtection(mykonosDevice_t *device, uint8_t enable);
+mykonosErr_t MYKONOS_getDacPower(mykonosDevice_t *device, mykonosTxChannels_t channel, uint16_t *channelPower);
+mykonosErr_t MYKONOS_getPaProtectErrorFlagStatus(mykonosDevice_t *device, uint8_t *errorFlagStatus);
+mykonosErr_t MYKONOS_clearPaErrorFlag(mykonosDevice_t *device);
+
+/*
+ *****************************************************************************
+ * Low level functions and helper functions. BBP should not need to call
+ *****************************************************************************
+ */
+const char* getMykonosErrorMessage(mykonosErr_t errorCode);
+
+mykonosErr_t MYKONOS_initSubRegisterTables(mykonosDevice_t *device);
+mykonosErr_t MYKONOS_setTxPfirSyncClk(mykonosDevice_t *device); /* Helper function */
+mykonosErr_t MYKONOS_setRxPfirSyncClk(mykonosDevice_t *device); /* Helper function */
+
+/*
+ *****************************************************************************
+ * Functions to configure DC offsets
+ *****************************************************************************
+ */
+mykonosErr_t MYKONOS_setRfDcOffsetCnt(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint16_t measureCount);
+mykonosErr_t MYKONOS_getRfDcOffsetCnt(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint16_t *measureCount);
+mykonosErr_t MYKONOS_setDigDcOffsetMShift(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint8_t mShift);
+mykonosErr_t MYKONOS_getDigDcOffsetMShift(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint8_t *mShift);
+mykonosErr_t MYKONOS_setDigDcOffsetEn(mykonosDevice_t *device, uint8_t enableMask);
+mykonosErr_t MYKONOS_getDigDcOffsetEn(mykonosDevice_t *device, uint8_t *enableMask);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

df_datalink_ge/src/hardware/mykonos/mykonosMmap.c

@@ -0,0 +1,136 @@
+/**
+ * \file mykonosMmap.c
+ * \brief Contains the Mykonos memory mapping
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#include <stdint.h>
+uint8_t mykonosMmap [] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x13,0x03,0x03,0x13,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+                                 0x00,0xE4,0xE4,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA5,0xA5,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x01,0x00,0xE4,0xE4,0x00,0x00,0x00,0x1F,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x9F,0xE0,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0xF5,0x8F,0x0F,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
+/*!< Mykonos memory map */

df_datalink_ge/src/hardware/mykonos/mykonos_gpio.h

@@ -0,0 +1,172 @@
+/*!
+ * \file mykonos_gpio.h
+ * \brief Contains macro definitions and function prototypes for mykonos_gpio.c
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef MYKONOSGPIO_H_
+#define MYKONOSGPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "t_mykonos.h"
+#include "t_mykonos_gpio.h"
+
+/*
+ *****************************************************************************
+ * GPIO functions
+ *****************************************************************************
+ */
+
+/* GPIO CMOS and SPI setting Functions */
+mykonosGpioErr_t MYKONOS_setGpioDrv(mykonosDevice_t *device, uint32_t gpioDrv);
+mykonosGpioErr_t MYKONOS_getGpioDrv(mykonosDevice_t *device, uint32_t *gpioDrv);
+
+mykonosGpioErr_t MYKONOS_setGpioSlewRate(mykonosDevice_t *device, mykonosGpioSelect_t gpioSelect, mykonosGpioSlewRate_t slewRate);
+mykonosGpioErr_t MYKONOS_getGpioSlewRate(mykonosDevice_t *device, mykonosGpioSelect_t gpioSelect, mykonosGpioSlewRate_t *slewRate);
+
+mykonosGpioErr_t MYKONOS_setCmosDrv(mykonosDevice_t *device, mykonosCmosPadDrvStr_t spiDrv);
+mykonosGpioErr_t MYKONOS_getCmosDrv(mykonosDevice_t *device, mykonosCmosPadDrvStr_t *spiDrv);
+
+
+/* Monitor output Functions */
+mykonosGpioErr_t MYKONOS_setGpioMonitorOut(mykonosDevice_t *device, uint8_t monitorIndex, uint8_t monitorMask);
+mykonosGpioErr_t MYKONOS_getGpioMonitorOut(mykonosDevice_t *device, uint8_t *monitorIndex, uint8_t *monitorMask);
+
+/* RX GPIO Functions */
+mykonosGpioErr_t MYKONOS_setRx1GainCtrlPin(mykonosDevice_t *device, uint8_t incStep, uint8_t decStep, mykonosGpioSelect_t rx1GainIncPin, mykonosGpioSelect_t rx1GainDecPin, uint8_t enable);
+mykonosGpioErr_t MYKONOS_setRx2GainCtrlPin(mykonosDevice_t *device, uint8_t incStep, uint8_t decStep, mykonosGpioSelect_t rx2GainIncPin, mykonosGpioSelect_t rx2GainDecPin, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getRx1GainCtrlPin(mykonosDevice_t *device, uint8_t *incStep, uint8_t *decStep, mykonosGpioSelect_t *rx1GainIncPin, mykonosGpioSelect_t *rx1GainDecPin, uint8_t *enable);
+mykonosGpioErr_t MYKONOS_getRx2GainCtrlPin(mykonosDevice_t *device, uint8_t *incStep, uint8_t *decStep, mykonosGpioSelect_t *rx2GainIncPin, mykonosGpioSelect_t *rx2GainDecPin, uint8_t *enable);
+
+mykonosGpioErr_t MYKONOS_setRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t rx1GainChangePin, mykonosGpioSelect_t rx2GainChangePin);
+mykonosGpioErr_t MYKONOS_getRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t *rx1GainChangePin, mykonosGpioSelect_t *rx2GainChangePin);
+mykonosGpioErr_t MYKONOS_setObsRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t obsRxGainChangePin);
+mykonosGpioErr_t MYKONOS_getObsRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t *obsRxGainChangePin);
+
+mykonosGpioErr_t MYKONOS_setRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t rx1AgcSyncPin, mykonosGpioSelect_t rx2AgcSyncPin);
+mykonosGpioErr_t MYKONOS_getRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t *rx1AgcSyncPin, mykonosGpioSelect_t *rx2AgcSyncPin);
+mykonosGpioErr_t MYKONOS_setObsRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t obsRxAgcSyncPin);
+mykonosGpioErr_t MYKONOS_getObsRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t *obsRxAgcSyncPin);
+
+/* TX GPIO Functions */
+mykonosGpioErr_t MYKONOS_setTx1AttenCtrlPin(mykonosDevice_t *device, uint8_t stepSize, mykonosGpioSelect_t tx1AttenIncPin, mykonosGpioSelect_t tx1AttenDecPin, uint8_t enable, uint8_t useTx1ForTx2);
+mykonosGpioErr_t MYKONOS_setTx2AttenCtrlPin(mykonosDevice_t *device, uint8_t stepSize, mykonosGpioSelect_t tx2AttenIncPin, mykonosGpioSelect_t tx2AttenDecPin, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getTx1AttenCtrlPin(mykonosDevice_t *device, uint8_t *stepSize, mykonosGpioSelect_t *tx1AttenIncPin, mykonosGpioSelect_t *tx1AttenDecPin, uint8_t *enable, uint8_t *useTx1ForTx2);
+mykonosGpioErr_t MYKONOS_getTx2AttenCtrlPin(mykonosDevice_t *device, uint8_t *stepSize, mykonosGpioSelect_t *tx2AttenIncPin, mykonosGpioSelect_t *tx2AttenDecPin, uint8_t *enable, uint8_t *useTx1ForTx2);
+
+mykonosGpioErr_t MYKONOS_spi2GpioSetup(mykonosDevice_t *device, uint8_t enable, uint8_t updateTxAttenPinSelect);
+
+/* GPIO memory source Functions */
+mykonosGpioErr_t MYKONOS_setGpioPinLevel(mykonosDevice_t *device, uint32_t gpioPinLevel);
+mykonosGpioErr_t MYKONOS_getGpioPinLevel(mykonosDevice_t *device, uint32_t *gpioPinLevel);
+mykonosGpioErr_t MYKONOS_getGpioSetLevel(mykonosDevice_t *device, uint32_t *gpioPinSetLevel);
+
+/* Gain Compensation Functions */
+mykonosGpioErr_t MYKONOS_setRxGainCompensation (mykonosDevice_t *device, mykonosGainComp_t *gainComp, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getRxGainCompensation (mykonosDevice_t *device, mykonosGainComp_t *gainComp, uint8_t *enabled);
+
+mykonosGpioErr_t MYKONOS_setObsRxGainCompensation (mykonosDevice_t *device, mykonosObsRxGainComp_t *gainComp, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getObsRxGainCompensation (mykonosDevice_t *device, mykonosObsRxGainComp_t *gainComp, uint8_t *enabled);
+
+/* SLICER Functions */
+mykonosGpioErr_t MYKONOS_setRxSlicerCtrl(mykonosDevice_t *device, uint8_t slicerStep, mykonosRxSlicer_t rx1Pins, mykonosRxSlicer_t rx2Pins, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getRxSlicerCtrl(mykonosDevice_t *device, uint8_t *slicerStep, mykonosRxSlicer_t *rx1Pins, mykonosRxSlicer_t *rx2Pins, uint8_t *enable);
+
+mykonosGpioErr_t MYKONOS_setObsRxSlicerCtrl(mykonosDevice_t *device, uint8_t slicerStep, mykonosObsRxSlicer_t obsRxPins, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getObsRxSlicerCtrl(mykonosDevice_t *device, uint8_t *slicerStep, mykonosObsRxSlicer_t *obsRxPins, uint8_t *enable);
+
+/* Floating Point Formatter Functions */
+mykonosGpioErr_t MYKONOS_setFloatPointFrmt (mykonosDevice_t *device, mykonosFloatPntFrmt_t *floatFrmt);
+mykonosGpioErr_t MYKONOS_getFloatPointFrmt (mykonosDevice_t *device, mykonosFloatPntFrmt_t *floatFrmt);
+
+mykonosGpioErr_t MYKONOS_setRxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t rx1Att, uint8_t rx2Att, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getRxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t *rx1Att, uint8_t *rx2Att, uint8_t *enable);
+
+mykonosGpioErr_t MYKONOS_setOrxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t orxAtt, uint8_t enable);
+mykonosGpioErr_t MYKONOS_getOrxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t *orxAtt, uint8_t *enable);
+
+/*
+ *****************************************************************************
+ * General Purpose Interrupt functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_configGpInterrupt(mykonosDevice_t *device, uint16_t gpMask);
+mykonosGpioErr_t MYKONOS_readGpInterruptStatus(mykonosDevice_t *device, uint16_t *status);
+
+/*
+ *****************************************************************************
+ * ARM GPIO usage functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_setArmGpioPins(mykonosDevice_t *device);
+
+/*
+ *****************************************************************************
+ * AuxADC/AuxDAC functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_setupAuxAdcs(mykonosDevice_t *device, uint8_t adcDecimation, uint8_t enable);
+mykonosGpioErr_t MYKONOS_setAuxAdcChannel(mykonosDevice_t *device, mykonosAuxAdcChannels_t auxAdcChannel);
+mykonosGpioErr_t MYKONOS_readAuxAdc(mykonosDevice_t *device, uint16_t *adcCode);
+mykonosGpioErr_t MYKONOS_setupAuxDacs(mykonosDevice_t *device);
+mykonosGpioErr_t MYKONOS_writeAuxDac(mykonosDevice_t *device, uint8_t auxDacIndex, uint16_t auxDacCode);
+
+/*
+ *****************************************************************************
+ * GPIO3v3 functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_setupGpio3v3(mykonosDevice_t *device);
+
+mykonosGpioErr_t MYKONOS_setGpio3v3PinLevel(mykonosDevice_t *device, uint16_t gpio3v3PinLevel);
+mykonosGpioErr_t MYKONOS_getGpio3v3SetLevel(mykonosDevice_t *device, uint16_t *gpio3v3SetLevel);
+
+mykonosGpioErr_t MYKONOS_getGpio3v3PinLevel(mykonosDevice_t *device, uint16_t *gpio3v3PinLevel);
+
+mykonosGpioErr_t MYKONOS_setGpio3v3Oe(mykonosDevice_t *device, uint16_t gpio3v3OutEn);
+mykonosGpioErr_t MYKONOS_getGpio3v3Oe(mykonosDevice_t *device, uint16_t *gpio3v3OutEn);
+
+mykonosGpioErr_t MYKONOS_setGpio3v3SourceCtrl(mykonosDevice_t *device, uint16_t gpio3v3SrcCtrl);
+mykonosGpioErr_t MYKONOS_getGpio3v3SourceCtrl(mykonosDevice_t *device, uint16_t *gpio3v3SrcCtrl);
+
+/*
+ *****************************************************************************
+ * GPIO helper functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_setupGpio(mykonosDevice_t *device);
+mykonosGpioErr_t MYKONOS_setGpioOe(mykonosDevice_t *device, uint32_t gpioOutEn, uint32_t gpioUsedMask);
+mykonosGpioErr_t MYKONOS_getGpioOe(mykonosDevice_t *device, uint32_t *gpioOutEn);
+
+mykonosGpioErr_t MYKONOS_setGpioSourceCtrl(mykonosDevice_t *device, uint32_t gpioSrcCtrl);
+mykonosGpioErr_t MYKONOS_getGpioSourceCtrl(mykonosDevice_t *device, uint32_t *gpioSrcCtrl);
+
+/*
+ *****************************************************************************
+ * Temperature Sensor functions
+ *****************************************************************************
+ */
+mykonosGpioErr_t MYKONOS_setupTempSensor(mykonosDevice_t *device, mykonosTempSensorConfig_t *tempSensor);
+mykonosGpioErr_t MYKONOS_getTempSensorConfig(mykonosDevice_t *device, mykonosTempSensorConfig_t *tempSensor);
+
+mykonosGpioErr_t MYKONOS_startTempMeasurement(mykonosDevice_t *device);
+mykonosGpioErr_t MYKONOS_readTempSensor(mykonosDevice_t *device, mykonosTempSensorStatus_t *tempStatus);
+
+const char* getGpioMykonosErrorMessage(mykonosGpioErr_t errorCode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MYKONOSGPIO_H_ */

df_datalink_ge/src/hardware/mykonos/mykonos_macros.h

@@ -0,0 +1,707 @@
+/**
+ * \file mykonos_macros.h
+ * \brief Contains address and miscellaneous macro definitions for Mykonos API
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef CLEMENTE_TDD_MACROS_H
+#define CLEMENTE_TDD_MACROS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MYKONOS_ADDR_CONFIGURATION_CONTROL_0                0x000
+#define MYKONOS_ADDR_SPI_CONFIGURATION_CONTROL_1            0x001
+#define MYKONOS_ADDR_PRODUCT_ID                             0x004
+#define MYKONOS_GPIO_DRV_CTL_0                              0x020
+#define MYKONOS_GPIO_DRV_CTL_1                              0x021
+#define MYKONOS_GPIO_SLEW_CTL_0                             0x022
+#define MYKONOS_GPIO_SLEW_CTL_1                             0x023
+#define MYKONOS_GPIO_SLEW_CTL_2                             0x024
+#define MYKONOS_GPIO_SLEW_CTL_3                             0x025
+
+#define MYKONOS_ADDR_DIGITAL_IO_CONTROL                     0x028
+
+#define MYKONOS_ADDR_SYSREF_PAD_CONFIG                      0x040
+#define MYKONOS_ADDR_TX1_SYNC_PAD_CONFIG                    0x041
+#define MYKONOS_ADDR_TX2_SYNC_PAD_CONFIG                    0x042
+#define MYKONOS_ADDR_RX1_SYNC_CONFIG                        0x043
+#define MYKONOS_ADDR_RX2_SYNC_CONFIG                        0x044
+
+/* Mykonos Framer Registers */
+#define MYKONOS_ADDR_FRAMER_RESET                           0x059
+#define MYKONOS_ADDR_FRAMER_CLK_EN                          0x05A
+#define MYKONOS_ADDR_FRAMER_ADDR                            0x05B
+#define MYKONOS_ADDR_FRAMER_DATA                            0x05C
+#define MYKONOS_ADDR_FRAMER_WRITE_EN                        0x05D
+#define MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN                  0x05E
+#define MYKONOS_ADDR_FRAMER_CONFIG_F                        0x05F
+#define MYKONOS_ADDR_FRAMER_LANE_CTL                        0x060
+#define MYKONOS_ADDR_FRAMER_ADC_XBAR_SEL                    0x061
+#define MYKONOS_ADDR_FRAMER_LANE_XBAR_SEL                   0x062
+#define MYKONOS_ADDR_FRAMER_CONFIG_LOOPBACK_XBAR_REV        0x063
+#define MYKONOS_ADDR_FRAMER_SYNCN_FILT                      0x064
+#define MYKONOS_ADDR_FRAMER_LMFC_F_OFFSET                   0x065
+#define MYKONOS_ADDR_FRAMER_LMFC_K_OFFSET                   0x066
+#define MYKONOS_ADDR_FRAMER_TEST_CNTR_CTL                   0x067
+#define MYKONOS_ADDR_FRAMER_STATUS_STRB                     0x068
+#define MYKONOS_ADDR_FRAMER_STATUS                          0x069
+#define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_CNTR_STAT        0x06A
+#define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN       0x06B
+#define MYKONOS_ADDR_FRAMER_LANE_FIFO_STRB                  0x06C
+#define MYKONOS_ADDR_FRAMER_LANE0_FIFO_RDWR_ADDR            0x06D
+#define MYKONOS_ADDR_FRAMER_LANE1_FIFO_RDWR_ADDR            0x06E
+#define MYKONOS_ADDR_FRAMER_LANE2_FIFO_RDWR_ADDR            0x06F
+#define MYKONOS_ADDR_FRAMER_LANE3_FIFO_RDWR_ADDR            0x070
+#define MYKONOS_ADDR_FRAMER_PRBS10_CTL                      0x071
+#define MYKONOS_ADDR_FRAMER_PRBS20_CTL                      0x072
+#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_EN                  0x073
+#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_7_TO_0              0x074
+#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_15_TO_8             0x075
+#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_19_TO_16            0x076
+#define MYKONOS_ADDR_FRAMER_CONFIG_JTX_GEN                  0x077
+#define MYKONOS_ADDR_FRAMER_LANE_DATA_CTL                   0x078
+#define MYKONOS_ADDR_FRAMER_DATA_SAMPLE_CTL                 0x079
+
+/* Mykonos Deframer Sub Address Map */
+#define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_RECVD           0x00
+#define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_CFG             0x50
+
+/* Mykonos Deframer Registers */
+#define MYKONOS_ADDR_DEFRAMER_RESET                         0x07A
+#define MYKONOS_ADDR_DEFRAMER_CLK_EN                        0x07B
+#define MYKONOS_ADDR_DEFRAMER_ADDR                          0x07C
+#define MYKONOS_ADDR_DEFRAMER_DATA                          0x07D
+#define MYKONOS_ADDR_DEFRAMER_WR_EN                         0x07E
+#define MYKONOS_ADDR_DEFRAMER_SYSREF_FIFO_EN                0x07F
+#define MYKONOS_ADDR_DEFRAMER_CONFIG_F                      0x080
+#define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_CTL                 0x081
+#define MYKONOS_ADDR_DEFRAMER_DAC_XBAR_SEL                  0x082
+#define MYKONOS_ADDR_DEFRAMER_LANE_XBAR_SEL                 0x083
+#define MYKONOS_ADDR_DEFRAMER_LMFC_F_OFFSET                 0x084
+#define MYKONOS_ADDR_DEFRAMER_LMFC_K_OFFSET                 0x085
+#define MYKONOS_ADDR_DEFRAMER_CONFIG_SYNC_USER_DATA_CTL     0x086
+#define MYKONOS_ADDR_DEFRAMER_SYNC_REQ_RETIME               0x087
+#define MYKONOS_ADDR_DEFRAMER_TEST                          0x088
+#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_STRT_DAC_XBAR_REV 0x089
+#define MYKONOS_ADDR_DEFRAMER_STAT_STRB                     0x08A
+#define MYKONOS_ADDR_DEFRAMER_STAT                          0x08B
+#define MYKONOS_ADDR_DEFRAMER_TEST_ERR_CNT_STAT             0x08C
+#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_RD_ADDR              0x08D
+#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_ADDR              0x08E
+#define MYKONOS_ADDR_DEFRAMER_QBLMFC_VS_EXTLMFC_CNTR_STAT   0x08F
+#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_STAT                 0x090
+#define MYKONOS_ADDR_DEFRAMER_STRT_RD_DEL_STOP_WR           0x091
+#define MYKONOS_ADDR_DEFRAMER_FIFO_SAMPLE_SPI_ADDR_RD       0x092
+#define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_ADDR_RD         0x093
+#define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_DATA_RD         0x094
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE0_7_TO_0                0x095
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE0_15_TO_8               0x096
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE1_7_TO_0                0x097
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE1_15_TO_8               0x098
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE2_7_TO_0                0x099
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE2_15_TO_8               0x09A
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE3_7_TO_0                0x09B
+#define MYKONOS_ADDR_DEFRAMER_SAMPLE3_15_TO_8               0x09C
+#define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_STRB                0x09D
+#define MYKONOS_ADDR_DEFRAMER_LANE0_FIFO_RDWR_ADDR          0x09E
+#define MYKONOS_ADDR_DEFRAMER_LANE1_FIFO_RDWR_ADDR          0x09F
+#define MYKONOS_ADDR_DEFRAMER_LANE2_FIFO_RDWR_ADDR          0x0A0
+#define MYKONOS_ADDR_DEFRAMER_LANE3_FIFO_RDWR_ADDR          0x0A1
+#define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_CNTR_STAT      0x0A2
+#define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_ERR_MARGIN     0x0A3
+#define MYKONOS_ADDR_DEFRAMER_PRBS10_CTL                    0x0A4
+#define MYKONOS_ADDR_DEFRAMER_PRBS20_CTL                    0x0A5
+#define MYKONOS_ADDR_DEFRAMER_PRBS20_STRB_CHKSUM_TYPE       0x0A6
+#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_7_TO_0        0x0A7
+#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_15_TO_8       0x0A8
+#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_23_TO_16      0x0A9
+#define MYKONOS_ADDR_DEFRAMER_LANE_DATA_CTL                 0x0AA
+#define MYKONOS_ADDR_DEFRAMER_STATUS_2                      0x0AB
+#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_PHASE                0x0AC
+
+/* Mykonos Serializer Registers */
+#define MYKONOS_ADDR_SERIALIZER_CTL_0                       0x0B0
+#define MYKONOS_ADDR_SERIALIZER_CTL_1                       0x0B1
+#define MYKONOS_ADDR_SERIALIZER_CTL_2                       0x0B2
+#define MYKONOS_ADDR_SERIALIZER_CTL_3                       0x0B3
+#define MYKONOS_ADDR_SERIALIZER_HS_DIV_TXSER_CLK_EN         0x0B4
+#define MYKONOS_ADDR_SERIALIZER_SPECIAL                     0x0B5
+
+/* Mykonos Deserializer Registers */
+#define MYKONOS_ADDR_DESERIALIZER_PDET_CTL                  0x0BC
+#define MYKONOS_ADDR_DESERIALIZER_CTL_0                     0x0BD
+#define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_0               0x0BE
+#define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_1               0x0BF
+#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_0                  0x0C1
+#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1                  0x0C2
+#define MYKONOS_ADDR_DESERIALIZER_MISC_CTL                  0x0C3
+#define MYKONOS_ADDR_DESERIALIZER_EQ_HP_EN                  0x0C4
+#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1_TO_0             0x0C5
+#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_3_TO_2             0x0C6
+#define MYKONOS_ADDR_DESERIALIZER_HS_DIV_RXCDR_CLK_EN       0x0CD
+#define MYKONOS_ADDR_DESERIALIZER_SPECIAL                   0x0CE
+#define MYKONOS_ADDR_DESERIALIZER_CDR_CAL_CTL               0x0D0
+
+#define MYKONOS_ADDR_CONFIGURATION_CONTROL_1                0x100
+#define MYKONOS_ADDR_CONFIGURATION_CONTROL_2                0x101
+#define MYKONOS_ADDR_CONFIGURATION_CONTROL_4                0x102
+#define MYKONOS_ADDR_CONFIGURATION_CONTROL_5                0x103
+#define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_1    0x104
+#define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_2    0x105
+#define MYKONOS_ADDR_DPD_SNIFFER_GPIO_SELECT                0x106
+#define MYKONOS_ADDR_SNIFFER_CONFIGURATION_CONTROL          0x107
+#define MYKONOS_ADDR_DPD_CONFIGURATION_CONTROL              0x108
+#define MYKONOS_ADDR_LOOPBACK_CONFIGURATION_CONTROL         0x109
+
+#define MYKONOS_ADDR_CLOCK_CONTROL_0						0x117
+#define MYKONOS_ADDR_CLOCK_CONTROL_1						0x118
+#define MYKONOS_ADDR_CLOCK_CONTROL_2						0x119
+#define MYKONOS_ADDR_CLOCK_CONTROL_3						0x11A
+#define MYKONOS_ADDR_CLOCK_CONTROL_4						0x11B
+#define MYKONOS_ADDR_CLOCK_CONTROL_5                        0x11C
+
+#define MYKONOS_ADDR_MCS_CONTROL                            0x120
+#define MYKONOS_ADDR_MCS_STATUS                             0x121
+
+/* CLK PLL Registers */
+#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE0            0x141
+#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE1            0x142
+#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE0           0x143
+#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE1           0x144
+#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE2           0x145
+#define MYKONOS_ADDR_CLK_SYNTH_F_VCOTN_BYTE1                0x148
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE1                        0x149
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE2                        0x14A
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE3                        0x14B
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE5                        0x14D
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE6                        0x14E
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE7                        0x14F
+#define MYKONOS_ADDR_CLK_SYNTH_LF_R3                        0x150
+#define MYKONOS_ADDR_CLK_SYNTH_BYTE9                        0x152
+#define MYKONOS_ADDR_CLK_SYNTH_CAL_STAT                     0x154
+#define MYKONOS_ADDR_CLK_SYNTH_VCO_CAL_REF                  0x155
+#define MYKONOS_ADDR_CLK_SYNTH_VCO_BAND_BYTE1               0x157
+#define MYKONOS_ADDR_CLK_SYNTH_CAL_CONTROL                  0x159
+#define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL1                 0x15E
+#define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL2                 0x15F
+
+/* DPD Registers */
+#define MYKONOS_ADDR_TX1_DPD_MODEL_INDIRECT_PTR             0x178
+#define MYKONOS_ADDR_TX2_DPD_MODEL_INDIRECT_PTR             0x17C
+#define MYKONOS_ADDR_DPD_RMS_BUF_SIZE                       0x180
+#define MYKONOS_ADDR_TX1_DPD_MODEL_WORKING_PTR              0x188
+#define MYKONOS_ADDR_TX2_DPD_MODEL_WORKING_PTR              0x18C
+
+/* Rx NCO Control registers */
+#define MYKONOS_ADDR_CALPLL_SDM_CONTROL                     0x17F
+#define MYKONOS_ADDR_RX_NCO_CONTROL                         0x190
+#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_3                  0x191
+#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_2                  0x192
+#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_1                  0x193
+#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_3                  0x194
+#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_2                  0x195
+#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_1                  0x196
+#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_3          0x197
+#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_2          0x198
+#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_1          0x199
+
+#define MYKONOS_ADDR_ENSM_CONFIG_7_0                        0x1B0
+#define MYKONOS_ADDR_CALIBRATION_CONTROL                    0x1B2
+#define MYKONOS_ADDR_ENSM_MANUAL_GAIN_LOCK_GPIO_SELECT      0x1B5
+#define MYKONOS_ADDR_REFERENCE_CLOCK_CYCLES                 0x1C0
+#define MYKONOS_ADDR_TX_PD_OVERIDE_7_0                      0x209
+#define MYKONOS_ADDR_RCAL_CONTROL                           0x224
+#define MYKONOS_ADDR_REF_PAD_CONFIG1                        0x230
+#define MYKONOS_ADDR_REF_PAD_CONFIG2                        0x231
+
+#define MYKONOS_ADDR_RXSYNTH_CP_CAL_STAT                    0x254
+#define MYKONOS_ADDR_RXSYNTH_VCO_BAND_BYTE1                 0x257
+#define MYKONOS_ADDR_TXSYNTH_CP_CAL_STAT                    0x2C4
+#define MYKONOS_ADDR_TXSYNTH_VCO_BAND_BYTE1                 0x2C7
+#define MYKONOS_ADDR_SNIFF_RXSYNTH_CP_CAL_STAT              0x354
+#define MYKONOS_ADDR_SNIFF_RXSYNTH_VCO_BAND_BYTE1           0x357
+#define MYKONOS_ADDR_SNIFF_RXLOGEN_BYTE1                    0x380
+
+#define MYKONOS_ADDR_RX_FILTER_CONFIGURATION                0x410
+#define MYKONOS_ADDR_RX_FILTER_GAIN                         0x411
+#define MYKONOS_ADDR_DPD_SNIFFER_RX_FILTER_GAIN             0x412
+
+/* Mykonos Temperature Gain Compensation Registers */
+#define MYKONOS_ADDR_RX1_TEMP_GAIN_COMP                     0x420
+#define MYKONOS_ADDR_RX2_TEMP_GAIN_COMP                     0x421
+#define MYKONOS_ADDR_OBS_TEMP_GAIN_COMP                     0x422
+
+/* Mykonos AGC General Registers */
+#define MYKONOS_ADDR_AGC_CFG_1                              0x42E
+#define MYKONOS_ADDR_AGC_CFG_2                              0x42F
+#define MYKONOS_ADDR_AGC_GAIN_CHANGE_GPIO_SEL               0x430
+#define MYKONOS_ADDR_AGC_RX1_MAX_GAIN_INDEX                 0x431
+#define MYKONOS_ADDR_AGC_RX1_MIN_GAIN_INDEX                 0x432
+#define MYKONOS_ADDR_AGC_MANUAL_GAIN_CFG                    0x433
+#define MYKONOS_ADDR_AGC_MANUAL_GAIN_GPIO_SEL               0x434
+#define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_1             0x435
+#define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_2             0x436
+#define MYKONOS_ADDR_AGC_LOCK_LEVEL                         0x437
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_1                   0x438
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_2                   0x439
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_3                   0x43A
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_4                   0x43B
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_5                   0x43C
+#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_6                   0x43D
+#define MYKONOS_ADDR_AGC_RX1_GAIN_LOCK_DELAY                0x43E
+#define MYKONOS_ADDR_AGC_RX2_GAIN_LOCK_DELAY                0x43F
+#define MYKONOS_ADDR_AGC_RX1_ATTACK_DELAY                   0x440
+#define MYKONOS_ADDR_AGC_RX2_ATTACK_DELAY                   0x441
+#define MYKONOS_ADDR_AGC_ULB_THRSH                          0x442
+#define MYKONOS_ADDR_AGC_LLB_THRSH                          0x443
+#define MYKONOS_ADDR_AGC_RX_BLOCK_DET_DECAY                 0x444
+#define MYKONOS_ADDR_AGC_RESET_PD_HIGH_CNT                  0x445
+#define MYKONOS_ADDR_AGC_RX2_MAX_GAIN_INDEX                 0x446
+#define MYKONOS_ADDR_AGC_RX2_MIN_GAIN_INDEX                 0x447
+#define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_1                     0x448
+#define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_2                     0x449
+#define MYKONOS_ADDR_AGC_ORX_SNRX_MAX_GAIN_INDEX            0x44A
+#define MYKONOS_ADDR_AGC_ORX_SNRX_MIN_GAIN_INDEX            0x44B
+#define MYKONOS_ADDR_AGC_ORX_SNRX_MANUAL_GAIN_CFG           0x44C
+#define MYKONOS_ADDR_AGC_ORX_SNRX_GPIO_SEL                  0x44D
+#define MYKONOS_ADDR_AGC_ORX_SNRX_LOCK_LEVEL                0x44E
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_1          0x44F
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_2          0x450
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_3          0x451
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_4          0x452
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_5          0x453
+#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_6          0x454
+#define MYKONOS_ADDR_AGC_ORX_SNRX_GAIN_LOCK_DELAY           0x455
+#define MYKONOS_ADDR_AGC_ORX_SNRX_ATTACK_DELAY              0x456
+#define MYKONOS_ADDR_AGC_ORX_SNRX_ULB_THRSH                 0x457
+#define MYKONOS_ADDR_AGC_ORX_SNRX_LLB_THRSH                 0x458
+#define MYKONOS_ADDR_AGC_ORX_SNRX_BLOCK_DET_DECAY           0x459
+#define MYKONOS_ADDR_AGC_ORX_SNRX_RESET_PD_HIGH_CNT         0x45A
+#define MYKONOS_ADDR_AGC_ORX1_MANUAL_GAIN_INDEX             0x45B
+#define MYKONOS_ADDR_AGC_ORX2_MANUAL_GAIN_INDEX             0x45C
+#define MYKONOS_ADDR_AGC_SNRX_MANUAL_GAIN_INDEX             0x45D
+#define MYKONOS_ADDR_AGC_LOOPBACK1_MANUAL_GAIN_INDEX        0x45E
+#define MYKONOS_ADDR_AGC_LOOPBACK2_MANUAL_GAIN_INDEX        0x45F
+#define MYKONOS_ADDR_AGC_ORX_SNRX_ACTIVE                    0x460
+
+/* Mykonos Fast Attack AGC Registers */
+#define MYKONOS_ADDR_AGC_FAST_CFG_1                         0x468
+#define MYKONOS_ADDR_AGC_FAST_CFG_2                         0x469
+#define MYKONOS_ADDR_AGC_FAST_ENRGY_LOST_THRSH              0x46A
+#define MYKONOS_ADDR_AGC_FAST_STRONG_SIG_THRSH              0x46B
+#define MYKONOS_ADDR_AGC_FAST_SETTING_DELAY                 0x46C
+#define MYKONOS_ADDR_AGC_FAST_OPT_MAX_GAIN                  0x46D
+#define MYKONOS_ADDR_AGC_FAST_ENRGY_DET_CNT                 0x46E
+#define MYKONOS_ADDR_AGC_FAST_AGCLL_UPPER_LIMIT             0x46F
+#define MYKONOS_ADDR_AGC_FAST_GAIN_LOCK_EXIT_CNT            0x470
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_1                0x471
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_2                0x472
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_LOST_THRSH     0x473
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_STRONG_SIG_THRSH     0x474
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_SET_DELAY            0x475
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_OPT_MAX_GAIN         0x476
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_DET_CNT        0x477
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_AGCLL_UPPER_LIMIT    0x478
+#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_GAIN_LOCK_EXIT_CNT   0x479
+
+/* Mykonos Slow Loop - Hybrid AGC Registers */
+#define MYKONOS_ADDR_AGC_SLOW_LOCK_LEV_THRSH                    0x480
+#define MYKONOS_ADDR_AGC_SLOW_ULB_CNT_THRSH                     0x481
+#define MYKONOS_ADDR_AGC_SLOW_LLB_CNT_THRSH                     0x482
+#define MYKONOS_ADDR_AGC_SLOW_HIGH_OVRG_CNT_THRSH               0x483
+#define MYKONOS_ADDR_AGC_SLOW_LOW_OVRG_CNT_THRSH                0x484
+#define MYKONOS_ADDR_AGC_SLOW_VERYLOW_OVRG_CNT_THRSH            0x485
+#define MYKONOS_ADDR_AGC_SLOW_DIG_SAT_CNT_THRSH                 0x486
+#define MYKONOS_ADDR_AGC_SLOW_UPPER0_THRSH_GAIN_STEP            0x487
+#define MYKONOS_ADDR_AGC_SLOW_LOWER0_THRSH_GAIN_STEP            0x488
+#define MYKONOS_ADDR_AGC_SLOW_UPPER1_THRSH_GAIN_STEP            0x489
+#define MYKONOS_ADDR_AGC_SLOW_LOWER1_THRSH_GAIN_STEP            0x48A
+#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_1                 0x48B
+#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_2                 0x48C
+#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_3                 0x48D
+#define MYKONOS_ADDR_AGC_SLOW_LOOP_CFG                          0x48E
+#define MYKONOS_ADDR_AGC_SLOW_POWER_THRSH                       0x48F
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOCK_LEV_THRSH           0x490
+
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ULB_CNT_THRSH                0x491
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LLB_CNT_THRSH                0x492
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_HIGH_OVRG_CNT_THRSH      0x493
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_LOW_OVRG_CNT_THRSH       0x494
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_VERYLOW_OVRG_CNT_THRSH   0x495
+
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_DIG_SAT_CNT_THRSH        0x496
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER0_THRSH_GAIN_STEP   0x497
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER0_THRSH_GAIN_STEP   0x498
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER1_THRSH_GAIN_STEP   0x499
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER1_THRSH_GAIN_STEP   0x49A
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_1        0x49B
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_2        0x49C
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_3        0x49D
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOOP_CFG                 0x49E
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_POWER_THRSH              0x49F
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_1    0x4A0
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_2    0x4A1
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_1    0x4A2
+#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_2    0x4A3
+
+/* Mykonos Gain Control Read Registers */
+#define MYKONOS_ADDR_GAIN_CTL_CHANNEL_1                         0x4B0
+#define MYKONOS_ADDR_GAIN_CTL_FAST_ATTK_STATE                   0x4B1
+#define MYKONOS_ADDR_GAIN_CTL_SLOW_LOOP_STATE                   0x4B2
+#define MYKONOS_ADDR_GAIN_CTL_CHANNEL_2                         0x4B3
+#define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_1               0x4B4
+#define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_2               0x4B5
+#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_GAIN                     0x4B6
+#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_LOOP_STATE               0x4B7
+#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_OVRG_SIGS                0x4B8
+
+/* Mykonos Rx Data Path Overrange Registers */
+#define MYKONOS_ADDR_RX_OVRG_DATAPATH_OVRFLW                    0x4B9
+#define MYKONOS_ADDR_RX_OVRG_ORX_SNRX_DATAPATH_OVRFLW           0x4BA
+
+/* Mykonos RSSI Measurement Registers and Dec Power Measurement Registers*/
+#define MYKONOS_ADDR_RSSI_MEAS_DURATION_0_1                     0x4C0
+#define MYKONOS_ADDR_RSSI_MEAS_DURATION_2_3                     0x4C1
+#define MYKONOS_ADDR_RSSI_CFG                                   0x4C6
+#define MYKONOS_DEC_POWER_CONFIG_1                              0x4C7
+#define MYKONOS_DEC_POWER_CONFIG_2								0x4C8
+#define MYKONOS_ADDR_DPD_SNF_RSSI_CFG                           0x4CF
+#define MYKONOS_ADDR_DPD_RSSI_CFG                               0x4D6
+#define MYKONOS_SNIFFER_DEC_POWER_CONFIG_1						0x4D7
+#define MYKONOS_SNIFFER_DEC_POWER_CONFIG_2						0x4D8
+#define MYKONOS_CH1_DECIMATED_PWR								0x4DE
+#define MYKONOS_CH2_DECIMATED_PWR								0x4DF
+#define MYKONOS_SNIFFER_DECIMATED_PWR							0x4E6
+
+#define MYKONOS_ADDR_DIGITAL_GAIN_CONFIG                    0x4F0
+#define MYKONOS_ADDR_DPD_SNIFFER_DIGITAL_GAIN_CONFIG        0x4F1
+#define MYKONOS_ADDR_GAIN_TABLE_ADDR						0x500
+#define MYKONOS_ADDR_GAIN_TABLE_RX1_FE_GAIN					0x501
+#define MYKONOS_ADDR_GAIN_TABLE_RX1_EXT_CTL					0x502
+#define MYKONOS_ADDR_GAIN_TABLE_RX1_DIG_GAIN				0x503
+#define MYKONOS_ADDR_GAIN_TABLE_RX2_FE_GAIN					0x504
+#define MYKONOS_ADDR_GAIN_TABLE_RX2_EXT_CTL					0x505
+#define MYKONOS_ADDR_GAIN_TABLE_RX2_DIG_GAIN				0x506
+#define MYKONOS_ADDR_GAIN_TABLE_RX3_FE_GAIN					0x507
+#define MYKONOS_ADDR_GAIN_TABLE_RX3_LNA_ENAB				0x508
+#define MYKONOS_ADDR_GAIN_TABLE_RX3_DIG_GAIN				0x509
+#define MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION               0x516
+#define MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION           0x517
+#define MYKONOS_ADDR_RXFE1_LOCM                             0x520
+#define MYKONOS_ADDR_RXFE2_LOCM                             0x521
+#define MYKONOS_ADDR_RXLOOPBACK1_CNTRL_1                    0x540
+#define MYKONOS_ADDR_RXLOOPBACK2_CNTRL_1                    0x541
+#define MYKONOS_ADDR_RX_LOOPBACK1_CNTRL_4                   0x546
+#define MYKONOS_ADDR_RX_LOOPBACK2_CNTRL_4                   0x547
+
+/* Mykonos Overload/Peak Detection Registers */
+#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_CFG                    0x580
+#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_UPPER_THRSH            0x581
+#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_LOWER_THRSH            0x582
+
+#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_CFG                 0x583
+#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_UPPER_THRSH         0x584
+#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_LOWER_THRSH         0x585
+#define MYKONOS_ADDR_OVRLD_PD_DEC_VERYLOW_THRSH             0x586
+#define MYKONOS_ADDR_ORX_SNRX_OVRLD_ADC_OVRLD_CFG           0x587
+#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_CFG        0x58A
+#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_UPPER_THRSH    0x58B
+#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_LOWER_THRSH    0x58C
+#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_VERYLOW_THRSH  0x58D
+
+#define MYKONOS_ADDR_RX_ADC_FLASH_DELAY                     0x5B6
+#define MYKONOS_ADDR_RX_ADC_FLASH_CTRL                      0x5B7
+#define MYKONOS_ADDR_RX_ADC1_PRFL                           0x5DD
+#define MYKONOS_ADDR_RX_ADC2_PRFL                           0x5DE
+#define MYKONOS_ADDR_ORX_ADC_PRFL                           0x5DF
+
+#define MYKONOS_ADDR_RFDC_MEASURE_COUNT_1                   0x631
+#define MYKONOS_ADDR_RFDC_MEASURE_COUNT_2                   0x632
+#define MYKONOS_ADDR_RFDC_PROGRAM_SHIFT                     0x635
+#define MYKONOS_ADDR_RFDC_CONFIG2                           0x636
+#define MYKONOS_DPD_Sniffer_RFDC_CAL_TRACK_EN               0x642
+#define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_1               0x644
+#define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_2               0x645
+#define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_1               0x650
+#define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_2               0x651
+#define MYKONOS_ADDR_DIGITAL_DC_MIN_CAL_IDX                 0x63A
+#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SHIFT                0x674
+#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CONFIG               0x676
+#define MYKONOS_DIGITAL_DC_OFFSET_CH3_TRACKING              0x67A
+#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SNF                  0x67C
+#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CH3_DPD_M_SHIFT      0x67D
+
+#define MYKONOS_ADDR_RX_GAIN_COMP_DELAY                     0x710
+#define MYKONOS_ADDR_RX1_GAIN_COMP_OFFSET                   0x711
+#define MYKONOS_ADDR_RX2_GAIN_COMP_OFFSET                   0x712
+#define MYKONOS_ADDR_RX_GAIN_COMP_CFG                       0x713
+#define MYKONOS_ADDR_RX_SLCR_PIN_CFG                        0x714
+#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_DELAY             0x715
+#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_OFFSET            0x716
+#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_CFG               0x717
+#define MYKONOS_ADDR_DPD_SNF_RX_SLCR_PIN_CFG                0x718
+
+#define MYKONOS_ADDR_FLOATING_POINT_CFG                     0x750
+#define MYKONOS_ADDR_FLOATING_POINT_RX_CTRL                 0x751
+#define MYKONOS_ADDR_FLOATING_POINT_ORX_CTRL                0x752
+
+
+#define MYKONOS_ADDR_SNRX_LNA_BIAS_C                        0x81B
+
+
+#define MYKONOS_ADDR_ORX_ADC_FLASH_DELAY                     0x846
+#define MYKONOS_ADDR_ORX_ADC_FLASH_CTRL                      0x847
+
+#define MYKONOS_ADDR_TX_FILTER_CONFIGURATION                0x910
+#define MYKONOS_ADDR_TX1_ATTENUATION_0_READBACK             0x940
+#define MYKONOS_ADDR_TX1_ATTENUATION_1_READBACK             0x941
+#define MYKONOS_ADDR_TX2_ATTENUATION_0_READBACK             0x942
+#define MYKONOS_ADDR_TX2_ATTENUATION_1_READBACK             0x943
+#define MYKONOS_ADDR_TX_FILTER_OVERFLOW 					0x950
+
+/* Mykonos PA Protection Block Registers */
+#define MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION            0x955
+#define MYKONOS_ADDR_PA_PROTECTION_ATTEN_CONTROL            0x956
+#define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_LSB            0x957
+#define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_MSB            0x958
+#define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_LSB       0x959
+#define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_MSB       0x95A
+#define MYKONOS_ADDR_TX1_ATTENUATION_0                      0x960
+#define MYKONOS_ADDR_TX1_ATTENUATION_1                      0x961
+#define MYKONOS_ADDR_TX2_ATTENUATION_0                      0x962
+#define MYKONOS_ADDR_TX2_ATTENUATION_1                      0x963
+#define MYKONOS_ADDR_TX1_GAIN_0                             0x967
+#define MYKONOS_ADDR_TX1_GAIN_1                             0x968
+#define MYKONOS_ADDR_TX1_GAIN_2                             0x969
+#define MYKONOS_ADDR_TX2_GAIN_0                             0x96A
+#define MYKONOS_ADDR_TX2_GAIN_1                             0x96B
+#define MYKONOS_ADDR_TX2_GAIN_2                             0x96C
+#define MYKONOS_ADDR_TX_INCR_DECR_WORD                      0x96D
+#define MYKONOS_ADDR_TX_TPC_CONFIG                          0x96E
+#define MYKONOS_ADDR_TX_TPC_GPIO_CFG                        0x96F
+
+#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_MSB             0x9CB
+#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_LSB             0x9CC
+#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_MSB             0x9CD
+#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_LSB             0x9CE
+
+/* Mykonos GPIO Registers */
+#define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_7_0					0xB00
+#define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_15_8					0xB01
+#define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_7_0					0xB02
+#define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_15_8					0xB03
+#define MYKONOS_ADDR_GPIO_3V3_SPI_READ_7_0					0xB04
+#define MYKONOS_ADDR_GPIO_3V3_SPI_READ_15_8					0xB05
+#define MYKONOS_ADDR_GPIO_3V3_LSB_SRC_CTL					0xB06
+#define MYKONOS_ADDR_GPIO_3V3_MSB_SRC_CTL					0xB07
+
+#define MYKONOS_ADDR_GPIO_DIR_CTL_7_0					    0xB20
+#define MYKONOS_ADDR_GPIO_DIR_CTL_15_8					    0xB21
+#define MYKONOS_ADDR_GPIO_DIR_CTL_18_16					    0xB22
+#define MYKONOS_ADDR_GPIO_SPI_SRC_7_0					    0xB23
+#define MYKONOS_ADDR_GPIO_SPI_SRC_15_8					    0xB24
+#define MYKONOS_ADDR_GPIO_SPI_SRC_18_16					    0xB25
+#define MYKONOS_ADDR_GPIO_SPI_READ_7_0					    0xB26
+#define MYKONOS_ADDR_GPIO_SPI_READ_15_8					    0xB27
+#define MYKONOS_ADDR_GPIO_SPI_READ_18_16				    0xB28
+#define MYKONOS_ADDR_SOURCE_CONTROL_LOWER_BYTE              0xB29
+#define MYKONOS_ADDR_SOURCE_CONTROL_UPPER_BYTE              0xB2A
+#define MYKONOS_ADDR_SOURCE_CONTROL_EXTRA_BITS              0xB2B
+
+#define MYKONOS_ADDR_GPIO_MONITOR_INDEX                     0xB40
+#define MYKONOS_ADDR_GPIO_MONITOR_ENABLE                    0xB41
+
+#define MYKONOS_ADDR_GP_INTERRUPT_MASK_1                    0xB42
+#define MYKONOS_ADDR_GP_INTERRUPT_MASK_0                    0xB43
+#define MYKONOS_ADDR_GP_INTERRUPT_READ_1                    0xB44
+#define MYKONOS_ADDR_GP_INTERRUPT_READ_0                    0xB45
+
+#define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_5_0            0xB73
+#define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_9_6            0xB74
+#define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_5_0                 0xB75
+#define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_9_6                 0xB76
+#define MYKONOS_ADDR_AUX_DAC_LATCH_CONTROL                  0xB9F
+#define MYKONOS_ADDR_AUXDAC_0_WORD_MSB                      0xBA0
+
+#define MYKONOS_ADR_AUX_ADC_CLOCK_DIVIDE                    0xBC0
+#define MYKONOS_ADDR_AUX_ADC_CFG                            0xBC1
+#define MYKONOS_ADDR_AUX_ADC_READ_MSB                       0xBC2
+#define MYKONOS_ADDR_AUX_ADC_READ_LSB                       0xBC3
+#define MYKONOS_ADDR_AUX_ADC_SEL                            0xBC4
+#define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_0                0xBC5
+#define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_1                0xBC6
+
+#define MYKONOS_ADDR_TEMP_SENSOR_OFFSET                     0xBE0
+#define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB                0xBE1
+#define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_MSB                0xBE2
+#define MYKONOS_ADDR_TEMP_SENSOR_READ                       0xBE3
+#define MYKONOS_ADDR_TEMP_SENSOR_CONFIG                     0xBE4
+
+#define MYKONOS_ADDR_DIGITAL_TEST_BYTE_0                    0xC40
+
+/* ARM subsystem registers */
+#define MYKONOS_ADDR_ARM_CTL_1								0xD00
+#define MYKONOS_ADDR_ARM_CTL_2								0xD01
+#define MYKONOS_ADDR_ARM_ADDR_BYTE_0						0xD02
+#define MYKONOS_ADDR_ARM_ADDR_BYTE_1						0xD03
+#define MYKONOS_ADDR_ARM_DATA_BYTE_0						0xD04
+#define MYKONOS_ADDR_ARM_DATA_BYTE_1						0xD05
+#define MYKONOS_ADDR_ARM_DATA_BYTE_2						0xD06
+#define MYKONOS_ADDR_ARM_DATA_BYTE_3						0xD07
+#define MYKONOS_ADDR_ARM_CLK_CTL							0xD08
+#define MYKONOS_ADDR_AHB_SPI_BRIDGE							0xD09
+#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_0					0xD0A
+#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_1					0xD0B
+#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_2					0xD0C
+#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_3					0xD0D
+#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_0					0xD0E
+#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_1					0xD0F
+#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_2					0xD10
+#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_3					0xD11
+#define MYKONOS_ADDR_ARM_BRIDGE_CLK_CTL						0xD14
+
+/* ARM mailbox registers */
+#define MYKONOS_ADDR_ARM_CMD								0xD30
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_1						0xD31
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_2						0xD32
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_3						0xD33
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_4						0xD34
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_5						0xD35
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_6						0xD36
+#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_7						0xD37
+#define MYKONOS_ADDR_ARM_CMD_STATUS_0						0xD38
+#define MYKONOS_ADDR_ARM_CMD_STATUS_1						0xD39
+#define MYKONOS_ADDR_ARM_CMD_STATUS_2						0xD3A
+#define MYKONOS_ADDR_ARM_CMD_STATUS_3						0xD3B
+#define MYKONOS_ADDR_ARM_CMD_STATUS_4						0xD3C
+#define MYKONOS_ADDR_ARM_CMD_STATUS_5						0xD3D
+#define MYKONOS_ADDR_ARM_CMD_STATUS_6						0xD3E
+#define MYKONOS_ADDR_ARM_CMD_STATUS_7						0xD3F
+
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_0						0xD40
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_1						0xD41
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_2						0xD42
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_3						0xD43
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_4						0xD44
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_5						0xD45
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_6						0xD46
+#define MYKONOS_ADDR_ARM_OPCODE_STATE_7						0xD47
+
+/* Mykonos Power-Down Override Control Registers */
+#define MYKONOS_ADDR_TX_PD_OVERRIDE_CONTROL_7_0             0xD89
+
+/* Mykonos Observation Framer Registers */
+#define MYKONOS_ADDR_OBS_FRAMER_RESET						0xDC0
+#define MYKONOS_ADDR_OBS_FRAMER_CLK_EN						0xDC1
+#define MYKONOS_ADDR_OBS_FRAMER_ADDR						0xDC2
+#define MYKONOS_ADDR_OBS_FRAMER_DATA						0xDC3
+#define MYKONOS_ADDR_OBS_FRAMER_WRITE_EN					0xDC4
+#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN				0xDC5
+#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_F					0xDC6
+#define MYKONOS_ADDR_OBS_FRAMER_LANE_CTL					0xDC7
+#define MYKONOS_ADDR_OBS_FRAMER_ADC_XBAR_SEL				0xDC8
+#define MYKONOS_ADDR_OBS_FRAMER_LANE_XBAR_SEL				0xDC9
+#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_LOOPBACK_XBAR_REV	0xDCA
+#define MYKONOS_ADDR_OBS_FRAMER_SYNCN_FILT					0xDCB
+#define MYKONOS_ADDR_OBS_FRAMER_LMFC_F_OFFSET				0xDCC
+#define MYKONOS_ADDR_OBS_FRAMER_LMFC_K_OFFSET				0xDCD
+#define MYKONOS_ADDR_OBS_FRAMER_TEST_CNTR_CTL				0xDCE
+#define MYKONOS_ADDR_OBS_FRAMER_STATUS_STRB					0xDCF
+#define MYKONOS_ADDR_OBS_FRAMER_STATUS						0xDD0
+#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_CNTR_STAT	0xDD1
+#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN	0xDD2
+#define MYKONOS_ADDR_OBS_FRAMER_LANE_FIFO_STRB				0xDD3
+#define MYKONOS_ADDR_OBS_FRAMER_LANE0_FIFO_RDWR_ADDR		0xDD4
+#define MYKONOS_ADDR_OBS_FRAMER_LANE1_FIFO_RDWR_ADDR		0xDD5
+#define MYKONOS_ADDR_OBS_FRAMER_LANE2_FIFO_RDWR_ADDR		0xDD6
+#define MYKONOS_ADDR_OBS_FRAMER_LANE3_FIFO_RDWR_ADDR		0xDD7
+#define MYKONOS_ADDR_OBS_FRAMER_PRBS10_CTL					0xDD8
+#define MYKONOS_ADDR_OBS_FRAMER_PRBS20_CTL					0xDD9
+#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_EN				0xDDA
+#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_7_TO_0			0xDDB
+#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_15_TO_8			0xDDC
+#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_19_TO_16		0xDDD
+#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_JTX_GEN				0xDDE
+#define MYKONOS_ADDR_OBS_FRAMER_LANE_DATA_CTL				0xDDF
+#define MYKONOS_ADDR_OBS_FRAMER_DATA_SAMPLE_CTL				0xDE0
+
+#define MYKONOS_ADDR_PFIR_COEFF_CTL                         0xDFF
+#define MYKONOS_ADDR_PFIR_COEFF_DATA                        0xE00
+#define MYKONOS_ADDR_PFIR_COEFF_ADDR                        0xE01
+
+/* ARM memory */
+#define MYKONOS_ADDR_ARM_START_PROG_ADDR					0x01000000
+#define MYKONOS_ADDR_ARM_END_PROG_ADDR						0x01017FFF
+#define MYKONOS_ADDR_ARM_START_DATA_ADDR					0x20000000
+#define MYKONOS_ADDR_ARM_END_DATA_ADDR						0x2000FFFF
+#define MYKONOS_ADDR_ARM_BUILD_CHKSUM_ADDR					0x01017FE0
+#define MYKONOS_ADDR_ARM_CALC_CHKSUM_ADDR					0x01017FE4
+#define MYKONOS_ADDR_ARM_VERSION                            0x01000128
+#define MYKONOS_ARM_ABORT_OPCODE                            0x00
+#define MYKONOS_ARM_RUNINIT_OPCODE                          0x02
+#define MYKONOS_ARM_RADIOON_OPCODE                          0x04
+#define MYKONOS_ARM_WRITECFG_OPCODE                         0x06
+#define MYKONOS_ARM_READCFG_OPCODE                          0x08
+#define MYKONOS_ARM_SET_OPCODE                              0x0A
+#define MYKONOS_ARM_GET_OPCODE                              0x0C
+
+#define MYKONOS_ARM_OBJECTID_DPDINIT_CONFIG                 0x0F
+#define MYKONOS_ARM_OBJECTID_CLGCINIT_CONFIG                0x10
+#define MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG                0x11
+#define MYKONOS_ARM_OBJECTID_DPDCONFIG                      0x24
+#define MYKONOS_ARM_DPD_RESET                               0x02
+#define MYKONOS_ARM_OBJECTID_GS_TRACKCALS                   0x66
+#define MYKONOS_ARM_OBJECTID_RXQEC_TRACKING                 0x20
+#define MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING                0x21
+#define MYKONOS_ARM_OBJECTID_TXLOL_TRACKING                 0x22
+#define MYKONOS_ARM_OBJECTID_TXQEC_TRACKING                 0x23
+#define MYKONOS_ARM_OBJECTID_CLGCCONFIG                     0x25
+#define MYKONOS_ARM_OBJECTID_VSWRCONFIG                     0x26
+#define MYKONOS_ARM_OBJECTID_CAL_STATUS                     0x42
+#define MYKONOS_ARM_OBJECTID_INIT_CAL_DONE                  0x43
+#define MYKONOS_ARM_OBJECTID_ORX_MODE                       0x61
+#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_SUSPEND_RESUME    0x65
+#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_CONTROL           0x66
+#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_PENDING           0x67
+#define MYKONOS_ARM_OBJECTID_RADIO_CONTROL                  0x81
+#define MYKONOS_ARM_OBJECTID_CALSCHEDULER                   0x83
+
+#define MYKONOS_ARM_SYSTEMSTATE_POWERUP                     0x00
+#define MYKONOS_ARM_SYSTEMSTATE_READY                       0x01
+#define MYKONOS_ARM_SYSTEMSTATE_IDLE                        0x02
+#define MYKONOS_ARM_SYSTEMSTATE_RADIO_ON                    0x03
+
+#define ORX_TRIGGER_SIGNALID      0x00
+#define ORX_MODE_0_SIGNALID       0x01
+#define ORX_MODE_1_SIGNALID       0x02
+#define ORX_MODE_2_SIGNALID       0x03
+#define RX1_ENABLE_ACK_SIGNALID   0x04
+#define RX2_ENABLE_ACK_SIGNALID   0x05
+#define TX1_ENABLE_ACK_SIGNALID   0x06
+#define TX2_ENABLE_ACK_SIGNALID   0x07
+#define ORX1_ENABLE_ACK_SIGNALID  0x08
+#define ORX2_ENABLE_ACK_SIGNALID  0x09
+#define SRX_ENABLE_ACK_SIGNALID   0x0A
+#define TX_OBS_SELECT_SIGNALID    0x0B
+
+#define DISABLE_DPD_ACTUATOR      0x03
+#define ENABLE_DPD_ACTUATOR       0x04
+#define SET_CLGC_DESIRED_GAIN_1   0x05
+#define SET_CLGC_DESIRED_GAIN_2   0x06
+#define SET_PATH_DELAY            0x08
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

df_datalink_ge/src/hardware/mykonos/mykonos_user.c

@@ -0,0 +1,176 @@
+/**
+ * \file mykonos_user.c
+ * \brief Contains Mykonos default gain table values for Rx, ObsRx, and SnRx
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#include <stdint.h>
+#include "t_mykonos.h"
+#include "mykonos_user.h"
+
+/**
+ * \brief Default Rx gain table settings
+ */
+uint8_t RxGainTable [61][4] =
+{
+	/* Order: {FE table, External Ctl, Digital Gain/Atten, Enable Atten} */
+        {0, 0, 0, 0},  /* Gain index 255 */
+        {3, 0, 2, 1},  /* Gain index 254 */
+        {6, 0, 3, 1},  /* Gain index 253 */
+        {10, 0, 0, 0}, /* Gain index 252 */
+        {13, 0, 1, 1}, /* Gain index 251 */
+        {16, 0, 0, 0}, /* Gain index 250 */
+        {18, 0, 3, 1}, /* Gain index 249 */
+        {21, 0, 1, 1}, /* Gain index 248 */
+        {23, 0, 3, 1}, /* Gain index 247 */
+        {25, 0, 4, 1}, /* Gain index 246 */
+        {28, 0, 0, 0}, /* Gain index 245 */
+        {30, 0, 0, 0}, /* Gain index 244 */
+        {31, 0, 5, 1}, /* Gain index 243 */
+        {33, 0, 4, 1}, /* Gain index 242 */
+        {35, 0, 2, 1}, /* Gain index 241 */
+        {37, 0, 0, 0}, /* Gain index 240 */
+        {38, 0, 4, 1}, /* Gain index 239 */
+        {39, 0, 7, 1}, /* Gain index 238 */
+        {41, 0, 2, 1}, /* Gain index 237 */
+        {42, 0, 4, 1}, /* Gain index 236 */
+        {43, 0, 6, 1}, /* Gain index 235 */
+        {44, 0, 8, 1}, /* Gain index 234 */
+        {45, 0, 9, 1},  /* Gain index 233 */
+        {46, 0, 10, 1}, /* Gain index 232 */
+        {47, 0, 10, 1}, /* Gain index 231 */
+        {48, 0, 9, 1}, /* Gain index 230 */
+        {49, 0, 8, 1}, /* Gain index 229 */
+        {50, 0, 6, 1}, /* Gain index 228 */
+        {51, 0, 3, 1}, /* Gain index 227 */
+        {51, 0, 13, 1}, /* Gain index 226 */
+        {52, 0, 9, 1}, /* Gain index 225 */
+        {53, 0, 5, 1}, /* Gain index 224 */
+        {53, 0, 15, 1}, /* Gain index 223 */
+        {54, 0, 9, 1}, /* Gain index 222 */
+        {54, 0, 19, 1}, /* Gain index 221 */
+        {55, 0, 11, 1}, /* Gain index 220 */
+        {55, 0, 21, 1}, /* Gain index 219 */
+        {56, 0, 11, 1}, /* Gain index 218 */
+        {56, 0, 21, 1}, /* Gain index 217 */
+        {57, 0, 9, 1}, /* Gain index 216 */
+        {57, 0, 19, 1}, /* Gain index 215 */
+        {57, 0, 29, 1}, /* Gain index 214 */
+        {58, 0, 12, 1}, /* Gain index 213 */
+        {58, 0, 22, 1}, /* Gain index 212 */
+        {58, 0, 32, 1}, /* Gain index 211 */
+        {59, 0, 11, 1}, /* Gain index 210 */
+        {59, 0, 21, 1}, /* Gain index 209 */
+        {59, 0, 31, 1}, /* Gain index 208 */
+        {59, 0, 41, 1}, /* Gain index 207 */
+        {60, 0, 13, 1}, /* Gain index 206 */
+        {60, 0, 23, 1}, /* Gain index 205 */
+        {60, 0, 33, 1}, /* Gain index 204 */
+        {60, 0, 43, 1}, /* Gain index 203 */
+        {60, 0, 53, 1}, /* Gain index 202 */
+        {61, 0, 14, 1}, /* Gain index 201 */
+        {61, 0, 24, 1}, /* Gain index 200 */
+        {61, 0, 34, 1}, /* Gain index 199 */
+        {61, 0, 44, 1}, /* Gain index 198 */
+        {61, 0, 54, 1}, /* Gain index 197 */
+        {61, 0, 64, 1}, /* Gain index 196 */
+        {61, 0, 74, 1}, /* Gain index 195 */
+};
+
+/**
+ * \brief Default ORx gain table settings
+ */
+uint8_t ORxGainTable [19][4] =
+{
+	/* Order: {FE table, External Ctl, Digital Gain/Atten, Enable Atten} */
+	{0, 0, 0, 0},	/* Gain index 255 */
+	{7, 0, 0, 0},	/* Gain index 254 */
+	{13, 0, 1, 1},	/* Gain index 253 */
+	{18, 0, 3, 1},	/* Gain index 252 */
+	{23, 0, 3, 1},	/* Gain index 251 */
+	{28, 0, 0, 0},	/* Gain index 250 */
+	{32, 0, 0, 0},	/* Gain index 249 */
+	{35, 0, 2, 1},	/* Gain index 248 */
+	{38, 0, 4, 1},	/* Gain index 247 */
+	{41, 0, 2, 1},	/* Gain index 246 */
+	{43, 0, 6, 1},	/* Gain index 245 */
+	{46, 0, 0, 0},	/* Gain index 244 */
+	{47, 0, 10, 1},	/* Gain index 243 */
+	{49, 0, 8, 1},	/* Gain index 242 */
+	{51, 0, 3, 1},	/* Gain index 241 */
+	{52, 0, 9, 1},	/* Gain index 240 */
+	{53, 0, 14, 1},	/* Gain index 239 */
+	{54, 0, 18, 1},	/* Gain index 238 */
+	{56, 0, 0, 0}	/* Gain index 237 */
+
+};
+
+/**
+ * \brief Default SnRx gain table settings
+ */
+uint8_t SnRxGainTable [53][4] =
+{
+	/* Order: {FE table, LNA Bypass, Digital Gain/Atten, Enable Atten} */
+    {0,  0,  0, 0},  /* Gain index 255 */
+    {1,  0,  7, 1},  /* Gain index 254 */
+    {3,  0,  1, 0},  /* Gain index 253 */
+    {3,  0, 15, 1}, /* Gain index 252 */
+    {5,  0,  0, 0},  /* Gain index 251 */
+    {6,  0,  2, 1},  /* Gain index 250 */
+    {7,  0,  2, 1},  /* Gain index 249 */
+    {8,  0, 12, 1}, /* Gain index 248 */
+    {9,  0,  7, 1},  /* Gain index 247 */
+    {11, 0,  1, 0}, /* Gain index 246 */
+    {11, 0, 15, 1},/* Gain index 245 */
+    {13, 0,  1, 0}, /* Gain index 244 */
+    {14, 0,  2, 0}, /* Gain index 243 */
+    {14, 0, 10, 1},/* Gain index 242 */
+    {15, 0,  0, 0}, /* Gain index 241 */
+    {15, 0, 20, 1},/* Gain index 240 */
+    {16, 0,  2, 1}, /* Gain index 239 */
+    {16, 0, 22, 1},/* Gain index 238 */
+    {17, 0,  1, 0}, /* Gain index 237 */
+    {17, 0, 15, 1},/* Gain index 236 */
+    {17, 0, 35, 1},/* Gain index 235 */
+    {17, 0, 55, 1},/* Gain index 234 */
+    {18, 0,  7, 1}, /* Gain index 233 */
+    {18, 0, 27, 1},/* Gain index 232 */
+    { 6, 1,  7, 1},  /* Gain index 231 */
+    { 7, 1,  7, 1},  /* Gain index 230 */
+    { 8, 1, 17, 1}, /* Gain index 229 */
+    { 9, 1, 12, 1}, /* Gain index 228 */
+    {11, 1,  0, 0}, /* Gain index 227 */
+    {12, 1,  3, 1}, /* Gain index 226 */
+    {13, 1,  0, 0}, /* Gain index 225 */
+    {14, 1,  1, 0}, /* Gain index 224 */
+    {14, 1, 15, 1},/* Gain index 223 */
+    {15, 1,  5, 1}, /* Gain index 222 */
+    {15, 1, 25, 1},/* Gain index 221 */
+    {16, 1,  7, 1}, /* Gain index 220 */
+    {16, 1, 27, 1},/* Gain index 219 */
+    {17, 1,  0, 0}, /* Gain index 218 */
+    {17, 1, 20, 1},/* Gain index 217 */
+    {17, 1, 40, 1},/* Gain index 216 */
+    {17, 1, 60, 1},/* Gain index 215 */
+    {18, 1, 12, 1},/* Gain index 214 */
+    {18, 1, 32, 1},/* Gain index 213 */
+    {18, 1, 52, 1},/* Gain index 212 */
+    {18, 1, 72, 1},/* Gain index 211 */
+    {18, 1, 92, 1},/* Gain index 210 */
+    {19, 1,  1, 0}, /* Gain index 209 */
+    {19, 1, 15, 1},/* Gain index 208 */
+    {19, 1, 35, 1},/* Gain index 207 */
+    {19, 1, 55, 1},/* Gain index 206 */
+    {19, 1, 75, 1},/* Gain index 205 */
+    {19, 1, 95, 1},/* Gain index 204 */
+    {19, 1, 115, 1}/* Gain index 203 */
+};
+

df_datalink_ge/src/hardware/mykonos/mykonos_user.h

@@ -0,0 +1,85 @@
+/**
+ * \file mykonos_user.h
+ *
+ * \brief Contains macro definitions and global structure declarations for mykonos_user.c
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef _MYKONOSPROFILES_H_
+#define _MYKONOSPROFILES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* turns verbose messaging on */
+#define MYKONOS_VERBOSE 1
+#define MYK_ENABLE_SPIWRITEARRAY 1
+
+/* 3 Bytes per SPI transaction * 341 transactions = ~1024 byte buffer size */
+/* Minimum MYK_SPIWRITEARRAY_BUFFERSIZE = 27 */
+#define MYK_SPIWRITEARRAY_BUFFERSIZE 341
+/*
+ *****************************************
+ * Rx, ObsRx, and Sniffer gain tables
+ ******************************************
+ */
+#define MAX_GAIN_TABLE_INDEX			255
+
+#define START_RX_GAIN_INDEX 			255
+#define MAX_RX_GAIN_TABLE_NUMINDEXES	(START_RX_GAIN_INDEX + 1)
+#define MIN_RX_GAIN_TABLE_INDEX			0
+
+#define START_ORX_GAIN_INDEX 			47
+#define MAX_ORX_GAIN_TABLE_NUMINDEXES  	(START_ORX_GAIN_INDEX + 1)
+#define MIN_ORX_GAIN_TABLE_INDEX		(MAX_GAIN_TABLE_INDEX - START_ORX_GAIN_INDEX)
+
+#define START_SNRX_GAIN_INDEX 			127
+#define MAX_SNRX_GAIN_TABLE_NUMINDEXES	(START_SNRX_GAIN_INDEX + 1)
+#define MIN_SNRX_GAIN_TABLE_INDEX		(MAX_GAIN_TABLE_INDEX - START_SNRX_GAIN_INDEX)
+
+#define START_LOOPBACK_GAIN_INDEX           47
+#define MAX_LOOPBACK_GAIN_TABLE_NUMINDEXES  (START_LOOPBACK_GAIN_INDEX + 1)
+#define MIN_LOOPBACK_GAIN_TABLE_INDEX       (MAX_GAIN_TABLE_INDEX - START_SNRX_GAIN_INDEX)
+
+extern uint8_t RxGainTable [61][4];
+extern uint8_t ORxGainTable [19][4];
+extern uint8_t SnRxGainTable [53][4];
+
+
+/*
+ ********************************************
+ * Rx, Sniffer, ObsRx and Tx Profiles limits
+ ********************************************
+ */
+#define MIN_RX_IQRATE_KHZ   15000       /*!< Mykonos minimum IQ rate for the Rx channel, expressed in KHz */
+#define MAX_RX_IQRATE_KHZ   320000      /*!< Mykonos maximum IQ rate for the Rx channel, expressed in KHz */
+
+#define MIN_TX_IQRATE_KHZ   15000       /*!< Mykonos minimum IQ rate for the Tx channel, expressed in KHz */
+#define MAX_TX_IQRATE_KHZ   492000      /*!< Mykonos maximum IQ rate for the Tx channel, expressed in KHz */
+
+#define MIN_SNIFFER_RFBW_HZ 5000000     /*!< Mykonos minimum Sniffer channel bandwidth expressed in Hz */
+#define MAX_SNIFFER_RFBW_HZ 20000000    /*!< Mykonos maximum Sniffer channel bandwidth expressed in Hz */
+
+#define MIN_ORX_RFBW_HZ     5000000     /*!< Mykonos minimum Observation channel bandwidth expressed in Hz */
+#define MAX_ORX_RFBW_HZ     250000000   /*!< Mykonos maximum Observation channel bandwidth expressed in Hz */
+
+#define MIN_RX_RFBW_HZ      5000000     /*!< Mykonos minimum Rx channel bandwidth expressed in Hz */
+#define MAX_RX_RFBW_HZ      100000000   /*!< Mykonos maximum Rx channel bandwidth expressed in Hz */
+
+#define MIN_TX_RFBW_HZ      20000000    /*!< Mykonos minimum Tx channel bandwidth expressed in Hz */
+#define MAX_TX_RFBW_HZ      250000000   /*!< Mykonos maximum Tx channel bandwidth expressed in Hz */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

df_datalink_ge/src/hardware/mykonos/mykonos_version.h

@@ -0,0 +1,31 @@
+/**
+ * \file mykonos_version.h
+ * \brief Contains the version number for the Mykonos API
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in * this zip file.
+*
+*/
+
+#ifndef MYKONOS_VERSION_H_
+#define MYKONOS_VERSION_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MYKONOS_CURRENT_SI_VERSION 1    		/*!< Mykonos current silicon version */
+#define MYKONOS_CURRENT_MAJOR_VERSION 5			/*!< Mykonos current ARM major version */
+#define MYKONOS_CURRENT_MINOR_VERSION 2			/*!< Mykonos current ARM minor version */
+#define MYKONOS_CURRENT_BUILD_VERSION 3566		/*!< Mykonos current API build version */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MYKONOS_VERSION_H_ */

df_datalink_ge/src/hardware/mykonos/t_ad9528.h

@@ -0,0 +1,194 @@
+/**
+ * \file t_ad9528.h
+ * \brief Contains enum and structure data types for all AD9528 function calls
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef _AD9528_TYPES_H_
+#define _AD9528_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "../common.h"
+
+/* AD9528 SPI Address defines */
+#define AD9528_ADDR_ADI_SPI_CONFIG_A  0x000
+#define AD9528_ADDR_ADI_SPI_CONFIG_B  0x001
+#define AD9528_ADDR_IO_UPDATE         0x00F
+
+#define AD9528_ADDR_REF_A_DIVIDER_LSB 0x100
+#define AD9528_ADDR_REF_A_DIVIDER_MSB 0x101
+#define AD9528_ADDR_REF_B_DIVIDER_LSB 0x102
+#define AD9528_ADDR_REF_B_DIVIDER_MSB 0x103
+#define AD9528_ADDR_PLL1_N_DIV_LSB    0x104
+#define AD9528_ADDR_PLL1_N_DIV_MSB    0x105
+#define AD9528_ADDR_PLL1_CHARGEPUMP   0x106
+#define AD9528_ADDR_PLL1_CP_CTRL2     0x107
+#define AD9528_ADDR_INPUT_RECEIVERS1  0x108
+#define AD9528_ADDR_INPUT_RECEIVERS2  0x109
+#define AD9528_ADDR_INPUT_RECEIVERS3  0x10A
+#define AD9528_ADDR_PLL1_FASTLOCK     0x10B
+
+#define AD9528_ADDR_PLL2_CHARGEPUMP        0x200
+#define AD9528_ADDR_PLL2_N_DIV             0x201
+#define AD9528_ADDR_PLL2_CTRL              0x202
+#define AD9528_ADDR_PLL2_VCO_CTRL          0x203
+#define AD9528_ADDR_PLL2_VCO_DIV           0x204
+#define AD9528_ADDR_PLL2_LF_CTRL1          0x205
+#define AD9528_ADDR_PLL2_LF_CTRL2          0x206
+#define AD9528_ADDR_PLL2_RDIV              0x207
+#define AD9528_ADDR_PLL2_REPLICA_CHDIV     0x208
+#define AD9528_ADDR_PLL2_REPLICA_DIV_PHASE 0x209
+
+#define AD9528_ADDR_CH_OUT0_CTRL1       0x300
+#define AD9528_ADDR_CH_OUT0_CTRL2       0x301
+#define AD9528_ADDR_CH_OUT0_CHDIV       0x302
+#define AD9528_ADDR_OUTPUT_SYNC         0x32A
+#define AD9528_ADDR_MASK_SYNC1          0x32B
+#define AD9528_ADDR_MASK_SYNC2          0x32C
+#define AD9528_ADDR_EN_OUTPUT_PATH_SEL1 0x32D
+#define AD9528_ADDR_EN_OUTPUT_PATH_SEL2 0x32E
+
+#define AD9528_ADDR_SYSERF_DIV_LSB      0x400
+#define AD9528_ADDR_SYSERF_DIV_MSB      0x401
+#define AD9528_ADDR_SYSREF_CTRL3        0x402
+#define AD9528_ADDR_SYSREF_CTRL4        0x403
+#define AD9528_ADDR_SYSREF_CTRL5        0x404
+
+#define AD9528_ADDR_POWERDOWN_CTRL      0x500
+#define AD9528_ADDR_CH_POWERDOWN1       0x501
+#define AD9528_ADDR_CH_POWERDOWN2       0x502
+#define AD9528_ADDR_LDO_ENABLES1        0x503
+#define AD9528_ADDR_LDO_ENABLES2        0x504
+#define AD9528_ADDR_STATUS0_CTRL        0x505
+#define AD9528_ADDR_STATUS1_CTRL        0x506
+#define AD9528_ADDR_STATUS_OE           0x507
+#define AD9528_ADDR_STATUS_READBACK0    0x508
+#define AD9528_ADDR_STATUS_READBACK1    0x509
+
+
+
+///Enum to select what source outputs from each AD9528 output channel
+typedef enum
+{
+    CHANNEL_DIV = 0, PLL1_OUTPUT = 1, //VCXO frequency
+    SYSREF = 2,
+    INV_PLL1_OUTPUT = 5 //VCXO inverted
+} ad9528outSourceSel_t;
+
+///Enum to select what output buffer standard is used for the clock outputs
+typedef enum
+{
+    LVDS = 0, LVDS_BOOST = 1, HSTL = 2
+} ad9528outBufferControl_t;
+
+///Enum to select the clock input buffer mode.
+typedef enum
+{
+    DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
+} ad9528RefBuffer_t;
+
+/// Structure to hold AD9528 PLL1 settings
+typedef struct
+{
+    uint32_t refA_Frequency_Hz;
+    uint16_t refA_Divider;
+    ad9528RefBuffer_t refA_bufferCtrl;
+
+    uint32_t refB_Frequency_Hz;
+    uint16_t refB_Divider;
+    ad9528RefBuffer_t refB_bufferCtrl;
+
+    uint32_t vcxo_Frequency_Hz;
+    ad9528RefBuffer_t vcxoBufferCtrl;
+
+    uint16_t nDivider;
+    uint8_t bypassPll1;
+} ad9528pll1Settings_t;
+
+/// Structure to hold AD9528 PLL2 settings
+typedef struct
+{
+    uint8_t rfDivider; //VCO divider: Valid range (3,4,5)
+    uint8_t n2Divider; //PLL2 N2 Divider
+    uint8_t totalNdiv; //NDiv = 4*Bdiv + Adiv //Bdiv valid range (3 to 63), Adiv valid range (0-3)
+} ad9528pll2Settings_t;
+
+/// Structure to hold AD9528 Output Clock settings
+typedef struct
+{
+    uint16_t outPowerDown; //bit per output, if 1 power down that output.
+    ad9528outSourceSel_t outSource[14]; //CHANNEL_DIV, PLL1_OUTPUT, SYSREF, INV_PLL1_OUTPUT
+    ad9528outBufferControl_t outBufferCtrl[14]; //LVDS, LVDS_BOOST, HSTL
+    uint8_t outAnalogDelay[14]; //5 bits
+    uint8_t outDigitalDelay[14]; //6 bits, 1/2 clock resolution @ channel div input frequency
+    uint8_t outChannelDiv[14]; //8 bit channel divider
+    uint32_t outFrequency_Hz[14]; //output clock frequency per clock output
+} ad9528outputSettings_t;
+
+///Enum to select the SYSREF output source
+typedef enum
+{
+    EXTERNAL = 0, EXT_RESAMPLED = 1, INTERNAL = 2
+} sysrefSourceSelection_t;
+
+///Enum to choose the SYSREF pattern mode.
+typedef enum
+{
+    NSHOT = 0, CONTINUOUS = 1, PRBS = 2, STOP = 3
+} sysrefPatternMode_t;
+
+///Enum to select the SYSREF input pin mode.
+typedef enum
+{
+    LEVEL_ACTIVE_HIGH = 0, LEVEL_ACTIVE_LOW = 1, RISING_EDGE = 2, FALLING_EDGE = 3
+} sysrefPinEdgeMode_t;
+
+///Enum to select the SYSREF output # of pulses for NSHOT mode.
+typedef enum
+{
+    ONE_PULSE = 0, TWO_PULSES = 2, FOUR_PULSES = 3, SIX_PULSES = 4, EIGHT_PULSES = 5
+} sysrefNshotMode_t;
+
+//Enum to select how a SYSREF is requested.
+typedef enum
+{
+    SPI = 0, PIN = 1
+} sysrefRequestMethod_t;
+
+/// Structure to hold AD9528 SYSREF output settings
+typedef struct
+{
+    sysrefRequestMethod_t sysrefRequestMethod;
+    sysrefSourceSelection_t sysrefSource;
+    sysrefPinEdgeMode_t sysrefPinEdgeMode;
+    ad9528RefBuffer_t sysrefPinBufferMode;
+    sysrefPatternMode_t sysrefPatternMode;
+    sysrefNshotMode_t sysrefNshotMode;
+    uint16_t sysrefDivide;
+
+} ad9528sysrefSettings_t;
+
+/// Structure to hold AD9528 settings
+typedef struct
+{
+    spiSettings_t *spiSettings;
+    ad9528pll1Settings_t *pll1Settings;
+    ad9528pll2Settings_t *pll2Settings;
+    ad9528outputSettings_t *outputSettings;
+    ad9528sysrefSettings_t *sysrefSettings;
+} ad9528Device_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

df_datalink_ge/src/hardware/mykonos/t_mykonos_gpio.h

@@ -0,0 +1,375 @@
+/*!
+ * \file t_mykonos_gpio.h
+ * \brief Mykonos GPIO error handling and type defines
+ *
+ * Mykonos API version: 1.5.2.3566
+ */
+
+/**
+* \page Disclaimer Legal Disclaimer
+* Copyright 2015-2017 Analog Devices Inc.
+* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
+*
+*/
+
+#ifndef T_MYKONOSGPIO_H_
+#define T_MYKONOSGPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include "../common.h"
+
+/**
+ *  \brief Enum of unique error codes from the Mykonos GPIO API functions.
+ * Each error condition in the library should get its own enum value to allow
+ * easy debug of errors.
+ */
+typedef enum
+{
+	MYKONOS_ERR_GPIO_OK = 0,
+	MYKONOS_ERR_EN_MONITOR_OUT_NOT_ENABLED,
+    MYKONOS_ERR_EN_MONITOR_OUT_SRC_CTRL,
+    MYKONOS_ERR_MONITOR_OUT_INDEX_RANGE,
+    MYKONOS_ERR_GETGPIOMON_INDEX_NULL_PARM,
+    MYKONOS_ERR_GETGPIOMON_MONITORMASK_NULL_PARM,
+
+    MYKONOS_ERR_MGCRX2_GPIO_DECPIN_INV_PARAM,
+    MYKONOS_ERR_MGCRX2_GPIO_INCPIN_INV_PARAM,
+    MYKONOS_ERR_MGCRX2_SOURCE_CONFIG,
+    MYKONOS_ERR_MGCRX2_STEP_INV_PARAM,
+    MYKONOS_ERR_MGCRX1_GPIO_DECPIN_INV_PARAM,
+    MYKONOS_ERR_MGCRX1_GPIO_INCPIN_INV_PARAM,
+    MYKONOS_ERR_MGCRX1_STEP_INV_PARAM,
+    MYKONOS_ERR_GETRX2PIN_INCSTEP_NULL_PARM,
+    MYKONOS_ERR_GETRX2PIN_DECSTEP_NULL_PARM,
+    MYKONOS_ERR_GETRX2PIN_INCPIN_NULL_PARM,
+    MYKONOS_ERR_GETRX2PIN_DECPIN_NULL_PARM,
+    MYKONOS_ERR_GETRX2PIN_EN_NULL_PARM,
+    MYKONOS_ERR_GETRX1PIN_INCSTEP_NULL_PARM,
+    MYKONOS_ERR_GETRX1PIN_DECSTEP_NULL_PARM,
+    MYKONOS_ERR_GETRX1PIN_INCPIN_NULL_PARM,
+    MYKONOS_ERR_GETRX1PIN_DECPIN_NULL_PARM,
+    MYKONOS_ERR_GETRX1PIN_EN_NULL_PARM,
+
+    MYKONOS_ERR_TPCTX2_GPIO_DECPIN_INV_PARAM,
+    MYKONOS_ERR_TPCTX2_GPIO_INCPIN_INV_PARAM,
+    MYKONOS_ERR_TPCTX2_GPIO_STEP_INV_PARAM,
+    MYKONOS_ERR_TPCTX1_GPIO_DECPIN_INV_PARAM,
+    MYKONOS_ERR_TPCTX1_GPIO_INCPIN_INV_PARAM,
+    MYKONOS_ERR_TPCTX1_GPIO_STEP_INV_PARAM,
+    MYKONOS_ERR_GETTX2PIN_STEP_NULL_PARM,
+    MYKONOS_ERR_GETTX2PIN_INC_NULL_PARM,
+    MYKONOS_ERR_GETTX2PIN_DEC_NULL_PARM,
+    MYKONOS_ERR_GETTX2PIN_EN_NULL_PARM,
+    MYKONOS_ERR_GETTX2PIN_TX1TX2_NULL_PARM,
+    MYKONOS_ERR_GETTX1PIN_STEP_NULL_PARM,
+    MYKONOS_ERR_GETTX1PIN_INC_NULL_PARM,
+    MYKONOS_ERR_GETTX1PIN_DEC_NULL_PARM,
+    MYKONOS_ERR_GETTX1PIN_EN_NULL_PARM,
+    MYKONOS_ERR_GETTX1PIN_TX1TX2_NULL_PARM,
+
+	MYKONOS_ERR_SPI2_INV_GPIO,
+	MYKONOS_ERR_SPI2_INV_SETUP,
+
+	MYKONOS_ERR_SET_GPIO_1V8_INV_POINTER,
+
+	MYKONOS_ERR_GETGPIOSETLEVEL_NULL_PARM,
+	MYKONOS_ERR_READGPIOSPI_NULL_PARM,
+    MYKONOS_ERR_SET_GPIO_1V8_INV_MODE,
+    MYKONOS_ERR_GETGPIO_OE_NULL_PARM,
+    MYKONOS_ERR_GPIO_OE_INV_PARAM,
+    MYKONOS_ERR_GPIO_SRC_PARAM_INV,
+    MYKONOS_ERR_GET_GPIO_SOURCE_CONTROL_NULL_PARM,
+
+    MYKONOS_ERR_INV_GP_INT_MASK_PARM,
+    MYKONOS_ERR_GP_INT_STATUS_NULL_PARAM,
+
+    MYKONOS_ERR_GETGPIO3V3OUT_NULL_PARM,
+    MYKONOS_ERR_SET_GPIO_3V3_INV_POINTER,
+    MYKONOS_ERR_GETGPIO3V3SPI_NULL_PARM,
+    MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM,
+    MYKONOS_ERR_SET_GPIO_3V3_INV_MODE,
+    MYKONOS_ERR_SET_GPIO_3V3_INV_SRC_CTRL,
+
+    MYKONOS_ERR_SET_ARMGPIO_INV_POINTER,
+    MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR,
+    MYKONOS_ERR_SET_ARMGPIO_PINS_INV_SIGNALID,
+    MYKONOS_ERR_SET_ARMGPIO_PINS_INV_GPIOPIN,
+
+    MYKONOS_ERR_SETUPAUXDAC_NULL_PARAM,
+    MYKONOS_ERR_WRITEAUXDAC_NULL_AUXIO,
+    MYKONOS_ERR_READAUXADC_NULL_PARAM,
+    MYKONOS_ERR_SETUPAUXDAC_INV_AUXDACCODE,
+    MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACCODE,
+    MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACINDEX,
+    MYKONOS_ERR_INV_AUX_ADC_CHAN_PARM,
+    MYKONOS_ERR_SETUPAUXADC_INV_VCODIV,
+    MYKONOS_ERR_INV_AUX_ADC_DEC_PARM,
+
+    MYKONOS_ERR_GAINCOMP_NULL_STRUCT,
+    MYKONOS_ERR_GAINCOMP_EN_NULL_PARM,
+    MYKONOS_ERR_GAINCOMP_SET_NULL_STRUCT,
+    MYKONOS_ERR_GAINCOMP_INV_RX1_OFFSET,
+    MYKONOS_ERR_GAINCOMP_INV_RX2_OFFSET,
+    MYKONOS_ERR_GAINCOMP_INV_STEP,
+    MYKONOS_ERR_GAINCOMP_INV_EN,
+
+    MYKONOS_ERR_OBS_RX_GAINCOMP_SET_NULL_STRUCT,
+    MYKONOS_ERR_OBS_RX_GAINCOMP_EN_NULL_PARAM,
+    MYKONOS_ERR_OBS_RX_GAINCOMP_INV_EN,
+    MYKONOS_ERR_OBS_RX_GAINCOMP_INV_OFFSET,
+    MYKONOS_ERR_OBS_RX_GAINCOMP_INV_STEP,
+    MYKONOS_ERR_OBS_RX_GAINCOMP_NULL_STRUCT,
+
+    MYKONOS_ERR_SLICER_STEP_OUT_OF_RANGE,
+    MYKONOS_ERR_SLICER_INV_RX1_SEL,
+    MYKONOS_ERR_SLICER_INV_RX2_SEL,
+    MYKONOS_ERR_SLICER_EN_INV,
+
+    MYKONOS_ERR_SLICER_RX1PIN_NULL_PARM,
+    MYKONOS_ERR_SLICER_RX2PIN_NULL_PARM,
+    MYKONOS_ERR_SLICER_STEP_NULL_PARM,
+    MYKONOS_ERR_SLICER_EN_NULL_PARM,
+
+    MYKONOS_ERR_SLICER_INV_OBS_RX_SEL,
+    MYKONOS_ERR_SLICER_OBS_RX_STEP_OUT_OF_RANGE,
+    MYKONOS_ERR_SLICER_OBS_RX_EN_INV,
+    MYKONOS_ERR_SLICER_OBS_RX_EN_NULL_PARM,
+    MYKONOS_ERR_SLICER_OBS_RX_STEP_NULL_PARM,
+    MYKONOS_ERR_SLICER_OBS_RXPIN_NULL_PARM,
+
+    MYKONOS_ERR_FLOATFRMT_NULL_STRUCT,
+    MYKONOS_ERR_FLOATFRMT_SET_NULL_STRUCT,
+    MYKONOS_ERR_FLOATFRMT_INV_ROUND_MODE,
+    MYKONOS_ERR_FLOATFRMT_INV_DATA_FORMAT,
+    MYKONOS_ERR_FLOATFRMT_INV_ENC_NAN,
+    MYKONOS_ERR_FLOATFRMT_INV_EXP_BITS,
+    MYKONOS_ERR_FLOATFRMT_INV_LEADING,
+    MYKONOS_ERR_FLOATFRMT_INV_RX1ATT,
+    MYKONOS_ERR_FLOATFRMT_INV_RX2ATT,
+    MYKONOS_ERR_FLOATFRMT_INV_EN,
+    MYKONOS_ERR_FLOATFRMT_NULL_RX1ATT,
+    MYKONOS_ERR_FLOATFRMT_NULL_RX2ATT,
+    MYKONOS_ERR_FLOATFRMT_NULL_ENABLE,
+    MYKONOS_ERR_FLOATFRMT_SET_INV_EN,
+    MYKONOS_ERR_FLOATFRMT_SET_INV_RX1ATT,
+    MYKONOS_ERR_FLOATFRMT_SET_INV_RX2ATT,
+
+    MYKONOS_ERR_FLOATFRMT_INV_ORXATT,
+    MYKONOS_ERR_FLOATFRMT_INV_ORXEN,
+    MYKONOS_ERR_FLOATFRMT_NULL_ORXATT,
+    MYKONOS_ERR_FLOATFRMT_NULL_ORXENABLE,
+
+    MYKONOS_ERR_SETUPTEMPSENSOR_NULL_PARAM,
+    MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPDECIMATION,
+    MYKONOS_ERR_SETUPTEMPSENSOR_INV_OFFSET,
+    MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPWINDOW,
+    MYKONOS_ERR_GETTEMPSENSORCFG_NULL_PARAM,
+    MYKONOS_ERR_READTEMPSENSOR_NULL_PARAM,
+    MYKONOS_ERR_READTEMPSENSOR_NOT_LOCKED,
+
+    MYKONOS_ERR_GAIN_CONTROL_NOT_HYBRID,
+    MYKONOS_ERR_GPIO_HYBRID_RX1_PIN,
+    MYKONOS_ERR_GPIO_HYBRID_RX2_PIN,
+    MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_NULL_PARM,
+    MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_NULL_PARM,
+    MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_READ,
+    MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_READ,
+    MYKONOS_ERR_AGC_OBS_NOT_IN_HYBRID,
+    MYKONOS_ERR_GPIO_HYBRID_ORX_PIN,
+    MYKONOS_ERR_GPIO_HYBRID_ORX_PIN_NULL_PARM,
+
+    MYKONOS_ERR_GAIN_CONTROL_NOT_AGC,
+    MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN,
+    MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN,
+    MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN_NULL_PARM,
+    MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN_NULL_PARM,
+    MYKONOS_ERR_OBS_GAIN_CONTROL_NOT_AGC,
+    MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN,
+    MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN_NULL_PARM,
+
+    MYKONOS_ERR_GETGPIODRV_NULL_PARAM,
+    MYKONOS_ERR_GPIO_DRV_INV_PARAM,
+
+    MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM,
+    MYKONOS_ERR_GPIO_GETSLEW_NULL_PARAM,
+
+    MYKONOS_ERR_CMOS_DRV_INV_PARAM,
+    MYKONOS_ERR_CMOS_DRV_NULL_PARAM
+} mykonosGpioErr_t;
+
+/**
+ *  \brief Enum of possible Rx Slicer pin combinations
+ */
+typedef enum
+{
+    GPIO_0_1_2      = 0,    /*!< GPIO combination for RX1        */
+    GPIO_5_6_7      = 1,    /*!< GPIO combination for RX1 or RX2 */
+    GPIO_8_9_10     = 2,    /*!< GPIO combination for RX1        */
+    GPIO_11_12_13   = 3     /*!< GPIO combination for RX2        */
+} mykonosRxSlicer_t;
+
+/**
+ *  \brief Enum of possible observation channel Slicer pin combinations
+ */
+typedef enum
+{
+    GPIO_18_17_16      = 0,    /*!< GPIO combination for observation channel */
+    GPIO_16_15_14      = 1     /*!< GPIO combination for observation channel */
+} mykonosObsRxSlicer_t;
+
+/**
+ *  \brief Enum of possible GPIO slew rate settings
+ */
+typedef enum
+{
+    MYK_SLEWRATE_NONE    = 0,    /*!< Lower slew rate for the GPIO  */
+    MYK_SLEWRATE_LOW     = 1,    /*!< Low slew rate for the GPIO    */
+    MYK_SLEWRATE_MEDIUM  = 2,    /*!< Medium slew rate for the GPIO */
+    MYK_SLEWRATE_HIGH    = 3     /*!< High slew rate for the GPIO   */
+} mykonosGpioSlewRate_t;
+
+/**
+ * \brief Enumerated list of CMOS pads drive strength options
+ */
+typedef enum
+{
+    MYK_CMOSPAD_DRV_1X  = 0x00,       /*!<  2.5pF  load @ 65MHz */
+    MYK_CMOSPAD_DRV_2X  = 0x01,       /*!<    5pF  load @ 65MHz */
+    MYK_CMOSPAD_DRV_3X  = 0x03,       /*!<  7.5pF  load @ 65MHz */
+    MYK_CMOSPAD_DRV_4X  = 0x07,       /*!<   10pF  load @ 65MHz */
+    MYK_CMOSPAD_DRV_5X  = 0x0F        /*!< 12.5pF  load @ 65MHz */
+} mykonosCmosPadDrvStr_t;
+
+
+/**
+ * \brief Enumerated list for Aux ADCs
+ */
+typedef enum
+{
+    MYK_AUXADC_0        = 0x00,       /*!< Aux ADC channel 0 */
+    MYK_AUXADC_1        = 0x01,       /*!< Aux ADC channel 1 */
+    MYK_AUXADC_2        = 0x02,       /*!< Aux ADC channel 2 */
+    MYK_AUXADC_3        = 0x03,       /*!< Aux ADC channel 3 */
+    MYK_AUXADC_0_DIV2   = 0x04,       /*!< Aux ADC channel 0 with the divider by 2 set */
+    MYK_TEMPSENSOR      = 0x10        /*!< Temperature sensor channel */
+} mykonosAuxAdcChannels_t;
+
+
+/**
+ *  \brief Data structure to hold Gain compensation settings for the main receive channels
+ **/
+typedef struct
+{
+    uint8_t rx1Offset;  /*!< These parameter contains the Rx1 offset word used for the gain compensation
+                        when the gain index is at its maximum setting.
+                         It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */
+    uint8_t rx2Offset;  /*!< These parameter contains the Rx2 offset word used for the gain compensation
+                        when the gain index is at its maximum setting.
+                        It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */
+    uint8_t compStep;   /*!< These bits contains the value in dB that the total Rx gain changes
+                         when there is an LSB change in the gain index according to the following settings:
+                         compStep |  dB ramp
+                         ---------|------------
+                            0     |   0.25dB
+                            1     |   0.5dB
+                            2     |   1.0dB
+                            3     |   2.0dB
+                            4     |   3.0dB
+                            5     |   4.0dB
+                            6     |   6.0dB
+                            7     |   Not valid defaulted to 0.25dB */
+} mykonosGainComp_t;
+
+/**
+ *  \brief Data structure to hold Gain compensation settings for the observation channel
+ **/
+typedef struct
+{
+    uint8_t obsRxOffset;    /*!< These parameter contains the Rx1 offset word used for the gain compensation
+                            when the gain index is at its maximum setting.
+                            It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */
+    uint8_t compStep;       /*!< These bits contains the value in dB that the total Rx gain changes
+                            when there is an LSB change in the gain index according to the following settings:
+                            compStep |  dB ramp
+                            ---------|------------
+                               0     |   0.25dB
+                               1     |   0.5dB
+                               2     |   1.0dB
+                               3     |   2.0dB
+                               4     |   3.0dB
+                               5     |   4.0dB
+                               6     |   6.0dB
+                               7     |   Not valid defaulted to 0.25dB */
+} mykonosObsRxGainComp_t;
+
+/**
+ * \brief Data structure to hold floating point formatter settings for the floating point
+ *  number generation
+ **/
+typedef struct
+{
+   uint8_t roundMode;   /*!<These parameter set the round modes for the significand.
+                        The following settings are defined in the IEEE754 specification:
+                        roundMode |  Round type
+                        ----------|-----------------
+                             0    |  RoundTiesToEven
+                             1    |  RoundTowardsPositive
+                             2    |  RoundTowardsNegative
+                             3    |  RoundTowardsZero
+                             4    |  RoundTiesToAway*/
+   uint8_t dataFormat;  /*!< These parameter sets the format of the 16-bit output on the JESD interface:
+                        Setting this to 1 then the format is from MSB to LSB to {sign, significand, exponent}.
+                        Clearing this bit sets the format to {sign, exponent, significand}.*/
+   uint8_t encNan;      /*!< if this parameter is set to 1 then the floating point formatter reserves the highest value
+                        of exponent for NaN to be compatible to the IEEE754 specification.
+                        Clearing this parameter increases the range of the exponent by one.*/
+   uint8_t expBits;     /*!<These parameter is used to indicate the number of exponent bits in the floating point number
+                        according to the following settings:
+                          expBits|  Round type
+                         --------|------------------------------------------------
+                            0    |  2 bit exponent, 13 bit significand, 1 bit sign
+                            1    |  3 bit exponent, 12 bit significand, 1 bit sign
+                            2    |  4 bit exponent, 11 bit significand, 1 bit sign
+                            3    |  5 bit exponent, 10 bit significand, 1 bit sign */
+   uint8_t leading;     /*!< Setting this parameter hides the leading one in the the significand to be compatible to the IEEE754 specification.
+                        Clearing this parameter causes the leading one to be at the MSB of the significand.*/
+}mykonosFloatPntFrmt_t;
+
+/**
+ *  \brief Data structure used to configure the on-die Temperature Sensor
+ */
+typedef struct
+{
+    uint8_t tempDecimation;      /*!<3-bit value that controls the AuxADC decimation factor when used for temp sensor calculations;
+                                 AuxADC_decimation = 256 * 2^tempDecimation */
+    uint8_t offset;              /*!< 8-bit offset that gets added to temp sensor code internally */
+    uint8_t overrideFusedOffset; /*!< This bit overrides the factory-calibrated fuse offset
+                                 and uses the value stored in the offset member */
+    uint8_t tempWindow;          /*!<  4-bit code with a resolution of 1?C/LSB, each time a temperature measurement is performed,
+                                 the device compares the current temperature against the previous value.*/
+}mykonosTempSensorConfig_t;
+
+
+/**
+ *  \brief Data structure used to store Temperature Sensor related values
+ */
+typedef struct
+{
+    int16_t tempCode;       /*!< 16-bit signed temperature value (in deg C) that is read back */
+    uint8_t windowExceeded; /*!< If the absolute value of the difference is greater than the value in temperature configuration
+                            tempWindow, the windowExceeded flag is set.*/
+    uint8_t windowHiLo;     /*!<when windowExceeded member gets set,
+                            this bit is set to 1 if current value is greater than previous value, else reset */
+    uint8_t tempValid;      /*!< When the reading is complete and a valid temperature value stored in tempCode*/
+}mykonosTempSensorStatus_t;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* T_MYKONOSGPIO_H_ */

df_datalink_ge/src/hardware/parameters.h

@@ -0,0 +1,81 @@
+/***************************************************************************//**
+ *   @file   ad9371/src/devices/adi_hal/parameters.h
+ *   @brief  Platform dependent parameters.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef _PARAMETERS_H_
+#define _PARAMETERS_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include "platform_drivers.h"
+#include "xparameters.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define DDR_MEM_BASEADDR		XPAR_DDR_MEM_BASEADDR
+#define GPIO_0_DEVICE_ID		XPAR_PS7_GPIO_0_DEVICE_ID
+
+//#define FREQ_CTRL_DEVICE_ID		XPAR_AXI_9731_FREQ_CTRL_DEVICE_ID
+//#define GAIN_CTRL_DEVICE_ID		XPAR_AXI_9731_RX_GAIN_DEVICE_ID
+//#define ATTN_CTRL_DEVICE_ID		XPAR_AXI_9731_TX_ATTN_DEVICE_ID
+//
+//#define FREQ_CTRL_INTR_ID		XPAR_FABRIC_AXI_9731_FREQ_CTRL_IP2INTC_IRPT_INTR
+//#define GAIN_CTRL_INTR_ID		XPAR_FABRIC_AXI_9731_RX_GAIN_IP2INTC_IRPT_INTR
+//#define ATTN_CTRL_INTR_ID		XPAR_FABRIC_AXI_9731_TX_ATTN_IP2INTC_IRPT_INTR
+
+#define GPIO_OFFSET				54
+#define AD9528_CS				1
+#define AD9371_CS				2
+
+#define TX_FREQ_INTR_MASK		XGPIO_IR_CH1_MASK
+#define RX_FREQ_INTR_MASK		XGPIO_IR_CH2_MASK
+#define TX1_ATTN_INTR_MASK		XGPIO_IR_CH1_MASK
+#define TX2_ATTN_INTR_MASK		XGPIO_IR_CH2_MASK
+#define RX1_ATTN_INTR_MASK		XGPIO_IR_CH1_MASK
+#define RX2_ATTN_INTR_MASK		XGPIO_IR_CH2_MASK
+
+#define AXI_GPIO_BANK_1 1
+#define AXI_GPIO_BANK_2 2
+
+//#define DAC_GPIO_PLDDR_BYPASS	GPIO_OFFSET + 60
+#define AD9528_RESET_B			GPIO_OFFSET + 4
+#define AD9528_SYSREF_REQ		GPIO_OFFSET + 3
+#define AD9371_RESET_B			GPIO_OFFSET + 1
+
+#endif

df_datalink_ge/src/hardware/platform_drivers.c

@@ -0,0 +1,497 @@
+/***************************************************************************//**
+ *   @file   platform_drivers.c
+ *   @brief  Implementation of Xilinx Platform Drivers.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <sleep.h>
+#include "platform_drivers.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Initialize the I2C communication peripheral.
+ * @param desc - The I2C descriptor.
+ * @param init_param - The structure that contains the I2C parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t i2c_init(struct i2c_desc **desc,
+		 const struct i2c_init_param *param)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (param->type) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by i2c_init().
+ * @param desc - The I2C descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t i2c_remove(struct i2c_desc *desc)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write data to a slave device.
+ * @param desc - The I2C descriptor.
+ * @param data - Buffer that stores the transmission data.
+ * @param bytes_number - Number of bytes to write.
+ * @param stop_bit - Stop condition control.
+ *                   Example: 0 - A stop condition will not be generated;
+ *                            1 - A stop condition will be generated.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t i2c_write(struct i2c_desc *desc,
+		  uint8_t *data,
+		  uint8_t bytes_number,
+		  uint8_t stop_bit)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (data) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (bytes_number) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (stop_bit) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Read data from a slave device.
+ * @param desc - The I2C descriptor.
+ * @param data - Buffer that will store the received data.
+ * @param bytes_number - Number of bytes to read.
+ * @param stop_bit - Stop condition control.
+ *                   Example: 0 - A stop condition will not be generated;
+ *                            1 - A stop condition will be generated.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t i2c_read(struct i2c_desc *desc,
+		 uint8_t *data,
+		 uint8_t bytes_number,
+		 uint8_t stop_bit)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (data) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (bytes_number) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (stop_bit) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initialize the SPI communication peripheral.
+ * @param desc - The SPI descriptor.
+ * @param init_param - The structure that contains the SPI parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_init(struct spi_desc **desc,
+		 const struct spi_init_param *param)
+{
+	spi_desc *descriptor;
+	int32_t ret;
+
+	descriptor = (struct spi_desc *) calloc(1, sizeof(*descriptor));
+	if (!descriptor)
+		return FAILURE;
+
+	descriptor->mode = param->mode;
+	descriptor->chip_select = param->chip_select;
+	descriptor->flags = param->flags;
+
+#ifdef _XPARAMETERS_PS_H_
+	descriptor->config = XSpiPs_LookupConfig(param->id);
+	if (descriptor->config == NULL)
+		goto error;
+
+	ret = XSpiPs_CfgInitialize(&descriptor->instance,
+				   descriptor->config, descriptor->config->BaseAddress);
+	if (ret != 0)
+		goto error;
+
+	XSpiPs_SetOptions(&descriptor->instance,
+			  XSPIPS_MASTER_OPTION |
+			  ((descriptor->flags & SPI_CS_DECODE) ?
+			   XSPIPS_DECODE_SSELECT_OPTION : 0) |
+			  XSPIPS_FORCE_SSELECT_OPTION |
+			  ((descriptor->mode & SPI_CPOL) ?
+			   XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) |
+			  ((descriptor->mode & SPI_CPHA) ?
+			   XSPIPS_CLK_PHASE_1_OPTION : 0));
+
+	XSpiPs_SetClkPrescaler(&descriptor->instance,
+			       XSPIPS_CLK_PRESCALE_64);
+
+	XSpiPs_SetSlaveSelect(&descriptor->instance, 0xf);
+#else
+	ret = XSpi_Initialize(&descriptor->instance, param->id);
+	if (ret != 0)
+		goto error;
+
+	XSpi_SetOptions(&descriptor->instance,
+			XSP_MASTER_OPTION |
+			((descriptor->mode & SPI_CPOL) ?
+			 XSP_CLK_ACTIVE_LOW_OPTION : 0) |
+			((descriptor->mode & SPI_CPHA) ?
+			 XSP_CLK_PHASE_1_OPTION : 0));
+
+	XSpi_Start(&descriptor->instance);
+
+	XSpi_IntrGlobalDisable(&descriptor->instance);
+#endif
+
+	*desc = descriptor;
+
+	return SUCCESS;
+
+error:
+	free(descriptor);
+
+	return FAILURE;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_remove(struct spi_desc *desc)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write and read data to/from SPI.
+ * @param desc - The SPI descriptor.
+ * @param data - The buffer with the transmitted/received data.
+ * @param bytes_number - Number of bytes to write/read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+
+int32_t spi_write_and_read(struct spi_desc *desc,
+			   uint8_t *data,
+			   uint8_t bytes_number)
+{
+#ifdef _XPARAMETERS_PS_H_
+	XSpiPs_SetOptions(&desc->instance,
+			  XSPIPS_MASTER_OPTION |
+			  ((desc->flags & SPI_CS_DECODE) ?
+			   XSPIPS_DECODE_SSELECT_OPTION : 0) |
+			  XSPIPS_FORCE_SSELECT_OPTION |
+			  ((desc->mode & SPI_CPOL) ?
+			   XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) |
+			  ((desc->mode & SPI_CPHA) ?
+			   XSPIPS_CLK_PHASE_1_OPTION : 0));
+
+	XSpiPs_SetSlaveSelect(&desc->instance, desc->chip_select);
+			     // 0xf & ~desc->chip_select);
+	XSpiPs_PolledTransfer(&desc->instance,
+			      data, data, bytes_number);
+#else
+	XSpi_SetOptions(&desc->instance,
+			XSP_MASTER_OPTION |
+			((desc->mode & SPI_CPOL) ?
+			 XSP_CLK_ACTIVE_LOW_OPTION : 0) |
+			((desc->mode & SPI_CPHA) ?
+			 XSP_CLK_PHASE_1_OPTION : 0));
+
+	XSpi_SetSlaveSelect(&desc->instance,
+			    desc->chip_select);
+
+	XSpi_Transfer(&desc->instance,
+		      data, data, bytes_number);
+#endif
+	return 0;
+}
+
+/**
+ * @brief Obtain the GPIO decriptor.
+ * @param desc - The GPIO descriptor.
+ * @param gpio_number - The number of the GPIO.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get(struct gpio_desc **desc,
+		 uint8_t gpio_number)
+{
+	gpio_desc *descriptor;
+	int32_t ret;
+
+	descriptor = (struct gpio_desc *) malloc(sizeof(*descriptor));
+	if (!descriptor)
+		return FAILURE;
+
+#ifdef _XPARAMETERS_PS_H_
+	descriptor->config = XGpioPs_LookupConfig(0);
+	if (descriptor->config == NULL)
+		goto error;
+
+	ret = XGpioPs_CfgInitialize(&descriptor->instance,
+				    descriptor->config, descriptor->config->BaseAddr);
+	if (ret != 0)
+		goto error;
+#else
+	ret = XGpio_Initialize(&descriptor->instance, 0);
+	if (ret != 0)
+		goto error;
+#endif
+
+	descriptor->number = gpio_number;
+
+	*desc = descriptor;
+
+	return SUCCESS;
+
+error:
+	free(descriptor);
+
+	return FAILURE;
+}
+
+/**
+ * @brief Free the resources allocated by gpio_get().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_remove(struct gpio_desc *desc)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Enable the input direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_input(struct gpio_desc *desc)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Enable the output direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+			      uint8_t value)
+{
+#ifdef _XPARAMETERS_PS_H_
+	XGpioPs_SetDirectionPin(&desc->instance, desc->number, 1);
+
+	XGpioPs_SetOutputEnablePin(&desc->instance, desc->number, 1);
+
+	XGpioPs_WritePin(&desc->instance, desc->number, value);
+#else
+	uint8_t pin = desc->number;
+	uint8_t channel;
+	uint32_t reg_val;
+
+	if (pin >= 32) {
+		channel = 2;
+		pin -= 32;
+	} else
+		channel = 1;
+
+	reg_val = XGpio_GetDataDirection(&desc->instance, channel);
+	reg_val &= ~(1 << pin);
+	XGpio_SetDataDirection(&desc->instance, channel, reg_val);
+
+	reg_val = XGpio_DiscreteRead(&desc->instance, channel);
+	if(value)
+		reg_val |= (1 << pin);
+	else
+		reg_val &= ~(1 << pin);
+	XGpio_DiscreteWrite(&desc->instance, channel, reg_val);
+#endif
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Get the direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param direction - The direction.
+ *                    Example: GPIO_OUT
+ *                             GPIO_IN
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+			   uint8_t *direction)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (direction) {
+		// Unused variable - fix compiler warning
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Set the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_set_value(struct gpio_desc *desc,
+		       uint8_t value)
+{
+#ifdef _XPARAMETERS_PS_H_
+	XGpioPs_WritePin(&desc->instance, desc->number, value);
+#else
+	uint8_t pin = desc->number;
+	uint8_t channel;
+	uint32_t reg_val;
+
+	if (pin >= 32) {
+		channel = 2;
+		pin -= 32;
+	} else
+		channel = 1;
+
+	reg_val = XGpio_DiscreteRead(&desc->instance, channel);
+	if(value)
+		reg_val |= (1 << pin);
+	else
+		reg_val &= ~(1 << pin);
+	XGpio_DiscreteWrite(&desc->instance, channel, reg_val);
+#endif
+
+	return 0;
+}
+
+/**
+ * @brief Get the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_value(struct gpio_desc *desc,
+		       uint8_t *value)
+{
+	if (desc) {
+		// Unused variable - fix compiler warning
+	}
+
+	if (value) {
+		// Unused variable - fix compiler warning
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Generate microseconds delay.
+ * @param usecs - Delay in microseconds.
+ * @return None.
+ */
+void udelay(uint32_t usecs)
+{
+	usleep(usecs);
+}
+
+/**
+ * @brief Generate miliseconds delay.
+ * @param msecs - Delay in miliseconds.
+ * @return None.
+ */
+void mdelay(uint32_t msecs)
+{
+#ifdef _XPARAMETERS_PS_H_
+	usleep(msecs * 1000);
+#else
+	usleep(msecs * 50);	// FIXME
+#endif
+}

df_datalink_ge/src/hardware/platform_drivers.h

@@ -0,0 +1,223 @@
+/***************************************************************************//**
+ *   @file   platform_drivers.h
+ *   @brief  Header file of Xilinx Platform Drivers.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef PLATFORM_DRIVERS_H_
+#define PLATFORM_DRIVERS_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include <xparameters.h>
+#ifdef _XPARAMETERS_PS_H_
+#include <xspips.h>
+#include <xgpiops.h>
+#else
+#include <xspi.h>
+#include <xgpio.h>
+#endif
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define SUCCESS		0
+#define FAILURE		-1
+
+#define	SPI_CPHA	0x01
+#define	SPI_CPOL	0x02
+
+#define SPI_CS_DECODE	0x01
+#define SPI_CS_DECODE_DISABLE	0x00
+
+#define GPIO_OUT	0x01
+#define GPIO_IN		0x00
+
+#define GPIO_HIGH	0x01
+#define GPIO_LOW	0x00
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+typedef enum i2c_type {
+	XILINX_I2C
+} i2c_type;
+
+typedef struct i2c_init_param {
+	enum i2c_type	type;
+	uint32_t	id;
+	uint32_t	max_speed_hz;
+	uint8_t		slave_address;
+} i2c_init_param;
+
+typedef struct i2c_desc {
+	enum i2c_type	type;
+	uint32_t	id;
+	uint32_t	max_speed_hz;
+	uint8_t		slave_address;
+} i2c_desc;
+
+typedef enum spi_type {
+	XILINX_SPI
+} spi_type;
+
+/**
+ * @enum spi_mode
+ * @brief SPI configuration for clock phase and polarity.
+ */
+typedef enum spi_mode {
+	/** Data on rising, shift out on falling */
+	SPI_MODE_0 = (0 | 0),
+	/** Data on falling, shift out on rising */
+	SPI_MODE_1 = (0 | SPI_CPHA),
+	/** Data on falling, shift out on rising */
+	SPI_MODE_2 = (SPI_CPOL | 0),
+	/** Data on rising, shift out on falling */
+	SPI_MODE_3 = (SPI_CPOL | SPI_CPHA)
+} spi_mode;
+
+typedef struct spi_init_param {
+	enum spi_type	type;
+	uint32_t	id;
+	uint32_t	max_speed_hz;
+	enum spi_mode	mode;
+	uint8_t		chip_select;
+	uint32_t	flags;
+} spi_init_param;
+
+typedef struct spi_desc {
+	enum spi_type	type;
+	uint32_t		id;
+	uint32_t		max_speed_hz;
+	enum spi_mode	mode;
+	uint8_t			chip_select;
+	uint32_t		flags;
+#ifdef _XPARAMETERS_PS_H_
+	XSpiPs_Config	*config;
+	XSpiPs			instance;
+#else
+	XSpi			instance;
+#endif
+} spi_desc;
+
+typedef enum gpio_type {
+	XILINX_GPIO
+} gpio_type;
+
+typedef struct gpio_desc {
+	enum gpio_type	type;
+	uint32_t		id;
+	uint8_t			number;
+#ifdef _XPARAMETERS_PS_H_
+	XGpioPs_Config	*config;
+	XGpioPs			instance;
+#else
+	XGpio			instance;
+#endif
+} gpio_desc;
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Initialize the I2C communication peripheral. */
+int32_t i2c_init(struct i2c_desc **desc,
+		 const struct i2c_init_param *param);
+
+/* Free the resources allocated by i2c_init(). */
+int32_t i2c_remove(struct i2c_desc *desc);
+
+/* Write data to a slave device. */
+int32_t i2c_write(struct i2c_desc *desc,
+		  uint8_t *data,
+		  uint8_t bytes_number,
+		  uint8_t stop_bit);
+
+/* Read data from a slave device. */
+int32_t i2c_read(struct i2c_desc *desc,
+		 uint8_t *data,
+		 uint8_t bytes_number,
+		 uint8_t stop_bit);
+
+/* Initialize the SPI communication peripheral. */
+int32_t spi_init(struct spi_desc **desc,
+		 const struct spi_init_param *param);
+
+/* Free the resources allocated by spi_init() */
+int32_t spi_remove(struct spi_desc *desc);
+
+/* Write and read data to/from SPI. */
+int32_t spi_write_and_read(struct spi_desc *desc,
+			   uint8_t *data,
+			   uint8_t bytes_number);
+
+/* Obtain the GPIO decriptor. */
+int32_t gpio_get(struct gpio_desc **desc,
+		 uint8_t gpio_number);
+
+/* Free the resources allocated by gpio_get() */
+int32_t gpio_remove(struct gpio_desc *desc);
+
+/* Enable the input direction of the specified GPIO. */
+int32_t gpio_direction_input(struct gpio_desc *desc);
+
+/* Enable the output direction of the specified GPIO. */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+			      uint8_t value);
+
+/* Get the direction of the specified GPIO. */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+			   uint8_t *direction);
+
+/* Set the value of the specified GPIO. */
+int32_t gpio_set_value(struct gpio_desc *desc,
+		       uint8_t value);
+
+/* Get the value of the specified GPIO. */
+int32_t gpio_get_value(struct gpio_desc *desc,
+		       uint8_t *value);
+
+/* Generate microseconds delay. */
+void udelay(uint32_t usecs);
+
+/* Generate miliseconds delay. */
+void mdelay(uint32_t msecs);
+
+#endif // PLATFORM_DRIVERS_H_

df_datalink_ge/src/include/axi_io.h

@@ -0,0 +1,59 @@
+/***************************************************************************//**
+ *   @file   axi_io.h
+ *   @brief  Header file of AXI IO.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef _AXI_IO_H_
+#define _AXI_IO_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* AXI IO Read data */
+int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data);
+
+/* AXI IO Write data */
+int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data);
+
+#endif // _AXI_IO_H_

df_datalink_ge/src/include/circ_queue.h

@@ -0,0 +1,111 @@
+/*****************************************************************************/
+/**
+ * Description: A simple circular FIFO bounded queue
+ * 
+ * Author: Fan Hao
+ * Date: 2023-02-23 10:29
+ * LastEditors: Fan Hao
+ * LastEditTime: 2023-02-23 12:53
+ * Revisions: Rev 0.0
+ * History: 
+ * [2023-02-23]: Initial Version.
+ * 
+ * Copyright(c) 2023 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * NOTE: Forked from https://github.com/chrismerck/rpa_queue.git
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The ASF licenses this file to You under the Apache License, Version 2.0
+ * (the "License"); you may not use this file except in compliance with
+ * the License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+******************************************************************************/
+
+#ifndef CIRC_QUEUE_H
+#define CIRC_QUEUE_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+
+
+/**
+ * opaque structure
+ */
+typedef struct {
+  void **data;
+  volatile uint32_t nelts; /**< # elements */
+  uint32_t in;  /**< next empty location */
+  uint32_t out;   /**< next filled location */
+  uint32_t bounds;/**< max size of queue */
+} CIRC_QUEUE;
+
+
+
+/**
+ * create a FIFO queue
+ * @param queue The new queue
+ * @param queue_capacity maximum size of the queue
+ * @param a pool to allocate queue from
+ */
+bool CircQueueCreate(CIRC_QUEUE **queue, uint32_t queue_capacity);
+
+/** free queue memory -- call after destroy 
+ * @note we do not free in destroy() to follow pthreads convention
+*/
+void CircQueueFree(CIRC_QUEUE * queue);
+
+/**
+ * Detects when the CIRC_QUEUE is full. This utility function is expected
+ * to be called from within critical sections, and is not threadsafe.
+ */
+bool isCircQueueFull(CIRC_QUEUE *queue);
+
+/**
+ * Detects when the CIRC_QUEUE is empty. This utility function is expected
+ * to be called from within critical sections, and is not threadsafe.
+ */
+bool isCircQueueEmpty(CIRC_QUEUE *queue);
+
+/**
+ * push/add an object to the queue, blocking if the queue is already full
+ *
+ * @param queue the queue
+ * @param data the data
+ * @returns RPA_EINTR the blocking was interrupted (try again)
+ * @returns RPA_EOF the queue has been terminated
+ * @returns RPA_SUCCESS on a successful push
+ */
+bool CircQueuePush(CIRC_QUEUE *queue, void *data);
+
+
+/**
+ * pop/get an object from the queue, blocking if the queue is already empty
+ *
+ * @param queue the queue
+ * @param data the data
+ * @returns RPA_EINTR the blocking was interrupted (try again)
+ * @returns RPA_EOF if the queue has been terminated
+ * @returns RPA_SUCCESS on a successful pop
+ */
+bool CircQueuePop(CIRC_QUEUE *queue, void **data);
+
+/**
+ * returns the size of the queue.
+ *
+ * @warning this is not threadsafe, and is intended for reporting/monitoring
+ * of the queue.
+ * @param queue the queue
+ * @returns the size of the queue
+ */
+uint32_t CircQueueSize(CIRC_QUEUE *queue);
+
+#endif /* CIRC_QUEUE_H */

df_datalink_ge/src/include/clist.h

@@ -0,0 +1,118 @@
+
+//
+// clist.h
+//
+// Copyright (c) 2010 TJ Holowaychuk <[email protected]>
+//
+
+#ifndef __CLIST_H__
+#define __CLIST_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdlib.h>
+#include <stdint.h>
+
+  /*
+   * clist_t iterator direction.
+   */
+
+  typedef enum
+  {
+    LIST_HEAD,
+    LIST_TAIL
+  } clist_direction_t;
+
+  /*
+   * clist_t node struct.
+   */
+
+  typedef struct clist_node
+  {
+    struct clist_node *prev;
+    struct clist_node *next;
+    void *val;
+  } clist_node_t;
+
+  /*
+   * clist_t struct.
+   */
+
+  typedef struct
+  {
+    clist_node_t *head;
+    clist_node_t *tail;
+    uint32_t len;
+    void (*free)(void *val);
+    int8_t (*compare)(void *a, void *b);
+  } clist_t;
+
+  /*
+   * clist_t iterator struct.
+   */
+
+  typedef struct
+  {
+    clist_node_t *next;
+    clist_direction_t direction;
+  } clist_iterator_t;
+
+  // Node prototypes.
+
+  clist_node_t *
+  clist_node_new(void *val);
+
+  // clist_t prototypes.
+
+  clist_t *
+  clist_new(void);
+
+  clist_node_t *
+  clist_rpush(clist_t *self, clist_node_t *node);
+
+  clist_node_t *
+  clist_lpush(clist_t *self, clist_node_t *node);
+
+  clist_node_t *
+  clist_find(clist_t *self, void *val);
+
+  clist_node_t *
+  clist_at(clist_t *self, int index);
+
+  clist_node_t *
+  clist_rpop(clist_t *self);
+
+  clist_node_t *
+  clist_lpop(clist_t *self);
+
+  void
+  clist_remove(clist_t *self, clist_node_t *node);
+
+  void
+  clist_clear(clist_t *self);
+
+  void
+  clist_destroy(clist_t *self);
+
+  // clist_t iterator prototypes.
+
+  clist_iterator_t *
+  clist_iterator_new(clist_t *list, clist_direction_t direction);
+
+  clist_iterator_t *
+  clist_iterator_new_from_node(clist_node_t *node, clist_direction_t direction);
+
+  clist_node_t *
+  clist_iterator_next(clist_iterator_t *self);
+
+  void
+  clist_iterator_destroy(clist_iterator_t *self);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CLIBS_LIST_H__ */

df_datalink_ge/src/include/common.h

@@ -0,0 +1,92 @@
+/*****************************************************************************/
+/**
+ * Description: Common definitions
+ *
+ * Date: 2023-12-21 16:32
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-07-16 17:13
+ * Revisions: Rev 0.1
+ * History:
+ * [2023-12-21]: Ensure the code conform ISO C11 standard.
+ * [2022-07-16]: New branch for Dijian.
+ * [2021-11-16]: Initial version.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+/***************************** Include Files *********************************/
+#ifndef __COMMON_H_
+#define __COMMON_H_
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <assert.h>
+#include "util.h"
+#include "error.h"
+#include "../config/app_config.h"
+
+/************************** Constant Definitions *****************************/
+/***************** Macros (Inline Functions) Definitions *********************/
+#define __PRINT_BLOCK(block) \
+    do                       \
+    {                        \
+        block                \
+    } while (0)
+
+#define ASSERT(exp) ((exp) ? (void)0 : AppAssert(__FILE__, __LINE__))
+#define _nop_() __asm__("nop")
+
+/* Stringify */
+#define STR(x) #x
+
+// #define _814_DEBUG_LEVEL 3
+
+#if _814_DEBUG_LEVEL > 0
+#define DBG_PRINT(...) printf(__VA_ARGS__)
+#endif
+#if _814_DEBUG_LEVEL >= 1
+#define DBG_ERROR(...) __PRINT_BLOCK( \
+    printf("in"__FILE__               \
+           " #%4d [error]\t",         \
+           __LINE__);                 \
+    printf(__VA_ARGS__);)
+#endif
+#if _814_DEBUG_LEVEL >= 2
+#define DBG_WARNING(...) __PRINT_BLOCK( \
+    printf("[warning]\t");              \
+    printf(__VA_ARGS__);)
+#endif
+#if _814_DEBUG_LEVEL >= 3
+#define DBG_INFO(...) __PRINT_BLOCK( \
+    printf("[Info]\t");              \
+    printf(__VA_ARGS__);)
+#endif
+
+#ifndef DBG_ERROR
+#define DBG_ERROR(...) \
+    {                  \
+    }
+#endif
+#ifndef DBG_WARNING
+#define DBG_WARNING(...) \
+    {                    \
+    }
+#endif
+#ifndef DBG_INFO
+#define DBG_INFO(...) \
+    {                 \
+    }
+#endif
+#ifndef DBG_PRINT
+#define DBG_PRINT(...) \
+    {                  \
+    }
+#endif
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+void AppAssert(const char *file, int line);
+#endif /* __COMMON_H_ */

df_datalink_ge/src/include/error.h

@@ -0,0 +1,47 @@
+/*****************************************************************************/
+/**
+ * Description: Error code definitions.
+ *
+ * Author: Fan Hao
+ * Date: 2022-06-18 16:37
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-06-18 17:12
+ * Revisions: Rev 0.0
+ * History:
+ * [2022-06-18]: Initial version.
+ *
+ * Copyright(c) 2022 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+******************************************************************************/
+
+#ifndef SRC_ERROR_H_
+#define SRC_ERROR_H_
+
+#include <errno.h>
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#ifdef SUCCESS
+#undef SUCCESS
+#endif
+#define SUCCESS		0
+#ifdef FAILURE
+#undef FAILURE
+#endif
+#define FAILURE		-1
+
+#define EPARAM -2	/*!< Data crc check failed */
+#define ECRC -3     /*!< Data crc check failed */
+#define EDINVAL -4	/*!< Device is invalid (sleep or power off) */
+#define EDCONF -5	/*!< Device confugure error */
+#define ETIMEOUT -6 /*!< Timeout error */
+#define EIGNORE -7	/*!< Received an unsupported command, and ignore it */
+#define EQUEUE  -8	/*!< Queue overflow */
+#define EUNEXP  -9	/*!< Encounter an unexpected error */
+
+#define IS_ERR_VALUE(x)	((x) != SUCCESS)
+
+#endif // ERROR_H_

df_datalink_ge/src/include/global_timer.h

@@ -0,0 +1,95 @@
+#ifndef SRC_GLOBAL_TIMER_H_
+#define SRC_GLOBAL_TIMER_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <inttypes.h>
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @struct timer_init_param
+ * @brief  Structure holding the parameters for timer initialization
+ */
+struct global_timer_init_param {
+	/** timer ID */
+	uintptr_t base_addr;
+	/** timer ID */
+	uint16_t id;
+	/** timer count frequency (Hz) */
+	uint32_t freq_hz;
+	/** counter start value */
+	uint64_t load_value;
+};
+
+/**
+ * @struct timer_desc
+ * @brief Structure holding timer descriptor
+ */
+struct global_timer_desc {
+	/** timer ID */
+	uintptr_t base_addr;
+	/** timer ID */
+	uint16_t id;
+	/** timer count frequency (Hz) */
+	uint32_t freq_hz;
+	/** counter start value */
+	uint64_t load_value;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Initialize hardware timer and the handler structure associated with it. */
+int32_t global_timer_init(struct global_timer_desc **desc,
+		   struct global_timer_init_param *param);
+
+/* Free the memory allocated by timer_setup(). */
+int32_t global_timer_remove(struct global_timer_desc *desc);
+
+/* Start a timer. */
+int32_t global_timer_start(struct global_timer_desc *desc);
+
+/* Stop a timer from counting. */
+int32_t global_timer_stop(struct global_timer_desc *desc);
+
+/* Get the value of the counter register for the timer. */
+int32_t global_timer_counter_get(struct global_timer_desc *desc, uint64_t *counter);
+
+/* Set the timer counter register value. */
+int32_t global_timer_counter_set(struct global_timer_desc *desc, uint64_t new_val);
+
+/* Get the timer clock frequency. */
+int32_t global_timer_count_clk_get(struct global_timer_desc *desc, uint32_t *freq_hz);
+
+/* Set the timer clock frequency. */
+int32_t global_timer_count_clk_set(struct global_timer_desc *desc, uint32_t freq_hz);
+
+/* Enable global timer interrupt. */
+int32_t global_timer_irq_enable(struct global_timer_desc *desc);
+
+/* Disable global timer interrupt. */
+int32_t global_timer_irq_disable(struct global_timer_desc *desc);
+
+/* Implement a acknowledgment global timer interrupt. */
+int32_t global_timer_irq_ack(struct global_timer_desc *desc);
+
+/* Set comparator register. */
+int32_t global_timer_compara_set(struct global_timer_desc *desc, uint64_t com_val);
+
+/* Set auto increment register . */
+int32_t global_timer_auto_inc_set(struct global_timer_desc *desc, uint32_t inc_val);
+
+/* Enable global timer auto increment mode. */
+int32_t global_timer_auto_inc_enable(struct global_timer_desc *desc);
+
+/* Disable global timer auto increment mode. */
+int32_t global_timer_auto_inc_disable(struct global_timer_desc *desc);
+
+#endif /* SRC_TIMER_H_ */
+

df_datalink_ge/src/include/gpio.h

@@ -0,0 +1,188 @@
+/***************************************************************************//**
+ *   @file   gpio.h
+ *   @brief  Header file of GPIO Interface
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define GPIO_OUT	0x01
+#define GPIO_IN		0x00
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @struct gpio_platform_ops
+ * @brief Structure holding gpio function pointers that point to the platform
+ * specific function
+ */
+struct gpio_platform_ops ;
+
+/**
+ * @enum gpio_pull_up
+ * @brief Enum that holds the possible pull up/ pull down resistor configuration.
+ */
+enum gpio_pull_up {
+	PULL_NONE,
+	/** Strong pull up */
+	PULL_UP,
+	/** Strong pull down */
+	PULL_DOWN,
+	PULL_UP_WEAK,
+	PULL_DOWN_WEAK
+};
+
+/**
+ * @struct gpio_init_param
+ * @brief Structure holding the parameters for GPIO initialization.
+ */
+struct gpio_init_param {
+	/** Port number */
+	int32_t		port;
+	/** GPIO number */
+	int32_t		number;
+	/** Pull up/down resistor configuration */
+	enum gpio_pull_up pull;
+	/** GPIO platform specific functions */
+	const struct gpio_platform_ops *platform_ops;
+	/** GPIO extra parameters (device specific) */
+	void		*extra;
+};
+
+/**
+ * @struct gpio_desc
+ * @brief Structure holding the GPIO descriptor.
+ */
+struct gpio_desc {
+	/** Port number */
+	int32_t		port;
+	/** GPIO number */
+	int32_t		number;
+	/** Pull up/down resistor configuration */
+	enum gpio_pull_up pull;
+	/** GPIO platform specific functions */
+	const struct gpio_platform_ops *platform_ops;
+	/** GPIO extra parameters (device specific) */
+	void		*extra;
+};
+
+/**
+ * @enum gpio_values
+ * @brief Enum that holds the possible output states of a GPIO.
+ */
+enum gpio_values {
+	/** GPIO logic low */
+	GPIO_LOW,
+	/** GPIO logic high */
+	GPIO_HIGH,
+	/** GPIO high impedance */
+	GPIO_HIGH_Z
+};
+
+/**
+ * @struct gpio_platform_ops
+ * @brief Structure holding gpio function pointers that point to the platform
+ * specific function
+ */
+struct gpio_platform_ops {
+	/** gpio initialization function pointer */
+	int32_t (*gpio_ops_get)(struct gpio_desc **,
+				const struct gpio_init_param *);
+	/** gpio optional descriptor function pointer */
+	int32_t (*gpio_ops_get_optional)(struct gpio_desc **,
+					 const struct gpio_init_param *);
+	/** gpio remove function pointer */
+	int32_t (*gpio_ops_remove)(struct gpio_desc *);
+	/** gpio direction input function pointer */
+	int32_t (*gpio_ops_direction_input)(struct gpio_desc *);
+	/** gpio direction output function pointer */
+	int32_t (*gpio_ops_direction_output)(struct gpio_desc *, uint8_t);
+	/** gpio get direction function pointer */
+	int32_t (*gpio_ops_get_direction)(struct gpio_desc *, uint8_t *);
+	/** gpio set value function pointer */
+	int32_t (*gpio_ops_set_value)(struct gpio_desc *, uint8_t);
+	/** gpio get value function pointer */
+	int32_t (*gpio_ops_get_value)(struct gpio_desc *, uint8_t *);
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Obtain the GPIO decriptor. */
+int32_t gpio_get(struct gpio_desc **desc,
+		       const struct gpio_init_param *param);
+
+/* Obtain optional GPIO descriptor. */
+int32_t gpio_get_optional(struct gpio_desc **desc,
+				const struct gpio_init_param *param);
+
+/* Free the resources allocated by gpio_get(). */
+int32_t gpio_remove(struct gpio_desc *desc);
+
+/* Enable the input direction of the specified GPIO. */
+int32_t gpio_direction_input(struct gpio_desc *desc);
+
+/* Enable the output direction of the specified GPIO. */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+				    uint8_t value);
+
+/* Get the direction of the specified GPIO. */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+				 uint8_t *direction);
+
+/* Set the value of the specified GPIO. */
+int32_t gpio_set_value(struct gpio_desc *desc,
+			     uint8_t value);
+
+/* Get the value of the specified GPIO. */
+int32_t gpio_get_value(struct gpio_desc *desc,
+			     uint8_t *value);
+
+#endif // _GPIO_H_

df_datalink_ge/src/include/irq.h

@@ -0,0 +1,235 @@
+/***************************************************************************//**
+ *   @file   irq.h
+ *   @brief  Header file of IRQ interface.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef _IRQ_H_
+#define _IRQ_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum irq_uart_event_e
+ * @brief Possible events for uart interrupt
+ * @todo replace this with enum irq_event
+ */
+enum irq_uart_event_e {
+	/** Write operation finalized */
+	IRQ_WRITE_DONE,
+	/** Read operation finalized */
+	IRQ_READ_DONE,
+	/** An error occurred */
+	IRQ_ERROR
+};
+
+enum irq_event {
+	EVT_GPIO,
+	EVT_UART_TX_COMPLETE,
+	EVT_UART_RX_COMPLETE,
+	EVT_UART_ERROR,
+	EVT_RTC,
+	EVT_XINT,
+	EVT_TIM_ELAPSED
+};
+
+enum irq_trig_level {
+	IRQ_LEVEL_LOW,
+	IRQ_LEVEL_HIGH,
+	IRQ_EDGE_FALLING,
+	IRQ_EDGE_RISING,
+	IRQ_EDGE_BOTH
+};
+
+enum irq_peripheral {
+	GPIO_IRQ,
+	UART_IRQ,
+	RTC_IRQ,
+	TIM_IRQ
+};
+
+/**
+ * @struct irq_platform_ops
+ * @brief Structure holding IRQ function pointers that point to the platform
+ * specific function
+ */
+struct irq_platform_ops ;
+
+/**
+ * @struct irq_init_param
+ * @brief Structure holding the initial parameters for Interrupt Request.
+ */
+struct irq_init_param {
+	/** Interrupt request controller ID. */
+	uint32_t	irq_ctrl_id;
+	/** Platform specific IRQ platform ops structure. */
+	const struct irq_platform_ops *platform_ops;
+	/**
+	 * This is intended to store irq controller specific configurations,
+	 * it should not be a reference to any peripheral descriptor.
+	*/
+	void		*extra;
+};
+
+/**
+ * @struct irq_desc
+ * @brief Structure for Interrupt Request descriptor.
+ */
+struct irq_ctrl_desc {
+	/** Interrupt request controller ID. */
+	uint32_t	irq_ctrl_id;
+	/** Platform specific IRQ platform ops structure. */
+	const struct irq_platform_ops *platform_ops;
+	/**
+	 * This is intended to store irq controller specific configurations,
+	 * it should not be a reference to any peripheral descriptor.
+	*/
+	void		*extra;
+};
+
+/**
+ * @struct callback_desc
+ * @brief Structure describing a callback to be registered
+ * @todo: remove this, use struct irq_callback instead.
+ */
+struct callback_desc {
+	/** Callback to be called when the event an event occurs. */
+	void (*callback)(void *context);
+	/**
+	 * Callback to be called when the event an event occurs
+	 *  @param ctx - Same as \ref callback_desc.ctx
+	 *  @param event - Event that generated the callback
+	 *  @param extra - Platform specific data
+	 */
+	void (*legacy_callback)(void *ctx, uint32_t event,
+				void *extra); /* TODO: remove this. */
+	/** Parameter to be passed when the callback is called */
+	void *ctx;
+	/** Platform specific configuration for a callback */
+	void *legacy_config; /* TODO: remove this. */
+	/** Platform specific event that triggers the calling of the callback. */
+	enum irq_event event;
+	/** Interrupt source peripheral specifier. */
+	enum irq_peripheral peripheral;
+	/** This will be used to store HAL specific descriptors */
+	void *handle;
+};
+
+/**
+ * @struct irq_platform_ops
+ * @brief Structure holding IRQ function pointers that point to the platform
+ * specific function
+ */
+struct irq_platform_ops {
+	/** Initialize a interrupt controller peripheral. */
+	int32_t (*init)(struct irq_ctrl_desc **desc,
+			const struct irq_init_param *param);
+	/** Register a legacy_callback to handle the irq events */
+	int32_t (*register_callback)(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				     struct callback_desc *callback);
+	/** Unregisters a generic IRQ handling function */
+	int32_t (*unregister_callback)(struct irq_ctrl_desc *desc,
+				       uint32_t irq_id,
+				       struct callback_desc *callback);
+	/** Global interrupt enable */
+	int32_t (*global_enable)(struct irq_ctrl_desc *desc);
+	/** Global interrupt disable */
+	int32_t (*global_disable)(struct irq_ctrl_desc *desc);
+	/** Set interrupt trigger level. */
+	int32_t (*trigger_level_set)(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				     enum irq_trig_level trig);
+	/** Enable specific interrupt */
+	int32_t (*enable)(struct irq_ctrl_desc *desc, uint32_t irq_id);
+	/** Disable specific interrupt */
+	int32_t (*disable)(struct irq_ctrl_desc *desc, uint32_t irq_id);
+	/** Set the priority level for a specific interrupt */
+	int32_t (*set_priority)(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				uint32_t priority_level);
+	/** IRQ remove function pointer */
+	int32_t (*remove)(struct irq_ctrl_desc *desc);
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Initialize a interrupt controller peripheral. */
+int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
+			    const struct irq_init_param *param);
+
+/* Free the resources allocated by irq_ctrl_init(). */
+int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc);
+
+/* Register a callback to handle the irq events */
+int32_t irq_register_callback(struct irq_ctrl_desc *desc,
+				    uint32_t irq_id,
+				    struct callback_desc *callback_desc);
+
+/* Unregisters a generic IRQ handling function */
+int32_t irq_unregister_callback(struct irq_ctrl_desc *desc,
+				      uint32_t irq_id,
+				      struct callback_desc *callback_desc);
+
+/* Global interrupt enable */
+int32_t irq_global_enable(struct irq_ctrl_desc *desc);
+
+/* Global interrupt disable */
+int32_t irq_global_disable(struct irq_ctrl_desc *desc);
+
+/* Set interrupt trigger level. */
+int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc,
+				    uint32_t irq_id,
+				    enum irq_trig_level trig);
+
+/* Enable specific interrupt */
+int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id);
+
+/* Disable specific interrupt */
+int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id);
+
+/** Set the priority level for a specific interrupt */
+int32_t irq_set_priority(struct irq_ctrl_desc *desc,
+			       uint32_t irq_id,
+			       uint32_t priority_level);
+#endif // _IRQ_H_

df_datalink_ge/src/include/list.h

@@ -0,0 +1,327 @@
+/***************************************************************************//**
+ *   @file   list.h
+ *   @brief  List library header
+ *   @author Mihail Chindris ([email protected])
+********************************************************************************
+ *   @copyright
+ * Copyright 2020(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+********************************************************************************
+ *
+ *  @section list_details Library description
+ *   This library handles double linked lists and it expose inseart,
+ *   read, get and delete functions. \n
+ *   It also can be accesed using it member functions which wrapp function for
+ *   usual list types.\n
+ *  @subsection example Sample code
+ *   @code{.c}
+ *	// -- Use a generic list
+ *	struct list_desc *list1;
+ *	struct iterator  *it;
+ *	uint32_t	 a;
+ *	// Create list list1
+ *	list_init(&list1, LIST_DEFAULT, NULL);
+ *	// Add items to the list
+ *	list_add_last(list1, 1);
+ *	list_add_last(list1, 2);
+ *	list_add_last(list1, 3);
+ *	// Here the list will be: 1 -> 2 - > 3
+ *
+ *	list_read_last(list1, &a);
+ *	printf("Last: %d\n", a);
+ *	// 3 will be printed
+ *	// Create an iterator on the end of the list
+ *	iterator_init(&it, list1, 0);
+ *	// Move the iterator backword with one position
+ *	iterator_move(it, -1);
+ *	// Read the data at the current position
+ *	iterator_read(it, &a);
+ *	printf("Current: %d\n", a);
+ *	// 2 will be printed
+ *	iterator_remove(it);
+ *	list_remove(list1);
+ *
+ *	// -- Use a popular list
+ *	struct list_desc *stack;
+ *	// Create a FIFO list
+ *	list_init(&stack, LIST_STACK, NULL);
+ *	// Put elements in the list
+ *	stack->push(stack, 1);
+ *	stack->push(stack, 2);
+ *	stack->push(stack, 3);
+ *	// Read from the stack
+ *	stack->pop(stack, &a);
+ *	printf("Last: %d\n", a);
+ *	// 3 will be printed
+ *	list_remove(stack);
+ *    @endcode
+*******************************************************************************/
+
+#ifndef _LIST_H_
+#define _LIST_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @struct list_desc
+ * @brief Structure storing the list and function wrapper for usual list types
+ *
+ * With this structure the funtionalities of usual list types
+ * ( \ref adapter_type ) can be accesed with the functions referenced in this
+ * structure.
+ * For example:
+ * @code{.c}
+ * my_queue->push(my_queue, my_data);
+ * @endcode
+ */
+struct list_desc;
+
+/**
+ * @struct list_iterator
+ * @brief Structure used to iterate through the list using Iterator functions.
+ */
+struct iterator;
+
+/**
+ * @brief Prototype of the compare function.
+ *
+ * The function used to compare the elements of the liste when doing
+ * operations on an ordered list.
+ * @param data1 - First element to be compared
+ * @param data2 - Second element to be compared
+ * @return
+ *  - -1 - If data1 < data2
+ *  - 0 - If data1 == data2
+ *  - 1 - If data1 > data2
+ */
+typedef int32_t (*f_cmp)(void *data1, void *data2);
+
+/**
+ * @name Generic functions
+ * Each function interacting with the list have one of the following formats.\n
+ * Aditionaly they may have one more parametere for specific functionalities.\n
+ * In the Iterator functions, the list reference is replaced by the iterator's
+ * one.
+ * @{
+ */
+
+/**
+ * @brief Add an element in the list.
+ *
+ * The element of the list is created and the data field is stored in it.
+ * @param list_desc - Reference to the list. Created by \ref list_init.
+ * @param data - Data to store in a list element
+ * @return
+ *  - 0 : On success
+ *  - -1 : Otherwise
+ */
+typedef int32_t (*f_add)(struct list_desc *list_desc, void *data);
+
+/**
+ * @brief Edit an element in the list. The content is replaced by new_data.
+ * @param list_desc - Reference to the list. Created by \ref list_init.
+ * @param new_data - New data to replace the old one
+ * @return
+ *  - 0 : On success
+ *  - -1 : Otherwise
+ */
+typedef int32_t (*f_edit)(struct list_desc *list_desc, void *new_data);
+
+/**
+ * @brief Read an element from the list.
+ * @param list_desc - Reference to the list. Created by \ref list_init.
+ * @param result - If not null, result is filled with:
+ * @param data - Content of the list element, NULL if some error occur.
+ * @return \n
+ *  - 0 : On success
+ *  - -1 : Otherwise
+ * @note If the content of an element can be 0 then the result must be checked
+ * to see if the functions has succeded
+ */
+typedef int32_t (*f_read)(struct list_desc *list_desc, void **data);
+
+/**
+ * @brief Read and remove an element from the list.
+ * @param list_desc - Reference to the list. Created by \ref list_init.
+ * @param result - If not null, result is filled with:
+ * @param data - Content of the list element, NULL if some error occur.
+ * @return
+ *  - 0 : On success
+ *  - -1 : Otherwise
+ */
+typedef int32_t (*f_get)(struct list_desc *list_desc, void **data);
+
+/** @} */
+
+/**
+ * @enum adapter_type
+ * @brief Selects functionalities for functions in \ref list_desc
+ */
+enum adapter_type {
+	/** Default type is LIST_STACK */
+	LIST_DEFAULT,
+	/**
+	 * Functions for a FIFO list (First-in first-out). Elements are inserted
+	 * in one end and extracted from the other end.
+	 *  - \e Push: Insert element
+	 *  - \e Pop: Get next element (Read and remove)
+	 *  - \e Top_next: Read next element
+	 *  - \e Back: Read first element
+	 *  - \e Swap: Edit the content of the next element
+	 */
+	LIST_QUEUE,
+	/**
+	 * Functions for a LIFO list (Last-in first-out). Elements are inserted
+	 * and extracted only from the same end.
+	 *  - \e Push: Insert element
+	 *  - \e Pop: Get top element (Read and remove)
+	 *  - \e Top_next: Read top element
+	 *  - \e Back: Read bottom element
+	 *  - \e Swap: Edit the content of the top element
+	 */
+	LIST_STACK,
+	/**
+	 * Functions for ordered list. The order of element is determinated
+	 * usinge the \ref f_cmp.
+	 *  - \e Push: Insert element
+	 *  - \e Pop: Get lowest element (Read and remove)
+	 *  - \e Top_next: Read lowest element
+	 *  - \e Back: Read the biggest element
+	 *  - \e Swap: Edit the lowest element
+	 */
+	LIST_PRIORITY_LIST
+};
+
+struct list_desc {
+	/** Refer to \ref adapter_type */
+	f_add	push;
+	/** Refer to \ref adapter_type */
+	f_get	pop;
+	/** Refer to \ref adapter_type */
+	f_read	top_next;
+	/** Refer to \ref adapter_type */
+	f_read	back;
+	/** Refer to \ref adapter_type */
+	f_edit	swap;
+	/** Structure storing the list internal parameters */
+	void	*priv_desc;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+int32_t list_init(struct list_desc **list_desc,
+			enum adapter_type type,
+			f_cmp comparator);
+int32_t list_remove(struct list_desc *list_desc);
+int32_t list_get_size(struct list_desc *list_desc,
+			    uint32_t *out_size);
+
+/**
+ * @name Iterator functions
+ * An iterator is used to iterate through the list. For a list, any number of
+ * iterators can be created. All must be removed before removing a list.
+ * @{
+ */
+int32_t iterator_init(struct iterator **iter,
+			    struct list_desc *list_desc,
+			    bool start);
+int32_t iterator_remove(struct iterator *iter);
+int32_t iterator_move(struct iterator *iter, int32_t steps);
+int32_t iterator_move_to_idx(struct iterator *iter, int32_t idx);
+int32_t iterator_find(struct iterator *iter, void *cmp_data);
+int32_t iterator_insert(struct iterator *iter, void *data,
+			      bool after);
+int32_t iterator_edit(struct iterator *iter, void *new_data);
+int32_t iterator_read(struct iterator *iter, void **data);
+int32_t iterator_get(struct iterator *iter, void **data);
+/** @}*/
+
+/**
+ * @name Operations on the ends of the list
+ * These functions will operate on the first or last element of the list
+ * @{
+ */
+int32_t list_add_first(struct list_desc *list_desc, void *data);
+int32_t list_edit_first(struct list_desc *list_desc,
+			      void *new_data);
+int32_t list_read_first(struct list_desc *list_desc, void **data);
+int32_t list_get_first(struct list_desc *list_desc, void **data);
+
+int32_t list_add_last(struct list_desc *list_desc, void *data);
+int32_t list_edit_last(struct list_desc *list_desc, void *new_data);
+int32_t list_read_last(struct list_desc *list_desc, void **data);
+int32_t list_get_last(struct list_desc *list_desc, void **data);
+/** @}*/
+
+/**
+ * @name Operations by index
+ * These functions use an index to identify the element in the list.
+ * @{
+ */
+int32_t list_add_idx(struct list_desc *list_desc, void *data,
+			   uint32_t idx);
+int32_t list_edit_idx(struct list_desc *list_desc, void *new_data,
+			    uint32_t idx);
+int32_t list_read_idx(struct list_desc *list_desc, void **data,
+			    uint32_t idx);
+int32_t list_get_idx(struct list_desc *list_desc, void **data,
+			   uint32_t idx);
+/** @}*/
+
+/**
+ * @name Operations by comparation
+ * These functions use the specified \ref f_cmp at \ref list_init to identify
+ * the element this will operate on.
+ * @{
+ */
+int32_t list_add_find(struct list_desc *list_desc, void *data);
+int32_t list_edit_find(struct list_desc *list_desc, void *new_data,
+			     void *cmp_data);
+int32_t list_read_find(struct list_desc *list_desc, void **data,
+			     void *cmp_data);
+int32_t list_get_find(struct list_desc *list_desc, void **data,
+			    void *cmp_data);
+/** @}*/
+
+#endif // _LIST_H_

df_datalink_ge/src/include/timer.h

@@ -0,0 +1,159 @@
+/***************************************************************************//**
+*   @file   timer.h
+*   @brief  Timer control module header.
+*   @author Andrei Drimbarean ([email protected])
+********************************************************************************
+* Copyright 2019(c) Analog Devices, Inc.
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*  - Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*  - Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in
+*    the documentation and/or other materials provided with the
+*    distribution.
+*  - Neither the name of Analog Devices, Inc. nor the names of its
+*    contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*  - The use of this software may or may not infringe the patent rights
+*    of one or more patent holders.  This license does not release you
+*    from the requirement that you obtain separate licenses from these
+*    patent holders to use this software.
+*  - Use of the software either in source or binary form, must be run
+*    on or directly connected to an Analog Devices Inc. component.
+*
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef _SRC_TIMER_H_
+#define _SRC_TIMER_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @struct timer_desc
+ * @brief Structure holding timer descriptor
+ */
+struct timer_desc {
+	/** timer ID */
+	uint16_t id;
+	/** timer count frequency (Hz) */
+	uint32_t freq_hz;
+	/** the number of ticks the timer counts until it resets */
+	uint32_t ticks_count;
+	/** Timer platform operations */
+	const struct timer_platform_ops *platform_ops;
+	/** timer extra parameters (device specific) */
+	void *extra;
+};
+
+/**
+ * @struct timer_platform_ops
+ * @brief Structure holding timer function pointers that point to the platform
+ * specific function
+ */
+struct timer_platform_ops ;
+
+/**
+ * @struct timer_init_param
+ * @brief  Structure holding the parameters for timer initialization
+ */
+struct timer_init_param {
+	/** timer ID */
+	uint16_t id;
+	/** timer count frequency (Hz) */
+	uint32_t freq_hz;
+	/** the number of ticks the timer counts until it resets */
+	uint32_t ticks_count;
+	/** Timer platform operations */
+	const struct timer_platform_ops *platform_ops;
+	/** timer extra parameters (device specific) */
+	void *extra;
+};
+
+/**
+ * @struct timer_platform_ops
+ * @brief Structure holding timer function pointers that point to the platform
+ * specific function
+ */
+struct timer_platform_ops {
+	/** timer initialization function pointer */
+	int32_t (*init)(struct timer_desc **,
+			const struct timer_init_param *);
+	/** timer start function pointer */
+	int32_t (*start)(struct timer_desc *);
+	/** timer stop function pointer */
+	int32_t (*stop)(struct timer_desc *);
+	/** timer get counter function pointer */
+	int32_t (*counter_get)(struct timer_desc *, uint32_t *counter);
+	/** timer set counter function pointer */
+	int32_t (*counter_set)(struct timer_desc *, uint32_t new_val);
+	/** timer get clock frequency function pointer */
+	int32_t (*count_clk_get)(struct timer_desc *, uint32_t *freq_hz);
+	/** timer set clock frequency function pointer */
+	int32_t (*count_clk_set)(struct timer_desc *, uint32_t freq_hz);
+	/** timer get elapsed time in nsec */
+	int32_t (*get_elapsed_time_nsec)(struct timer_desc *,
+					 uint64_t *elapsed_time);
+	/** timer remove function pointer */
+	int32_t (*remove)(struct timer_desc *);
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Initialize hardware timer and the handler structure associated with it. */
+int32_t timer_init(struct timer_desc **desc,
+			 struct timer_init_param *param);
+
+/* Free the memory allocated by timer_setup(). */
+int32_t timer_remove(struct timer_desc *desc);
+
+/* Start a timer. */
+int32_t timer_start(struct timer_desc *desc);
+
+/* Stop a timer from counting. */
+int32_t timer_stop(struct timer_desc *desc);
+
+/* Get the value of the counter register for the timer. */
+int32_t timer_counter_get(struct timer_desc *desc,
+				uint32_t *counter);
+
+/* Set the timer counter register value. */
+int32_t timer_counter_set(struct timer_desc *desc,
+				uint32_t new_val);
+
+/* Get the timer clock frequency. */
+int32_t timer_count_clk_get(struct timer_desc *desc,
+				  uint32_t *freq_hz);
+
+/* Set the timer clock frequency. */
+int32_t timer_count_clk_set(struct timer_desc *desc,
+				  uint32_t freq_hz);
+
+/* Get the elapsed time in nsec for the timer. */
+int32_t timer_get_elapsed_time_nsec(struct timer_desc *desc,
+		uint64_t *elapsed_time);
+
+#endif // _SRC_TIMER_H_

df_datalink_ge/src/include/trng.h

@@ -0,0 +1,115 @@
+/***************************************************************************//**
+ *   @file   trng.h
+ *   @brief  Header file of true random number generator
+ *   @author Mihail Chindris ([email protected])
+********************************************************************************
+ *   @copyright
+ * Copyright 2020(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef _TRNG_H_
+#define _TRNG_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @struct trng_platform_ops
+ * @brief Structure holding TRNG function pointers that point to the platform
+ * specific function
+ */
+struct trng_platform_ops;
+
+/**
+ * @struct trng_desc
+ * @brief TRNG Descriptor
+ */
+struct trng_desc {
+	/** Platform ops */
+	const struct trng_platform_ops *platform_ops;
+	/** Platform specific parameters */
+	void *extra;
+};
+
+/**
+ * @struct trng_init_param
+ * @brief Init parameter for TRNG
+ */
+struct trng_init_param {
+	/** Device id */
+	uint32_t	dev_id;
+	/** Platform specific parameter */
+	void		*extra;
+	/** Platform ops */
+	const struct trng_platform_ops *platform_ops;
+};
+
+/**
+ * @struct trng_platform_ops
+ * @brief Structure holding TRNG function pointers that point to the platform
+ * specific function
+ */
+struct trng_platform_ops {
+	/** TRNG initialization function pointer */
+	int (*init)(struct trng_desc **,
+		    const struct trng_init_param *);
+	/** Fill buffer with random numbers */
+	int (*fill_buffer)(struct trng_desc *, uint8_t *, uint32_t);
+	/** TRNG remove function pointer */
+	int (*remove)(struct trng_desc *);
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Initialize descriptor */
+int trng_init(struct trng_desc **desc,
+		    const struct trng_init_param *param);
+
+/* Free resources allocated in descriptor */
+int trng_remove(struct trng_desc *desc);
+
+/* Fill buffer with random numbers */
+int trng_fill_buffer(struct trng_desc *desc, uint8_t *buff,
+			   uint32_t len);
+
+#endif // _TRNG_H_

df_datalink_ge/src/include/util.h

@@ -0,0 +1,195 @@
+/*******************************************************************************
+ *   @file   util.h
+ *   @brief  Implementation of utility functions.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef __UTIL_H_
+#define __UTIL_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+// #define __CRC_LSB
+#define __BITSWAP_TABLE
+#define __CRC_LSB
+#define CRC16_INIT 0x0000
+#define CRC8_INIT 0x00
+
+#define BIT(x) (1 << (x))
+
+#define ARRAY_SIZE(x) \
+	(sizeof(x) / sizeof((x)[0]))
+
+#define DIV_ROUND_UP(x, y) \
+	(((x) + (y)-1) / (y))
+#define DIV_ROUND_CLOSEST(x, y) \
+	(((x) + (y) / 2) / (y))
+#define DIV_ROUND_CLOSEST_ULL(x, y) \
+	DIV_ROUND_CLOSEST(x, y)
+
+#define min(x, y) \
+	(((x) < (y)) ? (x) : (y))
+#define min_t(type, x, y) \
+	(type) min((type)(x), (type)(y))
+
+#define max(x, y) \
+	(((x) > (y)) ? (x) : (y))
+#define max_t(type, x, y) \
+	(type) max((type)(x), (type)(y))
+
+#define clamp(val, min_val, max_val) \
+	(max(min((val), (max_val)), (min_val)))
+#define clamp_t(type, val, min_val, max_val) \
+	(type) clamp((type)(val), (type)(min_val), (type)(max_val))
+
+#define swap(x, y)             \
+	{                          \
+		typeof(x) _tmp_ = (x); \
+		(x) = (y);             \
+		(y) = _tmp_;           \
+	}
+
+#define round_up(x, y) \
+	(((x) + (y)-1) / (y))
+
+#define BITS_PER_LONG 32
+
+#define GENMASK(h, l) ({                    \
+	uint32_t t = (uint32_t)(~0UL);          \
+	t = t << (BITS_PER_LONG - (h - l + 1)); \
+	t = t >> (BITS_PER_LONG - (h + 1));     \
+	t;                                      \
+})
+
+#define bswap_constant_32(x)                                  \
+	((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >> 8) | \
+	 (((x) & 0x0000ff00) << 8) | (((x) & 0x000000ff) << 24))
+
+#define bswap_constant_16(x) ((((x) & (uint16_t)0xff00) >> 8) | \
+							  (((x) & (uint16_t)0x00ff) << 8))
+
+#define bit_swap_constant_8(x) \
+	((((x) & 0x80) >> 7) |     \
+	 (((x) & 0x40) >> 5) |     \
+	 (((x) & 0x20) >> 3) |     \
+	 (((x) & 0x10) >> 1) |     \
+	 (((x) & 0x08) << 1) |     \
+	 (((x) & 0x04) << 3) |     \
+	 (((x) & 0x02) << 5) |     \
+	 (((x) & 0x01) << 7))
+
+#define U16_MAX ((uint16_t)~0U)
+#define S16_MAX ((int16_t)(U16_MAX >> 1))
+
+#define DIV_U64(x, y) (x / y)
+
+#define UNUSED_PARAM(x) ((void)x)
+
+#define shift_right(x, s) ((x) < 0 ? -(-(x) >> (s)) : (x) >> (s))
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+void IO_Out32(uintptr_t addr, uint32_t value);
+uint32_t IO_In32(uintptr_t addr);
+
+/* flip a byte left to right*/
+uint8_t byte_bit_swap(uint8_t byte);
+
+/* flip a 32bit word left to right */
+uint32_t word_bit_swap(uint32_t word);
+
+/* Returns the number of 1-bits in digit. */
+uint32_t count_ones(uint32_t word);
+
+/* convert a fixed number to a double. */
+double fix2double(int32_t val, uint8_t frac_bits);
+
+/* Find first set bit in word. */
+uint32_t find_first_set_bit(uint32_t word);
+/* Find last set bit in word. */
+uint32_t find_last_set_bit(uint32_t word);
+/* Locate the closest element in an array. */
+uint32_t find_closest(int32_t val,
+					  const int32_t *array,
+					  uint32_t size);
+/* Shift the value and apply the specified mask. */
+uint32_t field_prep(uint32_t mask, uint32_t val);
+/* Get a field specified by a mask from a word. */
+uint32_t field_get(uint32_t mask, uint32_t word);
+/* Log base 2 of the given number. */
+int32_t log_base_2(uint32_t x);
+/* Find greatest common divisor of the given two numbers. */
+uint32_t greatest_common_divisor(uint32_t a,
+								 uint32_t b);
+/* Calculate best rational approximation for a given fraction. */
+void rational_best_approximation(uint32_t given_numerator,
+								 uint32_t given_denominator,
+								 uint32_t max_numerator,
+								 uint32_t max_denominator,
+								 uint32_t *best_numerator,
+								 uint32_t *best_denominator);
+/* Calculate the number of set bits. */
+uint32_t hweight8(uint32_t word);
+/* Calculate the quotient and the remainder of an integer division. */
+uint64_t do_div(uint64_t *n,
+				uint64_t base);
+/* Unsigned 64bit divide with 64bit divisor and remainder */
+uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor,
+					   uint64_t *remainder);
+/* Unsigned 64bit divide with 32bit divisor with remainder */
+uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder);
+int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder);
+/* Unsigned 64bit divide with 32bit divisor */
+uint64_t div_u64(uint64_t dividend, uint32_t divisor);
+int64_t div_s64(int64_t dividend, int32_t divisor);
+/* Converts from string to int32_t */
+int32_t str_to_int32(const char *str);
+/* Converts from string to uint32_t */
+uint32_t srt_to_uint32(const char *str);
+
+int crc16_gen(uint8_t *buffPtr, uint32_t dataLen, uint16_t poly, uint16_t *crcVal);
+bool crc16_check(uint8_t *buffPtr, uint32_t dataLen, uint32_t crcOffset, uint16_t poly);
+int crc8_gen(uint8_t *buffPtr, uint32_t dataLen, uint16_t poly, uint8_t *crcVal);
+bool crc8_check(uint8_t *buffPtr, uint32_t dataLen, uint32_t crcOffset, uint16_t poly);
+#endif // __UTIL_H_

df_datalink_ge/src/lscript.ld

@@ -0,0 +1,292 @@
+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version: 2019.1.3                                               */
+/*                                                                 */
+/* Copyright (c) 2010-2016 Xilinx, Inc.  All rights reserved.      */
+/*                                                                 */
+/* Description : Cortex-A9 Linker Script                           */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x40000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x800000;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   phy_data_interface_tx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
+   phy_data_interface_ant_info_bram_ctrl_Mem0 : ORIGIN = 0x42000000, LENGTH = 0x2000
+   mpc_bram_interface_mpc_bram_ctrl_Mem0 : ORIGIN = 0x44000000, LENGTH = 0x8000
+   phy_data_interface_rx_frame_bram_ctrl_Mem0 : ORIGIN = 0x46000000, LENGTH = 0x2000
+   ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
+   ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
+   ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
+   ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+   KEEP (*(.vectors))
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.vfp11_veneer)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+} > ps7_ddr_0
+
+.init : {
+   KEEP (*(.init))
+} > ps7_ddr_0
+
+.fini : {
+   KEEP (*(.fini))
+} > ps7_ddr_0
+
+.rodata : {
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > ps7_ddr_0
+
+.rodata1 : {
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > ps7_ddr_0
+
+.sdata2 : {
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   __sdata2_end = .;
+} > ps7_ddr_0
+
+.sbss2 : {
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > ps7_ddr_0
+
+.data : {
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   __data_end = .;
+} > ps7_ddr_0
+
+.data1 : {
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > ps7_ddr_0
+
+.got : {
+   *(.got)
+} > ps7_ddr_0
+
+.ctors : {
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > ps7_ddr_0
+
+.dtors : {
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > ps7_ddr_0
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > ps7_ddr_0
+
+.eh_frame : {
+   *(.eh_frame)
+} > ps7_ddr_0
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > ps7_ddr_0
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > ps7_ddr_0
+
+.mmu_tbl (ALIGN(16384)) : {
+   __mmu_tbl_start = .;
+   *(.mmu_tbl)
+   __mmu_tbl_end = .;
+} > ps7_ddr_0
+
+.ARM.exidx : {
+   __exidx_start = .;
+   *(.ARM.exidx*)
+   *(.gnu.linkonce.armexidix.*.*)
+   __exidx_end = .;
+} > ps7_ddr_0
+
+.preinit_array : {
+   __preinit_array_start = .;
+   KEEP (*(SORT(.preinit_array.*)))
+   KEEP (*(.preinit_array))
+   __preinit_array_end = .;
+} > ps7_ddr_0
+
+.init_array : {
+   __init_array_start = .;
+   KEEP (*(SORT(.init_array.*)))
+   KEEP (*(.init_array))
+   __init_array_end = .;
+} > ps7_ddr_0
+
+.fini_array : {
+   __fini_array_start = .;
+   KEEP (*(SORT(.fini_array.*)))
+   KEEP (*(.fini_array))
+   __fini_array_end = .;
+} > ps7_ddr_0
+
+.ARM.attributes : {
+   __ARM.attributes_start = .;
+   *(.ARM.attributes)
+   __ARM.attributes_end = .;
+} > ps7_ddr_0
+
+.sdata : {
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > ps7_ddr_0
+
+.sbss (NOLOAD) : {
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   __sbss_end = .;
+} > ps7_ddr_0
+
+.tdata : {
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > ps7_ddr_0
+
+.tbss : {
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > ps7_ddr_0
+
+.bss (NOLOAD) : {
+   __bss_start = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   __bss_end = .;
+} > ps7_ddr_0
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(16);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+   HeapLimit = .;
+} > ps7_ddr_0
+
+.stack (NOLOAD) : {
+   . = ALIGN(16);
+   _stack_end = .;
+   . += _STACK_SIZE;
+   . = ALIGN(16);
+   _stack = .;
+   __stack = _stack;
+   . = ALIGN(16);
+   _irq_stack_end = .;
+   . += _IRQ_STACK_SIZE;
+   . = ALIGN(16);
+   __irq_stack = .;
+   _supervisor_stack_end = .;
+   . += _SUPERVISOR_STACK_SIZE;
+   . = ALIGN(16);
+   __supervisor_stack = .;
+   _abort_stack_end = .;
+   . += _ABORT_STACK_SIZE;
+   . = ALIGN(16);
+   __abort_stack = .;
+   _fiq_stack_end = .;
+   . += _FIQ_STACK_SIZE;
+   . = ALIGN(16);
+   __fiq_stack = .;
+   _undef_stack_end = .;
+   . += _UNDEF_STACK_SIZE;
+   . = ALIGN(16);
+   __undef_stack = .;
+} > ps7_ddr_0
+
+_end = .;
+}
+

df_datalink_ge/src/main.c

@@ -0,0 +1,505 @@
+/*****************************************************************************/
+/**
+ * Description: main.c
+ *
+
+ * Date: 2021-11-13 13:19
+ * Last Editors: Fan Hao
+ * Last Edit Time: [2022-03-28 20:32]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2021-11-13]: Initial edition.
+ * [2022-03-28]: Add bit error test mode.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+// Standard
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+// Xilinx
+#include "sleep.h"
+#include "xil_cache.h"
+#include "xscugic.h"
+#include "xscutimer.h"
+#include "xgpiops.h"
+#include "drivers/platform/xilinx_irq.h"
+#include "drivers/platform/xilinx_timer.h"
+// App
+#include "common.h"
+#include "error.h"
+#include "timer.h"
+#include "config/app_config.h"
+#include "dev_profile/dev_profile.h"
+#include "systembus/systembus.h"
+#include "networking/phy_layer/phy_layer.h"
+#include "networking/link_layer/link_layer.h"
+// RF-Driver
+#include "hardware/headless.h"
+#include "hardware/platform_drivers.h"
+
+/************************** Function Prototypes ******************************/
+int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr);
+void Phy_IntrHandler(void *context);
+void PeriodicPull_Handler(void *callBackRef);
+void ScuTimer_IntrHandler(void *context);
+void Systembus_RxIntrHandler(void *context);
+/************************** Constant Definitions *****************************/
+struct callback_desc phy_callback_desc = {
+	.callback = Phy_IntrHandler,
+	.ctx = NULL
+};
+
+struct callback_desc periodicpull_callback_desc = {
+	.callback = PeriodicPull_Handler,
+	.ctx = NULL
+};
+
+
+struct callback_desc sysbus_rx_callback_desc = {
+	.callback = Systembus_RxIntrHandler,
+	.ctx = NULL
+};
+
+struct callback_desc sysbus_tx_callback_desc = {
+	.callback = Systembus_RxIntrHandler,
+	.ctx = NULL
+};
+
+struct callback_desc scutm_callback_desc = {
+	.callback = ScuTimer_IntrHandler,
+	.ctx = NULL
+};
+
+static L2_CONFIG linkConfig = {
+	.myType = L2_NODE_HEAD,
+	.clustId = 1,
+	.myId = 1,
+	.headId = 1,
+	.bkpHeadId = 0,
+	.netScale = 2,
+	.phyInstPtr = NULL, // pyhsical layer reference
+	.tmcInstPtr = NULL
+};
+
+// static L2_CONFIG linkConfig = {
+// 	.myType = L2_NODE_MEMBER,
+// 	.clustId = 1,
+// 	.myId = 2,
+// 	.headId = 1,
+// 	.bkpHeadId = 0,
+// 	.netScale = 2,
+// 	.phyInstPtr = NULL, // pyhsical layer reference
+// 	.tmcInstPtr = NULL
+// };
+
+static PHY_CONFIG phyConfig = {
+	.devId = 0,
+	.baseAddr = PHY_BASEADDR,
+	.antBramId = PHY_ANTCONFIG_BRAM_DEVICE_ID,
+	.txBramId = PHY_TXBUFF_BRAM_DEVICE_ID,
+	.rxBramId = PHY_RXBUFF_BRAM_DEVICE_ID,
+	.hwXadcId = PHY_HW_XADC_DEVICE_ID
+};
+
+TIMECTRL_CONFIG tmcConfig = {
+	.baseAddr = 0, //TIME_CONTROLLER_BASEADDR,
+	.reset = 10
+};
+
+//static SYSBUS_CONFIG sysbusConfig = {
+//	.baseAddr = SYSBUS_BASE_ADDR,
+//	.txQueueMax = 16,
+//	.rxQueueMax = 16
+//};
+/************************** Function Prototypes ******************************/
+static struct irq_ctrl_desc *intcDescPtr; // General interrupt controller descriptor
+static struct timer_desc *logTmPtr;
+static SYSBUS *sysbusDescPtr;
+static PHY_INST *phyInstPtr;
+static TIMECTRL_INST *tmcInstPtr = NULL;
+static L2_INST *linkInstPtr;
+
+/****************************************************************************/
+/**
+ * This function is responsible for initializing the SCUGIC instance, looking
+ * for the device configuration based on the unique device ID, initializing a
+ * SCUGIC instance, and initialize the interrupt at IRQ_F2P[0:0]
+ *
+ * @param    intcDesc	A pointer to INTC descriptor
+ *
+ * @return  SUCCESS if initialize successful.
+ *          FAILURE if initialization failed.
+ *
+ *****************************************************************************/
+int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
+{
+	int32_t Status;
+	struct xil_irq_desc *xil_dev;
+
+	Status = irq_ctrl_init(&descPtr, &intc_init_param);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("Intc Init FAILED, ErrorCode: %ld.\n", Status);
+		return Status;
+	}
+
+	xil_dev = (struct xil_irq_desc *)(descPtr->extra);
+
+	// Clear any pending interrupt flags
+	uint32_t intrState = XScuGic_CPUReadReg((XScuGic *)(xil_dev->instance), XSCUGIC_INT_ACK_OFFSET);
+	XScuGic_CPUWriteReg((XScuGic *)(xil_dev->instance), XSCUGIC_EOI_OFFSET, intrState);
+
+	/* Initialize physical layer interrupt. */
+	Status = irq_trigger_level_set(descPtr, PHY_INTR_ID, IRQ_EDGE_RISING);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("PHY_INTR trigger level set FAILED, ErrorCode: %ld.\n", Status);
+		return Status;
+	}
+	// Set highest interrupt priority
+	Status = irq_set_priority(descPtr, PHY_INTR_ID, 0x08);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("PHY_INTR priority level set FAILED, ErrorCode: %ld.\n", Status);
+		return Status;
+	}
+	// Connect the interrupt service routine isr1 to the interrupt controller
+	Status = irq_register_callback(descPtr, PHY_INTR_ID, &phy_callback_desc);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
+		return Status;
+	}
+
+		/* Initialize linklayer layer interrupt. */
+	Status = irq_trigger_level_set(descPtr, PERIODIC_5MS_INTR_ID, IRQ_EDGE_RISING);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("PERIODIC_5MS_INTR_ID trigger level set FAILED, ErrorCode: %ld.\n", Status);
+		return Status;
+	}
+	// Set highest interrupt priority
+	Status = irq_set_priority(descPtr, PERIODIC_5MS_INTR_ID, 0x00);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("PERIODIC_5MS_INTR_ID priority level set FAILED, ErrorCode: %ld.\n", Status);
+		return Status;
+	}
+	// Connect the interrupt service routine isr1 to the interrupt controller
+	Status = irq_register_callback(descPtr, PHY_INTR_ID, &periodicpull_callback_desc);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
+		return Status;
+	}
+
+//	/* Initialize system bus interrupt. */
+//	Status = irq_trigger_level_set(descPtr, SYSBUS_TX_INTR_ID, IRQ_EDGE_RISING);
+//	if (Status != SUCCESS)
+//	{
+//		DBG_ERROR("PHY_INTR trigger level set FAILED, ErrorCode: %ld.\n", Status);
+//		return Status;
+//	}
+//	// Set interrupt priority
+//	Status = irq_set_priority(descPtr, SYSBUS_TX_INTR_ID, 0x10);
+//	if (Status != SUCCESS)
+//	{
+//		DBG_ERROR("PHY_INTR priority level set FAILED, ErrorCode: %ld.\n", Status);
+//		return Status;
+//	}
+//
+//	// Connect the interrupt service routine isr1 to the interrupt controller
+//	Status = irq_register_callback(descPtr, SYSBUS_TX_INTR_ID, &sysbus_tx_callback_desc);
+//	if (Status != SUCCESS)
+//	{
+//		DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
+//		return Status;
+//	}
+//	Status = irq_trigger_level_set(descPtr, SYSBUS_RX_INTR_ID, IRQ_EDGE_RISING);
+//	if (Status != SUCCESS)
+//	{
+//		DBG_ERROR("PHY_INTR trigger level set FAILED, ErrorCode: %ld.\n", Status);
+//		return Status;
+//	}
+//	// Set interrupt priority
+//	Status = irq_set_priority(descPtr, SYSBUS_RX_INTR_ID, 0x18);
+//	if (Status != SUCCESS)
+//	{
+//		DBG_ERROR("PHY_INTR priority level set FAILED, ErrorCode: %ld.\n", Status);
+//		return Status;
+//	}
+//
+//	// Connect the interrupt service routine isr1 to the interrupt controller
+//	Status = irq_register_callback(descPtr, SYSBUS_RX_INTR_ID, &sysbus_rx_callback_desc);
+//	if (Status != SUCCESS)
+//	{
+//		DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
+//		return Status;
+//	}
+//
+//	/* Initialize Scu timer interrupt. */
+//	// Connect the interrupt service routine isr1 to the interrupt controller
+//	Status = irq_register_callback(descPtr, SCUTIMER_INTR_ID, &scutm_callback_desc);
+//	if (Status != SUCCESS)
+//	{
+//		DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
+//		return Status;
+//	}
+
+	// Enable interrupts
+	irq_enable(descPtr, PHY_INTR_ID);
+	irq_enable(descPtr, PERIODIC_5MS_INTR_ID);
+//	irq_enable(descPtr, SYSBUS_RX_INTR_ID);
+//	irq_enable(descPtr, SYSBUS_TX_INTR_ID);
+	irq_enable(descPtr, SCUTIMER_INTR_ID);
+
+	// Enable Exceptions
+	Status = irq_global_enable(descPtr);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("IRQ global enable FAILED, ErrorCode: %ld.\n", Status);
+		return Status;
+	}
+	return SUCCESS;
+} // SetupInterruptSystem
+
+/****************************************************************************/
+/**
+ * This function is a interrupt service routine for IRQ_F2P[1:1], IRQ_F2P[1:1]
+ * tells CPU that the data in OCM is ready!
+ *
+ * @param    context
+ *
+ * @return   None.
+ *
+ *****************************************************************************/
+void Phy_IntrHandler(void *context)
+{
+	Phy_UpdateState(phyInstPtr);
+} // PhyIntr_Handler
+
+
+/****************************************************************************/
+/**
+ * Handler of periodic 5ms interrupt
+ *
+ * @param    callBackRef is the linklayer instance pointer.
+ *
+ * @return   None.
+ *
+ *****************************************************************************/
+void PeriodicPull_Handler(void *callBackRef)
+{
+	int32_t Status;
+	Status = Linklayer_Proc(linkInstPtr);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("Link layer runs failed, with error code: %ld\n", Status);
+		_nop_();
+	}
+} // PeriodicPull_Handler
+
+/*****************************************************************************/
+/**
+ * @brief   Handler of System Bus RX done interrupt.
+ *
+ * @param   context
+ *
+ * @return  None.
+ *
+ ******************************************************************************/
+void Systembus_RxIntrHandler(void *context)
+{
+	int32_t Status;
+	Status = SystemBus_RxIntrHandler(sysbusDescPtr);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("SystemBus_RxIntrHandler exit with error code %ld,\n", Status);
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Handler of System Bus TX done interrupt.
+ *
+ * @param   context
+ *
+ * @return  None.
+ *
+ ******************************************************************************/
+void Systembus_TxIntrHandler(void *context)
+{
+	int32_t Status;
+	Status = SystemBus_TxIntrHandler(sysbusDescPtr);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("SystemBus_TxIntrHandler exit with error code %ld,\n", Status);
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Handler of ScuTimer interrupt.
+ *
+ * @param   context
+ *
+ * @return  None.
+ *
+ ******************************************************************************/
+void ScuTimer_IntrHandler(void *context)
+{
+	struct xil_timer_desc *xdesc;
+	xdesc = (struct xil_timer_desc *)(logTmPtr->extra);
+	if (XScuTimer_IsExpired((XScuTimer *)xdesc->instance))
+	{
+		// Update log
+		Phy_UpdateHwSate(phyInstPtr);
+		XScuTimer_ClearInterruptStatus((XScuTimer *)xdesc->instance);
+	}
+	else
+	{
+		DBG_WARNING("UNEXPECTED CALL of ScuTimer_IntrHandler\n");
+	}
+}
+
+/*****************************************************************************/
+/**
+ * @brief	Main function, initialize all the device needed, initialize
+ * 			interrupt system, halt in while(1) wait for event interrupt.
+ *
+ * @param   None.
+ *
+ * @return
+ *
+ ******************************************************************************/
+int main(void)
+{
+	int Status;
+	DBG_PRINT("Application Version: %2d.%2d.%4d.\n", _APP_VER_MAIN, _APP_VER_MINOR, _APP_VER_PATCH);
+
+	/* System Monitor Initialize */
+	Status = SysMonitor_Init();
+	if (Status == SUCCESS)
+	{
+		DBG_PRINT("System monitor Init SUCCESS! \n");
+	}
+	else
+	{
+		DBG_PRINT("System monitor Init FAILED! \n");
+		return Status;
+	}
+
+	Status = HARDWARE_initialize();
+	if (Status == SUCCESS)
+	{
+		DBG_PRINT("Hardware Init SUCCESS! \n");
+	}
+	else
+	{
+		DBG_PRINT("Hardware Init FAILED! \n");
+		return Status;
+	}
+
+	// Init time controller
+		Status = TimeCtrl_Init(&tmcInstPtr, &tmcConfig);
+		if (Status == SUCCESS)
+		{
+			DBG_PRINT("TmcCtrl Init SUCCESS! \n");
+		}
+		else
+		{
+			DBG_PRINT("TmcCtrl Init FAILED! \n");
+			return Status;
+		}
+
+		/* Physical Layer Initialize */
+		Status = Phy_InstInit(&phyInstPtr, &phyConfig);
+		if (Status == SUCCESS)
+		{
+			DBG_PRINT("Physical layer Init SUCCESS! \n");
+		}
+		else
+		{
+			DBG_PRINT("Physical layer FAILED! \n");
+			return Status;
+		}
+
+		/* Link Layer Initialize */
+		linkConfig.phyInstPtr = phyInstPtr;
+		linkConfig.tmcInstPtr = tmcInstPtr;
+		Status = Linklayer_Init(&linkInstPtr, &linkConfig);
+		if (Status == SUCCESS)
+		{
+			DBG_PRINT("LinkLayer Init SUCCESS! \n");
+		}
+		else
+		{
+			DBG_PRINT("Linklayer Init FAILED! \n");
+			return Status;
+		}
+
+//		/* System Bus Initialize */
+//		Status = SystemBus_Init(&sysbusDescPtr, &sysbusConfig);
+//		if (Status != SUCCESS)
+//		{
+//			DBG_ERROR("Systembus init FAILED, with error code: %d\n", Status);
+//			return Status;
+//		}
+
+		/* System Monitor log timer Initialize */
+		Status = timer_init(&logTmPtr, &scutimer_init_param);
+		if (Status != SUCCESS)
+		{
+			DBG_ERROR("SCU Timer init FAILED, with error code: %d\n", Status);
+			return Status;
+		}
+
+		/* interrupts Initialize */
+		Status = SetupInterruptSystem(intcDescPtr);
+		if (Status == SUCCESS)
+		{
+			DBG_INFO("Interrupt system setup SUCCESS!\n");
+		}
+		else
+		{
+			DBG_ERROR("Interrupt system setup FAILED, ErrorCode: %d.\n", Status);
+			return Status;
+		}
+
+		// Start System Monitor logging.
+		timer_start(logTmPtr);
+
+		DBG_PRINT("Physical started...\n");
+		Phy_Start(phyInstPtr);
+
+		Linklayer_Start(linkInstPtr);
+
+		while (true)
+		{
+			// System bus handler
+			if (SystemBus_IsReqPendding(sysbusDescPtr))
+			{
+				Status = SystemBus_HandleCmd(sysbusDescPtr);
+				if (Status != SUCCESS)
+				{
+					DBG_ERROR("SystemBus_HandleCmd exit with ErrorCode: %d.\n", Status);
+				}
+			}
+			if (SystemBus_IsRsqPendding(sysbusDescPtr) && (!SystemBus_IsTxBusy(sysbusDescPtr)))
+			{
+				// FIXME: Required by 12 (CASC)
+				udelay(200);
+				Status = SystemBus_MakeResp(sysbusDescPtr);
+				if (Status != SUCCESS)
+				{
+					DBG_ERROR("SystemBus_HandleCmd exit with ErrorCode: %d.\n", Status);
+				}
+			}
+		}
+} // main

df_datalink_ge/src/networking

@@ -0,0 +1 @@
+../../df_datalink_sp/src/networking

df_datalink_ge/src/system_monitor.c

@@ -0,0 +1 @@
+../../df_datalink_sp/src/system_monitor.c

df_datalink_ge/src/system_monitor.h

@@ -0,0 +1 @@
+../../df_datalink_sp/src/system_monitor.h

df_datalink_ge/src/systembus

@@ -0,0 +1 @@
+../../df_datalink_sp/src/systembus

df_datalink_ge/src/time_ctrl

@@ -0,0 +1 @@
+../../df_datalink_sp/src/time_ctrl

df_datalink_ge/src/util

@@ -0,0 +1 @@
+../../df_datalink_sp/src/util