feat: 完成地检工程的修改, mpc暂不可用
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#include "dev_profile.h"
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#include "../config/app_config.h"
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#include "../drivers/rf-transceiver/ad9361/ad9361_api.h"
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#include "../drivers/axi_core/spi_engine/spi_engine.h"
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#include "../drivers/platform/xilinx_gpio.h"
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struct spi_engine_init_param spi_engine_param = {
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.ref_clk_hz = AD9361_SPI_ENGINE_REF_CLK,
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.type = SPI_ENGINE,
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.spi_engine_baseaddr = AD9361_SPI_ENGINE_BASEADDR,
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.cs_delay = AD9361_SPI_ENGINE_CS_DELAY,
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.data_width = AD9361_SPI_ENGINE_DATA_WIDTH
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};
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struct xil_gpio_init_param xil_gpio_param = {
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.type = GPIO_PS,
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.device_id = AD9361_GPIO_DEVICE_ID
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};
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AD9361_InitParam ad9361_default_init_param = {
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/* Device selection */
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ID_AD9361, // dev_sel
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/* Reference Clock */
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48000000UL, //reference_clk_rate
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/* Base Configuration */
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1, //two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable
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1, //one_rx_one_tx_mode_use_rx_num *** adi,1rx-1tx-mode-use-rx-num
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1, //one_rx_one_tx_mode_use_tx_num *** adi,1rx-1tx-mode-use-tx-num
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1, //frequency_division_duplex_mode_enable *** adi,frequency-division-duplex-mode-enable
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0, //frequency_division_duplex_independent_mode_enable *** adi,frequency-division-duplex-independent-mode-enable
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0, //tdd_use_dual_synth_mode_enable *** adi,tdd-use-dual-synth-mode-enable
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0, //tdd_skip_vco_cal_enable *** adi,tdd-skip-vco-cal-enable
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0, //tx_fastlock_delay_ns *** adi,tx-fastlock-delay-ns
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0, //rx_fastlock_delay_ns *** adi,rx-fastlock-delay-ns
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0, //rx_fastlock_pincontrol_enable *** adi,rx-fastlock-pincontrol-enable
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0, //tx_fastlock_pincontrol_enable *** adi,tx-fastlock-pincontrol-enable
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0, //external_rx_lo_enable *** adi,external-rx-lo-enable
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0, //external_tx_lo_enable *** adi,external-tx-lo-enable
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5, //dc_offset_tracking_update_event_mask *** adi,dc-offset-tracking-update-event-mask
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6, //dc_offset_attenuation_high_range *** adi,dc-offset-attenuation-high-range
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5, //dc_offset_attenuation_low_range *** adi,dc-offset-attenuation-low-range
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0x28, //dc_offset_count_high_range *** adi,dc-offset-count-high-range
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0x32, //dc_offset_count_low_range *** adi,dc-offset-count-low-range
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0, //split_gain_table_mode_enable *** adi,split-gain-table-mode-enable
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MAX_SYNTH_FREF, //trx_synthesizer_target_fref_overwrite_hz *** adi,trx-synthesizer-target-fref-overwrite-hz
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0, // qec_tracking_slow_mode_enable *** adi,qec-tracking-slow-mode-enable
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/* ENSM Control */
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0, //ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable
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0, //ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable
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/* LO Control */
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4125000000UL, //rx_synthesizer_frequency_hz *** adi,rx-synthesizer-frequency-hz
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4126000000UL, //tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz
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1, //tx_lo_powerdown_managed_enable *** adi,tx-lo-powerdown-managed-enable
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/* Rate & BW Control */
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{768000000, 192000000, 96000000, 48000000, 24000000, 24000000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
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{768000000, 192000000, 96000000, 48000000, 24000000, 24000000},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies
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18000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz
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18000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz
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/* RF Port Control */
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0, //rx_rf_port_input_select *** adi,rx-rf-port-input-select
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0, //tx_rf_port_input_select *** adi,tx-rf-port-input-select
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/* TX Attenuation Control */
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10000, //tx_attenuation_mdB *** adi,tx-attenuation-mdB
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0, //update_tx_gain_in_alert_enable *** adi,update-tx-gain-in-alert-enable
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/* Reference Clock Control */
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0, //xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable
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{8, 5920}, //dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune
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CLKOUT_DISABLE, //clk_output_mode_select *** adi,clk-output-mode-select
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/* Gain Control */
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2, //gc_rx1_mode *** adi,gc-rx1-mode
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2, //gc_rx2_mode *** adi,gc-rx2-mode
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58, //gc_adc_large_overload_thresh *** adi,gc-adc-large-overload-thresh
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4, //gc_adc_ovr_sample_size *** adi,gc-adc-ovr-sample-size
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47, //gc_adc_small_overload_thresh *** adi,gc-adc-small-overload-thresh
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8192, //gc_dec_pow_measurement_duration *** adi,gc-dec-pow-measurement-duration
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0, //gc_dig_gain_enable *** adi,gc-dig-gain-enable
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800, //gc_lmt_overload_high_thresh *** adi,gc-lmt-overload-high-thresh
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704, //gc_lmt_overload_low_thresh *** adi,gc-lmt-overload-low-thresh
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24, //gc_low_power_thresh *** adi,gc-low-power-thresh
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15, //gc_max_dig_gain *** adi,gc-max-dig-gain
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0, //gc_use_rx_fir_out_for_dec_pwr_meas_enable *** adi,gc-use-rx-fir-out-for-dec-pwr-meas-enable
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/* Gain MGC Control */
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2, //mgc_dec_gain_step *** adi,mgc-dec-gain-step
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2, //mgc_inc_gain_step *** adi,mgc-inc-gain-step
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0, //mgc_rx1_ctrl_inp_enable *** adi,mgc-rx1-ctrl-inp-enable
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0, //mgc_rx2_ctrl_inp_enable *** adi,mgc-rx2-ctrl-inp-enable
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0, //mgc_split_table_ctrl_inp_gain_mode *** adi,mgc-split-table-ctrl-inp-gain-mode
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/* Gain AGC Control */
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10, //agc_adc_large_overload_exceed_counter *** adi,agc-adc-large-overload-exceed-counter
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2, //agc_adc_large_overload_inc_steps *** adi,agc-adc-large-overload-inc-steps
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0, //agc_adc_lmt_small_overload_prevent_gain_inc_enable *** adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable
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10, //agc_adc_small_overload_exceed_counter *** adi,agc-adc-small-overload-exceed-counter
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4, //agc_dig_gain_step_size *** adi,agc-dig-gain-step-size
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3, //agc_dig_saturation_exceed_counter *** adi,agc-dig-saturation-exceed-counter
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1000, // agc_gain_update_interval_us *** adi,agc-gain-update-interval-us
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0, //agc_immed_gain_change_if_large_adc_overload_enable *** adi,agc-immed-gain-change-if-large-adc-overload-enable
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0, //agc_immed_gain_change_if_large_lmt_overload_enable *** adi,agc-immed-gain-change-if-large-lmt-overload-enable
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10, //agc_inner_thresh_high *** adi,agc-inner-thresh-high
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1, //agc_inner_thresh_high_dec_steps *** adi,agc-inner-thresh-high-dec-steps
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12, //agc_inner_thresh_low *** adi,agc-inner-thresh-low
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1, //agc_inner_thresh_low_inc_steps *** adi,agc-inner-thresh-low-inc-steps
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10, //agc_lmt_overload_large_exceed_counter *** adi,agc-lmt-overload-large-exceed-counter
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2, //agc_lmt_overload_large_inc_steps *** adi,agc-lmt-overload-large-inc-steps
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10, //agc_lmt_overload_small_exceed_counter *** adi,agc-lmt-overload-small-exceed-counter
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5, //agc_outer_thresh_high *** adi,agc-outer-thresh-high
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2, //agc_outer_thresh_high_dec_steps *** adi,agc-outer-thresh-high-dec-steps
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18, //agc_outer_thresh_low *** adi,agc-outer-thresh-low
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2, //agc_outer_thresh_low_inc_steps *** adi,agc-outer-thresh-low-inc-steps
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1, //agc_attack_delay_extra_margin_us; *** adi,agc-attack-delay-extra-margin-us
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0, //agc_sync_for_gain_counter_enable *** adi,agc-sync-for-gain-counter-enable
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/* Fast AGC */
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64, //fagc_dec_pow_measuremnt_duration *** adi,fagc-dec-pow-measurement-duration
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260, //fagc_state_wait_time_ns *** adi,fagc-state-wait-time-ns
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/* Fast AGC - Low Power */
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0, //fagc_allow_agc_gain_increase *** adi,fagc-allow-agc-gain-increase-enable
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5, //fagc_lp_thresh_increment_time *** adi,fagc-lp-thresh-increment-time
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1, //fagc_lp_thresh_increment_steps *** adi,fagc-lp-thresh-increment-steps
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/* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */
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1, //fagc_lock_level_lmt_gain_increase_en *** adi,fagc-lock-level-lmt-gain-increase-enable
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5, //fagc_lock_level_gain_increase_upper_limit *** adi,fagc-lock-level-gain-increase-upper-limit
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/* Fast AGC - Peak Detectors and Final Settling */
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1, //fagc_lpf_final_settling_steps *** adi,fagc-lpf-final-settling-steps
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1, //fagc_lmt_final_settling_steps *** adi,fagc-lmt-final-settling-steps
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3, //fagc_final_overrange_count *** adi,fagc-final-overrange-count
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/* Fast AGC - Final Power Test */
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0, //fagc_gain_increase_after_gain_lock_en *** adi,fagc-gain-increase-after-gain-lock-enable
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/* Fast AGC - Unlocking the Gain */
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0, //fagc_gain_index_type_after_exit_rx_mode *** adi,fagc-gain-index-type-after-exit-rx-mode
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1, //fagc_use_last_lock_level_for_set_gain_en *** adi,fagc-use-last-lock-level-for-set-gain-enable
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1, //fagc_rst_gla_stronger_sig_thresh_exceeded_en *** adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable
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5, //fagc_optimized_gain_offset *** adi,fagc-optimized-gain-offset
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10, //fagc_rst_gla_stronger_sig_thresh_above_ll *** adi,fagc-rst-gla-stronger-sig-thresh-above-ll
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1, //fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en *** adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable
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1, //fagc_rst_gla_engergy_lost_goto_optim_gain_en *** adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable
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10, //fagc_rst_gla_engergy_lost_sig_thresh_below_ll *** adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll
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8, //fagc_energy_lost_stronger_sig_gain_lock_exit_cnt *** adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt
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1, //fagc_rst_gla_large_adc_overload_en *** adi,fagc-rst-gla-large-adc-overload-enable
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1, //fagc_rst_gla_large_lmt_overload_en *** adi,fagc-rst-gla-large-lmt-overload-enable
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0, //fagc_rst_gla_en_agc_pulled_high_en *** adi,fagc-rst-gla-en-agc-pulled-high-enable
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0, //fagc_rst_gla_if_en_agc_pulled_high_mode *** adi,fagc-rst-gla-if-en-agc-pulled-high-mode
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64, //fagc_power_measurement_duration_in_state5 *** adi,fagc-power-measurement-duration-in-state5
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2, //fagc_large_overload_inc_steps *** adi,fagc-adc-large-overload-inc-steps
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/* RSSI Control */
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1, //rssi_delay *** adi,rssi-delay
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1000, //rssi_duration *** adi,rssi-duration
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3, //rssi_restart_mode *** adi,rssi-restart-mode
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0, //rssi_unit_is_rx_samples_enable *** adi,rssi-unit-is-rx-samples-enable
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1, //rssi_wait *** adi,rssi-wait
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/* Aux ADC Control */
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256, //aux_adc_decimation *** adi,aux-adc-decimation
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48000000UL, //aux_adc_rate *** adi,aux-adc-rate
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/* AuxDAC Control */
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1, //aux_dac_manual_mode_enable *** adi,aux-dac-manual-mode-enable
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0, //aux_dac1_default_value_mV *** adi,aux-dac1-default-value-mV
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0, //aux_dac1_active_in_rx_enable *** adi,aux-dac1-active-in-rx-enable
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0, //aux_dac1_active_in_tx_enable *** adi,aux-dac1-active-in-tx-enable
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0, //aux_dac1_active_in_alert_enable *** adi,aux-dac1-active-in-alert-enable
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0, //aux_dac1_rx_delay_us *** adi,aux-dac1-rx-delay-us
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0, //aux_dac1_tx_delay_us *** adi,aux-dac1-tx-delay-us
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0, //aux_dac2_default_value_mV *** adi,aux-dac2-default-value-mV
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0, //aux_dac2_active_in_rx_enable *** adi,aux-dac2-active-in-rx-enable
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0, //aux_dac2_active_in_tx_enable *** adi,aux-dac2-active-in-tx-enable
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0, //aux_dac2_active_in_alert_enable *** adi,aux-dac2-active-in-alert-enable
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0, //aux_dac2_rx_delay_us *** adi,aux-dac2-rx-delay-us
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0, //aux_dac2_tx_delay_us *** adi,aux-dac2-tx-delay-us
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/* Temperature Sensor Control */
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256, //temp_sense_decimation *** adi,temp-sense-decimation
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1000, //temp_sense_measurement_interval_ms *** adi,temp-sense-measurement-interval-ms
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0xCE, //temp_sense_offset_signed *** adi,temp-sense-offset-signed
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1, //temp_sense_periodic_measurement_enable *** adi,temp-sense-periodic-measurement-enable
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/* Control Out Setup */
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0xFF, //ctrl_outs_enable_mask *** adi,ctrl-outs-enable-mask
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0, //ctrl_outs_index *** adi,ctrl-outs-index
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/* External LNA Control */
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0, //elna_settling_delay_ns *** adi,elna-settling-delay-ns
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0, //elna_gain_mdB *** adi,elna-gain-mdB
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0, //elna_bypass_loss_mdB *** adi,elna-bypass-loss-mdB
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0, //elna_rx1_gpo0_control_enable *** adi,elna-rx1-gpo0-control-enable
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0, //elna_rx2_gpo1_control_enable *** adi,elna-rx2-gpo1-control-enable
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0, //elna_gaintable_all_index_enable *** adi,elna-gaintable-all-index-enable
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/* Digital Interface Control */
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0, //digital_interface_tune_skip_mode *** adi,digital-interface-tune-skip-mode
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0, //digital_interface_tune_fir_disable *** adi,digital-interface-tune-fir-disable
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1, //pp_tx_swap_enable *** adi,pp-tx-swap-enable
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1, //pp_rx_swap_enable *** adi,pp-rx-swap-enable
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0, //tx_channel_swap_enable *** adi,tx-channel-swap-enable
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0, //rx_channel_swap_enable *** adi,rx-channel-swap-enable
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1, //rx_frame_pulse_mode_enable *** adi,rx-frame-pulse-mode-enable
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0, //two_t_two_r_timing_enable *** adi,2t2r-timing-enable
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0, //invert_data_bus_enable *** adi,invert-data-bus-enable
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0, //invert_data_clk_enable *** adi,invert-data-clk-enable
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0, //fdd_alt_word_order_enable *** adi,fdd-alt-word-order-enable
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0, //invert_rx_frame_enable *** adi,invert-rx-frame-enable
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0, //fdd_rx_rate_2tx_enable *** adi,fdd-rx-rate-2tx-enable
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0, //swap_ports_enable *** adi,swap-ports-enable
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0, //single_data_rate_enable *** adi,single-data-rate-enable
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1, //lvds_mode_enable *** adi,lvds-mode-enable
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0, //half_duplex_mode_enable *** adi,half-duplex-mode-enable
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0, //single_port_mode_enable *** adi,single-port-mode-enable
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0, //full_port_enable *** adi,full-port-enable
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0, //full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable
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0, //delay_rx_data *** adi,delay-rx-data
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0, //rx_data_clock_delay *** adi,rx-data-clock-delay
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4, //rx_data_delay *** adi,rx-data-delay
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7, //tx_fb_clock_delay *** adi,tx-fb-clock-delay
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0, //tx_data_delay *** adi,tx-data-delay
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150, //lvds_bias_mV *** adi,lvds-bias-mV
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1, //lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable
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0, //rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable
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0xFF, //lvds_invert1_control *** adi,lvds-invert1-control
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0x0F, //lvds_invert2_control *** adi,lvds-invert2-control
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/* GPO Control */
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0, //gpo_manual_mode_enable *** adi,gpo-manual-mode-enable
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0, //gpo_manual_mode_enable_mask *** adi,gpo-manual-mode-enable-mask
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0, //gpo0_inactive_state_high_enable *** adi,gpo0-inactive-state-high-enable
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0, //gpo1_inactive_state_high_enable *** adi,gpo1-inactive-state-high-enable
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0, //gpo2_inactive_state_high_enable *** adi,gpo2-inactive-state-high-enable
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0, //gpo3_inactive_state_high_enable *** adi,gpo3-inactive-state-high-enable
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0, //gpo0_slave_rx_enable *** adi,gpo0-slave-rx-enable
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0, //gpo0_slave_tx_enable *** adi,gpo0-slave-tx-enable
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0, //gpo1_slave_rx_enable *** adi,gpo1-slave-rx-enable
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0, //gpo1_slave_tx_enable *** adi,gpo1-slave-tx-enable
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0, //gpo2_slave_rx_enable *** adi,gpo2-slave-rx-enable
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0, //gpo2_slave_tx_enable *** adi,gpo2-slave-tx-enable
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0, //gpo3_slave_rx_enable *** adi,gpo3-slave-rx-enable
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0, //gpo3_slave_tx_enable *** adi,gpo3-slave-tx-enable
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0, //gpo0_rx_delay_us *** adi,gpo0-rx-delay-us
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0, //gpo0_tx_delay_us *** adi,gpo0-tx-delay-us
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0, //gpo1_rx_delay_us *** adi,gpo1-rx-delay-us
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0, //gpo1_tx_delay_us *** adi,gpo1-tx-delay-us
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0, //gpo2_rx_delay_us *** adi,gpo2-rx-delay-us
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0, //gpo2_tx_delay_us *** adi,gpo2-tx-delay-us
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0, //gpo3_rx_delay_us *** adi,gpo3-rx-delay-us
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0, //gpo3_tx_delay_us *** adi,gpo3-tx-delay-us
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/* Tx Monitor Control */
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37000, //low_high_gain_threshold_mdB *** adi,txmon-low-high-thresh
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0, //low_gain_dB *** adi,txmon-low-gain
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24, //high_gain_dB *** adi,txmon-high-gain
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0, //tx_mon_track_en *** adi,txmon-dc-tracking-enable
|
||||
0, //one_shot_mode_en *** adi,txmon-one-shot-mode-enable
|
||||
511, //tx_mon_delay *** adi,txmon-delay
|
||||
8192, //tx_mon_duration *** adi,txmon-duration
|
||||
2, //tx1_mon_front_end_gain *** adi,txmon-1-front-end-gain
|
||||
2, //tx2_mon_front_end_gain *** adi,txmon-2-front-end-gain
|
||||
48, //tx1_mon_lo_cm *** adi,txmon-1-lo-cm
|
||||
48, //tx2_mon_lo_cm *** adi,txmon-2-lo-cm
|
||||
/* GPIO definitions */
|
||||
/* Reset_b */
|
||||
{
|
||||
.number = AD9361_1_RESET_B,
|
||||
.platform_ops = &xil_gpio_ops,
|
||||
.extra = &xil_gpio_param
|
||||
}, //gpio_resetb *** reset-gpios
|
||||
/* MCS Sync */
|
||||
{
|
||||
.number = -1,
|
||||
.platform_ops = &xil_gpio_ops,
|
||||
.extra = &xil_gpio_param
|
||||
}, //gpio_sync *** sync-gpios
|
||||
/* Cal-SW1 */
|
||||
{
|
||||
.number = -1,
|
||||
.platform_ops = &xil_gpio_ops,
|
||||
.extra = &xil_gpio_param
|
||||
}, //gpio_cal_sw1 *** cal-sw1-gpios
|
||||
/* Cal-SW2 */
|
||||
{
|
||||
.number = -1,
|
||||
.platform_ops = &xil_gpio_ops,
|
||||
.extra = &xil_gpio_param
|
||||
}, //gpio_cal_sw2 *** cal-sw2-gpios
|
||||
|
||||
{
|
||||
.device_id = AD9361_SPI_DEVICE_ID,
|
||||
.mode = SPI_MODE_1,
|
||||
.chip_select = AD9361_1_SPI_CS,
|
||||
.platform_ops = &spi_eng_platform_ops,
|
||||
.extra = &spi_engine_param
|
||||
},
|
||||
|
||||
/* External LO clocks */
|
||||
NULL, //(*ad9361_rfpll_ext_recalc_rate)()
|
||||
NULL, //(*ad9361_rfpll_ext_round_rate)()
|
||||
NULL, //(*ad9361_rfpll_ext_set_rate)()
|
||||
};
|
||||
|
||||
AD9361_RXFIRConfig rx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs
|
||||
3, // rx
|
||||
0, // rx_gain
|
||||
1, // rx_dec
|
||||
{
|
||||
-4, -6, -37, 35, 186, 86, -284, -315,
|
||||
107, 219, -4, 271, 558, -307, -1182, -356,
|
||||
658, 157, 207, 1648, 790, -2525, -2553, 748,
|
||||
865, -476, 3737, 6560, -3583, -14731, -5278, 14819,
|
||||
14819, -5278, -14731, -3583, 6560, 3737, -476, 865,
|
||||
748, -2553, -2525, 790, 1648, 207, 157, 658,
|
||||
-356, -1182, -307, 558, 271, -4, 219, 107,
|
||||
-315, -284, 86, 186, 35, -37, -6, -4,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0
|
||||
}, // rx_coef[128]
|
||||
64, // rx_coef_size
|
||||
{0, 0, 0, 0, 0, 0}, //rx_path_clks[6]
|
||||
0 // rx_bandwidth
|
||||
};
|
||||
|
||||
AD9361_TXFIRConfig tx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs
|
||||
3, // tx
|
||||
-6, // tx_gain
|
||||
1, // tx_int
|
||||
{
|
||||
-4, -6, -37, 35, 186, 86, -284, -315,
|
||||
107, 219, -4, 271, 558, -307, -1182, -356,
|
||||
658, 157, 207, 1648, 790, -2525, -2553, 748,
|
||||
865, -476, 3737, 6560, -3583, -14731, -5278, 14819,
|
||||
14819, -5278, -14731, -3583, 6560, 3737, -476, 865,
|
||||
748, -2553, -2525, 790, 1648, 207, 157, 658,
|
||||
-356, -1182, -307, 558, 271, -4, 219, 107,
|
||||
-315, -284, 86, 186, 35, -37, -6, -4,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0
|
||||
}, // tx_coef[128]
|
||||
64, // tx_coef_size
|
||||
{0, 0, 0, 0, 0, 0}, // tx_path_clks[6]
|
||||
0 // tx_bandwidth
|
||||
};
|
||||
|
||||
@@ -0,0 +1,134 @@
|
||||
#include "dev_profile.h"
|
||||
#include "../config/app_config.h"
|
||||
#include "../drivers/platform/xilinx_gpio.h"
|
||||
#include "../drivers/axi_core/spi_engine/spi_engine.h"
|
||||
#include "../drivers/frequency/ad9528/ad9528.h"
|
||||
|
||||
static struct spi_engine_init_param spi_engine_param = {
|
||||
.ref_clk_hz = AD9528_SPI_ENGINE_REF_CLK,
|
||||
.type = SPI_ENGINE,
|
||||
.spi_engine_baseaddr = AD9528_SPI_ENGINE_BASEADDR,
|
||||
.cs_delay = AD9528_SPI_ENGINE_CS_DELAY,
|
||||
.data_width = AD9528_SPI_ENGINE_DATA_WIDTH
|
||||
};
|
||||
|
||||
static struct xil_gpio_init_param xil_gpio_param = {
|
||||
.type = GPIO_PS,
|
||||
.device_id = AD9528_GPIO_DEVICE_ID
|
||||
};
|
||||
|
||||
static struct spi_init_param ad9528_spi_init = {
|
||||
.device_id = AD9528_SPI_DEVICE_ID,
|
||||
.max_speed_hz = AD9528_SPI_ENGINE_MAX_SPEED,
|
||||
.mode = SPI_MODE_0,
|
||||
.chip_select = AD9528_SPI_CS,
|
||||
.platform_ops = &spi_eng_platform_ops,
|
||||
.extra = &spi_engine_param
|
||||
};
|
||||
|
||||
static struct gpio_init_param ad9528_gpio_resetb_init = {
|
||||
.number = AD9528_RESETB,
|
||||
.platform_ops = &xil_gpio_ops,
|
||||
.extra = &xil_gpio_param
|
||||
};
|
||||
|
||||
static struct gpio_init_param ad9528_gpio_sysref_req_init = {
|
||||
.number = AD9528_SYSREF_REQ,
|
||||
.platform_ops = &xil_gpio_ops,
|
||||
.extra = &xil_gpio_param
|
||||
};
|
||||
|
||||
static ad9528pll1Settings_t clockPll1Settings = {
|
||||
.refA_Frequency_Hz = 50000000,
|
||||
.refA_Divider = 1,
|
||||
.refA_bufferCtrl = SINGLE_ENDED,
|
||||
.refB_Frequency_Hz = 0,
|
||||
.refB_Divider = 1,
|
||||
.refB_bufferCtrl = DISABLED,
|
||||
.vcxo_Frequency_Hz = 50000000,
|
||||
.vcxoBufferCtrl = SINGLE_ENDED,
|
||||
.nDivider = 1
|
||||
};
|
||||
|
||||
static ad9528pll2Settings_t clockPll2Settings = {
|
||||
.rfDivider = 4,
|
||||
.n2Divider = 20,
|
||||
.totalNdiv = 80
|
||||
};
|
||||
|
||||
/*******************************************************************
|
||||
* Output Distribution Settings
|
||||
* 9369CE02A uses the following clock outputs
|
||||
* OUT 1: FPGA REFCLK
|
||||
* OUT 3: FPGA SYSREF
|
||||
* OUT 12: DUT SYSREF
|
||||
* OUT 13: DUT REFCLK
|
||||
*******************************************************************
|
||||
*/
|
||||
static ad9528outputSettings_t clockOutputSettings = {
|
||||
.outPowerDown = 0xE001,
|
||||
.outSource = {
|
||||
AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV,
|
||||
AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV,
|
||||
AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV
|
||||
},
|
||||
.outBufferCtrl = {
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0
|
||||
},
|
||||
.outAnalogDelay = {
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0
|
||||
},
|
||||
.outDigitalDelay = {
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0
|
||||
},
|
||||
.outChannelDiv = {
|
||||
5,25,25,5,5,
|
||||
5,5,5,5,5,
|
||||
5,5,10,5
|
||||
},
|
||||
.outFrequency_Hz = {
|
||||
200e6, 40e6, 40e6, 200e6, 200e6,
|
||||
200e6, 200e6, 200e6, 200e6, 200e6,
|
||||
200e6, 200e6, 100e6, 200e6
|
||||
}
|
||||
};
|
||||
|
||||
static ad9528sysrefSettings_t clockSysrefSettings = {
|
||||
.sysrefRequestMethod = PIN,
|
||||
.sysrefSource = INTERNAL,
|
||||
.sysrefPinEdgeMode = LEVEL_ACTIVE_HIGH,
|
||||
.sysrefPinBufferMode = DISABLED,
|
||||
.sysrefPatternMode = CONTINUOUS,
|
||||
.sysrefNshotMode = FOUR_PULSES,
|
||||
.sysrefDivide = 256
|
||||
};
|
||||
|
||||
static ad9528spiSettings_t clockSpiSettings = {
|
||||
.chipSelectIndex = AD9528_SPI_CS, //chip select Index, not used
|
||||
.writeBitPolarity = 0, //Write bit polarity
|
||||
.longInstructionWord = 1, //16bit instruction word
|
||||
.MSBFirst = 1, //MSB first
|
||||
.CPHA = 0, //Clock phase
|
||||
.CPOL = 0, //Clock polarity
|
||||
.enSpiStreaming = 0, //uint8_t enSpiStreaming;
|
||||
.autoIncAddrUp = 1, //uint8_t autoIncAddrUp;
|
||||
.fourWireMode = 1 //uint8_t fourWireMode;
|
||||
};
|
||||
|
||||
ad9528Init_t ad9528_default_init_param = {
|
||||
/* SPI */
|
||||
.spi_init = &ad9528_spi_init,
|
||||
.gpio_init_resetb = &ad9528_gpio_resetb_init,
|
||||
.gpio_init_sysref_req = &ad9528_gpio_sysref_req_init,
|
||||
.spiSettings = &clockSpiSettings,
|
||||
.pll1Settings = &clockPll1Settings,
|
||||
.pll2Settings = &clockPll2Settings,
|
||||
.outputSettings = &clockOutputSettings,
|
||||
.sysrefSettings = &clockSysrefSettings
|
||||
};
|
||||
@@ -0,0 +1,46 @@
|
||||
#include "dev_profile.h"
|
||||
#include "spi.h"
|
||||
#include "../config/app_config.h"
|
||||
#include "../drivers/adc/ad9653/ad9653.h"
|
||||
#include "../drivers/axi_core/spi_engine/spi_engine.h"
|
||||
#include "../drivers/platform/xilinx_gpio.h"
|
||||
|
||||
static struct spi_engine_init_param spi_engine_param = {
|
||||
.ref_clk_hz = AD9653_SPI_ENGINE_REF_CLK,
|
||||
.type = SPI_ENGINE,
|
||||
.spi_engine_baseaddr = AD9653_SPI_ENGINE_BASEADDR,
|
||||
.cs_delay = AD9653_SPI_ENGINE_CS_DELAY,
|
||||
.data_width = AD9653_SPI_ENGINE_DATA_WIDTH
|
||||
};
|
||||
|
||||
static struct xil_gpio_init_param xil_gpio_param = {
|
||||
.type = GPIO_PS,
|
||||
.device_id = AD9653_GPIO_DEVICE_ID
|
||||
};
|
||||
|
||||
static struct spi_init_param ad9653_spi_init = {
|
||||
.device_id = AD9653_SPI_DEVICE_ID,
|
||||
.max_speed_hz = AD9653_SPI_ENGINE_MAX_SPEED,
|
||||
.mode = SPI_MODE_4,
|
||||
.chip_select = AD9653_SPI_CS,
|
||||
.platform_ops = &spi_eng_platform_ops,
|
||||
.extra = &spi_engine_param
|
||||
};
|
||||
|
||||
static struct gpio_init_param ad9653_gpio_resetb_init = {
|
||||
.number = AD9653_POWR_DOWN,
|
||||
.platform_ops = &xil_gpio_ops,
|
||||
.extra = &xil_gpio_param
|
||||
};
|
||||
|
||||
struct ad9653_init_param ad9653_default_init_param = {
|
||||
/* SPI */
|
||||
.spi_init = &ad9653_spi_init,
|
||||
.gpio_pdwn = &ad9653_gpio_resetb_init
|
||||
};
|
||||
|
||||
const uint32_t ad9653_default_config_len = 36;
|
||||
const struct ad9653_config ad9653_default_config[] = {
|
||||
// configuration
|
||||
|
||||
};
|
||||
@@ -0,0 +1,72 @@
|
||||
#include "dev_profile.h"
|
||||
#include "spi.h"
|
||||
#include "../config/app_config.h"
|
||||
#include "../drivers/adc/ad9694/ad9694.h"
|
||||
#include "../drivers/axi_core/spi_engine/spi_engine.h"
|
||||
#include "../drivers/platform/xilinx_gpio.h"
|
||||
|
||||
static struct spi_engine_init_param spi_engine_param = {
|
||||
.ref_clk_hz = AD9694_SPI_ENGINE_REF_CLK,
|
||||
.type = SPI_ENGINE,
|
||||
.spi_engine_baseaddr = AD9694_SPI_ENGINE_BASEADDR,
|
||||
.cs_delay = AD9694_SPI_ENGINE_CS_DELAY,
|
||||
.data_width = AD9694_SPI_ENGINE_DATA_WIDTH
|
||||
};
|
||||
|
||||
//static struct xil_gpio_init_param xil_gpio_param = {
|
||||
// .type = GPIO_PS,
|
||||
// .device_id = AD9694_GPIO_DEVICE_ID
|
||||
//};
|
||||
|
||||
static struct spi_init_param ad9694_spi_init = {
|
||||
.device_id = AD9694_SPI_DEVICE_ID,
|
||||
.max_speed_hz = AD9694_SPI_ENGINE_MAX_SPEED,
|
||||
.mode = SPI_MODE_4,
|
||||
.chip_select = AD9694_SPI_CS,
|
||||
.platform_ops = &spi_eng_platform_ops,
|
||||
.extra = &spi_engine_param
|
||||
};
|
||||
|
||||
struct ad9694_init_param ad9694_default_init_param = {
|
||||
/* SPI */
|
||||
.spi_init = &ad9694_spi_init
|
||||
};
|
||||
|
||||
const uint32_t ad9694_default_config_len = 36;
|
||||
const struct ad9694_config ad9694_default_config[] = {
|
||||
// reset
|
||||
{0x0000, 0x81},
|
||||
{0x1228, 0x4F}, // JESD204B start-up circuit reset
|
||||
{0x1228, 0x0F}, // JESD204B start-up normal operation
|
||||
{0x1222, 0x04}, // PLL calibration
|
||||
{0x1222, 0x00}, // PLL normal operation
|
||||
{0x1262, 0x08}, // PLL loss of lock control - Clear loss of lock
|
||||
{0x1262, 0x00}, // PLL loss of lock control - Normal operation
|
||||
|
||||
// system clock
|
||||
{0x0108, 0x00}, // Clock divider = 1 -> device clock = 368.64MHz
|
||||
{0x0201, 0x00}, // Chip decimation ration = 1 -> full sample rate
|
||||
|
||||
// channel configuration
|
||||
{0x0009, 0x03}, // ADC Pair AB & CD receive all spi command
|
||||
{0x0571, 0x15}, // JESD204B map JTX Link Control 1
|
||||
{0x056E, 0x00}, // JESD204B map PLL control, lane rate 6.75~13.5Gbps, actual = 7.3728Gbps
|
||||
{0x0570, 0x49}, // JESD204B map JTX quick config: L=2 M=2 F=2
|
||||
{0x058B, 0x01}, // JESD204B map JTX SCR L config: scrambler disabled, L=2
|
||||
{0x0590, 0x2F}, // JESD204B map JTX Subclass & NP config: subclass 1, N' = 16
|
||||
{0x058D, 0x1F}, // JESD204B map JTX K config: K = 32
|
||||
{0x058F, 0x2D}, // JESD204B map JTX N config: CS = 0, N = 14
|
||||
{0x0571, 0x14}, // JESD204B map JTX Link Control 1
|
||||
{0x05B0, 0x00}, // SERDOUTx0, SERDOUTx1 power on
|
||||
{0x0120, 0x0A}, // SYSREF COntrol: continuous mode, captured on falling edge
|
||||
|
||||
// fast detect control
|
||||
{0x0040, 0x00}, // FD_B/FD_D, FD_A/FD_C function as Fast Detect B/D, A/C output
|
||||
{0x0245, 0x01}, // Fine fast detect enabled
|
||||
{0x0247, 0xFE}, // Channel map fast detect upper threshold LSB
|
||||
{0x0248, 0x1F}, // Channel map fast detect upper threshold MSB, -> 8190
|
||||
{0x0249, 0xA4}, // Channel map fast detect lower threshold LSB
|
||||
{0x024A, 0x1F}, // Channel map fast detect lower threshold MSB, -> 8100
|
||||
{0x024B, 0x80}, // Channel map fast detect dwell time LSB
|
||||
{0x024C, 0x00} // Channel map fast detect dwell time MSB, -> 128
|
||||
};
|
||||
@@ -3,11 +3,55 @@
|
||||
|
||||
#include "irq.h"
|
||||
#include "error.h"
|
||||
#include "../drivers/frequency/hmc7044/hmc7044.h"
|
||||
#include "../drivers/frequency/ad9528/ad9528.h"
|
||||
#include "../drivers/frequency/lmk04828/lmk04828.h"
|
||||
#include "../drivers/frequency/lmx2594/lmx2594.h"
|
||||
#include "../drivers/rf-transceiver/ad9361_reg/ad9361_reg.h"
|
||||
#include "../drivers/rf-transceiver/ad9361/ad9361_api.h"
|
||||
#include "../drivers/adc/ad9694/ad9694.h"
|
||||
#include "../drivers/adc/ad9653/ad9653.h"
|
||||
#include "../config/app_config.h"
|
||||
|
||||
// device parameters
|
||||
extern struct irq_init_param intc_init_param;
|
||||
extern struct timer_init_param scutimer_init_param;
|
||||
extern struct global_timer_init_param globaltimer_init_param;
|
||||
extern struct timer_init_param apptimer_init_param;
|
||||
|
||||
// HMC7044
|
||||
extern struct hmc7044_init_param hmc7044_default_init_param;
|
||||
|
||||
// AD9528
|
||||
extern ad9528Init_t ad9528_default_init_param;
|
||||
|
||||
// LMK04828
|
||||
extern struct lmk04828_init_param lmk04828_default_init_param;
|
||||
extern const struct lmk04828_config lmk04828_default_config[];
|
||||
extern const uint32_t lmk04828_default_config_len;
|
||||
|
||||
// LMX2594
|
||||
extern struct lmx2594_init_param lmx2594_adc_init_param;
|
||||
extern struct lmx2594_init_param lmx2594_dac_init_param;
|
||||
extern const struct lmx2594_config lmx2594_default_config[];
|
||||
extern const uint32_t lmx2594_default_config_len;
|
||||
|
||||
// AD9361
|
||||
extern AD9361_InitParam ad9361_default_init_param;
|
||||
extern AD9361_RXFIRConfig rx_fir_config;
|
||||
extern AD9361_TXFIRConfig tx_fir_config;
|
||||
extern struct ad9361_reg_init_param ad9361_1_reg_default_init_param;
|
||||
extern struct ad9361_reg_init_param ad9361_2_reg_default_init_param;
|
||||
uint32_t ad9361_1_reg_config(struct ad9361_reg_dev *dev);
|
||||
uint32_t ad9361_2_reg_config(struct ad9361_reg_dev *dev);
|
||||
|
||||
// AD9653
|
||||
extern struct ad9653_init_param ad9653_default_init_param;
|
||||
extern const struct ad9653_config ad9653_default_config[];
|
||||
extern const uint32_t ad9653_default_config_len;
|
||||
|
||||
// AD9694
|
||||
extern struct ad9694_init_param ad9694_default_init_param;
|
||||
extern const struct ad9694_config ad9694_default_config[];
|
||||
extern const uint32_t ad9694_default_config_len;
|
||||
|
||||
|
||||
#endif /* SRC_DEV_PROFILE_H_ */
|
||||
|
||||
@@ -1,11 +0,0 @@
|
||||
#include "dev_profile.h"
|
||||
#include "global_timer.h"
|
||||
#include "../config/app_config.h"
|
||||
|
||||
struct global_timer_init_param globaltimer_init_param = {
|
||||
.base_addr = GLOBAL_TIMER_BASEADDR,
|
||||
.id = GLOBAL_TIMER_DEVICE_ID,
|
||||
.freq_hz = GLOBAL_TIMER_CLK_HZ,
|
||||
.load_value = 0x0000000000000000
|
||||
};
|
||||
|
||||
@@ -0,0 +1,132 @@
|
||||
#include "dev_profile.h"
|
||||
#include "../config/app_config.h"
|
||||
#include "../drivers/platform/xilinx_gpio.h"
|
||||
#include "../drivers/axi_core/spi_engine/spi_engine.h"
|
||||
#include "../drivers/frequency/hmc7044/hmc7044.h"
|
||||
|
||||
|
||||
static struct spi_engine_init_param spi_engine_param = {
|
||||
.ref_clk_hz = HMC7044_SPI_ENGINE_REF_CLK,
|
||||
.type = SPI_ENGINE,
|
||||
.spi_engine_baseaddr = HMC7044_SPI_ENGINE_BASEADDR,
|
||||
.cs_delay = HMC7044_SPI_ENGINE_CS_DELAY,
|
||||
.data_width = HMC7044_SPI_ENGINE_DATA_WIDTH
|
||||
};
|
||||
|
||||
//static struct xil_gpio_init_param xil_gpio_param = {
|
||||
// .type = GPIO_PS,
|
||||
// .device_id = AD9361_GPIO_DEVICE_ID
|
||||
//};
|
||||
|
||||
// hmc7044 spi settings
|
||||
static struct spi_init_param hmc7044_spi_init_param = {
|
||||
.device_id = HMC7044_SPI_DEVICE_ID,
|
||||
.max_speed_hz = HMC7044_SPI_ENGINE_MAX_SPEED,
|
||||
.mode = SPI_MODE_4,
|
||||
.chip_select = HMC7044_SPI_CS_HMC7044,
|
||||
.platform_ops = &spi_eng_platform_ops,
|
||||
.extra = &spi_engine_param
|
||||
};
|
||||
|
||||
// hmc7044 channel specifications
|
||||
struct hmc7044_chan_spec hmc7044_chan_spec[4] = {
|
||||
/* AD9361_XTAL */
|
||||
{
|
||||
.disable = 0,
|
||||
.num = 3,
|
||||
.divider = 100,
|
||||
.coarse_delay = 0,
|
||||
.fine_delay = 0,
|
||||
.high_performance_mode_dis = true,
|
||||
.start_up_mode_dynamic_enable = false,
|
||||
.dynamic_driver_enable = false,
|
||||
.output_control0_rb4_enable = true,
|
||||
.force_mute_enable = false,
|
||||
.driver_mode = CML,
|
||||
.driver_impedance = INTERNAL_100OHM_PER_PIN,
|
||||
.out_mux_mode = CHANNEL_DIV
|
||||
},
|
||||
/* FPGA_DAC_LOGIC_CLK */
|
||||
{
|
||||
.disable = 0,
|
||||
.num = 4,
|
||||
.divider = 10,
|
||||
.coarse_delay = 0,
|
||||
.fine_delay = 0,
|
||||
.high_performance_mode_dis = true,
|
||||
.start_up_mode_dynamic_enable = false,
|
||||
.dynamic_driver_enable = false,
|
||||
.output_control0_rb4_enable = true,
|
||||
.force_mute_enable = false,
|
||||
.driver_mode = CML,
|
||||
.driver_impedance = INTERNAL_100OHM_PER_PIN,
|
||||
.out_mux_mode = CHANNEL_DIV
|
||||
},
|
||||
/* B_AD9361_XTAL */
|
||||
{
|
||||
.disable = 0,
|
||||
.num = 12,
|
||||
.divider = 100,
|
||||
.coarse_delay = 0,
|
||||
.fine_delay = 0,
|
||||
.high_performance_mode_dis = false,
|
||||
.start_up_mode_dynamic_enable = false,
|
||||
.dynamic_driver_enable = false,
|
||||
.output_control0_rb4_enable = true,
|
||||
.force_mute_enable = false,
|
||||
.driver_mode = CML,
|
||||
.driver_impedance = INTERNAL_100OHM_PER_PIN,
|
||||
.out_mux_mode = CHANNEL_DIV
|
||||
},
|
||||
/* AD9361_RX_EXT_LO */
|
||||
{
|
||||
.disable = 0,
|
||||
.num = 13,
|
||||
.divider = 10,
|
||||
.coarse_delay = 0,
|
||||
.fine_delay = 0,
|
||||
.high_performance_mode_dis = false,
|
||||
.start_up_mode_dynamic_enable = false,
|
||||
.dynamic_driver_enable = false,
|
||||
.output_control0_rb4_enable = true,
|
||||
.force_mute_enable = false,
|
||||
.driver_mode = CML,
|
||||
.driver_impedance = INTERNAL_100OHM_PER_PIN,
|
||||
.out_mux_mode = CHANNEL_DIV
|
||||
},
|
||||
};
|
||||
|
||||
// hmc7044 default configurations
|
||||
struct hmc7044_init_param hmc7044_default_init_param = {
|
||||
.spi_init = &hmc7044_spi_init_param,
|
||||
.clkin_freq = {0, 100000000, 0, 0},
|
||||
.vcxo_freq = 100000000,
|
||||
.pll2_freq = 2500000000,
|
||||
.pll1_loop_bw = 200,
|
||||
.sysref_timer_div = 1536,
|
||||
.in_buf_mode = {
|
||||
BUFFER_DISABLE,
|
||||
ENABLE_AC_COUPLE | ENABLE_INTERNAL_TERM | BUFFER_ENABLE,
|
||||
BUFFER_DISABLE,
|
||||
BUFFER_DISABLE,
|
||||
ENABLE_AC_COUPLE | ENABLE_INTERNAL_TERM | BUFFER_ENABLE
|
||||
},
|
||||
.gpi_ctrl = {
|
||||
GPI_DISABLE,
|
||||
GPI_DISABLE,
|
||||
CHIP_SLEEP_MODE,
|
||||
PULSE_GEN_REQUSET
|
||||
},
|
||||
.gpo_ctrl = {
|
||||
PLL1_LOCK_DETECT | GPO_CMOS_MODE,
|
||||
PLL2_LOCK_DETECT | GPO_CMOS_MODE,
|
||||
GPO_DISABLE,
|
||||
GPO_DISABLE
|
||||
},
|
||||
.num_channels = 4,
|
||||
.pll1_ref_prio_ctrl = 0xE4,
|
||||
.sync_pin_mode = SYNC_MULTICHIP,
|
||||
.high_performance_mode_clock_dist_en = false,
|
||||
.pulse_gen_mode = PULSE_ONE,
|
||||
.channels = hmc7044_chan_spec
|
||||
};
|
||||
@@ -2,6 +2,7 @@
|
||||
#include "irq.h"
|
||||
#include "../config/app_config.h"
|
||||
#include "../drivers/platform/xilinx_irq.h"
|
||||
|
||||
struct xil_irq_init_param xil_intc_init_param = {
|
||||
.type = IRQ_PS
|
||||
};
|
||||
|
||||
@@ -0,0 +1,182 @@
|
||||
#include "dev_profile.h"
|
||||
#include "spi.h"
|
||||
#include "../config/app_config.h"
|
||||
#include "../drivers/frequency/lmk04828/lmk04828.h"
|
||||
#include "../drivers/axi_core/spi_engine/spi_engine.h"
|
||||
#include "../drivers/platform/xilinx_gpio.h"
|
||||
|
||||
static struct spi_engine_init_param spi_engine_param = {
|
||||
.ref_clk_hz = LMK04828_SPI_ENGINE_REF_CLK,
|
||||
.type = SPI_ENGINE,
|
||||
.spi_engine_baseaddr = LMK04828_SPI_ENGINE_BASEADDR,
|
||||
.cs_delay = LMK04828_SPI_ENGINE_CS_DELAY,
|
||||
.data_width = LMK04828_SPI_ENGINE_DATA_WIDTH
|
||||
};
|
||||
|
||||
//static struct xil_gpio_init_param xil_gpio_param = {
|
||||
// .type = GPIO_PS,
|
||||
// .device_id = LMK04828_GPIO_DEVICE_ID
|
||||
//};
|
||||
|
||||
static struct spi_init_param lmk04828_spi_init = {
|
||||
.device_id = LMK04828_SPI_DEVICE_ID,
|
||||
.max_speed_hz = LMK04828_SPI_ENGINE_MAX_SPEED,
|
||||
.mode = SPI_MODE_0,
|
||||
.chip_select = LMK04828_SPI_CS,
|
||||
.platform_ops = &spi_eng_platform_ops,
|
||||
.extra = &spi_engine_param
|
||||
};
|
||||
|
||||
struct lmk04828_init_param lmk04828_default_init_param = {
|
||||
/* SPI */
|
||||
.spi_init = &lmk04828_spi_init
|
||||
};
|
||||
|
||||
const uint32_t lmk04828_default_config_len = 137;
|
||||
const struct lmk04828_config lmk04828_default_config[] = {
|
||||
// 192MHz
|
||||
{0x0000, 0x90}, // [7] reset; [4] 3-wire mode disabled
|
||||
{0x0000, 0x10}, // [7] normal operation; [4] 3-wire mode disabled
|
||||
{0x0002, 0x00}, // [0] normal operation
|
||||
{0x0003, 0x06}, // [7-0] product device type, read only, default: 6
|
||||
{0x0004, 0xD0}, // [7-0] msb of product identifier, read only, default: 208
|
||||
{0x0005, 0x5B}, // [7-0] lsb of product identifier, read only, default: 91
|
||||
{0x0006, 0x00}, // [7-0] ic version identifier, read only, default: 32
|
||||
{0x000C, 0x51}, // [7-0] msb of vendor identifier, read only, default: 81
|
||||
{0x000D, 0x04}, // [7-0] lsb of vendor identifier, read only, default: 4
|
||||
// device clock 0
|
||||
{0x0100, 0x10}, // [6] output drive level (ODL); [5] input drive level (IDL); [4-0] device clock (DCLK) output divider
|
||||
{0x0101, 0x55}, // DCLK: [7-4] output digital delay (DDLY) high count; [3-0] DDLY low count
|
||||
{0x0102, 0x55},
|
||||
{0x0103, 0x01}, // DCLK: [7-3] analog delay (ADLY) value, 25 ps per lsb; [2] ADLY input mux; [1-0] DCLK input mux
|
||||
{0x0104, 0x22}, // [6] DCLK half step value; [5] SDCLK output MUX; [4-1] SDCLK DDLY; [0] SYSREF half step value
|
||||
{0x0105, 0x00}, // SYSREF: [4] ADLY enable; [3:0] ADLY value, 600 ps + 150 ps per lsb
|
||||
{0x0106, 0xF0}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable
|
||||
{0x0107, 0x11}, // [7] SDCLK output polarity; [6-4] SDCLK output format; [3] DCLK output polarity; [2:0] DCLK output format
|
||||
// device clock 2
|
||||
{0x0108, 0x10}, // [6] output drive level (ODL); [5] input drive level (IDL); [4-0] device clock (DCLK) output divider
|
||||
{0x0109, 0x55}, // DCLK: [7-4] output digital delay (DDLY) high count; [3-0] DDLY low count
|
||||
{0x010A, 0x55},
|
||||
{0x010B, 0x00}, // DCLK: [7-3] analog delay (ADLY) value, 25 ps per lsb; [2] ADLY input mux; [1-0] DCLK input mux
|
||||
{0x010C, 0x22}, // [6] DCLK half step value; [5] SDCLK output MUX; [4-1] SDCLK DDLY; [0] SYSREF half step value
|
||||
{0x010D, 0x00}, // SYSREF: [4] ADLY enable; [3:0] ADLY value, 600 ps + 150 ps per lsb
|
||||
{0x010E, 0xF0}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable
|
||||
{0x010F, 0x10}, // [7] SDCLK output polarity; [6-4] SDCLK output format; [3] DCLK output polarity; [2:0] DCLK output format
|
||||
// device clock 4
|
||||
{0x0110, 0x10}, // [6] output drive level (ODL); [5] input drive level (IDL); [4-0] device clock (DCLK) output divider
|
||||
{0x0111, 0x55}, // DCLK: [7-4] output digital delay (DDLY) high count; [3-0] DDLY low count
|
||||
{0x0112, 0x55},
|
||||
{0x0113, 0x00}, // DCLK: [7-3] analog delay (ADLY) value, 25 ps per lsb; [2] ADLY input mux; [1-0] DCLK input mux
|
||||
{0x0114, 0x22}, // [6] DCLK half step value; [5] SDCLK output MUX; [4-1] SDCLK DDLY; [0] SYSREF half step value
|
||||
{0x0115, 0x00}, // SYSREF: [4] ADLY enable; [3:0] ADLY value, 600 ps + 150 ps per lsb
|
||||
{0x0116, 0xF0}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable
|
||||
{0x0117, 0x11}, // [7] SDCLK output polarity; [6-4] SDCLK output format; [3] DCLK output polarity; [2:0] DCLK output format
|
||||
// device clock 6
|
||||
{0x0118, 0x10}, // [6] output drive level (ODL); [5] input drive level (IDL); [4-0] device clock (DCLK) output divider
|
||||
{0x0119, 0x55}, // DCLK: [7-4] output digital delay (DDLY) high count; [3-0] DDLY low count
|
||||
{0x011A, 0x55},
|
||||
{0x011B, 0x00}, // DCLK: [7-3] analog delay (ADLY) value, 25 ps per lsb; [2] ADLY input mux; [1-0] DCLK input mux
|
||||
{0x011C, 0x02}, // [6] DCLK half step value; [5] SDCLK output MUX; [4-1] SDCLK DDLY; [0] SYSREF half step value
|
||||
{0x011D, 0x00}, // SYSREF: [4] ADLY enable; [3:0] ADLY value, 600 ps + 150 ps per lsb
|
||||
{0x011E, 0xF0}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable
|
||||
{0x011F, 0x55}, // [7] SDCLK output polarity; [6-4] SDCLK output format; [3] DCLK output polarity; [2:0] DCLK output format
|
||||
// device clock 8
|
||||
{0x0120, 0x10}, // [6] output drive level (ODL); [5] input drive level (IDL); [4-0] device clock (DCLK) output divider
|
||||
{0x0121, 0x55}, // DCLK: [7-4] output digital delay (DDLY) high count; [3-0] DDLY low count
|
||||
{0x0122, 0x55},
|
||||
{0x0123, 0x00}, // DCLK: [7-3] analog delay (ADLY) value, 25 ps per lsb; [2] ADLY input mux; [1-0] DCLK input mux
|
||||
{0x0124, 0x22}, // [6] DCLK half step value; [5] SDCLK output MUX; [4-1] SDCLK DDLY; [0] SYSREF half step value
|
||||
{0x0125, 0x00}, // SYSREF: [4] ADLY enable; [3:0] ADLY value, 600 ps + 150 ps per lsb
|
||||
{0x0126, 0xF0}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable
|
||||
{0x0127, 0x55}, // [7] SDCLK output polarity; [6-4] SDCLK output format; [3] DCLK output polarity; [2:0] DCLK output format
|
||||
// device clock 10
|
||||
{0x0128, 0x10}, // [6] output drive level (ODL); [5] input drive level (IDL); [4-0] device clock (DCLK) output divider
|
||||
{0x0129, 0x55}, // DCLK: [7-4] output digital delay (DDLY) high count; [3-0] DDLY low count
|
||||
{0x012A, 0x55},
|
||||
{0x012B, 0x00}, // DCLK: [7-3] analog delay (ADLY) value, 25 ps per lsb; [2] ADLY input mux; [1-0] DCLK input mux
|
||||
{0x012C, 0x22}, // [6] DCLK half step value; [5] SDCLK output MUX; [4-1] SDCLK DDLY; [0] SYSREF half step value
|
||||
{0x012D, 0x00}, // SYSREF: [4] ADLY enable; [3:0] ADLY value, 600 ps + 150 ps per lsb
|
||||
{0x012E, 0xF0}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable
|
||||
{0x012F, 0x51}, // [7] SDCLK output polarity; [6-4] SDCLK output format; [3] DCLK output polarity; [2:0] DCLK output format
|
||||
// device clock 12
|
||||
{0x0130, 0x10}, // [6] output drive level (ODL); [5] input drive level (IDL); [4-0] device clock (DCLK) output divider
|
||||
{0x0131, 0x55}, // DCLK: [7-4] output digital delay (DDLY) high count; [3-0] DDLY low count
|
||||
{0x0132, 0x55},
|
||||
{0x0133, 0x00}, // DCLK: [7-3] analog delay (ADLY) value, 25 ps per lsb; [2] ADLY input mux; [1-0] DCLK input mux
|
||||
{0x0134, 0x22}, // [6] DCLK half step value; [5] SDCLK output MUX; [4-1] SDCLK DDLY; [0] SYSREF half step value
|
||||
{0x0135, 0x00}, // SYSREF: [4] ADLY enable; [3:0] ADLY value, 600 ps + 150 ps per lsb
|
||||
{0x0136, 0xF0}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable
|
||||
{0x0137, 0x55}, // [7] SDCLK output polarity; [6-4] SDCLK output format; [3] DCLK output polarity; [2:0] DCLK output format
|
||||
// clock distribution source
|
||||
{0x0138, 0x20}, // [6-5] VCO mux; [4] OSCout mux; [3:0] OSCout format
|
||||
{0x0139, 0x03}, // [2] SYSREF output mux; [1-0] SYSREF source
|
||||
{0x013A, 0x0C}, // [4-0] SYSREF divider [12:8]
|
||||
{0x013B, 0x00}, // [7-0] SYSREF divider [7:0]
|
||||
{0x013C, 0x00}, // [4-0] SYSREF DDLY [12:8]
|
||||
{0x013D, 0x08}, // [7-0] SYSREF DDLY [7:0]
|
||||
{0x013E, 0x03}, // [1-0] SYSREF pulse count
|
||||
{0x013F, 0x00}, // [4] pll2 mux; [3] pll1 mux; [2-1] feedback mux; [0] feedback mux enable
|
||||
{0x0140, 0x0B}, // power-down control: [7] pll1; [6] vco_ldo; [5] vco; [4] OSCin; [3] individual SYSREF; [2] SYSREF; [1] SYSREF DDLY; [0] SYSREF pluse generator
|
||||
{0x0141, 0x00}, // dynamic DDLY control
|
||||
{0x0142, 0x00}, // dynamic DDLY step control
|
||||
{0x0143, 0x10},
|
||||
{0x0144, 0xFF},
|
||||
{0x0145, 0x7F},
|
||||
{0x0146, 0x12},
|
||||
{0x0147, 0x1A},
|
||||
{0x0148, 0x03},
|
||||
{0x0149, 0x05},
|
||||
{0x014A, 0x1B},
|
||||
{0x014B, 0x16},
|
||||
{0x014C, 0x00},
|
||||
{0x014D, 0x00},
|
||||
{0x014E, 0xC0},
|
||||
{0x014F, 0x7F},
|
||||
{0x0150, 0x03},
|
||||
{0x0151, 0x02},
|
||||
{0x0152, 0x00},
|
||||
{0x0153, 0x00},
|
||||
{0x0154, 0x78},
|
||||
{0x0155, 0x00},
|
||||
{0x0156, 0x7D},
|
||||
{0x0157, 0x00},
|
||||
{0x0158, 0x96},
|
||||
{0x0159, 0x06},
|
||||
{0x015A, 0x00},
|
||||
{0x015B, 0xD4},
|
||||
{0x015C, 0x20},
|
||||
{0x015D, 0x00},
|
||||
{0x015E, 0x00},
|
||||
{0x015F, 0x3B},
|
||||
{0x0160, 0x00},
|
||||
{0x0161, 0x02},
|
||||
{0x0162, 0x44},
|
||||
{0x0163, 0x00},
|
||||
{0x0164, 0x00},
|
||||
{0x0165, 0x0C},
|
||||
{0x0171, 0xAA},
|
||||
{0x0172, 0x02},
|
||||
{0x017C, 0x15},
|
||||
{0x017D, 0x33},
|
||||
{0x0166, 0x00},
|
||||
{0x0167, 0x00},
|
||||
{0x0168, 0x19},
|
||||
{0x0169, 0x59},
|
||||
{0x016A, 0x20},
|
||||
{0x016B, 0x00},
|
||||
{0x016C, 0x00},
|
||||
{0x016D, 0x00},
|
||||
{0x016E, 0x1B},
|
||||
{0x0173, 0x00},
|
||||
{0x0182, 0x00},
|
||||
{0x0183, 0x00},
|
||||
{0x0184, 0x00},
|
||||
{0x0185, 0x00},
|
||||
{0x0188, 0x00},
|
||||
{0x0189, 0x00},
|
||||
{0x018A, 0x00},
|
||||
{0x018B, 0x00},
|
||||
{0x1FFD, 0x00},
|
||||
{0x1FFE, 0x00},
|
||||
{0x1FFF, 0x53}
|
||||
};
|
||||
@@ -0,0 +1,181 @@
|
||||
#include "dev_profile.h"
|
||||
#include "spi.h"
|
||||
#include "../config/app_config.h"
|
||||
#include "../drivers/frequency/lmx2594/lmx2594.h"
|
||||
#include "../drivers/axi_core/spi_engine/spi_engine.h"
|
||||
#include "../drivers/platform/xilinx_gpio.h"
|
||||
|
||||
static struct spi_engine_init_param spi_engine_param = {
|
||||
.ref_clk_hz = AD9653_SPI_ENGINE_REF_CLK,
|
||||
.type = SPI_ENGINE,
|
||||
.spi_engine_baseaddr = AD9653_SPI_ENGINE_BASEADDR,
|
||||
.cs_delay = AD9653_SPI_ENGINE_CS_DELAY,
|
||||
.data_width = AD9653_SPI_ENGINE_DATA_WIDTH
|
||||
};
|
||||
|
||||
//static struct xil_gpio_init_param xil_gpio_param = {
|
||||
// .type = GPIO_PS,
|
||||
// .device_id = AD9653_GPIO_DEVICE_ID
|
||||
//};
|
||||
|
||||
static struct spi_init_param lmx2594_adc_spi_init = {
|
||||
.device_id = LMX2594_ADC_SPI_DEVICE_ID,
|
||||
.max_speed_hz = LMX2594_ADC_SPI_ENGINE_MAX_SPEED,
|
||||
.mode = SPI_MODE_0,
|
||||
.chip_select = LMX2594_ADC_SPI_CS,
|
||||
.platform_ops = &spi_eng_platform_ops,
|
||||
.extra = &spi_engine_param
|
||||
};
|
||||
|
||||
static struct spi_init_param lmx2594_dac_spi_init = {
|
||||
.device_id = LMX2594_DAC_SPI_DEVICE_ID,
|
||||
.max_speed_hz = LMX2594_DAC_SPI_ENGINE_MAX_SPEED,
|
||||
.mode = SPI_MODE_0,
|
||||
.chip_select = LMX2594_DAC_SPI_CS,
|
||||
.platform_ops = &spi_eng_platform_ops,
|
||||
.extra = &spi_engine_param
|
||||
};
|
||||
|
||||
struct lmx2594_init_param lmx2594_adc_init_param = {
|
||||
/* SPI */
|
||||
.spi_init = &lmx2594_adc_spi_init
|
||||
};
|
||||
|
||||
struct lmx2594_init_param lmx2594_dac_init_param = {
|
||||
/* SPI */
|
||||
.spi_init = &lmx2594_dac_spi_init
|
||||
};
|
||||
|
||||
const uint32_t lmx2594_default_config_len = 110;
|
||||
const struct lmx2594_config lmx2594_default_config[] = {
|
||||
// 0 ~ 78: General configuration
|
||||
// 79 ~ 106: Ramping configuration
|
||||
// 107 ~ 112: Readback registers
|
||||
|
||||
// Recommended Initial Power-Up Sequence
|
||||
// For the most reliable programming, TI recommends this procedure::
|
||||
// 1. Apply power to device.
|
||||
// 2. Program RESET = 1 to reset registers.
|
||||
// 3. Program RESET = 0 to remove reset.
|
||||
// 4. Program registers as shown in the register map in REVERSE order from highest to lowest.
|
||||
// 5. Wait 10 ms.
|
||||
// 6. Program register R0 one additional time with FCAL_EN = 1 to ensure that the VCO calibration runs from a stable state.
|
||||
|
||||
// Reset
|
||||
{ 0, 0x0002},
|
||||
|
||||
// Remove Reset
|
||||
{ 0, 0x0000},
|
||||
|
||||
// Reverse order programming
|
||||
{106, 0x0000},
|
||||
{105, 0x0021},
|
||||
{104, 0x0000},
|
||||
{103, 0xD555},
|
||||
{102, 0x3F97},
|
||||
{101, 0x0011},
|
||||
{100, 0x0000},
|
||||
{ 99, 0x2AAB},
|
||||
{ 98, 0x01A0},
|
||||
{ 97, 0x0888},
|
||||
{ 96, 0x0000},
|
||||
{ 95, 0x0000}, // fixed
|
||||
{ 94, 0x0000}, // fixed
|
||||
{ 93, 0x0000}, // fixed
|
||||
{ 92, 0x0000}, // fixed
|
||||
{ 91, 0x0000}, // fixed
|
||||
{ 90, 0x0000}, // fixed
|
||||
{ 89, 0x0000}, // fixed
|
||||
{ 88, 0x0000}, // fixed
|
||||
{ 87, 0x0000}, // fixed
|
||||
{ 86, 0x5879},
|
||||
{ 85, 0xEC58},
|
||||
{ 84, 0x0001},
|
||||
{ 83, 0x54C9},
|
||||
{ 82, 0x2961},
|
||||
{ 81, 0x0000},
|
||||
{ 80, 0x4000},
|
||||
{ 79, 0x001F},
|
||||
{ 78, 0x0003}, // [8:1] VCO_CAPCTRL_STRT
|
||||
{ 77, 0x0000}, // fixed
|
||||
{ 76, 0x000C}, // fixed
|
||||
{ 75, 0x0800}, // [10:6] CHDIV
|
||||
{ 74, 0x0000}, // [11:6] JESD_DAC4_CTRL; [5:0] JESD_DAC3_CTRL
|
||||
{ 73, 0x003F}, // [11:6] JESD_DAC2_CTRL; [5:0] JESD_DAC1_CTRL
|
||||
{ 72, 0x0001}, // [10:0] SYSREF_DIV
|
||||
{ 71, 0x0081}, // [7:5] SYSREF_DIV_PRE; [4] SYSREF_PULSE; [3] SYSREF_EN; [2] SYSREF_REPEAT
|
||||
{ 70, 0xC350}, // [15:0] MASH_RST_COUNT
|
||||
{ 69, 0x0000}, // [15:0] MASH_RST_COUNT
|
||||
{ 68, 0x03E8}, // fixed
|
||||
{ 67, 0x0000}, // fixed
|
||||
{ 66, 0x01F4}, // fixed
|
||||
{ 65, 0x0000}, // fixed
|
||||
{ 64, 0x1388}, // fixed
|
||||
{ 63, 0x0000}, // fixed
|
||||
{ 62, 0x0322}, // fixed
|
||||
{ 61, 0x00A8}, // fixed
|
||||
{ 60, 0x0000}, // [15:0] LD_DLY
|
||||
{ 59, 0x0001}, // [0] LD_TYPE
|
||||
{ 58, 0x9001}, // [15] INPIN_IGNORE; [14] INPIN_HYST; [13:12] INPIN_LVL; [11:9] INPIN_FMT
|
||||
{ 57, 0x0020}, // fixed
|
||||
{ 56, 0x0000}, // fixed
|
||||
{ 55, 0x0000}, // fixed
|
||||
{ 54, 0x0000}, // fixed
|
||||
{ 53, 0x0000}, // fixed
|
||||
{ 52, 0x0820}, // fixed
|
||||
{ 51, 0x0080}, // fixed
|
||||
{ 50, 0x0000}, // fixed
|
||||
{ 49, 0x4180}, // fixed
|
||||
{ 48, 0x0300}, // fixed
|
||||
{ 47, 0x0300}, // fixed
|
||||
{ 46, 0x07FC}, // [1:0] OUTB_MUX
|
||||
{ 45, 0xC0DF}, // [12:11] OUTA_MUX; [10:9] OUT_ISET; [5:0] OUTB_PWR
|
||||
{ 44, 0x1AA3}, // [13:8] OUTA_PWR; [7] OUTB_PD; [6] OUTA_PD; [5] MASH_RESET_N; [2:0] MASH_ORDER
|
||||
{ 43, 0x0000}, // [15:0] PLL_NUM
|
||||
{ 42, 0x0000}, // [15:0] PLL_NUM
|
||||
{ 41, 0x0000}, // [15:0] MASH_SEE
|
||||
{ 40, 0x0000}, // [15:0] MASH_SEE
|
||||
{ 39, 0x03E8}, // [15:0] PLL_DEN
|
||||
{ 38, 0x0000}, // [15:0] PLL_DEN
|
||||
{ 37, 0x0304}, // [37] MASH_SEED_EN; [13:8] PFD_DLY_SEL
|
||||
{ 36, 0x0028}, // [15:0] PLL_N
|
||||
{ 35, 0x0004}, // fixed
|
||||
{ 34, 0x0000}, // [2:0] PLL_N
|
||||
{ 33, 0x1E21}, // fixed
|
||||
{ 32, 0x0393}, // fixed
|
||||
{ 31, 0x43EC}, // [14] SEG1_EN
|
||||
{ 30, 0x318C}, // fixed
|
||||
{ 29, 0x318C}, // fixed
|
||||
{ 28, 0x0488}, // fixed
|
||||
{ 27, 0x0002}, // fixed
|
||||
{ 26, 0x0DB0}, // fixed
|
||||
{ 25, 0x0C2B}, // fixed
|
||||
{ 24, 0x071A}, // fixed
|
||||
{ 23, 0x007C}, // fixed
|
||||
{ 22, 0x0001}, // fixed
|
||||
{ 21, 0x0401}, // fixed
|
||||
{ 20, 0xE048}, // [13:11] VCO_SEL. [10] VCO_SEL_FORCE
|
||||
{ 19, 0x27B7}, // [7:0] VCO_CAPCTRL
|
||||
{ 18, 0x0064}, // fixed
|
||||
{ 17, 0x012C}, // [8:0] VCO_DACISET_STRT
|
||||
{ 16, 0x0080}, // [8:0] VCO_DACISET
|
||||
{ 15, 0x064F}, // fixed
|
||||
{ 14, 0x1E70}, // [6:4] CPG
|
||||
{ 13, 0x4000}, // fixed
|
||||
{ 12, 0x5001}, // [11:0] PLL_R_PR
|
||||
{ 11, 0x0018}, // [11:4] PLL_R
|
||||
{ 10, 0x10D8}, // [11:7] MULT
|
||||
{ 9, 0x0604}, // [12] OSC_2X
|
||||
{ 8, 0x2000}, // [14] VCO_DACISET_FORCE; [11] VCO_CAPCTRL_FORCE
|
||||
{ 7, 0x40B2}, // [14] OUT_FORCE
|
||||
{ 6, 0xC802}, // fixed
|
||||
{ 5, 0x00C8}, // fixed
|
||||
{ 4, 0x0C43}, // [15:8] ACAL_CMP_DLY
|
||||
{ 3, 0x0642}, // fixed
|
||||
{ 2, 0x0500}, // fixed
|
||||
{ 1, 0x0809}, // [2:0] CAL_CLK_DIV
|
||||
{ 0, 0x2598}, // [15] RAMP_EN; [14] VCO_PHASE_SYNC; [9] OUT_MUTE; [8:7] FCAL_HPFD_ADJ; [6:5] FCAL_LPFD_ADJ; [3] FCAL_EN; [2] MUXOUT_LD_SEL; [1] RESET; [0] POWERDOWN
|
||||
|
||||
// one more time
|
||||
{ 0, 0x2598}
|
||||
};
|
||||
@@ -3,15 +3,19 @@
|
||||
#include "../config/app_config.h"
|
||||
#include "../drivers/platform/xilinx_timer.h"
|
||||
|
||||
struct xil_timer_init_param xil_scutimer_init_param = {
|
||||
struct xil_timer_init_param xil_apptimer_init_param = {
|
||||
.active_tmr = 0,
|
||||
#ifdef __aarch64__
|
||||
.type = TIMER_PL
|
||||
#else
|
||||
.type = TIMER_PS
|
||||
#endif
|
||||
};
|
||||
|
||||
struct timer_init_param scutimer_init_param = {
|
||||
.id = SCUTIMER_DEVICE_ID,
|
||||
.freq_hz = SCU_TIMER_CLK_HZ,
|
||||
.ticks_count = (SCU_TIMER_CLK_HZ/2), //update log every 500ms
|
||||
struct timer_init_param apptimer_init_param = {
|
||||
.id = APPTIMER_DEVICE_ID,
|
||||
.freq_hz = APP_TIMER_CLK_HZ,
|
||||
.ticks_count = (APP_TIMER_CLK_HZ/10), //update log every 100ms
|
||||
.platform_ops = &xil_timer_ops,
|
||||
.extra = &xil_scutimer_init_param
|
||||
.extra = &xil_apptimer_init_param
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user