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2024-01-19 17:19:32 +08:00
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df_datalink_sp/src/networking/phy_layer/phy_antenna.c
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/*****************************************************************************/
/**
* Description: Antenna configuration functions.
*
* Author: Fan Hao
* Date: 2022-06-18 16:37
* LastEditors: Fan Hao
* LastEditTime: 2022-06-18 17:15
* Revisions: Rev 0.0
* History:
* [2022-06-18]: Initial version.
*
* Copyright(c) 2022 Beijing Institute of Technology.
* Lab of Communication and Networking
*
******************************************************************************/
#include <string.h>
#include <stdint.h>
#include <math.h>
#include "error.h"
#include "../config//app_config.h"
#include "phy_layer.h"
#define ANT_PI 3.14159265358979323846
#define ANT_COINFO_HEAD 0xAA
#define ANT_COINFO_TAIL 0xCC
#define CTRL_WORD_DEFAULT 0x00
#define ANT_MODE_BEAM_MASK 0xF0
#define ANT_MODE_NARROR_BEAM 0x00 // 8
#define ANT_MODE_WIDE_BEAM_1 0x10 // 25
#define ANT_MODE_WIDE_BEAM_2 0x20 // 60
#define ANT_MODE_WIDE_BEAM_3 0x30 // 120
#define ANT_MODE_HIGH_POWER 0x00
#define ANT_MODE_LOWAPOWER 0x04
#define ANT_MODE_STANDBY 0x0F
#define ATN_MODE_DEFAULT (ANT_MODE_WIDE_BEAM_1 | ANT_MODE_LOWAPOWER)
#define ATN_MODE_HIGH (ANT_MODE_WIDE_BEAM_1 | ANT_MODE_HIGH_POWER)
#define DEFAULT_CENTRTAL_FREQ 0x06D7 // 26.25GHz
#define RXTXMODE_RX 0x00
#define RXTXMODE_TX 0x01
#define RXTXMODE_DEFAULT 0x00
#define CALIBRMODE_NORMAL 0x00
#define CALIBRMODE_SINGLE_TR_CAL 0x01
#define RF_CTRL_DEFAULT 0x00
// Pair by regex
// Regex: (([0-9]+, ){8})
uint16_t hopPattern_Config[L1_FRAME_MAX_HOPS] =
{
0
};
uint16_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS] =
{
1500
};
// uint16_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS] =
// {
// 0, 44, 88, 131, 175, 219, 263, 306,
// 350, 394, 438, 481, 525, 569, 613, 656,
// 700, 744, 788, 831, 875, 919, 963, 1006,
// 1050, 1094, 1138, 1181, 1225, 1269, 1313, 1356,
// 1400, 1444, 1488, 1531, 1575, 1619, 1663, 1706,
// 1750, 1794, 1838, 1881, 1925, 1969, 2013, 2056,
// 2100, 2144, 2188, 2231, 2275, 2319, 2363, 2406,
// 2450, 2494, 2538, 2581, 2625, 2669, 2713, 2756,
// 2800, 2844, 2888, 2931, 2975, 3019, 3063, 3106,
// 3150, 3194, 3238, 3281, 3325, 3369, 3413, 3456,
// 3500
// };
uint16_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS] =
{
1500
};
uint16_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS] =
{
1500
};
uint16_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS] =
{
1500, 1600, 1700, 1800, 1900, 2000, 1500, 1600,
1700, 1800, 1900
};
uint16_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS] =
{
2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
2400, 2400, 2400
};
uint16_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS] =
{
2400, 2400, 2400, 2400, 2400, 2400, 2400, 2400,
2400
};
uint16_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS] =
{
500, 1600, 1700, 1800, 1900, 2000, 1500, 1600,
1700, 1800, 1900, 2000, 1500, 1600, 1700, 1800,
1900, 2000, 1500, 1500
};
uint16_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS] =
{
500, 600, 700, 800, 900, 1000, 500, 600,
700, 800, 900, 1000, 500, 600, 700, 800,
900, 1000, 500, 500
};
// Pair by regex
// Regex: ((\{\.oaxis = [0-9]+[ ,]+\.raxis = [0-9]+[ ]*\}, ){2})
#ifdef PHY_BEAM_SET_PRESET
PHY_ANT_ANGLE antSubnrrwPattern[L1_NUM_ANT_SUBNRRW_PATTERN] =
{
{.oaxis = 0 , .raxis = 222}, {.oaxis = 10, .raxis = 85 },
{.oaxis = 14, .raxis = 307}, {.oaxis = 17, .raxis = 170},
{.oaxis = 19, .raxis = 32 }, {.oaxis = 21, .raxis = 255},
{.oaxis = 24, .raxis = 117}, {.oaxis = 25, .raxis = 340},
{.oaxis = 27, .raxis = 202}, {.oaxis = 29, .raxis = 65 },
{.oaxis = 31, .raxis = 287}, {.oaxis = 32, .raxis = 150},
{.oaxis = 34, .raxis = 12 }, {.oaxis = 35, .raxis = 235},
{.oaxis = 36, .raxis = 97 }, {.oaxis = 38, .raxis = 320},
{.oaxis = 39, .raxis = 182}, {.oaxis = 40, .raxis = 45 },
{.oaxis = 41, .raxis = 267}, {.oaxis = 43, .raxis = 130},
{.oaxis = 44, .raxis = 352}, {.oaxis = 45, .raxis = 215},
{.oaxis = 46, .raxis = 77 }, {.oaxis = 47, .raxis = 300},
{.oaxis = 48, .raxis = 162}, {.oaxis = 49, .raxis = 25 },
{.oaxis = 50, .raxis = 247}, {.oaxis = 51, .raxis = 110},
{.oaxis = 52, .raxis = 332}, {.oaxis = 53, .raxis = 195},
{.oaxis = 54, .raxis = 57 }, {.oaxis = 55, .raxis = 280},
{.oaxis = 56, .raxis = 142}, {.oaxis = 57, .raxis = 5 },
{.oaxis = 58, .raxis = 227}, {.oaxis = 59, .raxis = 90 },
{.oaxis = 60, .raxis = 312}
};
PHY_ANT_ANGLE antNrrwPattern[L1_NUM_ANT_NRRW_PATTERN] =
{
{.oaxis = 0 , .raxis = 222}, {.oaxis = 7 , .raxis = 85 },
{.oaxis = 10, .raxis = 307}, {.oaxis = 13, .raxis = 170},
{.oaxis = 15, .raxis = 32 }, {.oaxis = 17, .raxis = 255},
{.oaxis = 18, .raxis = 117}, {.oaxis = 20, .raxis = 340},
{.oaxis = 21, .raxis = 202}, {.oaxis = 22, .raxis = 65 },
{.oaxis = 24, .raxis = 287}, {.oaxis = 25, .raxis = 150},
{.oaxis = 26, .raxis = 12 }, {.oaxis = 27, .raxis = 235},
{.oaxis = 28, .raxis = 97 }, {.oaxis = 29, .raxis = 320},
{.oaxis = 30, .raxis = 182}, {.oaxis = 31, .raxis = 45 },
{.oaxis = 32, .raxis = 267}, {.oaxis = 33, .raxis = 130},
{.oaxis = 34, .raxis = 352}, {.oaxis = 34, .raxis = 215},
{.oaxis = 35, .raxis = 77 }, {.oaxis = 36, .raxis = 300},
{.oaxis = 37, .raxis = 162}, {.oaxis = 38, .raxis = 25 },
{.oaxis = 38, .raxis = 247}, {.oaxis = 39, .raxis = 110},
{.oaxis = 40, .raxis = 332}, {.oaxis = 41, .raxis = 195},
{.oaxis = 41, .raxis = 57 }, {.oaxis = 42, .raxis = 280},
{.oaxis = 43, .raxis = 142}, {.oaxis = 44, .raxis = 5 },
{.oaxis = 44, .raxis = 227}, {.oaxis = 45, .raxis = 90 },
{.oaxis = 46, .raxis = 312}, {.oaxis = 46, .raxis = 175},
{.oaxis = 47, .raxis = 37 }, {.oaxis = 48, .raxis = 260},
{.oaxis = 48, .raxis = 122}, {.oaxis = 49, .raxis = 345},
{.oaxis = 49, .raxis = 207}, {.oaxis = 50, .raxis = 70 },
{.oaxis = 51, .raxis = 292}, {.oaxis = 51, .raxis = 155},
{.oaxis = 52, .raxis = 17 }, {.oaxis = 53, .raxis = 240},
{.oaxis = 53, .raxis = 102}, {.oaxis = 54, .raxis = 325},
{.oaxis = 54, .raxis = 187}, {.oaxis = 55, .raxis = 50 },
{.oaxis = 55, .raxis = 272}, {.oaxis = 56, .raxis = 135},
{.oaxis = 57, .raxis = 357}, {.oaxis = 57, .raxis = 220},
{.oaxis = 58, .raxis = 82 }, {.oaxis = 58, .raxis = 305},
{.oaxis = 59, .raxis = 167}, {.oaxis = 59, .raxis = 30 },
{.oaxis = 60, .raxis = 252}
};
#else
PHY_ANT_ANGLE antSubnrrwPattern[NUM_ANT_SUBNRRW_PATTERN] =
{
0
};
PHY_ANT_ANGLE antNrrwPattern[NUM_ANT_NRRW_PATTERN] =
{
0
};
#endif
/*****************************************************************************/
/**
* @brief
*
* @param antConfigPtr
*
* @return
*
******************************************************************************/
int32_t Phy_AntConfigInit(PHY_ANT_COINFO *antConfigPtr)
{
ASSERT(antConfigPtr != NULL);
antConfigPtr->ctrlWord = 0x00;
antConfigPtr->antMode = ATN_MODE_DEFAULT;
// FIXME: Dummy default value.
// off axis angle setting
antConfigPtr->oaxis[0] = 0;
antConfigPtr->oaxis[1] = 0;
// round axis angle setting
antConfigPtr->raxis[0] = 0;
antConfigPtr->raxis[1] = 0;
// ***********************
antConfigPtr->antFreq[0] = (uint8_t)(DEFAULT_CENTRTAL_FREQ);
antConfigPtr->antFreq[1] = (uint8_t)(DEFAULT_CENTRTAL_FREQ >> 8);
// FIXME: Dummy default value.
// trSelect
antConfigPtr->trSlect = 0;
// Antenna attenuation setting
antConfigPtr->antAtt = 20;
// phase setting
antConfigPtr->phase = 0;
// ***********************
antConfigPtr->rxtxMode = RXTXMODE_DEFAULT;
antConfigPtr->calibrMode = CALIBRMODE_NORMAL;
antConfigPtr->antReserved = 0x00;
// FIXME: Dummy default value.
// RF mode control
antConfigPtr->rfCtrl = RF_CTRL_DEFAULT;
// RF frequency
antConfigPtr->rfFreq[0] = (uint8_t)(DEFAULT_CENTRTAL_FREQ);
antConfigPtr->rfFreq[1] = (uint8_t)(DEFAULT_CENTRTAL_FREQ >> 8);
// RF MGC control
antConfigPtr->rfTxMgc = 0;
// RF channel 1&2 calibration mgc
antConfigPtr->rf12CalMgc = 0;
// RF channel 2&3 calibration mgc
antConfigPtr->rf34CalMgc = 0;
// Receive channel 1-4 MGC
antConfigPtr->rcvMgc = 0;
antConfigPtr->rfReserved0 = 0x00;
antConfigPtr->rfReserved1 = 0x00;
// ***********************
return SUCCESS;
}
int32_t Phy_SetBeamNo(PHY_INST *instPtr, int32_t beamNo)
{
if (instPtr->beamWd.next == PHY_ANT_BEAM_8)
{
if (beamNo >= L1_NUM_ANT_NRRW_PATTERN)
{
return FAILURE;
}
else
{
instPtr->beamNo.next = beamNo;
instPtr->antConfigPtr.oaxis[1] = (uint8_t)(antNrrwPattern[beamNo].oaxis);
instPtr->antConfigPtr.oaxis[0] = (uint8_t)((antNrrwPattern[beamNo].oaxis) >> 8);
instPtr->antConfigPtr.raxis[1] = (uint8_t)(antNrrwPattern[beamNo].raxis);
instPtr->antConfigPtr.raxis[0] = (uint8_t)((antNrrwPattern[beamNo].raxis) >> 8);
return SUCCESS;
}
}
else if (instPtr->beamWd.next == PHY_ANT_BEAM_25)
{
if (beamNo >= L1_NUM_ANT_SUBNRRW_PATTERN)
{
return FAILURE;
}
else
{
instPtr->beamNo.next = beamNo;
instPtr->antConfigPtr.oaxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].oaxis);
instPtr->antConfigPtr.oaxis[0] = (uint8_t)((antSubnrrwPattern[beamNo].oaxis) >> 8);
instPtr->antConfigPtr.raxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].raxis);
instPtr->antConfigPtr.raxis[0] = (uint8_t)((antSubnrrwPattern[beamNo].raxis) >> 8);
return SUCCESS;
}
}
else
{
// Beam number assign not support.
// Assign default angle (0,0)
instPtr->beamNo.next = 0;
instPtr->antConfigPtr.oaxis[1] = 0;
instPtr->antConfigPtr.oaxis[0] = 0;
instPtr->antConfigPtr.raxis[1] = 0;
instPtr->antConfigPtr.raxis[0] = 0;
DBG_WARNING("Using default beam number...\n");
return SUCCESS;
}
}
int32_t Phy_SetBeamWidth(PHY_INST *instPtr, PHY_ANT_BEAM_WIDTH beamWidth)
{
uint8_t beamConfig = instPtr->antConfigPtr.antMode & (~ANT_MODE_BEAM_MASK);
switch (beamWidth)
{
case PHY_ANT_BEAM_120:
beamConfig |= ANT_MODE_WIDE_BEAM_3;
break;
case PHY_ANT_BEAM_60:
beamConfig |= ANT_MODE_WIDE_BEAM_2;
break;
case PHY_ANT_BEAM_25:
beamConfig |= ANT_MODE_WIDE_BEAM_1;
break;
case PHY_ANT_BEAM_8:
beamConfig |= ANT_MODE_NARROR_BEAM;
break;
default:
DBG_ERROR("Beam width code: 0x%08X is illegal.\n\r", beamWidth);
return EPARAM;
break;
}
instPtr->antConfigPtr.antMode = beamConfig;
instPtr->beamWd.next = beamWidth;
return SUCCESS;
}
// Common version radius double input
int32_t Phy_SetBeamAngle(PHY_INST *phyInstPtr, double offAx, double rndAx)
{
uint16_t offAxDeg = 0;
uint16_t rndAxDeg = 0;
offAxDeg = (offAx >= 0) ? (((int32_t)(offAx * 180 / ANT_PI)) % 360) : (((int32_t)(offAx * 180 / ANT_PI)) % 360 + 360);
rndAxDeg = (rndAx >= 0) ? (((int32_t)(rndAx * 180 / ANT_PI)) % 360) : (((int32_t)(rndAx * 180 / ANT_PI)) % 360 + 360);
if (offAxDeg > 60)
{
DBG_ERROR("Angle out of range, off axis angle: %u (should be 0~60), round axis angle: %u (should be 0~360).\n",
offAxDeg, rndAxDeg);
return EPARAM;
}
offAxDeg = offAxDeg * 10;
rndAxDeg = rndAxDeg * 10;
phyInstPtr->antConfigPtr.oaxis[1] = (uint8_t)offAxDeg;
phyInstPtr->antConfigPtr.oaxis[0] = (uint8_t)(offAxDeg >> 8);
phyInstPtr->antConfigPtr.raxis[1] = (uint8_t)rndAxDeg;
phyInstPtr->antConfigPtr.raxis[0] = (uint8_t)(rndAxDeg >> 8);
return SUCCESS;
}
df_datalink_sp/src/networking/phy_layer/phy_layer.c
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/*****************************************************************************/
/**
* Description: Implementation of physical control functions
*
* Date: 2021-11-16 00:08
* LastEditTime: 2023-04-23 17:48
* Revisions: Rev 0.2
* History:
* [2021-11-16]: Initial version.
* [2022-06-18]: New branch for glink control purpose:
* -Add poll mode, physical layer will start Tx/Rx procedure
* at specific time stamp.
* -Add 61/37 beam switch
* -Code simplification.
* [2023-04-24]: Porting for DUIFEI.
*
* Copyright(c) 2021 Beijing Institute of Technology.
* Lab of Communication and Networking
*
******************************************************************************/
/***************************** Include Files *********************************/
#include <string.h>
#include <stdlib.h>
#include "xbram.h"
#include "xadcps.h"
#include "phy_layer.h"
#include "util.h"
#include "error.h"
#include "../config/app_config.h"
/************************** Constant Definitions *****************************/
#define TOR_BUFF_MAX_SIZE 1024 // 8192bits
#define TMWORD_FRAC_MAX 500000
#define ANTCONFIG_MAX_LEN (8192 / 2)
#define PAYLOAD_MAX_LEN (4096 / 2)
#define INIT_BEAM_NO 0
#define INIT_ANT_WD PHY_ANT_BEAM_120
#define INIT_ANT_NO 0
#define L1_FRAME_NONE_LEN UINT32_MAX // byte
#define L1_FRAME_2KBPS_20MS_LEN 0 // byte
#define L1_FRAME_2KBPS_100MS_LEN (240 / 8) // byte
#define L1_FRAME_10KBPS_10MS_LEN 0 // byte
#define L1_FRAME_10KBPS_20MS_LEN (240 / 8) // byte
#define L1_FRAME_40KBPS_20MS_LEN (2160 / 8) // byte
#define L1_FRAME_40KBPS_10MS_LEN (720 / 8) // byte
#define L1_FRAME_200KBPS_5MS_LEN (2048 / 8) // byte
#define L1_FRAME_1M2BPS_5MS_LEN (8184 / 8) // byte
#define L1_FRAME_NONE_COMP UINT32_MAX // *10ns
#define L1_FRAME_2KBPS_20MS_COMP 1622400 // *10ns
#define L1_FRAME_2KBPS_100MS_COMP 1622400 // *10ns
#define L1_FRAME_10KBPS_10MS_COMP 747366 // *10ns
#define L1_FRAME_10KBPS_20MS_COMP 747366 // *10ns
#define L1_FRAME_40KBPS_20MS_COMP 97066 // *10ns
#define L1_FRAME_40KBPS_10MS_COMP 97066 // *10ns
#define L1_FRAME_200KBPS_5MS_COMP 17067 // *10ns
#define L1_FRAME_1M2BPS_5MS_COMP 17067 // *10ns
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static void Phy_RcdShift(PHY_RCD *rcd, int32_t netxVal);
static int32_t SetSendData(PHY_INST *instPtr, L1_FRAME_TYPE frameType, uint8_t *buff);
/**************************** Type Definitions *******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* @brief Get received data (base on PS Record), store it to data buffer.
*
* @param instPtr
* rcvBuffPtr
*
* @return SUCCESS
* FAILURE last frame type cannot be recognized.
*
******************************************************************************/
int32_t Phy_RetrieveRecvData(PHY_INST *instPtr, uint8_t *buff)
{
ASSERT(instPtr != NULL);
uint32_t frameLen, recvBramAddr;
frameLen = Phy_GetFrameLen(instPtr->frameType.last);
if (frameLen == L1_FRAME_NONE_LEN)
{
return FAILURE;
}
else
{
// Ping-pong flow.
recvBramAddr = instPtr->rxDataPtr + ((PhyRead(instPtr, RECV_DATA_SATE) & RECV_DATA_OFFSET_MASK) >> RECV_DATA_OFFSET_SHIFT);
memcpy(buff, (uint8_t *)recvBramAddr, frameLen);
}
return SUCCESS;
}
/*****************************************************************************/
/**
* @brief Setup data will be sent in next slot.
*
* @param instPtr A pointer to physical layer control instance.
*
* @return FAILURE Error occurred.
* SUCCESS Setting data successful.
*
******************************************************************************/
static int32_t SetSendData(PHY_INST *instPtr, L1_FRAME_TYPE frameType, uint8_t *buff)
{
ASSERT(instPtr != NULL);
uint32_t frameLen, sendCmd;
frameLen = Phy_GetFrameLen(frameType);
if (frameLen == L1_FRAME_NONE_LEN)
{
return FAILURE;
}
else
{
// Implement a ping-pong flow, offset always is 0 or half of buffer depth.
instPtr->sendOffset = (instPtr->sendOffset == PAYLOAD_MAX_LEN) ? 0 : PAYLOAD_MAX_LEN;
memcpy((uint8_t *)(instPtr->txDataPtr + instPtr->sendOffset), buff, frameLen);
// Trigger Physical layer to start fetching data.
sendCmd = frameLen & SEND_DATA_CMD_LEN_MASK;
sendCmd |= (instPtr->sendOffset << SEND_DATA_CMD_OFFSET_SHIFT) & SEND_DATA_CMD_OFFSET_MASK;
PhyWrite(instPtr, SEND_DATA_CMD, sendCmd);
}
return SUCCESS;
}
/*****************************************************************************/
/**
* @brief Check whether a frame was detected. (Do not check if the frame was
* deoced.)
*
* @param instPtr
*
* @return true
* false
*
******************************************************************************/
inline bool Phy_IsFrameDetected(PHY_INST *instPtr)
{
ASSERT(instPtr != NULL);
if (instPtr->TOR.last == PHY_TOR_RX && instPtr->isAcq && instPtr->isFrameSync)
{
return true;
}
else
{
return false;
}
}
/*****************************************************************************/
/**
* @brief Check whether a frame was received. (Do not check if the frame was
* crashed.)
*
* @param instPtr
*
* @return true
* false
*
******************************************************************************/
inline bool Phy_IsFrameReceived(PHY_INST *instPtr)
{
ASSERT(instPtr != NULL);
if (instPtr->TOR.last == PHY_TOR_RX && instPtr->isAcq && instPtr->isFrameSync && instPtr->isDecode)
{
return true;
}
else
{
return false;
}
}
/*****************************************************************************/
/**
* @brief Check whether a frame was valid. (if the frame was crashed, it will
* be regarded as not valid.
*
* @param instPtr
*
* @return true
* false
*
******************************************************************************/
inline bool Phy_IsFrameValid(PHY_INST *instPtr)
{
ASSERT(instPtr != NULL);
if (instPtr->TOR.last == PHY_TOR_RX && instPtr->isAcq && instPtr->isFrameSync && instPtr->isDecode && instPtr->isValid)
{
return true;
}
else
{
return false;
}
}
/*****************************************************************************/
/**
* @brief Get frame type of the frame in receive data buffer (Base on PS Record).
*
* @param instPtr A pointer to physical layer control instance.
*
* @return Layer2 frame type. Refer "frame_def.h"
*
******************************************************************************/
inline L1_FRAME_TYPE Phy_GetLastDetectedFrameType(PHY_INST *instPtr)
{
ASSERT(instPtr != NULL);
if (Phy_IsFrameDetected(instPtr) == false)
{
return L1_NONE_FRAME;
}
else
{
return instPtr->frameType.last;
}
}
/*****************************************************************************/
/**
* @brief Get frame type of the frame in receive data buffer (Base on PS Record).
*
* @param instPtr A pointer to physical layer control instance.
*
* @return Layer2 frame type. Refer "frame_def.h"
*
******************************************************************************/
inline L1_FRAME_TYPE Phy_GetLastReceivedFrameType(PHY_INST *instPtr)
{
ASSERT(instPtr != NULL);
if (Phy_IsFrameReceived(instPtr) == false)
{
return L1_NONE_FRAME;
}
else
{
return instPtr->frameType.last;
}
}
/*****************************************************************************/
/**
* @brief Get frame type of the frame was sent in last slot.
*
* @param instPtr A pointer to physical layer control instance.
*
* @return Layer2 frame type. Refer "frame_def.h"
*
******************************************************************************/
inline L1_FRAME_TYPE Phy_GetLastSentFrameType(PHY_INST *instPtr)
{
ASSERT(instPtr != NULL);
if (instPtr->TOR.last != PHY_TOR_TX)
{
return L1_NONE_FRAME;
}
else
{
return instPtr->frameType.last;
}
}
/*****************************************************************************/
/**
* @brief Shift l1 status record.(newval->next->curr->last)
*
* @param instPtr A pointer to physical layer control instance.
*
* @return NONE.
*
******************************************************************************/
static void Phy_RcdShift(PHY_RCD *rcd, int32_t netxVal)
{
ASSERT(rcd != NULL);
rcd->last = rcd->curr;
rcd->curr = rcd->next;
rcd->next = netxVal;
}
/*****************************************************************************/
/**
* @brief Get corresponding frame length in byte of L1 frame.
*
* @param frameType
*
* @return Corresponding frame length
* L1_FRAME_NONE_LEN if the frame type code cannot be recognized.
*
******************************************************************************/
uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType)
{
switch (frameType)
{
case L1_2KBPS_20MS_FRAME:
// FIXME: for DUIFEI net setup
return L1_FRAME_2KBPS_100MS_LEN;
// return L1_FRAME_2KBPS_20MS_LEN;
case L1_2KBPS_100MS_FRAME:
return L1_FRAME_2KBPS_100MS_LEN;
case L1_10KBPS_10MS_FRAME:
return L1_FRAME_10KBPS_10MS_LEN;
case L1_10KBPS_20MS_FRAME:
return L1_FRAME_10KBPS_20MS_LEN;
case L1_40KBPS_20MS_FRAME:
return L1_FRAME_40KBPS_20MS_LEN;
case L1_40KBPS_10MS_FRAME:
return L1_FRAME_40KBPS_10MS_LEN;
case L1_200KBPS_5MS_FRAME:
return L1_FRAME_200KBPS_5MS_LEN;
case L1_1M2BPS_5MS_FRAME:
return L1_FRAME_1M2BPS_5MS_LEN;
default:
return L1_FRAME_NONE_LEN;
}
}
/*****************************************************************************/
/**
* @brief Update Physical Layer reception status.
*
* @param instPtr
*
* @return
*
******************************************************************************/
void Phy_UpdateState(PHY_INST *instPtr)
{
ASSERT(instPtr != NULL);
Phy_RcdShift(&(instPtr->TOR), PHY_TOR_SUSPEND);
Phy_RcdShift(&(instPtr->frameType), L1_NONE_FRAME);
Phy_RcdShift(&(instPtr->antNo), INIT_ANT_NO);
Phy_RcdShift(&(instPtr->beamNo), INIT_BEAM_NO);
Phy_RcdShift(&(instPtr->beamWd), INIT_ANT_WD);
/* Update Frame Sate. */
uint32_t txrxSate = PhyRead(instPtr, TXRX_STATE);
instPtr->isAcq = ((txrxSate & TXRX_STATE_ACQ_MASK) == TXRX_STATE_ACQ_SUCCESS) ? true : false;
instPtr->isFrameSync = ((txrxSate & TXRX_STATE_FSYNC_MASK) == TXRX_STATE_FSYNC_SUCCESS) ? true : false;
instPtr->isDecode = ((txrxSate & TXRX_STATE_DECODE_MASK) == TXRX_STATE_DECODE_SUCCESS) ? true : false;
if (Phy_IsFrameReceived(instPtr))
{
DBG_INFO("Physical layer finished reception procedure, retrieving received data...\n");
instPtr->isValid = true;
}
else
{
instPtr->isValid = false;
}
return;
}
/*****************************************************************************/
/**
* @brief Initialize Physical Layer instance, allocate memory for buffers,
* apply a self test.
*
* @param instPtr
* phyConfig
*
* @return
*
******************************************************************************/
int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
{
ASSERT(instPtr != NULL);
ASSERT(phyConfig != NULL);
int32_t Status = SUCCESS;
*instPtr = (PHY_INST *)malloc(sizeof(PHY_INST));
if ((*instPtr) == NULL)
{
return ENOMEM;
}
memcpy(&((*instPtr)->phyCofig), phyConfig, sizeof(PHY_CONFIG));
(*instPtr)->isPhyEn = false;
(*instPtr)->isAcq = false;
(*instPtr)->isFrameSync = false;
(*instPtr)->isDecode = false;
(*instPtr)->isValid = false;
(*instPtr)->isPresetHop = true;
(*instPtr)->antConfigOffset = 0;
(*instPtr)->sendOffset = 0;
memset(&((*instPtr))->TOR, PHY_TOR_SUSPEND, sizeof(PHY_RCD));
memset(&((*instPtr)->frameType), L1_NONE_FRAME, sizeof(PHY_RCD));
memset(&((*instPtr)->antNo), (int32_t)INIT_BEAM_NO, sizeof(PHY_RCD));
memset(&((*instPtr)->beamNo), (int32_t)INIT_ANT_NO, sizeof(PHY_RCD));
memset(&((*instPtr)->beamWd), (int32_t)INIT_ANT_WD, sizeof(PHY_RCD));
memset(&((*instPtr)->hwSate), 0x00, sizeof(HWSTATE));
Status = Phy_AntConfigInit(&((*instPtr)->antConfigPtr));
if (Status != SUCCESS)
{
goto init_error;
}
XBram_Config *bramConfigPtr;
XBram antConfigBram;
XBram txDataBram;
XBram rxDataBram;
bramConfigPtr = XBram_LookupConfig(phyConfig->antBramId);
if (bramConfigPtr == NULL)
{
Status = EDCONF;
goto init_error;
}
Status = XBram_CfgInitialize(&antConfigBram, bramConfigPtr,
bramConfigPtr->CtrlBaseAddress);
if (Status != SUCCESS)
{
goto init_error;
}
/*
* Execute the BRAM driver selftest.
*/
Status = XBram_SelfTest(&antConfigBram, 0);
if (Status != SUCCESS)
{
goto init_error;
}
bramConfigPtr = XBram_LookupConfig(phyConfig->txBramId);
if (bramConfigPtr == NULL)
{
Status = EDCONF;
goto init_error;
}
Status = XBram_CfgInitialize(&txDataBram, bramConfigPtr,
bramConfigPtr->CtrlBaseAddress);
if (Status != SUCCESS)
{
goto init_error;
}
/*
* Execute the BRAM driver selftest.
*/
Status = XBram_SelfTest(&txDataBram, 0);
if (Status != SUCCESS)
{
goto init_error;
}
bramConfigPtr = XBram_LookupConfig(phyConfig->rxBramId);
if (bramConfigPtr == NULL)
{
Status = EDCONF;
goto init_error;
}
Status = XBram_CfgInitialize(&rxDataBram, bramConfigPtr,
bramConfigPtr->CtrlBaseAddress);
if (Status != SUCCESS)
{
goto init_error;
}
/*
* Execute the BRAM driver selftest.
*/
Status = XBram_SelfTest(&rxDataBram, 0);
if (Status != SUCCESS)
{
goto init_error;
}
(*instPtr)->txDataPtr = txDataBram.Config.MemBaseAddress;
(*instPtr)->rxDataPtr = rxDataBram.Config.MemBaseAddress;
(*instPtr)->antConfigDataPtr = antConfigBram.Config.MemBaseAddress;
/* Initialize the XAdc driver. */
XAdcPs_Config *xadcConfigPtr;
xadcConfigPtr = XAdcPs_LookupConfig(phyConfig->hwXadcId);
if (xadcConfigPtr == NULL)
{
Status = EDCONF;
goto init_error;
}
XAdcPs_CfgInitialize(&((*instPtr)->hwXadc), xadcConfigPtr, xadcConfigPtr->BaseAddress);
/* Self Test the XADC/ADC device */
Status = XAdcPs_SelfTest(&((*instPtr)->hwXadc));
if (Status != SUCCESS)
{
goto init_error;
}
/* Disable the Channel Sequencer before configuring the Sequence registers. */
XAdcPs_SetSequencerMode(&((*instPtr)->hwXadc), XADCPS_SEQ_MODE_SAFE);
return SUCCESS;
init_error:
free(*instPtr);
return Status;
}
/*****************************************************************************/
/**
* @brief Start physical layer
*
* @param instPtr a pointer to physical instance
*
* @return NONE
*
******************************************************************************/
void Phy_Start(PHY_INST *instPtr)
{
ASSERT(instPtr != NULL);
uint32_t phyMainCtrl = PhyRead(instPtr, PHY_MAIN_CTRL);
if ((phyMainCtrl & PHY_MAIN_CTRL_EN_MASK) == PHY_MAIN_CTRL_EN_EN)
{
DBG_WARNING("Physical layer was already enabled.\n");
}
instPtr->isPhyEn = true;
// Enable CRC check automatically
PhyWrite(instPtr, PHY_MAIN_CTRL, (phyMainCtrl | PHY_MAIN_CTRL_EN_EN));
}
/*****************************************************************************/
/**
* @brief Halt physical layer operation
*
* @param instPtr a pointer to physical instance
*
* @return NONE
*
******************************************************************************/
void Phy_Halt(PHY_INST *instPtr)
{
ASSERT(instPtr != NULL);
uint32_t phyMainCtrl = PhyRead(instPtr, PHY_MAIN_CTRL);
if ((phyMainCtrl & PHY_MAIN_CTRL_EN_MASK) == PHY_MAIN_CTRL_EN_DSBL)
{
DBG_WARNING("Physical layer was allready halted.\n");
}
instPtr->isPhyEn = false;
PhyWrite(instPtr, PHY_MAIN_CTRL, (phyMainCtrl & (~PHY_MAIN_CTRL_EN_MASK)));
}
/*****************************************************************************/
/**
* @brief Update Physical Layer mode.
*
* @param instPtr
* modeCod
*
* @return
*
******************************************************************************/
int32_t Phy_SetMode(PHY_INST *instPtr, PHY_MODE modeCod)
{
ASSERT(instPtr != NULL);
uint32_t phyMainCtrl = PhyRead(instPtr, PHY_MAIN_CTRL) & ~PHY_MAIN_CTRL_MODE_MASK;
switch (modeCod)
{
case PHY_MODE_NONE:
phyMainCtrl |= PHY_MAIN_CTRL_MODE_NONE;
break;
case PHY_MODE_LISTEN:
phyMainCtrl |= PHY_MAIN_CTRL_MODE_LISTEN;
break;
case PHY_MODE_SCHEDULE:
phyMainCtrl |= PHY_MAIN_CTRL_MODE_SCHEDULE;
break;
case PHY_MODE_PULL:
phyMainCtrl |= PHY_MAIN_CTRL_MODE_PULL;
break;
default:
return FAILURE;
break;
}
PhyWrite(instPtr, PHY_MAIN_CTRL, phyMainCtrl | PHY_MAIN_CTRL_EN_EN);
return SUCCESS;
}
/*****************************************************************************/
/**
* @brief Setup next slot operation.
*
* @param instPtr
* txrxMode
* l2FrameType
*
* @return
*
******************************************************************************/
int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
L1_FRAME_TYPE frameType, uint8_t *buff)
{
ASSERT(instPtr != NULL);
int32_t Status = SUCCESS;
uint32_t phyModeCtrl, antConfigBramAddr, hopNum;
uint16_t *hopPattern;
// Implement a ping-pong flow, offset always is 0 or half of buffer depth.
instPtr->antConfigOffset = (instPtr->antConfigOffset == ANTCONFIG_MAX_LEN) ? 0 : ANTCONFIG_MAX_LEN;
antConfigBramAddr = instPtr->antConfigDataPtr + instPtr->antConfigOffset;
instPtr->TOR.next = txrxMode;
instPtr->frameType.next = frameType;
switch (txrxMode)
{
case PHY_TOR_SUSPEND:
phyModeCtrl = PHY_MODE_CTRL_TOR_SUSPEND;
break;
case PHY_TOR_RX:
phyModeCtrl = PHY_MODE_CTRL_TOR_RX;
break;
case PHY_TOR_TX:
phyModeCtrl = PHY_MODE_CTRL_TOR_TX;
break;
default:
return EPARAM;
}
if (instPtr->isPresetHop == false)
{
hopPattern = hopPattern_Config;
}
else
{
switch (frameType)
{
case L1_2KBPS_20MS_FRAME:
phyModeCtrl |= PHY_MODE_CTRL_FRAME_2KBPS_20MS;
hopNum = L1_FRAME_2KBPS_20MS_HOPS;
// FIXME: For DUIFEI net setup.
// hopPattern = (txrxMode == TOR_TX) ? hopPattern_2KBPS_20MS;
hopPattern = hopPattern_2KBPS_100MS;
break;
case L1_2KBPS_100MS_FRAME:
phyModeCtrl |= PHY_MODE_CTRL_FRAME_2KBPS_100MS;
hopNum = L1_FRAME_2KBPS_100MS_HOPS;
hopPattern = hopPattern_2KBPS_100MS;
break;
case L1_10KBPS_10MS_FRAME:
phyModeCtrl |= PHY_MODE_CTRL_FRAME_10KBPS_10MS;
hopNum = L1_FRAME_10KBPS_10MS_HOPS;
hopPattern = hopPattern_10KBPS_10MS;
break;
case L1_10KBPS_20MS_FRAME:
phyModeCtrl |= PHY_MODE_CTRL_FRAME_10KBPS_20MS;
hopNum = L1_FRAME_10KBPS_20MS_HOPS;
hopPattern = hopPattern_10KBPS_20MS;
break;
case L1_40KBPS_20MS_FRAME:
phyModeCtrl |= PHY_MODE_CTRL_FRAME_200KBPS_5MS;
hopNum = L1_FRAME_200KBPS_5MS_HOPS;
hopPattern = hopPattern_200KBPS_5MS;
break;
case L1_40KBPS_10MS_FRAME:
phyModeCtrl |= PHY_MODE_CTRL_FRAME_40KBPS_10MS;
hopNum = L1_FRAME_40KBPS_10MS_HOPS;
hopPattern = hopPattern_40KBPS_10MS;
break;
case L1_200KBPS_5MS_FRAME:
phyModeCtrl |= PHY_MODE_CTRL_FRAME_200KBPS_5MS;
hopNum = L1_FRAME_200KBPS_5MS_HOPS;
hopPattern = hopPattern_200KBPS_5MS;
break;
case L1_1M2BPS_5MS_FRAME:
phyModeCtrl |= PHY_MODE_CTRL_FRAME_1M2BPS_5MS;
hopNum = L1_FRAME_1M2BPS_5MS_HOPS;
hopPattern = hopPattern_1M2BPS_5MS;
break;
default:
return EPARAM;
break;
}
}
PhyWrite(instPtr, PHY_MODE_CTRL, phyModeCtrl);
// TODO: Set antenna stand by, when suspend.
const uint8_t *dataSrcPtr = (uint8_t *)(&(instPtr->antConfigPtr));
for (int32_t i = 0; i < hopNum; i++)
{
instPtr->antConfigPtr.antFreq[1] = (uint8_t)(hopPattern[i] & 0x00FF);
instPtr->antConfigPtr.antFreq[0] = (uint8_t)((hopPattern[i] >> 8) & 0x00FF);
instPtr->antConfigPtr.rfFreq[1] = (uint8_t)(hopPattern[i] & 0x00FF);
instPtr->antConfigPtr.rfFreq[0] = (uint8_t)((hopPattern[i] >> 8) & 0x00FF);
memcpy((uint8_t *)(antConfigBramAddr + i * ANT_COINFO_LENGTH),
dataSrcPtr, sizeof(PHY_ANT_COINFO));
}
uint32_t antCtrl = (instPtr->antConfigOffset & ANT_CONFIG_CMD_OFFSET_MASK) | ((hopNum << ANT_CONFIG_CMD_NUM_SHIFT) & ANT_CONFIG_CMD_NUM_MASK) | ((ANT_COINFO_LENGTH << ANT_CONFIG_CMD_LEN_SHIFT) & ANT_CONFIG_CMD_LEN_MASK);
PhyWrite(instPtr, ANT_CONFIG_CMD, antCtrl);
// FIXME: For DUIFEI network setup. Should only set send data in send slots.
if (txrxMode == PHY_TOR_TX)
{
Status = SetSendData(instPtr, frameType, buff);
if (Status != SUCCESS)
{
return Status;
}
}
// Trigger physical configuration.
PhyWrite(instPtr, SLOT_CONFIG_CMD, SLOT_CONFIG_CMD_VAULE); // Phy start fetching data.
return SUCCESS;
}
/*****************************************************************************/
/**
* @brief Get the corresponding frequency hopping pattern length of a
* specified L1 frame type.
*
* @param frameType a L1 frame type enumeration.
*
* @return SUCCESS
* FAILURE frame type cannot be recognized
*
******************************************************************************/
uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType)
{
switch (frameType)
{
case L1_2KBPS_20MS_FRAME:
return L1_FRAME_2KBPS_20MS_HOPS;
case L1_2KBPS_100MS_FRAME:
return L1_FRAME_2KBPS_100MS_HOPS;
case L1_10KBPS_10MS_FRAME:
return L1_FRAME_10KBPS_10MS_HOPS;
case L1_10KBPS_20MS_FRAME:
return L1_FRAME_10KBPS_20MS_HOPS;
case L1_40KBPS_20MS_FRAME:
return L1_FRAME_40KBPS_20MS_HOPS;
case L1_40KBPS_10MS_FRAME:
return L1_FRAME_40KBPS_10MS_HOPS;
case L1_200KBPS_5MS_FRAME:
return L1_FRAME_200KBPS_5MS_HOPS;
case L1_1M2BPS_5MS_FRAME:
return L1_FRAME_1M2BPS_5MS_HOPS;
default:
return L1_FRAME_NONE_LEN;
}
}
/*****************************************************************************/
/**
* @brief Get the time from frame sync to slot end of different type.
*
* @param frameType
*
* @return 32bit unsigned integer (clock periods)
*
******************************************************************************/
uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType)
{
switch (frameType)
{
case L1_2KBPS_20MS_FRAME:
return L1_FRAME_2KBPS_20MS_COMP;
case L1_2KBPS_100MS_FRAME:
return L1_FRAME_2KBPS_100MS_COMP;
case L1_10KBPS_10MS_FRAME:
return L1_FRAME_10KBPS_10MS_COMP;
case L1_10KBPS_20MS_FRAME:
return L1_FRAME_10KBPS_20MS_COMP;
case L1_40KBPS_20MS_FRAME:
return L1_FRAME_40KBPS_20MS_COMP;
case L1_40KBPS_10MS_FRAME:
return L1_FRAME_40KBPS_10MS_COMP;
case L1_200KBPS_5MS_FRAME:
return L1_FRAME_200KBPS_5MS_COMP;
case L1_1M2BPS_5MS_FRAME:
return L1_FRAME_1M2BPS_5MS_COMP;
default:
return L1_FRAME_NONE_LEN;
}
}
/*****************************************************************************/
/**
* @brief Get latest frequency deviation estimation.
*
* @param instPtr
*
* @return 32bit signed integer (Hz)
*
******************************************************************************/
int32_t Phy_GetFreqEst(PHY_INST *instPtr)
{
uint32_t temp;
int32_t acqCh, fsCh;
double freqEst;
temp = PhyRead(instPtr, COASE_FREQEST);
acqCh = temp & 0x000000FF;
acqCh = 80 - acqCh;
fsCh = (temp >> 8) & 0x000000FF;
fsCh = fsCh - 128;
freqEst = acqCh * (31.25e3 / 4) + fsCh * (31.25e3 / 256);
return ((int32_t)freqEst);
}
/*****************************************************************************/
/**
* @brief Setup a frequency hopping pattern.
*
* @param patternBuff a pointer to hopping pattern buffer
* @param patternLen a integer indicate the length of hopping pattern.
*
* @return SUCCESS
* FAILURE pattern length exceeds maximum length.
*
******************************************************************************/
int32_t Phy_SetHopPattern(void *patternBuff, uint32_t patternLen)
{
ASSERT(patternBuff != NULL);
if (patternLen > L1_FRAME_MAX_HOPS)
{
return FAILURE;
}
memcpy(hopPattern_Config, patternBuff, patternLen * sizeof(uint16_t));
return SUCCESS;
}
/*****************************************************************************/
/**
* @brief Setup a specific timer word register in physical controller.
*
* @param instPtr
* @param tmWord
* @param tmType
*
* @return SUCCESS
* FAILURE pattern length exceeds maximum length.
*
******************************************************************************/
int32_t Phy_SetTimeWord(PHY_INST *instPtr, uint64_t tmWord, PHY_TIME_WORD_TYPE tmType)
{
ASSERT(instPtr != NULL);
switch (tmType)
{
case PHY_TIME_WORD_POLL:
PhyWrite(instPtr, POLLTIME_L, (uint32_t)tmWord);
PhyWrite(instPtr, POLLTIME_H, (uint32_t)(tmWord >> 32));
break;
case PHY_TIME_WORD_LOCAL_ADJ:
PhyWrite(instPtr, LOCALTM_ADJ_L, (uint32_t)tmWord);
PhyWrite(instPtr, LOCALTM_ADJ_H, (uint32_t)(tmWord >> 32));
break;
case PHY_TIME_WORD_STEP:
PhyWrite(instPtr, CNT_STEP_OPT, (uint32_t)tmWord);
break;
default:
return EPARAM;
}
return SUCCESS;
}
/*****************************************************************************/
/**
* @brief Setup a specific timer word register in physical controller.
*
* @param instPtr a pointer to hopping pattern buffer
* @param patternLen a integer indicate the length of hopping pattern.
*
* @return SUCCESS
* FAILURE pattern length exceeds maximum length.
*
******************************************************************************/
void Phy_UpdateHwSate(PHY_INST *instPtr)
{
ASSERT(instPtr != NULL);
uint32_t rawData;
// -- Update Chip voltage, unit mV
rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPINT);
instPtr->hwSate.spVolt = (uint16_t)(XAdcPs_RawToVoltage(rawData) * 1000);
// -- Update Chip temperature, unit 0.01 deg
rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_TEMP);
instPtr->hwSate.spTemp = (uint16_t)(XAdcPs_RawToTemperature(rawData) * 100);
// FIXME: Chip status determine.
instPtr->hwSate.chipSt = 0;
/*** Voltage and Status ***/
rawData = PhyRead(instPtr, ANT_STATUS);
// -- Update Antenna Status Code: 0xAA - normal, 0x55 - error
instPtr->hwSate.antSt = ((rawData & ANT_STATUS_CODE_MASK) == 0) ? 0xAA : 0x55;
// -- Update Antenna Voltage Status: 1 - normal, 0 - error
// [0] - ANT voltage status
// [2] - RF voltage status
// [4] - NIL voltage status
instPtr->hwSate.antVolt = (rawData & ANT_STATUS_ANT_VOLT_MASK) ? 0x01 : 0x00;
instPtr->hwSate.antVolt |= (rawData & ANT_STATUS_RF_VOLT_MASK) ? 0x04 : 0x00;
instPtr->hwSate.antVolt |= (rawData & ANT_STATUS_NIL_VOLT_MASK) ? 0x10 : 0x00;
/*** Temperature and Lock Status ***/
rawData = PhyRead(instPtr, RF_STATUS);
//-- Update Antenna Temperature (signed 8bit integer, 1 centigrade per LSB)
instPtr->hwSate.antTemp = (uint8_t)(rawData & RF_STATUS_TEMP_MASK);
// -- Update Antenna PLL Lock Status: 1 - normal, 0 - error
// [0] - BASEBAND lock status
// [2] - PLLA lock status
// [4] - PLLB lock status
instPtr->hwSate.antPll = (rawData & RF_STATUS_BDLOCK_MASK) ? 0x01 : 0x00;
instPtr->hwSate.antPll |= (rawData & RF_STATUS_PLLA_MASK) ? 0x04 : 0x00;
instPtr->hwSate.antPll |= (rawData & RF_STATUS_PLLB_MASK) ? 0x10 : 0x00;
/*** MGCs ***/
rawData = PhyRead(instPtr, RF_MGC);
// -- Update Antenna MGC (0~15 dB)
// [3:0] - Channel 1 MGC
// [7:4] - Channel 2 MGC
// [11:8] - Channel 3 MGC
// [15:12] - Channel 4 MGC
instPtr->hwSate.antMgc = (rawData & RF_MGC_CH1_MASK);
instPtr->hwSate.antMgc |= (rawData & RF_MGC_CH2_MASK) >> 4;
instPtr->hwSate.antMgc |= (rawData & RF_MGC_CH3_MASK) >> 8;
instPtr->hwSate.antMgc |= (rawData & RF_MGC_CH4_MASK) >> 12;
SysMonitor_UpdateHardwareStatus(&(instPtr->hwSate));
}
df_datalink_sp/src/networking/phy_layer/phy_layer.h
+249
View File
@@ -0,0 +1,249 @@
/*****************************************************************************/
/**
* Description: Physical layer control definitions and function prototypes.
*
* Date: 2021-12-04 16:32
* LastEditTime: 2023-04-24 17:41
* Revisions: Rev 0.1
* History:
* [2021-12-08]: Initial version.
* [2022-06-18]: New branch for glink control purpose:
* -Add poll mode, physical layer will start Tx/Rx procedure
* at specific time stamp.
* -Add 61/37 beam switch
* -Code simplification.
* [2023-04-24]: Porting for DUIFEI.
*
* Copyright(c) 2021 Beijing Institute of Technology.
* Lab of Communication and Networking
*
******************************************************************************/
#ifndef PHY_CTRL_H_
#define PHY_CTRL_H_
/***************************** Include Files *********************************/
#include <stdint.h>
#include "common.h"
#include "xbram.h"
#include "xadcps.h"
#include "phy_reg.h"
#include "../../system_monitor.h"
/************************** Constant Definitions *****************************/
#define L1_FRAME_NONE_HOPS UINT32_MAX
#define L1_FRAME_MAX_HOPS 81
#define L1_FRAME_2KBPS_20MS_HOPS 1
#define L1_FRAME_2KBPS_100MS_HOPS 81
#define L1_FRAME_10KBPS_10MS_HOPS 1
#define L1_FRAME_10KBPS_20MS_HOPS 11
#define L1_FRAME_40KBPS_20MS_HOPS 19
#define L1_FRAME_40KBPS_10MS_HOPS 9
#define L1_FRAME_200KBPS_5MS_HOPS 20
#define L1_FRAME_1M2BPS_5MS_HOPS 20
#define L1_NUM_ANT_SUBNRRW_PATTERN 37
#define L1_NUM_ANT_NRRW_PATTERN 61
#define ANT_COINFO_LENGTH 32 // bytes
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
typedef enum
{
L1_NONE_FRAME = 0,
L1_2KBPS_20MS_FRAME = 1,
L1_2KBPS_100MS_FRAME = 2,
L1_10KBPS_10MS_FRAME = 3,
L1_10KBPS_20MS_FRAME = 4,
L1_40KBPS_20MS_FRAME = 5,
L1_40KBPS_10MS_FRAME = 6,
L1_200KBPS_5MS_FRAME = 7,
L1_1M2BPS_5MS_FRAME = 8
} L1_FRAME_TYPE;
typedef struct
{
/*** Ant Control ***/
/* Antenna control frame head 0xAA */
/* default 0, reserved for further use */
uint8_t ctrlWord;
/* high 4 bits specified beam mode.
* low 4 bits specified power control */
uint8_t antMode;
/* off-axis angle range is 0~60,
* 0.1 degree each LSB */
uint8_t oaxis[2];
/* round-axis angle range is 0~360,
* 0.1 degree each LSB */
uint8_t raxis[2];
/* 0~3500Mhz, step 1MHz */
uint8_t antFreq[2];
/* in single tr mode, 0~63 specified tr channel
* in single subarray mode, 0~3 specified the subarray
* Only in debug mode*/
uint8_t trSlect;
/* Antenna attenuation 0~31, 0.5dB each LSB, Only in debug mode */
uint8_t antAtt;
/* 0~63, 5.625 degree each LSB, Only in debug mode*/
uint8_t phase;
/* Only for debug */
/* default 0x00 */
uint8_t rxtxMode;
/* 0x00 Normal, 0x01 single tr calibration */
uint8_t calibrMode;
/* reserved for further use */
uint8_t antReserved;
/*** RF Control ***/
/* [7:4]RF enable: 0-On, 1-Off(Default); [3:0]Work mode: 0(default) */
uint8_t rfCtrl;
/* 0~3500Mhz, step 1MHz */
uint8_t rfFreq[2];
/* RF MGC control: 0~31, 1dB each LSB*/
uint8_t rfTxMgc;
/* RF channel 1&2 calibration mgc: [7:4] Channle1 - max 15db, 1dB each LSB
* [3:0] Channle2 - max 15db, 1dB each LSB*/
uint8_t rf12CalMgc;
/* RF channel 3&4 calibration mgc: [7:4] Channle3 - max 15db, 1dB each LSB
* [3:0] Channle4 - max 15db, 1dB each LSB*/
uint8_t rf34CalMgc;
/* Receive channel 1-4 MGC: 0~31, 1dB each LSB */
uint8_t rcvMgc;
/* Receive monitor, 0-normal, 1-switch to monitor port */
uint8_t rfMonitor;
/* reserved for further use */
uint8_t rfReserved0;
uint8_t rfReserved1;
} PHY_ANT_COINFO;
typedef struct
{
/* off-axis angle range is 0~60,
* 0.1 degree each LSB */
uint16_t oaxis;
/* round-axis angle range is 0~360,
* 0.1 degree each LSB */
uint16_t raxis;
} PHY_ANT_ANGLE;
typedef enum
{
PHY_TIME_WORD_NONE = 0,
PHY_TIME_WORD_POLL = 1,
PHY_TIME_WORD_LISTEN_TIMEOUT = 2,
PHY_TIME_WORD_LOCAL_ADJ = 3,
PHY_TIME_WORD_STEP = 4,
} PHY_TIME_WORD_TYPE;
typedef enum
{
PHY_ANT_BEAM_NONE = 0,
PHY_ANT_BEAM_120 = 1,
PHY_ANT_BEAM_60 = 2,
PHY_ANT_BEAM_25 = 3,
PHY_ANT_BEAM_8 = 4
} PHY_ANT_BEAM_WIDTH;
typedef enum
{
PHY_TOR_SUSPEND = 0,
PHY_TOR_TX = 1,
PHY_TOR_RX = 2
} PHY_TOR_TYPE;
typedef enum
{
PHY_MODE_NONE = 0,
PHY_MODE_LISTEN = 1,
PHY_MODE_SCHEDULE = 2,
PHY_MODE_PULL = 3
} PHY_MODE;
typedef struct
{
uint32_t devId;
uint32_t txBramId;
uint32_t rxBramId;
uint32_t antBramId;
uint32_t hwXadcId;
uint32_t baseAddr;
} PHY_CONFIG;
typedef struct
{
int32_t last;
int32_t curr;
int32_t next;
} PHY_RCD;
typedef struct
{
PHY_CONFIG phyCofig; // Device address configs
bool isPhyEn; // if physical layer running
bool isAcq; // if last reception acquisition success
bool isFrameSync; // if last reception frame sync success
bool isDecode; // if last reception decode success
bool isValid; // if last reception frame data valid (crc check pass)
bool isPresetHop; // if using preset frequency hop
PHY_RCD antNo; // antenna number record
PHY_RCD beamNo; // beam number record
PHY_RCD beamWd; // beam width record
PHY_RCD TOR; // tx rx state record
PHY_RCD frameType; // frame type record
uint32_t antConfigOffset; // antenna configuration bram offset (to implement ping-pong data flow)
uint32_t sendOffset; // antenna configuration bram offset (to implement ping-pong data flow)
PHY_ANT_COINFO antConfigPtr; // antenna configuration pointer
uintptr_t txDataPtr;
uintptr_t rxDataPtr;
uintptr_t antConfigDataPtr;
XAdcPs hwXadc;
HWSTATE hwSate;
} PHY_INST;
/************************** Variable Definitions *****************************/
extern uint16_t hopPattern_Config[L1_FRAME_MAX_HOPS];
extern uint16_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS];
extern uint16_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS];
extern uint16_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS];
extern uint16_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS];
extern uint16_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS];
extern uint16_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS];
extern uint16_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS];
extern uint16_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS];
extern PHY_ANT_ANGLE antSubnrrwPattern[L1_NUM_ANT_SUBNRRW_PATTERN];
extern PHY_ANT_ANGLE antNrrwPattern[L1_NUM_ANT_NRRW_PATTERN];
/************************** Function Prototypes ******************************/
int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig);
void Phy_UpdateState(PHY_INST *instPtr);
void Phy_UpdateHwSate(PHY_INST *instPtr);
void Phy_Start(PHY_INST *instPtr);
void Phy_Halt(PHY_INST *instPtr);
int32_t Phy_SetMode(PHY_INST *instPtr, PHY_MODE modeCod);
int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode, L1_FRAME_TYPE frameType, uint8_t *buff);
int32_t Phy_RetrieveRecvData(PHY_INST *instPtr, uint8_t *buff);
bool Phy_IsFrameDetected(PHY_INST *instPtr);
bool Phy_IsFrameReceived(PHY_INST *instPtr);
bool Phy_IsFrameValid(PHY_INST *instPtr);
uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType);
L1_FRAME_TYPE Phy_GetLastDetectedFrameType(PHY_INST *instPtr);
L1_FRAME_TYPE Phy_GetLastReceivedFrameType(PHY_INST *instPtr);
L1_FRAME_TYPE Phy_GetLastSentFrameType(PHY_INST *instPtr);
int32_t Phy_SetHopPattern(void *patternBuff, uint32_t patternLen);
uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType);
uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType);
int32_t Phy_GetFreqEst(PHY_INST *instPtr);
int32_t Phy_SetTimeWord(PHY_INST *instPtr, uint64_t tmWord, PHY_TIME_WORD_TYPE tmType);
int32_t Phy_AntConfigInit(PHY_ANT_COINFO *antCoinfoPtr);
int32_t Phy_SetBeamWidth(PHY_INST *instPtr, PHY_ANT_BEAM_WIDTH beamWidth);
int32_t Phy_SetBeamNo(PHY_INST *instPtr, int32_t beamNo);
int32_t Phy_SetBeamAngle(PHY_INST *phyInstPtr, double offAx, double rndAx);
#endif /* PHY_CTRL_H_ */
df_datalink_sp/src/networking/phy_layer/phy_reg.h
+334
View File
@@ -0,0 +1,334 @@
/*****************************************************************************/
/**
* Description: Physical layer register definitions
*
* Author: Fan Hao
* Date: 2021-11-16 00:08
* LastEditors: Fan Hao
* LastEditTime: 2023-04-24 17:32
* Revisions: Rev 0.1
* History:
* [2021-11-16]: Initial version.
* [2022-06-18]: New branch for glink control purpose:
* -Add poll modephysical layer will start Tx/Rx procedure
* at specific time stamp.
* [2023-04-24]: Porting for DUIFEI.
*
* Copyright(c) 2021 Beijing Institute of Technology.
* Lab of Communication and Networking
*
******************************************************************************/
#ifndef PHY_CTRLREG_H_
#define PHY_CTRLREG_H_
/***************************** Include Files *********************************/
#include "util.h"
/***************** Macros (Inline Functions) Definitions *********************/
// Read Physical Layer register (0x00000000~0x000000FF)
#define PhyRead(instPtr, addr) IO_In32(instPtr->phyCofig.baseAddr + addr)
// Write Physical Layer register (0x000000100~0x00000200)
#define PhyWrite(instPtr, addr, value) IO_Out32(instPtr->phyCofig.baseAddr + addr, value)
/************************** Constant Definitions *****************************/
/************************* Ps2Pl Regs PS Write Only ***************************/
/**
* Register: PHY_MAIN_CTRL
*/
#define PHY_MAIN_CTRL 0X00000000U
#define PHY_MAIN_CTRL_EN_SHIFT 0
#define PHY_MAIN_CTRL_EN_WIDTH 1
#define PHY_MAIN_CTRL_EN_MASK 0x00000001U
#define PHY_MAIN_CTRL_MODE_SHIFT 8
#define PHY_MAIN_CTRL_MODE_WIDTH 8
#define PHY_MAIN_CTRL_MODE_MASK 0x0000FF00U
#define PHY_MAIN_CTRL_EN_EN 0x00000001U
#define PHY_MAIN_CTRL_EN_DSBL 0x00000000U
#define PHY_MAIN_CTRL_MODE_NONE 0x00000000U
#define PHY_MAIN_CTRL_MODE_LISTEN 0x00000100U
#define PHY_MAIN_CTRL_MODE_SCHEDULE 0x00000200U
#define PHY_MAIN_CTRL_MODE_PULL 0x00000300U
/**
* Register: TXRX_CTRL
*/
#define PHY_MODE_CTRL 0x00000004U
#define PHY_MODE_CTRL_TOR_SHIFT 0
#define PHY_MODE_CTRL_TOR_WIDTH 2
#define PHY_MODE_CTRL_TOR_MASK 0x00000003U
#define PHY_MODE_CTRL_FRAME_SHIFT 16
#define PHY_MODE_CTRL_FRAME_WIDTH 8
#define PHY_MODE_CTRL_FRAME_MASK 0x00FF0000U
#define PHY_MODE_CTRL_TOR_SUSPEND 0x00000000U
#define PHY_MODE_CTRL_TOR_TX 0x00000001U
#define PHY_MODE_CTRL_TOR_RX 0x00000002U
#define PHY_MODE_CTRL_FRAME_NONE 0x00000000U
#define PHY_MODE_CTRL_FRAME_2KBPS_20MS 0x00000100U
#define PHY_MODE_CTRL_FRAME_2KBPS_100MS 0x00000200U
#define PHY_MODE_CTRL_FRAME_10KBPS_10MS 0x00000300U // Initial Scan Frame
#define PHY_MODE_CTRL_FRAME_10KBPS_20MS 0x00000400U // Benchmark Frame
#define PHY_MODE_CTRL_FRAME_40KBPS_20MS 0x00000500U
#define PHY_MODE_CTRL_FRAME_40KBPS_10MS 0x00000600U
#define PHY_MODE_CTRL_FRAME_200KBPS_5MS 0x00000700U // 2-Way ACQ Frame, Management Frame, Service Frame
#define PHY_MODE_CTRL_FRAME_1M2BPS_5MS 0x00000800U // Bistatic Synthetic Aperture Radar Frame
/**
* Register: POLLTIME_L
*/
#define POLLTIME_L 0x00000008U
#define POLLTIME_L_SHIFT 0
#define POLLTIME_L_WIDTH 32
#define POLLTIME_L_MASK 0xFFFFFFFFU
/**
* Register: POLLTIME_H
*/
#define POLLTIME_H 0x0000000CU
#define POLLTIME_H_SHIFT 0
#define POLLTIME_H_WIDTH 32
#define POLLTIME_H_MASK 0xFFFFFFFFU
/**
* Register: TM_ADJ_MODE
*/
#define TM_ADJ_MODE 0x00000010U
#define TM_ADJ_MODE_SHIFT 0
#define TM_ADJ_MODE_WIDTH 8
#define TM_ADJ_MODE_MASK 0x000000FFU
#define TM_ADJ_MODE_NONE 0x00000000U
#define TM_ADJ_MODE_ADD 0x00000001U
#define TM_ADJ_MODE_SET 0x00000002U
#define TM_ADJ_MODE_LOCAL_SHIFT 8
#define TM_ADJ_MODE_LOCAL_WIDTH 8
#define TM_ADJ_MODE_LOCAL_MASK 0x0000FF00U
#define TM_ADJ_MODE_LOCAL_NONE 0x00000000U
#define TM_ADJ_MODE_LOCAL_ADD 0x00000100U
#define TM_ADJ_MODE_LOCAL_SET 0x00000200U
/**
* Register: LOCALTM_ADJ_L
*/
#define LOCALTM_ADJ_L 0x00000014U
#define LOCALTM_ADJ_L_SHIFT 0
#define LOCALTM_ADJ_L_WIDTH 32
#define LOCALTM_ADJ_L_MASK 0xFFFFFFFFU
/**
* Register: LOCALTM_ADJ_H
*/
#define LOCALTM_ADJ_H 0x00000018U
#define LOCALTM_ADJ_H_SHIFT 0
#define LOCALTM_ADJ_H_WIDTH 32
#define LOCALTM_ADJ_H_MASK 0xFFFFFFFFU
/**
* Register: CNT_STEP_TOPT
*/
#define CNT_STEP_OPT 0x0000001CU
#define CNT_STEP_OPT_SHIFT 0
#define CNT_STEP_OPT_WIDTH 32
#define CNT_STEP_OPT_MASK 0xFFFFFFFFU
/**
* Register: SEND_DATA_CMD
*/
#define SEND_DATA_CMD 0x00000020U
#define SEND_DATA_CMD_LEN_SHIFT 0
#define SEND_DATA_CMD_LEN_WIDTH 16
#define SEND_DATA_CMD_LEN_MASK 0x0000FFFFU
#define SEND_DATA_CMD_OFFSET_SHIFT 16
#define SEND_DATA_CMD_OFFSET_WIDTH 16
#define SEND_DATA_CMD_OFFSET_MASK 0xFFFF0000U
/**
* Register: ANT_CONFIG_CMD
*/
#define ANT_CONFIG_CMD 0x00000024U
#define ANT_CONFIG_CMD_OFFSET_SHIFT 0
#define ANT_CONFIG_CMD_OFFSET_WIDTH 16
#define ANT_CONFIG_CMD_OFFSET_MASK 0x0000FFFFU
#define ANT_CONFIG_CMD_LEN_SHIFT 16
#define ANT_CONFIG_CMD_LEN_WIDTH 8
#define ANT_CONFIG_CMD_LEN_MASK 0x00FF0000U
#define ANT_CONFIG_CMD_NUM_SHIFT 24
#define ANT_CONFIG_CMD_NUM_WIDTH 8
#define ANT_CONFIG_CMD_NUM_MASK 0xFF000000U
/**
* Register: SLOT_CONFIG_CMD
*/
#define SLOT_CONFIG_CMD 0x00000028U
#define SLOT_CONFIG_CMD_SHIFT 0
#define SLOT_CONFIG_CMD_WIDTH 32
#define SLOT_CONFIG_CMD_MASK 0xFFFFFFFFU
#define SLOT_CONFIG_CMD_VAULE 0x4846414E
/************************* Ps2Pl Regs PS Read Only ***************************/
/**
* Register: TXRX_STATE
*/
#define TXRX_STATE 0x00000100U
#define TXRX_STATE_ACQ_SHIFT 0
#define TXRX_STATE_ACQ_WIDTH 8
#define TXRX_STATE_ACQ_MASK 0x000000FFU
#define TXRX_STATE_ACQ_SUCCESS 0x00000001U
#define TXRX_STATE_ACQ_FAIL 0x00000002U
#define TXRX_STATE_FSYNC_SHIFT 8
#define TXRX_STATE_FSYNC_WIDTH 8
#define TXRX_STATE_FSYNC_MASK 0x0000FF00U
#define TXRX_STATE_FSYNC_SUCCESS 0x00000100U
#define TXRX_STATE_FSYNC_FAIL 0x00000200U
#define TXRX_STATE_DECODE_SHIFT 16
#define TXRX_STATE_DECODE_WIDTH 8
#define TXRX_STATE_DECODE_MASK 0x00FF0000U
#define TXRX_STATE_DECODE_SUCCESS 0x00010000U
#define TXRX_STATE_DECODE_FAIL 0x00020000U
/**
* Register: RECV_SATE
*/
#define RECV_DATA_SATE 0x00000104U
#define RECV_DATA_LEN_SHIFT 0
#define RECV_DATA_LEN_WIDTH 16
#define RECV_DATA_LEN_MASK 0x0000FFFFU
#define RECV_DATA_OFFSET_SHIFT 16
#define RECV_DATA_OFFSET_WIDTH 16
#define RECV_DATA_OFFSET_MASK 0xFFFFF0000U
/**
* Register: FSTIME_L
*/
#define FSTIME_L 0x00000108U
#define FSTIME_L_SHIFT 0
#define FSTIME_L_WIDTH 32
#define FSTIME_L_MASK 0xFFFFFFFFU
/**
* Register: FSTIME_INT1
*/
#define FSTIME_H 0x0000010CU
#define FSTIME_H_SHIFT 0
#define FSTIME_H_WIDTH 32
#define FSTIME_H_MASK 0xFFFFFFFFU
/**
* Register: TM_TARGET_L
*/
#define TM_TARGET_L 0x00000110U
#define TM_TARGET_L_SHIFT 0
#define TM_TARGET_L_WIDTH 32
#define TM_TARGET_L_MASK 0xFFFFFFFFU
/**
* Register: TM_TARGET_H
*/
#define TM_TARGET_H 0x00000114U
#define TM_TARGET_H_SHIFT 0
#define TM_TARGET_H_WIDTH 32
#define TM_TARGET_H_MASK 0xFFFFFFFFU
/**
* Register: LOCALTM_L
*/
#define TM_LOCAL_L 0x00000118U
#define TM_LOCAL_L_SHIFT 0
#define TM_LOCAL_L_WIDTH 32
#define TM_LOCAL_L_MASK 0xFFFFFFFFU
/**
* Register: LOCALTM_H
*/
#define TM_LOCAL_H 0x0000011CU
#define TM_LOCAL_H_SHIFT 0
#define TM_LOCAL_H_WIDTH 32
#define TM_LOCAL_H_MASK 0xFFFFFFFFU
/**
* Register: COASEFREQEST
*/
#define COASE_FREQEST 0x00000120U
#define COASE_FREQEST_SHIFT 0
#define COASE_FREQEST_WIDTH 32
#define COASE_FREQEST_MASK 0xFFFFFFFFU
/**
* Register: INTR_TYPE
*/
#define INTR_TYPE 0x00000124U
/**
* Register: ANT_STATUS_0
*/
#define ANT_STATUS 0x00000128U
#define ANT_STATUS_CODE_SHIFT 0
#define ANT_STATUS_CODE_WIDTH 8
#define ANT_STATUS_CODE_MASK 0x000000FFU
#define ANT_STATUS_NIL_VOLT_SHIFT 8
#define ANT_STATUS_NIL_VOLT_WIDTH 8
#define ANT_STATUS_NIL_VOLT_MASK 0x0000FF00U
#define ANT_STATUS_RF_VOLT_SHIFT 16
#define ANT_STATUS_RF_VOLT_WIDTH 8
#define ANT_STATUS_RF_VOLT_MASK 0x00FF0000U
#define ANT_STATUS_ANT_VOLT_SHIFT 24
#define ANT_STATUS_ANT_VOLT_WIDTH 8
#define ANT_STATUS_ANT_VOLT_MASK 0xFF000000U
/**
* Register: ANT_FRAME_CNT
*/
#define ANT_FRAME_CNT 0x0000012CU
#define ANT_FRAME_CNT_SHIFT 0
#define ANT_FRAME_CNT_WIDTH 32
#define ANT_FRAME_CNT_MASK 0xFFFFFFFFU
/**
* Register: RF_STATUS
*/
#define RF_STATUS 0x00000130U
#define RF_STATUS_TEMP_SHIFT 0
#define RF_STATUS_TEMP_WIDTH 8
#define RF_STATUS_TEMP_MASK 0x000000FFU
#define RF_STATUS_BDLOCK_SHIFT 8
#define RF_STATUS_BDLOCK_WIDTH 8
#define RF_STATUS_BDLOCK_MASK 0x0000FF00U
#define RF_STATUS_PLLA_SHIFT 16
#define RF_STATUS_PLLA_WIDTH 8
#define RF_STATUS_PLLA_MASK 0x00FF0000U
#define RF_STATUS_PLLB_SHIFT 24
#define RF_STATUS_PLLB_WIDTH 8
#define RF_STATUS_PLLB_MASK 0xFF000000U
/**
* Register: RF_MGC
*/
#define RF_MGC 0x00000134U
#define RF_MGC_CH1_SHIFT 0
#define RF_MGC_CH1_WIDTH 4
#define RF_MGC_CH1_MASK 0x0000000FU
#define RF_MGC_CH2_SHIFT 8
#define RF_MGC_CH2_WIDTH 4
#define RF_MGC_CH2_MASK 0x00000F00U
#define RF_MGC_CH3_SHIFT 16
#define RF_MGC_CH3_WIDTH 4
#define RF_MGC_CH3_MASK 0x000F0000U
#define RF_MGC_CH4_SHIFT 24
#define RF_MGC_CH4_WIDTH 4
#define RF_MGC_CH4_MASK 0x0F000000U
/**
* Register: RF_FRAME_CNT
*/
#define RF_FRAME_CNT 0x00000138U
#define RF_FRAME_CNT_SHIFT 0
#define RF_FRAME_CNT_WIDTH 32
#define RF_FRAME_CNT_MASK 0xFFFFFFFFU
#endif /* PHY_CTRLREG_H_ */