fix: 修改时隙表编号,配置时隙表时同时修改初始建网时隙表;修改自检回令

src/systembus/systembus.c

@@ -345,24 +345,30 @@ static int32_t SystemBus_SystemConfig(SYSBUS *instPtr, uint8_t *msg)
 	{
 		switch (msg[WD_RTNE_CMD])
 		{
-		case 0:
-		{
-			reconfig |= (linkConfig.normalTable != normalRoutTable0);
-			linkConfig.normalTable = normalRoutTable0;
-			break;
-		}
 		case 1:
 		{
+			reconfig |= (linkConfig.initTable != normalRoutTable1);
 			reconfig |= (linkConfig.normalTable != normalRoutTable1);
+			linkConfig.initTable = normalRoutTable1;
 			linkConfig.normalTable = normalRoutTable1;
 			break;
 		}
 		case 2:
 		{
+			reconfig |= (linkConfig.initTable != normalRoutTable2);
 			reconfig |= (linkConfig.normalTable != normalRoutTable2);
+			linkConfig.initTable = normalRoutTable2;
 			linkConfig.normalTable = normalRoutTable2;
 			break;
 		}
+		case 3:
+		{
+			reconfig |= (linkConfig.initTable != normalRoutTable3);
+			reconfig |= (linkConfig.normalTable != normalRoutTable3);
+			linkConfig.initTable = normalRoutTable3;
+			linkConfig.normalTable = normalRoutTable3;
+			break;
+		}
 		default:
 		{
 			// Ignore current command

src/systembus/systembus.h

@@ -61,6 +61,15 @@
 #define VOLT_ANT_NIL_OK BIT(4)
 #define ANT_STATE_OK BIT(6)
 
+#ifdef HSJL_GE
+// Xilinx Recommended
+ #define IS_PS_VALID(x) (x <= 0.892 && x >= 0.808)
+ #define IS_PSAUX_VALID(x) (x <= 1.89 && x >= 1.71)
+ #define IS_DDR_VALID(x) (x <= 1.89 && x >= 1.14)
+ #define IS_PL_VALID(x) (x <= 0.892 && x >= 0.808)
+ #define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71)
+ #define IS_BRAM_VALID(x) (x <= 0.892 && x >= 0.808)
+#else
 // Xilinx Recommended
 // #define IS_PS_VALID(x) (x <= 1.05 && x >= 0.95)
 // #define IS_PSAUX_VALID(x) (x <= 1.89 && x >= 1.71)
@@ -74,6 +83,7 @@
 #define IS_PL_VALID(x) (x <= 1.1 && (x) >= 0.9)
 #define IS_PLAUX_VALID(x) ((x) <= 2.0 && (x) >= 1.6)
 #define IS_BRAM_VALID(x) ((x) <= 1.1 && (x) >= 0.9)
+#endif
 
 #define CLK_SP_PLL1_LOCK BIT(0)
 #define CLK_SP_PLL2_LOCK BIT(2)