mitigate: 整个地检和节点工程, 增加自动编译
更新了AD9361的profile
This commit is contained in:
@@ -0,0 +1,427 @@
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/*****************************************************************************/
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/**
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* @file phy_antenna.h
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* @author FanHao ([email protected])
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* @brief Physical layer control antenna configuration functions.
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* @version 0.0
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* @date 2023-04-24
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*
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* @copyright Copyright(c) 2024 Beijing Institute of Technology.\n
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* Lab of Communication and Network
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*
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******************************************************************************/
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/**
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* @addtogroup PhysicalLayer
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* @{
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*/
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/**
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* @addtogroup PhysicalLayer_AntennaControl
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* @{
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*/
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#include <string.h>
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#include <stdint.h>
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#include <math.h>
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#include "error.h"
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#include "phy_layer.h"
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/**
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* @name PhysicalLayer_AntennaConfig_Constants
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* @{
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*/
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#define ANT_PI 3.14159265358979323846
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#define ANT_COINFO_HEAD 0xAA
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#define ANT_COINFO_TAIL 0xCC
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#define CTRL_WORD_DEFAULT 0x00
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#define ANT_ENABLE 0x01
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#define ANT_DISABLE 0x00
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#define ANT_MODE_RX_NORMAL 0x00
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#define ANT_MODE_RX_AJ 0x01
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#define DEFAULT_CENTRTAL_FREQ 300U // 4 GHz
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// Pair by regex
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// Regex: (([0-9]+, ){8})
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const uint16_t freqTable[L1_FRAME_MAX_HOPS] =
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{
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0U, 7U, 15U, 22U, 30U, 37U, 45U, 52U,
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60U, 67U, 75U, 82U, 90U, 97U, 105U, 112U,
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120U, 127U, 135U, 142U, 150U, 157U, 165U, 172U,
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180U, 187U, 195U, 202U, 210U, 217U, 225U, 232U,
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240U, 247U, 255U, 262U, 270U, 277U, 285U, 292U,
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300U, 307U, 315U, 322U, 330U, 337U, 345U, 352U,
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360U, 367U, 375U, 382U, 390U, 397U, 405U, 412U,
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420U, 427U, 435U, 442U, 450U, 457U, 465U, 472U,
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480U, 487U, 495U, 502U, 510U, 517U, 525U, 532U,
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540U, 547U, 555U, 562U, 570U, 577U, 585U, 592U,
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600U,
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};
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const uint8_t antCalTable[L1_ANT_NUM][L1_FRAME_MAX_HOPS][L1_ANT_CH_NUM] =
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//Antenna-JG01
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{
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// Antenna-1
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{
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{ 0, 2525, -7533, -6846}, { 0, 12726, -7818, -6860},
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{ 0, 2490, -7836, -6907}, { 0, 4479, -7716, -6837},
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{ 0, 6409, -7770, -6776}, { 0, 14616, -7977, -6816},
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{ 0, -22557, -8002, -6911}, { 0, -22587, -8121, -6918},
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{ 0, -1124, -8123, -7030}, { 0, -152, -8219, -7042},
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{ 0, 1823, -8209, -7130}, { 0, 1790, -8290, -7214},
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{ 0, 1669, -8362, -7283}, { 0, 1634, -8459, -7276},
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{ 0, 1615, -8315, -7415}, { 0, 1698, -8168, -7366},
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{ 0, 1535, -8285, -7520}, { 0, 1619, -8285, -7532},
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{ 0, 1609, -8201, -7693}, { 0, 1671, -8145, -7769},
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{ 0, 1676, -8135, -7805}, { 0, 951, -10279, -8871},
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{ 0, 976, -10235, -8978}, { 0, 1118, -10127, -9019},
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{ 0, 1175, -10003, -9007}, { 0, 1386, -9847, -9039},
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{ 0, 1535, -9572, -9058}, { 0, 1729, -9493, -9006},
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{ 0, -1158, -9312, -9003}, { 0, 23771, -9147, -8928},
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{ 0, 20733, -9074, -8924}, { 0, 2455, -8841, -8886},
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{ 0, 2622, -8718, -8735}, { 0, 2791, -8615, -8705},
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{ 0, 2861, -8168, -8331}, { 0, 3076, -8091, -8218},
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{ 0, 3257, -8046, -8100}, { 0, 3331, -7923, -8073},
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{ 0, 3396, -7826, -7994}, { 0, 3478, -7842, -8016},
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{ 0, 3518, -7846, -7765}, { 0, 3585, -7753, -7715},
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{ 0, 150, -8145, -8591}, { 0, 192, -8090, -8570},
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{ 0, 207, -8150, -8597}, { 0, 178, -8142, -8656},
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{ 0, 89, -8557, -8688}, { 0, 107, -8614, -8733},
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{ 0, 194, -8605, -8782}, { 0, 153, -8655, -8881},
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{ 0, 70, -8615, -8952}, { 0, 35, -8596, -9148},
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{ 0, 49, -8636, -9286}, { 0, 6, -8587, -9435},
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{ 0, -51, -8540, -9549}, { 0, -65, -8588, -9700},
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{ 0, -55, -8503, -9820}, { 0, -20, -8414, -9907},
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{ 0, -112, -8481, -10031}, { 0, -69, -8535, -10185},
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{ 0, 2, -8550, -10052}, { 0, -1, -8493, -10291},
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{ 0, -73, -8441, -10380}, { 0, 1958, -6930, -8295},
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{ 0, -1148, -6939, -8396}, { 0, 1915, -6784, -8370},
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{ 0, 1871, -6970, -8514}, { 0, 1821, -6974, -8387},
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{ 0, 1781, -6906, -8431}, { 0, 1736, -6897, -8462},
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{ 0, 1664, -7024, -8377}, { 0, 1629, -7127, -8436},
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{ 0, 1603, -7148, -8528}, { 0, 1577, -7198, -8500},
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{ 0, 1528, -7311, -8512}, { 0, 1577, -7390, -8570},
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{ 0, 1616, -7436, -8572}, { 0, 1589, -7597, -8590},
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{ 0, 1722, -7550, -8568}, { 0, 1741, -7691, -8449},
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{ 0, 1767, -7775, -8328},
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},
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// Antenna-2
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{
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{ 0, 2525, -7533, -6846}, { 0, 12726, -7818, -6860},
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{ 0, 2490, -7836, -6907}, { 0, 4479, -7716, -6837},
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{ 0, 6409, -7770, -6776}, { 0, 14616, -7977, -6816},
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{ 0, -22557, -8002, -6911}, { 0, -22587, -8121, -6918},
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{ 0, -1124, -8123, -7030}, { 0, -152, -8219, -7042},
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{ 0, 1823, -8209, -7130}, { 0, 1790, -8290, -7214},
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{ 0, 1669, -8362, -7283}, { 0, 1634, -8459, -7276},
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{ 0, 1615, -8315, -7415}, { 0, 1698, -8168, -7366},
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{ 0, 1535, -8285, -7520}, { 0, 1619, -8285, -7532},
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{ 0, 1609, -8201, -7693}, { 0, 1671, -8145, -7769},
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{ 0, 1676, -8135, -7805}, { 0, 951, -10279, -8871},
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{ 0, 976, -10235, -8978}, { 0, 1118, -10127, -9019},
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{ 0, 1175, -10003, -9007}, { 0, 1386, -9847, -9039},
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{ 0, 1535, -9572, -9058}, { 0, 1729, -9493, -9006},
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{ 0, -1158, -9312, -9003}, { 0, 23771, -9147, -8928},
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{ 0, 20733, -9074, -8924}, { 0, 2455, -8841, -8886},
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{ 0, 2622, -8718, -8735}, { 0, 2791, -8615, -8705},
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{ 0, 2861, -8168, -8331}, { 0, 3076, -8091, -8218},
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{ 0, 3257, -8046, -8100}, { 0, 3331, -7923, -8073},
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{ 0, 3396, -7826, -7994}, { 0, 3478, -7842, -8016},
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{ 0, 3518, -7846, -7765}, { 0, 3585, -7753, -7715},
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{ 0, 150, -8145, -8591}, { 0, 192, -8090, -8570},
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{ 0, 207, -8150, -8597}, { 0, 178, -8142, -8656},
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{ 0, 89, -8557, -8688}, { 0, 107, -8614, -8733},
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{ 0, 194, -8605, -8782}, { 0, 153, -8655, -8881},
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{ 0, 70, -8615, -8952}, { 0, 35, -8596, -9148},
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{ 0, 49, -8636, -9286}, { 0, 6, -8587, -9435},
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{ 0, -51, -8540, -9549}, { 0, -65, -8588, -9700},
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{ 0, -55, -8503, -9820}, { 0, -20, -8414, -9907},
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{ 0, -112, -8481, -10031}, { 0, -69, -8535, -10185},
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{ 0, 2, -8550, -10052}, { 0, -1, -8493, -10291},
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{ 0, -73, -8441, -10380}, { 0, 1958, -6930, -8295},
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{ 0, -1148, -6939, -8396}, { 0, 1915, -6784, -8370},
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{ 0, 1871, -6970, -8514}, { 0, 1821, -6974, -8387},
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{ 0, 1781, -6906, -8431}, { 0, 1736, -6897, -8462},
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{ 0, 1664, -7024, -8377}, { 0, 1629, -7127, -8436},
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{ 0, 1603, -7148, -8528}, { 0, 1577, -7198, -8500},
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{ 0, 1528, -7311, -8512}, { 0, 1577, -7390, -8570},
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{ 0, 1616, -7436, -8572}, { 0, 1589, -7597, -8590},
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{ 0, 1722, -7550, -8568}, { 0, 1741, -7691, -8449},
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{ 0, 1767, -7775, -8328},
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},
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// Antenna-3
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{
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{ 0, 2525, -7533, -6846}, { 0, 12726, -7818, -6860},
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{ 0, 2490, -7836, -6907}, { 0, 4479, -7716, -6837},
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{ 0, 6409, -7770, -6776}, { 0, 14616, -7977, -6816},
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{ 0, -22557, -8002, -6911}, { 0, -22587, -8121, -6918},
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{ 0, -1124, -8123, -7030}, { 0, -152, -8219, -7042},
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{ 0, 1823, -8209, -7130}, { 0, 1790, -8290, -7214},
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{ 0, 1669, -8362, -7283}, { 0, 1634, -8459, -7276},
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{ 0, 1615, -8315, -7415}, { 0, 1698, -8168, -7366},
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{ 0, 1535, -8285, -7520}, { 0, 1619, -8285, -7532},
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{ 0, 1609, -8201, -7693}, { 0, 1671, -8145, -7769},
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{ 0, 1676, -8135, -7805}, { 0, 951, -10279, -8871},
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{ 0, 976, -10235, -8978}, { 0, 1118, -10127, -9019},
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{ 0, 1175, -10003, -9007}, { 0, 1386, -9847, -9039},
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{ 0, 1535, -9572, -9058}, { 0, 1729, -9493, -9006},
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{ 0, -1158, -9312, -9003}, { 0, 23771, -9147, -8928},
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{ 0, 20733, -9074, -8924}, { 0, 2455, -8841, -8886},
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{ 0, 2622, -8718, -8735}, { 0, 2791, -8615, -8705},
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{ 0, 2861, -8168, -8331}, { 0, 3076, -8091, -8218},
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{ 0, 3257, -8046, -8100}, { 0, 3331, -7923, -8073},
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{ 0, 3396, -7826, -7994}, { 0, 3478, -7842, -8016},
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{ 0, 3518, -7846, -7765}, { 0, 3585, -7753, -7715},
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{ 0, 150, -8145, -8591}, { 0, 192, -8090, -8570},
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{ 0, 207, -8150, -8597}, { 0, 178, -8142, -8656},
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{ 0, 89, -8557, -8688}, { 0, 107, -8614, -8733},
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{ 0, 194, -8605, -8782}, { 0, 153, -8655, -8881},
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{ 0, 70, -8615, -8952}, { 0, 35, -8596, -9148},
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{ 0, 49, -8636, -9286}, { 0, 6, -8587, -9435},
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{ 0, -51, -8540, -9549}, { 0, -65, -8588, -9700},
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{ 0, -55, -8503, -9820}, { 0, -20, -8414, -9907},
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{ 0, -112, -8481, -10031}, { 0, -69, -8535, -10185},
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{ 0, 2, -8550, -10052}, { 0, -1, -8493, -10291},
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{ 0, -73, -8441, -10380}, { 0, 1958, -6930, -8295},
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{ 0, -1148, -6939, -8396}, { 0, 1915, -6784, -8370},
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{ 0, 1871, -6970, -8514}, { 0, 1821, -6974, -8387},
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{ 0, 1781, -6906, -8431}, { 0, 1736, -6897, -8462},
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{ 0, 1664, -7024, -8377}, { 0, 1629, -7127, -8436},
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{ 0, 1603, -7148, -8528}, { 0, 1577, -7198, -8500},
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{ 0, 1528, -7311, -8512}, { 0, 1577, -7390, -8570},
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{ 0, 1616, -7436, -8572}, { 0, 1589, -7597, -8590},
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{ 0, 1722, -7550, -8568}, { 0, 1741, -7691, -8449},
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{ 0, 1767, -7775, -8328},
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},
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};
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const uint8_t hopPattern_ADV_24MS[L1_FRAME_ADV_24MS_HOPS] =
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{
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0U, 35U, 66U, 47U, 40U, 16U, 30U, 65U,
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43U, 7U, 70U, 63U, 7U, 65U, 42U, 28U,
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};
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const uint8_t hopPattern_ACK_8MS[L1_FRAME_ACK_8MS_HOPS] =
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{
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0U, 5U, 49U, 25U,
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};
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const uint8_t hopPattern_128KBPS_4MS[L1_FRAME_128KBPS_4MS_HOPS] =
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{
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80U, 16U, 17U, 65U, 60U, 54U, 31U, 15U,
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6U, 19U, 79U, 52U, 29U, 42U, 23U, 59U,
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60U, 58U, 76U, 67U, 31U, 76U, 77U, 79U,
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79U, 14U, 61U, 5U, 71U, 50U, 32U, 77U,
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60U,
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};
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const uint8_t hopPattern_512KBPS_4MS[L1_FRAME_512KBPS_4MS_HOPS] =
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{
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80U, 62U, 40U, 66U, 65U, 33U, 55U, 33U,
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57U, 11U, 37U, 45U, 5U, 69U, 77U, 54U,
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37U, 63U, 14U, 64U, 76U, 31U, 45U, 52U,
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40U, 20U, 20U, 32U, 0U, 60U, 23U, 19U,
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15U, 38U, 62U, 18U,
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};
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const uint8_t hopPattern_2MBPS_4MS[L1_FRAME_2MBPS_4MS_HOPS] =
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{
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0U, 13U, 37U, 44U, 16U, 0U, 59U, 50U,
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69U, 70U, 58U, 14U, 9U, 72U, 27U, 25U,
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21U, 76U, 20U, 35U, 30U, 58U, 22U, 59U,
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48U, 33U, 8U, 7U, 41U, 12U, 44U, 79U,
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77U, 38U, 76U, 75U, 48U, 56U,
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};
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/** @} PhysicalLayer_AntennaConfig_Constants*/
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/*****************************************************************************/
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/**
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* @brief Initialize antenna configurations (load preset values)
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*
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* @param antConfig pointer to antenna configure
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*
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* @return None.
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*
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******************************************************************************/
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void Phy_AntConfigInit(PHY_ANT_CONFIG *antConfig)
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{
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ASSERT(antConfig != NULL);
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// FIXME: Dummy default value.
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for (uint8_t ii = 0; ii < L1_ANT_NUM; ii ++)
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{
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for (uint8_t jj = 0; jj < L1_ANT_CH_NUM; jj ++)
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{
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antConfig->rfNormComp[ii][jj] = 0;
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antConfig->rfNormIdpAttn[ii][jj] = 0;
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}
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antConfig->rfNormComAttn[ii] = 0;
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antConfig->rfFreq[ii][0] = (uint8_t)(DEFAULT_CENTRTAL_FREQ);
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antConfig->rfFreq[ii][1] = (uint8_t)(DEFAULT_CENTRTAL_FREQ >> 8);
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}
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for (uint8_t ii = 0; ii < L1_ANT_CH_NUM; ii ++)
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{
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antConfig->rfAntiAttn[ii] = 0;
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}
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antConfig->antControl.antMode = ANT_MODE_RX_NORMAL;
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antConfig->antControl.antRx1En = ANT_DISABLE;
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antConfig->antControl.antRx2En = ANT_DISABLE;
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antConfig->antControl.antRx3En = ANT_DISABLE;
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antConfig->antControl.antTx1En = ANT_DISABLE;
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antConfig->antControl.antTx2En = ANT_DISABLE;
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antConfig->antControl.antTx3En = ANT_DISABLE;
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}
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/*****************************************************************************/
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/**
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* @brief Set tx antenna index
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*
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* @param instPtr pointer to physical layer instance
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* @param antTxIndex target tx antenna index
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*
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* @return None.
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*
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******************************************************************************/
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void Phy_SetTxAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antIndex)
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{
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ASSERT(instPtr != NULL);
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switch (antIndex)
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{
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case PHY_ANT_INDEX_1:
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instPtr->antConfig.antControl.antTx1En = ANT_ENABLE;
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instPtr->antConfig.antControl.antTx2En = ANT_DISABLE;
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instPtr->antConfig.antControl.antTx3En = ANT_DISABLE;
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break;
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case PHY_ANT_INDEX_2:
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instPtr->antConfig.antControl.antTx1En = ANT_DISABLE;
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instPtr->antConfig.antControl.antTx2En = ANT_ENABLE;
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instPtr->antConfig.antControl.antTx3En = ANT_DISABLE;
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break;
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case PHY_ANT_INDEX_3:
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instPtr->antConfig.antControl.antTx1En = ANT_DISABLE;
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instPtr->antConfig.antControl.antTx2En = ANT_DISABLE;
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instPtr->antConfig.antControl.antTx3En = ANT_ENABLE;
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||||
break;
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default:
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instPtr->antConfig.antControl.antTx1En = ANT_DISABLE;
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instPtr->antConfig.antControl.antTx2En = ANT_DISABLE;
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||||
instPtr->antConfig.antControl.antTx3En = ANT_DISABLE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief Set rx antenna index
|
||||
*
|
||||
* @param instPtr pointer to physical layer instance
|
||||
* @param antRxIndex target rx antenna index
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Phy_SetRxAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antRxIndex)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
|
||||
if (instPtr->antConfig.antControl.antMode == ANT_MODE_RX_AJ)
|
||||
{
|
||||
switch (antRxIndex)
|
||||
{
|
||||
case PHY_ANT_INDEX_1:
|
||||
instPtr->antConfig.antControl.antRx1En = ANT_ENABLE;
|
||||
instPtr->antConfig.antControl.antRx2En = ANT_DISABLE;
|
||||
instPtr->antConfig.antControl.antRx3En = ANT_DISABLE;
|
||||
break;
|
||||
case PHY_ANT_INDEX_2:
|
||||
instPtr->antConfig.antControl.antRx1En = ANT_DISABLE;
|
||||
instPtr->antConfig.antControl.antRx2En = ANT_ENABLE;
|
||||
instPtr->antConfig.antControl.antRx3En = ANT_DISABLE;
|
||||
break;
|
||||
case PHY_ANT_INDEX_3:
|
||||
instPtr->antConfig.antControl.antRx1En = ANT_DISABLE;
|
||||
instPtr->antConfig.antControl.antRx2En = ANT_DISABLE;
|
||||
instPtr->antConfig.antControl.antRx3En = ANT_ENABLE;
|
||||
break;
|
||||
default:
|
||||
instPtr->antConfig.antControl.antRx1En = ANT_DISABLE;
|
||||
instPtr->antConfig.antControl.antRx2En = ANT_DISABLE;
|
||||
instPtr->antConfig.antControl.antRx3En = ANT_DISABLE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
instPtr->antConfig.antControl.antRx1En = ANT_DISABLE;
|
||||
instPtr->antConfig.antControl.antRx2En = ANT_DISABLE;
|
||||
instPtr->antConfig.antControl.antRx3En = ANT_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief Set rx mode to normal or anti-jamming.
|
||||
*
|
||||
* @param instPtr pointer to physical layer instance
|
||||
* @param antRxMode target rx mode
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Phy_SetRxMode(PHY_INST *instPtr, PHY_ANT_RX_MODE antRxMode)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
|
||||
instPtr->antConfig.antControl.antMode = antRxMode;
|
||||
// Sync logs to system monitor
|
||||
SysMonitor_UpdatePhysicalLayerLog(&(instPtr->phyLog));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief Update antenna index of the next slot.
|
||||
*
|
||||
* @param instPtr pointer to physical layer instance
|
||||
* @param AntIndex antenna index
|
||||
*
|
||||
* @return SUCCESS.
|
||||
* EPARAM - antenna index exceeds predefined range
|
||||
*
|
||||
******************************************************************************/
|
||||
int32_t Phy_SetAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antIndex)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
|
||||
if (antIndex < 0 || antIndex >= L1_ANT_NUM)
|
||||
{
|
||||
DBG_ERROR("Antenna index out of range: %" PRIu8 ". \n", antIndex);
|
||||
return EPARAM;
|
||||
}
|
||||
DBG_INFO("Set new antenna index: %" PRId8 "\n", antIndex);
|
||||
instPtr->antIndex.next = antIndex;
|
||||
Phy_SetTxAntIndex(instPtr, antIndex);
|
||||
Phy_SetRxAntIndex(instPtr, antIndex);
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get antenna index of the next slot.
|
||||
*/
|
||||
inline size_t Phy_GetNextAntIndex(PHY_INST *instPtr)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
return instPtr->antIndex.next;
|
||||
}
|
||||
|
||||
/** @} PhysicalLayer_AntennaControl*/
|
||||
|
||||
/** @} PhysicalLayer*/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,304 @@
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file phy_layer.c
|
||||
* @author FanHao ([email protected])
|
||||
* @brief Physical layer control header file.
|
||||
* @version 0.0
|
||||
* @date 2023-04-24
|
||||
*
|
||||
* @copyright Copyright(c) 2024 Beijing Institute of Technology.\n
|
||||
* Lab of Communication and Network
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @defgroup PhysicalLayer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef PHY_CTRL_H_
|
||||
#define PHY_CTRL_H_
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include <stdint.h>
|
||||
#include "common.h"
|
||||
#ifndef EMULATION
|
||||
#include "xbram.h"
|
||||
#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
|
||||
#include "xsysmon.h"
|
||||
#else
|
||||
#include "xadcps.h"
|
||||
#endif
|
||||
#include "../config/app_config.h"
|
||||
#endif
|
||||
#include "../../system_monitor.h"
|
||||
#include "../../time_ctrl/time_ctrl.h"
|
||||
/************************** Constant Definitions *****************************/
|
||||
/**
|
||||
* @name PhysicalLayer_Common_Constant
|
||||
* @{
|
||||
*/
|
||||
#define L1_ANT_NUM 3U // 1 beam per antenna, and 3 antennas in total
|
||||
#define L1_ANT_CH_NUM 4U // channel number per antenna
|
||||
#define L1_INIT_ANT_IDX 0U
|
||||
|
||||
#define L1_FRAME_NONE_LEN UINT32_MAX // byte
|
||||
#define L1_FRAME_NONE_COMP UINT32_MAX // *10ns(Timer_L)
|
||||
#define L1_FRAME_NONE_HOPS UINT32_MAX
|
||||
#define L1_FRAME_MAX_HOPS 81
|
||||
#define L1_FRAME_ADV_24MS_HOPS 16U // sync 16 ms + data 8 ms, 2000 hops/s
|
||||
#define L1_FRAME_ACK_8MS_HOPS 4U // sync 6 ms + data 2 ms, 2000 hops/s
|
||||
#define L1_FRAME_128KBPS_4MS_HOPS 33U
|
||||
#define L1_FRAME_512KBPS_4MS_HOPS 36U
|
||||
#define L1_FRAME_2MBPS_4MS_HOPS 38U
|
||||
#define PHY_LOG_EXPIRE 50U // number of 2 ms slot
|
||||
/** @} */
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
/**************************** Type Definitions *******************************/
|
||||
/**
|
||||
* @enum L1_FRAME_TYPE
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
L1_FRAME_NONE = 0,
|
||||
L1_FRAME_ADV_24MS = 1,
|
||||
L1_FRAME_ACK_8MS = 2,
|
||||
L1_FRAME_128KBPS_4MS = 3, // 128kbps
|
||||
L1_FRAME_512KBPS_4MS = 4, // 512kbps
|
||||
L1_FRAME_2MBPS_4MS = 5 // 2 Mbps
|
||||
} L1_FRAME_TYPE;
|
||||
|
||||
/**
|
||||
* @struct PHY_ANT_CONFIG
|
||||
* @brief PhysicalLayer antenna config
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*** Antenna & RF Control ***/
|
||||
uint8_t rfNormComp[L1_ANT_NUM][L1_ANT_CH_NUM];
|
||||
///< Normal mode RF phase compensation, 3 antennas
|
||||
/// and 4 channels each: 0~63, 5.625° step
|
||||
uint8_t rfNormIdpAttn[L1_ANT_NUM][L1_ANT_CH_NUM];
|
||||
///< Normal mode RF attenuation for independent channel:
|
||||
/// 0~30 dB, 1dB step
|
||||
uint8_t rfNormComAttn[L1_ANT_NUM];
|
||||
///< Normal mode RF attenuation for combined channel:
|
||||
/// 0~30 dB, 1dB step
|
||||
struct
|
||||
{
|
||||
uint8_t antMode : 1; /// [0]: Anti-jamming mode control, 1 - enable, 0 - disable
|
||||
/// only one antenna can be selected in anti-jamming mode
|
||||
uint8_t antRx1En : 1; /// [1]: Anti-jamming antenna 1 select, 1 - enable, 0 - disable
|
||||
uint8_t antRx2En : 1; /// [2]: Anti-jamming antenna 2 select, 1 - enable, 0 - disable
|
||||
uint8_t antRx3En : 1; /// [3]: Anti-jamming antenna 3 select, 1 - enable, 0 - disable
|
||||
uint8_t antTx1En : 1; /// [4]: Antenna 1 tx control, 1 - enable, 0 - disable
|
||||
uint8_t antTx2En : 1; /// [5]: Antenna 2 tx control, 1 - enable, 0 - disable
|
||||
uint8_t antTx3En : 1; /// [6]: Antenna 3 tx control, 1 - enable, 0 - disable
|
||||
uint8_t antRsvd : 1; /// [7]: reserved
|
||||
} antControl;
|
||||
|
||||
uint8_t rfAntiAttn[L1_ANT_CH_NUM];
|
||||
///< Anti-jamming mode RF attenuation, 4 channels:
|
||||
/// 0~60 dB, 1dB step
|
||||
uint8_t rfFreq[L1_ANT_NUM][2];
|
||||
///< RF synthesizer ping-pong frequency, 3 antennas
|
||||
/// and 2 byte each: 0~600 MHz, step 1MHz, with base
|
||||
/// frequency of 3700 MHz
|
||||
uint8_t rfRsvd; ///< reserved for further use
|
||||
} PHY_ANT_CONFIG;
|
||||
|
||||
/**
|
||||
* @enum PHY_TIME_WORD_TYPE
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PHY_TIME_WORD_NONE = 0,
|
||||
PHY_TIME_WORD_POLL = 1,
|
||||
PHY_TIME_WORD_LISTEN_TIMEOUT = 2
|
||||
} PHY_TIME_WORD_TYPE;
|
||||
|
||||
/**
|
||||
* @enum PHY_TOR_TYPE
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PHY_TOR_SUSPEND = 0,
|
||||
PHY_TOR_TX = 1,
|
||||
PHY_TOR_RX = 2
|
||||
} PHY_TOR_TYPE;
|
||||
|
||||
/**
|
||||
* @enum PHY_MODE
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PHY_MODE_NONE = 0,
|
||||
PHY_MODE_LISTEN = 1,
|
||||
PHY_MODE_POLL = 2
|
||||
} PHY_MODE;
|
||||
|
||||
/**
|
||||
* @enum PHY_ANT_MODE
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PHY_ANT_MODE_NONE = 0,
|
||||
PHY_ANT_MODE_STANDBY = 1,
|
||||
PHY_ANT_MODE_NORMAL = 2,
|
||||
PHY_ANT_MODE_ANTI_JAM = 3
|
||||
} PHY_ANT_MODE;
|
||||
|
||||
/**
|
||||
* @enum PHY_ANT_RX_MODE
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PHY_ANT_RX_MODE_NORMAL = 0,
|
||||
PHY_ANT_RX_MODE_AJ = 1
|
||||
} PHY_ANT_RX_MODE;
|
||||
|
||||
/**
|
||||
* @enum PHY_ANT_INDEX
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PHY_ANT_INDEX_NONE = 0,
|
||||
PHY_ANT_INDEX_1 = 1,
|
||||
PHY_ANT_INDEX_2 = 2,
|
||||
PHY_ANT_INDEX_3 = 3
|
||||
} PHY_ANT_INDEX;
|
||||
|
||||
/**
|
||||
* @struct PHY_RCD
|
||||
* @brief Physical Layer recode buffer
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
int32_t last;
|
||||
int32_t curr;
|
||||
int32_t next;
|
||||
} PHY_RCD;
|
||||
|
||||
/**
|
||||
* @struct PHY_CONFIG
|
||||
* @brief struct holds all physical layer initialization parameters
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t devId; ///< device ID
|
||||
uint32_t txBramId; ///< tx bram ID
|
||||
uint32_t rxBramId; ///< rx bram ID
|
||||
uint32_t antBramId; ///< antenna config bram ID
|
||||
#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
|
||||
uint32_t hwSysmonId; ///< hardware system monitor device ID
|
||||
#else
|
||||
uint32_t hwXadcId; ///< hardware xadc device ID
|
||||
#endif
|
||||
uintptr_t baseAddr; ///< Physical layer controller base address
|
||||
#ifndef EMULATION
|
||||
uint8_t (*get_clk_state)(void); ///< function handle returns hardware clock state
|
||||
uint8_t (*get_ad_lock_state)(void); ///< function handle returns adc lock state
|
||||
int8_t (*get_ad0_temp)(void); ///< function handle returns adc0 temperature state
|
||||
int8_t (*get_ad1_temp)(void); ///< function handle returns adc1 temperature state
|
||||
#endif
|
||||
} PHY_CONFIG;
|
||||
|
||||
/**
|
||||
* @struct PHY_INST
|
||||
* @brief Physical Layer operating instance
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
PHY_CONFIG phyCofig; ///< physical layer configuration parameters
|
||||
uintptr_t recvDataAddr; ///< receive data bram address
|
||||
uintptr_t sendDataAddr; ///< send data bram address
|
||||
uintptr_t antConfigAddr; ///< antenna config data bram address
|
||||
bool isPhyEn; ///< indicates if physical layer running
|
||||
bool isAcq; ///< indicates if last reception acquisition success
|
||||
bool isFrameSync; ///< indicates if last reception frame sync success
|
||||
bool isDecode; ///< indicates if last reception decode success
|
||||
bool isValid; ///< indicates if last reception frame data valid (crc check pass)
|
||||
TIME_WORD recvSlotTime; ///< last slot start time stamp
|
||||
TIME_WORD recvFsTime; ///< last frame sync time stamp
|
||||
PHY_RCD antIndex; ///< antenna number record
|
||||
PHY_RCD tor; ///< tx rx state record
|
||||
PHY_RCD frameType; ///< frame type record
|
||||
uint32_t sendDataOffset; ///< antenna configuration bram offset (to implement ping-pong data flow)
|
||||
uint32_t antConfigOffset; ///< antenna configuration bram offset (to implement ping-pong data flow)
|
||||
PHY_ANT_CONFIG antConfig; ///< antenna configuration pointer
|
||||
#ifndef EMULATION
|
||||
#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
|
||||
XSysMon sysMon; ///< System monitor
|
||||
#else
|
||||
XAdcPs hwXadc; ///< hardware Xadc instance
|
||||
#endif
|
||||
#endif
|
||||
HWSTATE hwSate; ///< hardware state log
|
||||
PHYLOG phyLog; ///< physical state log
|
||||
uint32_t lastLogTime; /// physical state log time stamp
|
||||
} PHY_INST;
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/**
|
||||
* @defgroup PhysicalLayer_Main
|
||||
* @{
|
||||
*/
|
||||
int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig);
|
||||
void Phy_Destroy(PHY_INST *instPtr);
|
||||
void Phy_Start(PHY_INST *instPtr);
|
||||
void Phy_Halt(PHY_INST *instPtr);
|
||||
|
||||
int32_t Phy_SetMode(PHY_INST *instPtr, PHY_MODE modeCod);
|
||||
int32_t Phy_SetTimeWord(PHY_INST *instPtr, const TIME_WORD *tmWord, PHY_TIME_WORD_TYPE tmType);
|
||||
int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode, L1_FRAME_TYPE frameType, uint8_t *dataBuff);
|
||||
void Phy_UpdateState(PHY_INST *instPtr);
|
||||
void Phy_PeekRecvData(PHY_INST *instPtr, uint8_t *dataBuff);
|
||||
void Phy_RetrieveRecvData(PHY_INST *instPtr, uint8_t *dataBuff);
|
||||
void Phy_UpdateLogging(PHY_INST *instPtr);
|
||||
void Phy_RefreshHwSate(PHY_INST *instPtr);
|
||||
/** @} PhysicalLayer_Main*/
|
||||
|
||||
/**
|
||||
* @defgroup PhysicalLayer_Utility
|
||||
* @{
|
||||
*/
|
||||
bool Phy_IsFrameDetected(PHY_INST *instPtr);
|
||||
bool Phy_IsFrameReceived(PHY_INST *instPtr);
|
||||
bool Phy_IsFrameValid(PHY_INST *instPtr);
|
||||
uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType);
|
||||
uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType);
|
||||
uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType);
|
||||
L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr);
|
||||
L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr);
|
||||
/** @} PhysicalLayer_Utility*/
|
||||
|
||||
/**
|
||||
* @defgroup PhysicalLayer_Receive_Estimations
|
||||
* @{
|
||||
*/
|
||||
uint8_t Phy_ReceiveAntIndex(PHY_INST *instPtr);
|
||||
double Phy_GetFreqEst(PHY_INST *instPtr);
|
||||
double Phy_GetCoarseFreqEst(PHY_INST *instPtr);
|
||||
double Phy_GetFineFreqEst(PHY_INST *instPtr);
|
||||
void Phy_GetFrameSyncTimeStamp(PHY_INST *instPtr, TIME_WORD *frameSyncT);
|
||||
void Phy_GetLastReceivedFrameSyncTimeStamp(PHY_INST *instPtr, TIME_WORD *frameSyncT);
|
||||
void Phy_GetSlotStartTimeStamp(PHY_INST *instPtr, TIME_WORD *slotStart);
|
||||
void Phy_GetLastReceivedSlotStartTimeStamp(PHY_INST *instPtr, TIME_WORD *slotStart);
|
||||
/** @} PhysicalLayer_Receive_Estimations*/
|
||||
|
||||
/**
|
||||
* @defgroup PhysicalLayer_AntennaControl
|
||||
* @{
|
||||
*/
|
||||
void Phy_AntConfigInit(PHY_ANT_CONFIG *antConfig);
|
||||
void Phy_SetTxAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antIndex);
|
||||
void Phy_SetRxAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antRxIndex);
|
||||
void Phy_SetRxMode(PHY_INST *instPtr, PHY_ANT_RX_MODE antRxMode);
|
||||
int32_t Phy_SetAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antIndex);
|
||||
size_t Phy_GetNextAntIndex(PHY_INST *instPtr);
|
||||
/** @} PhysicalLayer_AntennaControl*/
|
||||
|
||||
#endif // PHY_CTRL_H_
|
||||
|
||||
/** @} PhysicalLayer*/
|
||||
@@ -0,0 +1,502 @@
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file phy_layer.h
|
||||
* @author FanHao ([email protected])
|
||||
* @brief Physical layer controller register definition
|
||||
* @version 0.0
|
||||
* @date 2023-04-24
|
||||
*
|
||||
* @copyright Copyright(c) 2024 Beijing Institute of Technology.\n
|
||||
* Lab of Communication and Network
|
||||
*
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup PhysicalLayer
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @name PhysicalLayer_REG_Constants
|
||||
* @{
|
||||
*/
|
||||
#ifndef PHY_REG_H_
|
||||
#define PHY_REG_H_
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "util.h"
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
#define PhyRead(instPtr, addr) IO_In32((instPtr)->phyCofig.baseAddr + (addr))
|
||||
#define PhyWrite(instPtr, addr, value) IO_Out32((instPtr)->phyCofig.baseAddr + (addr), (value))
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
/**
|
||||
* Register: PHY_MAIN_CTRL
|
||||
*/
|
||||
#define PHY_MAIN_CTRL 0x00000000U
|
||||
#define PHY_MAIN_CTRL_EN_SHIFT 0
|
||||
#define PHY_MAIN_CTRL_EN_WIDTH 1
|
||||
#define PHY_MAIN_CTRL_EN_MASK 0x00000001U
|
||||
#define PHY_MAIN_CTRL_MODE_SHIFT 8
|
||||
#define PHY_MAIN_CTRL_MODE_WIDTH 8
|
||||
#define PHY_MAIN_CTRL_MODE_MASK 0x0000FF00U
|
||||
#define PHY_MAIN_CTRL_NSCAN_SHIFT 16
|
||||
#define PHY_MAIN_CTRL_NSCAN_WIDTH 8
|
||||
#define PHY_MAIN_CTRL_NSCAN_MASK 0x00FF0000U
|
||||
|
||||
#define PHY_MAIN_CTRL_EN_EN 0x00000001U
|
||||
#define PHY_MAIN_CTRL_EN_DSBL 0x00000000U
|
||||
#define PHY_MAIN_CTRL_MODE_NONE 0x00000000U
|
||||
#define PHY_MAIN_CTRL_MODE_LISTEN 0x00000100U
|
||||
#define PHY_MAIN_CTRL_MODE_POLL 0x00000200U
|
||||
|
||||
/**
|
||||
* Register: TXRX_CTRL
|
||||
*/
|
||||
#define PHY_MODE_CTRL 0x00000004U
|
||||
#define PHY_MODE_CTRL_TOR_SHIFT 0
|
||||
#define PHY_MODE_CTRL_TOR_WIDTH 8
|
||||
#define PHY_MODE_CTRL_TOR_MASK 0x000000FFU
|
||||
#define PHY_MODE_CTRL_FRAME_SHIFT 8
|
||||
#define PHY_MODE_CTRL_FRAME_WIDTH 8
|
||||
#define PHY_MODE_CTRL_FRAME_MASK 0x0000FF00U
|
||||
#define PHY_MODE_CTRL_CRC_SHIFT 8
|
||||
#define PHY_MODE_CTRL_CRC_WIDTH 16
|
||||
#define PHY_MODE_CTRL_CRC_MASK 0x00FF0000U
|
||||
|
||||
#define PHY_MODE_CTRL_TOR_SUSPEND 0x00000000U
|
||||
#define PHY_MODE_CTRL_TOR_TX 0x00000001U
|
||||
#define PHY_MODE_CTRL_TOR_RX 0x00000002U
|
||||
|
||||
#define PHY_MODE_CTRL_FRAME_NONE 0x00000000U
|
||||
#define PHY_MODE_CTRL_FRAME_ADV_24MS 0x00000100U
|
||||
#define PHY_MODE_CTRL_FRAME_ACK_8MS 0x00000200U
|
||||
#define PHY_MODE_CTRL_FRAME_128KBPS_4MS 0x00000300U
|
||||
#define PHY_MODE_CTRL_FRAME_512KBPS_4MS 0x00000400U
|
||||
#define PHY_MODE_CTRL_FRAME_2MBPS_4MS 0x00000500U
|
||||
|
||||
#define PHY_MODE_CTRL_CRC_EN 0x00010000U
|
||||
#define PHY_MODE_CTRL_CRC_DSBL 0x00000000U
|
||||
/**
|
||||
* Register: POLLTIME_L
|
||||
*/
|
||||
#define POLLTIME_L 0x00000008U
|
||||
#define POLLTIME_L_SHIFT 0
|
||||
#define POLLTIME_L_WIDTH 32
|
||||
#define POLLTIME_L_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: POLLTIME_H
|
||||
*/
|
||||
#define POLLTIME_H 0x0000000CU
|
||||
#define POLLTIME_H_SHIFT 0
|
||||
#define POLLTIME_H_WIDTH 32
|
||||
#define POLLTIME_H_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: TIMEOUT_L
|
||||
*/
|
||||
#define LISTENTIMEOUT_L 0x00000010U
|
||||
#define LISTENTIMEOUT_L_SHIFT 0
|
||||
#define LISTENTIMEOUT_L_WIDTH 32
|
||||
#define LISTENTIMEOUT_L_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: TIMEOUT_H
|
||||
*/
|
||||
#define LISTENTIMEOUT_H 0x00000014U
|
||||
#define LISTENTIMEOUT_H_SHIFT 0
|
||||
#define LISTENTIMEOUT_H_WIDTH 32
|
||||
#define LISTENTIMEOUT_H_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: ANT_CTRL
|
||||
*/
|
||||
#define ANT_CONFIG 0x00000018U
|
||||
#define ANT_CONFIG_OFFSET_SHIFT 0
|
||||
#define ANT_CONFIG_OFFSET_WIDTH 16
|
||||
#define ANT_CONFIG_OFFSET_MASK 0x0000FFFFU
|
||||
#define ANT_CONFIG_LEN_SHIFT 16
|
||||
#define ANT_CONFIG_LEN_WIDTH 8
|
||||
#define ANT_CONFIG_LEN_MASK 0x00FF0000U
|
||||
#define ANT_CONFIG_NUM_SHIFT 24
|
||||
#define ANT_CONFIG_NUM_WIDTH 8
|
||||
#define ANT_CONFIG_NUM_MASK 0xFF000000U
|
||||
|
||||
/**
|
||||
* Register: SEND_DATA_CMD
|
||||
*/
|
||||
#define SEND_DATA_CMD 0x0000001CU
|
||||
#define SEND_DATA_CMD_SHIFT 0
|
||||
#define SEND_DATA_CMD_WIDTH 32
|
||||
#define SEND_DATA_CMD_MASK 0xFFFFFFFFU
|
||||
|
||||
#define SEND_DATA_CMD_LEN_SHIFT 0
|
||||
#define SEND_DATA_CMD_LEN_WIDTH 16
|
||||
#define SEND_DATA_CMD_LEN_MASK 0x0000FFFFU
|
||||
#define SEND_DATA_CMD_OFFSET_SHIFT 16
|
||||
#define SEND_DATA_CMD_OFFSET_WIDTH 16
|
||||
#define SEND_DATA_CMD_OFFSET_MASK 0xFFFF0000U
|
||||
|
||||
/**
|
||||
* Register: SLOT_CONFIG_CMD
|
||||
*/
|
||||
#define SLOT_CMD 0x00000020U
|
||||
#define SLOT_CMD_SHIFT 0
|
||||
#define SLOT_CMD_WIDTH 32
|
||||
#define SLOT_CMD_MASK 0xFFFFFFFFU
|
||||
#define SLOT_CMD_KEY 0x434D442EU
|
||||
|
||||
/**
|
||||
* Register: TXRX_STATE
|
||||
*/
|
||||
#define TXRX_STATE 0x00000024U
|
||||
#define TXRX_STATE_ACQ_SHIFT 0
|
||||
#define TXRX_STATE_ACQ_WIDTH 8
|
||||
#define TXRX_STATE_ACQ_MASK 0x000000FFU
|
||||
#define TXRX_STATE_ACQ_SUCCESS 0x00000001U
|
||||
#define TXRX_STATE_ACQ_FAIL 0x00000002U
|
||||
|
||||
#define TXRX_STATE_FSYNC_SHIFT 8
|
||||
#define TXRX_STATE_FSYNC_WIDTH 8
|
||||
#define TXRX_STATE_FSYNC_MASK 0x0000FF00U
|
||||
#define TXRX_STATE_FSYNC_SUCCESS 0x00000100U
|
||||
#define TXRX_STATE_FSYNC_FAIL 0x00000200U
|
||||
|
||||
#define TXRX_STATE_DECODE_SHIFT 16
|
||||
#define TXRX_STATE_DECODE_WIDTH 8
|
||||
#define TXRX_STATE_DECODE_MASK 0x00FF0000U
|
||||
#define TXRX_STATE_DECODE_SUCCESS 0x00010000U
|
||||
#define TXRX_STATE_DECODE_FAIL 0x00020000U
|
||||
|
||||
#define TXRX_STATE_CRC_SHIFT 24
|
||||
#define TXRX_STATE_CRC_WIDTH 8
|
||||
#define TXRX_STATE_CRC_MASK 0xFF000000U
|
||||
#define TXRX_STATE_CRC_OK 0x01000000U
|
||||
#define TXRX_STATE_CRC_ERROR 0x02000000U
|
||||
|
||||
/**
|
||||
* Register: RECVDATA_STATE
|
||||
*/
|
||||
#define RECVDATA_STATE 0x00000028U
|
||||
#define RECVDATA_STATE_LEN_SHIFT 0
|
||||
#define RECVDATA_STATE_LEN_WIDTH 16
|
||||
#define RECVDATA_STATE_LEN_MASK 0x0000FFFFU
|
||||
|
||||
#define RECVDATA_STATE_OFFSET_SHIFT 16
|
||||
#define RECVDATA_STATE_OFFSET_WIDTH 16
|
||||
#define RECVDATA_STATE_OFFSET_MASK 0xFFFF0000U
|
||||
|
||||
/**
|
||||
* Register: FSTIME_L
|
||||
*/
|
||||
#define FSTIME_L 0x0000002CU
|
||||
#define FSTIME_L_SHIFT 0
|
||||
#define FSTIME_L_WIDTH 32
|
||||
#define FSTIME_L_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: FSTIME_INT1
|
||||
*/
|
||||
#define FSTIME_H 0x00000030U
|
||||
#define FSTIME_H_SHIFT 0
|
||||
#define FSTIME_H_WIDTH 32
|
||||
#define FSTIME_H_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: TM_TARGET_L
|
||||
*/
|
||||
#define TM_TARGET_L 0x00000064U
|
||||
#define TM_TARGET_L_SHIFT 0
|
||||
#define TM_TARGET_L_WIDTH 32
|
||||
#define TM_TARGET_L_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: TM_TARGET_H
|
||||
*/
|
||||
#define TM_TARGET_H 0x00000038U
|
||||
#define TM_TARGET_H_SHIFT 0
|
||||
#define TM_TARGET_H_WIDTH 32
|
||||
#define TM_TARGET_H_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: COASEFREQEST
|
||||
*/
|
||||
#define COASE_FREQEST 0x0000003CU
|
||||
#define COASE_FREQEST_ACQ_SHIFT 0
|
||||
#define COASE_FREQEST_ACQ_WIDTH 8
|
||||
#define COASE_FREQEST_ACQ_MASK 0x000000FFU
|
||||
#define COASE_FREQEST_SYNC_SHIFT 8
|
||||
#define COASE_FREQEST_SYNC_WIDTH 8
|
||||
#define COASE_FREQEST_SYNC_MASK 0x0000FF00U
|
||||
#define COASE_TYPE_SHIFT 16
|
||||
#define COASE_TYPE_WIDTH 8
|
||||
#define COASE_TYPE_MASK 0x00FF0000U
|
||||
#define COASE_TYPE_ADV_24MS 0x00010000U
|
||||
#define COASE_TYPE_ACK_8MS 0x00020000U
|
||||
#define COASE_TYPE_128KBPS_4MS 0x00030000U
|
||||
#define COASE_TYPE_512KBPS_4MS 0x00040000U
|
||||
#define COASE_TYPE_2MBPS_4MS 0x00050000U
|
||||
|
||||
/**
|
||||
* Register: FINE_FREQEST
|
||||
*/
|
||||
#define FINE_FREQEST 0x00000040U
|
||||
#define FINE_FREQEST_VAL_SHIFT 0
|
||||
#define FINE_FREQEST_VAL_WIDTH 24
|
||||
#define FINE_FREQEST_VAL_MASK 0x00FFFFFFU
|
||||
#define FINE_FREQEST_SIGN_SHIFT 24
|
||||
#define FINE_FREQEST_SIGN_WIDTH 8
|
||||
#define FINE_FREQEST_SIGN_MASK 0xFF000000U
|
||||
#define FINE_FREQEST_SIGN_POS 0x00000000U
|
||||
#define FINE_FREQEST_SIGN_NEG 0x01000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_SELECT
|
||||
*/
|
||||
#define ANT_SELECT_INDEX 0x00000044U
|
||||
#define ANT_SELECT_INDEX_SHIFT 0
|
||||
#define ANT_SELECT_INDEX_WIDTH 32
|
||||
#define ANT_SELECT_INDEX_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: ANT_STATUS_1
|
||||
*/
|
||||
#define ANT_STATUS_1 0x00000100U
|
||||
|
||||
#define ANT_STATUS_1_ANT1_STATUS_SHIFT 0
|
||||
#define ANT_STATUS_1_ANT1_STATUS_WIDTH 16
|
||||
#define ANT_STATUS_1_ANT1_STATUS_MASK 0x0000FFFFU
|
||||
|
||||
#define ANT_STATUS_1_ANT1_FREQ_SHIFT 0
|
||||
#define ANT_STATUS_1_ANT1_FREQ_WIDTH 15
|
||||
#define ANT_STATUS_1_ANT1_FREQ_MASK 0x00003FFFU
|
||||
|
||||
#define ANT_STATUS_1_ANT1_PLL_SHIFT 15
|
||||
#define ANT_STATUS_1_ANT1_PLL_WIDTH 1
|
||||
#define ANT_STATUS_1_ANT1_PLL_MASK 0x00008000U
|
||||
|
||||
#define ANT_STATUS_1_ANT2_STATUS_SHIFT 16
|
||||
#define ANT_STATUS_1_ANT2_STATUS_WIDTH 16
|
||||
#define ANT_STATUS_1_ANT2_STATUS_MASK 0x0000FFFFU
|
||||
|
||||
#define ANT_STATUS_1_ANT2_FREQ_SHIFT 16
|
||||
#define ANT_STATUS_1_ANT2_FREQ_WIDTH 15
|
||||
#define ANT_STATUS_1_ANT2_FREQ_MASK 0x3FFF0000U
|
||||
|
||||
#define ANT_STATUS_1_ANT2_PLL_SHIFT 31
|
||||
#define ANT_STATUS_1_ANT2_PLL_WIDTH 1
|
||||
#define ANT_STATUS_1_ANT2_PLL_MASK 0x80000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_STATUS_2
|
||||
*/
|
||||
#define ANT_STATUS_2 0x00000104U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_STATUS_SHIFT 0
|
||||
#define ANT_STATUS_2_ANT3_STATUS_WIDTH 16
|
||||
#define ANT_STATUS_2_ANT3_STATUS_MASK 0x0000FFFFU
|
||||
|
||||
#define ANT_STATUS_2_ANT3_FREQ_SHIFT 0
|
||||
#define ANT_STATUS_2_ANT3_FREQ_WIDTH 15
|
||||
#define ANT_STATUS_2_ANT3_FREQ_MASK 0x00003FFFU
|
||||
|
||||
#define ANT_STATUS_2_ANT3_PLL_SHIFT 15
|
||||
#define ANT_STATUS_2_ANT3_PLL_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_PLL_MASK 0x00008000U
|
||||
|
||||
#define ANT_STATUS_2_PLL_LK_SHIFT 16
|
||||
#define ANT_STATUS_2_PLL_LK_WIDTH 8
|
||||
#define ANT_STATUS_2_PLL_LK_MASK 0x00FF0000U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_PLL2_LK_SHIFT 16
|
||||
#define ANT_STATUS_2_ANT3_PLL2_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_PLL2_LK_MASK 0x00010000U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_PLL1_LK_SHIFT 17
|
||||
#define ANT_STATUS_2_ANT3_PLL1_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_PLL1_LK_MASK 0x00020000U
|
||||
|
||||
#define ANT_STATUS_2_ANT2_PLL2_LK_SHIFT 18
|
||||
#define ANT_STATUS_2_ANT2_PLL2_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT2_PLL2_LK_MASK 0x00040000U
|
||||
|
||||
#define ANT_STATUS_2_ANT2_PLL1_LK_SHIFT 19
|
||||
#define ANT_STATUS_2_ANT2_PLL1_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT2_PLL1_LK_MASK 0x00080000U
|
||||
|
||||
#define ANT_STATUS_2_ANT1_PLL2_LK_SHIFT 20
|
||||
#define ANT_STATUS_2_ANT1_PLL2_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT1_PLL2_LK_MASK 0x00100000U
|
||||
|
||||
#define ANT_STATUS_2_ANT1_PLL1_LK_SHIFT 21
|
||||
#define ANT_STATUS_2_ANT1_PLL1_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT1_PLL1_LK_MASK 0x00200000U
|
||||
|
||||
#define ANT_STATUS_2_MODE_SHIFT 24
|
||||
#define ANT_STATUS_2_MODE_WIDTH 8
|
||||
#define ANT_STATUS_2_MODE_MASK 0xFF000000U
|
||||
|
||||
#define ANT_STATUS_2_ANT1_MODE_SHIFT 24
|
||||
#define ANT_STATUS_2_ANT1_MODE_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT1_MODE_MASK 0x01000000U
|
||||
|
||||
#define ANT_STATUS_2_ANT2_MODE_SHIFT 25
|
||||
#define ANT_STATUS_2_ANT2_MODE_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT2_MODE_MASK 0x02000000U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_MODE_SHIFT 26
|
||||
#define ANT_STATUS_2_ANT3_MODE_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_MODE_MASK 0x04000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_STATUS_TEMP
|
||||
*/
|
||||
#define ANT_STATUS_TEMP 0x00000108U
|
||||
|
||||
#define ANT_STATUS_TEMP_SHIFT 0
|
||||
#define ANT_STATUS_TEMP_WIDTH 8
|
||||
#define ANT_STATUS_TEMP_MASK 0x000000FFU
|
||||
|
||||
#define ANT_STATUS_TEMP_RSVD_SHIFT 8
|
||||
#define ANT_STATUS_TEMP_RSVD_WIDTH 8
|
||||
#define ANT_STATUS_TEMP_RSVD_MASK 0x0000FF00U
|
||||
|
||||
/**
|
||||
* Register: PHY_ACQ_CNT
|
||||
*/
|
||||
#define PHY_ACQ_CNT 0x00000114U
|
||||
#define PHY_ACQ_CNT_SHIFT 0
|
||||
#define PHY_ACQ_CNT_WIDTH 32
|
||||
#define PHY_ACQ_CNT_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: PHY_FRAME_SYNC_CNT
|
||||
*/
|
||||
#define PHY_FRAME_SYNC_CNT 0x00000118U
|
||||
#define PHY_FRAME_SYNC_CNT_SHIFT 0
|
||||
#define PHY_FRAME_SYNC_CNT_WIDTH 32
|
||||
#define PHY_FRAME_SYNC_CNT_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: PHY_DECODE_CNT
|
||||
*/
|
||||
#define PHY_DECODE_CNT 0x0000011CU
|
||||
#define PHY_DECODE_CNT_SHIFT 0
|
||||
#define PHY_DECODE_CNT_WIDTH 32
|
||||
#define PHY_DECODE_CNT_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: PHY_CRC_OK_CNT
|
||||
*/
|
||||
#define PHY_CRC_OK_CNT 0x00000120U
|
||||
#define PHY_CRC_OK_CNT_SHIFT 0
|
||||
#define PHY_CRC_OK_CNT_WIDTH 32
|
||||
#define PHY_CRC_OK_CNT_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: PHY_ACQ_PEAK_H
|
||||
*/
|
||||
#define PHY_ACQ_PEAK_H 0x00000124U
|
||||
#define PHY_ACQ_PEAK_H_SHIFT 0
|
||||
#define PHY_ACQ_PEAK_H_WIDTH 32
|
||||
#define PHY_ACQ_PEAK_H_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: PHY_ACQ_PEAK_L
|
||||
*/
|
||||
#define PHY_ACQ_PEAK_L 0x00000128U
|
||||
#define PHY_ACQ_PEAK_L_SHIFT 0
|
||||
#define PHY_ACQ_PEAK_L_WIDTH 32
|
||||
#define PHY_ACQ_PEAK_L_MASK 0xFFFFFFFFU
|
||||
|
||||
|
||||
/**
|
||||
* Register: PHY_ACQ_MEAN_H
|
||||
*/
|
||||
#define PHY_ACQ_MEAN_H 0x0000012CU
|
||||
#define PHY_ACQ_MEAN_H_SHIFT 0
|
||||
#define PHY_ACQ_MEAN_H_WIDTH 32
|
||||
#define PHY_ACQ_MEAN_H_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: PHY_ACQ_MEAN_L
|
||||
*/
|
||||
#define PHY_ACQ_MEAN_L 0x00000130U
|
||||
#define PHY_ACQ_MEAN_L_SHIFT 0
|
||||
#define PHY_ACQ_MEAN_L_WIDTH 32
|
||||
#define PHY_ACQ_MEAN_L_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: PHY_ACQ_FREQEST
|
||||
*/
|
||||
#define PHY_ACQ_FREQEST 0x00000134U
|
||||
#define PHY_ACQ_FREQEST_SHIFT 0
|
||||
#define PHY_ACQ_FREQEST_WIDTH 32
|
||||
#define PHY_ACQ_FREQEST_MASK 0xFFFFFFFFU
|
||||
|
||||
#define PHY_ACQ_FREQEST_PHASE_SHIFT 0
|
||||
#define PHY_ACQ_FREQEST_PHASE_WIDTH 8
|
||||
#define PHY_ACQ_FREQEST_PHASE_MASK 0x000000FFU
|
||||
#define PHY_ACQ_FREQEST_CHANNEL_SHIFT 8
|
||||
#define PHY_ACQ_FREQEST_CHANNEL_WIDTH 8
|
||||
#define PHY_ACQ_FREQEST_CHANNEL_MASK 0x0000FF00U
|
||||
|
||||
/**
|
||||
* Register: PHY_FRAME_SYNC_PEAK_H
|
||||
*/
|
||||
#define PHY_FRAME_SYNC_PEAK_H 0x00000138U
|
||||
#define PHY_FRAME_SYNC_PEAK_H_SHIFT 0
|
||||
#define PHY_FRAME_SYNC_PEAK_H_WIDTH 32
|
||||
#define PHY_FRAME_SYNC_PEAK_H_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: PHY_FRAME_SYNC_PEAK_L
|
||||
*/
|
||||
#define PHY_FRAME_SYNC_PEAK_L 0x0000013CU
|
||||
#define PHY_FRAME_SYNC_PEAK_L_SHIFT 0
|
||||
#define PHY_FRAME_SYNC_PEAK_L_WIDTH 32
|
||||
#define PHY_FRAME_SYNC_PEAK_L_MASK 0xFFFFFFFFU
|
||||
|
||||
|
||||
/**
|
||||
* Register: PHY_FRAME_SYNC_MEAN_H
|
||||
*/
|
||||
#define PHY_FRAME_SYNC_MEAN_H 0x00000140U
|
||||
#define PHY_FRAME_SYNC_MEAN_H_SHIFT 0
|
||||
#define PHY_FRAME_SYNC_MEAN_H_WIDTH 32
|
||||
#define PHY_FRAME_SYNC_MEAN_H_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: PHY_FRAME_SYNC_MEAN_L
|
||||
*/
|
||||
#define PHY_FRAME_SYNC_MEAN_L 0x00000144U
|
||||
#define PHY_FRAME_SYNC_MEAN_L_SHIFT 0
|
||||
#define PHY_FRAME_SYNC_MEAN_L_WIDTH 32
|
||||
#define PHY_FRAME_SYNC_MEAN_L_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: PHY_FRAME_SYNC_FREQEST
|
||||
*/
|
||||
#define PHY_FRAME_SYNC_FREQEST 0x00000148U
|
||||
#define PHY_FRAME_SYNC_FREQEST_SHIFT 0
|
||||
#define PHY_FRAME_SYNC_FREQEST_WIDTH 32
|
||||
#define PHY_FRAME_SYNC_FREQEST_MASK 0xFFFFFFFFU
|
||||
|
||||
#define PHY_FRAME_SYNC_FREQEST_CHANNEL_SHIFT 0
|
||||
#define PHY_FRAME_SYNC_FREQEST_CHANNEL_WIDTH 8
|
||||
#define PHY_FRAME_SYNC_FREQEST_CHANNEL_MASK 0x000000FFU
|
||||
|
||||
/**
|
||||
* Register: PHY_DEINTLV_AMPEST
|
||||
*/
|
||||
#define PHY_DEINTLV_AMPEST 0x0000014CU
|
||||
#define PHY_DEINTLV_AMPEST_SHIFT 0
|
||||
#define PHY_DEINTLV_AMPEST_WIDTH 16
|
||||
#define PHY_DEINTLV_AMPEST_MASK 0x0000FFFFU
|
||||
|
||||
#endif /* PHY_REG_H_ */
|
||||
|
||||
/** @} PhysicalLayer_REG_Constants*/
|
||||
|
||||
/** @} PhysicalLayer*/
|
||||
Reference in New Issue
Block a user