Common Update: Better Doxygen Style

This commit is contained in:
bit-cyber-fh
2024-03-28 00:00:59 +08:00
parent 9b416114a1
commit bab91e13df
43 changed files with 1800 additions and 1195 deletions
+35 -23
View File
@@ -1,18 +1,20 @@
/*****************************************************************************/
/**
* Description: System bus protocol head file.
* @file systembus.h
* @author FanHao ([email protected])
* @brief System bus protocol header file.
* @version 0.1
* @date 2023-05-06
*
* Date: 2023-05-06 10:12
* Last Edit Time: [2023-05-06 10:13]
*
* Revisions: Rev 0.0
* History:
* [2023-05-06]: Initial version.
*
* Copyright(c) 2021 Beijing Institute of Technology.
* @copyright Copyright(c) 2024 Beijing Institute of Technology.\n
* Lab of Communication and Network
*
******************************************************************************/
/**
* @defgroup SystemBus
* @{
*/
#ifndef __SYSTEMBUS_H_
#define __SYSTEMBUS_H_
@@ -25,26 +27,34 @@
/************************** Constant Definitions *****************************/
/************************** Data Type Definitions ****************************/
// Definition of SystemBus instance.
/**
* @struct SystemBus Config
* @brief SystemBus Config struct holds SystemBus initialization parameters
*/
typedef struct
{
uintptr_t baseAddr;
uint32_t txQueueMax;
uint32_t rxQueueMax;
uintptr_t baseAddr; ///< base address in memory
uint32_t txQueueMax; ///< maximum tx queue length
uint32_t rxQueueMax; ///< maximum rx queue length
} SYSBUS_CONFIG;
/**
* @struct SystemBus Instance
* @brief SystemBus Instance struct
*/
typedef struct
{
SYSBUS_CONFIG config;
SYSBUSLOG sysbusLog; // systembus log
LINKLOG linkLog; // Link layer log
PHYLOG phyLog; // Physical layer log
HWSTATE hwState; // Hardware status
SYSBUS_UART *uartInst;
CIRC_QUEUE *txQueue;
CIRC_QUEUE *rxQueue;
bool isRxDone;
bool isTxDone;
SYSBUS_CONFIG config; ///< SystemBus initialization parameters
SYSBUSLOG sysbusLog; ///< SystemBus log
LINKLOG linkLog; ///< Link layer log
PHYLOG phyLog; ///< Physical layer log
HWSTATE hwState; ///< Hardware status
SYSBUS_UART *uartInst; ///< physical uart controller instance
CIRC_QUEUE *txQueue; ///< tx queue
CIRC_QUEUE *rxQueue; ///< rx queue
bool isRxDone; ///< tx done indicator
bool isTxDone; ///< rx done indicator
} SYSBUS;
/************************** Function Prototypes ******************************/
@@ -64,3 +74,5 @@ bool SystemBus_IsTxBusy(SYSBUS *instPtr);
bool SystemBus_IsRxBusy(SYSBUS *instPtr);
#endif //__SYSTEMBUS_H_
/** @} SystemBus*/