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adapted to new log content definition

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This commit is contained in:
Gatsby Van
2024-02-20 13:13:57 +08:00
parent 0701eb6f43
commit c27d6fc455
3 changed files with 148 additions and 101 deletions
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df_datalink_sp/src/networking/link_layer/link_layer.c
+3 -1
View File
@@ -1249,7 +1249,9 @@ int32_t Linklayer_Proc(L2_INST *instPtr)
instPtr->linkLog.svcTxCnt = instPtr->log.svcTxCnt;
instPtr->linkLog.svcRecvCnt = instPtr->log.svcRecvCnt;
instPtr->linkLog.svcCorrectCnt = instPtr->log.svcCorrectCnt;
instPtr->linkLog.timeDev = instPtr->log.timeDev;
instPtr->linkLog.timeDev = (instPtr->log.timeDev > INT32_MAX) ?
INT32_MAX :
((instPtr->log.timeDev < INT32_MIN) ? INT32_MIN : (int32_t) instPtr->log.timeDev);
instPtr->linkLog.sendId = instPtr->serviceFSM->txLog.dataId;
instPtr->linkLog.recvId = instPtr->serviceFSM->rxLog.dataId;
df_datalink_sp/src/networking/phy_layer/phy_layer.c
+94 -66
View File
@@ -311,26 +311,28 @@ void Phy_UpdateState(PHY_INST *instPtr)
instPtr->recvSlotTime.frac_part = PhyRead(instPtr, TM_TARGET_L);
instPtr->recvFsTime.int_part = PhyRead(instPtr, FSTIME_H);
instPtr->recvFsTime.frac_part = PhyRead(instPtr, FSTIME_L);
instPtr->phyLog.acqCnt = PhyRead(instPtr, PHY_ACQ_CNT);
instPtr->phyLog.fsyncCnt = PhyRead(instPtr, PHY_FRAME_SYNC_CNT);
instPtr->phyLog.decodeCnt = PhyRead(instPtr, PHY_DECODE_CNT);
instPtr->phyLog.crcCnt = PhyRead(instPtr, PHY_CRC_OK_CNT);
instPtr->phyLog.doppler = Phy_GetFreqEst(instPtr);
instPtr->phyLog.recvStamp = (uint64_t)instPtr->recvFsTime.int_part * TIME_FRAC_MAX + instPtr->recvFsTime.frac_part;
instPtr->phyLog.acqPeak = PhyRead(instPtr, PHY_ACQ_PEAK_L);
instPtr->phyLog.acqPeak |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_PEAK_H)) << 32;
instPtr->phyLog.acqMean = PhyRead(instPtr, PHY_ACQ_MEAN_L);
instPtr->phyLog.acqMean |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_MEAN_H)) << 32;
uint64_t peak, avg;
peak = PhyRead(instPtr, PHY_ACQ_PEAK_L);
peak |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_PEAK_H)) << 32;
avg = PhyRead(instPtr, PHY_ACQ_MEAN_L);
avg |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_MEAN_H)) << 32;
instPtr->phyLog.acqPAPR = ((double)peak) / ((double)avg);
instPtr->phyLog.acqPhase = (PhyRead(instPtr, PHY_ACQ_FREQEST) & PHY_ACQ_FREQEST_PHASE_MASK) >> PHY_ACQ_FREQEST_PHASE_SHIFT;
instPtr->phyLog.acqFreqCh = (PhyRead(instPtr, PHY_ACQ_FREQEST) & PHY_ACQ_FREQEST_CHANNEL_MASK) >> PHY_ACQ_FREQEST_CHANNEL_SHIFT;
instPtr->phyLog.fsyncPeak = PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_L);
instPtr->phyLog.fsyncPeak |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_H)) << 32;
instPtr->phyLog.fsyncMean = PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_L);
instPtr->phyLog.fsyncMean |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_H)) << 32;
peak = PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_L);
peak |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_H)) << 32;
avg = PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_L);
avg |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_H)) << 32;
instPtr->phyLog.fsyncPAPR = ((double)peak) / ((double)avg);
instPtr->phyLog.fsyncFreqCh = (PhyRead(instPtr, PHY_FRAME_SYNC_FREQEST) & PHY_FRAME_SYNC_FREQEST_CHANNEL_MASK) >> PHY_FRAME_SYNC_FREQEST_CHANNEL_SHIFT;
instPtr->phyLog.deintlvAmpEst = PhyRead(instPtr, PHY_DEINTLV_AMPEST) & PHY_DEINTLV_AMPEST_MASK;
instPtr->phyLog.reserve = 0;
memset(instPtr->phyLog.reserve, 0x00, sizeof(instPtr->phyLog.reserve));
SysMonitor_UpdatePhysicalLayerLog(&(instPtr->phyLog));
}
@@ -581,7 +583,7 @@ void Phy_Halt(PHY_INST *instPtr)
int32_t Phy_SetMode(PHY_INST *instPtr, PHY_MODE modeCod)
{
ASSERT(instPtr != NULL);
uint32_t phyMainCtrl = PhyRead(instPtr, PHY_MAIN_CTRL) & ~PHY_MAIN_CTRL_MODE_MASK;
switch (modeCod)
{
@@ -710,17 +712,17 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
memcpy((uint8_t *)(antConfigAddr + i *ANT_COINFO_LEN),
dataSrcPtr, sizeof(PHY_ANT_CONFIG));
}
uint32_t antCtrl = (instPtr->antConfigOffset & ANT_CONFIG_OFFSET_MASK)
| ((hopNum << ANT_CONFIG_NUM_SHIFT) & ANT_CONFIG_NUM_MASK)
uint32_t antCtrl = (instPtr->antConfigOffset & ANT_CONFIG_OFFSET_MASK)
| ((hopNum << ANT_CONFIG_NUM_SHIFT) & ANT_CONFIG_NUM_MASK)
| ((ANT_COINFO_LEN << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK);
/*
memcpy((uint8_t*)antConfigDataAddr, hopPattern, hopNum*sizeof(uint16_t));
uint32_t antCtrl = (instPtr->antCoinfigOffset & ANT_CONFIG_OFFSET_MASK)
| ((hopNum << ANT_CONFIG_NUM_SHIFT) & ANT_CONFIG_NUM_MASK)
| ((sizeof(uint16_t) << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK);
*/
// Set antenna configs
PhyWrite(instPtr, ANT_CONFIG, antCtrl);
@@ -736,7 +738,7 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
}
// Trigger physical configuration.
// Indicate physical layer that all the configurations were done.
// Indicate physical layer that all the configurations were done.
PhyWrite(instPtr, SLOT_CMD, SLOT_CMD_KEY);
Phy_RcdShift(&(instPtr->tor), txrxMode);
@@ -837,7 +839,7 @@ double Phy_GetFreqEst(PHY_INST *instPtr)
L1_FRAME_TYPE frameType;
double coarse, fine;
frameType = Phy_GetLastRecvFrameType(instPtr);
if (frameType > L1_1M2BPS_5MS_FRAME || frameType <= L1_NONE_FRAME)
{
@@ -866,9 +868,9 @@ double Phy_GetFreqEst(PHY_INST *instPtr)
fine = 12e6/2048*((double)estAbs)/8192.0;
}
fine = ((fineReg & FINE_FREQEST_SIGN_MASK) == FINE_FREQEST_SIGN_NEG) ?
fine = ((fineReg & FINE_FREQEST_SIGN_MASK) == FINE_FREQEST_SIGN_NEG) ?
-fine : fine;
return (coarse + fine);
}
@@ -946,7 +948,7 @@ double Phy_GetFineFreqEst(PHY_INST *instPtr)
// 1.5M Rc
freqEst = 12e6/2048*((double)estAbs)/8192.0;
}
freqEst = ((regValue & FINE_FREQEST_SIGN_MASK) == FINE_FREQEST_SIGN_NEG) ?
freqEst = ((regValue & FINE_FREQEST_SIGN_MASK) == FINE_FREQEST_SIGN_NEG) ?
-freqEst : freqEst;
return freqEst;
}
@@ -1143,58 +1145,88 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
#ifndef EMULATION
float evalData;
instPtr->hwSate.isSpOk = true;
// -- Update Ps voltage, unit mV
// -- Update FPGA voltage status;
instPtr->hwSate.spFpgaVolt = 0;
rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPINT);
evalData = XAdcPs_RawToVoltage(rawData);
instPtr->hwSate.spPsVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PS_VALID(evalData);
instPtr->hwSate.spFpgaVolt |= (IS_PS_VALID(evalData)) ? VOLT_PS_OK : 0;
// -- Update Ps aux voltage, unit mV
// -- -- Update Ps aux voltage
rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPAUX);
evalData = XAdcPs_RawToVoltage(rawData);
instPtr->hwSate.spPsAuxVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PSAUX_VALID(evalData);
instPtr->hwSate.spFpgaVolt |= (IS_PSAUX_VALID(evalData)) ? VOLT_PSAUX_OK : 0;
// -- Update DDR voltage, unit mV
// -- -- Update DDR voltage
rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPDRO);
evalData = XAdcPs_RawToVoltage(rawData);
instPtr->hwSate.spDdrVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_DDR_VALID(evalData);
instPtr->hwSate.spFpgaVolt |= (IS_DDR_VALID(evalData)) ? VOLT_DDR_OK : 0;
// -- Update PL voltage, unit mV
// -- -- Update PL voltage
rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCINT);
evalData = XAdcPs_RawToVoltage(rawData);
instPtr->hwSate.spPlVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PL_VALID(evalData);
instPtr->hwSate.spFpgaVolt |= (IS_PL_VALID(evalData)) ? VOLT_PL_OK : 0;
// -- Update PL aux voltage, unit mV
// -- -- Update PL aux voltage
rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCAUX);
evalData = XAdcPs_RawToVoltage(rawData);
instPtr->hwSate.spPlAuxVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PLAUX_VALID(evalData);
instPtr->hwSate.spFpgaVolt |= (IS_PLAUX_VALID(evalData)) ? VOLT_PLAUX_OK : 0;
// -- Update Bram voltage, unit mV
// -- -- Update Bram voltage
rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VBRAM);
evalData = XAdcPs_RawToVoltage(rawData);
instPtr->hwSate.spBramVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_BRAM_VALID(evalData);
instPtr->hwSate.spFpgaVolt |= (IS_BRAM_VALID(evalData)) ? VOLT_BRAM_OK : 0;
// -- Update Chip temperature, unit 0.01 deg
// -- Update clock lock state
if (instPtr->phyCofig.get_clk_state != NULL)
{
instPtr->hwSate.spClkState = instPtr->phyCofig.get_clk_state();
}
else
{
instPtr->hwSate.spClkState = 0;
}
// -- Update AD9361 pll lock state
if (instPtr->phyCofig.get_ad_lock_state != NULL)
{
instPtr->hwSate.spAdLockState = instPtr->phyCofig.get_ad_lock_state();
}
else
{
instPtr->hwSate.spAdLockState = 0;
}
// -- Update AD9361-0 temperature, unit 1 Celcius degree
if (instPtr->phyCofig.get_ad0_temp != NULL)
{
instPtr->hwSate.spAdTemp_0 = instPtr->phyCofig.get_ad0_temp();
}
else
{
instPtr->hwSate.spAdTemp_0 = 0;
}
// -- Update AD9361-1 temperature, unit 1 Celcius degree
if (instPtr->phyCofig.get_ad1_temp != NULL)
{
instPtr->hwSate.spAdTemp_1 = instPtr->phyCofig.get_ad1_temp();
}
else
{
instPtr->hwSate.spAdTemp_1 = 0;
}
// -- Update FPGA Chip temperature, unit 1 deg
rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_TEMP);
evalData = XAdcPs_RawToTemperature(rawData);
instPtr->hwSate.spTemp = (evalData > TEMPERATURE_MAX)
? INT8_MAX
instPtr->hwSate.spFpgaTemp = (evalData > TEMPERATURE_MAX)
? INT8_MAX
: ((evalData < TEMPERATURE_MIN) ? INT8_MIN : (int8_t) round(evalData/TEMPERATURE_LSB));
instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK & VOLT_PSAUX_OK & VOLT_DDR_OK & VOLT_PL_OK & VOLT_PLAUX_OK & VOLT_BRAM_OK))
&& (instPtr->hwSate.spClkState == (CLK_SP_PLL0_LOCK & CLK_SP_PLL1_LOCK))
&& (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK && CLK_AD0_RFPLL_LOCK & CLK_AD1_BBPLL_LOCK & CLK_AD1_RFPLL_LOCK));
#else
instPtr->spPsVolt = 0;
instPtr->spPsAuxVolt = 0;
instPtr->spDdrVolt = 0;
instPtr->spPlVolt = 0;
instPtr->spPlAuxVolt = 0;
instPtr->spBramVolt = 0;
instPtr->spTemp = 0;
instPtr->isSpOk = true;
instPtr->hwSate.isSpOk = true;
#endif
/*** Voltage and Status ***/
rawData = PhyRead(instPtr, ANT_STATUS);
@@ -1203,10 +1235,10 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
// [2] - RF voltage status
// [4] - NIL voltage status
// [6] - Antenna status
instPtr->hwSate.antVolt = ((rawData & ANT_STATUS_ANT_VOLT_MASK) == ANT_STATUS_ANT_VOLT_OK) ? 0x01 : 0x00;
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_RF_VOLT_MASK) == ANT_STATUS_RF_VOLT_OK) ? 0x04 : 0x00;
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_NIL_VOLT_MASK) == ANT_STATUS_NIL_VOLT_OK) ? 0x10 : 0x00;
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_CODE_MASK) == ANT_STATUS_CODE_OK) ? 0x40 : 0x00;
instPtr->hwSate.antVolt = ((rawData & ANT_STATUS_ANT_VOLT_MASK) == ANT_STATUS_ANT_VOLT_OK) ? VOLT_ANT_PROC_OK : 0x00;
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_RF_VOLT_MASK) == ANT_STATUS_RF_VOLT_OK) ? VOLT_ANT_RF_OK : 0x00;
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_NIL_VOLT_MASK) == ANT_STATUS_NIL_VOLT_OK) ? VOLT_ANT_NIL_OK : 0x00;
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_CODE_MASK) == ANT_STATUS_CODE_OK) ? ANT_STATE_OK : 0x00;
/*** Temperature and Lock Status ***/
rawData = PhyRead(instPtr, ANT_RF_STATUS);
@@ -1216,9 +1248,9 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
// [0] - BASEBAND lock status
// [2] - PLLA lock status
// [4] - PLLB lock status
instPtr->hwSate.antPll = ((rawData & ANT_RF_STATUS_BBLOCK_MASK) == ANT_RF_STATUS_BBLOCK_OK) ? 0x01 : 0x00;
instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLA_MASK) == ANT_RF_STATUS_PLLA_OK) ? 0x04 : 0x00;
instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLB_MASK) == ANT_RF_STATUS_PLLB_OK) ? 0x10 : 0x00;
instPtr->hwSate.antPll = ((rawData & ANT_RF_STATUS_BBLOCK_MASK) == ANT_RF_STATUS_BBLOCK_OK) ? CLK_ANT_BBPLL_LOCK : 0x00;
instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLA_MASK) == ANT_RF_STATUS_PLLA_OK) ? CLK_ANT_RFPLL0_LOCK : 0x00;
instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLB_MASK) == ANT_RF_STATUS_PLLB_OK) ? CLK_ANT_RFPLL1_LOCK : 0x00;
/*** MGCs ***/
rawData = PhyRead(instPtr, ANT_RF_MGC);
@@ -1233,14 +1265,10 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
instPtr->hwSate.antMgc1 |= (rawData & ANT_RF_MGC_CH4_MASK) >> 24;
// Determin if antenna is ok.
if(instPtr->hwSate.antVolt != 0x55 //01010101
||instPtr->hwSate.antPll != 0x15) // 00010101
{
instPtr->hwSate.isSpOk = false;
}
else
{
instPtr->hwSate.isSpOk = true;
}
instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK & VOLT_ANT_RF_OK & VOLT_ANT_NIL_OK & ANT_STATE_OK))
&& (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK & CLK_ANT_RFPLL0_LOCK & CLK_ANT_RFPLL1_LOCK));
memset(instPtr->hwSate.reserve, 0x00, sizeof(instPtr->hwSate.reserve));
SysMonitor_UpdateHardwareStatus(&(instPtr->hwSate));
}