10 Commits
8 changed files with 124 additions and 99 deletions
+3
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@@ -67,6 +67,9 @@
#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR #define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR #define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
// Time Controller Configs
#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR
// System Bus Configs // System Bus Configs
//#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR //#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR
//#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR //#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
+26 -24
View File
@@ -108,7 +108,7 @@ static PHY_CONFIG phyConfig = {
}; };
TMC_CONFIG tmcConfig = { TMC_CONFIG tmcConfig = {
.baseAddr = 0, //TIME_CONTROLLER_BASEADDR, .baseAddr = TIME_CONTROLLER_BASEADDR,
.reset = 10 .reset = 10
}; };
@@ -192,7 +192,7 @@ int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
return Status; return Status;
} }
// Connect the interrupt service routine isr1 to the interrupt controller // Connect the interrupt service routine isr1 to the interrupt controller
Status = irq_register_callback(descPtr, PHY_INTR_ID, &periodicpull_callback_desc); Status = irq_register_callback(descPtr, PERIODIC_5MS_INTR_ID, &periodicpull_callback_desc);
if (Status != SUCCESS) if (Status != SUCCESS)
{ {
DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status); DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
@@ -480,26 +480,28 @@ int main(void)
Linklayer_Start(linkInstPtr); Linklayer_Start(linkInstPtr);
while (true) while (true);
{
// System bus handler // while (true)
if (SystemBus_IsReqPendding(sysbusDescPtr)) // {
{ // // System bus handler
Status = SystemBus_HandleCmd(sysbusDescPtr); // if (SystemBus_IsReqPendding(sysbusDescPtr))
if (Status != SUCCESS) // {
{ // Status = SystemBus_HandleCmd(sysbusDescPtr);
DBG_ERROR("SystemBus_HandleCmd exit with ErrorCode: %d.\n", Status); // if (Status != SUCCESS)
} // {
} // DBG_ERROR("SystemBus_HandleCmd exit with ErrorCode: %d.\n", Status);
if (SystemBus_IsRsqPendding(sysbusDescPtr) && (!SystemBus_IsTxBusy(sysbusDescPtr))) // }
{ // }
// FIXME: Required by 12 (CASC) // if (SystemBus_IsRsqPendding(sysbusDescPtr) && (!SystemBus_IsTxBusy(sysbusDescPtr)))
udelay(200); // {
Status = SystemBus_MakeResp(sysbusDescPtr); // // FIXME: Required by 12 (CASC)
if (Status != SUCCESS) // udelay(200);
{ // Status = SystemBus_MakeResp(sysbusDescPtr);
DBG_ERROR("SystemBus_HandleCmd exit with ErrorCode: %d.\n", Status); // if (Status != SUCCESS)
} // {
} // DBG_ERROR("SystemBus_HandleCmd exit with ErrorCode: %d.\n", Status);
} // }
// }
// }
} // main } // main
+3
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@@ -67,6 +67,9 @@
#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR #define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR #define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
// Time Controller Configs
#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR
// System Bus Configs // System Bus Configs
#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR #define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR
#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR #define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
+2 -2
View File
@@ -104,7 +104,7 @@ static PHY_CONFIG phyConfig = {
}; };
TMC_CONFIG tmcConfig = { TMC_CONFIG tmcConfig = {
.baseAddr = 0, //TIME_CONTROLLER_BASEADDR, .baseAddr = TIME_CONTROLLER_BASEADDR,
.reset = 10 .reset = 10
}; };
@@ -193,7 +193,7 @@ int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
return Status; return Status;
} }
// Connect the interrupt service routine isr1 to the interrupt controller // Connect the interrupt service routine isr1 to the interrupt controller
Status = irq_register_callback(descPtr, PHY_INTR_ID, &periodicpull_callback_desc); Status = irq_register_callback(descPtr, PERIODIC_5MS_INTR_ID, &periodicpull_callback_desc);
if (Status != SUCCESS) if (Status != SUCCESS)
{ {
DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status); DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
@@ -99,8 +99,8 @@ L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
{L2_SLOT_ADVERTISE, 0x01, 0x01, 0xFF}, {L2_SLOT_ADVERTISE, 0x01, 0x01, 0xFF},
{L2_SLOT_ADVERTISE, 0x02, 0x01, 0xFF}, {L2_SLOT_ADVERTISE, 0x02, 0x01, 0xFF},
{L2_SLOT_ADVERTISE, 0x03, 0x01, 0xFF}, {L2_SLOT_ADVERTISE, 0x03, 0x01, 0xFF},
{L2_SLOT_IDLE, 0x00}, {L2_SLOT_IDLE, 0x00, 0x00, 0x00},
{L2_SLOT_IDLE, 0x00}, {L2_SLOT_IDLE, 0x00, 0x00, 0x00},
// SubFrame 4 // SubFrame 4
{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF}, {L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF}, {L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
@@ -26,7 +26,9 @@
/************************** Constant Definitions *****************************/ /************************** Constant Definitions *****************************/
#define ADV_LISTEN_TIMEOUT 40 #define ADV_LISTEN_TIMEOUT 40
#define CFM_LISTEN_TIMEOUT 40 #define CFM_LISTEN_TIMEOUT 25
#define ADV_FRAME_SLOTS 4
#define CFM_FRAME_SLOTS 4
/***************** Macros (In-line Functions) Definitions *********************/ /***************** Macros (In-line Functions) Definitions *********************/
/**************************** Type Definitions *******************************/ /**************************** Type Definitions *******************************/
@@ -193,15 +195,16 @@ static int32_t Scan_CfmHandler(L2_INST *instPtr)
{ {
DBG_WARNING("Cmf timeout, restart net scan from L2_SCAN_INIT_STAGE.\n"); DBG_WARNING("Cmf timeout, restart net scan from L2_SCAN_INIT_STAGE.\n");
L2_Scan_Reset(scanFsmPtr); L2_Scan_Reset(scanFsmPtr);
return SUCCESS;
} }
else if (L2_GetNextSlotNum(instPtr) % CFM_FRAME_SLOTS == 0)
{ {
scanFsmPtr->cfmTimeout++; // increase counter.
}
// using pull mode to receive confirm frame // using pull mode to receive confirm frame
// since first time sync procedure is accomplished in BM stage. // since first time sync procedure is accomplished in ADV stage.
Phy_SetMode(instPtr->config.phyInstPtr, PHY_MODE_PULL); Phy_SetMode(instPtr->config.phyInstPtr, PHY_MODE_PULL);
L2_SetupNextSlot(instPtr, L2_TOR_RX, L2_CFM_FRAME); L2_SetupNextSlot(instPtr, L2_TOR_RX, L2_CFM_FRAME);
scanFsmPtr->cfmTimeout++; // increase counter.
}
return SUCCESS; return SUCCESS;
} }
@@ -403,6 +406,9 @@ int32_t L2_Scan_PktHandler(L2_INST *instPtr, uint8_t *msg)
L2_FrameGetChunk(msg, L2_MSG_ADV_SRC_POSZ, L2_MSG_ADV_SRC_POSZ_LEN, &nodePos); L2_FrameGetChunk(msg, L2_MSG_ADV_SRC_POSZ, L2_MSG_ADV_SRC_POSZ_LEN, &nodePos);
node->nodeInfo.pos.z = (double) nodePos; node->nodeInfo.pos.z = (double) nodePos;
// Reset node ttl
node->ttlCnt = 0;
if (L2_isCxn2Net(instPtr) == false) if (L2_isCxn2Net(instPtr) == false)
{ {
uint32_t netstartTime, frameNum, slotNum = 0; uint32_t netstartTime, frameNum, slotNum = 0;
@@ -456,6 +462,9 @@ int32_t L2_Scan_PktHandler(L2_INST *instPtr, uint8_t *msg)
L2_FrameGetChunk(msg, L2_MSG_CFM_SRC_SPEEDZ, L2_MSG_CFM_SRC_SPEEDZ_LEN, &nodeSpeed); L2_FrameGetChunk(msg, L2_MSG_CFM_SRC_SPEEDZ, L2_MSG_CFM_SRC_SPEEDZ_LEN, &nodeSpeed);
node->nodeInfo.speed.z = (double) nodePos; node->nodeInfo.speed.z = (double) nodePos;
// Reset node ttl
node->ttlCnt = 0;
if (L2_GetNodeType(instPtr) != L2_NODE_HEAD) if (L2_GetNodeType(instPtr) != L2_NODE_HEAD)
{ {
// check if net setup finished. // check if net setup finished.
@@ -255,6 +255,9 @@ int32_t L2_Service_PktHandler(L2_INST *instPtr, uint8_t *msg)
L2_FrameGetChunk(msg, L2_MSG_SVC_SRC_SPEEDZ, L2_MSG_SVC_SRC_SPEEDZ_LEN, &nodeSpeed); L2_FrameGetChunk(msg, L2_MSG_SVC_SRC_SPEEDZ, L2_MSG_SVC_SRC_SPEEDZ_LEN, &nodeSpeed);
node->nodeInfo.speed.z = (double) nodePos; node->nodeInfo.speed.z = (double) nodePos;
// Reset node ttl
node->ttlCnt = 0;
if(L2_GetNodeType(instPtr) == L2_NODE_HEAD) if(L2_GetNodeType(instPtr) == L2_NODE_HEAD)
{ {
SysMonitor_UpdateRecvPayloadLJRaw(msg+L2_MSG_SVC_PAYLOAD); SysMonitor_UpdateRecvPayloadLJRaw(msg+L2_MSG_SVC_PAYLOAD);
@@ -629,7 +629,7 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
hopPattern = hopPattern_10KBPS_20MS; hopPattern = hopPattern_10KBPS_20MS;
break; break;
case L1_40KBPS_20MS_FRAME: case L1_40KBPS_20MS_FRAME:
phyModeCtrl |= PHY_MODE_CTRL_FRAME_200KBPS_5MS; phyModeCtrl |= PHY_MODE_CTRL_FRAME_40KBPS_20MS;
hopNum = L1_FRAME_200KBPS_5MS_HOPS; hopNum = L1_FRAME_200KBPS_5MS_HOPS;
hopPattern = hopPattern_200KBPS_5MS; hopPattern = hopPattern_200KBPS_5MS;
break; break;
@@ -654,6 +654,9 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
} }
} }
// Set frame configs
PhyWrite(instPtr, PHY_MODE_CTRL, phyModeCtrl);
// TODO: Set antenna stand by, when suspend. // TODO: Set antenna stand by, when suspend.
const uint8_t *dataSrcPtr = (uint8_t *)(&(instPtr->antConfig)); const uint8_t *dataSrcPtr = (uint8_t *)(&(instPtr->antConfig));
for (int32_t i = 0; i < hopNum; i++) for (int32_t i = 0; i < hopNum; i++)
@@ -676,10 +679,12 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
| ((sizeof(uint16_t) << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK); | ((sizeof(uint16_t) << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK);
*/ */
// Set antenna configs
PhyWrite(instPtr, ANT_CONFIG, antCtrl); PhyWrite(instPtr, ANT_CONFIG, antCtrl);
if (txrxMode == PHY_TOR_TX) if (txrxMode == PHY_TOR_TX)
{ {
// Set data to be sent
Status = Phy_SetSendData(instPtr, frameType, dataBuff); Status = Phy_SetSendData(instPtr, frameType, dataBuff);
if (Status != SUCCESS) if (Status != SUCCESS)
{ {