Compare commits
10
Commits
| Author | SHA1 | Date | |
|---|---|---|---|
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b5f920b4f3 | ||
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5afe87e5c1 | ||
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2cb5fae3f2 | ||
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3613b4a4b7 | ||
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38359c72b6 | ||
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00d568e6e7 | ||
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9ecaf92011 | ||
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de5f628ef6 | ||
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fea9795b5a | ||
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49a934e3d4 |
@@ -67,6 +67,9 @@
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|||||||
#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
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#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
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||||||
#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
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#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
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// Time Controller Configs
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#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR
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// System Bus Configs
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// System Bus Configs
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//#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR
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//#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR
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//#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
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//#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
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+90
-88
@@ -108,7 +108,7 @@ static PHY_CONFIG phyConfig = {
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};
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};
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TMC_CONFIG tmcConfig = {
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TMC_CONFIG tmcConfig = {
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.baseAddr = 0, //TIME_CONTROLLER_BASEADDR,
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.baseAddr = TIME_CONTROLLER_BASEADDR,
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.reset = 10
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.reset = 10
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};
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};
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@@ -192,7 +192,7 @@ int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
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return Status;
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return Status;
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}
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}
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// Connect the interrupt service routine isr1 to the interrupt controller
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// Connect the interrupt service routine isr1 to the interrupt controller
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Status = irq_register_callback(descPtr, PHY_INTR_ID, &periodicpull_callback_desc);
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Status = irq_register_callback(descPtr, PERIODIC_5MS_INTR_ID, &periodicpull_callback_desc);
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if (Status != SUCCESS)
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if (Status != SUCCESS)
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{
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{
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DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
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DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
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@@ -407,99 +407,101 @@ int main(void)
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}
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}
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// Init time controller
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// Init time controller
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Status = TimeCtrl_Init(&tmcInstPtr, &tmcConfig);
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Status = TimeCtrl_Init(&tmcInstPtr, &tmcConfig);
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if (Status == SUCCESS)
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if (Status == SUCCESS)
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{
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{
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DBG_PRINT("TmcCtrl Init SUCCESS! \n");
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DBG_PRINT("TmcCtrl Init SUCCESS! \n");
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}
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}
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else
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else
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{
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{
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DBG_PRINT("TmcCtrl Init FAILED! \n");
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DBG_PRINT("TmcCtrl Init FAILED! \n");
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return Status;
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return Status;
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}
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}
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/* Physical Layer Initialize */
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/* Physical Layer Initialize */
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Status = Phy_InstInit(&phyInstPtr, &phyConfig);
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Status = Phy_InstInit(&phyInstPtr, &phyConfig);
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if (Status == SUCCESS)
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if (Status == SUCCESS)
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{
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{
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DBG_PRINT("Physical layer Init SUCCESS! \n");
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DBG_PRINT("Physical layer Init SUCCESS! \n");
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}
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}
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else
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else
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{
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{
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DBG_PRINT("Physical layer FAILED! \n");
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DBG_PRINT("Physical layer FAILED! \n");
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return Status;
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return Status;
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}
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}
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/* Link Layer Initialize */
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/* Link Layer Initialize */
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linkConfig.phyInstPtr = phyInstPtr;
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linkConfig.phyInstPtr = phyInstPtr;
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linkConfig.tmcInstPtr = tmcInstPtr;
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linkConfig.tmcInstPtr = tmcInstPtr;
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Status = Linklayer_Init(&linkInstPtr, &linkConfig);
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Status = Linklayer_Init(&linkInstPtr, &linkConfig);
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if (Status == SUCCESS)
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if (Status == SUCCESS)
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{
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{
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DBG_PRINT("LinkLayer Init SUCCESS! \n");
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DBG_PRINT("LinkLayer Init SUCCESS! \n");
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}
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}
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else
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else
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{
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{
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DBG_PRINT("Linklayer Init FAILED! \n");
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DBG_PRINT("Linklayer Init FAILED! \n");
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return Status;
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return Status;
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}
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}
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// /* System Bus Initialize */
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// /* System Bus Initialize */
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// Status = SystemBus_Init(&sysbusDescPtr, &sysbusConfig);
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// Status = SystemBus_Init(&sysbusDescPtr, &sysbusConfig);
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// if (Status != SUCCESS)
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// if (Status != SUCCESS)
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// {
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// {
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// DBG_ERROR("Systembus init FAILED, with error code: %d\n", Status);
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// DBG_ERROR("Systembus init FAILED, with error code: %d\n", Status);
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// return Status;
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// return Status;
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// }
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// }
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/* System Monitor log timer Initialize */
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/* System Monitor log timer Initialize */
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Status = timer_init(&logTmPtr, &scutimer_init_param);
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Status = timer_init(&logTmPtr, &scutimer_init_param);
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if (Status != SUCCESS)
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if (Status != SUCCESS)
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{
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{
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DBG_ERROR("SCU Timer init FAILED, with error code: %d\n", Status);
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DBG_ERROR("SCU Timer init FAILED, with error code: %d\n", Status);
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return Status;
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return Status;
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}
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}
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/* interrupts Initialize */
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/* interrupts Initialize */
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Status = SetupInterruptSystem(intcDescPtr);
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Status = SetupInterruptSystem(intcDescPtr);
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if (Status == SUCCESS)
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if (Status == SUCCESS)
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{
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{
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DBG_INFO("Interrupt system setup SUCCESS!\n");
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DBG_INFO("Interrupt system setup SUCCESS!\n");
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}
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}
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else
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else
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{
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{
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DBG_ERROR("Interrupt system setup FAILED, ErrorCode: %d.\n", Status);
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DBG_ERROR("Interrupt system setup FAILED, ErrorCode: %d.\n", Status);
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return Status;
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return Status;
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}
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}
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// Start System Monitor logging.
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// Start System Monitor logging.
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timer_start(logTmPtr);
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timer_start(logTmPtr);
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DBG_PRINT("Physical started...\n");
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DBG_PRINT("Physical started...\n");
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Phy_Start(phyInstPtr);
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Phy_Start(phyInstPtr);
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Linklayer_Start(linkInstPtr);
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Linklayer_Start(linkInstPtr);
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while (true)
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while (true);
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{
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// System bus handler
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// while (true)
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if (SystemBus_IsReqPendding(sysbusDescPtr))
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// {
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{
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// // System bus handler
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Status = SystemBus_HandleCmd(sysbusDescPtr);
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// if (SystemBus_IsReqPendding(sysbusDescPtr))
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if (Status != SUCCESS)
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// {
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{
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// Status = SystemBus_HandleCmd(sysbusDescPtr);
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DBG_ERROR("SystemBus_HandleCmd exit with ErrorCode: %d.\n", Status);
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// if (Status != SUCCESS)
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}
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// {
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}
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// DBG_ERROR("SystemBus_HandleCmd exit with ErrorCode: %d.\n", Status);
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if (SystemBus_IsRsqPendding(sysbusDescPtr) && (!SystemBus_IsTxBusy(sysbusDescPtr)))
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// }
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{
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// }
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// FIXME: Required by 12 (CASC)
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// if (SystemBus_IsRsqPendding(sysbusDescPtr) && (!SystemBus_IsTxBusy(sysbusDescPtr)))
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udelay(200);
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// {
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Status = SystemBus_MakeResp(sysbusDescPtr);
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// // FIXME: Required by 12 (CASC)
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if (Status != SUCCESS)
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// udelay(200);
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{
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// Status = SystemBus_MakeResp(sysbusDescPtr);
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DBG_ERROR("SystemBus_HandleCmd exit with ErrorCode: %d.\n", Status);
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// if (Status != SUCCESS)
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}
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// {
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}
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// DBG_ERROR("SystemBus_HandleCmd exit with ErrorCode: %d.\n", Status);
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}
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// }
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// }
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// }
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} // main
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} // main
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@@ -67,6 +67,9 @@
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#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
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#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
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#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
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#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
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// Time Controller Configs
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#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR
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// System Bus Configs
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// System Bus Configs
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#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR
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#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR
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#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
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#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
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||||||
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@@ -104,7 +104,7 @@ static PHY_CONFIG phyConfig = {
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};
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};
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TMC_CONFIG tmcConfig = {
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TMC_CONFIG tmcConfig = {
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.baseAddr = 0, //TIME_CONTROLLER_BASEADDR,
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.baseAddr = TIME_CONTROLLER_BASEADDR,
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.reset = 10
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.reset = 10
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};
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};
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@@ -193,7 +193,7 @@ int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
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return Status;
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return Status;
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}
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}
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// Connect the interrupt service routine isr1 to the interrupt controller
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// Connect the interrupt service routine isr1 to the interrupt controller
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Status = irq_register_callback(descPtr, PHY_INTR_ID, &periodicpull_callback_desc);
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Status = irq_register_callback(descPtr, PERIODIC_5MS_INTR_ID, &periodicpull_callback_desc);
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if (Status != SUCCESS)
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if (Status != SUCCESS)
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{
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{
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DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
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DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %ld.\n", Status);
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@@ -99,8 +99,8 @@ L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
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{L2_SLOT_ADVERTISE, 0x01, 0x01, 0xFF},
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{L2_SLOT_ADVERTISE, 0x01, 0x01, 0xFF},
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{L2_SLOT_ADVERTISE, 0x02, 0x01, 0xFF},
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{L2_SLOT_ADVERTISE, 0x02, 0x01, 0xFF},
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{L2_SLOT_ADVERTISE, 0x03, 0x01, 0xFF},
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{L2_SLOT_ADVERTISE, 0x03, 0x01, 0xFF},
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{L2_SLOT_IDLE, 0x00},
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{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
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{L2_SLOT_IDLE, 0x00},
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{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
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// SubFrame 4
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// SubFrame 4
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{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
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{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
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{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
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{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
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@@ -26,7 +26,9 @@
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/************************** Constant Definitions *****************************/
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/************************** Constant Definitions *****************************/
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#define ADV_LISTEN_TIMEOUT 40
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#define ADV_LISTEN_TIMEOUT 40
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#define CFM_LISTEN_TIMEOUT 40
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#define CFM_LISTEN_TIMEOUT 25
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#define ADV_FRAME_SLOTS 4
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#define CFM_FRAME_SLOTS 4
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/***************** Macros (In-line Functions) Definitions *********************/
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/***************** Macros (In-line Functions) Definitions *********************/
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/**************************** Type Definitions *******************************/
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/**************************** Type Definitions *******************************/
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@@ -193,15 +195,16 @@ static int32_t Scan_CfmHandler(L2_INST *instPtr)
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{
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{
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DBG_WARNING("Cmf timeout, restart net scan from L2_SCAN_INIT_STAGE.\n");
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DBG_WARNING("Cmf timeout, restart net scan from L2_SCAN_INIT_STAGE.\n");
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L2_Scan_Reset(scanFsmPtr);
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L2_Scan_Reset(scanFsmPtr);
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return SUCCESS;
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}
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}
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else
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if (L2_GetNextSlotNum(instPtr) % CFM_FRAME_SLOTS == 0)
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{
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{
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||||||
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// using pull mode to receive confirm frame
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||||||
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// since first time sync procedure is accomplished in ADV stage.
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Phy_SetMode(instPtr->config.phyInstPtr, PHY_MODE_PULL);
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L2_SetupNextSlot(instPtr, L2_TOR_RX, L2_CFM_FRAME);
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scanFsmPtr->cfmTimeout++; // increase counter.
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scanFsmPtr->cfmTimeout++; // increase counter.
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||||||
}
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}
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// using pull mode to receive confirm frame
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// since first time sync procedure is accomplished in BM stage.
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Phy_SetMode(instPtr->config.phyInstPtr, PHY_MODE_PULL);
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L2_SetupNextSlot(instPtr, L2_TOR_RX, L2_CFM_FRAME);
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return SUCCESS;
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return SUCCESS;
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}
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}
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||||||
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||||||
@@ -403,6 +406,9 @@ int32_t L2_Scan_PktHandler(L2_INST *instPtr, uint8_t *msg)
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L2_FrameGetChunk(msg, L2_MSG_ADV_SRC_POSZ, L2_MSG_ADV_SRC_POSZ_LEN, &nodePos);
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L2_FrameGetChunk(msg, L2_MSG_ADV_SRC_POSZ, L2_MSG_ADV_SRC_POSZ_LEN, &nodePos);
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||||||
node->nodeInfo.pos.z = (double) nodePos;
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node->nodeInfo.pos.z = (double) nodePos;
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||||||
|
|
||||||
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// Reset node ttl
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||||||
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node->ttlCnt = 0;
|
||||||
|
|
||||||
if (L2_isCxn2Net(instPtr) == false)
|
if (L2_isCxn2Net(instPtr) == false)
|
||||||
{
|
{
|
||||||
uint32_t netstartTime, frameNum, slotNum = 0;
|
uint32_t netstartTime, frameNum, slotNum = 0;
|
||||||
@@ -456,6 +462,9 @@ int32_t L2_Scan_PktHandler(L2_INST *instPtr, uint8_t *msg)
|
|||||||
L2_FrameGetChunk(msg, L2_MSG_CFM_SRC_SPEEDZ, L2_MSG_CFM_SRC_SPEEDZ_LEN, &nodeSpeed);
|
L2_FrameGetChunk(msg, L2_MSG_CFM_SRC_SPEEDZ, L2_MSG_CFM_SRC_SPEEDZ_LEN, &nodeSpeed);
|
||||||
node->nodeInfo.speed.z = (double) nodePos;
|
node->nodeInfo.speed.z = (double) nodePos;
|
||||||
|
|
||||||
|
// Reset node ttl
|
||||||
|
node->ttlCnt = 0;
|
||||||
|
|
||||||
if (L2_GetNodeType(instPtr) != L2_NODE_HEAD)
|
if (L2_GetNodeType(instPtr) != L2_NODE_HEAD)
|
||||||
{
|
{
|
||||||
// check if net setup finished.
|
// check if net setup finished.
|
||||||
|
|||||||
@@ -255,6 +255,9 @@ int32_t L2_Service_PktHandler(L2_INST *instPtr, uint8_t *msg)
|
|||||||
L2_FrameGetChunk(msg, L2_MSG_SVC_SRC_SPEEDZ, L2_MSG_SVC_SRC_SPEEDZ_LEN, &nodeSpeed);
|
L2_FrameGetChunk(msg, L2_MSG_SVC_SRC_SPEEDZ, L2_MSG_SVC_SRC_SPEEDZ_LEN, &nodeSpeed);
|
||||||
node->nodeInfo.speed.z = (double) nodePos;
|
node->nodeInfo.speed.z = (double) nodePos;
|
||||||
|
|
||||||
|
// Reset node ttl
|
||||||
|
node->ttlCnt = 0;
|
||||||
|
|
||||||
if(L2_GetNodeType(instPtr) == L2_NODE_HEAD)
|
if(L2_GetNodeType(instPtr) == L2_NODE_HEAD)
|
||||||
{
|
{
|
||||||
SysMonitor_UpdateRecvPayloadLJRaw(msg+L2_MSG_SVC_PAYLOAD);
|
SysMonitor_UpdateRecvPayloadLJRaw(msg+L2_MSG_SVC_PAYLOAD);
|
||||||
|
|||||||
@@ -629,7 +629,7 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
|
|||||||
hopPattern = hopPattern_10KBPS_20MS;
|
hopPattern = hopPattern_10KBPS_20MS;
|
||||||
break;
|
break;
|
||||||
case L1_40KBPS_20MS_FRAME:
|
case L1_40KBPS_20MS_FRAME:
|
||||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_200KBPS_5MS;
|
phyModeCtrl |= PHY_MODE_CTRL_FRAME_40KBPS_20MS;
|
||||||
hopNum = L1_FRAME_200KBPS_5MS_HOPS;
|
hopNum = L1_FRAME_200KBPS_5MS_HOPS;
|
||||||
hopPattern = hopPattern_200KBPS_5MS;
|
hopPattern = hopPattern_200KBPS_5MS;
|
||||||
break;
|
break;
|
||||||
@@ -654,6 +654,9 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// Set frame configs
|
||||||
|
PhyWrite(instPtr, PHY_MODE_CTRL, phyModeCtrl);
|
||||||
|
|
||||||
// TODO: Set antenna stand by, when suspend.
|
// TODO: Set antenna stand by, when suspend.
|
||||||
const uint8_t *dataSrcPtr = (uint8_t *)(&(instPtr->antConfig));
|
const uint8_t *dataSrcPtr = (uint8_t *)(&(instPtr->antConfig));
|
||||||
for (int32_t i = 0; i < hopNum; i++)
|
for (int32_t i = 0; i < hopNum; i++)
|
||||||
@@ -676,10 +679,12 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
|
|||||||
| ((sizeof(uint16_t) << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK);
|
| ((sizeof(uint16_t) << ANT_CONFIG_LEN_SHIFT) & ANT_CONFIG_LEN_MASK);
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
// Set antenna configs
|
||||||
PhyWrite(instPtr, ANT_CONFIG, antCtrl);
|
PhyWrite(instPtr, ANT_CONFIG, antCtrl);
|
||||||
|
|
||||||
if (txrxMode == PHY_TOR_TX)
|
if (txrxMode == PHY_TOR_TX)
|
||||||
{
|
{
|
||||||
|
// Set data to be sent
|
||||||
Status = Phy_SetSendData(instPtr, frameType, dataBuff);
|
Status = Phy_SetSendData(instPtr, frameType, dataBuff);
|
||||||
if (Status != SUCCESS)
|
if (Status != SUCCESS)
|
||||||
{
|
{
|
||||||
|
|||||||
Reference in New Issue
Block a user