make compatible withe BSD sed

df_datalink_ge/src/config/app_config.h

@@ -93,9 +93,6 @@
 #if !defined(DATALINK_ENABLE_AUTOTIMESYNC)
 	#warning To enbale bit error rate test, auto time-sync should be enabled...
 #endif
-#if defined(DATALINK_ENABLE_AUTORECONNECT)
-	#error Do not support auto reconnnect in bit error rate test mode...
-#endif
 #endif
 
 #endif

df_datalink_ge/src/hardware/headless.h

@@ -1,7 +1,7 @@
 /*
  * headless.h
  *
- *  Created on: 2021Äê6ÔÂ8ÈÕ
+ *  Created on: 2021��6��8��
  *      Author: Josh
  */
 
@@ -30,7 +30,8 @@
 /**************************** Type Definitions *******************************/
 
 /***************** Macros (Inline Functions) Definitions *********************/
-
+#define HW_PRINT(...)  __asm__("nop")
+// #define HW_PRINT(...)  printf(__VA_ARGS__)
 /************************** Variable Definitions *****************************/
 
 /************************** Function Prototypes ******************************/

df_datalink_ge/src/main.c

@@ -51,33 +51,39 @@ void ScuTimer_IntrHandler(void *context);
 void Systembus_RxIntrHandler(void *context);
 void Systembus_TxIntrHandler(void *context);
 /************************** Constant Definitions *****************************/
-struct callback_desc phy_callback_desc = {
+struct callback_desc phy_callback_desc =
+{
 	.callback = Phy_IntrHandler,
 	.ctx = NULL
 };
 
-struct callback_desc periodicpull_callback_desc = {
+struct callback_desc periodicpull_callback_desc =
+{
 	.callback = PeriodicPull_Handler,
 	.ctx = NULL
 };
 
 
-struct callback_desc sysbus_rx_callback_desc = {
+struct callback_desc sysbus_rx_callback_desc =
+{
 	.callback = Systembus_RxIntrHandler,
 	.ctx = NULL
 };
 
-struct callback_desc sysbus_tx_callback_desc = {
+struct callback_desc sysbus_tx_callback_desc =
+{
 	.callback = Systembus_TxIntrHandler,
 	.ctx = NULL
 };
 
-struct callback_desc scutm_callback_desc = {
+struct callback_desc scutm_callback_desc =
+{
 	.callback = ScuTimer_IntrHandler,
 	.ctx = NULL
 };
 
-L2_CONFIG linkConfig = {
+L2_CONFIG linkConfig =
+{
 	.myType = L2_NODE_HEAD,
 	.clustId = 1,
 	.myId = 1,
@@ -99,16 +105,22 @@ L2_CONFIG linkConfig = {
 // 	.tmcInstPtr = NULL
 // };
 
-static PHY_CONFIG phyConfig = {
+static PHY_CONFIG phyConfig =
+{
 	.devId = 0,
 	.baseAddr = PHY_BASEADDR,
 	.antBramId = PHY_ANTCONFIG_BRAM_DEVICE_ID,
 	.txBramId = PHY_TXBUFF_BRAM_DEVICE_ID,
 	.rxBramId = PHY_RXBUFF_BRAM_DEVICE_ID,
-	.hwXadcId = PHY_HW_XADC_DEVICE_ID
+	.hwXadcId = PHY_HW_XADC_DEVICE_ID,
+	.get_clk_state = NULL,
+	.get_ad_lock_state = NULL,
+	.get_ad0_temp = NULL,
+	.get_ad1_temp = NULL
 };
 
-TMC_CONFIG tmcConfig = {
+TMC_CONFIG tmcConfig =
+{
 	.baseAddr = TIME_CONTROLLER_BASEADDR,
 	.reset = 10
 };
@@ -359,8 +371,8 @@ void ScuTimer_IntrHandler(void *context)
 	xdesc = (struct xil_timer_desc *)(logTmPtr->extra);
 	if (XScuTimer_IsExpired((XScuTimer *)xdesc->instance))
 	{
-		// Update log
-		Phy_UpdateHwSate(phyInstPtr);
+		// Refresh log
+		Phy_RefreshHwSate(phyInstPtr);
 		XScuTimer_ClearInterruptStatus((XScuTimer *)xdesc->instance);
 	}
 	else

df_datalink_sp/build/src/subdir.mk

@@ -8,15 +8,18 @@ LD_SRCS += \
 
 C_SRCS += \
 ../src/main.c \
-../src/system_monitor.c 
+../src/system_monitor.c \
+../src/hwconfig.c
 
 OBJS += \
 ./src/main.o \
-./src/system_monitor.o 
+./src/system_monitor.o \
+./src/hwconfig.o
 
 C_DEPS += \
 ./src/main.d \
-./src/system_monitor.d 
+./src/system_monitor.d \
+./src/hwconfig.d
 
 
 # Each subdirectory must supply rules for building sources it contributes

df_datalink_sp/src/config/app_config.h

@@ -190,9 +190,6 @@ typedef enum
 #if !defined(DATALINK_ENABLE_AUTOTIMESYNC)
 	#warning To enbale bit error rate test, auto time-sync should be enabled...
 #endif
-#if defined(DATALINK_ENABLE_AUTORECONNECT)
-	#error Do not support auto reconnnect in bit error rate test mode...
-#endif
 #endif
 
 #endif //__APP_CONFIG_H_

df_datalink_sp/src/hwconfig.c

@@ -0,0 +1,464 @@
+/*****************************************************************************/
+/**
+ * Description: hwconfig.h
+ *
+
+ * Date: 2024-02-20 13:19
+ * Last Edit Time: [2024-02-20 13:19]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2023-05-07]: Initial edition.
+ *
+ * Copyright(c) 2024 Beijing Institute of Technology.
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+// Standard
+#include <stdint.h>
+#include <stdbool.h>
+// Xilinx
+#include "xgpiops.h"
+#include "drivers/rf-transceiver/ad9361_reg/ad9361_reg.h"
+#include "drivers/rf-transceiver/ad9361/ad9361_api.h"
+#include "drivers/axi_core/spi_engine/spi_engine.h"
+// App
+#include "common.h"
+#include "error.h"
+#include "delay.h"
+#include "system_monitor.h"
+#include "hwconfig.h"
+#include "config/app_config.h"
+#include "dev_profile/dev_profile.h"
+
+/************************** Function Prototypes ******************************/
+/*********************** Driver Instance Definitions **************************/
+static struct hmc7044_dev *hmc7044_inst;
+static struct ad9361_reg_dev *ad9361_1_reg_inst;
+static struct ad9361_reg_dev *ad9361_2_reg_inst;
+// static struct ad9361_rf_phy *ad9361_phy;
+// static struct ad9361_rf_phy *ad9361_2_phy;
+
+/*****************************************************************************/
+/**
+ * @brief   Hardware_Init
+ *
+ * @param   none.
+ *
+ * @return  None.
+ *
+ ******************************************************************************/
+int32_t Hardware_Init(void)
+{
+	int32_t Status;
+	XGpioPs Gpio;
+	XGpioPs_Config *ConfigPtr;
+	ConfigPtr = XGpioPs_LookupConfig(AD9361_GPIO_DEVICE_ID);
+	Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
+	if (Status != SUCCESS)
+	{
+		return FAILURE;
+	}
+
+	/**********************************************************/
+	/****************** HMC7044 Configuration *****************/
+	/**********************************************************/
+	Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("hmc7044_init() error: %" PRId32 "\n", Status);
+		return FAILURE;
+	}
+
+	/**********************************************************/
+	/***************** AD9361-1 Configuration *****************/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, AD9361_GPIO_OUTPUT);
+
+	ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param);
+	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0);
+	ad9361_reg_config(ad9361_1_reg_inst);
+	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1);
+
+	//	Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param);
+	//	if (Status != XST_SUCCESS){
+	//		return XST_FAILURE;
+	//	}else{
+	//		printf("Configurate AD9361 Completely!\n");
+	//	}
+	//	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
+	//	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
+
+	/**********************************************************/
+	/***************** AD9361-2 Configuration *****************/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, AD9361_GPIO_OUTPUT);
+
+	ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param);
+	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0);
+	ad9361_reg_config(ad9361_2_reg_inst);
+	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1);
+
+	//	uint8_t rd_back;
+	//	Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
+	//	Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);
+
+	/**********************************************************/
+	/******* AD9361 Baseband Multichip Synchronization ********/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, AD9361_GPIO_OUTPUT);
+
+	// SYNC BBPLL and DIGITAL SAMPLING CLOCKS
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
+	mdelay(20);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin
+	mdelay(500);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
+	mdelay(2000);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin
+	mdelay(500);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08);
+
+	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
+	mdelay(20);
+	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1);
+	mdelay(20);
+	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
+
+	/**********************************************************/
+	/********* AD9361 Multichip Rx Phase Calibration **********/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, AD9361_GPIO_INPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, AD9361_GPIO_INPUT);
+
+	// switch to lower frequency
+	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
+	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1);
+	mdelay(20);
+
+	// switch rx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30);
+	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30);
+
+	// enable dual ad9361 tx channels
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels
+
+	// switch ad9361 tx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
+	mdelay(20);
+
+	// begin to calibrate the 1st ad9361
+	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
+	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1);
+	mdelay(1);
+	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
+
+	// read calibration status
+	int32_t time_out_cnt = 0;
+	do
+	{
+		mdelay(1); // Wait 1ms
+		time_out_cnt++;
+	} while (((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
+
+	if (time_out_cnt == AD9361_TIMEOUT_TH)
+	{
+		return FAILURE;
+	}
+
+	// begin to calibrate the 2nd ad9361
+	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1);
+	mdelay(1);
+	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0);
+
+	// read calibration status
+	time_out_cnt = 0;
+	do
+	{
+		mdelay(1); // Wait 1ms
+		time_out_cnt++;
+	} while (((XGpioPs_ReadPin(&Gpio, AD9361_2_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
+
+	if (time_out_cnt == AD9361_TIMEOUT_TH)
+	{
+		return FAILURE;
+	}
+
+	// enable single ad9361 tx channels
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
+
+	// switch ad9361 tx & rx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03);
+	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03);
+
+	// switch to higher frequency
+	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
+	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0);
+
+	DBG_PRINT("Done.\n");
+
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Hardware_SwitchFreq
+ *
+ * @param   devSysMonitor_UpdateHardwareStatus(newHwState);
+ * @param   freq
+ *
+ * @return  None.
+ *
+ ******************************************************************************/
+int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
+{
+	int32_t status = 0;
+	uint8_t value = 0;
+	int32_t time_out_cnt = 0;
+
+	switch (freq)
+	{
+	case TX_FREQ_125:
+	{
+		//************************************************************
+		// Setup Tx Frequency-Dependent Syntheisizer Registers
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
+		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
+		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
+		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
+		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
+		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+		status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp)
+		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
+		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
+		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
+
+		//************************************************************
+		// Write Tx Frequency Words
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
+		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
+		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
+		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
+		status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
+
+		//************************************************************
+		// Tx Quadrature Calibration Settings
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
+		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
+		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
+		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
+		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
+		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
+		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
+		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
+
+		break;
+	}
+	case TX_FREQ_126:
+	{
+		//************************************************************
+		// Setup Tx Frequency-Dependent Syntheisizer Registers
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
+		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
+		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
+		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
+		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
+		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
+		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
+		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
+		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
+
+		//************************************************************
+		// Write Tx Frequency Words
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0]
+		status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8]
+		status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16]
+		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
+		status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
+
+		//************************************************************
+		// Tx Quadrature Calibration Settings
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
+		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
+		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
+		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
+		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
+		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
+		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
+		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
+
+		break;
+	}
+	case TX_FREQ_4125:
+	{
+		//************************************************************
+		// Setup Tx Frequency-Dependent Syntheisizer Registers
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
+		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
+		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
+		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
+		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
+		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
+		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
+		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
+		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
+
+		//************************************************************
+		// Write Rx Frequency Words
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
+		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
+		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
+		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
+		status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+		status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting
+
+		//************************************************************
+		// Tx Quadrature Calibration Settings
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
+		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
+		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
+		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
+		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
+		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index
+		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
+		status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
+
+		break;
+	}
+
+		// Wait for cal to complete (Done when 0x016[4]==0)
+		time_out_cnt = 0;
+		do
+		{
+			status |= ad9361_reg_read(dev, 0x0016, &value);
+			mdelay(1); // Wait 1ms
+			time_out_cnt++;
+		} while ((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
+	}
+
+	return status;
+}
+
+// @ Get AD9361 - 1 temperature (Celsius Degree)
+/**
+ * Read corresponding register to get AD9361 - 1 current temperature.
+ */
+int8_t Hardware_GetAD9361Temp_1(void)
+{
+	int8_t scaleTemp;
+
+	ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x01); // disable aux adc
+	ad9361_reg_read(ad9361_1_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x00); // enable aux adc
+
+	return (int8_t) scaleTemp/1.16;
+}
+
+// @ Get AD9361 - 2 temperature (Celsius Degree)
+/**
+ * Read corresponding register to get AD9361 - 2 current temperature.
+ */
+int8_t Hardware_GetAD9361Temp_2(void)
+{
+	int8_t scaleTemp;
+
+	ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x01); // disable aux adc
+	ad9361_reg_read(ad9361_2_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
+	ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x00); // enable aux adc
+
+	return (int8_t) scaleTemp/1.16;
+}
+
+// @ Determine AD9361 lock state
+/**
+ * Read corresponding register to determine AD9361(both) lock state.
+ */
+uint8_t Hardware_GetAD9361LockStatus(void)
+{
+	uint8_t ret = 0;
+	uint8_t regVal;
+
+	// bbpll
+	ad9361_reg_read(ad9361_1_reg_inst, 0x005E, &regVal); // [D7] is lock indicator
+	ret |= ((regVal & 0x80) == 0x80) ? CLK_AD0_BBPLL_LOCK : 0;
+	ad9361_reg_read(ad9361_2_reg_inst, 0x005E, &regVal); // [D7] is lock indicator
+	ret |= ((regVal & 0x80) == 0x80) ? CLK_AD1_BBPLL_LOCK : 0;
+
+	// rfpll
+	ad9361_reg_read(ad9361_1_reg_inst, 0x0287, &regVal); // [D1] is lock indicator
+	ret |= ((regVal & 0x02) == 0x02) ? CLK_AD0_RFPLL_LOCK : 0;
+	ad9361_reg_read(ad9361_2_reg_inst, 0x0287, &regVal); // [D1] is lock indicator
+	ret |= ((regVal & 0x02) == 0x02) ? CLK_AD1_RFPLL_LOCK : 0;
+
+	return ret;
+}
+
+// @ Determine HMC7044 lock state
+/**
+ * Read corresponding register to determine clock lock state.
+ */
+uint8_t Hardware_GetHMC7044LockStatus(void)
+{
+	uint8_t ret = 0;
+	uint8_t regVal;
+
+	// pll1
+	hmc7044_read(hmc7044_inst, 0x007C, &regVal); // [D5] is lock indicator
+	ret |= ((regVal & 0xE0) != 0x00) ? CLK_SP_PLL0_LOCK : 0;
+
+	// pll2
+	hmc7044_read(hmc7044_inst, 0x007D, &regVal); // [D0] is lock indicator
+	ret |= ((regVal & 0x01) == 0x01) ? CLK_SP_PLL1_LOCK : 0;
+
+	return ret;
+}

df_datalink_sp/src/hwconfig.h

@@ -0,0 +1,32 @@
+/*****************************************************************************/
+/**
+ * Description: hwconfig.h
+ *
+
+ * Date: 2024-02-20 13:19
+ * Last Edit Time: [2024-02-20 13:19]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2023-05-07]: Initial edition.
+ *
+ * Copyright(c) 2024 Beijing Institute of Technology.
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+// Standard
+#include <stdint.h>
+#include "config/app_config.h"
+#include "drivers/rf-transceiver/ad9361_reg/ad9361_reg.h"
+#include "drivers/rf-transceiver/ad9361/ad9361_api.h"
+
+/************************** Function Prototypes ******************************/
+int32_t Hardware_Init(void);
+int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq);
+int8_t Hardware_GetAD9361Temp_1(void);
+int8_t Hardware_GetAD9361Temp_2(void);
+uint8_t Hardware_GetAD9361LockStatus(void);
+uint8_t Hardware_GetHMC7044LockStatus(void);
+
+

df_datalink_sp/src/main.c

@@ -20,19 +20,15 @@
 #include <stdint.h>
 #include <stdbool.h>
 // Xilinx
-#include "sleep.h"
-#include "xil_cache.h"
 #include "xscugic.h"
-#include "xscutimer.h"
-#include "xgpiops.h"
 #include "drivers/platform/xilinx_irq.h"
 #include "drivers/platform/xilinx_timer.h"
-#include "drivers/rf-transceiver/ad9361/ad9361_api.h"
-#include "drivers/axi_core/spi_engine/spi_engine.h"
 // App
 #include "common.h"
 #include "error.h"
 #include "timer.h"
+#include "hwconfig.h"
+#include "system_monitor.h"
 #include "config/app_config.h"
 #include "dev_profile/dev_profile.h"
 #include "systembus/systembus.h"
@@ -46,6 +42,7 @@ void PeriodicPull_Handler(void *callBackRef);
 void ScuTimer_IntrHandler(void *context);
 void Systembus_RxIntrHandler(void *context);
 void Systembus_TxIntrHandler(void *context);
+
 /************************** Constant Definitions *****************************/
 struct callback_desc phy_callback_desc = {
 	.callback = Phy_IntrHandler,
@@ -101,7 +98,11 @@ static PHY_CONFIG phyConfig = {
 	.antBramId = PHY_ANTCONFIG_BRAM_DEVICE_ID,
 	.txBramId = PHY_TXBUFF_BRAM_DEVICE_ID,
 	.rxBramId = PHY_RXBUFF_BRAM_DEVICE_ID,
-	.hwXadcId = PHY_HW_XADC_DEVICE_ID
+	.hwXadcId = PHY_HW_XADC_DEVICE_ID,
+	.get_clk_state = Hardware_GetHMC7044LockStatus,
+	.get_ad_lock_state = Hardware_GetAD9361LockStatus,
+	.get_ad0_temp = Hardware_GetAD9361Temp_1,
+	.get_ad1_temp = Hardware_GetAD9361Temp_2
 };
 
 TMC_CONFIG tmcConfig = {
@@ -122,11 +123,7 @@ static PHY_INST *phyInstPtr;
 static TMC_INST *tmcInstPtr = NULL;
 L2_INST *linkInstPtr;
 
-static struct hmc7044_dev *hmc7044_inst;
-static struct ad9361_reg_dev *ad9361_1_reg_inst;
-static struct ad9361_reg_dev *ad9361_2_reg_inst;
-// static struct ad9361_rf_phy *ad9361_phy;
-// static struct ad9361_rf_phy *ad9361_2_phy;
+
 /****************************************************************************/
 /**
  * This function is responsible for initializing the SCUGIC instance, looking
@@ -360,8 +357,8 @@ void ScuTimer_IntrHandler(void *context)
 	xdesc = (struct xil_timer_desc *)(logTmPtr->extra);
 	if (XScuTimer_IsExpired((XScuTimer *)xdesc->instance))
 	{
-		// Update log
-		Phy_UpdateHwSate(phyInstPtr);
+		// Refresh log
+		Phy_RefreshHwSate(phyInstPtr);
 		XScuTimer_ClearInterruptStatus((XScuTimer *)xdesc->instance);
 	}
 	else
@@ -370,355 +367,6 @@ void ScuTimer_IntrHandler(void *context)
 	}
 }
 
-/*****************************************************************************/
-/**
- * @brief   Hardware_SwitchFreq
- *
- * @param   dev
- * @param   freq
- *
- * @return  None.
- *
- ******************************************************************************/
-int Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
-{
-	int32_t status = 0;
-	uint8_t value = 0;
-	int32_t time_out_cnt = 0;
-
-	switch (freq)
-	{
-	case TX_FREQ_125:
-	{
-		//************************************************************
-		// Setup Tx Frequency-Dependent Syntheisizer Registers
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
-		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
-		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
-		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
-		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
-		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
-		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
-		status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp)
-		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
-		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
-		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
-
-		//************************************************************
-		// Write Tx Frequency Words
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
-		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
-		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
-		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
-		status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
-		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
-
-		//************************************************************
-		// Tx Quadrature Calibration Settings
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
-		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
-		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
-		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
-		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
-		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
-		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
-		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
-
-		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
-		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
-
-		break;
-	}
-	case TX_FREQ_126:
-	{
-		//************************************************************
-		// Setup Tx Frequency-Dependent Syntheisizer Registers
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
-		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
-		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
-		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
-		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
-		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
-		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
-		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
-		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
-		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
-		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
-
-		//************************************************************
-		// Write Tx Frequency Words
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0]
-		status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8]
-		status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16]
-		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
-		status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
-		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
-
-		//************************************************************
-		// Tx Quadrature Calibration Settings
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
-		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
-		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
-		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
-		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
-		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
-		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
-		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
-
-		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
-		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
-
-		break;
-	}
-	case TX_FREQ_4125:
-	{
-		//************************************************************
-		// Setup Tx Frequency-Dependent Syntheisizer Registers
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
-		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
-		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
-		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
-		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
-		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
-		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
-		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
-		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
-		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
-		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
-
-		//************************************************************
-		// Write Rx Frequency Words
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
-		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
-		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
-		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
-		status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
-		status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting
-
-		//************************************************************
-		// Tx Quadrature Calibration Settings
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
-		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
-		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
-		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
-		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
-		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index
-		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
-		status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used
-
-		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
-		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
-
-		break;
-	}
-
-		// Wait for cal to complete (Done when 0x016[4]==0)
-		time_out_cnt = 0;
-		do
-		{
-			status |= ad9361_reg_read(dev, 0x0016, &value);
-			mdelay(1); // Wait 1ms
-			time_out_cnt++;
-		} while ((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
-	}
-
-	return status;
-}
-
-/*****************************************************************************/
-/**
- * @brief   Hardware_Init
- *
- * @param   none.
- *
- * @return  None.
- *
- ******************************************************************************/
-int Hardware_Init(void)
-{
-	int32_t Status;
-	XGpioPs Gpio;
-	XGpioPs_Config *ConfigPtr;
-	ConfigPtr = XGpioPs_LookupConfig(AD9361_GPIO_DEVICE_ID);
-	Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
-	if (Status != SUCCESS)
-	{
-		return FAILURE;
-	}
-
-	/**********************************************************/
-	/****************** HMC7044 Configuration *****************/
-	/**********************************************************/
-	Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param);
-	if (Status != SUCCESS)
-	{
-		DBG_ERROR("hmc7044_init() error: %" PRId32 "\n", Status);
-		return FAILURE;
-	}
-
-	/**********************************************************/
-	/***************** AD9361-1 Configuration *****************/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, AD9361_GPIO_OUTPUT);
-
-	ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param);
-	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0);
-	ad9361_reg_config(ad9361_1_reg_inst);
-	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1);
-
-	//	Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param);
-	//	if (Status != XST_SUCCESS){
-	//		return XST_FAILURE;
-	//	}else{
-	//		printf("Configurate AD9361 Completely!\n");
-	//	}
-	//	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
-	//	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
-
-	/**********************************************************/
-	/***************** AD9361-2 Configuration *****************/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, AD9361_GPIO_OUTPUT);
-
-	ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param);
-	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0);
-	ad9361_reg_config(ad9361_2_reg_inst);
-	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1);
-
-	//	uint8_t rd_back;
-	//	Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
-	//	Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);
-
-	/**********************************************************/
-	/******* AD9361 Baseband Multichip Synchronization ********/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, AD9361_GPIO_OUTPUT);
-
-	// SYNC BBPLL and DIGITAL SAMPLING CLOCKS
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D);
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
-	mdelay(20);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin
-	mdelay(500);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
-	mdelay(2000);
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin
-	mdelay(500);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08);
-
-	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
-	mdelay(20);
-	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1);
-	mdelay(20);
-	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
-
-	/**********************************************************/
-	/********* AD9361 Multichip Rx Phase Calibration **********/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, AD9361_GPIO_INPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, AD9361_GPIO_INPUT);
-
-	// switch to lower frequency
-	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
-	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1);
-	mdelay(20);
-
-	// switch rx channel
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30);
-	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30);
-
-	// enable dual ad9361 tx channels
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels
-
-	// switch ad9361 tx channel
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
-	mdelay(20);
-
-	// begin to calibrate the 1st ad9361
-	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
-	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1);
-	mdelay(1);
-	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
-
-	// read calibration status
-	int32_t time_out_cnt = 0;
-	do
-	{
-		mdelay(1); // Wait 1ms
-		time_out_cnt++;
-	} while (((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
-
-	if (time_out_cnt == AD9361_TIMEOUT_TH)
-	{
-		return FAILURE;
-	}
-
-	// begin to calibrate the 2nd ad9361
-	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1);
-	mdelay(1);
-	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0);
-
-	// read calibration status
-	time_out_cnt = 0;
-	do
-	{
-		mdelay(1); // Wait 1ms
-		time_out_cnt++;
-	} while (((XGpioPs_ReadPin(&Gpio, AD9361_2_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
-
-	if (time_out_cnt == AD9361_TIMEOUT_TH)
-	{
-		return FAILURE;
-	}
-
-	// enable single ad9361 tx channels
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
-
-	// switch ad9361 tx & rx channel
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03);
-	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03);
-
-	// switch to higher frequency
-	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
-	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0);
-
-	DBG_PRINT("Done.\n");
-
-	return 0;
-}
-
 /*****************************************************************************/
 /**
  * @brief	Main function, initialize all the device needed, initialize

df_datalink_sp/src/networking/link_layer/link_layer.c

@@ -333,7 +333,6 @@ void L2_FrameStateUpdate(L2_INST *instPtr)
 	PHY_INST *phyRef = instPtr->config.phyInstPtr;
 	bool isValid;
 	L2_FRAME_TYPE recvType = L2_GetLastOptFrameType(instPtr);
-	L2_FRAME_TYPE sendType = L2_GetNextFrameType(instPtr);
 	// Update frame state.
 	if (Phy_IsFrameValid(phyRef) == false)
 	{
@@ -347,7 +346,6 @@ void L2_FrameStateUpdate(L2_INST *instPtr)
 	instPtr->log.frameRecv++;
 
 	// Update frame state.
-	// FIXME: add log
 	switch (recvType)
 	{
 	case L2_SCAN_FRAME:
@@ -385,54 +383,6 @@ void L2_FrameStateUpdate(L2_INST *instPtr)
 		L2_DataAvailUpdate(instPtr, false);
 	}
 	}
-
-	// Logging status.
-	// -- send slot status
-	if (instPtr->tor.curr == L2_TOR_RX)
-	{
-		instPtr->rxSlotLog.tuNo = L2_GetCurrentFrameNum(instPtr);
-		instPtr->rxSlotLog.slotNo = L2_GetCurrentSlotNum(instPtr);
-		instPtr->rxSlotLog.frameType = recvType;
-		memset(instPtr->rxSlotLog.payload, 0x00, sizeof(instPtr->rxSlotLog.payload));
-		if (isValid == true)
-		{
-			memcpy(instPtr->rxSlotLog.payload,
-					instPtr->recvPktData,
-					Phy_GetFrameLen(L2_L2frame2L1frame(recvType)));
-			TIME_WORD timeWrod;
-			Phy_GetLastReceivedFrameSyncTimeStamp(phyRef, &timeWrod);
-			instPtr->rxSlotLog.tmStamp = timeWrod.frac_part;
-			instPtr->rxSlotLog.tmStamp += (uint64_t)timeWrod.int_part * TIME_FRAC_MAX;
-
-			// Log time deviation.
-			instPtr->txSlotLog.tmDevi = 0; // TODO:
-			// Log frequency deviation
-			instPtr->rxSlotLog.freqDevi = (uint32_t)Phy_GetFreqEst(phyRef);
-		}
-		else
-		{
-			instPtr->rxSlotLog.tmStamp = 0;
-			instPtr->rxSlotLog.tmDevi = 0;
-			instPtr->rxSlotLog.freqDevi = 0;
-			memset(instPtr->rxSlotLog.payload, 0x00, sizeof(instPtr->rxSlotLog.payload));
-		}
-		SysMonitor_UpdateRecvSlotLog(&(instPtr->rxSlotLog));
-	}
-	// -- send slot status
-	if (instPtr->tor.next == L2_TOR_TX)
-	{
-		instPtr->txSlotLog.tuNo = L2_GetCurrentFrameNum(instPtr);
-		instPtr->txSlotLog.slotNo = L2_GetCurrentSlotNum(instPtr);
-		instPtr->txSlotLog.frameType = sendType;
-		memset(instPtr->rxSlotLog.payload, 0x00, sizeof(instPtr->txSlotLog.payload));
-		memcpy(instPtr->txSlotLog.payload,
-			   instPtr->sendPktData,
-			   Phy_GetFrameLen(L2_L2frame2L1frame(sendType)));
-		instPtr->txSlotLog.tmStamp = 0;
-		instPtr->txSlotLog.tmDevi = 0;
-		instPtr->txSlotLog.freqDevi = 0;
-		SysMonitor_UpdateSendSlotLog(&(instPtr->txSlotLog));
-	}
 }
 
 /*****************************************************************************/
@@ -1276,25 +1226,35 @@ int32_t Linklayer_Proc(L2_INST *instPtr)
 	// Check and execute scheduled event.
 	L2_EventPoolHandler(instPtr);
 
-	PHY_INST* phyRef = instPtr->config.phyInstPtr;
-	TMC_INST* tmcRef = instPtr->config.tmcInstPtr;
-
-	TIME_WORD timeWord;
-	// Update Protocol log
-	instPtr->prtcLog.tmSys = instPtr->frameNum.last * L2_SLOTS_PER_FRAME + instPtr->slotNum.last;
-	instPtr->prtcLog.phySt = 0; // TODO: Update physical state.
-	TimeCtrl_GetCurrentTime(tmcRef, &timeWord);
-	instPtr->prtcLog.tmLocal = timeWord.frac_part; // us
-	instPtr->prtcLog.tmLocal += (uint64_t)timeWord.int_part * TIME_FRAC_MAX; // us
-	instPtr->prtcLog.beamNo = phyRef->beamNo.last;
-	instPtr->prtcLog.beamNo = phyRef->beamWd.last;
-	instPtr->prtcLog.stage = instPtr->mainState;
-	instPtr->prtcLog.recvCnt = instPtr->log.frameRecv;
-	instPtr->prtcLog.recvCorrect = instPtr->log.frameCorrect;
-	SysMonitor_UpdateProtocolLog(&(instPtr->prtcLog));
-
-
 	// Update link layer state.
 	instPtr->mainState = instPtr->nextState;
+
+	instPtr->linkLog.tuNum = instPtr->frameNum.curr;
+	instPtr->linkLog.slotNum = (uint8_t)instPtr->slotNum.curr;
+	instPtr->linkLog.nodeType = (instPtr->config.myType == L2_NODE_HEAD) ? 0xAA : 0xCC;
+	instPtr->linkLog.cxnStatus = (instPtr->cxn2Net) ? 0x11 : 0x00;
+	instPtr->linkLog.linkStage = (instPtr->mainState == L2_INIT_STATE) ? 0x00 : 0x11;
+	// TODO:
+	// instPtr->linkLog.recxnCnt =
+	// instPtr->linkLog.beamNo =
+	// instPtr->linkLog.beamWidth =
+	// instPtr->linkLog.beamAz =
+	// instPtr->linkLog.beamEl =
+	instPtr->linkLog.advTxCnt = (uint16_t)instPtr->log.advTxCnt;
+	instPtr->linkLog.advRecvCnt = (uint16_t)instPtr->log.advRecvCnt;
+	instPtr->linkLog.advCorrectCnt = (uint16_t)instPtr->log.advCorrectCnt;
+	instPtr->linkLog.cfmTxCnt = instPtr->log.cfmTxCnt;
+	instPtr->linkLog.cfmRecvCnt = instPtr->log.cfmRecvCnt;
+	instPtr->linkLog.cfmCorrectCnt = instPtr->log.cfmCorrectCnt;
+	instPtr->linkLog.svcTxCnt = instPtr->log.svcTxCnt;
+	instPtr->linkLog.svcRecvCnt = instPtr->log.svcRecvCnt;
+	instPtr->linkLog.svcCorrectCnt = instPtr->log.svcCorrectCnt;
+	instPtr->linkLog.timeDev = (instPtr->log.timeDev > INT32_MAX) ?
+								INT32_MAX :
+								((instPtr->log.timeDev < INT32_MIN) ? INT32_MIN : (int32_t) instPtr->log.timeDev);
+	instPtr->linkLog.sendId = instPtr->serviceFSM->txLog.dataId;
+	instPtr->linkLog.recvId = instPtr->serviceFSM->rxLog.dataId;
+
+	SysMonitor_UpdateLinklayerLog(&(instPtr->linkLog));
 	return SUCCESS;
 }

df_datalink_sp/src/networking/link_layer/link_layer.h

@@ -64,6 +64,8 @@ typedef struct
 	uint32_t svcTxCnt;
 	uint32_t svcRecvCnt;
 	uint32_t svcCorrectCnt;
+
+	int64_t timeDev;
 } L2_LOG;
 
 typedef struct
@@ -90,9 +92,7 @@ typedef struct
 	L2_LOG log;
 	// for system log
 	SYSINFO sysInfo;
-	SLOTLOG txSlotLog;
-	SLOTLOG rxSlotLog;
-	PRTCLLOG prtcLog;
+	LINKLOG linkLog;
 } L2_INST;
 
 /************************** Variable Definitions *****************************/
@@ -166,7 +166,8 @@ L2_FRAME_TYPE L2_GetNextFrameType(L2_INST *instPtr);
 L2_TOR_TYPE L2_GetNextTor(L2_INST *instPtr);
 
 // Time syncronization
-int32_t L2_TimeAlign(L2_INST *instPtr, uint32_t frameNum, uint32_t slotNum, bool relative);
+int32_t L2_GetTimeDeviation(L2_INST *instPtr, uint32_t frameNum, uint32_t slotNum, bool relative, int64_t* timeDev);
+void L2_TimeAdjust(L2_INST *instPtr, const int64_t *timeDev);
 
 
 #endif /* __LINK_LAYER_H_ */

df_datalink_sp/src/networking/link_layer/link_layer_types.h

@@ -22,6 +22,9 @@
 #include "geometry/coord.h"
 #include "geometry/quaternion.h"
 #include "../phy_layer/phy_layer.h"
+#ifndef EMULATION
+#include "../config/app_config.h"
+#endif
 /************************** Constant Definitions *****************************/
 // Common node ID definition
 #define L2_BROADCAST_ID 0xFF
@@ -210,6 +213,8 @@ typedef struct
 #ifdef DATALINK_ENABLE_BERTEST
 	uint32_t bitTotal;
 	uint32_t bitError;
+	double lossRate;
+	double errorRate;
 #endif
 } L2_SVC_FSM;
 

df_datalink_sp/src/networking/link_layer/routine_table.c

@@ -16,6 +16,9 @@
 #include "link_layer.h"
 #include "link_layer_types.h"
 
+#define LINKLAYER_INSERT_EXTRGAP
+
+#ifndef LINKLAYER_INSERT_EXTRGAP
 L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
 // SubFrame 0
 	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
@@ -38,6 +41,7 @@ L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
 	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
 	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
 	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+
 // SubFrame 1
 	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
 	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
@@ -59,6 +63,7 @@ L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
 	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
 	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
 	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+
 // SubFrame 2
 	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
 	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
@@ -80,6 +85,7 @@ L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
 	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
 	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
 	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+
 // SubFrame 3
 	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
 	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
@@ -122,6 +128,7 @@ L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
 	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
 	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
 	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+
 // SubFrame 5
 	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
 	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
@@ -143,6 +150,7 @@ L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
 	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
 	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
 	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+
 // SubFrame 6
 	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
 	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
@@ -164,6 +172,7 @@ L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
 	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
 	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
 	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+
 // SubFrame 7
 	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
 	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
@@ -185,6 +194,7 @@ L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
 	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
 	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
 	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+
 // SubFrame 8
 	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
 	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
@@ -206,6 +216,7 @@ L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
 	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
 	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
 	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+
 // SubFrame 9
 	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
 	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
@@ -450,6 +461,451 @@ L2_RTNE_TABLE_ENTRY normalSub[L2_SLOTS_PER_FRAME] = {
 	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
 	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
 };
+#else
+L2_RTNE_TABLE_ENTRY intraScanSubT[L2_SLOTS_PER_FRAME] = {
+// SubFrame 0
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+
+// SubFrame 1
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+
+// SubFrame 2
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+
+// SubFrame 3
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x00, 0x01, 0xFF},
+	{L2_SLOT_SCAN, 0x01, 0x01, 0xFF},
+	{L2_SLOT_ADVERTISE, 0x00, 0x01, 0xFF},
+	{L2_SLOT_ADVERTISE, 0x01, 0x01, 0xFF},
+	{L2_SLOT_ADVERTISE, 0x02, 0x01, 0xFF},
+	{L2_SLOT_ADVERTISE, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 4
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 5
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 6
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 7
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 8
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 9
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x01, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x02, 0x01, 0xFF},
+	{L2_SLOT_CONFIRM, 0x03, 0x01, 0xFF},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_CONFIRM, 0x00, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x01, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x02, 0xFF, 0x01},
+	{L2_SLOT_CONFIRM, 0x03, 0xFF, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+};
+
+L2_RTNE_TABLE_ENTRY normalSub[L2_SLOTS_PER_FRAME] = {
+// SubFrame 0
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 1
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 2
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 3
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 4
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 5
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 6
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 7
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 8
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+
+// SubFrame 9
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x01, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x02, 0x01, 0x02},
+	{L2_SLOT_SERVICE, 0x03, 0x01, 0x02},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+	{L2_SLOT_SERVICE, 0x00, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x01, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x02, 0x02, 0x01},
+	{L2_SLOT_SERVICE, 0x03, 0x02, 0x01},
+	{L2_SLOT_IDLE, 0x00, 0x00, 0x00},
+};
+#endif
 
 L2_RTNE_TABLE_ENTRY *initTable[L2_INIT_RTNE_PERIOD] =
 {

df_datalink_sp/src/networking/link_layer/scan.c

@@ -409,9 +409,7 @@ int32_t L2_Scan_PktHandler(L2_INST *instPtr, uint8_t *msg)
 		// Reset node ttl
 		node->ttlCnt = 0;
 
-		if (L2_isCxn2Net(instPtr) == false)
-		{
-			uint32_t netstartTime, frameNum, slotNum = 0;
+		uint32_t netstartTime;
 		// Update net start time.
 		L2_FrameGetChunk(msg, L2_MSG_ADV_SRC_NETSTART_TIME, L2_MSG_ADV_SRC_NETSTART_TIME_LEN, &netstartTime);
 		L2_EVENT netSetupDoneEvent = {
@@ -419,12 +417,20 @@ int32_t L2_Scan_PktHandler(L2_INST *instPtr, uint8_t *msg)
 			.msg = &netstartTime};
 		AssertL2Event(instPtr, &netSetupDoneEvent);
 
-			// Time sync.
+		// Calculate time deviation
+		uint32_t frameNum, slotNum = 0;
 		L2_FrameGetChunk(msg, L2_MSG_FRAME_NUM, L2_MSG_FRAME_NUM_LEN, &frameNum);
 		L2_FrameGetChunk(msg, L2_MSG_SLOT_NUM, L2_MSG_SLOT_NUM_LEN, &slotNum);
-			// TODO: Check
-			L2_TimeAlign(instPtr, frameNum, slotNum, true);
+		Status = L2_GetTimeDeviation(instPtr, frameNum, slotNum, true, &(instPtr->log.timeDev));
+		if (Status != SUCCESS)
+		{
+			DBG_ERROR("Failed to compute time deviation.\n")
+			break;
 		}
+
+		// Time sync.
+		L2_TimeAdjust(instPtr, &(instPtr->log.timeDev));
+
 		// trigger flag
 		AdvRecvStateUpdate(scanFsmPtr, true);
 		Status = SUCCESS;
@@ -465,6 +471,17 @@ int32_t L2_Scan_PktHandler(L2_INST *instPtr, uint8_t *msg)
 		// Reset node ttl
 		node->ttlCnt = 0;
 
+		// Calculate time deviation
+		uint32_t frameNum, slotNum = 0;
+		L2_FrameGetChunk(msg, L2_MSG_FRAME_NUM, L2_MSG_FRAME_NUM_LEN, &frameNum);
+		L2_FrameGetChunk(msg, L2_MSG_SLOT_NUM, L2_MSG_SLOT_NUM_LEN, &slotNum);
+		Status = L2_GetTimeDeviation(instPtr, frameNum, slotNum, true, &(instPtr->log.timeDev));
+		if (Status != SUCCESS)
+		{
+			DBG_ERROR("Failed to compute time deviation.\n")
+			break;
+		}
+
 		if (L2_GetNodeType(instPtr) != L2_NODE_HEAD)
 		{
 			// check if net setup finished.
@@ -501,6 +518,8 @@ int32_t L2_Scan_PktHandler(L2_INST *instPtr, uint8_t *msg)
 				l2Event.msg = &newState;
 				AssertL2Event(instPtr, &l2Event);
 			}
+			// Time sync.
+			L2_TimeAdjust(instPtr, &(instPtr->log.timeDev));
 		}
 		Status = SUCCESS;
 		break;

df_datalink_sp/src/networking/link_layer/service.c

@@ -115,11 +115,11 @@ static int32_t Service_Packing(L2_INST *instPtr, L2_FRAME_TYPE type, uint8_t dst
 		uint32_t dataId;
 		if(L2_GetNodeType(instPtr) == L2_NODE_HEAD)
 		{
-			SysMonitor_GetSendPayloadFLJRaw(buff + L2_MSG_SVC_PAYLOAD, &dataId);
+			SysMonitor_GetSendPayload(buff + L2_MSG_SVC_PAYLOAD, &dataId, PAYLOAD_LEN_FLJ_TX);
 		}
 		else
 		{
-			SysMonitor_GetSendPayloadLJRaw(buff + L2_MSG_SVC_PAYLOAD, &dataId);
+			SysMonitor_GetSendPayload(buff + L2_MSG_SVC_PAYLOAD, &dataId, PAYLOAD_LEN_LJ_TX);
 		}
 
 		L2_FrameInsertChunk(buff, L2_MSG_SVC_PAYLOAD_ID, L2_MSG_SVC_PAYLOAD_ID_LEN, &dataId);
@@ -141,6 +141,9 @@ static int32_t Service_Packing(L2_INST *instPtr, L2_FRAME_TYPE type, uint8_t dst
 			DBG_ERROR("Fail to append CRC...\n");
 			return Status;
 		}
+
+		memcpy(instPtr->serviceFSM->txLog.data, buff, L2_SVC_PACK_LEN);
+		instPtr->serviceFSM->txLog.dataId = dataId;
 		break;
 	}
 	default:
@@ -227,8 +230,8 @@ int32_t L2_Service_PktHandler(L2_INST *instPtr, uint8_t *msg)
 {
 	ASSERT(instPtr != NULL);
 	ASSERT(msg != NULL);
-#ifndef DATALINK_ENABLE_BERTEST
 	int32_t Status;
+#ifndef DATALINK_ENABLE_BERTEST
 	uint8_t frameType;
 	L2_FrameGetChunk(msg, L2_MSG_TYPE, L2_MSG_TYPE_LEN, &frameType);
 	switch (frameType)
@@ -269,6 +272,17 @@ int32_t L2_Service_PktHandler(L2_INST *instPtr, uint8_t *msg)
 		// Reset node ttl
 		node->ttlCnt = 0;
 
+		// Calculate time deviation
+		uint32_t frameNum, slotNum = 0;
+		L2_FrameGetChunk(msg, L2_MSG_FRAME_NUM, L2_MSG_FRAME_NUM_LEN, &frameNum);
+		L2_FrameGetChunk(msg, L2_MSG_SLOT_NUM, L2_MSG_SLOT_NUM_LEN, &slotNum);
+		Status = L2_GetTimeDeviation(instPtr, frameNum, slotNum, true, &(instPtr->log.timeDev));
+		if (Status != SUCCESS)
+		{
+			DBG_ERROR("Failed to compute time deviation.\n")
+			break;
+		}
+
 		uint32_t dataId;
 		L2_FrameGetChunk(msg, L2_MSG_SVC_PAYLOAD_ID, L2_MSG_SVC_PAYLOAD_ID_LEN, &dataId);
 
@@ -276,22 +290,24 @@ int32_t L2_Service_PktHandler(L2_INST *instPtr, uint8_t *msg)
 		{
 			if(L2_GetNodeType(instPtr) == L2_NODE_HEAD)
 			{
-				SysMonitor_UpdateRecvPayloadFLJRaw(msg+L2_MSG_SVC_PAYLOAD);
+				SysMonitor_UpdateRecvPayload(msg+L2_MSG_SVC_PAYLOAD, PAYLOAD_LEN_FLJ_RX);
 			}
 			else
 			{
-				SysMonitor_UpdateRecvPayloadLJRaw(msg+L2_MSG_SVC_PAYLOAD);
+				SysMonitor_UpdateRecvPayload(msg+L2_MSG_SVC_PAYLOAD, PAYLOAD_LEN_LJ_RX);
 			}
 		}
 
+		// Logging
+		memcpy(instPtr->serviceFSM->rxLog.data, msg, L2_SVC_PACK_LEN);
+		instPtr->serviceFSM->rxLog.dataId = dataId;
+
 #ifdef DATALINK_ENABLE_AUTOTIMESYNC
 		// Implement a auto time sync.
 		if (L2_GetNodeType(instPtr) != L2_NODE_HEAD)
 		{
-			uint32_t frameNum, slotNum;
-			L2_FrameGetChunk(msg, L2_MSG_FRAME_NUM, L2_MSG_FRAME_NUM_LEN, &frameNum);
-			L2_FrameGetChunk(msg, L2_MSG_SLOT_NUM, L2_MSG_SLOT_NUM_LEN, &slotNum);
-			L2_TimeAlign(instPtr, frameNum, slotNum, true);
+			// Time sync.
+			L2_TimeAdjust(instPtr, &(instPtr->log.timeDev));
 		}
 #endif
 		break;
@@ -303,22 +319,31 @@ int32_t L2_Service_PktHandler(L2_INST *instPtr, uint8_t *msg)
 	return Status;
 #else
 	uint32_t errorBits = 0;
-	for (int i = 0; i < SVC_PACK_LEN; i++)
+	for (int i = 0; i < L2_SVC_PACK_LEN; i++)
 	{
 		errorBits += count_ones(msg[i] ^ testData[i]);
 	}
 
-	instPtr->serviceFsm.bitError += errorBits;
-	instPtr->serviceFsm.bitTotal += SVC_PACK_LEN * 8;
+	instPtr->serviceFSM->bitError += errorBits;
+	instPtr->serviceFSM->bitTotal += L2_SVC_PACK_LEN * 8;
 
+	// Calculate time deviation
+	uint32_t frameNum, slotNum = 0;
+	L2_FrameGetChunk(msg, L2_MSG_FRAME_NUM, L2_MSG_FRAME_NUM_LEN, &frameNum);
+	L2_FrameGetChunk(msg, L2_MSG_SLOT_NUM, L2_MSG_SLOT_NUM_LEN, &slotNum);
+	Status = L2_GetTimeDeviation(instPtr, frameNum, slotNum, true, &(instPtr->log.timeDev));
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("Failed to compute time deviation.\n")
+		return Status;
+	}
 	// Implement a auto time sync.
 	if (L2_GetNodeType(instPtr) != L2_NODE_HEAD)
 	{
-		uint32_t frameNum, slotNum;
-		L2_FrameGetChunk(msg, L2_MSG_FRAME_NUM, L2_MSG_FRAME_NUM_LEN, &frameNum);
-		L2_FrameGetChunk(msg, L2_MSG_SLOT_NUM, L2_MSG_SLOT_NUM_LEN, &slotNum);
-		L2_TimeAlign(instPtr, frameNum, slotNum, true);
+		// Time sync.
+		L2_TimeAdjust(instPtr, &(instPtr->log.timeDev));
 	}
+	return SUCCESS;
 #endif
 }
 
@@ -366,7 +391,7 @@ int32_t L2_Service_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntr
 			// Packing service data
 			Service_Packing(instPtr, L2_SVC_FRAME, rtneEntry->dst);
 #else
-			memcpy(instPtr->sendPktData, testData, SVC_PACK_LEN);
+			memcpy(instPtr->sendPktData, testData, L2_SVC_PACK_LEN);
 #endif
 		}
 		// FIXME: Steer antenna to point to destination.
@@ -380,12 +405,11 @@ int32_t L2_Service_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntr
 	}
 #ifdef DATALINK_ENABLE_BERTEST
 	uint32_t pktLoss;
-	double errorRate, lossRate;
 	pktLoss = instPtr->log.svcRecvCnt - instPtr->log.svcCorrectCnt;
-	lossRate = (instPtr->log.svcRecvCnt == 0) ? 0 : (double)pktLoss / (double)instPtr->serviceFsm.pktRecv;
-	errorRate = (instPtr->serviceFsm.bitTotal == 0) ? 0 : (double)instPtr->serviceFsm.bitError / (double)instPtr->serviceFsm.bitTotal;
-	DBG_PRINT("Packet Loss Rate -- Total: %lu, Loss: %lu.\n", instPtr->serviceFsm.pktRecv, pktLoss);
-	DBG_PRINT("Bit Error Rate -- Total:%lu, Error:%lu.\n", instPtr->serviceFsm.bitTotal, instPtr->serviceFsm.bitError);
+	instPtr->serviceFSM->lossRate = (instPtr->log.svcRecvCnt == 0) ? 0 : (double)pktLoss / (double)instPtr->serviceFSM->pktRecv;
+	instPtr->serviceFSM->errorRate = (instPtr->serviceFSM->bitTotal == 0) ? 0 : (double)instPtr->serviceFSM->bitError / (double)instPtr->serviceFSM->bitTotal;
+	DBG_PRINT("Packet Loss Rate -- Total: %lu, Loss: %lu.\n", instPtr->serviceFSM->pktRecv, pktLoss);
+	DBG_PRINT("Bit Error Rate -- Total:%lu, Error:%lu.\n", instPtr->serviceFSM->bitTotal, instPtr->serviceFSM->bitError);
 #endif
 	return SUCCESS;
 }

df_datalink_sp/src/networking/link_layer/time_sync.c

@@ -32,20 +32,22 @@
 
 /*****************************************************************************/
 /**
- * @brief    a slot alignment, base on physical layer information.
+ * @brief    Get time deviation to the specified frame and slot number.
  *
  * @param   instPtr	a pointer to linklayer layer instance
  * @param   frameNum
  * @param   slotNum
+ * @param   relative
+ * @param   timeDev
  *
- * @return  SUCCESS Initialize successfully.
- *          FAILURE Initialization failed, allocate memory fail or initial
- *          bram controller fail.
+ * @return  SUCCESS
+ * 			EIGNORE there is no received frame
  *
  ******************************************************************************/
-// TODO: Check
-int32_t L2_TimeAlign(L2_INST *instPtr, uint32_t frameNum, uint32_t slotNum, bool relative)
+int32_t L2_GetTimeDeviation(L2_INST *instPtr, uint32_t frameNum, uint32_t slotNum, bool relative, int64_t *timeDev)
 {
+	ASSERT(instPtr != NULL);
+	ASSERT(timeDev != NULL);
 	L1_FRAME_TYPE lastRecvdFrame;
 	lastRecvdFrame = Phy_GetLastRecvFrameType(instPtr->config.phyInstPtr);
 	if (lastRecvdFrame == L1_NONE_FRAME)
@@ -57,8 +59,7 @@ int32_t L2_TimeAlign(L2_INST *instPtr, uint32_t frameNum, uint32_t slotNum, bool
 	DBG_INFO("Starting TimeAlign operation...\n");
 	// read nextSendTime from physical layer
 	uint64_t currTime, expectTime;
-	int64_t timeDiff;
-	TIME_WORD timeStamp, slotTimerAdjmet;
+	TIME_WORD timeStamp;
 	expectTime = ((uint64_t)(frameNum * L2_SLOTS_PER_FRAME + slotNum)) * TIME_FRAC_MAX;
 	expectTime += Phy_GetTimeComp(lastRecvdFrame);
 
@@ -71,10 +72,27 @@ int32_t L2_TimeAlign(L2_INST *instPtr, uint32_t frameNum, uint32_t slotNum, bool
 	currTime = (uint64_t)timeStamp.frac_part;
 	currTime += ((uint64_t)timeStamp.int_part) * TIME_FRAC_MAX;
 
-	timeDiff = (int64_t)(expectTime - currTime);
-
-	slotTimerAdjmet.int_part = (uint32_t)(timeDiff / TIME_FRAC_MAX);
-	slotTimerAdjmet.frac_part = (uint32_t)(timeDiff % TIME_FRAC_MAX);
-	TimeCtrl_TimeAdjust(instPtr->config.tmcInstPtr, &slotTimerAdjmet, TM_ADJ_ADD);
+	*timeDev = (int64_t)(expectTime - currTime);
 	return SUCCESS;
 }
+
+
+/*****************************************************************************/
+/**
+ * @brief    Implement time adjustment by applying time deviation.
+ *
+ * @param   instPtr	a pointer to linklayer layer instance
+ * @param   timeDev
+ *
+ * @return  NONE
+ *
+ ******************************************************************************/
+void L2_TimeAdjust(L2_INST *instPtr, const int64_t *timeDev)
+{
+	ASSERT(instPtr != NULL);
+	ASSERT(timeDev != NULL);
+	TIME_WORD slotTimerAdjmet;
+	slotTimerAdjmet.int_part = (uint32_t)(*timeDev / TIME_FRAC_MAX);
+	slotTimerAdjmet.frac_part = (uint32_t)(*timeDev % TIME_FRAC_MAX);
+	TimeCtrl_TimeAdjust(instPtr->config.tmcInstPtr, &slotTimerAdjmet, TM_ADJ_ADD);
+}

df_datalink_sp/src/networking/phy_layer/phy_layer.c

@@ -311,6 +311,30 @@ void Phy_UpdateState(PHY_INST *instPtr)
 	instPtr->recvSlotTime.frac_part = PhyRead(instPtr, TM_TARGET_L);
 	instPtr->recvFsTime.int_part = PhyRead(instPtr, FSTIME_H);
 	instPtr->recvFsTime.frac_part = PhyRead(instPtr, FSTIME_L);
+	instPtr->phyLog.acqCnt = PhyRead(instPtr, PHY_ACQ_CNT);
+	instPtr->phyLog.fsyncCnt = PhyRead(instPtr, PHY_FRAME_SYNC_CNT);
+	instPtr->phyLog.decodeCnt = PhyRead(instPtr, PHY_DECODE_CNT);
+	instPtr->phyLog.crcCnt = PhyRead(instPtr, PHY_CRC_OK_CNT);
+	instPtr->phyLog.doppler = Phy_GetFreqEst(instPtr);
+	instPtr->phyLog.recvStamp = (uint64_t)instPtr->recvFsTime.int_part * TIME_FRAC_MAX + instPtr->recvFsTime.frac_part;
+	uint64_t peak, avg;
+	peak = PhyRead(instPtr, PHY_ACQ_PEAK_L);
+	peak |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_PEAK_H)) << 32;
+	avg = PhyRead(instPtr, PHY_ACQ_MEAN_L);
+	avg |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_MEAN_H)) << 32;
+	instPtr->phyLog.acqPAPR = ((double)peak) / ((double)avg);
+	instPtr->phyLog.acqPhase = (PhyRead(instPtr, PHY_ACQ_FREQEST) & PHY_ACQ_FREQEST_PHASE_MASK) >> PHY_ACQ_FREQEST_PHASE_SHIFT;
+	instPtr->phyLog.acqFreqCh = (PhyRead(instPtr, PHY_ACQ_FREQEST) & PHY_ACQ_FREQEST_CHANNEL_MASK) >> PHY_ACQ_FREQEST_CHANNEL_SHIFT;
+	peak = PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_L);
+	peak |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_H)) << 32;
+	avg = PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_L);
+	avg |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_H)) << 32;
+	instPtr->phyLog.fsyncPAPR = ((double)peak) / ((double)avg);
+	instPtr->phyLog.fsyncFreqCh = (PhyRead(instPtr, PHY_FRAME_SYNC_FREQEST) & PHY_FRAME_SYNC_FREQEST_CHANNEL_MASK) >> PHY_FRAME_SYNC_FREQEST_CHANNEL_SHIFT;
+	instPtr->phyLog.deintlvAmpEst = PhyRead(instPtr, PHY_DEINTLV_AMPEST) & PHY_DEINTLV_AMPEST_MASK;
+	memset(instPtr->phyLog.reserve, 0x00, sizeof(instPtr->phyLog.reserve));
+
+	SysMonitor_UpdatePhysicalLayerLog(&(instPtr->phyLog));
 }
 
 /*****************************************************************************/
@@ -357,6 +381,7 @@ int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
 	memset(&((*instPtr)->beamNo), (int32_t)L1_INIT_ANT_NO, sizeof(PHY_RCD));
 	memset(&((*instPtr)->beamWd), (int32_t)L1_INIT_ANT_WD, sizeof(PHY_RCD));
 	memset(&((*instPtr)->hwSate), 0x00, sizeof(HWSTATE));
+	memset(&((*instPtr)->phyLog), 0x00, sizeof(PHYLOG));
 
 #ifndef EMULATION
 	XBram_Config *bramConfigPtr;
@@ -827,14 +852,6 @@ double Phy_GetFreqEst(PHY_INST *instPtr)
 	fineReg = PhyRead(instPtr, FINE_FREQEST);
 	estAbs = fineReg & FINE_FREQEST_VAL_MASK;
 	if (frameType >= L1_200KBPS_5MS_FRAME)
-	{
-		// 1.5M Rc
-		coarse = (double)(80 - acqFreqIdx) * (31.25e3 / 4);
-		coarse += (double)syncFreqIdx * 1.5e6 / 64 / 128;
-
-		fine = 12e6/2048*((double)estAbs)/8192.0;
-	}
-	else
 	{
 		// 12M Rc
 		coarse = (double)(8 - acqFreqIdx) * (250e3 / 4);
@@ -842,6 +859,14 @@ double Phy_GetFreqEst(PHY_INST *instPtr)
 
 		fine = 48e6/2048*((double)estAbs)/8192.0;
 	}
+	else
+	{
+		// 1.5M Rc
+		coarse = (double)(80 - acqFreqIdx) * (31.25e3 / 4);
+		coarse += (double)syncFreqIdx * 1.5e6 / 64 / 128;
+
+		fine = 12e6/2048*((double)estAbs)/8192.0;
+	}
 
 	fine = ((fineReg & FINE_FREQEST_SIGN_MASK) == FINE_FREQEST_SIGN_NEG) ?
 			-fine : fine;
@@ -876,17 +901,17 @@ double Phy_GetCoarseFreqEst(PHY_INST *instPtr)
 	acqFreqIdx = (regValue & COASE_FREQEST_ACQ_MASK) >> COASE_FREQEST_ACQ_SHIFT;
 	syncFreqIdx = (regValue & COASE_FREQEST_SYNC_MASK) >> COASE_FREQEST_SYNC_SHIFT;
 	if (frameType >= L1_200KBPS_5MS_FRAME)
-	{
-		// 1.5M Rc
-		freqEst = (double)(80 - acqFreqIdx) * (31.25e3 / 4);
-		freqEst += (double)syncFreqIdx * 1.5e6 / 64 / 128;
-	}
-	else
 	{
 		// 12M Rc
 		freqEst = (double)(8 - acqFreqIdx) * (250e3 / 4);
 		freqEst += (double)syncFreqIdx * 12e6 / 64 / 128;
 	}
+	else
+	{
+		// 1.5M Rc
+		freqEst = (double)(80 - acqFreqIdx) * (31.25e3 / 4);
+		freqEst += (double)syncFreqIdx * 1.5e6 / 64 / 128;
+	}
 
 	return freqEst;
 }
@@ -915,13 +940,13 @@ double Phy_GetFineFreqEst(PHY_INST *instPtr)
 	estAbs = regValue & FINE_FREQEST_VAL_MASK;
 	if (frameType >= L1_200KBPS_5MS_FRAME)
 	{
-		// 1.5M Rc
-		freqEst = 12e6/2048*((double)estAbs)/8192.0;
+		// 12M Rc
+		freqEst = 48e6/2048*((double)estAbs)/8192.0;
 	}
 	else
 	{
-		// 12M Rc
-		freqEst = 48e6/2048*((double)estAbs)/8192.0;
+		// 1.5M Rc
+		freqEst = 12e6/2048*((double)estAbs)/8192.0;
 	}
 	freqEst = ((regValue & FINE_FREQEST_SIGN_MASK) == FINE_FREQEST_SIGN_NEG) ?
 			-freqEst : freqEst;
@@ -1110,64 +1135,140 @@ void Phy_RetrieveRecvData(PHY_INST *instPtr, uint8_t *dataBuff)
  * @param   instPtr	a pointer to hopping pattern buffer
  * @param   patternLen	a integer indicate the length of hopping pattern.
  *
- * @return  SUCCESS
- * 			FAILURE	pattern length exceeds maximum length.
+ * @return  NONE
  *
  ******************************************************************************/
-void Phy_UpdateHwSate(PHY_INST *instPtr)
+void Phy_RefreshHwSate(PHY_INST *instPtr)
 {
 	ASSERT(instPtr != NULL);
 	uint32_t rawData;
 #ifndef EMULATION
-	// -- Update Chip voltage, unit mV
+	float evalData;
+	instPtr->hwSate.isSpOk = true;
+	// -- Update FPGA voltage status;
+	instPtr->hwSate.spFpgaVolt = 0;
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPINT);
-	instPtr->hwSate.spVolt = (uint16_t)(XAdcPs_RawToVoltage(rawData) * 1000);
+	evalData = XAdcPs_RawToVoltage(rawData);
+	instPtr->hwSate.spFpgaVolt |= (IS_PS_VALID(evalData)) ? VOLT_PS_OK : 0;
 
-	// -- Update Chip temperature, unit 0.01 deg
+	// -- -- Update Ps aux voltage
+	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPAUX);
+	evalData = XAdcPs_RawToVoltage(rawData);
+	instPtr->hwSate.spFpgaVolt |= (IS_PSAUX_VALID(evalData)) ? VOLT_PSAUX_OK : 0;
+
+	// -- -- Update DDR voltage
+	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPDRO);
+	evalData = XAdcPs_RawToVoltage(rawData);
+	instPtr->hwSate.spFpgaVolt |= (IS_DDR_VALID(evalData)) ? VOLT_DDR_OK : 0;
+
+	// -- -- Update PL voltage
+	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCINT);
+	evalData = XAdcPs_RawToVoltage(rawData);
+	instPtr->hwSate.spFpgaVolt |= (IS_PL_VALID(evalData)) ? VOLT_PL_OK : 0;
+
+	// -- -- Update PL aux voltage
+	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCAUX);
+	evalData = XAdcPs_RawToVoltage(rawData);
+	instPtr->hwSate.spFpgaVolt |= (IS_PLAUX_VALID(evalData)) ? VOLT_PLAUX_OK : 0;
+
+	// -- -- Update Bram voltage
+	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VBRAM);
+	evalData = XAdcPs_RawToVoltage(rawData);
+	instPtr->hwSate.spFpgaVolt |= (IS_BRAM_VALID(evalData)) ? VOLT_BRAM_OK : 0;
+
+	// -- Update clock lock state
+	if (instPtr->phyCofig.get_clk_state != NULL)
+	{
+		instPtr->hwSate.spClkState = instPtr->phyCofig.get_clk_state();
+	}
+	else
+	{
+		instPtr->hwSate.spClkState = 0;
+	}
+
+	// -- Update AD9361 pll lock state
+	if (instPtr->phyCofig.get_ad_lock_state != NULL)
+	{
+		instPtr->hwSate.spAdLockState = instPtr->phyCofig.get_ad_lock_state();
+	}
+	else
+	{
+		instPtr->hwSate.spAdLockState = 0;
+	}
+
+	// -- Update AD9361-0 temperature, unit 1 Celcius degree
+	if (instPtr->phyCofig.get_ad0_temp != NULL)
+	{
+		instPtr->hwSate.spAdTemp_0 = instPtr->phyCofig.get_ad0_temp();
+	}
+	else
+	{
+		instPtr->hwSate.spAdTemp_0 = 0;
+	}
+
+	// -- Update AD9361-1 temperature, unit 1 Celcius degree
+	if (instPtr->phyCofig.get_ad1_temp != NULL)
+	{
+		instPtr->hwSate.spAdTemp_1 = instPtr->phyCofig.get_ad1_temp();
+	}
+	else
+	{
+		instPtr->hwSate.spAdTemp_1 = 0;
+	}
+
+	// -- Update FPGA Chip temperature, unit 1 deg
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_TEMP);
-	instPtr->hwSate.spTemp = (uint16_t)(XAdcPs_RawToTemperature(rawData) * 100);
-
-	// FIXME: Chip status determine.
-	instPtr->hwSate.chipSt = 0;
+	evalData = XAdcPs_RawToTemperature(rawData);
+	instPtr->hwSate.spFpgaTemp = (evalData > TEMPERATURE_MAX)
+								? INT8_MAX
+								: ((evalData < TEMPERATURE_MIN) ? INT8_MIN : (int8_t) round(evalData/TEMPERATURE_LSB));
+	instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK & VOLT_PSAUX_OK & VOLT_DDR_OK & VOLT_PL_OK & VOLT_PLAUX_OK & VOLT_BRAM_OK))
+						&& (instPtr->hwSate.spClkState == (CLK_SP_PLL0_LOCK & CLK_SP_PLL1_LOCK))
+						&& (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK && CLK_AD0_RFPLL_LOCK & CLK_AD1_BBPLL_LOCK & CLK_AD1_RFPLL_LOCK));
 #else
-	instPtr->hwSate.spVolt = 0;
-	instPtr->hwSate.spTemp = 0;
-	instPtr->hwSate.chipSt = 0;
+	instPtr->hwSate.isSpOk = true;
 #endif
 	/*** Voltage and Status ***/
 	rawData = PhyRead(instPtr, ANT_STATUS);
-	// -- Update Antenna Status Code: 0xAA - normal, 0x55 - error
-	instPtr->hwSate.antSt = ((rawData & ANT_STATUS_CODE_MASK) == 0) ? 0xAA : 0x55;
 	// -- Update Antenna Voltage Status: 1 - normal, 0 - error
 	//    [0] - ANT voltage status
 	//    [2] - RF voltage status
 	//    [4] - NIL voltage status
-	instPtr->hwSate.antVolt = (rawData & ANT_STATUS_ANT_VOLT_MASK) ? 0x01 : 0x00;
-	instPtr->hwSate.antVolt |= (rawData & ANT_STATUS_RF_VOLT_MASK) ? 0x04 : 0x00;
-	instPtr->hwSate.antVolt |= (rawData & ANT_STATUS_NIL_VOLT_MASK) ? 0x10 : 0x00;
+	//    [6] - Antenna status
+	instPtr->hwSate.antVolt = ((rawData & ANT_STATUS_ANT_VOLT_MASK) == ANT_STATUS_ANT_VOLT_OK) ? VOLT_ANT_PROC_OK : 0x00;
+	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_RF_VOLT_MASK) == ANT_STATUS_RF_VOLT_OK) ? VOLT_ANT_RF_OK : 0x00;
+	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_NIL_VOLT_MASK) == ANT_STATUS_NIL_VOLT_OK) ? VOLT_ANT_NIL_OK : 0x00;
+	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_CODE_MASK) == ANT_STATUS_CODE_OK) ? ANT_STATE_OK : 0x00;
 
 	/*** Temperature and Lock Status ***/
-	rawData = PhyRead(instPtr, RF_STATUS);
+	rawData = PhyRead(instPtr, ANT_RF_STATUS);
 	//-- Update Antenna Temperature (signed 8bit integer, 1 centigrade per LSB)
-	instPtr->hwSate.antTemp = (uint8_t)(rawData & RF_STATUS_TEMP_MASK);
+	instPtr->hwSate.antTemp = (uint8_t)(rawData & ANT_RF_STATUS_TEMP_MASK);
 	// -- Update Antenna PLL Lock Status: 1 - normal, 0 - error
 	//    [0] - BASEBAND lock status
 	//    [2] - PLLA lock status
 	//    [4] - PLLB lock status
-	instPtr->hwSate.antPll = (rawData & RF_STATUS_BDLOCK_MASK) ? 0x01 : 0x00;
-	instPtr->hwSate.antPll |= (rawData & RF_STATUS_PLLA_MASK) ? 0x04 : 0x00;
-	instPtr->hwSate.antPll |= (rawData & RF_STATUS_PLLB_MASK) ? 0x10 : 0x00;
+	instPtr->hwSate.antPll = ((rawData & ANT_RF_STATUS_BBLOCK_MASK) == ANT_RF_STATUS_BBLOCK_OK) ? CLK_ANT_BBPLL_LOCK : 0x00;
+	instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLA_MASK) == ANT_RF_STATUS_PLLA_OK) ? CLK_ANT_RFPLL0_LOCK : 0x00;
+	instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLB_MASK) == ANT_RF_STATUS_PLLB_OK) ? CLK_ANT_RFPLL1_LOCK : 0x00;
 
 	/*** MGCs ***/
-	rawData = PhyRead(instPtr, RF_MGC);
+	rawData = PhyRead(instPtr, ANT_RF_MGC);
 	// -- Update Antenna MGC (0~15 dB)
 	//    [3:0] - Channel 1 MGC
 	//    [7:4] - Channel 2 MGC
 	//    [11:8] - Channel 3 MGC
 	//    [15:12] - Channel 4 MGC
-	instPtr->hwSate.antMgc = (rawData & RF_MGC_CH1_MASK);
-	instPtr->hwSate.antMgc |= (rawData & RF_MGC_CH2_MASK) >> 4;
-	instPtr->hwSate.antMgc |= (rawData & RF_MGC_CH3_MASK) >> 8;
-	instPtr->hwSate.antMgc |= (rawData & RF_MGC_CH4_MASK) >> 12;
+	instPtr->hwSate.antMgc0 = (rawData & ANT_RF_MGC_CH1_MASK);
+	instPtr->hwSate.antMgc0 |= (rawData & ANT_RF_MGC_CH2_MASK) >> 4;
+	instPtr->hwSate.antMgc1 = (rawData & ANT_RF_MGC_CH3_MASK) >> 16;
+	instPtr->hwSate.antMgc1 |= (rawData & ANT_RF_MGC_CH4_MASK) >> 24;
+
+	// Determin if antenna is ok.
+	instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK & VOLT_ANT_RF_OK & VOLT_ANT_NIL_OK & ANT_STATE_OK))
+								&& (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK & CLK_ANT_RFPLL0_LOCK & CLK_ANT_RFPLL1_LOCK));
+
+	memset(instPtr->hwSate.reserve, 0x00, sizeof(instPtr->hwSate.reserve));
+
 	SysMonitor_UpdateHardwareStatus(&(instPtr->hwSate));
 }

df_datalink_sp/src/networking/phy_layer/phy_layer.h

@@ -183,6 +183,12 @@ typedef struct
 	uint32_t antBramId;
 	uint32_t hwXadcId;
 	uintptr_t baseAddr;
+#ifndef EMULATION
+	uint8_t (*get_clk_state)(void);
+	uint8_t (*get_ad_lock_state)(void);
+	int8_t (*get_ad0_temp)(void);
+	int8_t (*get_ad1_temp)(void);
+#endif
 } PHY_CONFIG;
 
 typedef struct
@@ -218,6 +224,7 @@ typedef struct
 	XAdcPs hwXadc;
 #endif
 	HWSTATE hwSate;
+	PHYLOG phyLog;
 } PHY_INST;
 
 /************************** Variable Definitions *****************************/
@@ -240,7 +247,7 @@ int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig);
 void Phy_Destroy(PHY_INST *instPtr);
 
 void Phy_UpdateState(PHY_INST *instPtr);
-void Phy_UpdateHwSate(PHY_INST *instPtr);
+void Phy_RefreshHwSate(PHY_INST *instPtr);
 
 void Phy_Start(PHY_INST *instPtr);
 void Phy_Halt(PHY_INST *instPtr);

df_datalink_sp/src/networking/phy_layer/phy_reg.h

@@ -10,7 +10,7 @@
  * History:
  * [2021-11-16]: Initial version.
  * [2022-06-18]: New branch for glink control purpose:
- *               -Add poll modephysical layer will start Tx/Rx procedure
+ *               -Add poll mode physical layer will start Tx/Rx procedure
  * 				  at specific time stamp.
  * [2023-04-24]: Porting for DUIFEI.
  *
@@ -33,7 +33,7 @@
 /**
  * Register: PHY_MAIN_CTRL
  */
-#define PHY_MAIN_CTRL 0X00000000U
+#define PHY_MAIN_CTRL 0x00000000U
 #define PHY_MAIN_CTRL_EN_SHIFT 0
 #define PHY_MAIN_CTRL_EN_WIDTH 1
 #define PHY_MAIN_CTRL_EN_MASK 0x00000001U
@@ -275,70 +275,216 @@
 #define BEAM_AXIS_AZ_MASK 0xFFFF0000U
 
 /**
- * Register: ANT_STATUS_0
+ * Register: ANT_STATUS
  */
-#define ANT_STATUS 0x00000048U
-#define ANT_STATUS_CODE_SHIFT 0
-#define ANT_STATUS_CODE_WIDTH 8
-#define ANT_STATUS_CODE_MASK 0x000000FFU
-#define ANT_STATUS_NIL_VOLT_SHIFT 8
-#define ANT_STATUS_NIL_VOLT_WIDTH 8
-#define ANT_STATUS_NIL_VOLT_MASK 0x0000FF00U
-#define ANT_STATUS_RF_VOLT_SHIFT 16
-#define ANT_STATUS_RF_VOLT_WIDTH 8
-#define ANT_STATUS_RF_VOLT_MASK 0x00FF0000U
-#define ANT_STATUS_ANT_VOLT_SHIFT 24
+#define ANT_STATUS 0x00000100U
+#define ANT_STATUS_ANT_VOLT_SHIFT 0
 #define ANT_STATUS_ANT_VOLT_WIDTH 8
-#define ANT_STATUS_ANT_VOLT_MASK 0xFF000000U
+#define ANT_STATUS_ANT_VOLT_MASK 0x000000FFU
+#define ANT_STATUS_ANT_VOLT_OK 0x00000001U
+
+#define ANT_STATUS_RF_VOLT_SHIFT 8
+#define ANT_STATUS_RF_VOLT_WIDTH 8
+#define ANT_STATUS_RF_VOLT_MASK 0x0000FF00U
+#define ANT_STATUS_RF_VOLT_OK 0x00000100U
+
+#define ANT_STATUS_NIL_VOLT_SHIFT 16
+#define ANT_STATUS_NIL_VOLT_WIDTH 8
+#define ANT_STATUS_NIL_VOLT_MASK 0x00FF0000U
+#define ANT_STATUS_NIL_VOLT_OK 0x00010000U
+
+#define ANT_STATUS_CODE_SHIFT 24
+#define ANT_STATUS_CODE_WIDTH 8
+#define ANT_STATUS_CODE_MASK 0xFF000000U
+#define ANT_STATUS_CODE_OK 0x00000000U
 
 /**
  * Register: ANT_FRAME_CNT
  */
-#define ANT_FRAME_CNT 0x0000004CU
+#define ANT_FRAME_CNT 0x00000104U
 #define ANT_FRAME_CNT_SHIFT 0
 #define ANT_FRAME_CNT_WIDTH 32
 #define ANT_FRAME_CNT_MASK 0xFFFFFFFFU
 
 /**
- * Register: RF_STATUS
+ * Register: ANT_RF_STATUS
  */
-#define RF_STATUS 0x00000050U
-#define RF_STATUS_TEMP_SHIFT 0
-#define RF_STATUS_TEMP_WIDTH 8
-#define RF_STATUS_TEMP_MASK 0x000000FFU
-#define RF_STATUS_BDLOCK_SHIFT 8
-#define RF_STATUS_BDLOCK_WIDTH 8
-#define RF_STATUS_BDLOCK_MASK 0x0000FF00U
-#define RF_STATUS_PLLA_SHIFT 16
-#define RF_STATUS_PLLA_WIDTH 8
-#define RF_STATUS_PLLA_MASK 0x00FF0000U
-#define RF_STATUS_PLLB_SHIFT 24
-#define RF_STATUS_PLLB_WIDTH 8
-#define RF_STATUS_PLLB_MASK 0xFF000000U
+#define ANT_RF_STATUS 0x00000108U
+#define ANT_RF_STATUS_TEMP_SHIFT 0
+#define ANT_RF_STATUS_TEMP_WIDTH 8
+#define ANT_RF_STATUS_TEMP_MASK 0x000000FFU
+
+#define ANT_RF_STATUS_BBLOCK_SHIFT 8
+#define ANT_RF_STATUS_BBLOCK_WIDTH 8
+#define ANT_RF_STATUS_BBLOCK_MASK 0x0000FF00U
+#define ANT_RF_STATUS_BBLOCK_OK 0x00000100U
+
+#define ANT_RF_STATUS_PLLA_SHIFT 16
+#define ANT_RF_STATUS_PLLA_WIDTH 8
+#define ANT_RF_STATUS_PLLA_MASK 0x00FF0000U
+#define ANT_RF_STATUS_PLLA_OK 0x00010000U
+
+#define ANT_RF_STATUS_PLLB_SHIFT 24
+#define ANT_RF_STATUS_PLLB_WIDTH 8
+#define ANT_RF_STATUS_PLLB_MASK 0xFF000000U
+#define ANT_RF_STATUS_PLLB_OK 0x01000000U
 
 /**
- * Register: RF_MGC
+ * Register: ANT_RF_MGC
  */
-#define RF_MGC 0x00000054U
-#define RF_MGC_CH1_SHIFT 0
-#define RF_MGC_CH1_WIDTH 4
-#define RF_MGC_CH1_MASK 0x0000000FU
-#define RF_MGC_CH2_SHIFT 8
-#define RF_MGC_CH2_WIDTH 4
-#define RF_MGC_CH2_MASK 0x00000F00U
-#define RF_MGC_CH3_SHIFT 16
-#define RF_MGC_CH3_WIDTH 4
-#define RF_MGC_CH3_MASK 0x000F0000U
-#define RF_MGC_CH4_SHIFT 24
-#define RF_MGC_CH4_WIDTH 4
-#define RF_MGC_CH4_MASK 0x0F000000U
+#define ANT_RF_MGC 0x0000010CU
+#define ANT_RF_MGC_CH1_SHIFT 0
+#define ANT_RF_MGC_CH1_WIDTH 4
+#define ANT_RF_MGC_CH1_MASK 0x0000000FU
+#define ANT_RF_MGC_CH2_SHIFT 8
+#define ANT_RF_MGC_CH2_WIDTH 4
+#define ANT_RF_MGC_CH2_MASK 0x00000F00U
+#define ANT_RF_MGC_CH3_SHIFT 16
+#define ANT_RF_MGC_CH3_WIDTH 4
+#define ANT_RF_MGC_CH3_MASK 0x000F0000U
+#define ANT_RF_MGC_CH4_SHIFT 24
+#define ANT_RF_MGC_CH4_WIDTH 4
+#define ANT_RF_MGC_CH4_MASK 0x0F000000U
 
 /**
- * Register: RF_FRAME_CNT
+ * Register: ANT_RF_FRAME_CNT
  */
-#define RF_FRAME_CNT 0x00000058U
-#define RF_FRAME_CNT_SHIFT 0
-#define RF_FRAME_CNT_WIDTH 32
-#define RF_FRAME_CNT_MASK 0xFFFFFFFFU
+#define ANT_RF_FRAME_CNT 0x00000110U
+#define ANT_RF_FRAME_CNT_SHIFT 0
+#define ANT_RF_FRAME_CNT_WIDTH 32
+#define ANT_RF_FRAME_CNT_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_ACQ_CNT
+ */
+#define PHY_ACQ_CNT 0x00000114U
+#define PHY_ACQ_CNT_SHIFT 0
+#define PHY_ACQ_CNT_WIDTH 32
+#define PHY_ACQ_CNT_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_FRAME_SYNC_CNT
+ */
+#define PHY_FRAME_SYNC_CNT 0x00000118U
+#define PHY_FRAME_SYNC_CNT_SHIFT 0
+#define PHY_FRAME_SYNC_CNT_WIDTH 32
+#define PHY_FRAME_SYNC_CNT_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_DECODE_CNT
+ */
+#define PHY_DECODE_CNT 0x0000011CU
+#define PHY_DECODE_CNT_SHIFT 0
+#define PHY_DECODE_CNT_WIDTH 32
+#define PHY_DECODE_CNT_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_CRC_OK_CNT
+ */
+#define PHY_CRC_OK_CNT 0x00000120U
+#define PHY_CRC_OK_CNT_SHIFT 0
+#define PHY_CRC_OK_CNT_WIDTH 32
+#define PHY_CRC_OK_CNT_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_ACQ_PEAK_H
+ */
+#define PHY_ACQ_PEAK_H 0x00000124U
+#define PHY_ACQ_PEAK_H_SHIFT 0
+#define PHY_ACQ_PEAK_H_WIDTH 32
+#define PHY_ACQ_PEAK_H_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_ACQ_PEAK_L
+ */
+#define PHY_ACQ_PEAK_L 0x00000128U
+#define PHY_ACQ_PEAK_L_SHIFT 0
+#define PHY_ACQ_PEAK_L_WIDTH 32
+#define PHY_ACQ_PEAK_L_MASK 0xFFFFFFFFU
+
+
+/**
+ * Register: PHY_ACQ_MEAN_H
+ */
+#define PHY_ACQ_MEAN_H 0x0000012CU
+#define PHY_ACQ_MEAN_H_SHIFT 0
+#define PHY_ACQ_MEAN_H_WIDTH 32
+#define PHY_ACQ_MEAN_H_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_ACQ_MEAN_L
+ */
+#define PHY_ACQ_MEAN_L 0x00000130U
+#define PHY_ACQ_MEAN_L_SHIFT 0
+#define PHY_ACQ_MEAN_L_WIDTH 32
+#define PHY_ACQ_MEAN_L_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_ACQ_FREQEST
+ */
+#define PHY_ACQ_FREQEST 0x00000134U
+#define PHY_ACQ_FREQEST_SHIFT 0
+#define PHY_ACQ_FREQEST_WIDTH 32
+#define PHY_ACQ_FREQEST_MASK 0xFFFFFFFFU
+
+#define PHY_ACQ_FREQEST_PHASE_SHIFT 0
+#define PHY_ACQ_FREQEST_PHASE_WIDTH 8
+#define PHY_ACQ_FREQEST_PHASE_MASK 0x000000FFU
+#define PHY_ACQ_FREQEST_CHANNEL_SHIFT 8
+#define PHY_ACQ_FREQEST_CHANNEL_WIDTH 8
+#define PHY_ACQ_FREQEST_CHANNEL_MASK 0x0000FF00U
+
+/**
+ * Register: PHY_FRAME_SYNC_PEAK_H
+ */
+#define PHY_FRAME_SYNC_PEAK_H 0x00000138U
+#define PHY_FRAME_SYNC_PEAK_H_SHIFT 0
+#define PHY_FRAME_SYNC_PEAK_H_WIDTH 32
+#define PHY_FRAME_SYNC_PEAK_H_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_FRAME_SYNC_PEAK_L
+ */
+#define PHY_FRAME_SYNC_PEAK_L 0x0000013CU
+#define PHY_FRAME_SYNC_PEAK_L_SHIFT 0
+#define PHY_FRAME_SYNC_PEAK_L_WIDTH 32
+#define PHY_FRAME_SYNC_PEAK_L_MASK 0xFFFFFFFFU
+
+
+/**
+ * Register: PHY_FRAME_SYNC_MEAN_H
+ */
+#define PHY_FRAME_SYNC_MEAN_H 0x00000140U
+#define PHY_FRAME_SYNC_MEAN_H_SHIFT 0
+#define PHY_FRAME_SYNC_MEAN_H_WIDTH 32
+#define PHY_FRAME_SYNC_MEAN_H_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_FRAME_SYNC_MEAN_L
+ */
+#define PHY_FRAME_SYNC_MEAN_L 0x00000144U
+#define PHY_FRAME_SYNC_MEAN_L_SHIFT 0
+#define PHY_FRAME_SYNC_MEAN_L_WIDTH 32
+#define PHY_FRAME_SYNC_MEAN_L_MASK 0xFFFFFFFFU
+
+/**
+ * Register: PHY_FRAME_SYNC_FREQEST
+ */
+#define PHY_FRAME_SYNC_FREQEST 0x00000148U
+#define PHY_FRAME_SYNC_FREQEST_SHIFT 0
+#define PHY_FRAME_SYNC_FREQEST_WIDTH 32
+#define PHY_FRAME_SYNC_FREQEST_MASK 0xFFFFFFFFU
+
+#define PHY_FRAME_SYNC_FREQEST_CHANNEL_SHIFT 0
+#define PHY_FRAME_SYNC_FREQEST_CHANNEL_WIDTH 8
+#define PHY_FRAME_SYNC_FREQEST_CHANNEL_MASK 0x000000FFU
+
+/**
+ * Register: PHY_DEINTLV_AMPEST
+ */
+#define PHY_DEINTLV_AMPEST 0x0000014CU
+#define PHY_DEINTLV_AMPEST_SHIFT 0
+#define PHY_DEINTLV_AMPEST_WIDTH 16
+#define PHY_DEINTLV_AMPEST_MASK 0x0000FFFFU
 
 #endif /* PHY_REG_H_ */

df_datalink_sp/src/system_monitor.c

@@ -23,18 +23,16 @@ typedef struct
 
 typedef struct
 {
-	PINGPONG recvPLCtrl;
-	PAYLOAD recvPL[2];
-	PINGPONG sendPLCtrl;
-	PAYLOAD sendPL[2];
+	PINGPONG recvCtrl;
+	PAYLOAD recv[2];
+	PINGPONG sendCtrl;
+	PAYLOAD send[2];
 	PINGPONG sysInfoCtrl;
 	SYSINFO sysInfo[2];
-	PINGPONG sendLogCtrl;
-	SLOTLOG sendLog[2];
-	PINGPONG recvLogCtrl;
-	SLOTLOG recvLog[2];
-	PINGPONG protocolLogCtrl;
-	PRTCLLOG protocolLog[2];
+	PINGPONG linkLogCtrl;
+	LINKLOG linkLog[2];
+	PINGPONG phyLogCtrl;
+	PHYLOG phyLog[2];
 	PINGPONG hwStateCtrl;
 	HWSTATE hwState[2];
 } SYSMONITOR;
@@ -70,22 +68,17 @@ int32_t SysMonitor_Init(void)
 	{
 		return ENOMEM;
 	}
-	memset(&(sysMonitorInst->recvPLCtrl), BUFF_NONE, sizeof(PINGPONG));
-	memset(&(sysMonitorInst->sendPLCtrl), BUFF_NONE, sizeof(PINGPONG));
+	memset(&(sysMonitorInst->recvCtrl), BUFF_NONE, sizeof(PINGPONG));
+	memset(&(sysMonitorInst->sendCtrl), BUFF_NONE, sizeof(PINGPONG));
 	memset(&(sysMonitorInst->sysInfoCtrl), BUFF_NONE, sizeof(PINGPONG));
-	memset(&(sysMonitorInst->sendLogCtrl), BUFF_NONE, sizeof(PINGPONG));
-	memset(&(sysMonitorInst->recvLogCtrl), BUFF_NONE, sizeof(PINGPONG));
-	memset(&(sysMonitorInst->protocolLogCtrl), BUFF_NONE, sizeof(PINGPONG));
+	memset(&(sysMonitorInst->linkLogCtrl), BUFF_NONE, sizeof(PINGPONG));
+	memset(&(sysMonitorInst->phyLogCtrl), BUFF_NONE, sizeof(PINGPONG));
 	memset(&(sysMonitorInst->hwStateCtrl), BUFF_NONE, sizeof(PINGPONG));
 
-	sysMonitorInst->recvPL[0].dataId_flj = DATA_ID_NONE;
-	sysMonitorInst->recvPL[0].dataId_lj = DATA_ID_NONE;
-	sysMonitorInst->recvPL[1].dataId_flj = DATA_ID_NONE;
-	sysMonitorInst->recvPL[1].dataId_lj = DATA_ID_NONE;
-	sysMonitorInst->sendPL[0].dataId_flj = DATA_ID_NONE;
-	sysMonitorInst->sendPL[0].dataId_lj = DATA_ID_NONE;
-	sysMonitorInst->sendPL[1].dataId_flj = DATA_ID_NONE;
-	sysMonitorInst->sendPL[1].dataId_lj = DATA_ID_NONE;
+	sysMonitorInst->recv[0].dataId = DATA_ID_NONE;
+	sysMonitorInst->recv[1].dataId = DATA_ID_NONE;
+	sysMonitorInst->send[0].dataId = DATA_ID_NONE;
+	sysMonitorInst->send[1].dataId = DATA_ID_NONE;
 	return SUCCESS;
 }
 
@@ -96,7 +89,10 @@ void SysMonitor_Destroy(void)
 }
 
 // @System Info
-void SysMonitor_UpdateSysinfo(SYSINFO *info)
+/**
+ * Update system info.
+ */
+void SysMonitor_UpdateSysinfo(const SYSINFO *info)
 {
 	uint8_t buffIndx;
 	buffIndx = GetWritable(sysMonitorInst->sysInfoCtrl);
@@ -106,49 +102,9 @@ void SysMonitor_UpdateSysinfo(SYSINFO *info)
 	sysMonitorInst->sysInfoCtrl.wBusy = BUFF_NONE;
 }
 
-void SysMonitor_UpdateSysinfoRaw(uint8_t *buff)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx;
-	buffIndx = GetWritable(sysMonitorInst->sysInfoCtrl);
-	sysMonitorInst->sysInfoCtrl.wBusy = buffIndx;
-	// Decapsulate Systeminfo
-	SYSINFO *infoEntry = &(sysMonitorInst->sysInfo[buffIndx]);
-	memcpy(&(infoEntry->psBDS), buff, sizeof(infoEntry->psBDS));
-	buff += sizeof(infoEntry->psBDS);
-	memcpy(&(infoEntry->pBDS), buff, sizeof(infoEntry->pBDS));
-	buff += sizeof(infoEntry->pBDS);
-	memcpy(&(infoEntry->psGPS), buff, sizeof(infoEntry->psGPS));
-	buff += sizeof(infoEntry->psGPS);
-	memcpy(&(infoEntry->pGPS), buff, sizeof(infoEntry->pGPS));
-	buff += sizeof(infoEntry->pGPS);
-	memcpy(&(infoEntry->tmInd), buff, sizeof(infoEntry->tmInd));
-	buff += sizeof(infoEntry->tmInd);
-	memcpy(&(infoEntry->tmFly), buff, sizeof(infoEntry->tmFly));
-	buff += sizeof(infoEntry->tmFly);
-	memcpy(&(infoEntry->stFly), buff, sizeof(infoEntry->stFly));
-	buff += sizeof(infoEntry->stFly);
-	memcpy(&(infoEntry->posX), buff, sizeof(infoEntry->posX));
-	buff += sizeof(infoEntry->posX);
-	memcpy(&(infoEntry->posY), buff, sizeof(infoEntry->posY));
-	buff += sizeof(infoEntry->posY);
-	memcpy(&(infoEntry->posZ), buff, sizeof(infoEntry->posZ));
-	buff += sizeof(infoEntry->posZ);
-	memcpy(&(infoEntry->vX), buff, sizeof(infoEntry->vX));
-	buff += sizeof(infoEntry->vX);
-	memcpy(&(infoEntry->vY), buff, sizeof(infoEntry->vY));
-	buff += sizeof(infoEntry->vY);
-	memcpy(&(infoEntry->vZ), buff, sizeof(infoEntry->vZ));
-	buff += sizeof(infoEntry->vZ);
-	memcpy(&(infoEntry->pitch), buff, sizeof(infoEntry->pitch));
-	buff += sizeof(infoEntry->pitch);
-	memcpy(&(infoEntry->yaw), buff, sizeof(infoEntry->yaw));
-	buff += sizeof(infoEntry->yaw);
-	memcpy(&(infoEntry->roll), buff, sizeof(infoEntry->roll));
-	sysMonitorInst->sysInfoCtrl.latest = buffIndx;
-	sysMonitorInst->sysInfoCtrl.wBusy = BUFF_NONE;
-}
-
+/**
+ * Get system info.
+ */
 void SysMonitor_GetSysinfo(SYSINFO *info)
 {
 	ASSERT(sysMonitorInst != NULL);
@@ -163,395 +119,150 @@ void SysMonitor_GetSysinfo(SYSINFO *info)
 	sysMonitorInst->sysInfoCtrl.rBusy = buffIndex_old;
 }
 
-void SysMonitor_GetSysinfoRaw(uint8_t *buff)
-{
-	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->sysInfoCtrl.rBusy;
-	if (buffIndex_old != BUFF_NONE)
-		buffIndx = buffIndex_old; // Keep it busy
-	else
-		buffIndx = GetReadable(sysMonitorInst->sysInfoCtrl);
-	sysMonitorInst->sysInfoCtrl.rBusy = buffIndx;
-
-	// Encapsulate Systeminfo
-	SYSINFO *infoEntry = &(sysMonitorInst->sysInfo[buffIndx]);
-	memcpy(buff, &(infoEntry->psBDS), sizeof(infoEntry->psBDS));
-	buff += sizeof(infoEntry->psBDS);
-	memcpy(buff, &(infoEntry->pBDS), sizeof(infoEntry->pBDS));
-	buff += sizeof(infoEntry->pBDS);
-	memcpy(buff, &(infoEntry->psGPS), sizeof(infoEntry->psGPS));
-	buff += sizeof(infoEntry->psGPS);
-	memcpy(buff, &(infoEntry->pGPS), sizeof(infoEntry->pGPS));
-	buff += sizeof(infoEntry->pGPS);
-	memcpy(buff, &(infoEntry->tmInd), sizeof(infoEntry->tmInd));
-	buff += sizeof(infoEntry->tmInd);
-	memcpy(buff, &(infoEntry->tmFly), sizeof(infoEntry->tmFly));
-	buff += sizeof(infoEntry->tmFly);
-	memcpy(buff, &(infoEntry->stFly), sizeof(infoEntry->stFly));
-	buff += sizeof(infoEntry->stFly);
-	memcpy(buff, &(infoEntry->posX), sizeof(infoEntry->posX));
-	buff += sizeof(infoEntry->posX);
-	memcpy(buff, &(infoEntry->posY), sizeof(infoEntry->posY));
-	buff += sizeof(infoEntry->posY);
-	memcpy(buff, &(infoEntry->posZ), sizeof(infoEntry->posZ));
-	buff += sizeof(infoEntry->posZ);
-	memcpy(buff, &(infoEntry->vX), sizeof(infoEntry->vX));
-	buff += sizeof(infoEntry->vX);
-	memcpy(buff, &(infoEntry->vY), sizeof(infoEntry->vY));
-	buff += sizeof(infoEntry->vY);
-	memcpy(buff, &(infoEntry->vZ), sizeof(infoEntry->vZ));
-	buff += sizeof(infoEntry->vZ);
-	memcpy(buff, &(infoEntry->pitch), sizeof(infoEntry->pitch));
-	buff += sizeof(infoEntry->pitch);
-	memcpy(buff, &(infoEntry->yaw), sizeof(infoEntry->yaw));
-	buff += sizeof(infoEntry->yaw);
-	memcpy(buff, &(infoEntry->roll), sizeof(infoEntry->roll));
-	sysMonitorInst->sysInfoCtrl.rBusy = buffIndex_old;
-}
 // @Send Payload
 /**
- * Update send FLJ payload by raw data.
+ * Update send payload by.
  */
-void SysMonitor_UpdateSendPayloadFLJRaw(uint8_t *buff)
+void SysMonitor_UpdateSendPayload(const uint8_t *buff, size_t len)
 {
 	ASSERT(sysMonitorInst != NULL);
 	uint8_t buffIndx;
-	buffIndx = GetWritable(sysMonitorInst->sendPLCtrl);
-	sysMonitorInst->sendPLCtrl.wBusy = buffIndx;
-	memcpy(sysMonitorInst->sendPL[buffIndx].data_flj, buff, sizeof(uint8_t) * PAYLOAD_FLJ_TX);
-	sysMonitorInst->sendPL[buffIndx].dataId_flj++;
-	sysMonitorInst->sendPLCtrl.latest = buffIndx;
-	sysMonitorInst->sendPLCtrl.wBusy = BUFF_NONE;
+	buffIndx = GetWritable(sysMonitorInst->sendCtrl);
+	sysMonitorInst->sendCtrl.wBusy = buffIndx;
+	memcpy(sysMonitorInst->send[buffIndx].data, buff, len);
+	sysMonitorInst->send[buffIndx].dataId++;
+	sysMonitorInst->sendCtrl.latest = buffIndx;
+	sysMonitorInst->sendCtrl.wBusy = BUFF_NONE;
 }
 
 /**
- * Get send FLJ payload as raw data.
+ * Get the latest send payload.
  */
-void SysMonitor_GetSendPayloadFLJRaw(uint8_t *buff, uint32_t *id)
+void SysMonitor_GetSendPayload(uint8_t *buff, uint32_t *id, size_t len)
 {
 	ASSERT(sysMonitorInst != NULL);
 	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->sendPLCtrl.rBusy;
+	buffIndex_old = sysMonitorInst->sendCtrl.rBusy;
 	if (buffIndex_old != BUFF_NONE)
 		buffIndx = buffIndex_old; // Keep it busy
 	else
-		buffIndx = GetReadable(sysMonitorInst->sendPLCtrl);
-	sysMonitorInst->sendPLCtrl.rBusy = buffIndx;
-	if (sysMonitorInst->sendPL[buffIndx].dataId_flj != DATA_ID_NONE)
+		buffIndx = GetReadable(sysMonitorInst->sendCtrl);
+	sysMonitorInst->sendCtrl.rBusy = buffIndx;
+	if (sysMonitorInst->send[buffIndx].dataId != DATA_ID_NONE)
 	{
-		memcpy(buff, sysMonitorInst->sendPL[buffIndx].data_flj, sizeof(uint8_t) * PAYLOAD_FLJ_TX);
+		memcpy(buff, sysMonitorInst->send[buffIndx].data, len);
 	}
-	*id = sysMonitorInst->sendPL[buffIndx].dataId_flj;
-	sysMonitorInst->sendPLCtrl.rBusy = buffIndex_old;
-}
-
-/**
- * Update LJ send payload by raw data.
- */
-void SysMonitor_UpdateSendPayloadLJRaw(uint8_t *buff)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx;
-	buffIndx = GetWritable(sysMonitorInst->sendPLCtrl);
-	sysMonitorInst->sendPLCtrl.wBusy = buffIndx;
-	memcpy(sysMonitorInst->sendPL[buffIndx].data_lj, buff, sizeof(uint8_t) * PAYLOAD_LJ_TX);
-	sysMonitorInst->sendPL[buffIndx].dataId_lj++;
-	sysMonitorInst->sendPLCtrl.latest = buffIndx;
-	sysMonitorInst->sendPLCtrl.wBusy = BUFF_NONE;
-}
-
-/**
- * Get send LJ payload as raw data.
- */
-void SysMonitor_GetSendPayloadLJRaw(uint8_t *buff, uint32_t *id)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->sendPLCtrl.rBusy;
-	if (buffIndex_old != BUFF_NONE)
-		buffIndx = buffIndex_old; // Keep it busy
-	else
-		buffIndx = GetReadable(sysMonitorInst->sendPLCtrl);
-	sysMonitorInst->sendPLCtrl.rBusy = buffIndx;
-	if (sysMonitorInst->sendPL[buffIndx].dataId_lj != DATA_ID_NONE) 
-	{
-		memcpy(buff, sysMonitorInst->sendPL[buffIndx].data_lj, sizeof(uint8_t) * PAYLOAD_LJ_TX);
-	}
-	*id = sysMonitorInst->sendPL[buffIndx].dataId_lj;
-	sysMonitorInst->sendPLCtrl.rBusy = buffIndex_old;
+	*id = sysMonitorInst->send[buffIndx].dataId;
+	sysMonitorInst->sendCtrl.rBusy = buffIndex_old;
 }
 
 // @Receive Payload
 /**
- * Update receive FLJ payload by raw data.
+ * Update receive payload.
  */
-void SysMonitor_UpdateRecvPayloadFLJRaw(uint8_t *buff)
+void SysMonitor_UpdateRecvPayload(const uint8_t *buff, size_t len)
 {
 	ASSERT(sysMonitorInst != NULL);
 	uint8_t buffIndx;
-	buffIndx = GetWritable(sysMonitorInst->recvPLCtrl);
-	sysMonitorInst->recvPLCtrl.wBusy = buffIndx;
-	memcpy(sysMonitorInst->recvPL[buffIndx].data_flj, buff, sizeof(uint8_t) * PAYLOAD_FLJ_RX);
-	sysMonitorInst->recvPL[buffIndx].dataId_flj++;
-	sysMonitorInst->recvPLCtrl.latest = buffIndx;
-	sysMonitorInst->recvPLCtrl.wBusy = BUFF_NONE;
+	buffIndx = GetWritable(sysMonitorInst->recvCtrl);
+	sysMonitorInst->recvCtrl.wBusy = buffIndx;
+	memcpy(sysMonitorInst->recv[buffIndx].data, buff, len);
+	sysMonitorInst->recv[buffIndx].dataId++;
+	sysMonitorInst->recvCtrl.latest = buffIndx;
+	sysMonitorInst->recvCtrl.wBusy = BUFF_NONE;
 }
 
 /**
- * Get send FLJ payload as raw data.
+ * Get the latest receive payload.
  */
-void SysMonitor_GetRecvPayloadFLJRaw(uint8_t *buff, uint32_t *id)
+void SysMonitor_GetRecvPayload(uint8_t *buff, uint32_t *id, size_t len)
 {
 	ASSERT(sysMonitorInst != NULL);
 	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->recvPLCtrl.rBusy;
+	buffIndex_old = sysMonitorInst->recvCtrl.rBusy;
 	if (buffIndex_old != BUFF_NONE)
 		buffIndx = buffIndex_old; // Keep it busy
 	else
-		buffIndx = GetReadable(sysMonitorInst->recvPLCtrl);
-	sysMonitorInst->recvPLCtrl.rBusy = buffIndx;
-	if (sysMonitorInst->recvPL[buffIndx].dataId_flj != DATA_ID_NONE)
+		buffIndx = GetReadable(sysMonitorInst->recvCtrl);
+	sysMonitorInst->recvCtrl.rBusy = buffIndx;
+	if (sysMonitorInst->recv[buffIndx].dataId != DATA_ID_NONE)
 	{
-		memcpy(buff, sysMonitorInst->recvPL[buffIndx].data_flj, sizeof(uint8_t) * PAYLOAD_FLJ_RX);
+		memcpy(buff, sysMonitorInst->recv[buffIndx].data, len);
 	}
-	*id = sysMonitorInst->recvPL[buffIndx].dataId_flj;
-	sysMonitorInst->recvPLCtrl.rBusy = buffIndex_old;
+	*id = sysMonitorInst->recv[buffIndx].dataId;
+	sysMonitorInst->recvCtrl.rBusy = buffIndex_old;
 }
 
+// @Link layer log
 /**
- * Update receive LJ payload by raw data.
+ * Update link layer log
  */
-void SysMonitor_UpdateRecvPayloadLJRaw(uint8_t *buff)
+void SysMonitor_UpdateLinklayerLog(const LINKLOG *log)
 {
 	ASSERT(sysMonitorInst != NULL);
 	uint8_t buffIndx;
-	buffIndx = GetWritable(sysMonitorInst->recvPLCtrl);
-	sysMonitorInst->recvPLCtrl.wBusy = buffIndx;
-	memcpy(sysMonitorInst->recvPL[buffIndx].data_lj, buff, sizeof(uint8_t) * PAYLOAD_LJ_RX);
-	sysMonitorInst->recvPL[buffIndx].dataId_lj++;
-	sysMonitorInst->recvPLCtrl.latest = buffIndx;
-	sysMonitorInst->recvPLCtrl.wBusy = BUFF_NONE;
+	buffIndx = GetWritable(sysMonitorInst->linkLogCtrl);
+	sysMonitorInst->linkLogCtrl.wBusy = buffIndx;
+	memcpy(&(sysMonitorInst->linkLog[buffIndx]), log, sizeof(LINKLOG));
+	sysMonitorInst->linkLogCtrl.latest = buffIndx;
+	sysMonitorInst->linkLogCtrl.wBusy = BUFF_NONE;
 }
 
 /**
- * Get send LJ payload as raw data.
+ * Get the latest link layer log
  */
-void SysMonitor_GetRecvPayloadLJRaw(uint8_t *buff, uint32_t *id)
+void SysMonitor_GetLinklayerLog(LINKLOG *log)
 {
 	ASSERT(sysMonitorInst != NULL);
 	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->recvPLCtrl.rBusy;
+	buffIndex_old = sysMonitorInst->linkLogCtrl.rBusy;
 	if (buffIndex_old != BUFF_NONE)
 		buffIndx = buffIndex_old; // Keep it busy
 	else
-		buffIndx = GetReadable(sysMonitorInst->recvPLCtrl);
-	sysMonitorInst->recvPLCtrl.rBusy = buffIndx;
-	if (sysMonitorInst->recvPL[buffIndx].dataId_lj != DATA_ID_NONE) 
-	{
-		memcpy(buff, sysMonitorInst->recvPL[buffIndx].data_lj, sizeof(uint8_t) * PAYLOAD_LJ_RX);
-	}
-	*id = sysMonitorInst->recvPL[buffIndx].dataId_lj;
-	sysMonitorInst->recvPLCtrl.rBusy = buffIndex_old;
+		buffIndx = GetReadable(sysMonitorInst->linkLogCtrl);
+	sysMonitorInst->linkLogCtrl.rBusy = buffIndx;
+	memcpy(log, &(sysMonitorInst->linkLog[buffIndx]), sizeof(LINKLOG));
+	sysMonitorInst->linkLogCtrl.rBusy = buffIndex_old;
 }
 
-//  @Send Slot log
+// @Physical layer log
 /**
- * Log send slot information
+ * Update physical layer log
  */
-void SysMonitor_UpdateSendSlotLog(SLOTLOG *log)
+void SysMonitor_UpdatePhysicalLayerLog(const PHYLOG *log)
 {
 	ASSERT(sysMonitorInst != NULL);
 	uint8_t buffIndx;
-	buffIndx = GetWritable(sysMonitorInst->sendLogCtrl);
-	sysMonitorInst->sendLogCtrl.wBusy = buffIndx;
-	memcpy(&(sysMonitorInst->sendLog[buffIndx]), log, sizeof(SLOTLOG));
-	sysMonitorInst->sendLogCtrl.latest = buffIndx;
-	sysMonitorInst->sendLogCtrl.wBusy = BUFF_NONE;
+	buffIndx = GetWritable(sysMonitorInst->phyLogCtrl);
+	sysMonitorInst->phyLogCtrl.wBusy = buffIndx;
+	memcpy(&(sysMonitorInst->phyLog[buffIndx]), log, sizeof(PHYLOG));
+	sysMonitorInst->phyLogCtrl.latest = buffIndx;
+	sysMonitorInst->phyLogCtrl.wBusy = BUFF_NONE;
 }
 
 /**
- * Get the latest send slot log
+ * Get the latest physical layer log
  */
-void SysMonitor_GetSendSlotLog(SLOTLOG *log)
+void SysMonitor_GetPhysicalLayerLog(PHYLOG *log)
 {
 	ASSERT(sysMonitorInst != NULL);
 	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->sendLogCtrl.rBusy;
+	buffIndex_old = sysMonitorInst->phyLogCtrl.rBusy;
 	if (buffIndex_old != BUFF_NONE)
 		buffIndx = buffIndex_old; // Keep it busy
 	else
-		buffIndx = GetReadable(sysMonitorInst->sendLogCtrl);
-	sysMonitorInst->sendLogCtrl.rBusy = buffIndx;
-	memcpy(log, &(sysMonitorInst->sendLog[buffIndx]), sizeof(SLOTLOG));
-	sysMonitorInst->sendLogCtrl.rBusy = buffIndex_old;
+		buffIndx = GetReadable(sysMonitorInst->phyLogCtrl);
+	sysMonitorInst->phyLogCtrl.rBusy = buffIndx;
+	memcpy(log, &(sysMonitorInst->phyLog[buffIndx]), sizeof(PHYLOG));
+	sysMonitorInst->phyLogCtrl.rBusy = buffIndex_old;
 }
 
-/**
- * Get the latest send slot log as raw data
- */
-void SysMonitor_GetSendSlotLogRaw(uint8_t *buff)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->sendLogCtrl.rBusy;
-	if (buffIndex_old != BUFF_NONE)
-		buffIndx = buffIndex_old; // Keep it busy
-	else
-		buffIndx = GetReadable(sysMonitorInst->sendLogCtrl);
-	sysMonitorInst->sendLogCtrl.rBusy = buffIndx;
-
-	// Encapsulate log
-	SLOTLOG *logEntry = &(sysMonitorInst->sendLog[buffIndx]);
-	memcpy(buff, &(logEntry->tuNo), sizeof(logEntry->tuNo));
-	buff += sizeof(logEntry->tuNo);
-	memcpy(buff, &(logEntry->slotNo), sizeof(logEntry->slotNo));
-	buff += sizeof(logEntry->slotNo);
-	memcpy(buff, &(logEntry->frameType), sizeof(logEntry->frameType));
-	buff += sizeof(logEntry->frameType);
-	memcpy(buff, &(logEntry->payload), sizeof(logEntry->payload));
-	buff += sizeof(logEntry->payload);
-	memcpy(buff, &(logEntry->tmStamp), sizeof(logEntry->tmStamp));
-	buff += sizeof(logEntry->tmStamp);
-	memcpy(buff, &(logEntry->tmDevi), sizeof(logEntry->tmDevi));
-	buff += sizeof(logEntry->tmDevi);
-	memcpy(buff, &(logEntry->freqDevi), sizeof(logEntry->freqDevi));
-	sysMonitorInst->sendLogCtrl.rBusy = buffIndex_old;
-}
-
-// @Receive Slot log
-/**
- * Log receive slot information
- */
-void SysMonitor_UpdateRecvSlotLog(SLOTLOG *log)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx;
-	buffIndx = GetWritable(sysMonitorInst->recvLogCtrl);
-	sysMonitorInst->recvLogCtrl.wBusy = buffIndx;
-	memcpy(&(sysMonitorInst->recvLog[buffIndx]), log, sizeof(SLOTLOG));
-	sysMonitorInst->recvLogCtrl.latest = buffIndx;
-	sysMonitorInst->recvLogCtrl.wBusy = BUFF_NONE;
-}
-
-/**
- * Get the latest receive slot information
- */
-void SysMonitor_GetRecvSlotLog(SLOTLOG *log)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->recvLogCtrl.rBusy;
-	if (buffIndex_old != BUFF_NONE)
-		buffIndx = buffIndex_old; // Keep it busy
-	else
-		buffIndx = GetReadable(sysMonitorInst->recvLogCtrl);
-	sysMonitorInst->recvLogCtrl.rBusy = buffIndx;
-	memcpy(log, &(sysMonitorInst->recvLog[buffIndx]), sizeof(SLOTLOG));
-	sysMonitorInst->recvLogCtrl.rBusy = buffIndex_old;
-}
-
-/**
- * Get the latest receive slot information as raw data
- */
-void SysMonitor_GetRecvSlotLogRaw(uint8_t *buff)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->recvLogCtrl.rBusy;
-	if (buffIndex_old != BUFF_NONE)
-		buffIndx = buffIndex_old; // Keep it busy
-	else
-		buffIndx = GetReadable(sysMonitorInst->recvLogCtrl);
-	sysMonitorInst->recvLogCtrl.rBusy = buffIndx;
-
-	// Encapsulate log
-	SLOTLOG *logEntry = &(sysMonitorInst->recvLog[buffIndx]);
-	memcpy(buff, &(logEntry->tuNo), sizeof(logEntry->tuNo));
-	buff += sizeof(logEntry->tuNo);
-	memcpy(buff, &(logEntry->slotNo), sizeof(logEntry->slotNo));
-	buff += sizeof(logEntry->slotNo);
-	memcpy(buff, &(logEntry->frameType), sizeof(logEntry->frameType));
-	buff += sizeof(logEntry->frameType);
-	memcpy(buff, &(logEntry->payload), sizeof(logEntry->payload));
-	buff += sizeof(logEntry->payload);
-	memcpy(buff, &(logEntry->tmStamp), sizeof(logEntry->tmStamp));
-	buff += sizeof(logEntry->tmStamp);
-	memcpy(buff, &(logEntry->tmDevi), sizeof(logEntry->tmDevi));
-	buff += sizeof(logEntry->tmDevi);
-	memcpy(buff, &(logEntry->freqDevi), sizeof(logEntry->freqDevi));
-	sysMonitorInst->recvLogCtrl.rBusy = buffIndex_old;
-}
-
-// @Protocol log
-/**
- * Log protocol running status.
- */
-void SysMonitor_UpdateProtocolLog(PRTCLLOG *log)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx;
-	buffIndx = GetWritable(sysMonitorInst->protocolLogCtrl);
-	sysMonitorInst->protocolLogCtrl.wBusy = buffIndx;
-	memcpy(&(sysMonitorInst->protocolLog[buffIndx]), log, sizeof(PRTCLLOG));
-	sysMonitorInst->protocolLogCtrl.latest = buffIndx;
-	sysMonitorInst->protocolLogCtrl.wBusy = BUFF_NONE;
-}
-
-/**
- * Get the protocol running log.
- */
-void SysMonitor_GetProtocolLog(PRTCLLOG *log)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->protocolLogCtrl.rBusy;
-	if (buffIndex_old != BUFF_NONE)
-		buffIndx = buffIndex_old; // Keep it busy
-	else
-		buffIndx = GetReadable(sysMonitorInst->protocolLogCtrl);
-	sysMonitorInst->protocolLogCtrl.rBusy = buffIndx;
-	memcpy(log, &(sysMonitorInst->protocolLog[buffIndx]), sizeof(PRTCLLOG));
-	sysMonitorInst->protocolLogCtrl.rBusy = buffIndex_old;
-}
-
-/**
- * Get the protocol running log as raw data.
- */
-void SysMonitor_GetProtocolLogRaw(uint8_t *buff)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->protocolLogCtrl.rBusy;
-	if (buffIndex_old != BUFF_NONE)
-		buffIndx = buffIndex_old; // Keep it busy
-	else
-		buffIndx = GetReadable(sysMonitorInst->protocolLogCtrl);
-	sysMonitorInst->protocolLogCtrl.rBusy = buffIndx;
-
-	// Encapsulate log
-	PRTCLLOG *logEntry = &(sysMonitorInst->protocolLog[buffIndx]);
-	memcpy(buff, &(logEntry->tmSys), sizeof(logEntry->tmSys));
-	buff += sizeof(logEntry->tmSys);
-	memcpy(buff, &(logEntry->phySt), sizeof(logEntry->phySt));
-	buff += sizeof(logEntry->phySt);
-	memcpy(buff, &(logEntry->tmLocal), sizeof(logEntry->tmLocal));
-	buff += sizeof(logEntry->tmLocal);
-	memcpy(buff, &(logEntry->beamNo), sizeof(logEntry->beamNo));
-	buff += sizeof(logEntry->beamNo);
-	memcpy(buff, &(logEntry->beamWidth), sizeof(logEntry->beamWidth));
-	buff += sizeof(logEntry->beamWidth);
-	memcpy(buff, &(logEntry->stage), sizeof(logEntry->stage));
-	buff += sizeof(logEntry->stage);
-	memcpy(buff, &(logEntry->recvCnt), sizeof(logEntry->recvCnt));
-	buff += sizeof(logEntry->recvCnt);
-	sysMonitorInst->protocolLogCtrl.rBusy = buffIndex_old;
-}
 
 // @Hardware state
 /**
  * Log hardware running status.
  */
-void SysMonitor_UpdateHardwareStatus(HWSTATE *state)
+void SysMonitor_UpdateHardwareStatus(const HWSTATE *state)
 {
 	ASSERT(sysMonitorInst != NULL);
 	uint8_t buffIndx;
@@ -578,65 +289,3 @@ void SysMonitor_GetHardwareStatus(HWSTATE *state)
 	memcpy(state, &(sysMonitorInst->hwState[buffIndx]), sizeof(HWSTATE));
 	sysMonitorInst->hwStateCtrl.rBusy = buffIndex_old;
 }
-
-/**
- * Get the latest hardware running status as raw data.
- */
-void SysMonitor_GetHardwareStatusRaw(uint8_t *buff)
-{
-	ASSERT(sysMonitorInst != NULL);
-	uint8_t buffIndx, buffIndex_old;
-	buffIndex_old = sysMonitorInst->hwStateCtrl.rBusy;
-	if (buffIndex_old != BUFF_NONE)
-		buffIndx = buffIndex_old; // Keep it busy
-	else
-		buffIndx = GetReadable(sysMonitorInst->hwStateCtrl);
-	sysMonitorInst->hwStateCtrl.rBusy = buffIndx;
-
-	// Encapsulate state
-	HWSTATE *stateEntry = &(sysMonitorInst->hwState[buffIndx]);
-	memcpy(buff, &(stateEntry->spVolt), sizeof(stateEntry->spVolt));
-	buff += sizeof(stateEntry->spVolt);
-	memcpy(buff, &(stateEntry->spTemp), sizeof(stateEntry->spTemp));
-	buff += sizeof(stateEntry->spTemp);
-	memcpy(buff, &(stateEntry->chipSt), sizeof(stateEntry->chipSt));
-	buff += sizeof(stateEntry->chipSt);
-	memcpy(buff, &(stateEntry->antVolt), sizeof(stateEntry->antVolt));
-	buff += sizeof(stateEntry->antVolt);
-	memcpy(buff, &(stateEntry->antTemp), sizeof(stateEntry->antTemp));
-	buff += sizeof(stateEntry->antTemp);
-	memcpy(buff, &(stateEntry->antPll), sizeof(stateEntry->antPll));
-	buff += sizeof(stateEntry->antPll);
-	memcpy(buff, &(stateEntry->antMgc), sizeof(stateEntry->antMgc));
-	buff += sizeof(stateEntry->antMgc);
-	memcpy(buff, &(stateEntry->antSt), sizeof(stateEntry->antSt));
-	sysMonitorInst->hwStateCtrl.rBusy = buffIndex_old;
-}
-
-// @System log
-/**
- * Get the latest system running log.
- */
-void SysMonitor_GetSyslog(SYSLOG *log)
-{
-	ASSERT(sysMonitorInst != NULL);
-	SysMonitor_GetSendSlotLog(&(log->sendLog));
-	SysMonitor_GetRecvSlotLog(&(log->recvLog));
-	SysMonitor_GetProtocolLog(&(log->protocolLog));
-	SysMonitor_GetHardwareStatus(&(log->hwSate));
-}
-
-/**
- * Get the latest system running log as raw data.
- */
-void SysMonitor_GetSyslogRaw(uint8_t *buff)
-{
-	ASSERT(sysMonitorInst != NULL);
-	SysMonitor_GetSendSlotLogRaw(buff);
-	buff += SLOTLOG_PACK_LEN;
-	SysMonitor_GetRecvSlotLogRaw(buff);
-	buff += SLOTLOG_PACK_LEN;
-	SysMonitor_GetProtocolLogRaw(buff);
-	buff += PRTCLLOG_PACK_ELN;
-	SysMonitor_GetHardwareStatusRaw(buff);
-}

df_datalink_sp/src/system_monitor.h

@@ -3,23 +3,63 @@
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "util.h"
 
-#define PAYLOAD_LEN 256
-#define PAYLOAD_FLJ_RX 168
-#define PAYLOAD_FLJ_TX 66
-#define PAYLOAD_LJ_RX 66
-#define PAYLOAD_LJ_TX 168
+#define PAYLOAD_LEN_MAX 256
+#define PAYLOAD_LEN_FLJ_RX 168
+#define PAYLOAD_LEN_FLJ_TX 66
+#define PAYLOAD_LEN_LJ_RX 66
+#define PAYLOAD_LEN_LJ_TX 168
 
 #define DATA_ID_NONE UINT32_MAX
 #define DATA_ID_TEST 0x02030203
 
-typedef struct
-{
-	// FIXME: To Complete
-	uint8_t dummy;
-} SYSCONFIG;
+#define VOLTAGE_LSB 0.01 // volt
+#define VOLTAGE_MAX 2.55 // volt
 
-typedef struct
+#define VOLT_PS_STD 1.0
+#define VOLT_PSAUX_STD 1.8
+#define VOLT_DDR_STD 1.5
+#define VOLT_PL_STD 1.0
+#define VOLT_PLAUX_STD 1.8
+#define VOLT_BRAM_STD 1.0
+
+#define VOLT_PS_OK BIT(0)
+#define VOLT_PSAUX_OK BIT(1)
+#define VOLT_DDR_OK BIT(2)
+#define VOLT_PL_OK BIT(3)
+#define VOLT_PLAUX_OK BIT(4)
+#define VOLT_BRAM_OK BIT(5)
+
+#define VOLT_ANT_PROC_OK BIT(0)
+#define VOLT_ANT_RF_OK BIT(2)
+#define VOLT_ANT_NIL_OK BIT(4)
+#define ANT_STATE_OK BIT(6)
+
+#define IS_PS_VALID(x) (x <= 0.95 && x >= 1.05)
+#define IS_PSAUX_VALID(x) (x <= 1.89 && x >= 1.71)
+#define IS_DDR_VALID(x) (x <= 1.14 && x >= 1.89)
+#define IS_PL_VALID(x) (x <= 0.97 && x >= 1.03)
+#define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71)
+#define IS_BRAM_VALID(x) (x <= 0.97 && x >= 1.03)
+
+#define CLK_SP_PLL0_LOCK BIT(0)
+#define CLK_SP_PLL1_LOCK BIT(2)
+
+#define CLK_AD0_BBPLL_LOCK BIT(0)
+#define CLK_AD0_RFPLL_LOCK BIT(2)
+#define CLK_AD1_BBPLL_LOCK BIT(4)
+#define CLK_AD1_RFPLL_LOCK BIT(6)
+
+#define CLK_ANT_BBPLL_LOCK BIT(0)
+#define CLK_ANT_RFPLL0_LOCK BIT(2)
+#define CLK_ANT_RFPLL1_LOCK BIT(4)
+
+#define TEMPERATURE_LSB 1.0	   // Celsius degree
+#define TEMPERATURE_MAX 127.0  // Celsius degree
+#define TEMPERATURE_MIN -128.0 // Celsius degree
+
+typedef struct __attribute__((packed))
 {
 	// -- unit: ms, 0~604799999
 	uint32_t psBDS;
@@ -58,107 +98,106 @@ typedef struct
 	float roll;
 } SYSINFO;
 
-typedef struct
+typedef struct __attribute__((packed))
 {
-	uint32_t dataId_lj;
-	uint8_t data_lj[PAYLOAD_LEN];
-	uint32_t dataId_flj;
-	uint8_t data_flj[PAYLOAD_LEN];
-} PAYLOAD;
+	// SystemBus log
+	// -- last valid config
+	//    byte 0: 0x11 FLJ, 0x00 LJ
+	//    byte 1: 0x66 Full Power, 0x88 Low Power
+	uint8_t lastConfig[2];
+	uint32_t pollCnt;
+	uint32_t svcCnt;
+	uint32_t remoteCnt;
+} SYSBUSLOG;
 
-typedef struct
+typedef struct __attribute__((packed))
 {
 	// Network log
-	uint32_t tuNo;
-	uint8_t slotNo;
-	uint8_t frameType;
-	// Payload
-	uint8_t payload[PAYLOAD_LEN];
-	// Time sync info
-	uint64_t tmStamp;
-	uint32_t tmDevi;
-	uint32_t freqDevi;
-} SLOTLOG;
-
-typedef struct
-{
-	// Protocol log
-	// -- System time
-	uint32_t tmSys;
-	// -- Physical layer status
-	uint8_t phySt;
-	// -- Link layer status
-	uint64_t tmLocal;
-	uint16_t beamNo;
+	uint32_t tuNum;
+	uint8_t slotNum;
+	uint8_t nodeType;
+	uint8_t cxnStatus;
+	uint8_t linkStage;
+	uint32_t recxnCnt;
+	uint8_t beamNo;
 	uint8_t beamWidth;
-	// -- Network layer status
-	uint8_t stage;
-	uint32_t recvCnt;
-	uint32_t recvCorrect;
-} PRTCLLOG;
+	uint16_t beamAz;
+	uint16_t beamEl;
+	uint16_t advTxCnt;
+	uint16_t advRecvCnt;
+	uint16_t advCorrectCnt;
+	uint32_t cfmTxCnt;
+	uint32_t cfmRecvCnt;
+	uint32_t cfmCorrectCnt;
+	uint32_t svcTxCnt;
+	uint32_t svcRecvCnt;
+	uint32_t svcCorrectCnt;
+	int32_t timeDev;
+	uint32_t sendId;
+	uint32_t recvId;
+	uint8_t reserve[4];
+} LINKLOG;
 
-typedef struct
+typedef struct __attribute__((packed))
 {
-	// Hardware log
+	uint32_t acqCnt;
+	uint32_t fsyncCnt;
+	uint32_t decodeCnt;
+	uint32_t crcCnt;
+	double doppler;
+	uint64_t recvStamp;
+	double acqPAPR;
+	uint8_t acqPhase;
+	uint8_t acqFreqCh;
+	double fsyncPAPR;
+	uint8_t fsyncFreqCh;
+	uint16_t deintlvAmpEst;
+	uint8_t reserve[4];
+} PHYLOG;
+
+typedef struct __attribute__((packed))
+{
+	// Hardware status
+	bool isSpOk;
+	bool isAntOk;
 	// -- Signal processor status
-	uint16_t spVolt;
-	uint16_t spTemp;
-	uint8_t chipSt;
+	uint8_t spFpgaVolt;
+	uint8_t spClkState;
+	uint8_t spAdLockState;
+	uint8_t spAdTemp_0;
+	uint8_t spAdTemp_1;
+	uint8_t spFpgaTemp;
 	// -- Antenna status
 	uint8_t antVolt;
 	uint8_t antTemp;
 	uint8_t antPll;
-	uint16_t antMgc;
-	uint8_t antSt;
+	uint8_t antMgc0;
+	uint8_t antMgc1;
+	uint8_t reserve[2];
 } HWSTATE;
 
 typedef struct
 {
-	// Send slot log
-	SLOTLOG sendLog;
-
-	// Receive slot log
-	SLOTLOG recvLog;
-
-	// Protocol log
-	PRTCLLOG protocolLog;
-
-	// Hardware status
-	HWSTATE hwSate;
-} SYSLOG;
+	uint32_t dataId;
+	uint8_t data[PAYLOAD_LEN_MAX];
+} PAYLOAD;
 
 int32_t SysMonitor_Init(void);
 void SysMonitor_Destroy(void);
 
-void SysMonitor_UpdateSysinfo(SYSINFO *info);
-void SysMonitor_UpdateSysinfoRaw(uint8_t *buff);
+void SysMonitor_UpdateSysinfo(const SYSINFO *info);
 void SysMonitor_GetSysinfo(SYSINFO *info);
-void SysMonitor_GetSysinfoRaw(uint8_t *buff);
 
-void SysMonitor_UpdateSendPayloadFLJRaw(uint8_t *buff);
-void SysMonitor_UpdateRecvPayloadFLJRaw(uint8_t *buff);
-void SysMonitor_UpdateSendPayloadLJRaw(uint8_t *buff);
-void SysMonitor_UpdateRecvPayloadLJRaw(uint8_t *buff);
-void SysMonitor_GetSendPayloadFLJRaw(uint8_t *buff, uint32_t *id);
-void SysMonitor_GetRecvPayloadFLJRaw(uint8_t *buff, uint32_t *id);
-void SysMonitor_GetSendPayloadLJRaw(uint8_t *buff, uint32_t *id);
-void SysMonitor_GetRecvPayloadLJRaw(uint8_t *buff, uint32_t *id);
+void SysMonitor_UpdateSendPayload(const uint8_t *buff, size_t len);
+void SysMonitor_UpdateRecvPayload(const uint8_t *buff, size_t len);
+void SysMonitor_GetSendPayload(uint8_t *buff, uint32_t *id, size_t len);
+void SysMonitor_GetRecvPayload(uint8_t *buff, uint32_t *id, size_t len);
 
-void SysMonitor_UpdateSendSlotLog(SLOTLOG *log);
-void SysMonitor_UpdateRecvSlotLog(SLOTLOG *log);
-void SysMonitor_UpdateProtocolLog(PRTCLLOG *log);
-void SysMonitor_GetSendSlotLog(SLOTLOG *log);
-void SysMonitor_GetRecvSlotLog(SLOTLOG *log);
-void SysMonitor_GetProtocolLog(PRTCLLOG *log);
-void SysMonitor_GetSendSlotLogRaw(uint8_t *buff);
-void SysMonitor_GetRecvSlotLogRaw(uint8_t *buff);
-void SysMonitor_GetProtocolLogRaw(uint8_t *buff);
-
-void SysMonitor_UpdateHardwareStatus(HWSTATE *state);
+void SysMonitor_UpdateLinklayerLog(const LINKLOG *log);
+void SysMonitor_UpdatePhysicalLayerLog(const PHYLOG *log);
+void SysMonitor_UpdateHardwareStatus(const HWSTATE *state);
+void SysMonitor_GetLinklayerLog(LINKLOG *log);
+void SysMonitor_GetPhysicalLayerLog(PHYLOG *log);
 void SysMonitor_GetHardwareStatus(HWSTATE *state);
-void SysMonitor_GetHardwareStatusRaw(uint8_t *buff);
-
-void SysMonitor_GetSyslog(SYSLOG *log);
-void SysMonitor_GetSyslogRaw(uint8_t *buff);
 
 #endif //__SYSTEM_MONITOR_H_

df_datalink_sp/src/systembus/systembus.c

@@ -51,25 +51,32 @@
 #define WD_ST_RET 0x02
 #define ST_RET_OK 0xAA
 #define ST_RET_ERROR 0x55
-// -- -- Signal processor voltage
-#define WD_SP_VOLT 0x03
-// -- -- Signal processor temperature
-#define WD_SP_TEMP 0x04
-// -- -- Signal processor chip status
-#define WD_SP_CS 0x05
-// -- -- Signal processor antenna voltage
-#define WD_ANT_VOLT 0x06
-// -- -- Signal processor antenna temperature
-#define WD_ANT_TEMP 0x07
+#define ST_RET_INFO_LEN 13
+// -- -- Signal processor PS voltage
+#define WD_SP_FPGA_VOLT 0x03
+// -- -- Signal processor PS AUX voltage
+#define WD_SP_CLK_STATE 0x04
+// -- -- Signal processor DDR voltage
+#define WD_SP_AD_LOCK_STATE 0x05
+// -- -- Signal processor PL voltage
+#define WD_SP_AD_TEMP_0 0x06
+// -- -- Signal processor PL AUX voltage
+#define WD_SP_AD_TEMP_1 0x07
+// -- -- Signal processor Bram voltage
+#define WD_SP_FPGA_TEMP 0x08
+
+// -- -- Signal processor antenna voltage status
+#define WD_ANT_VOLT 0x09
+
+// -- -- Signal processor antenna RF temperature
+#define WD_ANT_RF_TEMP 0x0A
 // -- -- Signal processor antenna PLL lock status
-#define WD_ANT_PLL 0x08
+#define WD_ANT_RF_PLL 0x0B
 // -- -- Signal processor antenna MGC
-#define WD_ANT_MGC_L 0x09
-#define WD_ANT_MGC_H 0x0A
-// -- -- Signal processor antenna status
-#define WD_ANT_ST 0x0B
-// -- -- Dummy must be 0x00
-#define WD_ST_DUMMY 0x0C
+#define WD_ANT_MGC_0 0x0C
+#define WD_ANT_MGC_1 0x0D
+// -- -- Reserved
+#define WD_ANT_RESERVE 0x0E
 
 // Data Send Test Command
 #define CMD_DATA_TEST_A 0xE2
@@ -150,6 +157,17 @@
 #define WD_FLJ_RM_TEST 0x02
 #define FLJ_RM_TEST_CODE 0x99
 // -- Response
+#define WD_FLJ_TIME_STAMP 0x02
+#define WD_FLJ_TIME_STAMP_LEN 8
+#define WD_FLJ_SYSBUS_LOG 0x0A
+#define WD_FLJ_SYSBUS_LOG_LEN 14
+#define WD_FLJ_LINK_LOG 0x18
+#define WD_FLJ_LINK_LOG_LEN 64
+#define WD_FLJ_PHY_LOG 0x58
+#define WD_FLJ_PHY_LOG_LEN 57
+#define WD_FLJ_HARDWARE_ST 0x91
+#define WD_FLJ_HARDWARE_ST_LEN 13
+
 #define FLJ_RM_TEST_RESP_LEN 158
 
 // Remote Test LJ
@@ -158,6 +176,17 @@
 #define WD_LJ_RM_TEST 0x02
 #define LJ_RM_TEST_CODE 0x99
 // -- Response
+#define WD_LJ_TIME_STAMP 0x02
+#define WD_LJ_TIME_STAMP_LEN 8
+#define WD_LJ_SYSBUS_LOG 0x0A
+#define WD_LJ_SYSBUS_LOG_LEN 14
+#define WD_LJ_LINK_LOG 0x18
+#define WD_LJ_LINK_LOG_LEN 64
+#define WD_LJ_PHY_LOG 0x58
+#define WD_LJ_PHY_LOG_LEN 57
+#define WD_LJ_HARDWARE_ST 0x91
+#define WD_LJ_HARDWARE_ST_LEN 13
+
 #define LJ_RM_TEST_RESP_LEN 158
 
 
@@ -221,6 +250,10 @@ int32_t SystemBus_Init(SYSBUS **instPtr, SYSBUS_CONFIG *config)
 	(*instPtr)->txQueue = NULL;
 	(*instPtr)->uartInst = NULL;
 	memcpy(&((*instPtr)->config), config, sizeof(SYSBUS_CONFIG));
+	memset(&((*instPtr)->sysbusLog), 0x00, sizeof(SYSBUSLOG));
+	memset(&((*instPtr)->linkLog), 0x00, sizeof(LINKLOG));
+	memset(&((*instPtr)->phyLog), 0x00, sizeof(PHYLOG));
+	memset(&((*instPtr)->hwState), 0x00, sizeof(HWSTATE));
 	uartConfig.baseAddr = config->baseAddr;
 	Status = SysbusUart_Init(&((*instPtr)->uartInst), &uartConfig);
 	if (Status != SUCCESS)
@@ -277,10 +310,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		DBG_WARNING("SystemBus::Production code mismatch!\n");
 		return EIGNORE;
 	}
+
 	switch (data[WD_CMD])
 	{
 	case CMD_SELF_TEST:
 	{
+		HWSTATE *hwStatsPtr = &(instPtr->hwState);
 		sysbusRsp = malloc(sizeof(SYSBUS_UART_FRAME));
 		if (sysbusRsp == NULL) {
 			DBG_ERROR("Failed to allocate memory for SELF TEST Response!\n");
@@ -291,9 +326,18 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		memset(sysbusRsp->data, 0x00, ST_RSP_LEN);
 		sysbusRsp->data[WD_CMD] = CMD_SELF_TEST;
 		sysbusRsp->data[WD_PRD] = MY_PRD_ID;
+		SysMonitor_GetHardwareStatus(hwStatsPtr);
+		if (linkInstPtr->isEnable == false)
+		{
+			sysbusRsp->data[WD_ST_RET] = (hwStatsPtr->isSpOk) ? ST_RET_OK : ST_RET_ERROR;
+		}
+		else
+		{
+			sysbusRsp->data[WD_ST_RET] = (hwStatsPtr->isSpOk && hwStatsPtr->isAntOk) ? ST_RET_OK : ST_RET_ERROR;
+		}
+		// apply status and omit 2 bytes of overhead.
+		memcpy(sysbusRsp->data + WD_SP_FPGA_VOLT, &(hwStatsPtr->spFpgaVolt), ST_RET_INFO_LEN);
 
-		// FIXME: run self-test and insert result
-		sysbusRsp->data[WD_ST_RET] = ST_RET_OK;
 		if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false)
 		{
 			free(sysbusRsp);
@@ -350,44 +394,53 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		TMC_INST *tmcRef = linkInstPtr->config.tmcInstPtr;
 
 		if (data[WD_MODE_CMD] == MODE_CMD_HEAD)
+		{
+			// omit unnecessary reconfiguration
+			if (L2_GetNodeType(linkInstPtr) != L2_NODE_HEAD)
 			{
 				// head node config
 				linkConfig.myType = L2_NODE_HEAD;
 				linkConfig.myId = 1;
 				Linklayer_Reconfig(linkInstPtr, &linkConfig);
 			}
-		else if (data[WD_MODE_CMD] == MODE_CMD_MEMBER) 
+		}
+
+		else if (data[WD_MODE_CMD] == MODE_CMD_MEMBER )
+		{
+			// omit unnecessary reconfiguration
+			if (L2_GetNodeType(linkInstPtr) != L2_NODE_MEMBER)
 			{
 				// member node config
 				linkConfig.myType = L2_NODE_MEMBER;
 				linkConfig.myId = 2;
 				Linklayer_Reconfig(linkInstPtr, &linkConfig);
 			}
+		}
 		else
 		{
-			// FIXME: 
+			// FIXME: to confirm
 			// Halt linklayer
 			Linklayer_Halt(linkInstPtr);
 			DBG_ERROR("Unexpected config command 0x%02X:0x%02X",
 				WD_MODE_CMD, data[WD_MODE_CMD]);
+			Status = EPARAM;
+			break;
 		}
 
 		if(data[WD_EN_CMD] == EN_CMD_ON_HIGH_POWER)
 		{
 			// high power config
 			Phy_AntConfigMode(phyRef, PHY_ANT_MODE_HIGH_POWER);
-			Linklayer_Start(linkInstPtr);
-
 		}
 		else if(data[WD_EN_CMD] == EN_CMD_ON_LOW_POWER)
 		{
 			// low power config
 			Phy_AntConfigMode(phyRef, PHY_ANT_MODE_LOW_POWER);
-			Linklayer_Start(linkInstPtr);
 		}
 		else
 		{
 			// silence config
+			// FIXME: confirm
 			// TODO: better approach?
 			Linklayer_Halt(linkInstPtr);
 			Phy_AntConfigMode(phyRef, PHY_ANT_MODE_SILENT);
@@ -399,27 +452,32 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 				DBG_ERROR("Physical set pull time failed, with error code: %" PRId32 ".\n", Status);
 			}
 			Phy_SetupNextSlot(phyRef, PHY_TOR_RX, L1_10KBPS_10MS_FRAME, NULL);
+			break;
 		}
 
-		_nop_(); // for debug
+		Linklayer_Start(linkInstPtr);
+		instPtr->sysbusLog.lastConfig[0] = data[WD_MODE_CMD];
+		instPtr->sysbusLog.lastConfig[1] = data[WD_EN_CMD];
 		Status = SUCCESS;
 		break;
 	}
 	case CMD_SYS_INFO:
 	{
-		SysMonitor_UpdateSysinfoRaw(data + SYS_INFO_OFFSET);
+		SysMonitor_UpdateSysinfo((SYSINFO *)(data + SYS_INFO_OFFSET));
 		Status = SUCCESS;
 		break;
 	}
 	// TODO
 	case CMD_FLJ_SEND:
 	{
-		SysMonitor_UpdateSendPayloadFLJRaw(data + FLJ_DATA_OFFSET); // omit control info
+		SysMonitor_UpdateSendPayload(data + FLJ_DATA_OFFSET, PAYLOAD_LEN_FLJ_TX); // omit control info
+		instPtr->sysbusLog.svcCnt++;
 		break;
 	}
 	case CMD_LJ_SEND:
 	{
-		SysMonitor_UpdateSendPayloadLJRaw(data + LJ_DATA_OFFSET); // omit control info
+		SysMonitor_UpdateSendPayload(data + LJ_DATA_OFFSET, PAYLOAD_LEN_LJ_TX); // omit control info
+		instPtr->sysbusLog.svcCnt++;
 		break;
 	}
 	case CMD_FLJ_POLL:
@@ -440,7 +498,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		sysbusRsp->data[WD_CMD] = CMD_FLJ_POLL;
 		sysbusRsp->data[WD_PRD] = MY_PRD_ID;
 		uint32_t dataId;
-		SysMonitor_GetRecvPayloadFLJRaw(sysbusRsp->data + FLJ_DATA_OFFSET, &dataId); // omit control info
+		SysMonitor_GetRecvPayload(sysbusRsp->data + FLJ_DATA_OFFSET, &dataId, PAYLOAD_LEN_FLJ_RX); // omit control info
 		if (dataId == DATA_ID_NONE)
 		{
 			free(sysbusRsp);
@@ -455,6 +513,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.pollCnt++;
 		Status = SUCCESS;
 		break;
 	}
@@ -476,7 +535,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		sysbusRsp->data[WD_CMD] = CMD_LJ_POLL;
 		sysbusRsp->data[WD_PRD] = MY_PRD_ID;
 		uint32_t dataId;
-		SysMonitor_GetRecvPayloadLJRaw(sysbusRsp->data + LJ_DATA_OFFSET, &dataId); // omit control info
+		SysMonitor_GetRecvPayload(sysbusRsp->data + LJ_DATA_OFFSET, &dataId, PAYLOAD_LEN_LJ_RX); // omit control info
 		if (dataId == DATA_ID_NONE)
 		{
 			free(sysbusRsp);
@@ -491,6 +550,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.pollCnt++;
 		Status = SUCCESS;
 		break;
 	}
@@ -514,12 +574,25 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		sysbusRsp->data[WD_CMD] = CMD_FLJ_RM_TEST;
 		sysbusRsp->data[WD_PRD] = MY_PRD_ID;
 
+		TIME_WORD tmWord;
+		uint64_t time;
+		TimeCtrl_GetCurrentTime(linkInstPtr->config.tmcInstPtr, &tmWord);
+		time = tmWord.int_part * TIME_FRAC_MAX + tmWord.frac_part;
+		memcpy(sysbusRsp->data + WD_FLJ_TIME_STAMP, &time, WD_FLJ_TIME_STAMP_LEN);
+		SysMonitor_GetLinklayerLog(&(instPtr->linkLog));
+		SysMonitor_GetPhysicalLayerLog(&(instPtr->phyLog));
+		SysMonitor_GetHardwareStatus(&(instPtr->hwState));
+		memcpy(sysbusRsp->data + WD_FLJ_LINK_LOG, &(instPtr->linkLog), WD_FLJ_LINK_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_FLJ_PHY_LOG, &(instPtr->phyLog), WD_FLJ_PHY_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_FLJ_HARDWARE_ST, &(instPtr->hwState.spFpgaVolt), WD_FLJ_HARDWARE_ST_LEN);
+
 		if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false){
 			free(sysbusRsp);
 			DBG_WARNING("SystemBus::TX Queue overflowed!\n");
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.remoteCnt++;
 		Status = SUCCESS;
 		break;
 	}
@@ -543,12 +616,25 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		sysbusRsp->data[WD_CMD] = CMD_LJ_RM_TEST;
 		sysbusRsp->data[WD_PRD] = MY_PRD_ID;
 
+		TIME_WORD tmWord;
+		uint64_t time;
+		TimeCtrl_GetCurrentTime(linkInstPtr->config.tmcInstPtr, &tmWord);
+		time = tmWord.int_part * TIME_FRAC_MAX + tmWord.frac_part;
+		memcpy(sysbusRsp->data + WD_LJ_TIME_STAMP, &time, WD_LJ_TIME_STAMP_LEN);
+		SysMonitor_GetLinklayerLog(&(instPtr->linkLog));
+		SysMonitor_GetPhysicalLayerLog(&(instPtr->phyLog));
+		SysMonitor_GetHardwareStatus(&(instPtr->hwState));
+		memcpy(sysbusRsp->data + WD_LJ_LINK_LOG, &(instPtr->linkLog), WD_LJ_LINK_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_LJ_PHY_LOG, &(instPtr->phyLog), WD_LJ_PHY_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_LJ_HARDWARE_ST, &(instPtr->hwState.spFpgaVolt), WD_LJ_HARDWARE_ST_LEN);
+
 		if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false){
 			free(sysbusRsp);
 			DBG_WARNING("SystemBus::TX Queue overflowed!\n");
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.remoteCnt++;
 		Status = SUCCESS;
 		break;
 	}
@@ -562,18 +648,6 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 	return Status;
 }
 
-int32_t SystemBus_FLJ_PeriodUpdate(SYSBUS *instPtr)
-{
-	// TODO
-	return SUCCESS;
-}
-
-int32_t SystemBus_LJ_PeriodUpdate(SYSBUS *instPtr)
-{
-	// TODO
-	return SUCCESS;
-}
-
 /*****************************************************************************/
 /**
  * @brief   This function send a repose frame from system bus tx queue.

df_datalink_sp/src/systembus/systembus.h

@@ -17,10 +17,11 @@
 #define __SYSTEMBUS_H_
 
 /***************************** Include Files *********************************/
-#include "systembus_uart.h" // SystemBus UART driver
-#include "circ_queue.h"
 #include <stdint.h>
 #include <stdbool.h>
+#include "systembus_uart.h" // SystemBus UART driver
+#include "circ_queue.h"
+#include "../system_monitor.h"
 
 /************************** Constant Definitions *****************************/
 /************************** Data Type Definitions ****************************/
@@ -35,6 +36,10 @@ typedef struct
 typedef struct
 {
     SYSBUS_CONFIG config;
+    SYSBUSLOG sysbusLog; // systembus log
+	LINKLOG linkLog; // Link layer log
+	PHYLOG phyLog; // Physical layer log
+	HWSTATE hwState; // Hardware status
     SYSBUS_UART *uartInst;
     CIRC_QUEUE *txQueue;
     CIRC_QUEUE *rxQueue;
@@ -47,10 +52,6 @@ typedef struct
 int32_t SystemBus_Init(SYSBUS **instPtr, SYSBUS_CONFIG *config);
 
 int32_t SystemBus_HandleCmd(SYSBUS *instPtr);
-
-int32_t SystemBus_FLJ_PeriodUpdate(SYSBUS *instPtr);
-int32_t SystemBus_LJ_PeriodUpdate(SYSBUS *instPtr);
-
 int32_t SystemBus_MakeResp(SYSBUS *instPtr);
 
 int32_t SystemBus_TxIntrHandler(SYSBUS *instPtr);

df_datalink_sp/src/util/clist.c

@@ -56,7 +56,6 @@ clist_new(void)
 
 void clist_clear(clist_t *self)
 {
-  uint32_t len = self->len;
   clist_node_t *next;
   clist_node_t *curr = self->head;
 

makecopy

@@ -10,5 +10,5 @@ cp -rL $PROJECT_DIR/df_datalink_sp/src $DST_DIR/df_datalink_sp
 cp -rL $PROJECT_DIR/df_datalink_ge/src $DST_DIR/df_datalink_ge
 
 cd $DST_DIR/df_datalink_ge/networking/phy_layer
-sed -i "s/antConfig->rfTxMgc = 0;/antConfig->rfTxMgc = $GE_TXATT;/g" ./phy_antenna.c
-sed -i "s/antConfig->rcvMgc = 0;/antConfig->rcvMgc = $GE_RXATT;/g" ./phy_antenna.c
+sed -i'' -e "s/antConfig->rfTxMgc = 0;/antConfig->rfTxMgc = $GE_TXATT;/g" ./phy_antenna.c
+sed -i'' -e "s/antConfig->rcvMgc = 0;/antConfig->rcvMgc = $GE_RXATT;/g" ./phy_antenna.c