enhanced code inherence

comtool-plugin-duifei.py

@@ -0,0 +1,388 @@
+'''
+    @brief This is an example plugin, can receive and send data
+    @author
+    @date
+    @license LGPL-3.0
+'''
+from PyQt5.QtWidgets import QWidget, QVBoxLayout, QHBoxLayout, QTextEdit, QPushButton, QLabel, QScrollArea, QSplitter
+from PyQt5.QtCore import Qt, pyqtSignal
+from PyQt5.QtGui import QFont, QTextCursor
+from struct import Struct
+try:
+    import utils_ui
+    from plugins.base import Plugin_Base
+    from conn import ConnectionStatus
+    from i18n import _
+    from widgets import statusBar
+except ImportError:
+    from COMTool import utils_ui
+    from COMTool.plugins.base import Plugin_Base
+    from COMTool.i18n import _
+    from COMTool.conn import  ConnectionStatus
+    from COMTool.widgets import statusBar
+
+class Plugin(Plugin_Base):
+    id = "DEIFEI"
+    name = _("DUIFEI")
+    showReceiveDataSignal = pyqtSignal(str)
+
+    def onInit(self, config):
+        '''
+            init params
+        '''
+        default = {
+            "version": 1,
+            "customSendItems": [
+                {
+                    "caption": "Self Test",
+                    "icon": "fa5.question-circle",
+                    "data": "5A 54 E1 DD 00 BE 02 5A FE"
+                },
+                {
+                    "caption": "Config - FLJ Low Power",
+                    "icon": "fa5.play-circle",
+                    "data": "5A 54 E3 DD 88 11 00 00 00 59 06 5A FE"
+                },{
+                    "caption": "Config - FLJ Full Power",
+                    "icon": "fa5.play-circle",
+                    "data": "5A 54 E3 DD 66 11 00 00 00 37 06 5A FE"
+                }, {
+                    "caption": "Config - FLJ Silent",
+                    "icon": "fa5.play-circle",
+                    "data": "5A 54 E3 DD 00 11 00 00 00 D1 06 5A FE"
+                },{
+                    "caption": "Config - LJ Low Power",
+                    "icon": "fa5.play-circle",
+                    "data": "5A 54 E3 DD 88 00 00 00 00 48 06 5A FE"
+                },{
+                    "caption": "Config - LJ Full Power",
+                    "icon": "fa5.play-circle",
+                    "data": "5A 54 E3 DD 66 00 00 00 00 26 06 5A FE"
+                },{
+                    "caption": "Config - LJ Silent",
+                    "icon": "fa5.play-circle",
+                    "data": "5A 54 E3 DD 00 00 00 00 00 C0 06 5A FE"
+                },{
+                    "caption": "StatusCheck - FLJ",
+                    "icon": "fa5.play-circle",
+                    "data": "5A 54 E6 DD 99 00 5C 03 5A FE"
+                },{
+                    "caption": "StatusCheck - LJ",
+                    "icon": "fa5.play-circle",
+                    "data": "5A 54 F6 DD 99 00 6C 03 5A FE"
+                },{
+                    "caption": "DataRetrieve - FLJ",
+                    "icon": "fa5.play-circle",
+                    "data": "5A 54 E5 DD 77 00 39 03 5A FE"
+                },{
+                    "caption": "DataRetrieve - LJ",
+                    "icon": "fa5.play-circle",
+                    "data": "5A 54 F5 DD 77 00 49 03 5A FE"
+                }
+            ]
+        }
+        self.config = config
+        for k in default:
+            if not k in self.config:
+                self.config[k] = default[k]
+
+    def onConnChanged(self, status:ConnectionStatus, msg:str):
+        print("-- connection changed: {}, msg: {}".format(status, msg))
+
+    def onWidgetMain(self, parent):
+        '''
+            main widget, just return a QWidget object
+        '''
+        self.mainWidget = QSplitter(Qt.Vertical)
+        # receive widget
+        self.receiveWidget = QTextEdit("")
+        font = QFont('Menlo, Consolas, Bitstream Vera Sans Mono, Courier New, monospace, Microsoft YaHei', 10)
+        self.receiveWidget.setFont(font)
+        self.receiveWidget.setLineWrapMode(QTextEdit.NoWrap)
+        # clear button
+        self.clearBtn = QPushButton("")
+        utils_ui.setButtonIcon(self.clearBtn, "mdi6.broom")
+        # send scroll
+        self.customSendScroll = QScrollArea()
+        self.customSendScroll.setMinimumHeight(20)
+        self.customSendScroll.setWidgetResizable(True)
+        self.customSendScroll.setVerticalScrollBarPolicy(Qt.ScrollBarAsNeeded)
+        self.customSendScroll.setHorizontalScrollBarPolicy(Qt.ScrollBarAlwaysOff)
+        cutomSendItemsWraper = QWidget()
+        self.customSendScroll.setWidget(cutomSendItemsWraper)
+
+        # -- wrapper widget
+        cutomSendItemsWraper0 = QWidget()
+        cutomSendItemsWraper0.setProperty("class", "scrollbar2")
+        layout0 = QVBoxLayout()
+        layout0.setContentsMargins(0,8,0,0)
+        cutomSendItemsWraper0.setLayout(layout0)
+        layout0.addWidget(self.customSendScroll)
+        customSendItemsLayoutWrapper = QVBoxLayout()
+        customSendItemsLayoutWrapper.setContentsMargins(0,0,0,0)
+        cutomSendItemsWraper.setLayout(customSendItemsLayoutWrapper)
+
+        # -- items container
+        self.customItems = QWidget()
+        self.customSendItemsLayout = QVBoxLayout()
+        self.customSendItemsLayout.setContentsMargins(0,0,0,0)
+        self.customItems.setLayout(self.customSendItemsLayout)
+        customSendItemsLayoutWrapper.addWidget(self.customItems)
+        customSendItemsLayoutWrapper.addStretch(0)
+
+        # add widgets
+        self.mainWidget.addWidget(self.receiveWidget)
+        self.mainWidget.addWidget(self.clearBtn)
+        self.mainWidget.addWidget(cutomSendItemsWraper0)
+        self.mainWidget.setStretchFactor(0, 2)
+        self.mainWidget.setStretchFactor(1, 1)
+        self.mainWidget.setStretchFactor(2, 11)
+
+        # event
+        def clearReceived():
+            self.receiveWidget.clear();self.statusBar.clear()
+        self.clearBtn.clicked.connect(clearReceived)
+        return self.mainWidget
+
+    def onWidgetStatusBar(self, parent):
+        self.statusBar = statusBar(rxTxCount=True)
+        return self.statusBar
+
+    def onUiInitDone(self):
+        '''
+            UI init done, you can update your widget here
+            this method runs in UI thread, do not block too long
+        '''
+        newItems = []
+        print(self.config["customSendItems"])
+        for item in self.config["customSendItems"]:
+            print(item)
+            item = self.insertSendItem(item, load=True)
+            newItems.append(item)
+        self.config["customSendItems"] = newItems
+        self.showReceiveDataSignal.connect(self.showReceivedData)
+        # frame struct
+        self.structSelfTestRsp = Struct("<BB B BBBbbb BbBBB H")
+        self.structStatusCheckRsp = Struct("<BB Q      HIII      IBBBBI BBHH HHHIIIIII i II I      IIII d Q dBB dB H I      BBBbbb BbBBB H")
+
+    def insertSendItem(self, item = None, load = False):
+        caption = item["caption"]
+        itemWidget = QWidget()
+        layout = QHBoxLayout()
+        layout.setContentsMargins(0,0,0,0)
+        itemWidget.setLayout(layout)
+        send = QPushButton("")
+        label = QLabel(caption)
+        if (not "icon" in item) or not item["icon"]:
+            item["icon"] = "fa.send"
+        utils_ui.setButtonIcon(send, item["icon"])
+        send.setProperty("class", "smallBtn")
+        def sendCustomData(idx):
+            self.sendCustomItem(self.config["customSendItems"][idx])
+        send.clicked.connect(lambda: sendCustomData(self.customSendItemsLayout.indexOf(itemWidget)))
+        layout.addWidget(label)
+        layout.addWidget(send)
+        self.customSendItemsLayout.addWidget(itemWidget)
+        if not load:
+            self.config["customSendItems"].append(item)
+        return item
+
+    def showReceivedData(self, text: str):
+        curScrollValue = self.receiveWidget.verticalScrollBar().value()
+        self.receiveWidget.moveCursor(QTextCursor.End)
+        endScrollValue = self.receiveWidget.verticalScrollBar().value()
+        self.receiveWidget.insertPlainText(text)
+        if curScrollValue < endScrollValue:
+            self.receiveWidget.verticalScrollBar().setValue(curScrollValue)
+        else:
+            self.receiveWidget.moveCursor(QTextCursor.End)
+
+    def onReceived(self, data : bytes):
+        '''
+            call in receive thread, not UI thread
+        '''
+        self.statusBar.addRx(len(data))
+        ## Apply data validation check
+        if len(data) < 7:
+            self.showReceiveDataSignal.emit("\n### Wrong data format: wrong frame header/tail\n")
+            return
+
+        dataLen = data[-3]
+        if data[0] != 0x5A or data[1] != 0x54 or data[-1] != 0xFE or data[-2] != 0x5A:
+            self.showReceiveDataSignal.emit("\n### Wrong data format: wrong length\n")
+
+        checkSum = 0
+        for i in data[2:-4]:
+            checkSum += i
+        if checkSum & 0xFF != data[-4]:
+            self.showReceiveDataSignal.emit("\n### Wrong data format: wrong check sum\n")
+
+        ## Eval data
+        data = data[2:-5].replace(b'\x00\x54\xFE', b'\x54\xFE')
+        # self.printFrame(data)
+        if data[0] == 0xE1:
+            # eval self test
+            self.showReceiveDataSignal.emit(self.evalSelfTestRsp(data) + "\n")
+        elif data[0] == 0xE6 or data[0] == 0xF6:
+            self.showReceiveDataSignal.emit(self.evalStatusCheckRsp(data) + "\n")
+        else:
+            self.showReceiveDataSignal.emit(f"\n### Unexpected response code 0x{data[0]:02x}.\n")
+
+    def evalSelfTestRsp(self, data: bytes):
+        try:
+            payload = self.structSelfTestRsp.unpack(data)
+        except :
+            return f"\n### evalSelfTestRsp:: Failed to unpack data (data length {len(data)} byte).\n"
+
+        ret = "----------- 自检回令 -----------\n"
+        ret += "节点类型: "
+        ret += "K频段(0xDD)\n" if payload[1] == 0xDD else "S频段(0xDD)\n"
+
+        ret += "自检结果: "
+        ret += "正常(0xAA)\n" if payload[2] == 0xAA else "异常(0x55 or other)\n"
+
+        hwOffset = 3
+
+        ret += f"FPGA 电压监测: {bin(payload[hwOffset+0])[2:].zfill(8)}\n"
+        ret += f"时钟锁定状态:   {bin(payload[hwOffset+1])[2:].zfill(8)}\n"
+        ret += f"AD 锁定状态:   {bin(payload[hwOffset+2])[2:].zfill(8)}\n"
+        ret += f"AD 温度 1: {payload[hwOffset+3]:>4d}\n"
+        ret += f"AD 温度 2: {payload[hwOffset+4]:>4d}\n"
+        ret += f"FPGA 温度: {payload[hwOffset+5]:>4d}\n"
+        ret += f"电压监测: {bin(payload[hwOffset+6])[2:].zfill(8)}\n"
+        ret += f"射频温度: {payload[hwOffset+7]:>4d}\n"
+        ret += f"锁定指示: {bin(payload[hwOffset+8])[2:].zfill(8)}\n"
+        ret += f"MGC 1~2: {payload[hwOffset+9] & 0x0f:>2d} - {payload[hwOffset+9] >> 4:>2d}\n"
+        ret += f"MGC 3~4: {payload[hwOffset+10] & 0x0f:>2d} - {payload[hwOffset+10] >> 4:>2d}\n"
+        ret += "--------------------------------\n"
+
+        return ret
+
+    def printFrame(self, data: bytes):
+        ret = ''
+        for i in data:
+            ret += f'{i:02X} '
+        print(ret)
+
+    def evalStatusCheckRsp(self, data: bytes):
+        try:
+            payload = self.structStatusCheckRsp.unpack(data)
+        except :
+            return f"\n### evalStatusCheckRsp:: Failed to unpack data (data length {len(data)} byte).\n"
+
+        ret = "----------- 遥测回令 -----------\n"
+        ret += "节点类型: "
+        ret += "K频段(0xDD)\n" if payload[1] == 0xDD else "S频段(0xDD)\n"
+
+        ret += f"时间戳: {payload[2]/1e2:.2f} us\n"
+
+        sysbusOffset = 3
+        linkOffset = 7
+        phyOffset = 30
+        hwOffset = 43
+
+        ret += "\n  -- 总线状态\n"
+        ret += f"配置装订:    {payload[sysbusOffset + 0]:04X}\n"
+        ret += f"装置点名计数: {payload[sysbusOffset + 1]:>6d}\n"
+        ret += f"业务下发计数: {payload[sysbusOffset + 2]:>6d}\n"
+        ret += f"遥测请求计数: {payload[sysbusOffset + 3]:>6d}\n"
+
+        ret += "\n  -- 链路层状态\n"
+        ret += f"帧号:   {payload[linkOffset + 0]:>6d}\n"
+        ret += f"时隙号: {payload[linkOffset + 1]:>3d}\n"
+
+        ret += "当前角色: "
+        if payload[linkOffset + 2] == 0xAA:
+            ret += f"反拦截 (0x{payload[linkOffset + 2]:02X})\n"
+        elif payload[linkOffset + 2] == 0xCC:
+            ret += f"拦截 (0x{payload[linkOffset + 2]:02X})\n"
+        else:
+            ret += f"【未知错误】(0x{payload[linkOffset + 2]:02X})\n"
+
+        ret += "网络连接状态: "
+        if payload[linkOffset + 3] == 0x11:
+            ret += f"已连接 (0x{payload[linkOffset + 3]:02X})\n"
+        elif payload[linkOffset + 3] == 0x00:
+            ret += f"未连接 (0x{payload[linkOffset + 3]:02X})\n"
+        else:
+            ret += f"【未知错误】(0x{payload[linkOffset + 3]:02X})\n"
+
+        ret += "网络运行阶段: "
+        if payload[linkOffset + 4] == 0x11:
+            ret += f"扫描建网 (0x{payload[linkOffset + 4]:02X})\n"
+        elif payload[linkOffset + 4] == 0x22:
+            ret += f"业务通信 (0x{payload[linkOffset + 4]:02X})\n"
+        else:
+            ret += f"【未知错误】(0x{payload[linkOffset + 4]:02X})\n"
+
+        ret += f"重建/入网计数: {payload[linkOffset + 5]:>6d}\n"
+        ret += f"通信波位号:  {payload[linkOffset + 6]:>2d}\n"
+
+        ret += "通信波束宽度: "
+        if payload[linkOffset + 7] == 0x00:
+            ret += f"8° 窄波束 (0x{payload[linkOffset + 7]:02X})\n"
+        elif payload[linkOffset + 7] == 0x10:
+            ret += f"25° 次波束 (0x{payload[linkOffset + 7]:02X})\n"
+        elif payload[linkOffset + 7] == 0x20:
+            ret += f"60° 次波束 (0x{payload[linkOffset + 7]:02X})\n"
+        elif payload[linkOffset + 7] == 0x30:
+            ret += f"120° 宽波束 (0x{payload[linkOffset + 7]:02X})\n"
+        else:
+            ret += f"【未知错误】(0x{payload[linkOffset + 7]:02X})\n"
+
+        ret += f"离轴角: {payload[linkOffset + 8]*0.1:.2f}°\n"
+        ret += f"偏航角: {payload[linkOffset + 9]*0.1:.2f}°\n"
+        ret += f"基准帧发送计数: {payload[linkOffset + 10]:>6d}\n"
+        ret += f"基准帧接收计数: {payload[linkOffset + 11]:>6d}\n"
+        ret += f"基准帧正确计数: {payload[linkOffset + 12]:>6d}\n"
+        ret += f"双向握手帧发送计数: {payload[linkOffset + 13]:>6d}\n"
+        ret += f"双向握手帧接收计数: {payload[linkOffset + 14]:>6d}\n"
+        ret += f"双向握手帧正确计数: {payload[linkOffset + 15]:>6d}\n"
+        ret += f"业务帧发送计数: {payload[linkOffset + 16]:>6d}\n"
+        ret += f"业务帧接收计数: {payload[linkOffset + 17]:>6d}\n"
+        ret += f"业务帧正确计数: {payload[linkOffset + 18]:>6d}\n"
+        ret += f"时间偏差记录: {payload[linkOffset + 19]/1e2:.2f} us\n"
+        ret += f"发送数据 ID: {payload[linkOffset + 20]:>6d}\n"
+        ret += f"接收数据 ID: {payload[linkOffset + 21]:>6d}\n"
+
+        ret += "\n  -- 物理层状态\n"
+        ret += f"捕获计数:    {payload[phyOffset + 0]:>6d}\n"
+        ret += f"帧同步计数:  {payload[phyOffset + 1]:>6d}\n"
+        ret += f"译码计数:    {payload[phyOffset + 2]:>6d}\n"
+        ret += f"CRC 正确计数:{payload[phyOffset + 3]:>6d}\n"
+        ret += f"多普勒估计:  {payload[phyOffset + 4]:.2f} Hz\n"
+        ret += f"正确接收时刻: {payload[phyOffset + 5]/1e2:.2f} us\n"
+        ret += f"捕获峰均比:  {payload[phyOffset + 6]:.2f}\n"
+        ret += f"捕获相位值:  {payload[phyOffset + 7]:>3d}\n"
+        ret += f"捕获频偏通道: {payload[phyOffset + 8]:>3d}\n"
+        ret += f"帧同步峰均比:   {payload[phyOffset + 9]:.2f}\n"
+        ret += f"帧同步频偏通道: {payload[phyOffset + 10]:>3d}\n"
+        ret += f"交织输入数据幅度统计:\t0x{payload[phyOffset + 11]:04X}\n"
+
+        ret += "\n  -- 硬件状态\n"
+        ret += f"FPGA 电压监测: {bin(payload[hwOffset+0])[2:].zfill(8)}\n"
+        ret += f"时钟锁定状态:   {bin(payload[hwOffset+1])[2:].zfill(8)}\n"
+        ret += f"AD 锁定状态:   {bin(payload[hwOffset+2])[2:].zfill(8)}\n"
+        ret += f"AD 温度 1: {payload[hwOffset+3]:>4d}\n"
+        ret += f"AD 温度 2: {payload[hwOffset+4]:>4d}\n"
+        ret += f"FPGA 温度: {payload[hwOffset+5]:>4d}\n"
+        ret += f"电压监测: {bin(payload[hwOffset+6])[2:].zfill(8)}\n"
+        ret += f"射频温度: {payload[hwOffset+7]:>4d}\n"
+        ret += f"锁定指示: {bin(payload[hwOffset+8])[2:].zfill(8)}\n"
+        ret += f"MGC 1~2: {payload[hwOffset+9] & 0x0f:>2d} - {payload[hwOffset+9] >> 4:>2d}\n"
+        ret += f"MGC 3~4: {payload[hwOffset+10] & 0x0f:>2d} - {payload[hwOffset+10] >> 4:>2d}\n"
+
+        ret += "--------------------------------\n"
+        return ret
+
+    def onSent(self, ok, msg, length, path):
+        if ok:
+            self.statusBar.addTx(length)
+        else:
+            self.hintSignal.emit("error", _("Error"), _("Send data failed!") + " " + msg)
+
+    def sendCustomItem(self, item):
+        data = item["data"]
+        dateBytes = self.parseSendData(data, encoding = self.configGlobal["encoding"], isHexStr = True)
+        if dateBytes:
+            self.send(dateBytes, callback=self.onSent)

df_datalink_ge/src/hardware/headless.c

@@ -1,5 +1,4 @@
-/***************************************************************************//**
+/*******************************************************************************																		   *   @file   ad9371/src/app/headless.c
- *   @file   ad9371/src/app/headless.c
  *   @brief  Implementation of Main Function.
  ********************************************************************************
  * Copyright 2017(c) Analog Devices, Inc.
@@ -66,7 +65,8 @@ int HARDWARE_initialize()
 
 	Status = HARDWARE_ad9371Config();
 
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
@@ -75,11 +75,11 @@ int HARDWARE_initialize()
 	//	/**********************************************************/
 	//	Status = HW_ad9371DynamicCfgInit();
 	//	if (Status != ADIERR_OK){
-//		printf("HW:: AD9371 dynamic configuration initialization failed!\n");
+	//		HW_PRINT("HW:: AD9371 dynamic configuration initialization failed!\n");
 	//		return ADIERR_FAILED;
 	//	}
 	//
-//	printf("HW:: AD9371 ready to be reconfigured!\n");
+	//	HW_PRINT("HW:: AD9371 ready to be reconfigured!\n");
 	//
 	//	// main loop
 	//	while(1);
@@ -101,57 +101,64 @@ int HARDWARE_ad9371Config(void)
 	/*********** Initialize Configuration Interface ***********/
 	/**********************************************************/
 	Status = CMB_initPlatform();
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
 	Status = HW_adiCfgProfileInit();
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
-	printf("HW:: Initialize configuration interface done!\n");
+	HW_PRINT("HW:: Initialize configuration interface done!\n");
 
 	/**********************************************************/
 	/****************** AD9528 Configuration ******************/
 	/**********************************************************/
 	Status = HW_9528Config(ad9528Init);
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
-	printf("HW:: AD9528 configuration done!\n");
+	HW_PRINT("HW:: AD9528 configuration done!\n");
 
 	Status = HW_9528GetLockStatus(ad9528Init, &reg508);
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
-	printf("HW:: AD9528 REG508: 0x%02x\n",reg508);
+	HW_PRINT("HW:: AD9528 REG508: 0x%02x\n", reg508);
 
 	/**********************************************************/
 	/****************** AD9371 Configuration ******************/
 	/**********************************************************/
 	Status = HW_9371Config(ad9528Init, &mykDevice);
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
 	Status = HW_9371CheckJesdStatus(&mykDevice, &framerStatus,
 									&obsFramerStatus, &deframerStatus);
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
-	else {
+	else
+	{
 		// typical value: 0x3E
-		printf("HW:: RxFramerStatus = 0x%x\n", framerStatus);
+		HW_PRINT("HW:: RxFramerStatus = 0x%x\n", framerStatus);
 		// typical value: 0x3E
-		printf("HW:: OrxFramerStatus = 0x%x\n", obsFramerStatus);
+		HW_PRINT("HW:: OrxFramerStatus = 0x%x\n", obsFramerStatus);
 		// typical value: 0x28
-		printf("HW:: DeframerStatus = 0x%x\n", deframerStatus);
+		HW_PRINT("HW:: DeframerStatus = 0x%x\n", deframerStatus);
 	}
 
-	printf("HW:: All configuration done!\n");
+	HW_PRINT("HW:: All configuration done!\n");
 
 	return ADIERR_OK;
 }
@@ -163,7 +170,7 @@ int HARDWARE_ad9371Config(void)
 //
 //	Status = HW_setupIntrSystem(INTC_DEVICE_ID, &Intc);
 //	if (Status != XST_SUCCESS) {
-//		printf("HW: HW_setupIntrSystem() failed!\n");
+//		HW_PRINT("HW: HW_setupIntrSystem() failed!\n");
 //		return XST_FAILURE;
 //	}
 //
@@ -171,7 +178,7 @@ int HARDWARE_ad9371Config(void)
 //	Status |= XGpio_Initialize(&GpioGainCtrl, GAIN_CTRL_DEVICE_ID);
 //	Status |= XGpio_Initialize(&GpioAttnCtrl, ATTN_CTRL_DEVICE_ID);
 //	if (Status != XST_SUCCESS) {
-//		printf("HW: GPIO init failed!\n");
+//		HW_PRINT("HW: GPIO init failed!\n");
 //		return XST_FAILURE;
 //	}
 //
@@ -229,14 +236,16 @@ int HW_setupIntrSystem(u16 DeviceId, XScuGic * GicPtr)
 	 * use.
 	 */
 	CfgPtr = XScuGic_LookupConfig(DeviceId);
-    if (!CfgPtr) {
+	if (!CfgPtr)
-        printf("No interrupt config found for %d\n", DeviceId);
+	{
+		HW_PRINT("No interrupt config found for %d\n", DeviceId);
 		return XST_FAILURE;
 	}
 
 	Status = XScuGic_CfgInitialize(GicPtr, CfgPtr, CfgPtr->CpuBaseAddress);
-    if (Status != XST_SUCCESS) {
+	if (Status != XST_SUCCESS)
-        printf("No interrupt config found for %d\n", DeviceId);
+	{
+		HW_PRINT("No interrupt config found for %d\n", DeviceId);
 		return XST_FAILURE;
 	}
 
@@ -249,7 +258,6 @@ int HW_setupIntrSystem(u16 DeviceId, XScuGic * GicPtr)
 	return XST_SUCCESS;
 }
 
-
 int HW_connectIntr(XScuGic *GicPtr, u32 IntrId, Xil_InterruptHandler Handler,
 				   void *CallBackRef, u8 Priority, u8 Trigger)
 {
@@ -268,16 +276,17 @@ int HW_connectIntr(XScuGic *GicPtr,u32 IntrId,Xil_InterruptHandler Handler,
 	return XST_SUCCESS;
 }
 
-
 int HW_adiCfgProfileInit(void)
 {
-	if (!ad9528Init) {
+	if (!ad9528Init)
-		printf("Cannot find ad9528 configuration profile with name 'ad9528Init'!");
+	{
+		HW_PRINT("Cannot find ad9528 configuration profile with name 'ad9528Init'!");
 		return ADIERR_FAILED;
 	}
 
-	if (!&mykDevice) {
+	if (!&mykDevice)
-		printf("Cannot find ad9371 configuration profile with name 'mykDevice'!");
+	{
+		HW_PRINT("Cannot find ad9371 configuration profile with name 'mykDevice'!");
 		return ADIERR_FAILED;
 	}
 
@@ -293,7 +302,6 @@ int HW_adiCfgProfileInit(void)
 	return ADIERR_OK;
 }
 
-
 int HW_9528Config(ad9528Device_t *clockAD9528_device)
 {
 	ADI_ERR error;
@@ -303,8 +311,9 @@ int HW_9528Config(ad9528Device_t *clockAD9528_device)
 
 	/* Perform a hard reset on the AD9528 DUT */
 	error = AD9528_resetDevice(clockAD9528_device);
-	if (error != ADIERR_OK) {
+	if (error != ADIERR_OK)
-		printf("AD9528_resetDevice() failed\n");
+	{
+		HW_PRINT("AD9528_resetDevice() failed\n");
 		return ADIERR_FAILED;
 	}
 
@@ -312,35 +321,36 @@ int HW_9528Config(ad9528Device_t *clockAD9528_device)
 										clockAD9528_device->pll1Settings->vcxo_Frequency_Hz,
 										clockAD9528_device->pll1Settings->refA_Frequency_Hz,
 										clockAD9528_device->outputSettings->outFrequency_Hz[1]);
-	if (error != ADIERR_OK) {
+	if (error != ADIERR_OK)
-		printf("AD9528_initDeviceDataStruct() failed\n");
+	{
+		HW_PRINT("AD9528_initDeviceDataStruct() failed\n");
 		return ADIERR_FAILED;
 	}
 
 	/* Initialize the AD9528 by writing all SPI registers */
 	error = AD9528_initialize(clockAD9528_device);
-	if (error != ADIERR_OK) {
+	if (error != ADIERR_OK)
-		printf("WARNING: AD9528_initialize() issues.\n");
+	{
+		HW_PRINT("WARNING: AD9528_initialize() issues.\n");
 	}
 
 	return ADIERR_OK;
 }
 
-
 int HW_9528GetLockStatus(ad9528Device_t *device, uint8_t *reg508)
 {
 	ADI_ERR error;
 
 	error = CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, reg508);
-	if (error != ADIERR_OK) {
+	if (error != ADIERR_OK)
-		printf("HW_9528GetLockStatus failed.\n");
+	{
+		HW_PRINT("HW_9528GetLockStatus failed.\n");
 		return ADIERR_FAILED;
 	}
 
 	return ADIERR_OK;
 }
 
-
 int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice)
 {
 	ADI_ERR error;
@@ -365,19 +375,19 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/* Allocating memory for the errorString */
 	errorString = NULL;
 
-
-
 	/*************************************************************************/
 	/*****                Mykonos Initialization Sequence                *****/
 	/*************************************************************************/
 
 	/* Perform a hard reset on the MYKONOS DUT (Toggle RESETB pin on device) */
-	if ((mykError = MYKONOS_resetDevice(mykDevice)) != MYKONOS_ERR_OK) {
+	if ((mykError = MYKONOS_resetDevice(mykDevice)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
-	if ((mykError = MYKONOS_initialize(mykDevice)) != MYKONOS_ERR_OK) {
+	if ((mykError = MYKONOS_initialize(mykDevice)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -387,7 +397,8 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_checkPllsLockStatus(mykDevice,
-			&pllLockStatus)) != MYKONOS_ERR_OK) {
+												&pllLockStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -397,7 +408,8 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_enableMultichipSync(mykDevice, 1,
-			&mcsStatus)) != MYKONOS_ERR_OK) {
+												&mcsStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -418,34 +430,40 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_enableMultichipSync(mykDevice, 0,
-			&mcsStatus)) != MYKONOS_ERR_OK) {
+												&mcsStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	if ((mcsStatus & 0x0B) == 0x0B)
-		printf("MCS successful\n");
+		HW_PRINT("MCS successful\n");
 	else
-		printf("MCS failed\n");
+		HW_PRINT("MCS failed\n");
 
 	/*************************************************************************/
 	/*****                Mykonos Load ARM file                          *****/
 	/*************************************************************************/
 
-	if (pllLockStatus & 0x01) {
+	if (pllLockStatus & 0x01)
-		printf("CLKPLL locked\n");
+	{
-		if ((mykError = MYKONOS_initArm(mykDevice)) != MYKONOS_ERR_OK) {
+		HW_PRINT("CLKPLL locked\n");
+		if ((mykError = MYKONOS_initArm(mykDevice)) != MYKONOS_ERR_OK)
+		{
 			errorString = getMykonosErrorMessage(mykError);
 			goto error_11;
 		}
 
 		if ((mykError = MYKONOS_loadArmFromBinary(mykDevice,
-				&firmware_Mykonos_M3_bin[0], firmware_Mykonos_M3_bin_len)) != MYKONOS_ERR_OK) {
+												  &firmware_Mykonos_M3_bin[0], firmware_Mykonos_M3_bin_len)) != MYKONOS_ERR_OK)
+		{
 			errorString = getMykonosErrorMessage(mykError);
 			goto error_11;
 		}
-	} else {
+	}
-		printf("CLKPLL not locked (0x%x)\n", pllLockStatus);
+	else
+	{
+		HW_PRINT("CLKPLL not locked (0x%x)\n", pllLockStatus);
 		error = ADIERR_FAILED;
 		goto error_2;
 	}
@@ -453,26 +471,29 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/* Read back the version of the ARM binary loaded into the Mykonos ARM memory */
 	if ((mykError = MYKONOS_getArmVersion(mykDevice, &arm_major, &arm_minor,
 										  &arm_release, NULL)) == MYKONOS_ERR_OK)
-		printf("AD9371 ARM version %d.%d.%d\n", arm_major, arm_minor, arm_release);
+		HW_PRINT("AD9371 ARM version %d.%d.%d\n", arm_major, arm_minor, arm_release);
 
 	/*************************************************************************/
 	/*****                Mykonos Set RF PLL Frequencies                 *****/
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, RX_PLL,
-			mykDevice->rx->rxPllLoFrequency_Hz)) != MYKONOS_ERR_OK) {
+											  mykDevice->rx->rxPllLoFrequency_Hz)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, TX_PLL,
-			mykDevice->tx->txPllLoFrequency_Hz)) != MYKONOS_ERR_OK) {
+											  mykDevice->tx->txPllLoFrequency_Hz)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, SNIFFER_PLL,
-			mykDevice->obsRx->snifferPllLoFrequency_Hz)) != MYKONOS_ERR_OK) {
+											  mykDevice->obsRx->snifferPllLoFrequency_Hz)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -481,15 +502,17 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	mdelay(200);
 
 	if ((mykError = MYKONOS_checkPllsLockStatus(mykDevice,
-			&pllLockStatus)) != MYKONOS_ERR_OK) {
+												&pllLockStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	if ((pllLockStatus & 0x0F) == 0x0F)
-		printf("PLLs locked\n");
+		HW_PRINT("PLLs locked\n");
-	else {
+	else
-		printf("PLLs not locked (0x%x)\n", pllLockStatus);
+	{
+		HW_PRINT("PLLs not locked (0x%x)\n", pllLockStatus);
 		error = ADIERR_FAILED;
 		goto error_2;
 	}
@@ -592,56 +615,67 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_runInitCals(mykDevice,
-					    (initCalMask & ~TX_LO_LEAKAGE_EXTERNAL))) != MYKONOS_ERR_OK) {
+										(initCalMask & ~TX_LO_LEAKAGE_EXTERNAL))) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	if ((mykError = MYKONOS_waitInitCals(mykDevice, 60000, &errorFlag,
-					     &errorCode)) != MYKONOS_ERR_OK) {
+										 &errorCode)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
-	if ((errorFlag != 0) || (errorCode != 0)) {
+	if ((errorFlag != 0) || (errorCode != 0))
+	{
 		/*** < Info: abort init cals > ***/
 		if ((mykError = MYKONOS_abortInitCals(mykDevice,
-						      &initCalsCompleted)) != MYKONOS_ERR_OK) {
+											  &initCalsCompleted)) != MYKONOS_ERR_OK)
+		{
 			errorString = getMykonosErrorMessage(mykError);
 			goto error_11;
 		}
 		if (initCalsCompleted)
-			printf("Completed calibrations: %x\n", (unsigned int)initCalsCompleted);
+			HW_PRINT("Completed calibrations: %x\n", (unsigned int)initCalsCompleted);
-	} else
+	}
-		printf("Calibrations completed successfully\n");
+	else
+		HW_PRINT("Calibrations completed successfully\n");
 
 	/*************************************************************************/
 	/*****  Mykonos ARM Initialization External LOL Calibrations with PA *****/
 	/*************************************************************************/
 
 	/* Please ensure PA is enabled operational at this time */
-	if (initCalMask & TX_LO_LEAKAGE_EXTERNAL) {
+	if (initCalMask & TX_LO_LEAKAGE_EXTERNAL)
+	{
 		if ((mykError = MYKONOS_runInitCals(mykDevice,
-						    TX_LO_LEAKAGE_EXTERNAL)) != MYKONOS_ERR_OK) {
+											TX_LO_LEAKAGE_EXTERNAL)) != MYKONOS_ERR_OK)
+		{
 			errorString = getMykonosErrorMessage(mykError);
 			goto error_11;
 		}
 
 		if ((mykError = MYKONOS_waitInitCals(mykDevice, 60000, &errorFlag,
-						     &errorCode)) != MYKONOS_ERR_OK) {
+											 &errorCode)) != MYKONOS_ERR_OK)
+		{
 			errorString = getMykonosErrorMessage(mykError);
 			goto error_11;
 		}
 
-		if ((errorFlag != 0) || (errorCode != 0)) {
+		if ((errorFlag != 0) || (errorCode != 0))
+		{
 			/*** < Info: abort init cals > ***/
 			if ((mykError = MYKONOS_abortInitCals(mykDevice,
-							      &initCalsCompleted)) != MYKONOS_ERR_OK) {
+												  &initCalsCompleted)) != MYKONOS_ERR_OK)
+			{
 				errorString = getMykonosErrorMessage(mykError);
 				goto error_11;
 			}
-		} else
+		}
-			printf("External LOL Calibrations completed successfully\n");
+		else
+			HW_PRINT("External LOL Calibrations completed successfully\n");
 	}
 
 	/*************************************************************************/
@@ -649,7 +683,8 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_enableSysrefToRxFramer(mykDevice,
-			1)) != MYKONOS_ERR_OK) {
+												   1)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -657,7 +692,8 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	 * transmitting CGS from the RxFramer> ***/
 
 	if ((mykError = MYKONOS_enableSysrefToObsRxFramer(mykDevice,
-			1)) != MYKONOS_ERR_OK) {
+													  1)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -665,18 +701,20 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	 * transmitting CGS from the ObsRxFramer> ***/
 
 	if ((mykError = MYKONOS_enableSysrefToDeframer(mykDevice,
-			0)) != MYKONOS_ERR_OK) {
+												   0)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
-	if ((mykError = MYKONOS_resetDeframer(mykDevice)) != MYKONOS_ERR_OK) {
+	if ((mykError = MYKONOS_resetDeframer(mykDevice)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
-	if ((mykError = MYKONOS_enableSysrefToDeframer(mykDevice,
+	if ((mykError = MYKONOS_enableSysrefToDeframer(mykDevice, 1)) != MYKONOS_ERR_OK)
-			1)) != MYKONOS_ERR_OK) {
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -704,7 +742,8 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_enableTrackingCals(mykDevice,
-			trackingCalMask)) != MYKONOS_ERR_OK) {
+											   trackingCalMask)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -714,19 +753,22 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 
 	/*** < Info: Function to turn radio on, Enables transmitters and receivers
 	 * that were setup during MYKONOS_initialize() > ***/
-	if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK) {
+	if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	/*** < Info: Allow TxQEC to run when User: is not actively using ORx receive path > ***/
 	if ((mykError = MYKONOS_setObsRxPathSource(mykDevice,
-			OBS_RXOFF)) != MYKONOS_ERR_OK) {
+											   OBS_RXOFF)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 	if ((mykError = MYKONOS_setObsRxPathSource(mykDevice,
-			OBS_INTERNALCALS)) != MYKONOS_ERR_OK) {
+											   OBS_INTERNALCALS)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -734,26 +776,26 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	mdelay(1000);
 
 	if ((mykError = MYKONOS_setObsRxPathSource(mykDevice,
-			OBS_RX1_SNIFFERLO)) != MYKONOS_ERR_OK) {
+											   OBS_RX1_SNIFFERLO)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	Xil_DCacheInvalidateRange(DDR_MEM_BASEADDR + 0x800000, 16384 * 8);
 
-	printf("Done\n");
+	HW_PRINT("Done\n");
 
 	return 0;
 
 error_11:
-	printf("%s", errorString);
+	HW_PRINT("%s", errorString);
 
 error_2:
 	//	axi_clkgen_remove(rx_clkgen);
 	return FAILURE;
 }
 
-
 int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus,
 						   uint8_t *obsFramerStatus, uint8_t *deframerStatus)
 {
@@ -767,19 +809,24 @@ int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus,
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_readRxFramerStatus(mykDevice,
-			framerStatus)) != MYKONOS_ERR_OK) {
+											   framerStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		return ADIERR_FAILED;
 	}
-	else {
+	else
+	{
 		// typical value: 0x3E
 	}
 
 	if ((mykError = MYKONOS_readOrxFramerStatus(mykDevice,
-			obsFramerStatus)) != MYKONOS_ERR_OK) {
+												obsFramerStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		return ADIERR_FAILED;
-	} else {
+	}
+	else
+	{
 		// typical value: 0x3E
 	}
 
@@ -788,17 +835,19 @@ int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus,
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_readDeframerStatus(mykDevice,
-			deframerStatus)) != MYKONOS_ERR_OK) {
+											   deframerStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		return ADIERR_FAILED;
-	} else {
+	}
+	else
+	{
 		// typical value: 0x28
 	}
 
 	return ADIERR_OK;
 }
 
-
 int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 {
 	mykonosErr_t mykError = MYKONOS_ERR_OK;
@@ -808,7 +857,7 @@ int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	 */
 	if ((mykError = MYKONOS_radioOff(mykDevice)) != MYKONOS_ERR_OK)
 	{
-		printf("Turn radio off failed!\n\r");
+		HW_PRINT("Turn radio off failed!\n\r");
 		return ADIERR_FAILED;
 	}
 
@@ -818,14 +867,14 @@ int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, TX_PLL,
 											  freq_Hz)) != MYKONOS_ERR_OK)
 	{
-		printf("Set TX PLL failed!\n\r");
+		HW_PRINT("Set TX PLL failed!\n\r");
 		return ADIERR_FAILED;
 	}
 	mykError = MYKONOS_checkPllsLockStatus(mykDevice, &pllLockStatus);
 	if ((pllLockStatus & 0x07) != 0x07)
 	{
 		/*** < Info: Clock, Rx and Tx PLLs not locked > ***/
-		printf("Not all PLLs locked, lock status: 0x%02x\n", pllLockStatus);
+		HW_PRINT("Not all PLLs locked, lock status: 0x%02x\n", pllLockStatus);
 	}
 
 	/*
@@ -834,7 +883,7 @@ int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	//	If((mykError = MYKONOS_resetExtTxLolChannel(mykDevice, TX1_TX2))
 	//		!= MYKONOS_ERR_OK) ; //where TX1_TX2 is part of the enum mykonosTxChannels_t
 	//	{
-//		printf("Reset external channel FAILED!");
+	//		HW_PRINT("Reset external channel FAILED!");
 	//	}
 
 	/*
@@ -842,7 +891,7 @@ int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	 */
 	if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK)
 	{
-		printf("Turn radio on failed!\n\r");
+		HW_PRINT("Turn radio on failed!\n\r");
 		return ADIERR_FAILED;
 	}
 
@@ -852,12 +901,11 @@ int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	//	If((mykError = MYKONOS_MYKONOS_setObsRxPathSource(mykDevice, OBS_INTERNALCALS))
 	//		!= MYKONOS_ERR_OK) ; //where TX1_TX2 is part of the enum mykonosTxChannels_t
 	//	{
-//		printf("Reenable tracking calibrations FAILED!");
+	//		HW_PRINT("Reenable tracking calibrations FAILED!");
 	//	}
 	return ADIERR_OK;
 }
 
-
 int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 {
 	mykonosErr_t mykError = MYKONOS_ERR_OK;
@@ -875,7 +923,7 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	 */
 	if ((mykError = MYKONOS_radioOff(mykDevice)) != MYKONOS_ERR_OK)
 	{
-		printf("Turn radio off failed!\n\r");
+		HW_PRINT("Turn radio off failed!\n\r");
 		return ADIERR_FAILED;
 	}
 
@@ -885,14 +933,14 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, TX_PLL,
 											  freq_Hz)) != MYKONOS_ERR_OK)
 	{
-		printf("Set TX PLL failed!\n\r");
+		HW_PRINT("Set TX PLL failed!\n\r");
 		return ADIERR_FAILED;
 	}
 	mykError = MYKONOS_checkPllsLockStatus(mykDevice, &pllLockStatus);
 	if ((pllLockStatus & 0x07) != 0x07)
 	{
 		/*** < Info: Clock, Rx and Tx PLLs not locked > ***/
-		printf("Not all PLLs locked, lock status: 0x%02x\n", pllLockStatus);
+		HW_PRINT("Not all PLLs locked, lock status: 0x%02x\n", pllLockStatus);
 	}
 
 	/*
@@ -900,34 +948,30 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	 */
 	uint32_t initCalMask = TX_QEC_INIT | LOOPBACK_RX_LO_DELAY |
 						   LOOPBACK_RX_RX_QEC_INIT | RX_LO_DELAY | RX_QEC_INIT;
-	if ((mykError = MYKONOS_runInitCals(mykDevice, initCalMask))
+	if ((mykError = MYKONOS_runInitCals(mykDevice, initCalMask)) != MYKONOS_ERR_OK)
-		!= MYKONOS_ERR_OK)
 	{
-		printf("Rerun the initialization calibrations FAILED!");
+		HW_PRINT("Rerun the initialization calibrations FAILED!");
 		return ADIERR_FAILED;
 	}
 	if ((mykError = MYKONOS_waitInitCals(mykDevice, 60000, &errorFlag,
 										 &errorCode)) != MYKONOS_ERR_OK)
 	{
-		printf("Initialize calibration TIME OUT!");
+		HW_PRINT("Initialize calibration TIME OUT!");
 		return ADIERR_FAILED;
 	}
 	if ((errorFlag != 0) || (errorCode != 0))
 	{
-		printf("initial cals error!\n\r");
+		HW_PRINT("initial cals error!\n\r");
 
-		if((mykError = MYKONOS_getInitCalStatus(mykDevice, &initCalStatus))
+		if ((mykError = MYKONOS_getInitCalStatus(mykDevice, &initCalStatus)) != MYKONOS_ERR_OK)
-			!= MYKONOS_ERR_OK)
 		{
 			/*** < User log error return value to debug why init failed > ***/
 		}
 
 		// abort init calibrations
-		if((mykError = MYKONOS_abortInitCals(mykDevice, &initCalsCompleted))
+		if ((mykError = MYKONOS_abortInitCals(mykDevice, &initCalsCompleted)) != MYKONOS_ERR_OK)
-			!= MYKONOS_ERR_OK)
 		{
 			/*** < User log error return value to debug why init failed > ***/
-
 		}
 		if (initCalsCompleted)
 		{
@@ -938,10 +982,8 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 		{
 			/*** < User log error return value to debug why init failed > ***/
 		}
-		if((mykError = MYKONOS_readArmCmdStatusByte(mykDevice, 2, &status))
+		if ((mykError = MYKONOS_readArmCmdStatusByte(mykDevice, 2, &status)) != MYKONOS_ERR_OK)
-			!= MYKONOS_ERR_OK)
 		{
-
 		}
 		if (status != 0)
 		{
@@ -955,26 +997,25 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	 */
 	if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK)
 	{
-		printf("Turn radio on failed!\n\r");
+		HW_PRINT("Turn radio on failed!\n\r");
 		return ADIERR_FAILED;
 	}
 
 	return ADIERR_OK;
 }
 
-
 // void FreqIntrHandler(void *CallbackRef)
 // {
 // 	XGpio *GpioPtr = (XGpio *)CallbackRef;
 // 	uint8_t IntrStatus;
 // 	uint32_t NewFreqHz;
 // 	IntrStatus = XGpio_InterruptGetStatus(GpioPtr);
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH1_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH1_MASK);
-//
+
 // 		NewFreqHz = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_1);
 // 		if (NewFreqHz != mykDevice.tx->txPllLoFrequency_Hz)
 // 		{
@@ -989,20 +1030,20 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 					HW_9371LargeFrequencyChange(&mykDevice, NewFreqHz);
 // 				}
 // 				mykDevice.tx->txPllLoFrequency_Hz = NewFreqHz;
-//				printf("New Tx frequency set to %d Hz!\n",NewFreqHz);
+// 				HW_PRINT("New Tx frequency set to %d Hz!\n", NewFreqHz);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Tx Frequency is out of range(300 ~ 6000 MHz)!\n");
+// 				HW_PRINT("The desired Tx Frequency is out of range(300 ~ 6000 MHz)!\n");
 // 			}
 // 		}
 // 	}
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH2_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH2_MASK);
-//
+
 // 		NewFreqHz = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_2);
 // 		if (NewFreqHz != mykDevice.rx->rxPllLoFrequency_Hz)
 // 		{
@@ -1017,29 +1058,28 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 					HW_9371LargeFrequencyChange(&mykDevice, NewFreqHz);
 // 				}
 // 				mykDevice.rx->rxPllLoFrequency_Hz = NewFreqHz;
-//				printf("New Rx frequency set to %d Hz!\n",NewFreqHz);
+// 				HW_PRINT("New Rx frequency set to %d Hz!\n", NewFreqHz);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Rx Frequency is out of range(300 ~ 6000 MHz)!\n");
+// 				HW_PRINT("The desired Rx Frequency is out of range(300 ~ 6000 MHz)!\n");
 // 			}
 // 		}
 // 	}
 // }
-//
+
-//
 // void GainIntrHandler(void *CallbackRef)
 // {
 // 	XGpio *GpioPtr = (XGpio *)CallbackRef;
 // 	uint8_t IntrStatus;
 // 	uint32_t NewRxGain;
 // 	IntrStatus = XGpio_InterruptGetStatus(GpioPtr);
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH1_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH1_MASK);
-//
+
 // 		NewRxGain = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_1);
 // 		if (NewRxGain != mykDevice.rx->rxGainCtrl->rx1GainIndex)
 // 		{
@@ -1048,21 +1088,21 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 				MYKONOS_setRx1ManualGain(&mykDevice, NewRxGain);
 // 				mykDevice.rx->rxGainCtrl->rx1GainIndex = NewRxGain;
 // 				char buf[BUFSIZ];
-//				sprintf(buf, "%u", NewRxGain);
+// 				sHW_PRINT(buf, "%u", NewRxGain);
-//				printf("New Rx1 gain index set to %s!\n",buf);
+// 				HW_PRINT("New Rx1 gain index set to %s!\n", buf);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Rx1 gain index is out of range(195 ~ 255), 0.5dB per stage!\n");
+// 				HW_PRINT("The desired Rx1 gain index is out of range(195 ~ 255), 0.5dB per stage!\n");
 // 			}
 // 		}
 // 	}
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH2_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH2_MASK);
-//
+
 // 		NewRxGain = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_2);
 // 		if (NewRxGain != mykDevice.rx->rxGainCtrl->rx2GainIndex)
 // 		{
@@ -1071,30 +1111,29 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 				MYKONOS_setRx2ManualGain(&mykDevice, NewRxGain);
 // 				mykDevice.rx->rxGainCtrl->rx2GainIndex = NewRxGain;
 // 				char buf[BUFSIZ];
-//				sprintf(buf, "%u", NewRxGain);
+// 				sHW_PRINT(buf, "%u", NewRxGain);
-//				printf("New Rx2 gain index set to %s!\n",buf);
+// 				HW_PRINT("New Rx2 gain index set to %s!\n", buf);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Rx2 gain index is out of range(195 ~ 255), 0.5dB per stage!\n");
+// 				HW_PRINT("The desired Rx2 gain index is out of range(195 ~ 255), 0.5dB per stage!\n");
 // 			}
 // 		}
 // 	}
 // }
-//
+
-//
 // void AttnIntrHandler(void *CallbackRef)
 // {
 // 	XGpio *GpioPtr = (XGpio *)CallbackRef;
 // 	uint8_t IntrStatus;
 // 	uint32_t NewTxAttn;
 // 	IntrStatus = XGpio_InterruptGetStatus(GpioPtr);
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH1_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH1_MASK);
-//
+
 // 		NewTxAttn = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_1);
 // 		if (NewTxAttn != mykDevice.tx->tx1Atten_mdB)
 // 		{
@@ -1103,21 +1142,21 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 				MYKONOS_setTx1Attenuation(&mykDevice, NewTxAttn);
 // 				mykDevice.tx->tx1Atten_mdB = NewTxAttn;
 // 				char buf[BUFSIZ];
-//				sprintf(buf, "%u", NewTxAttn);
+// 				sHW_PRINT(buf, "%u", NewTxAttn);
-//				printf("New Tx1 attenuation set to %s dBm!\n",buf);
+// 				HW_PRINT("New Tx1 attenuation set to %s dBm!\n", buf);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Tx1 attenuation is out of range(0 ~ 41950 dBm), 50 dBm step!\n");
+// 				HW_PRINT("The desired Tx1 attenuation is out of range(0 ~ 41950 dBm), 50 dBm step!\n");
 // 			}
 // 		}
 // 	}
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH2_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH2_MASK);
-//
+
 // 		NewTxAttn = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_2);
 // 		if (NewTxAttn != mykDevice.tx->tx2Atten_mdB)
 // 		{
@@ -1126,12 +1165,12 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 				MYKONOS_setTx2Attenuation(&mykDevice, NewTxAttn);
 // 				mykDevice.tx->tx2Atten_mdB = NewTxAttn;
 // 				char buf[BUFSIZ];
-//				sprintf(buf, "%u", NewTxAttn);
+// 				sHW_PRINT(buf, "%u", NewTxAttn);
-//				printf("New Tx2 attenuation set to %s dBm!\n",buf);
+// 				HW_PRINT("New Tx2 attenuation set to %s dBm!\n", buf);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Tx2 attenuation is out of range(0 ~ 41950 dBm), 50 dBm step!\n");
+// 				HW_PRINT("The desired Tx2 attenuation is out of range(0 ~ 41950 dBm), 50 dBm step!\n");
 // 			}
 // 		}
 // 	}

df_datalink_ge/src/hardware/headless.h

@@ -1,7 +1,7 @@
 /*
  * headless.h
  *
- *  Created on: 2021Äê6ÔÂ8ÈÕ
+ *  Created on: 2021��6��8��
  *      Author: Josh
  */
 
@@ -30,7 +30,8 @@
 /**************************** Type Definitions *******************************/
 
 /***************** Macros (Inline Functions) Definitions *********************/
-
+#define HW_PRINT(...)  __asm__("nop")
+// #define HW_PRINT(...)  printf(__VA_ARGS__)
 /************************** Variable Definitions *****************************/
 
 /************************** Function Prototypes ******************************/

df_datalink_ge/src/main.c

@@ -51,33 +51,39 @@ void ScuTimer_IntrHandler(void *context);
 void Systembus_RxIntrHandler(void *context);
 void Systembus_TxIntrHandler(void *context);
 /************************** Constant Definitions *****************************/
-struct callback_desc phy_callback_desc = {
+struct callback_desc phy_callback_desc =
+{
 	.callback = Phy_IntrHandler,
 	.ctx = NULL
 };
 
-struct callback_desc periodicpull_callback_desc = {
+struct callback_desc periodicpull_callback_desc =
+{
 	.callback = PeriodicPull_Handler,
 	.ctx = NULL
 };
 
 
-struct callback_desc sysbus_rx_callback_desc = {
+struct callback_desc sysbus_rx_callback_desc =
+{
 	.callback = Systembus_RxIntrHandler,
 	.ctx = NULL
 };
 
-struct callback_desc sysbus_tx_callback_desc = {
+struct callback_desc sysbus_tx_callback_desc =
+{
 	.callback = Systembus_TxIntrHandler,
 	.ctx = NULL
 };
 
-struct callback_desc scutm_callback_desc = {
+struct callback_desc scutm_callback_desc =
+{
 	.callback = ScuTimer_IntrHandler,
 	.ctx = NULL
 };
 
-L2_CONFIG linkConfig = {
+L2_CONFIG linkConfig =
+{
 	.myType = L2_NODE_HEAD,
 	.clustId = 1,
 	.myId = 1,
@@ -99,16 +105,23 @@ L2_CONFIG linkConfig = {
 // 	.tmcInstPtr = NULL
 // };
 
-static PHY_CONFIG phyConfig = {
+static PHY_CONFIG phyConfig =
+{
 	.devId = 0,
 	.baseAddr = PHY_BASEADDR,
 	.antBramId = PHY_ANTCONFIG_BRAM_DEVICE_ID,
+	.antInfoBramId = -1,
 	.txBramId = PHY_TXBUFF_BRAM_DEVICE_ID,
 	.rxBramId = PHY_RXBUFF_BRAM_DEVICE_ID,
-	.hwXadcId = PHY_HW_XADC_DEVICE_ID
+	.hwXadcId = PHY_HW_XADC_DEVICE_ID,
+	.get_clk_state = NULL,
+	.get_ad_lock_state = NULL,
+	.get_ad0_temp = NULL,
+	.get_ad1_temp = NULL
 };
 
-TMC_CONFIG tmcConfig = {
+TMC_CONFIG tmcConfig =
+{
 	.baseAddr = TIME_CONTROLLER_BASEADDR,
 	.reset = 10
 };

df_datalink_sp/bsp/ps7_cortexa9_0/include/xparameters.h

@@ -42,10 +42,28 @@
  
 /******************************************************************/
 /* Definitions for driver BRAM */
-#define XPAR_XBRAM_NUM_INSTANCES 3U
+#define XPAR_XBRAM_NUM_INSTANCES 4U
+
+/* Definitions for peripheral PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL */
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DEVICE_ID 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DATA_WIDTH 32U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_FAULT_INJECT 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_CE_FAILING_REGISTERS 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_UE_FAILING_REGISTERS 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_CE_COUNTER_WIDTH 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_WRITE_ACCESS 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_BASEADDR 0x42000000U
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_HIGHADDR 0x42000FFFU
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
+
 
 /* Definitions for peripheral PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL */
-#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID 0U
+#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID 1U
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DATA_WIDTH 32U
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC 0U
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_FAULT_INJECT 0U
@@ -63,7 +81,7 @@
 
 
 /* Definitions for peripheral PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL */
-#define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID 1U
+#define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID 2U
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DATA_WIDTH 32U
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_ECC 0U
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_FAULT_INJECT 0U
@@ -81,7 +99,7 @@
 
 
 /* Definitions for peripheral PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL */
-#define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID 2U
+#define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID 3U
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DATA_WIDTH 32U
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_ECC 0U
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_FAULT_INJECT 0U
@@ -100,8 +118,8 @@
 
 /******************************************************************/
 
-/* Canonical definitions for peripheral PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL */
+/* Canonical definitions for peripheral PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL */
-#define XPAR_BRAM_0_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID
+#define XPAR_BRAM_0_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DEVICE_ID
 #define XPAR_BRAM_0_DATA_WIDTH 32U
 #define XPAR_BRAM_0_ECC 0U
 #define XPAR_BRAM_0_FAULT_INJECT 0U
@@ -112,13 +130,13 @@
 #define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0U
 #define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_0_WRITE_ACCESS 0U
-#define XPAR_BRAM_0_BASEADDR 0x40004000U
+#define XPAR_BRAM_0_BASEADDR 0x42000000U
-#define XPAR_BRAM_0_HIGHADDR 0x40005FFFU
+#define XPAR_BRAM_0_HIGHADDR 0x42000FFFU
 #define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU  
 
-/* Canonical definitions for peripheral PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL */
+/* Canonical definitions for peripheral PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL */
-#define XPAR_BRAM_1_DEVICE_ID XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID
+#define XPAR_BRAM_1_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID
 #define XPAR_BRAM_1_DATA_WIDTH 32U
 #define XPAR_BRAM_1_ECC 0U
 #define XPAR_BRAM_1_FAULT_INJECT 0U
@@ -129,13 +147,13 @@
 #define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0U
 #define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_1_WRITE_ACCESS 0U
-#define XPAR_BRAM_1_BASEADDR 0x40000000U
+#define XPAR_BRAM_1_BASEADDR 0x40004000U
-#define XPAR_BRAM_1_HIGHADDR 0x40001FFFU
+#define XPAR_BRAM_1_HIGHADDR 0x40005FFFU
 #define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU  
 
-/* Canonical definitions for peripheral PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL */
+/* Canonical definitions for peripheral PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL */
-#define XPAR_BRAM_2_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
+#define XPAR_BRAM_2_DEVICE_ID XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID
 #define XPAR_BRAM_2_DATA_WIDTH 32U
 #define XPAR_BRAM_2_ECC 0U
 #define XPAR_BRAM_2_FAULT_INJECT 0U
@@ -146,11 +164,28 @@
 #define XPAR_BRAM_2_ECC_ONOFF_REGISTER 0U
 #define XPAR_BRAM_2_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_2_WRITE_ACCESS 0U
-#define XPAR_BRAM_2_BASEADDR 0x40002000U
+#define XPAR_BRAM_2_BASEADDR 0x40000000U
-#define XPAR_BRAM_2_HIGHADDR 0x40003FFFU
+#define XPAR_BRAM_2_HIGHADDR 0x40001FFFU
 #define XPAR_BRAM_2_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_2_CTRL_HIGHADDR 0xFFFFFFFEU  
 
+/* Canonical definitions for peripheral PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL */
+#define XPAR_BRAM_3_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
+#define XPAR_BRAM_3_DATA_WIDTH 32U
+#define XPAR_BRAM_3_ECC 0U
+#define XPAR_BRAM_3_FAULT_INJECT 0U
+#define XPAR_BRAM_3_CE_FAILING_REGISTERS 0U
+#define XPAR_BRAM_3_UE_FAILING_REGISTERS 0U
+#define XPAR_BRAM_3_ECC_STATUS_REGISTERS 0U
+#define XPAR_BRAM_3_CE_COUNTER_WIDTH 0U
+#define XPAR_BRAM_3_ECC_ONOFF_REGISTER 0U
+#define XPAR_BRAM_3_ECC_ONOFF_RESET_VALUE 0U
+#define XPAR_BRAM_3_WRITE_ACCESS 0U
+#define XPAR_BRAM_3_BASEADDR 0x40002000U
+#define XPAR_BRAM_3_HIGHADDR 0x40003FFFU
+#define XPAR_BRAM_3_CTRL_BASEADDR 0xFFFFFFFFU  
+#define XPAR_BRAM_3_CTRL_HIGHADDR 0xFFFFFFFEU  
+
 
 /******************************************************************/
 

df_datalink_sp/bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_g.c

@@ -42,6 +42,25 @@
 
 XBram_Config XBram_ConfigTable[] =
 {
+	{
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DEVICE_ID,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DATA_WIDTH,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_FAULT_INJECT,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_CE_FAILING_REGISTERS,
+		0,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_UE_FAILING_REGISTERS,
+		0,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_STATUS_REGISTERS,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_CE_COUNTER_WIDTH,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_REGISTER,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_WRITE_ACCESS,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_BASEADDR,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_HIGHADDR,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
+		XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
+	},
 	{
 		XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID,
 		XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DATA_WIDTH,

df_datalink_sp/bsp/system.mss

@@ -24,6 +24,12 @@ BEGIN DRIVER
  PARAMETER HW_INSTANCE = axi_spi_engine_axi_spi_engine
 END
 
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = phy_data_interface_ant_beam_bram_ctrl
+END
+
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = bram
  PARAMETER DRIVER_VER = 4.3

df_datalink_sp/build/src/subdir.mk

@@ -8,15 +8,18 @@ LD_SRCS += \
 
 C_SRCS += \
 ../src/main.c \
-../src/system_monitor.c 
+../src/system_monitor.c \
+../src/hwconfig.c
 
 OBJS += \
 ./src/main.o \
-./src/system_monitor.o 
+./src/system_monitor.o \
+./src/hwconfig.o
 
 C_DEPS += \
 ./src/main.d \
-./src/system_monitor.d 
+./src/system_monitor.d \
+./src/hwconfig.d
 
 
 # Each subdirectory must supply rules for building sources it contributes

df_datalink_sp/src/config/app_config.h

@@ -58,6 +58,7 @@
 #define PHY_BEAM_FORMING_ENABLE
 // -- Antenna Bram Configs
 #define PHY_ANTCONFIG_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID
+#define PHY_ANTINFO_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DEVICE_ID
 // -- Buffers
 #define PHY_TXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
 #define PHY_RXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID

df_datalink_sp/src/hwconfig.c

@@ -0,0 +1,464 @@
+/*****************************************************************************/
+/**
+ * Description: hwconfig.h
+ *
+
+ * Date: 2024-02-20 13:19
+ * Last Edit Time: [2024-02-20 13:19]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2023-05-07]: Initial edition.
+ *
+ * Copyright(c) 2024 Beijing Institute of Technology.
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+// Standard
+#include <stdint.h>
+#include <stdbool.h>
+// Xilinx
+#include "xgpiops.h"
+#include "drivers/rf-transceiver/ad9361_reg/ad9361_reg.h"
+#include "drivers/rf-transceiver/ad9361/ad9361_api.h"
+#include "drivers/axi_core/spi_engine/spi_engine.h"
+// App
+#include "common.h"
+#include "error.h"
+#include "delay.h"
+#include "system_monitor.h"
+#include "hwconfig.h"
+#include "config/app_config.h"
+#include "dev_profile/dev_profile.h"
+
+/************************** Function Prototypes ******************************/
+/*********************** Driver Instance Definitions **************************/
+static struct hmc7044_dev *hmc7044_inst;
+static struct ad9361_reg_dev *ad9361_1_reg_inst;
+static struct ad9361_reg_dev *ad9361_2_reg_inst;
+// static struct ad9361_rf_phy *ad9361_phy;
+// static struct ad9361_rf_phy *ad9361_2_phy;
+
+/*****************************************************************************/
+/**
+ * @brief   Hardware_Init
+ *
+ * @param   none.
+ *
+ * @return  None.
+ *
+ ******************************************************************************/
+int32_t Hardware_Init(void)
+{
+	int32_t Status;
+	XGpioPs Gpio;
+	XGpioPs_Config *ConfigPtr;
+	ConfigPtr = XGpioPs_LookupConfig(AD9361_GPIO_DEVICE_ID);
+	Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
+	if (Status != SUCCESS)
+	{
+		return FAILURE;
+	}
+
+	/**********************************************************/
+	/****************** HMC7044 Configuration *****************/
+	/**********************************************************/
+	Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("hmc7044_init() error: %" PRId32 "\n", Status);
+		return FAILURE;
+	}
+
+	/**********************************************************/
+	/***************** AD9361-1 Configuration *****************/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, AD9361_GPIO_OUTPUT);
+
+	ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param);
+	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0);
+	ad9361_reg_config(ad9361_1_reg_inst);
+	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1);
+
+	//	Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param);
+	//	if (Status != XST_SUCCESS){
+	//		return XST_FAILURE;
+	//	}else{
+	//		printf("Configurate AD9361 Completely!\n");
+	//	}
+	//	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
+	//	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
+
+	/**********************************************************/
+	/***************** AD9361-2 Configuration *****************/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, AD9361_GPIO_OUTPUT);
+
+	ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param);
+	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0);
+	ad9361_reg_config(ad9361_2_reg_inst);
+	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1);
+
+	//	uint8_t rd_back;
+	//	Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
+	//	Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);
+
+	/**********************************************************/
+	/******* AD9361 Baseband Multichip Synchronization ********/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, AD9361_GPIO_OUTPUT);
+
+	// SYNC BBPLL and DIGITAL SAMPLING CLOCKS
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
+	mdelay(20);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin
+	mdelay(500);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
+	mdelay(2000);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin
+	mdelay(500);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08);
+
+	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
+	mdelay(20);
+	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1);
+	mdelay(20);
+	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
+
+	/**********************************************************/
+	/********* AD9361 Multichip Rx Phase Calibration **********/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, AD9361_GPIO_INPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, AD9361_GPIO_INPUT);
+
+	// switch to lower frequency
+	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
+	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1);
+	mdelay(20);
+
+	// switch rx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30);
+	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30);
+
+	// enable dual ad9361 tx channels
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels
+
+	// switch ad9361 tx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
+	mdelay(20);
+
+	// begin to calibrate the 1st ad9361
+	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
+	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1);
+	mdelay(1);
+	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
+
+	// read calibration status
+	int32_t time_out_cnt = 0;
+	do
+	{
+		mdelay(1); // Wait 1ms
+		time_out_cnt++;
+	} while (((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
+
+	if (time_out_cnt == AD9361_TIMEOUT_TH)
+	{
+		return FAILURE;
+	}
+
+	// begin to calibrate the 2nd ad9361
+	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1);
+	mdelay(1);
+	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0);
+
+	// read calibration status
+	time_out_cnt = 0;
+	do
+	{
+		mdelay(1); // Wait 1ms
+		time_out_cnt++;
+	} while (((XGpioPs_ReadPin(&Gpio, AD9361_2_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
+
+	if (time_out_cnt == AD9361_TIMEOUT_TH)
+	{
+		return FAILURE;
+	}
+
+	// enable single ad9361 tx channels
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
+
+	// switch ad9361 tx & rx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03);
+	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03);
+
+	// switch to higher frequency
+	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
+	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0);
+
+	DBG_PRINT("Done.\n");
+
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Hardware_SwitchFreq
+ *
+ * @param   devSysMonitor_UpdateHardwareStatus(newHwState);
+ * @param   freq
+ *
+ * @return  None.
+ *
+ ******************************************************************************/
+int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
+{
+	int32_t status = 0;
+	uint8_t value = 0;
+	int32_t time_out_cnt = 0;
+
+	switch (freq)
+	{
+	case TX_FREQ_125:
+	{
+		//************************************************************
+		// Setup Tx Frequency-Dependent Syntheisizer Registers
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
+		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
+		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
+		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
+		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
+		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+		status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp)
+		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
+		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
+		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
+
+		//************************************************************
+		// Write Tx Frequency Words
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
+		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
+		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
+		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
+		status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
+
+		//************************************************************
+		// Tx Quadrature Calibration Settings
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
+		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
+		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
+		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
+		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
+		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
+		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
+		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
+
+		break;
+	}
+	case TX_FREQ_126:
+	{
+		//************************************************************
+		// Setup Tx Frequency-Dependent Syntheisizer Registers
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
+		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
+		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
+		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
+		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
+		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
+		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
+		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
+		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
+
+		//************************************************************
+		// Write Tx Frequency Words
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0]
+		status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8]
+		status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16]
+		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
+		status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
+
+		//************************************************************
+		// Tx Quadrature Calibration Settings
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
+		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
+		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
+		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
+		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
+		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
+		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
+		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
+
+		break;
+	}
+	case TX_FREQ_4125:
+	{
+		//************************************************************
+		// Setup Tx Frequency-Dependent Syntheisizer Registers
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
+		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
+		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
+		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
+		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
+		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
+		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
+		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
+		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
+
+		//************************************************************
+		// Write Rx Frequency Words
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
+		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
+		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
+		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
+		status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+		status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting
+
+		//************************************************************
+		// Tx Quadrature Calibration Settings
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
+		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
+		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
+		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
+		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
+		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index
+		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
+		status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
+
+		break;
+	}
+
+		// Wait for cal to complete (Done when 0x016[4]==0)
+		time_out_cnt = 0;
+		do
+		{
+			status |= ad9361_reg_read(dev, 0x0016, &value);
+			mdelay(1); // Wait 1ms
+			time_out_cnt++;
+		} while ((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
+	}
+
+	return status;
+}
+
+// @ Get AD9361 - 1 temperature (Celsius Degree)
+/**
+ * Read corresponding register to get AD9361 - 1 current temperature.
+ */
+int8_t Hardware_GetAD9361Temp_1(void)
+{
+	int8_t scaleTemp;
+
+	ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x01); // disable aux adc
+	ad9361_reg_read(ad9361_1_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x00); // enable aux adc
+
+	return (int8_t) scaleTemp/1.16;
+}
+
+// @ Get AD9361 - 2 temperature (Celsius Degree)
+/**
+ * Read corresponding register to get AD9361 - 2 current temperature.
+ */
+int8_t Hardware_GetAD9361Temp_2(void)
+{
+	int8_t scaleTemp;
+
+	ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x01); // disable aux adc
+	ad9361_reg_read(ad9361_2_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
+	ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x00); // enable aux adc
+
+	return (int8_t) scaleTemp/1.16;
+}
+
+// @ Determine AD9361 lock state
+/**
+ * Read corresponding register to determine AD9361(both) lock state.
+ */
+uint8_t Hardware_GetAD9361LockStatus(void)
+{
+	uint8_t ret = 0;
+	uint8_t regVal;
+
+	// bbpll
+	ad9361_reg_read(ad9361_1_reg_inst, 0x005E, &regVal); // [D7] is lock indicator
+	ret |= ((regVal & 0x80) == 0x80) ? CLK_AD0_BBPLL_LOCK : 0;
+	ad9361_reg_read(ad9361_2_reg_inst, 0x005E, &regVal); // [D7] is lock indicator
+	ret |= ((regVal & 0x80) == 0x80) ? CLK_AD1_BBPLL_LOCK : 0;
+
+	// rfpll
+	ad9361_reg_read(ad9361_1_reg_inst, 0x0287, &regVal); // [D1] is lock indicator
+	ret |= ((regVal & 0x02) == 0x02) ? CLK_AD0_RFPLL_LOCK : 0;
+	ad9361_reg_read(ad9361_2_reg_inst, 0x0287, &regVal); // [D1] is lock indicator
+	ret |= ((regVal & 0x02) == 0x02) ? CLK_AD1_RFPLL_LOCK : 0;
+
+	return ret;
+}
+
+// @ Determine HMC7044 lock state
+/**
+ * Read corresponding register to determine clock lock state.
+ */
+uint8_t Hardware_GetHMC7044LockStatus(void)
+{
+	uint8_t ret = 0;
+	uint8_t regVal;
+
+	// pll1
+	hmc7044_read(hmc7044_inst, 0x007C, &regVal); // [D5] is lock indicator
+	ret |= ((regVal & 0xE0) != 0x00) ? CLK_SP_PLL0_LOCK : 0;
+
+	// pll2
+	hmc7044_read(hmc7044_inst, 0x007D, &regVal); // [D0] is lock indicator
+	ret |= ((regVal & 0x01) == 0x01) ? CLK_SP_PLL1_LOCK : 0;
+
+	return ret;
+}

df_datalink_sp/src/hwconfig.h

@@ -0,0 +1,32 @@
+/*****************************************************************************/
+/**
+ * Description: hwconfig.h
+ *
+
+ * Date: 2024-02-20 13:19
+ * Last Edit Time: [2024-02-20 13:19]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2023-05-07]: Initial edition.
+ *
+ * Copyright(c) 2024 Beijing Institute of Technology.
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+// Standard
+#include <stdint.h>
+#include "config/app_config.h"
+#include "drivers/rf-transceiver/ad9361_reg/ad9361_reg.h"
+#include "drivers/rf-transceiver/ad9361/ad9361_api.h"
+
+/************************** Function Prototypes ******************************/
+int32_t Hardware_Init(void);
+int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq);
+int8_t Hardware_GetAD9361Temp_1(void);
+int8_t Hardware_GetAD9361Temp_2(void);
+uint8_t Hardware_GetAD9361LockStatus(void);
+uint8_t Hardware_GetHMC7044LockStatus(void);
+
+

df_datalink_sp/src/lscript.ld

@@ -26,6 +26,7 @@ MEMORY
    phy_data_interface_rx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
    phy_data_interface_tx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40002000, LENGTH = 0x2000
    phy_data_interface_ant_info_bram_ctrl_Mem0 : ORIGIN = 0x40004000, LENGTH = 0x2000
+   phy_data_interface_ant_beam_bram_ctrl_Mem0 : ORIGIN = 0x42000000, LENGTH = 0x1000
    ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
    ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
    ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000

df_datalink_sp/src/main.c

@@ -20,19 +20,15 @@
 #include <stdint.h>
 #include <stdbool.h>
 // Xilinx
-#include "sleep.h"
-#include "xil_cache.h"
 #include "xscugic.h"
-#include "xscutimer.h"
-#include "xgpiops.h"
 #include "drivers/platform/xilinx_irq.h"
 #include "drivers/platform/xilinx_timer.h"
-#include "drivers/rf-transceiver/ad9361/ad9361_api.h"
-#include "drivers/axi_core/spi_engine/spi_engine.h"
 // App
 #include "common.h"
 #include "error.h"
 #include "timer.h"
+#include "hwconfig.h"
+#include "system_monitor.h"
 #include "config/app_config.h"
 #include "dev_profile/dev_profile.h"
 #include "systembus/systembus.h"
@@ -46,6 +42,7 @@ void PeriodicPull_Handler(void *callBackRef);
 void ScuTimer_IntrHandler(void *context);
 void Systembus_RxIntrHandler(void *context);
 void Systembus_TxIntrHandler(void *context);
+
 /************************** Constant Definitions *****************************/
 struct callback_desc phy_callback_desc = {
 	.callback = Phy_IntrHandler,
@@ -99,9 +96,14 @@ static PHY_CONFIG phyConfig = {
 	.devId = 0,
 	.baseAddr = PHY_BASEADDR,
 	.antBramId = PHY_ANTCONFIG_BRAM_DEVICE_ID,
+	.antInfoBramId = PHY_ANTINFO_BRAM_DEVICE_ID,
 	.txBramId = PHY_TXBUFF_BRAM_DEVICE_ID,
 	.rxBramId = PHY_RXBUFF_BRAM_DEVICE_ID,
-	.hwXadcId = PHY_HW_XADC_DEVICE_ID
+	.hwXadcId = PHY_HW_XADC_DEVICE_ID,
+	.get_clk_state = Hardware_GetHMC7044LockStatus,
+	.get_ad_lock_state = Hardware_GetAD9361LockStatus,
+	.get_ad0_temp = Hardware_GetAD9361Temp_1,
+	.get_ad1_temp = Hardware_GetAD9361Temp_2
 };
 
 TMC_CONFIG tmcConfig = {
@@ -122,11 +124,7 @@ static PHY_INST *phyInstPtr;
 static TMC_INST *tmcInstPtr = NULL;
 L2_INST *linkInstPtr;
 
-static struct hmc7044_dev *hmc7044_inst;
+
-static struct ad9361_reg_dev *ad9361_1_reg_inst;
-static struct ad9361_reg_dev *ad9361_2_reg_inst;
-// static struct ad9361_rf_phy *ad9361_phy;
-// static struct ad9361_rf_phy *ad9361_2_phy;
 /****************************************************************************/
 /**
  * This function is responsible for initializing the SCUGIC instance, looking
@@ -370,355 +368,6 @@ void ScuTimer_IntrHandler(void *context)
 	}
 }
 
-/*****************************************************************************/
-/**
- * @brief   Hardware_SwitchFreq
- *
- * @param   devSysMonitor_UpdateHardwareStatus(newHwState);
- * @param   freq
- *
- * @return  None.
- *
- ******************************************************************************/
-int Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
-{
-	int32_t status = 0;
-	uint8_t value = 0;
-	int32_t time_out_cnt = 0;
-
-	switch (freq)
-	{
-	case TX_FREQ_125:
-	{
-		//************************************************************
-		// Setup Tx Frequency-Dependent Syntheisizer Registers
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
-		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
-		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
-		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
-		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
-		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
-		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
-		status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp)
-		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
-		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
-		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
-
-		//************************************************************
-		// Write Tx Frequency Words
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
-		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
-		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
-		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
-		status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
-		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
-
-		//************************************************************
-		// Tx Quadrature Calibration Settings
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
-		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
-		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
-		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
-		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
-		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
-		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
-		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
-
-		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
-		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
-
-		break;
-	}
-	case TX_FREQ_126:
-	{
-		//************************************************************
-		// Setup Tx Frequency-Dependent Syntheisizer Registers
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
-		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
-		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
-		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
-		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
-		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
-		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
-		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
-		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
-		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
-		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
-
-		//************************************************************
-		// Write Tx Frequency Words
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0]
-		status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8]
-		status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16]
-		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
-		status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
-		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
-
-		//************************************************************
-		// Tx Quadrature Calibration Settings
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
-		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
-		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
-		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
-		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
-		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
-		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
-		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
-
-		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
-		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
-
-		break;
-	}
-	case TX_FREQ_4125:
-	{
-		//************************************************************
-		// Setup Tx Frequency-Dependent Syntheisizer Registers
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
-		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
-		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
-		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
-		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
-		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
-		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
-		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
-		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
-		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
-		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
-
-		//************************************************************
-		// Write Rx Frequency Words
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
-		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
-		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
-		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
-		status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
-		status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting
-
-		//************************************************************
-		// Tx Quadrature Calibration Settings
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
-		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
-		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
-		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
-		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
-		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index
-		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
-		status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used
-
-		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
-		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
-
-		break;
-	}
-
-		// Wait for cal to complete (Done when 0x016[4]==0)
-		time_out_cnt = 0;
-		do
-		{
-			status |= ad9361_reg_read(dev, 0x0016, &value);
-			mdelay(1); // Wait 1ms
-			time_out_cnt++;
-		} while ((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
-	}
-
-	return status;
-}
-
-/*****************************************************************************/
-/**
- * @brief   Hardware_Init
- *
- * @param   none.
- *
- * @return  None.
- *
- ******************************************************************************/
-int Hardware_Init(void)
-{
-	int32_t Status;
-	XGpioPs Gpio;
-	XGpioPs_Config *ConfigPtr;
-	ConfigPtr = XGpioPs_LookupConfig(AD9361_GPIO_DEVICE_ID);
-	Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
-	if (Status != SUCCESS)
-	{
-		return FAILURE;
-	}
-
-	/**********************************************************/
-	/****************** HMC7044 Configuration *****************/
-	/**********************************************************/
-	Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param);
-	if (Status != SUCCESS)
-	{
-		DBG_ERROR("hmc7044_init() error: %" PRId32 "\n", Status);
-		return FAILURE;
-	}
-
-	/**********************************************************/
-	/***************** AD9361-1 Configuration *****************/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, AD9361_GPIO_OUTPUT);
-
-	ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param);
-	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0);
-	ad9361_reg_config(ad9361_1_reg_inst);
-	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1);
-
-	//	Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param);
-	//	if (Status != XST_SUCCESS){
-	//		return XST_FAILURE;
-	//	}else{
-	//		printf("Configurate AD9361 Completely!\n");
-	//	}
-	//	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
-	//	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
-
-	/**********************************************************/
-	/***************** AD9361-2 Configuration *****************/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, AD9361_GPIO_OUTPUT);
-
-	ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param);
-	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0);
-	ad9361_reg_config(ad9361_2_reg_inst);
-	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1);
-
-	//	uint8_t rd_back;
-	//	Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
-	//	Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);
-
-	/**********************************************************/
-	/******* AD9361 Baseband Multichip Synchronization ********/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, AD9361_GPIO_OUTPUT);
-
-	// SYNC BBPLL and DIGITAL SAMPLING CLOCKS
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D);
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
-	mdelay(20);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin
-	mdelay(500);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
-	mdelay(2000);
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin
-	mdelay(500);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08);
-
-	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
-	mdelay(20);
-	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1);
-	mdelay(20);
-	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
-
-	/**********************************************************/
-	/********* AD9361 Multichip Rx Phase Calibration **********/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, AD9361_GPIO_INPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, AD9361_GPIO_INPUT);
-
-	// switch to lower frequency
-	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
-	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1);
-	mdelay(20);
-
-	// switch rx channel
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30);
-	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30);
-
-	// enable dual ad9361 tx channels
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels
-
-	// switch ad9361 tx channel
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
-	mdelay(20);
-
-	// begin to calibrate the 1st ad9361
-	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
-	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1);
-	mdelay(1);
-	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
-
-	// read calibration status
-	int32_t time_out_cnt = 0;
-	do
-	{
-		mdelay(1); // Wait 1ms
-		time_out_cnt++;
-	} while (((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
-
-	if (time_out_cnt == AD9361_TIMEOUT_TH)
-	{
-		return FAILURE;
-	}
-
-	// begin to calibrate the 2nd ad9361
-	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1);
-	mdelay(1);
-	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0);
-
-	// read calibration status
-	time_out_cnt = 0;
-	do
-	{
-		mdelay(1); // Wait 1ms
-		time_out_cnt++;
-	} while (((XGpioPs_ReadPin(&Gpio, AD9361_2_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
-
-	if (time_out_cnt == AD9361_TIMEOUT_TH)
-	{
-		return FAILURE;
-	}
-
-	// enable single ad9361 tx channels
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
-
-	// switch ad9361 tx & rx channel
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03);
-	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03);
-
-	// switch to higher frequency
-	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
-	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0);
-
-	DBG_PRINT("Done.\n");
-
-	return 0;
-}
-
 /*****************************************************************************/
 /**
  * @brief	Main function, initialize all the device needed, initialize

df_datalink_sp/src/networking/link_layer/link_layer.c

@@ -662,6 +662,8 @@ int32_t Linklayer_Init(L2_INST **instPtr, const L2_CONFIG *config)
 	}
 	memset(*instPtr, 0x00, sizeof(L2_INST));
 	memcpy(&((*instPtr)->config), config, sizeof(L2_CONFIG));
+	// Clear log
+	memset(&((*instPtr)->log), 0x00, sizeof((*instPtr)->log));
 
 	// Packet buffer
 	(*instPtr)->sendPktData = calloc(L2_PACK_LEN_MAX / sizeof(uint64_t), sizeof(uint64_t));
@@ -954,6 +956,7 @@ int32_t Linklayer_EventHandler(L2_INST *instPtr, const L2_EVENT *l2Event)
 		L2_Service_Reset(instPtr->serviceFSM);
 		instPtr->cxn2Net = false;
 		UpdateMainSate(instPtr, L2_INIT_STATE);
+		instPtr->log.reconnectCnt++;
 		break;
 	}
 	case L2_EV_LOST_NODE:
@@ -962,6 +965,8 @@ int32_t Linklayer_EventHandler(L2_INST *instPtr, const L2_EVENT *l2Event)
 		L2_Scan_Reset(instPtr->scanFSM);
 		L2_Service_Reset(instPtr->serviceFSM);
 		UpdateMainSate(instPtr, L2_INIT_STATE);
+		// Log reconnect 
+		instPtr->log.reconnectCnt++;
 		break;
 	}
 	case L2_ROUTINE_FINISH:
@@ -1233,13 +1238,12 @@ int32_t Linklayer_Proc(L2_INST *instPtr)
 	instPtr->linkLog.slotNum = (uint8_t)instPtr->slotNum.curr;
 	instPtr->linkLog.nodeType = (instPtr->config.myType == L2_NODE_HEAD) ? 0xAA : 0xCC;
 	instPtr->linkLog.cxnStatus = (instPtr->cxn2Net) ? 0x11 : 0x00;
-	instPtr->linkLog.linkStage = (instPtr->mainState == L2_INIT_STATE) ? 0x00 : 0x11;
+	instPtr->linkLog.linkStage = (instPtr->mainState == L2_INIT_STATE) ? 0x11 : 0x22;
-	// TODO:
+	instPtr->linkLog.recxnCnt = instPtr->log.reconnectCnt;
-	// instPtr->linkLog.recxnCnt =
+	instPtr->linkLog.beamNo = instPtr->log.scanBeamNo;
-	// instPtr->linkLog.beamNo =
+	instPtr->linkLog.beamWidth = instPtr->log.lastBeamWidth;
-	// instPtr->linkLog.beamWidth =
+	instPtr->linkLog.beamAz = antSubnrrwPattern[instPtr->log.scanBeamNo].oaxis;
-	// instPtr->linkLog.beamAz =
+	instPtr->linkLog.beamEl = antSubnrrwPattern[instPtr->log.scanBeamNo].raxis;
-	// instPtr->linkLog.beamEl =
 	instPtr->linkLog.advTxCnt = (uint16_t)instPtr->log.advTxCnt;
 	instPtr->linkLog.advRecvCnt = (uint16_t)instPtr->log.advRecvCnt;
 	instPtr->linkLog.advCorrectCnt = (uint16_t)instPtr->log.advCorrectCnt;
@@ -1249,7 +1253,9 @@ int32_t Linklayer_Proc(L2_INST *instPtr)
 	instPtr->linkLog.svcTxCnt = instPtr->log.svcTxCnt;
 	instPtr->linkLog.svcRecvCnt = instPtr->log.svcRecvCnt;
 	instPtr->linkLog.svcCorrectCnt = instPtr->log.svcCorrectCnt;
-	instPtr->linkLog.timeDev = instPtr->log.timeDev;
+	instPtr->linkLog.timeDev = (instPtr->log.timeDev > INT32_MAX) ?
+								INT32_MAX :
+								((instPtr->log.timeDev < INT32_MIN) ? INT32_MIN : (int32_t) instPtr->log.timeDev);
 	instPtr->linkLog.sendId = instPtr->serviceFSM->txLog.dataId;
 	instPtr->linkLog.recvId = instPtr->serviceFSM->rxLog.dataId;
 

df_datalink_sp/src/networking/link_layer/link_layer.h

@@ -66,6 +66,9 @@ typedef struct
 	uint32_t svcCorrectCnt;
 
 	int64_t timeDev;
+	uint8_t scanBeamNo;
+	uint8_t lastBeamWidth;
+	uint32_t reconnectCnt;
 } L2_LOG;
 
 typedef struct

df_datalink_sp/src/networking/link_layer/scan.c

@@ -405,6 +405,10 @@ int32_t L2_Scan_PktHandler(L2_INST *instPtr, uint8_t *msg)
 		node->nodeInfo.pos.y = (double) nodePos;
 		L2_FrameGetChunk(msg, L2_MSG_ADV_SRC_POSZ, L2_MSG_ADV_SRC_POSZ_LEN, &nodePos);
 		node->nodeInfo.pos.z = (double) nodePos;
+		node->nodeInfo.beamNo = Phy_LastScanBeamNo(instPtr->config.phyInstPtr);
+
+		// log last scan beam number
+		instPtr->log.scanBeamNo = node->nodeInfo.beamNo;
 
 		// Reset node ttl
 		node->ttlCnt = 0;
@@ -591,6 +595,7 @@ int32_t L2_Scan_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
 	ASSERT(instPtr != NULL);
 	L2_TOR_TYPE torState;
 	int32_t Status;
+	const NODE_ENTRY* commNode;
 	DBG_INFO("-------- Scan Routine --------\n");
 
 	if (rtneEntry->slotSeq != 0)
@@ -603,15 +608,24 @@ int32_t L2_Scan_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
 		if (rtneEntry->dst == L2_GetNodeId(instPtr) || rtneEntry->dst == L2_BROADCAST_ID)
 		{
 			torState = L2_TOR_RX;
+			commNode = L2_GetNodeById(instPtr->nodeList, rtneEntry->dst);
 		}
 		else if (rtneEntry->src == L2_GetNodeId(instPtr) || rtneEntry->src == L2_BROADCAST_ID)
 		{
 			torState = L2_TOR_TX;
+			commNode = L2_GetNodeById(instPtr->nodeList, rtneEntry->src);
 		}
 		else
 		{
 			torState = L2_TOR_SUSPEND;
 		}
+
+		Phy_SetBeamWidth(instPtr->config.phyInstPtr, PHY_ANT_BEAM_25);
+		instPtr->log.lastBeamWidth = PHY_ANT_BEAM_25;
+		if (commNode != NULL)
+		{
+			Phy_SetBeamNo(instPtr->config.phyInstPtr, commNode->nodeInfo.beamNo);
+		}
 	}
 	else
 	{
@@ -627,6 +641,8 @@ int32_t L2_Scan_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntry)
 		{
 			torState = L2_TOR_SUSPEND;
 		}
+		Phy_SetBeamWidth(instPtr->config.phyInstPtr, PHY_ANT_BEAM_120);
+		instPtr->log.lastBeamWidth = PHY_ANT_BEAM_120;
 	}
 
 	switch (rtneEntry->slotType)

df_datalink_sp/src/networking/link_layer/service.c

@@ -369,19 +369,34 @@ int32_t L2_Service_Routine(L2_INST *instPtr, const L2_RTNE_TABLE_ENTRY *rtneEntr
 
 	PHY_INST* phyRef = instPtr->config.phyInstPtr;
 	L2_TOR_TYPE torState;
+	const NODE_ENTRY* commNode;
 	if (rtneEntry->src == L2_GetNodeId(instPtr))
 	{
 		torState = L2_TOR_TX;
+		commNode = L2_GetNodeById(instPtr->nodeList, rtneEntry->src);
 	}
 	else if (rtneEntry->dst == L2_GetNodeId(instPtr))
 	{
 		torState = L2_TOR_RX;
+		commNode = L2_GetNodeById(instPtr->nodeList, rtneEntry->src);
 	}
 	else
 	{
 		torState = L2_TOR_SUSPEND;
 	}
 
+	if (L2_GetNodeType(instPtr) != L2_NODE_HEAD && commNode != NULL)
+	{
+		Phy_SetBeamWidth(phyRef, PHY_ANT_BEAM_25);
+		Phy_SetBeamNo(phyRef, commNode->nodeInfo.beamNo);
+		instPtr->log.lastBeamWidth = PHY_ANT_BEAM_25;
+	}
+	else
+	{
+		Phy_SetBeamWidth(phyRef, PHY_ANT_BEAM_120);
+		instPtr->log.lastBeamWidth = PHY_ANT_BEAM_120;
+	}
+
 	switch (rtneEntry->slotType)
 	{
 	case L2_SLOT_SERVICE:

df_datalink_sp/src/networking/phy_layer/phy_antenna.c

@@ -86,17 +86,21 @@ uint16_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS] =
 
 uint16_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS] = 
 {
-	1500
+	1500, 1600, 1700, 1800, 1900, 1400, 1300, 1200, 
+	1100, 1000, 900
 };
 
 uint16_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS] = 
 {
-	1600
+	1600, 1650, 1700, 1750, 1800, 1850, 1900, 1550, 
+	1500
 };
 
 uint16_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS] = 
 {
-	1600
+	1600, 1650, 1700, 1750, 1800, 1850, 1900, 1550, 
+	1500, 1450, 1400, 1350, 1300, 1250, 1200, 1150, 
+	1100, 1050, 1000
 };
 
 uint16_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS] =
@@ -118,7 +122,7 @@ uint16_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS] =
 #ifdef PHY_BEAM_SET_PRESET
 PHY_ANT_ANGLE antSubnrrwPattern[L1_NUM_ANT_SUBNRRW_PATTERN] = 
 {
-	{.oaxis = 0 , .raxis = 222}, {.oaxis = 10, .raxis = 85 },
+	{.oaxis = 0 , .raxis = 0  }, {.oaxis = 10, .raxis = 85 },
 	{.oaxis = 14, .raxis = 307}, {.oaxis = 17, .raxis = 170},
 	{.oaxis = 19, .raxis = 32 }, {.oaxis = 21, .raxis = 255},
 	{.oaxis = 24, .raxis = 117}, {.oaxis = 25, .raxis = 340},
@@ -140,7 +144,7 @@ PHY_ANT_ANGLE antSubnrrwPattern[L1_NUM_ANT_SUBNRRW_PATTERN] =
 };
 PHY_ANT_ANGLE antNrrwPattern[L1_NUM_ANT_NRRW_PATTERN] = 
 {
-	{.oaxis = 0 , .raxis = 222}, {.oaxis = 7 , .raxis = 85 },
+	{.oaxis = 0 , .raxis = 0  }, {.oaxis = 7 , .raxis = 85 },
 	{.oaxis = 10, .raxis = 307}, {.oaxis = 13, .raxis = 170},
 	{.oaxis = 15, .raxis = 32 }, {.oaxis = 17, .raxis = 255},
 	{.oaxis = 18, .raxis = 117}, {.oaxis = 20, .raxis = 340},
@@ -276,10 +280,10 @@ int32_t Phy_SetBeamNo(PHY_INST *instPtr, int32_t beamNo)
 		else
 		{
 			instPtr->beamNo.next = beamNo;
-			instPtr->antConfig.oaxis[1] = (uint8_t)(antNrrwPattern[beamNo].oaxis);
+			instPtr->antConfig.oaxis[1] = (uint8_t)(antNrrwPattern[beamNo].oaxis >> 8);
-			instPtr->antConfig.oaxis[0] = (uint8_t)((antNrrwPattern[beamNo].oaxis) >> 8);
+			instPtr->antConfig.oaxis[0] = (uint8_t)(antNrrwPattern[beamNo].oaxis);
-			instPtr->antConfig.raxis[1] = (uint8_t)(antNrrwPattern[beamNo].raxis);
+			instPtr->antConfig.raxis[1] = (uint8_t)(antNrrwPattern[beamNo].raxis >> 8);
-			instPtr->antConfig.raxis[0] = (uint8_t)((antNrrwPattern[beamNo].raxis) >> 8);
+			instPtr->antConfig.raxis[0] = (uint8_t)(antNrrwPattern[beamNo].raxis);
 			return SUCCESS;
 		}
 	}
@@ -292,10 +296,10 @@ int32_t Phy_SetBeamNo(PHY_INST *instPtr, int32_t beamNo)
 		else
 		{
 			instPtr->beamNo.next = beamNo;
-			instPtr->antConfig.oaxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].oaxis);
+			instPtr->antConfig.oaxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].oaxis >> 8);
-			instPtr->antConfig.oaxis[0] = (uint8_t)((antSubnrrwPattern[beamNo].oaxis) >> 8);
+			instPtr->antConfig.oaxis[0] = (uint8_t)(antSubnrrwPattern[beamNo].oaxis);
-			instPtr->antConfig.raxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].raxis);
+			instPtr->antConfig.raxis[1] = (uint8_t)(antSubnrrwPattern[beamNo].raxis >> 8);
-			instPtr->antConfig.raxis[0] = (uint8_t)((antSubnrrwPattern[beamNo].raxis) >> 8);
+			instPtr->antConfig.raxis[0] = (uint8_t)(antSubnrrwPattern[beamNo].raxis);
 			return SUCCESS;
 		}
 	}
@@ -334,7 +338,6 @@ int32_t Phy_SetBeamWidth(PHY_INST *instPtr, PHY_ANT_BEAM_WIDTH beamWidth)
 	default:
 		DBG_ERROR("Beam width code: 0x%08X is illegal.\n\r", beamWidth);
 		return EPARAM;
-		break;
 	}
 	instPtr->antConfig.antMode = beamConfig;
 	instPtr->beamWd.next = beamWidth;

df_datalink_sp/src/networking/phy_layer/phy_layer.c

@@ -26,6 +26,7 @@
 #include <stdlib.h>
 #include <math.h>
 #include "phy_layer.h"
+#include "phy_reg.h"
 #include "util.h"
 #include "error.h"
 #ifndef EMULATION
@@ -311,26 +312,28 @@ void Phy_UpdateState(PHY_INST *instPtr)
 	instPtr->recvSlotTime.frac_part = PhyRead(instPtr, TM_TARGET_L);
 	instPtr->recvFsTime.int_part = PhyRead(instPtr, FSTIME_H);
 	instPtr->recvFsTime.frac_part = PhyRead(instPtr, FSTIME_L);
-
 	instPtr->phyLog.acqCnt = PhyRead(instPtr, PHY_ACQ_CNT);
 	instPtr->phyLog.fsyncCnt = PhyRead(instPtr, PHY_FRAME_SYNC_CNT);
 	instPtr->phyLog.decodeCnt = PhyRead(instPtr, PHY_DECODE_CNT);
 	instPtr->phyLog.crcCnt = PhyRead(instPtr, PHY_CRC_OK_CNT);
 	instPtr->phyLog.doppler = Phy_GetFreqEst(instPtr);
 	instPtr->phyLog.recvStamp = (uint64_t)instPtr->recvFsTime.int_part * TIME_FRAC_MAX + instPtr->recvFsTime.frac_part;
-	instPtr->phyLog.acqPeak = PhyRead(instPtr, PHY_ACQ_PEAK_L);
+	uint64_t peak, avg;
-	instPtr->phyLog.acqPeak |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_PEAK_H)) << 32;
+	peak = PhyRead(instPtr, PHY_ACQ_PEAK_L);
-	instPtr->phyLog.acqMean = PhyRead(instPtr, PHY_ACQ_MEAN_L);
+	peak |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_PEAK_H)) << 32;
-	instPtr->phyLog.acqMean |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_MEAN_H)) << 32;
+	avg = PhyRead(instPtr, PHY_ACQ_MEAN_L);
+	avg |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_MEAN_H)) << 32;
+	instPtr->phyLog.acqPAPR = ((double)peak) / ((double)avg);
 	instPtr->phyLog.acqPhase = (PhyRead(instPtr, PHY_ACQ_FREQEST) & PHY_ACQ_FREQEST_PHASE_MASK) >> PHY_ACQ_FREQEST_PHASE_SHIFT;
 	instPtr->phyLog.acqFreqCh = (PhyRead(instPtr, PHY_ACQ_FREQEST) & PHY_ACQ_FREQEST_CHANNEL_MASK) >> PHY_ACQ_FREQEST_CHANNEL_SHIFT;
-	instPtr->phyLog.fsyncPeak = PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_L);
+	peak = PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_L);
-	instPtr->phyLog.fsyncPeak |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_H)) << 32;
+	peak |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_H)) << 32;
-	instPtr->phyLog.fsyncMean = PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_L);
+	avg = PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_L);
-	instPtr->phyLog.fsyncMean |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_H)) << 32;
+	avg |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_H)) << 32;
+	instPtr->phyLog.fsyncPAPR = ((double)peak) / ((double)avg);
 	instPtr->phyLog.fsyncFreqCh = (PhyRead(instPtr, PHY_FRAME_SYNC_FREQEST) & PHY_FRAME_SYNC_FREQEST_CHANNEL_MASK) >> PHY_FRAME_SYNC_FREQEST_CHANNEL_SHIFT;
 	instPtr->phyLog.deintlvAmpEst = PhyRead(instPtr, PHY_DEINTLV_AMPEST) & PHY_DEINTLV_AMPEST_MASK;
-	instPtr->phyLog.reserve = 0;
+	memset(instPtr->phyLog.reserve, 0x00, sizeof(instPtr->phyLog.reserve));
 
 	SysMonitor_UpdatePhysicalLayerLog(&(instPtr->phyLog));
 }
@@ -454,6 +457,40 @@ int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
 	(*instPtr)->recvDataAddr = rxDataBram.Config.MemBaseAddress;
 	(*instPtr)->sendDataAddr = txDataBram.Config.MemBaseAddress;
 
+	// Setup antenna presets
+	XBram antInfoBram;
+	if (phyConfig->antInfoBramId != -1)
+	{
+		bramConfigPtr = XBram_LookupConfig(phyConfig->antInfoBramId);
+		if (bramConfigPtr == NULL)
+		{
+			Status = EDCONF;
+			goto init_error;
+		}
+		Status = XBram_CfgInitialize(&antInfoBram, bramConfigPtr,
+									bramConfigPtr->CtrlBaseAddress);
+		if (Status != SUCCESS)
+		{
+			goto init_error;
+		}
+		/*
+		* Execute the BRAM driver selftest.
+		*/
+		Status = XBram_SelfTest(&antConfigBram, 0);
+		if (Status != SUCCESS)
+		{
+			goto init_error;
+		}
+
+		memcpy((void*)antConfigBram.Config.MemBaseAddress,
+				antSubnrrwPattern, sizeof(antSubnrrwPattern));
+		uint32_t phyMainCtrl = PhyRead(*instPtr, PHY_MAIN_CTRL);
+		phyMainCtrl &= ~PHY_MAIN_CTRL_NSCAN_MASK;
+		phyMainCtrl |= PHY_MAIN_CTRL_NSCAN_MASK &
+						(L1_NUM_ANT_SUBNRRW_PATTERN << PHY_MAIN_CTRL_NSCAN_SHIFT);
+		PhyWrite(*instPtr, PHY_MAIN_CTRL, phyMainCtrl);
+	}
+
 	/* Initialize the XAdc driver. */
 	XAdcPs_Config *xadcConfigPtr;
 
@@ -662,8 +699,8 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
 		break;
 	case L1_10KBPS_10MS_FRAME:
 		phyModeCtrl |= PHY_MODE_CTRL_FRAME_10KBPS_10MS;
-		hopNum = L1_FRAME_10KBPS_10MS_HOPS;
+		hopNum = L1_FRAME_10KBPS_20MS_HOPS;
-		hopPattern = hopPattern_10KBPS_10MS;
+		hopPattern = hopPattern_10KBPS_20MS;
 		break;
 	case L1_10KBPS_20MS_FRAME:
 		phyModeCtrl |= PHY_MODE_CTRL_FRAME_10KBPS_20MS;
@@ -819,6 +856,21 @@ uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType)
 	}
 }
 
+/*****************************************************************************/
+/**
+ * @brief   Get the last scan beam number after autoscan.
+ *
+ * @param   instPtr  a pointer to physical instance
+ *
+ * @return  beam number
+ *
+ ******************************************************************************/
+uint8_t Phy_LastScanBeamNo(PHY_INST *instPtr)
+{
+	ASSERT(instPtr != NULL);
+	return (uint8_t)PhyRead(instPtr, BEAM_SELECT_INDEX);
+}
+
 /*****************************************************************************/
 /**
  * @brief   Get frequency estimation of last valid frame.
@@ -1143,58 +1195,88 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
 #ifndef EMULATION
 	float evalData;
 	instPtr->hwSate.isSpOk = true;
-	// -- Update Ps voltage, unit mV
+	// -- Update FPGA voltage status;
+	instPtr->hwSate.spFpgaVolt = 0;
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPINT);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spPsVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
+	instPtr->hwSate.spFpgaVolt |= (IS_PS_VALID(evalData)) ? VOLT_PS_OK : 0;
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PS_VALID(evalData);
 
-	// -- Update Ps aux voltage, unit mV
+	// -- -- Update Ps aux voltage
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPAUX);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spPsAuxVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
+	instPtr->hwSate.spFpgaVolt |= (IS_PSAUX_VALID(evalData)) ? VOLT_PSAUX_OK : 0;
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PSAUX_VALID(evalData);
 
-	// -- Update DDR voltage, unit mV
+	// -- -- Update DDR voltage
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPDRO);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spDdrVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
+	instPtr->hwSate.spFpgaVolt |= (IS_DDR_VALID(evalData)) ? VOLT_DDR_OK : 0;
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_DDR_VALID(evalData);
 
-	// -- Update PL voltage, unit mV
+	// -- -- Update PL voltage
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCINT);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spPlVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
+	instPtr->hwSate.spFpgaVolt |= (IS_PL_VALID(evalData)) ? VOLT_PL_OK : 0;
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PL_VALID(evalData);
 
-	// -- Update PL aux voltage, unit mV
+	// -- -- Update PL aux voltage
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCAUX);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spPlAuxVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
+	instPtr->hwSate.spFpgaVolt |= (IS_PLAUX_VALID(evalData)) ? VOLT_PLAUX_OK : 0;
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PLAUX_VALID(evalData);
 
-	// -- Update Bram voltage, unit mV
+	// -- -- Update Bram voltage
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VBRAM);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spBramVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
+	instPtr->hwSate.spFpgaVolt |= (IS_BRAM_VALID(evalData)) ? VOLT_BRAM_OK : 0;
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_BRAM_VALID(evalData);
 
-	// -- Update Chip temperature, unit 0.01 deg
+	// -- Update clock lock state
+	if (instPtr->phyCofig.get_clk_state != NULL)
+	{
+		instPtr->hwSate.spClkState = instPtr->phyCofig.get_clk_state();
+	}
+	else
+	{
+		instPtr->hwSate.spClkState = 0;
+	}
+
+	// -- Update AD9361 pll lock state
+	if (instPtr->phyCofig.get_ad_lock_state != NULL)
+	{
+		instPtr->hwSate.spAdLockState = instPtr->phyCofig.get_ad_lock_state();
+	}
+	else
+	{
+		instPtr->hwSate.spAdLockState = 0;
+	}
+
+	// -- Update AD9361-0 temperature, unit 1 Celcius degree
+	if (instPtr->phyCofig.get_ad0_temp != NULL)
+	{
+		instPtr->hwSate.spAdTemp_0 = instPtr->phyCofig.get_ad0_temp();
+	}
+	else
+	{
+		instPtr->hwSate.spAdTemp_0 = 0;
+	}
+
+	// -- Update AD9361-1 temperature, unit 1 Celcius degree
+	if (instPtr->phyCofig.get_ad1_temp != NULL)
+	{
+		instPtr->hwSate.spAdTemp_1 = instPtr->phyCofig.get_ad1_temp();
+	}
+	else
+	{
+		instPtr->hwSate.spAdTemp_1 = 0;
+	}
+
+	// -- Update FPGA Chip temperature, unit 1 deg
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_TEMP);
 	evalData = XAdcPs_RawToTemperature(rawData);
-	instPtr->hwSate.spTemp = (evalData > TEMPERATURE_MAX) 
+	instPtr->hwSate.spFpgaTemp = (evalData > TEMPERATURE_MAX)
 								? INT8_MAX
 								: ((evalData < TEMPERATURE_MIN) ? INT8_MIN : (int8_t) round(evalData/TEMPERATURE_LSB));
-
+	instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK | VOLT_PSAUX_OK | VOLT_DDR_OK | VOLT_PL_OK | VOLT_PLAUX_OK | VOLT_BRAM_OK))
+						&& (instPtr->hwSate.spClkState == (CLK_SP_PLL0_LOCK | CLK_SP_PLL1_LOCK))
+						&& (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK | CLK_AD0_RFPLL_LOCK | CLK_AD1_BBPLL_LOCK | CLK_AD1_RFPLL_LOCK));
 #else
-	instPtr->spPsVolt = 0;
+	instPtr->hwSate.isSpOk = true;
-	instPtr->spPsAuxVolt = 0;
-	instPtr->spDdrVolt = 0;
-	instPtr->spPlVolt = 0;
-	instPtr->spPlAuxVolt = 0;
-	instPtr->spBramVolt = 0;
-	instPtr->spTemp = 0;
-	instPtr->isSpOk = true;
 #endif
 	/*** Voltage and Status ***/
 	rawData = PhyRead(instPtr, ANT_STATUS);
@@ -1203,10 +1285,10 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
 	//    [2] - RF voltage status
 	//    [4] - NIL voltage status
 	//    [6] - Antenna status
-	instPtr->hwSate.antVolt = ((rawData & ANT_STATUS_ANT_VOLT_MASK) == ANT_STATUS_ANT_VOLT_OK) ? 0x01 : 0x00;
+	instPtr->hwSate.antVolt = ((rawData & ANT_STATUS_ANT_VOLT_MASK) == ANT_STATUS_ANT_VOLT_OK) ? VOLT_ANT_PROC_OK : 0x00;
-	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_RF_VOLT_MASK) == ANT_STATUS_RF_VOLT_OK) ? 0x04 : 0x00;
+	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_RF_VOLT_MASK) == ANT_STATUS_RF_VOLT_OK) ? VOLT_ANT_RF_OK : 0x00;
-	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_NIL_VOLT_MASK) == ANT_STATUS_NIL_VOLT_OK) ? 0x10 : 0x00;
+	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_NIL_VOLT_MASK) == ANT_STATUS_NIL_VOLT_OK) ? VOLT_ANT_NIL_OK : 0x00;
-	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_CODE_MASK) == ANT_STATUS_CODE_OK) ? 0x40 : 0x00;
+	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_CODE_MASK) == ANT_STATUS_CODE_OK) ? ANT_STATE_OK : 0x00;
 
 	/*** Temperature and Lock Status ***/
 	rawData = PhyRead(instPtr, ANT_RF_STATUS);
@@ -1216,9 +1298,9 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
 	//    [0] - BASEBAND lock status
 	//    [2] - PLLA lock status
 	//    [4] - PLLB lock status
-	instPtr->hwSate.antPll = ((rawData & ANT_RF_STATUS_BBLOCK_MASK) == ANT_RF_STATUS_BBLOCK_OK) ? 0x01 : 0x00;
+	instPtr->hwSate.antPll = ((rawData & ANT_RF_STATUS_BBLOCK_MASK) == ANT_RF_STATUS_BBLOCK_OK) ? CLK_ANT_BBPLL_LOCK : 0x00;
-	instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLA_MASK) == ANT_RF_STATUS_PLLA_OK) ? 0x04 : 0x00;
+	instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLA_MASK) == ANT_RF_STATUS_PLLA_OK) ? CLK_ANT_RFPLL0_LOCK : 0x00;
-	instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLB_MASK) == ANT_RF_STATUS_PLLB_OK) ? 0x10 : 0x00;
+	instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLB_MASK) == ANT_RF_STATUS_PLLB_OK) ? CLK_ANT_RFPLL1_LOCK : 0x00;
 
 	/*** MGCs ***/
 	rawData = PhyRead(instPtr, ANT_RF_MGC);
@@ -1233,14 +1315,10 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
 	instPtr->hwSate.antMgc1 |= (rawData & ANT_RF_MGC_CH4_MASK) >> 24;
 
 	// Determin if antenna is ok.
-	if(instPtr->hwSate.antVolt != 0x55 //01010101
+	instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK | VOLT_ANT_RF_OK | VOLT_ANT_NIL_OK | ANT_STATE_OK))
-		||instPtr->hwSate.antPll != 0x15) // 00010101
+								&& (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK | CLK_ANT_RFPLL0_LOCK | CLK_ANT_RFPLL1_LOCK));
-	{
+
-		instPtr->hwSate.isSpOk = false;
+	memset(instPtr->hwSate.reserve, 0x00, sizeof(instPtr->hwSate.reserve));
-	}
+
-	else 
-	{
-		instPtr->hwSate.isSpOk = true;
-	}
 	SysMonitor_UpdateHardwareStatus(&(instPtr->hwSate));
 }

df_datalink_sp/src/networking/phy_layer/phy_layer.h

@@ -26,7 +26,6 @@
 
 /***************************** Include Files *********************************/
 #include <stdint.h>
-#include "phy_reg.h"
 #include "common.h"
 #ifndef EMULATION
 #include "xbram.h"
@@ -181,8 +180,15 @@ typedef struct
 	uint32_t txBramId;
 	uint32_t rxBramId;
 	uint32_t antBramId;
+	uint32_t antInfoBramId;
 	uint32_t hwXadcId;
 	uintptr_t baseAddr;
+#ifndef EMULATION
+	uint8_t (*get_clk_state)(void);
+	uint8_t (*get_ad_lock_state)(void);
+	int8_t (*get_ad0_temp)(void);
+	int8_t (*get_ad1_temp)(void);
+#endif
 } PHY_CONFIG;
 
 typedef struct
@@ -270,6 +276,7 @@ int32_t Phy_SetBeamNo(PHY_INST *instPtr, int32_t beamNo);
 int32_t Phy_SetBeamAngle(PHY_INST *phyInstPtr, double offAx, double rndAx);
 int32_t Phy_SetTimeWord(PHY_INST *instPtr, const TIME_WORD *tmWord, PHY_TIME_WORD_TYPE tmType);
 
+uint8_t Phy_LastScanBeamNo(PHY_INST *instPtr);
 double Phy_GetFreqEst(PHY_INST *instPtr);
 double Phy_GetCoarseFreqEst(PHY_INST *instPtr);
 double Phy_GetFineFreqEst(PHY_INST *instPtr);

df_datalink_sp/src/networking/phy_layer/phy_reg.h

@@ -26,8 +26,8 @@
 #include "util.h"
 
 /***************** Macros (Inline Functions) Definitions *********************/
-#define PhyRead(instPtr, addr) IO_In32(instPtr->phyCofig.baseAddr + addr)
+#define PhyRead(instPtr, addr) IO_In32((instPtr)->phyCofig.baseAddr + addr)
-#define PhyWrite(instPtr, addr, value) IO_Out32(instPtr->phyCofig.baseAddr + addr, value)
+#define PhyWrite(instPtr, addr, value) IO_Out32((instPtr)->phyCofig.baseAddr + addr, value)
 
 /************************** Constant Definitions *****************************/
 /**
@@ -40,6 +40,9 @@
 #define PHY_MAIN_CTRL_MODE_SHIFT 8
 #define PHY_MAIN_CTRL_MODE_WIDTH 8
 #define PHY_MAIN_CTRL_MODE_MASK 0x0000FF00U
+#define PHY_MAIN_CTRL_NSCAN_SHIFT 16
+#define PHY_MAIN_CTRL_NSCAN_WIDTH 8
+#define PHY_MAIN_CTRL_NSCAN_MASK 0x00FF0000U
 
 #define PHY_MAIN_CTRL_EN_EN 0x00000001U
 #define PHY_MAIN_CTRL_EN_DSBL 0x00000000U

df_datalink_sp/src/system_monitor.c

@@ -289,16 +289,3 @@ void SysMonitor_GetHardwareStatus(HWSTATE *state)
 	memcpy(state, &(sysMonitorInst->hwState[buffIndx]), sizeof(HWSTATE));
 	sysMonitorInst->hwStateCtrl.rBusy = buffIndex_old;
 }
-
-
-// @System log
-/**
- * Get the latest system running log.
- */
-void SysMonitor_GetSyslog(SYSLOG *log)
-{
-	ASSERT(sysMonitorInst != NULL);
-	SysMonitor_GetLinklayerLog(&(log->linkLog));
-	SysMonitor_GetPhysicalLayerLog(&(log->phyLog));
-	SysMonitor_GetHardwareStatus(&(log->hwState));
-}

df_datalink_sp/src/system_monitor.h

@@ -3,6 +3,7 @@
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "util.h"
 
 #define PAYLOAD_LEN_MAX 256
 #define PAYLOAD_LEN_FLJ_RX 168
@@ -23,12 +24,36 @@
 #define VOLT_PLAUX_STD 1.8
 #define VOLT_BRAM_STD 1.0
 
-#define IS_PS_VALID(x) (x <= 0.95 && x >= 1.05)
+#define VOLT_PS_OK BIT(0)
+#define VOLT_PSAUX_OK BIT(1)
+#define VOLT_DDR_OK BIT(2)
+#define VOLT_PL_OK BIT(3)
+#define VOLT_PLAUX_OK BIT(4)
+#define VOLT_BRAM_OK BIT(5)
+
+#define VOLT_ANT_PROC_OK BIT(0)
+#define VOLT_ANT_RF_OK BIT(2)
+#define VOLT_ANT_NIL_OK BIT(4)
+#define ANT_STATE_OK BIT(6)
+
+#define IS_PS_VALID(x) (x <= 1.05 && x >= 0.95)
 #define IS_PSAUX_VALID(x) (x <= 1.89 && x >= 1.71)
-#define IS_DDR_VALID(x) (x <= 1.14 && x >= 1.89)
+#define IS_DDR_VALID(x) (x <= 1.89 && x >= 1.14)
-#define IS_PL_VALID(x) (x <= 0.97 && x >= 1.03)
+#define IS_PL_VALID(x) (x <= 1.03 && x >= 0.97)
 #define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71)
-#define IS_BRAM_VALID(x) (x <= 0.97 && x >= 1.03)
+#define IS_BRAM_VALID(x) (x <= 1.03 && x >= 0.97)
+
+#define CLK_SP_PLL0_LOCK BIT(0)
+#define CLK_SP_PLL1_LOCK BIT(2)
+
+#define CLK_AD0_BBPLL_LOCK BIT(0)
+#define CLK_AD0_RFPLL_LOCK BIT(2)
+#define CLK_AD1_BBPLL_LOCK BIT(4)
+#define CLK_AD1_RFPLL_LOCK BIT(6)
+
+#define CLK_ANT_BBPLL_LOCK BIT(0)
+#define CLK_ANT_RFPLL0_LOCK BIT(2)
+#define CLK_ANT_RFPLL1_LOCK BIT(4)
 
 #define TEMPERATURE_LSB 1.0	   // Celsius degree
 #define TEMPERATURE_MAX 127.0  // Celsius degree
@@ -73,6 +98,18 @@ typedef struct __attribute__((packed))
 	float roll;
 } SYSINFO;
 
+typedef struct __attribute__((packed))
+{
+	// SystemBus log
+	// -- last valid config
+	//    byte 0: 0x11 FLJ, 0x00 LJ
+	//    byte 1: 0x66 Full Power, 0x88 Low Power
+	uint8_t lastConfig[2];
+	uint32_t pollCnt;
+	uint32_t svcCnt;
+	uint32_t remoteCnt;
+} SYSBUSLOG;
+
 typedef struct __attribute__((packed))
 {
 	// Network log
@@ -95,9 +132,10 @@ typedef struct __attribute__((packed))
 	uint32_t svcTxCnt;
 	uint32_t svcRecvCnt;
 	uint32_t svcCorrectCnt;
-	int64_t	timeDev;
+	int32_t timeDev;
 	uint32_t sendId;
 	uint32_t recvId;
+	uint8_t reserve[4];
 } LINKLOG;
 
 typedef struct __attribute__((packed))
@@ -108,15 +146,13 @@ typedef struct __attribute__((packed))
 	uint32_t crcCnt;
 	double doppler;
 	uint64_t recvStamp;
-	uint64_t acqPeak;
+	double acqPAPR;
-	uint64_t acqMean;
 	uint8_t acqPhase;
 	uint8_t acqFreqCh;
-	uint64_t fsyncPeak;
+	double fsyncPAPR;
-	uint64_t fsyncMean;
 	uint8_t fsyncFreqCh;
 	uint16_t deintlvAmpEst;
-	uint16_t reserve;
+	uint8_t reserve[4];
 } PHYLOG;
 
 typedef struct __attribute__((packed))
@@ -125,34 +161,21 @@ typedef struct __attribute__((packed))
 	bool isSpOk;
 	bool isAntOk;
 	// -- Signal processor status
-	uint8_t spPsVolt;
+	uint8_t spFpgaVolt;
-	uint8_t spPsAuxVolt;
+	uint8_t spClkState;
-	uint8_t spDdrVolt;
+	uint8_t spAdLockState;
-	uint8_t spPlVolt;
+	uint8_t spAdTemp_0;
-	uint8_t spPlAuxVolt;
+	uint8_t spAdTemp_1;
-	uint8_t spBramVolt;
+	uint8_t spFpgaTemp;
-	int8_t spTemp;
 	// -- Antenna status
 	uint8_t antVolt;
 	uint8_t antTemp;
 	uint8_t antPll;
 	uint8_t antMgc0;
 	uint8_t antMgc1;
-	uint8_t dummy;
+	uint8_t reserve[2];
 } HWSTATE;
 
-typedef struct
-{
-	// Link layer log
-	LINKLOG linkLog;
-
-	// Physical layer log
-	PHYLOG phyLog;
-
-	// Hardware status
-	HWSTATE hwState;
-} SYSLOG;
-
 typedef struct
 {
 	uint32_t dataId;
@@ -177,6 +200,4 @@ void SysMonitor_GetLinklayerLog(LINKLOG *log);
 void SysMonitor_GetPhysicalLayerLog(PHYLOG *log);
 void SysMonitor_GetHardwareStatus(HWSTATE *state);
 
-void SysMonitor_GetSyslog(SYSLOG *log);
-
 #endif //__SYSTEM_MONITOR_H_

df_datalink_sp/src/systembus/systembus.c

@@ -53,31 +53,30 @@
 #define ST_RET_ERROR 0x55
 #define ST_RET_INFO_LEN 13
 // -- -- Signal processor PS voltage
-#define WD_SP_PS_VOLT 0x03
+#define WD_SP_FPGA_VOLT 0x03
 // -- -- Signal processor PS AUX voltage
-#define WD_SP_PSAUX_VOLT 0x04
+#define WD_SP_CLK_STATE 0x04
 // -- -- Signal processor DDR voltage
-#define WD_SP_DDR_VOLT 0x05
+#define WD_SP_AD_LOCK_STATE 0x05
 // -- -- Signal processor PL voltage
-#define WD_SP_PL_VOLT 0x06
+#define WD_SP_AD_TEMP_0 0x06
 // -- -- Signal processor PL AUX voltage
-#define WD_SP_PLAUX_VOLT 0x07
+#define WD_SP_AD_TEMP_1 0x07
 // -- -- Signal processor Bram voltage
-#define WD_SP_BRAM_VOLT 0x08
+#define WD_SP_FPGA_TEMP 0x08
-// -- -- Signal processor temperature
-#define WD_SP_TEMP 0x09
 
 // -- -- Signal processor antenna voltage status
-#define WD_ANT_VOLT 0x0A
+#define WD_ANT_VOLT 0x09
+
 // -- -- Signal processor antenna RF temperature
-#define WD_ANT_RF_TEMP 0x0B
+#define WD_ANT_RF_TEMP 0x0A
 // -- -- Signal processor antenna PLL lock status
-#define WD_ANT_RF_PLL 0x0C
+#define WD_ANT_RF_PLL 0x0B
 // -- -- Signal processor antenna MGC
-#define WD_ANT_MGC_0 0x0D
+#define WD_ANT_MGC_0 0x0C
-#define WD_ANT_MGC_1 0x0E
+#define WD_ANT_MGC_1 0x0D
-// -- -- Dummy must be 0x00
+// -- -- Reserved
-#define WD_ST_DUMMY 0x0F
+#define WD_ANT_RESERVE 0x0E
 
 // Data Send Test Command
 #define CMD_DATA_TEST_A 0xE2
@@ -160,10 +159,12 @@
 // -- Response
 #define WD_FLJ_TIME_STAMP 0x02
 #define WD_FLJ_TIME_STAMP_LEN 8
-#define WD_FLJ_LINK_LOG 0x0A
+#define WD_FLJ_SYSBUS_LOG 0x0A
+#define WD_FLJ_SYSBUS_LOG_LEN 14
+#define WD_FLJ_LINK_LOG 0x18
 #define WD_FLJ_LINK_LOG_LEN 64
-#define WD_FLJ_PHY_LOG 0x4A
+#define WD_FLJ_PHY_LOG 0x58
-#define WD_FLJ_PHY_LOG_LEN 71
+#define WD_FLJ_PHY_LOG_LEN 57
 #define WD_FLJ_HARDWARE_ST 0x91
 #define WD_FLJ_HARDWARE_ST_LEN 13
 
@@ -177,10 +178,12 @@
 // -- Response
 #define WD_LJ_TIME_STAMP 0x02
 #define WD_LJ_TIME_STAMP_LEN 8
-#define WD_LJ_LINK_LOG 0x0A
+#define WD_LJ_SYSBUS_LOG 0x0A
+#define WD_LJ_SYSBUS_LOG_LEN 14
+#define WD_LJ_LINK_LOG 0x18
 #define WD_LJ_LINK_LOG_LEN 64
-#define WD_LJ_PHY_LOG 0x4A
+#define WD_LJ_PHY_LOG 0x58
-#define WD_LJ_PHY_LOG_LEN 71
+#define WD_LJ_PHY_LOG_LEN 57
 #define WD_LJ_HARDWARE_ST 0x91
 #define WD_LJ_HARDWARE_ST_LEN 13
 
@@ -247,7 +250,10 @@ int32_t SystemBus_Init(SYSBUS **instPtr, SYSBUS_CONFIG *config)
 	(*instPtr)->txQueue = NULL;
 	(*instPtr)->uartInst = NULL;
 	memcpy(&((*instPtr)->config), config, sizeof(SYSBUS_CONFIG));
-	memset(&((*instPtr)->sysLog), 0x00, sizeof(SYSLOG));
+	memset(&((*instPtr)->sysbusLog), 0x00, sizeof(SYSBUSLOG));
+	memset(&((*instPtr)->linkLog), 0x00, sizeof(LINKLOG));
+	memset(&((*instPtr)->phyLog), 0x00, sizeof(PHYLOG));
+	memset(&((*instPtr)->hwState), 0x00, sizeof(HWSTATE));
 	uartConfig.baseAddr = config->baseAddr;
 	Status = SysbusUart_Init(&((*instPtr)->uartInst), &uartConfig);
 	if (Status != SUCCESS)
@@ -304,11 +310,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		DBG_WARNING("SystemBus::Production code mismatch!\n");
 		return EIGNORE;
 	}
+
 	switch (data[WD_CMD])
 	{
 	case CMD_SELF_TEST:
 	{
-		HWSTATE *hwStatsPtr = &(instPtr->sysLog.hwState);
+		HWSTATE *hwStatsPtr = &(instPtr->hwState);
 		sysbusRsp = malloc(sizeof(SYSBUS_UART_FRAME));
 		if (sysbusRsp == NULL) {
 			DBG_ERROR("Failed to allocate memory for SELF TEST Response!\n");
@@ -329,7 +336,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			sysbusRsp->data[WD_ST_RET] = (hwStatsPtr->isSpOk && hwStatsPtr->isAntOk) ? ST_RET_OK : ST_RET_ERROR;
 		}
 		// apply status and omit 2 bytes of overhead.
-		memcpy(sysbusRsp->data + WD_SP_PS_VOLT, &(hwStatsPtr->spPsVolt), ST_RET_INFO_LEN);
+		memcpy(sysbusRsp->data + WD_SP_FPGA_VOLT, &(hwStatsPtr->spFpgaVolt), ST_RET_INFO_LEN);
 
 		if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false)
 		{
@@ -449,6 +456,8 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		}
 
 		Linklayer_Start(linkInstPtr);
+		instPtr->sysbusLog.lastConfig[0] = data[WD_MODE_CMD];
+		instPtr->sysbusLog.lastConfig[1] = data[WD_EN_CMD];
 		Status = SUCCESS;
 		break;
 	}
@@ -462,11 +471,15 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 	case CMD_FLJ_SEND:
 	{
 		SysMonitor_UpdateSendPayload(data + FLJ_DATA_OFFSET, PAYLOAD_LEN_FLJ_TX); // omit control info
+		instPtr->sysbusLog.svcCnt++;
+		Status = SUCCESS;
 		break;
 	}
 	case CMD_LJ_SEND:
 	{
 		SysMonitor_UpdateSendPayload(data + LJ_DATA_OFFSET, PAYLOAD_LEN_LJ_TX); // omit control info
+		instPtr->sysbusLog.svcCnt++;
+		Status = SUCCESS;
 		break;
 	}
 	case CMD_FLJ_POLL:
@@ -502,6 +515,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.pollCnt++;
 		Status = SUCCESS;
 		break;
 	}
@@ -538,12 +552,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.pollCnt++;
 		Status = SUCCESS;
 		break;
 	}
 	case CMD_FLJ_RM_TEST:
 	{
-		SYSLOG *sysLogPtr = &(instPtr->sysLog);
 		if (data[WD_FLJ_RM_TEST] != FLJ_RM_TEST_CODE)
 		{
 			DBG_WARNING("SystemBus::Invalid remote test code!\n");
@@ -567,10 +581,13 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		TimeCtrl_GetCurrentTime(linkInstPtr->config.tmcInstPtr, &tmWord);
 		time = tmWord.int_part * TIME_FRAC_MAX + tmWord.frac_part;
 		memcpy(sysbusRsp->data + WD_FLJ_TIME_STAMP, &time, WD_FLJ_TIME_STAMP_LEN);
-		SysMonitor_GetSyslog(sysLogPtr);
+		SysMonitor_GetLinklayerLog(&(instPtr->linkLog));
-		memcpy(sysbusRsp->data + WD_FLJ_LINK_LOG, &(sysLogPtr->linkLog), WD_FLJ_LINK_LOG_LEN);
+		SysMonitor_GetPhysicalLayerLog(&(instPtr->phyLog));
-		memcpy(sysbusRsp->data + WD_FLJ_PHY_LOG, &(sysLogPtr->phyLog), WD_FLJ_PHY_LOG_LEN);
+		SysMonitor_GetHardwareStatus(&(instPtr->hwState));
-		memcpy(sysbusRsp->data + WD_FLJ_HARDWARE_ST, &(sysLogPtr->hwState.spPsVolt), WD_FLJ_HARDWARE_ST_LEN);
+		memcpy(sysbusRsp->data + WD_FLJ_SYSBUS_LOG, &(instPtr->sysbusLog), WD_FLJ_SYSBUS_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_FLJ_LINK_LOG, &(instPtr->linkLog), WD_FLJ_LINK_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_FLJ_PHY_LOG, &(instPtr->phyLog), WD_FLJ_PHY_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_FLJ_HARDWARE_ST, &(instPtr->hwState.spFpgaVolt), WD_FLJ_HARDWARE_ST_LEN);
 
 		if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false){
 			free(sysbusRsp);
@@ -578,12 +595,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.remoteCnt++;
 		Status = SUCCESS;
 		break;
 	}
 	case CMD_LJ_RM_TEST:
 	{
-		SYSLOG *sysLogPtr = &(instPtr->sysLog);
 		if (data[WD_LJ_RM_TEST] != LJ_RM_TEST_CODE)
 		{
 			DBG_WARNING("SystemBus::Invalid remote test code!\n");
@@ -607,10 +624,13 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		TimeCtrl_GetCurrentTime(linkInstPtr->config.tmcInstPtr, &tmWord);
 		time = tmWord.int_part * TIME_FRAC_MAX + tmWord.frac_part;
 		memcpy(sysbusRsp->data + WD_LJ_TIME_STAMP, &time, WD_LJ_TIME_STAMP_LEN);
-		SysMonitor_GetSyslog(sysLogPtr);
+		SysMonitor_GetLinklayerLog(&(instPtr->linkLog));
-		memcpy(sysbusRsp->data + WD_LJ_LINK_LOG, &(sysLogPtr->linkLog), WD_LJ_LINK_LOG_LEN);
+		SysMonitor_GetPhysicalLayerLog(&(instPtr->phyLog));
-		memcpy(sysbusRsp->data + WD_LJ_PHY_LOG, &(sysLogPtr->phyLog), WD_LJ_PHY_LOG_LEN);
+		SysMonitor_GetHardwareStatus(&(instPtr->hwState));
-		memcpy(sysbusRsp->data + WD_LJ_HARDWARE_ST, &(sysLogPtr->hwState.spPsVolt), WD_LJ_HARDWARE_ST_LEN);
+		memcpy(sysbusRsp->data + WD_LJ_SYSBUS_LOG, &(instPtr->sysbusLog), WD_LJ_SYSBUS_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_LJ_LINK_LOG, &(instPtr->linkLog), WD_LJ_LINK_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_LJ_PHY_LOG, &(instPtr->phyLog), WD_LJ_PHY_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_LJ_HARDWARE_ST, &(instPtr->hwState.spFpgaVolt), WD_LJ_HARDWARE_ST_LEN);
 
 		if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false){
 			free(sysbusRsp);
@@ -618,12 +638,14 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.remoteCnt++;
 		Status = SUCCESS;
 		break;
 	}
 	default:
 	{
 		DBG_ERROR("SystemBus::Unknown command code!\n");
+		Status = FAILURE;
 		break;
 	}
 	}

df_datalink_sp/src/systembus/systembus.h

@@ -36,7 +36,10 @@ typedef struct
 typedef struct
 {
     SYSBUS_CONFIG config;
-    SYSLOG sysLog;
+    SYSBUSLOG sysbusLog; // systembus log
+	LINKLOG linkLog; // Link layer log
+	PHYLOG phyLog; // Physical layer log
+	HWSTATE hwState; // Hardware status
     SYSBUS_UART *uartInst;
     CIRC_QUEUE *txQueue;
     CIRC_QUEUE *rxQueue;

makecopy

@@ -10,5 +10,5 @@ cp -rL $PROJECT_DIR/df_datalink_sp/src $DST_DIR/df_datalink_sp
 cp -rL $PROJECT_DIR/df_datalink_ge/src $DST_DIR/df_datalink_ge
 
 cd $DST_DIR/df_datalink_ge/networking/phy_layer
-sed -i "s/antConfig->rfTxMgc = 0;/antConfig->rfTxMgc = $GE_TXATT;/g" ./phy_antenna.c
+sed -i'' -e "s/antConfig->rfTxMgc = 0;/antConfig->rfTxMgc = $GE_TXATT;/g" ./phy_antenna.c
-sed -i "s/antConfig->rcvMgc = 0;/antConfig->rcvMgc = $GE_RXATT;/g" ./phy_antenna.c
+sed -i'' -e "s/antConfig->rcvMgc = 0;/antConfig->rcvMgc = $GE_RXATT;/g" ./phy_antenna.c