add hardware configuration files

df_datalink_ge/src/hardware/headless.c

@@ -1,5 +1,4 @@
-/***************************************************************************//**
+/*******************************************************************************																		   *   @file   ad9371/src/app/headless.c
- *   @file   ad9371/src/app/headless.c
  *   @brief  Implementation of Main Function.
  ********************************************************************************
  * Copyright 2017(c) Analog Devices, Inc.
@@ -66,7 +65,8 @@ int HARDWARE_initialize()
 
 	Status = HARDWARE_ad9371Config();
 
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
@@ -75,11 +75,11 @@ int HARDWARE_initialize()
 	//	/**********************************************************/
 	//	Status = HW_ad9371DynamicCfgInit();
 	//	if (Status != ADIERR_OK){
-//		printf("HW:: AD9371 dynamic configuration initialization failed!\n");
+	//		HW_PRINT("HW:: AD9371 dynamic configuration initialization failed!\n");
 	//		return ADIERR_FAILED;
 	//	}
 	//
-//	printf("HW:: AD9371 ready to be reconfigured!\n");
+	//	HW_PRINT("HW:: AD9371 ready to be reconfigured!\n");
 	//
 	//	// main loop
 	//	while(1);
@@ -101,57 +101,64 @@ int HARDWARE_ad9371Config(void)
 	/*********** Initialize Configuration Interface ***********/
 	/**********************************************************/
 	Status = CMB_initPlatform();
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
 	Status = HW_adiCfgProfileInit();
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
-	printf("HW:: Initialize configuration interface done!\n");
+	HW_PRINT("HW:: Initialize configuration interface done!\n");
 
 	/**********************************************************/
 	/****************** AD9528 Configuration ******************/
 	/**********************************************************/
 	Status = HW_9528Config(ad9528Init);
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
-	printf("HW:: AD9528 configuration done!\n");
+	HW_PRINT("HW:: AD9528 configuration done!\n");
 
 	Status = HW_9528GetLockStatus(ad9528Init, &reg508);
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
-	printf("HW:: AD9528 REG508: 0x%02x\n",reg508);
+	HW_PRINT("HW:: AD9528 REG508: 0x%02x\n", reg508);
 
 	/**********************************************************/
 	/****************** AD9371 Configuration ******************/
 	/**********************************************************/
 	Status = HW_9371Config(ad9528Init, &mykDevice);
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
 
 	Status = HW_9371CheckJesdStatus(&mykDevice, &framerStatus,
 									&obsFramerStatus, &deframerStatus);
-	if (Status != ADIERR_OK){
+	if (Status != ADIERR_OK)
+	{
 		return ADIERR_FAILED;
 	}
-	else {
+	else
+	{
 		// typical value: 0x3E
-		printf("HW:: RxFramerStatus = 0x%x\n", framerStatus);
+		HW_PRINT("HW:: RxFramerStatus = 0x%x\n", framerStatus);
 		// typical value: 0x3E
-		printf("HW:: OrxFramerStatus = 0x%x\n", obsFramerStatus);
+		HW_PRINT("HW:: OrxFramerStatus = 0x%x\n", obsFramerStatus);
 		// typical value: 0x28
-		printf("HW:: DeframerStatus = 0x%x\n", deframerStatus);
+		HW_PRINT("HW:: DeframerStatus = 0x%x\n", deframerStatus);
 	}
 
-	printf("HW:: All configuration done!\n");
+	HW_PRINT("HW:: All configuration done!\n");
 
 	return ADIERR_OK;
 }
@@ -163,7 +170,7 @@ int HARDWARE_ad9371Config(void)
 //
 //	Status = HW_setupIntrSystem(INTC_DEVICE_ID, &Intc);
 //	if (Status != XST_SUCCESS) {
-//		printf("HW: HW_setupIntrSystem() failed!\n");
+//		HW_PRINT("HW: HW_setupIntrSystem() failed!\n");
 //		return XST_FAILURE;
 //	}
 //
@@ -171,7 +178,7 @@ int HARDWARE_ad9371Config(void)
 //	Status |= XGpio_Initialize(&GpioGainCtrl, GAIN_CTRL_DEVICE_ID);
 //	Status |= XGpio_Initialize(&GpioAttnCtrl, ATTN_CTRL_DEVICE_ID);
 //	if (Status != XST_SUCCESS) {
-//		printf("HW: GPIO init failed!\n");
+//		HW_PRINT("HW: GPIO init failed!\n");
 //		return XST_FAILURE;
 //	}
 //
@@ -229,14 +236,16 @@ int HW_setupIntrSystem(u16 DeviceId, XScuGic * GicPtr)
 	 * use.
 	 */
 	CfgPtr = XScuGic_LookupConfig(DeviceId);
-    if (!CfgPtr) {
+	if (!CfgPtr)
-        printf("No interrupt config found for %d\n", DeviceId);
+	{
+		HW_PRINT("No interrupt config found for %d\n", DeviceId);
 		return XST_FAILURE;
 	}
 
 	Status = XScuGic_CfgInitialize(GicPtr, CfgPtr, CfgPtr->CpuBaseAddress);
-    if (Status != XST_SUCCESS) {
+	if (Status != XST_SUCCESS)
-        printf("No interrupt config found for %d\n", DeviceId);
+	{
+		HW_PRINT("No interrupt config found for %d\n", DeviceId);
 		return XST_FAILURE;
 	}
 
@@ -249,7 +258,6 @@ int HW_setupIntrSystem(u16 DeviceId, XScuGic * GicPtr)
 	return XST_SUCCESS;
 }
 
-
 int HW_connectIntr(XScuGic *GicPtr, u32 IntrId, Xil_InterruptHandler Handler,
 				   void *CallBackRef, u8 Priority, u8 Trigger)
 {
@@ -268,16 +276,17 @@ int HW_connectIntr(XScuGic *GicPtr,u32 IntrId,Xil_InterruptHandler Handler,
 	return XST_SUCCESS;
 }
 
-
 int HW_adiCfgProfileInit(void)
 {
-	if (!ad9528Init) {
+	if (!ad9528Init)
-		printf("Cannot find ad9528 configuration profile with name 'ad9528Init'!");
+	{
+		HW_PRINT("Cannot find ad9528 configuration profile with name 'ad9528Init'!");
 		return ADIERR_FAILED;
 	}
 
-	if (!&mykDevice) {
+	if (!&mykDevice)
-		printf("Cannot find ad9371 configuration profile with name 'mykDevice'!");
+	{
+		HW_PRINT("Cannot find ad9371 configuration profile with name 'mykDevice'!");
 		return ADIERR_FAILED;
 	}
 
@@ -293,7 +302,6 @@ int HW_adiCfgProfileInit(void)
 	return ADIERR_OK;
 }
 
-
 int HW_9528Config(ad9528Device_t *clockAD9528_device)
 {
 	ADI_ERR error;
@@ -303,8 +311,9 @@ int HW_9528Config(ad9528Device_t *clockAD9528_device)
 
 	/* Perform a hard reset on the AD9528 DUT */
 	error = AD9528_resetDevice(clockAD9528_device);
-	if (error != ADIERR_OK) {
+	if (error != ADIERR_OK)
-		printf("AD9528_resetDevice() failed\n");
+	{
+		HW_PRINT("AD9528_resetDevice() failed\n");
 		return ADIERR_FAILED;
 	}
 
@@ -312,35 +321,36 @@ int HW_9528Config(ad9528Device_t *clockAD9528_device)
 										clockAD9528_device->pll1Settings->vcxo_Frequency_Hz,
 										clockAD9528_device->pll1Settings->refA_Frequency_Hz,
 										clockAD9528_device->outputSettings->outFrequency_Hz[1]);
-	if (error != ADIERR_OK) {
+	if (error != ADIERR_OK)
-		printf("AD9528_initDeviceDataStruct() failed\n");
+	{
+		HW_PRINT("AD9528_initDeviceDataStruct() failed\n");
 		return ADIERR_FAILED;
 	}
 
 	/* Initialize the AD9528 by writing all SPI registers */
 	error = AD9528_initialize(clockAD9528_device);
-	if (error != ADIERR_OK) {
+	if (error != ADIERR_OK)
-		printf("WARNING: AD9528_initialize() issues.\n");
+	{
+		HW_PRINT("WARNING: AD9528_initialize() issues.\n");
 	}
 
 	return ADIERR_OK;
 }
 
-
 int HW_9528GetLockStatus(ad9528Device_t *device, uint8_t *reg508)
 {
 	ADI_ERR error;
 
 	error = CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, reg508);
-	if (error != ADIERR_OK) {
+	if (error != ADIERR_OK)
-		printf("HW_9528GetLockStatus failed.\n");
+	{
+		HW_PRINT("HW_9528GetLockStatus failed.\n");
 		return ADIERR_FAILED;
 	}
 
 	return ADIERR_OK;
 }
 
-
 int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice)
 {
 	ADI_ERR error;
@@ -365,19 +375,19 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/* Allocating memory for the errorString */
 	errorString = NULL;
 
-
-
 	/*************************************************************************/
 	/*****                Mykonos Initialization Sequence                *****/
 	/*************************************************************************/
 
 	/* Perform a hard reset on the MYKONOS DUT (Toggle RESETB pin on device) */
-	if ((mykError = MYKONOS_resetDevice(mykDevice)) != MYKONOS_ERR_OK) {
+	if ((mykError = MYKONOS_resetDevice(mykDevice)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
-	if ((mykError = MYKONOS_initialize(mykDevice)) != MYKONOS_ERR_OK) {
+	if ((mykError = MYKONOS_initialize(mykDevice)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -387,7 +397,8 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_checkPllsLockStatus(mykDevice,
-			&pllLockStatus)) != MYKONOS_ERR_OK) {
+												&pllLockStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -397,7 +408,8 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_enableMultichipSync(mykDevice, 1,
-			&mcsStatus)) != MYKONOS_ERR_OK) {
+												&mcsStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -418,34 +430,40 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_enableMultichipSync(mykDevice, 0,
-			&mcsStatus)) != MYKONOS_ERR_OK) {
+												&mcsStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	if ((mcsStatus & 0x0B) == 0x0B)
-		printf("MCS successful\n");
+		HW_PRINT("MCS successful\n");
 	else
-		printf("MCS failed\n");
+		HW_PRINT("MCS failed\n");
 
 	/*************************************************************************/
 	/*****                Mykonos Load ARM file                          *****/
 	/*************************************************************************/
 
-	if (pllLockStatus & 0x01) {
+	if (pllLockStatus & 0x01)
-		printf("CLKPLL locked\n");
+	{
-		if ((mykError = MYKONOS_initArm(mykDevice)) != MYKONOS_ERR_OK) {
+		HW_PRINT("CLKPLL locked\n");
+		if ((mykError = MYKONOS_initArm(mykDevice)) != MYKONOS_ERR_OK)
+		{
 			errorString = getMykonosErrorMessage(mykError);
 			goto error_11;
 		}
 
 		if ((mykError = MYKONOS_loadArmFromBinary(mykDevice,
-				&firmware_Mykonos_M3_bin[0], firmware_Mykonos_M3_bin_len)) != MYKONOS_ERR_OK) {
+												  &firmware_Mykonos_M3_bin[0], firmware_Mykonos_M3_bin_len)) != MYKONOS_ERR_OK)
+		{
 			errorString = getMykonosErrorMessage(mykError);
 			goto error_11;
 		}
-	} else {
+	}
-		printf("CLKPLL not locked (0x%x)\n", pllLockStatus);
+	else
+	{
+		HW_PRINT("CLKPLL not locked (0x%x)\n", pllLockStatus);
 		error = ADIERR_FAILED;
 		goto error_2;
 	}
@@ -453,26 +471,29 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/* Read back the version of the ARM binary loaded into the Mykonos ARM memory */
 	if ((mykError = MYKONOS_getArmVersion(mykDevice, &arm_major, &arm_minor,
 										  &arm_release, NULL)) == MYKONOS_ERR_OK)
-		printf("AD9371 ARM version %d.%d.%d\n", arm_major, arm_minor, arm_release);
+		HW_PRINT("AD9371 ARM version %d.%d.%d\n", arm_major, arm_minor, arm_release);
 
 	/*************************************************************************/
 	/*****                Mykonos Set RF PLL Frequencies                 *****/
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, RX_PLL,
-			mykDevice->rx->rxPllLoFrequency_Hz)) != MYKONOS_ERR_OK) {
+											  mykDevice->rx->rxPllLoFrequency_Hz)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, TX_PLL,
-			mykDevice->tx->txPllLoFrequency_Hz)) != MYKONOS_ERR_OK) {
+											  mykDevice->tx->txPllLoFrequency_Hz)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, SNIFFER_PLL,
-			mykDevice->obsRx->snifferPllLoFrequency_Hz)) != MYKONOS_ERR_OK) {
+											  mykDevice->obsRx->snifferPllLoFrequency_Hz)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -481,15 +502,17 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	mdelay(200);
 
 	if ((mykError = MYKONOS_checkPllsLockStatus(mykDevice,
-			&pllLockStatus)) != MYKONOS_ERR_OK) {
+												&pllLockStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	if ((pllLockStatus & 0x0F) == 0x0F)
-		printf("PLLs locked\n");
+		HW_PRINT("PLLs locked\n");
-	else {
+	else
-		printf("PLLs not locked (0x%x)\n", pllLockStatus);
+	{
+		HW_PRINT("PLLs not locked (0x%x)\n", pllLockStatus);
 		error = ADIERR_FAILED;
 		goto error_2;
 	}
@@ -592,56 +615,67 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_runInitCals(mykDevice,
-					    (initCalMask & ~TX_LO_LEAKAGE_EXTERNAL))) != MYKONOS_ERR_OK) {
+										(initCalMask & ~TX_LO_LEAKAGE_EXTERNAL))) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	if ((mykError = MYKONOS_waitInitCals(mykDevice, 60000, &errorFlag,
-					     &errorCode)) != MYKONOS_ERR_OK) {
+										 &errorCode)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
-	if ((errorFlag != 0) || (errorCode != 0)) {
+	if ((errorFlag != 0) || (errorCode != 0))
+	{
 		/*** < Info: abort init cals > ***/
 		if ((mykError = MYKONOS_abortInitCals(mykDevice,
-						      &initCalsCompleted)) != MYKONOS_ERR_OK) {
+											  &initCalsCompleted)) != MYKONOS_ERR_OK)
+		{
 			errorString = getMykonosErrorMessage(mykError);
 			goto error_11;
 		}
 		if (initCalsCompleted)
-			printf("Completed calibrations: %x\n", (unsigned int)initCalsCompleted);
+			HW_PRINT("Completed calibrations: %x\n", (unsigned int)initCalsCompleted);
-	} else
+	}
-		printf("Calibrations completed successfully\n");
+	else
+		HW_PRINT("Calibrations completed successfully\n");
 
 	/*************************************************************************/
 	/*****  Mykonos ARM Initialization External LOL Calibrations with PA *****/
 	/*************************************************************************/
 
 	/* Please ensure PA is enabled operational at this time */
-	if (initCalMask & TX_LO_LEAKAGE_EXTERNAL) {
+	if (initCalMask & TX_LO_LEAKAGE_EXTERNAL)
+	{
 		if ((mykError = MYKONOS_runInitCals(mykDevice,
-						    TX_LO_LEAKAGE_EXTERNAL)) != MYKONOS_ERR_OK) {
+											TX_LO_LEAKAGE_EXTERNAL)) != MYKONOS_ERR_OK)
+		{
 			errorString = getMykonosErrorMessage(mykError);
 			goto error_11;
 		}
 
 		if ((mykError = MYKONOS_waitInitCals(mykDevice, 60000, &errorFlag,
-						     &errorCode)) != MYKONOS_ERR_OK) {
+											 &errorCode)) != MYKONOS_ERR_OK)
+		{
 			errorString = getMykonosErrorMessage(mykError);
 			goto error_11;
 		}
 
-		if ((errorFlag != 0) || (errorCode != 0)) {
+		if ((errorFlag != 0) || (errorCode != 0))
+		{
 			/*** < Info: abort init cals > ***/
 			if ((mykError = MYKONOS_abortInitCals(mykDevice,
-							      &initCalsCompleted)) != MYKONOS_ERR_OK) {
+												  &initCalsCompleted)) != MYKONOS_ERR_OK)
+			{
 				errorString = getMykonosErrorMessage(mykError);
 				goto error_11;
 			}
-		} else
+		}
-			printf("External LOL Calibrations completed successfully\n");
+		else
+			HW_PRINT("External LOL Calibrations completed successfully\n");
 	}
 
 	/*************************************************************************/
@@ -649,7 +683,8 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_enableSysrefToRxFramer(mykDevice,
-			1)) != MYKONOS_ERR_OK) {
+												   1)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -657,7 +692,8 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	 * transmitting CGS from the RxFramer> ***/
 
 	if ((mykError = MYKONOS_enableSysrefToObsRxFramer(mykDevice,
-			1)) != MYKONOS_ERR_OK) {
+													  1)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -665,18 +701,20 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	 * transmitting CGS from the ObsRxFramer> ***/
 
 	if ((mykError = MYKONOS_enableSysrefToDeframer(mykDevice,
-			0)) != MYKONOS_ERR_OK) {
+												   0)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
-	if ((mykError = MYKONOS_resetDeframer(mykDevice)) != MYKONOS_ERR_OK) {
+	if ((mykError = MYKONOS_resetDeframer(mykDevice)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
-	if ((mykError = MYKONOS_enableSysrefToDeframer(mykDevice,
+	if ((mykError = MYKONOS_enableSysrefToDeframer(mykDevice, 1)) != MYKONOS_ERR_OK)
-			1)) != MYKONOS_ERR_OK) {
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -704,7 +742,8 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_enableTrackingCals(mykDevice,
-			trackingCalMask)) != MYKONOS_ERR_OK) {
+											   trackingCalMask)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -714,19 +753,22 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 
 	/*** < Info: Function to turn radio on, Enables transmitters and receivers
 	 * that were setup during MYKONOS_initialize() > ***/
-	if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK) {
+	if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	/*** < Info: Allow TxQEC to run when User: is not actively using ORx receive path > ***/
 	if ((mykError = MYKONOS_setObsRxPathSource(mykDevice,
-			OBS_RXOFF)) != MYKONOS_ERR_OK) {
+											   OBS_RXOFF)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 	if ((mykError = MYKONOS_setObsRxPathSource(mykDevice,
-			OBS_INTERNALCALS)) != MYKONOS_ERR_OK) {
+											   OBS_INTERNALCALS)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
@@ -734,26 +776,26 @@ int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice
 	mdelay(1000);
 
 	if ((mykError = MYKONOS_setObsRxPathSource(mykDevice,
-			OBS_RX1_SNIFFERLO)) != MYKONOS_ERR_OK) {
+											   OBS_RX1_SNIFFERLO)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		goto error_11;
 	}
 
 	Xil_DCacheInvalidateRange(DDR_MEM_BASEADDR + 0x800000, 16384 * 8);
 
-	printf("Done\n");
+	HW_PRINT("Done\n");
 
 	return 0;
 
 error_11:
-	printf("%s", errorString);
+	HW_PRINT("%s", errorString);
 
 error_2:
 	//	axi_clkgen_remove(rx_clkgen);
 	return FAILURE;
 }
 
-
 int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus,
 						   uint8_t *obsFramerStatus, uint8_t *deframerStatus)
 {
@@ -767,19 +809,24 @@ int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus,
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_readRxFramerStatus(mykDevice,
-			framerStatus)) != MYKONOS_ERR_OK) {
+											   framerStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		return ADIERR_FAILED;
 	}
-	else {
+	else
+	{
 		// typical value: 0x3E
 	}
 
 	if ((mykError = MYKONOS_readOrxFramerStatus(mykDevice,
-			obsFramerStatus)) != MYKONOS_ERR_OK) {
+												obsFramerStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		return ADIERR_FAILED;
-	} else {
+	}
+	else
+	{
 		// typical value: 0x3E
 	}
 
@@ -788,17 +835,19 @@ int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus,
 	/*************************************************************************/
 
 	if ((mykError = MYKONOS_readDeframerStatus(mykDevice,
-			deframerStatus)) != MYKONOS_ERR_OK) {
+											   deframerStatus)) != MYKONOS_ERR_OK)
+	{
 		errorString = getMykonosErrorMessage(mykError);
 		return ADIERR_FAILED;
-	} else {
+	}
+	else
+	{
 		// typical value: 0x28
 	}
 
 	return ADIERR_OK;
 }
 
-
 int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 {
 	mykonosErr_t mykError = MYKONOS_ERR_OK;
@@ -808,7 +857,7 @@ int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	 */
 	if ((mykError = MYKONOS_radioOff(mykDevice)) != MYKONOS_ERR_OK)
 	{
-		printf("Turn radio off failed!\n\r");
+		HW_PRINT("Turn radio off failed!\n\r");
 		return ADIERR_FAILED;
 	}
 
@@ -818,14 +867,14 @@ int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, TX_PLL,
 											  freq_Hz)) != MYKONOS_ERR_OK)
 	{
-		printf("Set TX PLL failed!\n\r");
+		HW_PRINT("Set TX PLL failed!\n\r");
 		return ADIERR_FAILED;
 	}
 	mykError = MYKONOS_checkPllsLockStatus(mykDevice, &pllLockStatus);
 	if ((pllLockStatus & 0x07) != 0x07)
 	{
 		/*** < Info: Clock, Rx and Tx PLLs not locked > ***/
-		printf("Not all PLLs locked, lock status: 0x%02x\n", pllLockStatus);
+		HW_PRINT("Not all PLLs locked, lock status: 0x%02x\n", pllLockStatus);
 	}
 
 	/*
@@ -834,7 +883,7 @@ int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	//	If((mykError = MYKONOS_resetExtTxLolChannel(mykDevice, TX1_TX2))
 	//		!= MYKONOS_ERR_OK) ; //where TX1_TX2 is part of the enum mykonosTxChannels_t
 	//	{
-//		printf("Reset external channel FAILED!");
+	//		HW_PRINT("Reset external channel FAILED!");
 	//	}
 
 	/*
@@ -842,7 +891,7 @@ int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	 */
 	if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK)
 	{
-		printf("Turn radio on failed!\n\r");
+		HW_PRINT("Turn radio on failed!\n\r");
 		return ADIERR_FAILED;
 	}
 
@@ -852,12 +901,11 @@ int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	//	If((mykError = MYKONOS_MYKONOS_setObsRxPathSource(mykDevice, OBS_INTERNALCALS))
 	//		!= MYKONOS_ERR_OK) ; //where TX1_TX2 is part of the enum mykonosTxChannels_t
 	//	{
-//		printf("Reenable tracking calibrations FAILED!");
+	//		HW_PRINT("Reenable tracking calibrations FAILED!");
 	//	}
 	return ADIERR_OK;
 }
 
-
 int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 {
 	mykonosErr_t mykError = MYKONOS_ERR_OK;
@@ -875,7 +923,7 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	 */
 	if ((mykError = MYKONOS_radioOff(mykDevice)) != MYKONOS_ERR_OK)
 	{
-		printf("Turn radio off failed!\n\r");
+		HW_PRINT("Turn radio off failed!\n\r");
 		return ADIERR_FAILED;
 	}
 
@@ -885,14 +933,14 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, TX_PLL,
 											  freq_Hz)) != MYKONOS_ERR_OK)
 	{
-		printf("Set TX PLL failed!\n\r");
+		HW_PRINT("Set TX PLL failed!\n\r");
 		return ADIERR_FAILED;
 	}
 	mykError = MYKONOS_checkPllsLockStatus(mykDevice, &pllLockStatus);
 	if ((pllLockStatus & 0x07) != 0x07)
 	{
 		/*** < Info: Clock, Rx and Tx PLLs not locked > ***/
-		printf("Not all PLLs locked, lock status: 0x%02x\n", pllLockStatus);
+		HW_PRINT("Not all PLLs locked, lock status: 0x%02x\n", pllLockStatus);
 	}
 
 	/*
@@ -900,34 +948,30 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	 */
 	uint32_t initCalMask = TX_QEC_INIT | LOOPBACK_RX_LO_DELAY |
 						   LOOPBACK_RX_RX_QEC_INIT | RX_LO_DELAY | RX_QEC_INIT;
-	if ((mykError = MYKONOS_runInitCals(mykDevice, initCalMask))
+	if ((mykError = MYKONOS_runInitCals(mykDevice, initCalMask)) != MYKONOS_ERR_OK)
-		!= MYKONOS_ERR_OK)
 	{
-		printf("Rerun the initialization calibrations FAILED!");
+		HW_PRINT("Rerun the initialization calibrations FAILED!");
 		return ADIERR_FAILED;
 	}
 	if ((mykError = MYKONOS_waitInitCals(mykDevice, 60000, &errorFlag,
 										 &errorCode)) != MYKONOS_ERR_OK)
 	{
-		printf("Initialize calibration TIME OUT!");
+		HW_PRINT("Initialize calibration TIME OUT!");
 		return ADIERR_FAILED;
 	}
 	if ((errorFlag != 0) || (errorCode != 0))
 	{
-		printf("initial cals error!\n\r");
+		HW_PRINT("initial cals error!\n\r");
 
-		if((mykError = MYKONOS_getInitCalStatus(mykDevice, &initCalStatus))
+		if ((mykError = MYKONOS_getInitCalStatus(mykDevice, &initCalStatus)) != MYKONOS_ERR_OK)
-			!= MYKONOS_ERR_OK)
 		{
 			/*** < User log error return value to debug why init failed > ***/
 		}
 
 		// abort init calibrations
-		if((mykError = MYKONOS_abortInitCals(mykDevice, &initCalsCompleted))
+		if ((mykError = MYKONOS_abortInitCals(mykDevice, &initCalsCompleted)) != MYKONOS_ERR_OK)
-			!= MYKONOS_ERR_OK)
 		{
 			/*** < User log error return value to debug why init failed > ***/
-
 		}
 		if (initCalsCompleted)
 		{
@@ -938,10 +982,8 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 		{
 			/*** < User log error return value to debug why init failed > ***/
 		}
-		if((mykError = MYKONOS_readArmCmdStatusByte(mykDevice, 2, &status))
+		if ((mykError = MYKONOS_readArmCmdStatusByte(mykDevice, 2, &status)) != MYKONOS_ERR_OK)
-			!= MYKONOS_ERR_OK)
 		{
-
 		}
 		if (status != 0)
 		{
@@ -955,26 +997,25 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 	 */
 	if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK)
 	{
-		printf("Turn radio on failed!\n\r");
+		HW_PRINT("Turn radio on failed!\n\r");
 		return ADIERR_FAILED;
 	}
 
 	return ADIERR_OK;
 }
 
-
 // void FreqIntrHandler(void *CallbackRef)
 // {
 // 	XGpio *GpioPtr = (XGpio *)CallbackRef;
 // 	uint8_t IntrStatus;
 // 	uint32_t NewFreqHz;
 // 	IntrStatus = XGpio_InterruptGetStatus(GpioPtr);
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH1_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH1_MASK);
-//
+
 // 		NewFreqHz = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_1);
 // 		if (NewFreqHz != mykDevice.tx->txPllLoFrequency_Hz)
 // 		{
@@ -989,20 +1030,20 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 					HW_9371LargeFrequencyChange(&mykDevice, NewFreqHz);
 // 				}
 // 				mykDevice.tx->txPllLoFrequency_Hz = NewFreqHz;
-//				printf("New Tx frequency set to %d Hz!\n",NewFreqHz);
+// 				HW_PRINT("New Tx frequency set to %d Hz!\n", NewFreqHz);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Tx Frequency is out of range(300 ~ 6000 MHz)!\n");
+// 				HW_PRINT("The desired Tx Frequency is out of range(300 ~ 6000 MHz)!\n");
 // 			}
 // 		}
 // 	}
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH2_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH2_MASK);
-//
+
 // 		NewFreqHz = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_2);
 // 		if (NewFreqHz != mykDevice.rx->rxPllLoFrequency_Hz)
 // 		{
@@ -1017,29 +1058,28 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 					HW_9371LargeFrequencyChange(&mykDevice, NewFreqHz);
 // 				}
 // 				mykDevice.rx->rxPllLoFrequency_Hz = NewFreqHz;
-//				printf("New Rx frequency set to %d Hz!\n",NewFreqHz);
+// 				HW_PRINT("New Rx frequency set to %d Hz!\n", NewFreqHz);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Rx Frequency is out of range(300 ~ 6000 MHz)!\n");
+// 				HW_PRINT("The desired Rx Frequency is out of range(300 ~ 6000 MHz)!\n");
 // 			}
 // 		}
 // 	}
 // }
-//
+
-//
 // void GainIntrHandler(void *CallbackRef)
 // {
 // 	XGpio *GpioPtr = (XGpio *)CallbackRef;
 // 	uint8_t IntrStatus;
 // 	uint32_t NewRxGain;
 // 	IntrStatus = XGpio_InterruptGetStatus(GpioPtr);
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH1_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH1_MASK);
-//
+
 // 		NewRxGain = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_1);
 // 		if (NewRxGain != mykDevice.rx->rxGainCtrl->rx1GainIndex)
 // 		{
@@ -1048,21 +1088,21 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 				MYKONOS_setRx1ManualGain(&mykDevice, NewRxGain);
 // 				mykDevice.rx->rxGainCtrl->rx1GainIndex = NewRxGain;
 // 				char buf[BUFSIZ];
-//				sprintf(buf, "%u", NewRxGain);
+// 				sHW_PRINT(buf, "%u", NewRxGain);
-//				printf("New Rx1 gain index set to %s!\n",buf);
+// 				HW_PRINT("New Rx1 gain index set to %s!\n", buf);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Rx1 gain index is out of range(195 ~ 255), 0.5dB per stage!\n");
+// 				HW_PRINT("The desired Rx1 gain index is out of range(195 ~ 255), 0.5dB per stage!\n");
 // 			}
 // 		}
 // 	}
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH2_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH2_MASK);
-//
+
 // 		NewRxGain = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_2);
 // 		if (NewRxGain != mykDevice.rx->rxGainCtrl->rx2GainIndex)
 // 		{
@@ -1071,30 +1111,29 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 				MYKONOS_setRx2ManualGain(&mykDevice, NewRxGain);
 // 				mykDevice.rx->rxGainCtrl->rx2GainIndex = NewRxGain;
 // 				char buf[BUFSIZ];
-//				sprintf(buf, "%u", NewRxGain);
+// 				sHW_PRINT(buf, "%u", NewRxGain);
-//				printf("New Rx2 gain index set to %s!\n",buf);
+// 				HW_PRINT("New Rx2 gain index set to %s!\n", buf);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Rx2 gain index is out of range(195 ~ 255), 0.5dB per stage!\n");
+// 				HW_PRINT("The desired Rx2 gain index is out of range(195 ~ 255), 0.5dB per stage!\n");
 // 			}
 // 		}
 // 	}
 // }
-//
+
-//
 // void AttnIntrHandler(void *CallbackRef)
 // {
 // 	XGpio *GpioPtr = (XGpio *)CallbackRef;
 // 	uint8_t IntrStatus;
 // 	uint32_t NewTxAttn;
 // 	IntrStatus = XGpio_InterruptGetStatus(GpioPtr);
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH1_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH1_MASK);
-//
+
 // 		NewTxAttn = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_1);
 // 		if (NewTxAttn != mykDevice.tx->tx1Atten_mdB)
 // 		{
@@ -1103,21 +1142,21 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 				MYKONOS_setTx1Attenuation(&mykDevice, NewTxAttn);
 // 				mykDevice.tx->tx1Atten_mdB = NewTxAttn;
 // 				char buf[BUFSIZ];
-//				sprintf(buf, "%u", NewTxAttn);
+// 				sHW_PRINT(buf, "%u", NewTxAttn);
-//				printf("New Tx1 attenuation set to %s dBm!\n",buf);
+// 				HW_PRINT("New Tx1 attenuation set to %s dBm!\n", buf);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Tx1 attenuation is out of range(0 ~ 41950 dBm), 50 dBm step!\n");
+// 				HW_PRINT("The desired Tx1 attenuation is out of range(0 ~ 41950 dBm), 50 dBm step!\n");
 // 			}
 // 		}
 // 	}
-//
+
 // 	if (IntrStatus & XGPIO_IR_CH2_MASK)
 // 	{
 // 		/* Clear the Interrupt */
 // 		XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH2_MASK);
-//
+
 // 		NewTxAttn = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_2);
 // 		if (NewTxAttn != mykDevice.tx->tx2Atten_mdB)
 // 		{
@@ -1126,12 +1165,12 @@ int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz)
 // 				MYKONOS_setTx2Attenuation(&mykDevice, NewTxAttn);
 // 				mykDevice.tx->tx2Atten_mdB = NewTxAttn;
 // 				char buf[BUFSIZ];
-//				sprintf(buf, "%u", NewTxAttn);
+// 				sHW_PRINT(buf, "%u", NewTxAttn);
-//				printf("New Tx2 attenuation set to %s dBm!\n",buf);
+// 				HW_PRINT("New Tx2 attenuation set to %s dBm!\n", buf);
 // 			}
 // 			else
 // 			{
-//				printf("The desired Tx2 attenuation is out of range(0 ~ 41950 dBm), 50 dBm step!\n");
+// 				HW_PRINT("The desired Tx2 attenuation is out of range(0 ~ 41950 dBm), 50 dBm step!\n");
 // 			}
 // 		}
 // 	}

df_datalink_ge/src/hardware/headless.h

@@ -1,7 +1,7 @@
 /*
  * headless.h
  *
- *  Created on: 2021Äê6ÔÂ8ÈÕ
+ *  Created on: 2021��6��8��
  *      Author: Josh
  */
 
@@ -30,7 +30,8 @@
 /**************************** Type Definitions *******************************/
 
 /***************** Macros (Inline Functions) Definitions *********************/
-
+#define HW_PRINT(...)  __asm__("nop")
+// #define HW_PRINT(...)  printf(__VA_ARGS__)
 /************************** Variable Definitions *****************************/
 
 /************************** Function Prototypes ******************************/

df_datalink_ge/src/main.c

@@ -51,33 +51,39 @@ void ScuTimer_IntrHandler(void *context);
 void Systembus_RxIntrHandler(void *context);
 void Systembus_TxIntrHandler(void *context);
 /************************** Constant Definitions *****************************/
-struct callback_desc phy_callback_desc = {
+struct callback_desc phy_callback_desc =
+{
 	.callback = Phy_IntrHandler,
 	.ctx = NULL
 };
 
-struct callback_desc periodicpull_callback_desc = {
+struct callback_desc periodicpull_callback_desc =
+{
 	.callback = PeriodicPull_Handler,
 	.ctx = NULL
 };
 
 
-struct callback_desc sysbus_rx_callback_desc = {
+struct callback_desc sysbus_rx_callback_desc =
+{
 	.callback = Systembus_RxIntrHandler,
 	.ctx = NULL
 };
 
-struct callback_desc sysbus_tx_callback_desc = {
+struct callback_desc sysbus_tx_callback_desc =
+{
 	.callback = Systembus_TxIntrHandler,
 	.ctx = NULL
 };
 
-struct callback_desc scutm_callback_desc = {
+struct callback_desc scutm_callback_desc =
+{
 	.callback = ScuTimer_IntrHandler,
 	.ctx = NULL
 };
 
-L2_CONFIG linkConfig = {
+L2_CONFIG linkConfig =
+{
 	.myType = L2_NODE_HEAD,
 	.clustId = 1,
 	.myId = 1,
@@ -99,16 +105,22 @@ L2_CONFIG linkConfig = {
 // 	.tmcInstPtr = NULL
 // };
 
-static PHY_CONFIG phyConfig = {
+static PHY_CONFIG phyConfig =
+{
 	.devId = 0,
 	.baseAddr = PHY_BASEADDR,
 	.antBramId = PHY_ANTCONFIG_BRAM_DEVICE_ID,
 	.txBramId = PHY_TXBUFF_BRAM_DEVICE_ID,
 	.rxBramId = PHY_RXBUFF_BRAM_DEVICE_ID,
-	.hwXadcId = PHY_HW_XADC_DEVICE_ID
+	.hwXadcId = PHY_HW_XADC_DEVICE_ID,
+	.get_clk_state = NULL,
+	.get_ad_lock_state = NULL,
+	.get_ad0_temp = NULL,
+	.get_ad1_temp = NULL
 };
 
-TMC_CONFIG tmcConfig = {
+TMC_CONFIG tmcConfig =
+{
 	.baseAddr = TIME_CONTROLLER_BASEADDR,
 	.reset = 10
 };

df_datalink_sp/build/src/subdir.mk

@@ -8,15 +8,18 @@ LD_SRCS += \
 
 C_SRCS += \
 ../src/main.c \
-../src/system_monitor.c 
+../src/system_monitor.c \
+../src/hwconfig.c
 
 OBJS += \
 ./src/main.o \
-./src/system_monitor.o 
+./src/system_monitor.o \
+./src/hwconfig.o
 
 C_DEPS += \
 ./src/main.d \
-./src/system_monitor.d 
+./src/system_monitor.d \
+./src/hwconfig.d
 
 
 # Each subdirectory must supply rules for building sources it contributes

df_datalink_sp/src/hwconfig.c

@@ -0,0 +1,464 @@
+/*****************************************************************************/
+/**
+ * Description: hwconfig.h
+ *
+
+ * Date: 2024-02-20 13:19
+ * Last Edit Time: [2024-02-20 13:19]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2023-05-07]: Initial edition.
+ *
+ * Copyright(c) 2024 Beijing Institute of Technology.
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+// Standard
+#include <stdint.h>
+#include <stdbool.h>
+// Xilinx
+#include "xgpiops.h"
+#include "drivers/rf-transceiver/ad9361_reg/ad9361_reg.h"
+#include "drivers/rf-transceiver/ad9361/ad9361_api.h"
+#include "drivers/axi_core/spi_engine/spi_engine.h"
+// App
+#include "common.h"
+#include "error.h"
+#include "delay.h"
+#include "system_monitor.h"
+#include "hwconfig.h"
+#include "config/app_config.h"
+#include "dev_profile/dev_profile.h"
+
+/************************** Function Prototypes ******************************/
+/*********************** Driver Instance Definitions **************************/
+static struct hmc7044_dev *hmc7044_inst;
+static struct ad9361_reg_dev *ad9361_1_reg_inst;
+static struct ad9361_reg_dev *ad9361_2_reg_inst;
+// static struct ad9361_rf_phy *ad9361_phy;
+// static struct ad9361_rf_phy *ad9361_2_phy;
+
+/*****************************************************************************/
+/**
+ * @brief   Hardware_Init
+ *
+ * @param   none.
+ *
+ * @return  None.
+ *
+ ******************************************************************************/
+int32_t Hardware_Init(void)
+{
+	int32_t Status;
+	XGpioPs Gpio;
+	XGpioPs_Config *ConfigPtr;
+	ConfigPtr = XGpioPs_LookupConfig(AD9361_GPIO_DEVICE_ID);
+	Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
+	if (Status != SUCCESS)
+	{
+		return FAILURE;
+	}
+
+	/**********************************************************/
+	/****************** HMC7044 Configuration *****************/
+	/**********************************************************/
+	Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param);
+	if (Status != SUCCESS)
+	{
+		DBG_ERROR("hmc7044_init() error: %" PRId32 "\n", Status);
+		return FAILURE;
+	}
+
+	/**********************************************************/
+	/***************** AD9361-1 Configuration *****************/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, AD9361_GPIO_OUTPUT);
+
+	ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param);
+	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0);
+	ad9361_reg_config(ad9361_1_reg_inst);
+	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1);
+
+	//	Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param);
+	//	if (Status != XST_SUCCESS){
+	//		return XST_FAILURE;
+	//	}else{
+	//		printf("Configurate AD9361 Completely!\n");
+	//	}
+	//	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
+	//	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
+
+	/**********************************************************/
+	/***************** AD9361-2 Configuration *****************/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, AD9361_GPIO_OUTPUT);
+
+	ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param);
+	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0);
+	ad9361_reg_config(ad9361_2_reg_inst);
+	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1);
+
+	//	uint8_t rd_back;
+	//	Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
+	//	Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);
+
+	/**********************************************************/
+	/******* AD9361 Baseband Multichip Synchronization ********/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, AD9361_GPIO_OUTPUT);
+
+	// SYNC BBPLL and DIGITAL SAMPLING CLOCKS
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
+	mdelay(20);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin
+	mdelay(500);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
+	mdelay(2000);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin
+	mdelay(500);
+	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08);
+
+	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
+	mdelay(20);
+	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1);
+	mdelay(20);
+	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
+
+	/**********************************************************/
+	/********* AD9361 Multichip Rx Phase Calibration **********/
+	/**********************************************************/
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, AD9361_GPIO_INPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, AD9361_GPIO_OUTPUT);
+	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, AD9361_GPIO_INPUT);
+
+	// switch to lower frequency
+	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
+	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1);
+	mdelay(20);
+
+	// switch rx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30);
+	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30);
+
+	// enable dual ad9361 tx channels
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels
+
+	// switch ad9361 tx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
+	mdelay(20);
+
+	// begin to calibrate the 1st ad9361
+	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
+	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1);
+	mdelay(1);
+	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
+
+	// read calibration status
+	int32_t time_out_cnt = 0;
+	do
+	{
+		mdelay(1); // Wait 1ms
+		time_out_cnt++;
+	} while (((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
+
+	if (time_out_cnt == AD9361_TIMEOUT_TH)
+	{
+		return FAILURE;
+	}
+
+	// begin to calibrate the 2nd ad9361
+	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1);
+	mdelay(1);
+	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0);
+
+	// read calibration status
+	time_out_cnt = 0;
+	do
+	{
+		mdelay(1); // Wait 1ms
+		time_out_cnt++;
+	} while (((XGpioPs_ReadPin(&Gpio, AD9361_2_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
+
+	if (time_out_cnt == AD9361_TIMEOUT_TH)
+	{
+		return FAILURE;
+	}
+
+	// enable single ad9361 tx channels
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
+
+	// switch ad9361 tx & rx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03);
+	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03);
+
+	// switch to higher frequency
+	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
+	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0);
+
+	DBG_PRINT("Done.\n");
+
+	return SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * @brief   Hardware_SwitchFreq
+ *
+ * @param   devSysMonitor_UpdateHardwareStatus(newHwState);
+ * @param   freq
+ *
+ * @return  None.
+ *
+ ******************************************************************************/
+int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
+{
+	int32_t status = 0;
+	uint8_t value = 0;
+	int32_t time_out_cnt = 0;
+
+	switch (freq)
+	{
+	case TX_FREQ_125:
+	{
+		//************************************************************
+		// Setup Tx Frequency-Dependent Syntheisizer Registers
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
+		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
+		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
+		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
+		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
+		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+		status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp)
+		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
+		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
+		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
+
+		//************************************************************
+		// Write Tx Frequency Words
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
+		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
+		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
+		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
+		status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
+
+		//************************************************************
+		// Tx Quadrature Calibration Settings
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
+		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
+		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
+		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
+		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
+		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
+		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
+		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
+
+		break;
+	}
+	case TX_FREQ_126:
+	{
+		//************************************************************
+		// Setup Tx Frequency-Dependent Syntheisizer Registers
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
+		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
+		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
+		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
+		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
+		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
+		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
+		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
+		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
+
+		//************************************************************
+		// Write Tx Frequency Words
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0]
+		status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8]
+		status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16]
+		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
+		status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
+
+		//************************************************************
+		// Tx Quadrature Calibration Settings
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
+		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
+		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
+		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
+		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
+		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
+		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
+		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
+
+		break;
+	}
+	case TX_FREQ_4125:
+	{
+		//************************************************************
+		// Setup Tx Frequency-Dependent Syntheisizer Registers
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
+		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
+		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
+		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
+		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
+		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
+		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
+		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
+		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
+
+		//************************************************************
+		// Write Rx Frequency Words
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
+		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
+		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
+		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
+		status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+		status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting
+
+		//************************************************************
+		// Tx Quadrature Calibration Settings
+		//************************************************************
+		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
+		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
+		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
+		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
+		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
+		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
+		status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index
+		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
+		status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
+
+		break;
+	}
+
+		// Wait for cal to complete (Done when 0x016[4]==0)
+		time_out_cnt = 0;
+		do
+		{
+			status |= ad9361_reg_read(dev, 0x0016, &value);
+			mdelay(1); // Wait 1ms
+			time_out_cnt++;
+		} while ((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
+	}
+
+	return status;
+}
+
+// @ Get AD9361 - 1 temperature (Celsius Degree)
+/**
+ * Read corresponding register to get AD9361 - 1 current temperature.
+ */
+int8_t Hardware_GetAD9361Temp_1(void)
+{
+	int8_t scaleTemp;
+
+	ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x01); // disable aux adc
+	ad9361_reg_read(ad9361_1_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x00); // enable aux adc
+
+	return (int8_t) scaleTemp/1.16;
+}
+
+// @ Get AD9361 - 2 temperature (Celsius Degree)
+/**
+ * Read corresponding register to get AD9361 - 2 current temperature.
+ */
+int8_t Hardware_GetAD9361Temp_2(void)
+{
+	int8_t scaleTemp;
+
+	ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x01); // disable aux adc
+	ad9361_reg_read(ad9361_2_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
+	ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x00); // enable aux adc
+
+	return (int8_t) scaleTemp/1.16;
+}
+
+// @ Determine AD9361 lock state
+/**
+ * Read corresponding register to determine AD9361(both) lock state.
+ */
+uint8_t Hardware_GetAD9361LockStatus(void)
+{
+	uint8_t ret = 0;
+	uint8_t regVal;
+
+	// bbpll
+	ad9361_reg_read(ad9361_1_reg_inst, 0x005E, &regVal); // [D7] is lock indicator
+	ret |= ((regVal & 0x80) == 0x80) ? CLK_AD0_BBPLL_LOCK : 0;
+	ad9361_reg_read(ad9361_2_reg_inst, 0x005E, &regVal); // [D7] is lock indicator
+	ret |= ((regVal & 0x80) == 0x80) ? CLK_AD1_BBPLL_LOCK : 0;
+
+	// rfpll
+	ad9361_reg_read(ad9361_1_reg_inst, 0x0287, &regVal); // [D1] is lock indicator
+	ret |= ((regVal & 0x02) == 0x02) ? CLK_AD0_RFPLL_LOCK : 0;
+	ad9361_reg_read(ad9361_2_reg_inst, 0x0287, &regVal); // [D1] is lock indicator
+	ret |= ((regVal & 0x02) == 0x02) ? CLK_AD1_RFPLL_LOCK : 0;
+
+	return ret;
+}
+
+// @ Determine HMC7044 lock state
+/**
+ * Read corresponding register to determine clock lock state.
+ */
+uint8_t Hardware_GetHMC7044LockStatus(void)
+{
+	uint8_t ret = 0;
+	uint8_t regVal;
+
+	// pll1
+	hmc7044_read(hmc7044_inst, 0x007C, &regVal); // [D5] is lock indicator
+	ret |= ((regVal & 0xE0) != 0x00) ? CLK_SP_PLL0_LOCK : 0;
+
+	// pll2
+	hmc7044_read(hmc7044_inst, 0x007D, &regVal); // [D0] is lock indicator
+	ret |= ((regVal & 0x01) == 0x01) ? CLK_SP_PLL1_LOCK : 0;
+
+	return ret;
+}

df_datalink_sp/src/hwconfig.h

@@ -0,0 +1,32 @@
+/*****************************************************************************/
+/**
+ * Description: hwconfig.h
+ *
+
+ * Date: 2024-02-20 13:19
+ * Last Edit Time: [2024-02-20 13:19]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2023-05-07]: Initial edition.
+ *
+ * Copyright(c) 2024 Beijing Institute of Technology.
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+// Standard
+#include <stdint.h>
+#include "config/app_config.h"
+#include "drivers/rf-transceiver/ad9361_reg/ad9361_reg.h"
+#include "drivers/rf-transceiver/ad9361/ad9361_api.h"
+
+/************************** Function Prototypes ******************************/
+int32_t Hardware_Init(void);
+int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq);
+int8_t Hardware_GetAD9361Temp_1(void);
+int8_t Hardware_GetAD9361Temp_2(void);
+uint8_t Hardware_GetAD9361LockStatus(void);
+uint8_t Hardware_GetHMC7044LockStatus(void);
+
+

df_datalink_sp/src/main.c

@@ -20,19 +20,15 @@
 #include <stdint.h>
 #include <stdbool.h>
 // Xilinx
-#include "sleep.h"
-#include "xil_cache.h"
 #include "xscugic.h"
-#include "xscutimer.h"
-#include "xgpiops.h"
 #include "drivers/platform/xilinx_irq.h"
 #include "drivers/platform/xilinx_timer.h"
-#include "drivers/rf-transceiver/ad9361/ad9361_api.h"
-#include "drivers/axi_core/spi_engine/spi_engine.h"
 // App
 #include "common.h"
 #include "error.h"
 #include "timer.h"
+#include "hwconfig.h"
+#include "system_monitor.h"
 #include "config/app_config.h"
 #include "dev_profile/dev_profile.h"
 #include "systembus/systembus.h"
@@ -46,6 +42,7 @@ void PeriodicPull_Handler(void *callBackRef);
 void ScuTimer_IntrHandler(void *context);
 void Systembus_RxIntrHandler(void *context);
 void Systembus_TxIntrHandler(void *context);
+
 /************************** Constant Definitions *****************************/
 struct callback_desc phy_callback_desc = {
 	.callback = Phy_IntrHandler,
@@ -102,10 +99,10 @@ static PHY_CONFIG phyConfig = {
 	.txBramId = PHY_TXBUFF_BRAM_DEVICE_ID,
 	.rxBramId = PHY_RXBUFF_BRAM_DEVICE_ID,
 	.hwXadcId = PHY_HW_XADC_DEVICE_ID,
-	.get_clk_state = NULL,
+	.get_clk_state = Hardware_GetHMC7044LockStatus,
-	.get_ad_lock_state = NULL,
+	.get_ad_lock_state = Hardware_GetAD9361LockStatus,
-	.get_ad0_temp = NULL,
+	.get_ad0_temp = Hardware_GetAD9361Temp_1,
-	.get_ad1_temp = NULL
+	.get_ad1_temp = Hardware_GetAD9361Temp_2
 };
 
 TMC_CONFIG tmcConfig = {
@@ -126,11 +123,7 @@ static PHY_INST *phyInstPtr;
 static TMC_INST *tmcInstPtr = NULL;
 L2_INST *linkInstPtr;
 
-static struct hmc7044_dev *hmc7044_inst;
+
-static struct ad9361_reg_dev *ad9361_1_reg_inst;
-static struct ad9361_reg_dev *ad9361_2_reg_inst;
-// static struct ad9361_rf_phy *ad9361_phy;
-// static struct ad9361_rf_phy *ad9361_2_phy;
 /****************************************************************************/
 /**
  * This function is responsible for initializing the SCUGIC instance, looking
@@ -374,355 +367,6 @@ void ScuTimer_IntrHandler(void *context)
 	}
 }
 
-/*****************************************************************************/
-/**
- * @brief   Hardware_SwitchFreq
- *
- * @param   devSysMonitor_UpdateHardwareStatus(newHwState);
- * @param   freq
- *
- * @return  None.
- *
- ******************************************************************************/
-int Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
-{
-	int32_t status = 0;
-	uint8_t value = 0;
-	int32_t time_out_cnt = 0;
-
-	switch (freq)
-	{
-	case TX_FREQ_125:
-	{
-		//************************************************************
-		// Setup Tx Frequency-Dependent Syntheisizer Registers
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
-		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
-		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
-		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
-		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
-		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
-		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
-		status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp)
-		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
-		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
-		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
-
-		//************************************************************
-		// Write Tx Frequency Words
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
-		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
-		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
-		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
-		status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
-		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
-
-		//************************************************************
-		// Tx Quadrature Calibration Settings
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
-		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
-		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
-		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
-		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
-		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
-		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
-		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
-
-		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
-		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
-
-		break;
-	}
-	case TX_FREQ_126:
-	{
-		//************************************************************
-		// Setup Tx Frequency-Dependent Syntheisizer Registers
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
-		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
-		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
-		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
-		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
-		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
-		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
-		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
-		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
-		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
-		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
-
-		//************************************************************
-		// Write Tx Frequency Words
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0]
-		status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8]
-		status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16]
-		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
-		status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
-		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
-
-		//************************************************************
-		// Tx Quadrature Calibration Settings
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
-		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
-		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
-		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
-		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
-		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
-		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
-		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
-
-		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
-		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
-
-		break;
-	}
-	case TX_FREQ_4125:
-	{
-		//************************************************************
-		// Setup Tx Frequency-Dependent Syntheisizer Registers
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
-		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
-		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
-		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
-		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
-		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
-		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
-		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
-		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
-		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
-		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
-
-		//************************************************************
-		// Write Rx Frequency Words
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
-		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
-		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
-		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
-		status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
-		status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting
-
-		//************************************************************
-		// Tx Quadrature Calibration Settings
-		//************************************************************
-		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
-		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
-		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
-		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
-		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
-		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
-		status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index
-		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
-		status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used
-
-		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
-		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
-
-		break;
-	}
-
-		// Wait for cal to complete (Done when 0x016[4]==0)
-		time_out_cnt = 0;
-		do
-		{
-			status |= ad9361_reg_read(dev, 0x0016, &value);
-			mdelay(1); // Wait 1ms
-			time_out_cnt++;
-		} while ((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
-	}
-
-	return status;
-}
-
-/*****************************************************************************/
-/**
- * @brief   Hardware_Init
- *
- * @param   none.
- *
- * @return  None.
- *
- ******************************************************************************/
-int Hardware_Init(void)
-{
-	int32_t Status;
-	XGpioPs Gpio;
-	XGpioPs_Config *ConfigPtr;
-	ConfigPtr = XGpioPs_LookupConfig(AD9361_GPIO_DEVICE_ID);
-	Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
-	if (Status != SUCCESS)
-	{
-		return FAILURE;
-	}
-
-	/**********************************************************/
-	/****************** HMC7044 Configuration *****************/
-	/**********************************************************/
-	Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param);
-	if (Status != SUCCESS)
-	{
-		DBG_ERROR("hmc7044_init() error: %" PRId32 "\n", Status);
-		return FAILURE;
-	}
-
-	/**********************************************************/
-	/***************** AD9361-1 Configuration *****************/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, AD9361_GPIO_OUTPUT);
-
-	ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param);
-	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0);
-	ad9361_reg_config(ad9361_1_reg_inst);
-	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1);
-
-	//	Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param);
-	//	if (Status != XST_SUCCESS){
-	//		return XST_FAILURE;
-	//	}else{
-	//		printf("Configurate AD9361 Completely!\n");
-	//	}
-	//	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
-	//	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
-
-	/**********************************************************/
-	/***************** AD9361-2 Configuration *****************/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, AD9361_GPIO_OUTPUT);
-
-	ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param);
-	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0);
-	ad9361_reg_config(ad9361_2_reg_inst);
-	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1);
-
-	//	uint8_t rd_back;
-	//	Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
-	//	Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);
-
-	/**********************************************************/
-	/******* AD9361 Baseband Multichip Synchronization ********/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, AD9361_GPIO_OUTPUT);
-
-	// SYNC BBPLL and DIGITAL SAMPLING CLOCKS
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D);
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
-	mdelay(20);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin
-	mdelay(500);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
-	mdelay(2000);
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin
-	mdelay(500);
-	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
-	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits
-	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08);
-
-	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
-	mdelay(20);
-	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1);
-	mdelay(20);
-	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
-
-	/**********************************************************/
-	/********* AD9361 Multichip Rx Phase Calibration **********/
-	/**********************************************************/
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, AD9361_GPIO_INPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, AD9361_GPIO_OUTPUT);
-	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, AD9361_GPIO_INPUT);
-
-	// switch to lower frequency
-	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
-	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1);
-	mdelay(20);
-
-	// switch rx channel
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30);
-	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30);
-
-	// enable dual ad9361 tx channels
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels
-
-	// switch ad9361 tx channel
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
-	mdelay(20);
-
-	// begin to calibrate the 1st ad9361
-	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
-	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1);
-	mdelay(1);
-	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
-
-	// read calibration status
-	int32_t time_out_cnt = 0;
-	do
-	{
-		mdelay(1); // Wait 1ms
-		time_out_cnt++;
-	} while (((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
-
-	if (time_out_cnt == AD9361_TIMEOUT_TH)
-	{
-		return FAILURE;
-	}
-
-	// begin to calibrate the 2nd ad9361
-	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1);
-	mdelay(1);
-	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0);
-
-	// read calibration status
-	time_out_cnt = 0;
-	do
-	{
-		mdelay(1); // Wait 1ms
-		time_out_cnt++;
-	} while (((XGpioPs_ReadPin(&Gpio, AD9361_2_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
-
-	if (time_out_cnt == AD9361_TIMEOUT_TH)
-	{
-		return FAILURE;
-	}
-
-	// enable single ad9361 tx channels
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
-
-	// switch ad9361 tx & rx channel
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03);
-	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03);
-
-	// switch to higher frequency
-	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
-	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0);
-
-	DBG_PRINT("Done.\n");
-
-	return 0;
-}
-
 /*****************************************************************************/
 /**
  * @brief	Main function, initialize all the device needed, initialize

df_datalink_sp/src/networking/phy_layer/phy_layer.h

@@ -186,8 +186,8 @@ typedef struct
 #ifndef EMULATION
 	uint8_t (*get_clk_state)(void);
 	uint8_t (*get_ad_lock_state)(void);
-	uint8_t (*get_ad0_temp)(void);
+	int8_t (*get_ad0_temp)(void);
-	uint8_t (*get_ad1_temp)(void);
+	int8_t (*get_ad1_temp)(void);
 #endif
 } PHY_CONFIG;