/*****************************************************************************/
/**
 * Description: Global configurations.
 *
 * Date: 2021-04-28 13:19
 * Last Editors: Fan Hao
 * Last Edit Time: [2022-05-23 20:32]
 *
 * Revisions: Rev 0.0
 * History:
 * [2021-04-28]: Initial edition.
 *
 * Copyright(c) 2021 Beijing Institute of Technology.
 * Lab of Communication and Networking
 *
 ******************************************************************************/

#ifndef CONFIG_H_
#define CONFIG_H_

#define XILINX_PLATFORM

#include "xparameters.h"

/******** Software Version ********/
#define _APP_VER	0x00010008

#define _APP_VER_MAIN	((_APP_VER & 0xFF000000) >> 24)
#define _APP_VER_MINOR	((_APP_VER & 0x00FF0000) >> 16)
#define _APP_VER_PATCH	(_APP_VER & 0x0000FFFF)

/*********** Debug Info Level ************/
//  #define _DEBUG_LEVEL 1
// 3 - print all debug info
// 2 - print warnings and errors
// 1 - print only errors
// other - print nothing
#define DATALINK_ENABLE_AUTORECONNECT
#define DATALINK_ENABLE_AUTOTIMESYNC
//#define DATALINK_ENABLE_BERTEST


/************ Hardware Configs ************/
#define CPU_CLK_HZ 			XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
#define GLOBAL_TIMER_CLK_HZ (CPU_CLK_HZ/2)
#define SCU_TIMER_CLK_HZ 	(CPU_CLK_HZ/2)
#define FCLK_CLK0_HZ 		100000000

/********* Zynq Platform Configs **********/
// SCU Timer (for logging)
#define SCUTIMER_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
#define SCUTIMER_INTR_ID XPAR_SCUTIMER_INTR

// Physical Layer Configs
#define PHY_DEVICE_ID 0
#define PHY_BASEADDR	XPAR_PHYC_BASEADDR
#define PHY_BEAM_SET_PRESET
#define PHY_BEAM_FORMING_ENABLE
// -- Antenna Bram Configs
#define PHY_ANTCONFIG_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID
// -- Buffers
#define PHY_TXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
#define PHY_RXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID
// -- Xadc
#define PHY_HW_XADC_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
// -- Interrupt id
#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR

// Time Controller Configs
#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR

// System Bus Configs
//#define SYSBUS_BASE_ADDR	XPAR_SYSTEMBUS_BASEADDR
//#define SYSBUS_TX_INTR_ID	XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
//#define SYSBUS_RX_INTR_ID	XPAR_FABRIC_SYSTEMBUS_RX_DONE_INTR

// Global Timer config
#define GLOBAL_TIMER_DEVICE_ID	XPAR_GLOBAL_TMR_DEVICE_ID
#define GLOBAL_TIMER_BASEADDR	XPAR_GLOBAL_TMR_BASEADDR
#define GLOBAL_TIMER_INTR_ID	XPAR_GLOBAL_TMR_INTR

// INTC configis
#define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID

// Configuration Check
#if defined(PHY_BEAM_SET_PRESET) && !defined(PHY_BEAM_FORMING_ENABLE)
#define PHY_BEAM_FORMING_ENABLE
#warning To impliment beam scan must enable beam forming...
#endif

#if defined(DATALINK_ENABLE_BERTEST)
#if !defined(DATALINK_ENABLE_AUTOTIMESYNC)
	#warning To enbale bit error rate test, auto time-sync should be enabled...
#endif
#endif

#endif