102 lines
3.0 KiB
C
102 lines
3.0 KiB
C
/*****************************************************************************/
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/**
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* Description: Global configurations.
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*
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* Date: 2021-04-28 13:19
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* Last Editors: Fan Hao
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* Last Edit Time: [2022-05-23 20:32]
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*
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* Revisions: Rev 0.0
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* History:
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* [2021-04-28]: Initial edition.
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*
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* Copyright(c) 2021 Beijing Institute of Technology.
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* Lab of Communication and Networking
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*
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******************************************************************************/
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#ifndef CONFIG_H_
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#define CONFIG_H_
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#define XILINX_PLATFORM
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#include "xparameters.h"
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/******** Software Version ********/
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#define _APP_VER 0x00010008
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#define _APP_VER_MAIN ((_APP_VER & 0xFF000000) >> 24)
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#define _APP_VER_MINOR ((_APP_VER & 0x00FF0000) >> 16)
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#define _APP_VER_PATCH (_APP_VER & 0x0000FFFF)
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/*********** Debug Info Level ************/
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// #define _DEBUG_LEVEL 1
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// 3 - print all debug info
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// 2 - print warnings and errors
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// 1 - print only errors
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// other - print nothing
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#define APP_EMULATE_DATA
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#define DATALINK_ENABLE_AUTORECONNECT
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#define DATALINK_ENABLE_AUTOTIMESYNC
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//#define DATALINK_ENABLE_BERTEST
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/************ Hardware Configs ************/
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#define CPU_CLK_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
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#define GLOBAL_TIMER_CLK_HZ (CPU_CLK_HZ/2)
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#define SCU_TIMER_CLK_HZ (CPU_CLK_HZ/2)
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#define FCLK_CLK0_HZ 100000000
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/********* Zynq Platform Configs **********/
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// SCU Timer (for logging)
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#define SCUTIMER_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
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#define SCUTIMER_INTR_ID XPAR_SCUTIMER_INTR
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// Physical Layer Configs
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#define PHY_DEVICE_ID 0
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#define PHY_BASEADDR XPAR_PHYC_BASEADDR
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#define PHY_BEAM_SET_PRESET
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#define PHY_BEAM_FORMING_ENABLE
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// -- Antenna Bram Configs
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#define PHY_ANTCONFIG_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID
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// -- Buffers
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#define PHY_TXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
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#define PHY_RXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID
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// -- Xadc
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#define PHY_HW_XADC_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
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// -- Interrupt id
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#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
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#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
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// Time Controller Configs
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#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR
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// System Bus Configs
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#define MPC_BRAM_ID XPAR_MPC_BRAM_INTERFACE_MPC_BRAM_CTRL_DEVICE_ID
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#define MPC_GPIO_ID XPAR_MPC_GPIO_DEVICE_ID
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#define MPC_TX_INTR_ID XPAR_FABRIC_MPC_TX_IRQ_INTR
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#define MPC_RX_INTR_ID XPAR_FABRIC_MPC_RX_IRQ_INTR
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// Global Timer config
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#define GLOBAL_TIMER_DEVICE_ID XPAR_GLOBAL_TMR_DEVICE_ID
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#define GLOBAL_TIMER_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
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#define GLOBAL_TIMER_INTR_ID XPAR_GLOBAL_TMR_INTR
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// INTC configis
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#define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
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// Configuration Check
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#if defined(PHY_BEAM_SET_PRESET) && !defined(PHY_BEAM_FORMING_ENABLE)
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#define PHY_BEAM_FORMING_ENABLE
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#warning To impliment beam scan must enable beam forming...
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#endif
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#if defined(DATALINK_ENABLE_BERTEST)
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#if !defined(DATALINK_ENABLE_AUTOTIMESYNC)
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#warning To enbale bit error rate test, auto time-sync should be enabled...
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#endif
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#endif
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#endif
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