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Initial version.

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Gatsby Van
2023-12-20 00:11:03 +08:00
commit 416bd53733
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datalink814_ge/src/mpc/mpc_ctrl.c
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/*****************************************************************************/
/**
* Description: A brief description of this file
*
* Date: 2022-01-19 00:54
* LastEditors: Fan Hao
* LastEditTime: 2022-03-28 20:24
* Revisions: Rev 0.0
* History:
* [2022-01-19]: Initial version.
* [2022-03-28]: Add general information print function.
*
* Copyright(c) 2022 Beijing Institute of Technology.
* Lab of Communication and Networking
*
******************************************************************************/
#include <inttypes.h>
#include <string.h>
#include "mpc_ctrl.h"
#include "mpc_msg_def.h"
#include "../error.h"
#include "../config/app_config.h"
#include "../bit_array/bit_array.h"
#include "../util/util.h"
#include "../linklayer/linklayer814.h"
#include "../linklayer/msg_def.h"
#include "../linklayer/node_list.h"
#include "../linklayer/rtt.h"
#ifdef _MPC_CTRL
#define STATE_STROAGE_BUFF_MAX 32768 // 32K Bytes
static int32_t MPC_InsertChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t chunk);
static int32_t MPC_GetChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t* chunk);
#ifdef _MPC_UART
#include <frame_uart.h>
//...
#endif //_MPC_CTRL
#ifdef _MPC_PCIE
#include "../phy_ctrl/phy_ctrl.h"
extern L2_CONFIG l2Config;
extern PHY_INST* phyInstPtr;
extern L2_INST* linkInstPtr;
MPC_INST* mpcInstPtr = NULL;
MPC_RECORD* mpcRecord = NULL;
BIT_ARRAY* mpcTxMsgBuff = NULL;
BIT_ARRAY* mpcRxMsgBuff = NULL;
static MPC_MSG_HEADER mpcHeader = {
.head = 0x5302,
};
/*****************************************************************************/
/**
* @brief Insert a data chunk to a bit array.
*
* @param bitarr pointer to target bit array.
* offset offset of insert start position.
* numBit number of insert bits
* chunk 64 bit data chunk, contains the data should be stored
* in LSB style.
*
* @return FAILURE insert operation exceed bit array size.
* SUCCESS
*
******************************************************************************/
static int32_t MPC_InsertChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t chunk){
ASSERT(bitarr != NULL);
if(bitarr->num_of_bits < offset+numBit){
return FAILURE;
}
bit_array_set_wordn(bitarr, offset, chunk, numBit);
return SUCCESS;
}
/*****************************************************************************/
/**
* @brief Get a data chunk to a bit array.
*
* @param bitarr pointer to target bit array.
* offset offset of data chunk start position.
* numBit number of data chunk
* chunk pointer to a 64 bit data chunk container, data will be stored
* in LSB style.
*
* @return FAILURE read operation exceed bit array size.
* SUCCESS
*
******************************************************************************/
static int32_t MPC_GetChunk(BIT_ARRAY* bitarr, uint32_t offset, uint32_t numBit, uint64_t* chunk){
ASSERT(bitarr != NULL);
if(bitarr->num_of_bits < offset+numBit || numBit > 64){
return FAILURE;
}
*chunk = bit_array_get_wordn(bitarr, offset, numBit);
return SUCCESS;
}
static uint32_t MPC_GetMsgLen(MPC_MSG_TYPE type){
switch(type){
case MPC_MSG_TEST:
return (MPC_MSG_TEST_LEN/8);
case MPC_MSG_STATE:
return (MPC_MSG_STATE_LEN/8);
default:
return MPC_MSG_LEN_NONE;
}
}
/*****************************************************************************/
/**
* @brief Initialize mpc instance, apply customize configurations.
*
* @param instPtr pointer mpc descriptor.
* configPtr pointer to mpc configurations.
*
* @return SUCCESS MPC init successfully.
* error code.
*
******************************************************************************/
int MPC_Init(MPC_INST** instPtr, MPC_CONFIG* configPtr){
ASSERT(instPtr != NULL);
ASSERT(configPtr != NULL);
int Status = SUCCESS;
XBram_Config *bramConfigPtr;
(*instPtr) = (MPC_INST*)malloc(sizeof(MPC_INST));
if((*instPtr) == NULL){
Status = EALLOC;
goto init_failed;
}
(*instPtr)->configs.bramDevId = configPtr->bramDevId;
(*instPtr)->configs.msgLenMax = configPtr->msgLenMax;
bramConfigPtr = XBram_LookupConfig(configPtr->bramDevId);
if (bramConfigPtr == NULL) {
Status = EDINVAL;
goto init_failed;
}
Status = XBram_CfgInitialize(&((*instPtr)->pcieBram), bramConfigPtr,
bramConfigPtr->CtrlBaseAddress);
if (Status != SUCCESS) {
goto init_failed;
}
/* Execute the BRAM driver selftest. */
Status = XBram_SelfTest(&((*instPtr)->pcieBram), 0);
if (Status != SUCCESS) {
goto init_failed;
}
(*instPtr)->txBaseAddr = (uint8_t*)((*instPtr)->pcieBram.Config.MemBaseAddress);
(*instPtr)->rxBaseAddr = (uint8_t*)((*instPtr)->pcieBram.Config.MemBaseAddress);
mpcRecord = (MPC_RECORD*) malloc(sizeof(MPC_RECORD));
if(mpcRecord == NULL){
Status = EALLOC;
goto init_failed;
}
memset(mpcRecord, 0x00, sizeof(MPC_RECORD));
mpcTxMsgBuff = bit_array_create(STATE_STROAGE_BUFF_MAX*8);
if(mpcTxMsgBuff == NULL){
goto init_failed;
}
mpcRxMsgBuff = bit_array_create(MPC_MSG_LEN_MAX);
if(mpcRxMsgBuff == NULL){
goto init_failed;
}
return Status;
init_failed:
free(*instPtr);
free(mpcRecord);
free(mpcTxMsgBuff);
free(mpcRxMsgBuff);
return Status;
}
/*****************************************************************************/
/**
* @brief Handle a mpc message in rx buffer.
*
* @param instPtr pointer mpc descriptor.
*
* @return SUCCESS MPC handler runs successfully.
* error code.
*
******************************************************************************/
int MPC_MsgHandler(MPC_INST* instPtr){
ASSERT(instPtr != NULL);
MPC_MSG_HEADER* pktHeader = (MPC_MSG_HEADER*)(instPtr->rxBaseAddr);
// instPtr->txBaseAddr + MPC_MSG_HEAD_LEN;
uint64_t dataChunk = 0;
switch(pktHeader->type){
case MPC_MSG_TEST_CODE:
memcpy(mpcRxMsgBuff->words,
instPtr->rxBaseAddr + (MPC_MSG_HEAD_LEN/8),
DIV_ROUND_UP(MPC_MSG_TEST_LEN,8));
MPC_GetChunk(mpcRxMsgBuff, TEST_REQ_CMD_OFFSET, TEST_REQ_CMD_LEN, &dataChunk);
if((uint8_t)dataChunk == TEST_REQ_CMD_START){
MPC_GetChunk(mpcRxMsgBuff, TEST_MODE_SET_OFFSET, TEST_MODE_SET_LEN, &dataChunk);
// FIXME
if((uint8_t)dataChunk == TEST_MODE_HEAD){
l2Config.myType = HEAD_NODE;
l2Config.myId = 1;
}
else{
l2Config.myType = MEMBER_NODE;
l2Config.myId = 2;
}
MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_FPGA_ST_OFFSET, TEST_REQ_FPGA_ST_LEN, 0x01);
MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_AD_ST_OFFSET, TEST_REQ_AD_ST_LEN, 0x01);
MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_RF_ST_OFFSET, TEST_REQ_RF_ST_LEN, 0x01);
MPC_SendMsg(instPtr, MPC_MSG_TEST, (uint8_t*)mpcTxMsgBuff->words, MPC_MSG_TEST_LEN);
Linklayer_Reconfig(linkInstPtr, &l2Config);
Linklayer_Start(linkInstPtr);
}
else if((uint8_t)dataChunk == TEST_REQ_CMD_END){
MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_FPGA_ST_OFFSET, TEST_REQ_FPGA_ST_LEN, 0x00);
MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_AD_ST_OFFSET, TEST_REQ_AD_ST_LEN, 0x00);
MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_RF_ST_OFFSET, TEST_REQ_RF_ST_LEN, 0x00);
MPC_SendMsg(instPtr, MPC_MSG_TEST, (uint8_t*)mpcTxMsgBuff->words, MPC_MSG_TEST_LEN);
memset(mpcRecord, 0x00, sizeof(MPC_RECORD));
memset((uint8_t*)mpcTxMsgBuff->words,0x00,STATE_STROAGE_BUFF_MAX);
Linklayer_Halt(linkInstPtr);
MPC_SendMsg(instPtr, MPC_MSG_STATE, (uint8_t*)mpcTxMsgBuff->words, STATE_STROAGE_BUFF_MAX);
Phy_SetupNextSlot(phyInstPtr, PHY_TOR_SUSPEND, L1_200KBPS_5MS_FRAME, NULL); // any frame type is okay
}
else{
DBG_WARNING("Unexpected self-test command.\n");
}
break;
case MPC_MSG_TSYNC_CODE:
memcpy(mpcRxMsgBuff->words,
instPtr->rxBaseAddr + ((MPC_MSG_HEAD_LEN/8)/2),
DIV_ROUND_UP(MPC_MSG_TSYNC_LEN,8));
//FIXME:
// MPC_GetChunk(mpcRxMsgBuff, RTT_ADJ_OFFSET, RTT_ADJ_LEN, &dataChunk);
// rttRecord->rttAdj = (double)dataChunk ;
// MPC_GetChunk(mpcRxMsgBuff, TSYNC_ADJ_OFFSET, TSYNC_ADJ_LEN, &dataChunk);
// double tsyncAdj = (double)dataChunk * 0.192;
//FIXME:
// PhyWrite(TSYNC_PULS_ADJ, (uint32_t)tsyncAdj);
// MPC_GetChunk(mpcRxMsgBuff, DOPPLER_OFFSET, DOPPLER_LEN, &dataChunk);
// double dopplerAdj = (double)((dataChunk << 32)/192000000) ;
// PhyWrite(DOPPLER_ADJ, (uint32_t)dopplerAdj);
break;
default:
DBG_ERROR("Unknown message type code: %04X.\n\r", pktHeader->type);
return EPARAM;
}
return SUCCESS;
}
/*****************************************************************************/
/**
* @brief Encapsulate upload a packet to master pc, upload content defined
* in the mpc message protocols.
*
* @param instPtr pointer mpc descriptor.
* type packet type
* buffer pinter to send packet buffer.
* dlen length of data need to be sent.
*
* @return SUCCESS MPC handler runs successfully.
* error code.
*
******************************************************************************/
int MPC_SendMsg(MPC_INST* instPtr, MPC_MSG_TYPE type, uint8_t* buffer, uint32_t dlen){
ASSERT(instPtr != NULL);
if(buffer == NULL ||
dlen >= instPtr->configs.msgLenMax ||
(type <= MPC_MSG_NONE || type > MPC_MSG_STATE)){
return EPARAM;
}
if(instPtr->pcieBram.IsReady == false){
return EDINVAL;
}
int Status = SUCCESS;
switch(type){
case MPC_MSG_TEST:
mpcHeader.type = MPC_MSG_TEST_CODE;
break;
case MPC_MSG_STATE:
mpcHeader.type = MPC_MSG_STATE_CODE;
break;
default:
DBG_ERROR("Unknown mpc message type: %d.\n", type);
break;
}
memcpy(instPtr->txBaseAddr, &mpcHeader, MPC_MSG_HEAD_LEN/8);
memcpy(instPtr->txBaseAddr + (MPC_MSG_HEAD_LEN/8), buffer, dlen);
MPC_PCIESentStart();
return Status;
}
/*****************************************************************************/
/**
* @brief Upload current state to master pc.(content detail defined in mpc
* mesage protocol)
*
* @param instPtr pointer mpc descriptor.
*
* @return SUCCESS MPC handler runs successfully.
* error code.
*
******************************************************************************/
int MPC_StateUpload(MPC_INST* instPtr , uint8_t* mgmtBuffer , uint32_t mgmtMsgCnt ,
uint8_t* svcBuffer , uint32_t svcMsgCnt , MGMT_MSG_RECORD* mgmtMsg){
ASSERT(instPtr != NULL);
int32_t Status = SUCCESS;
uint64_t dataChunk = 0;
if(instPtr->pcieBram.IsReady == false){
return EDINVAL;
}
// Stage
switch (linkInstPtr->mainState) {
case INIT_STATE :
dataChunk = STATE_STAGE_SETUP;
break;
case INTRA_SEEK_STATE:
dataChunk = STATE_STAGE_RTNE;
break;
case NORMAL_STATE :
dataChunk = STATE_STAGE_SVC;
break;
default:
return EUNEXP;
}
MPC_InsertChunk(mpcTxMsgBuff, STATE_STAGE_OFFSET, STATE_STAGE_LEN, dataChunk);
// Net setup time
dataChunk = (L2_GetNextFrameNum(linkInstPtr) - linkInstPtr->netStartTime) * 1000 + L2_GetNextSlotNum(linkInstPtr) * 5 ;
MPC_InsertChunk(mpcTxMsgBuff, STATE_SETUP_TIME_OFFSET, STATE_SETUP_TIME_LEN, dataChunk);
// number of nodes
dataChunk = GetNodeNum(linkInstPtr->nodeList);
MPC_InsertChunk(mpcTxMsgBuff, STATE_NUM_NODE_OFFSET, STATE_NUM_NODE_LEN, dataChunk);
// frame 1 counter
dataChunk = mpcRecord->frame1Cnt;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_1_CNT_OFFSET, STATE_FRAME_1_CNT_LEN, dataChunk);
// frame 2 counter
dataChunk = mpcRecord->frame2Cnt;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_2_CNT_OFFSET, STATE_FRAME_2_CNT_LEN, dataChunk);
// frame 3 counter
dataChunk = mpcRecord->frame3Cnt;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_3_CNT_OFFSET, STATE_FRAME_3_CNT_LEN, dataChunk);
// frame 4 counter
dataChunk = mpcRecord->frame4Cnt;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_4_CNT_OFFSET, STATE_FRAME_4_CNT_LEN, dataChunk);
// frame 5 counter
dataChunk = mpcRecord->frame5Cnt;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_5_CNT_OFFSET, STATE_FRAME_5_CNT_LEN, dataChunk);
// frame 6 counter
dataChunk = mpcRecord->frame6Cnt;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_6_CNT_OFFSET, STATE_FRAME_6_CNT_LEN, dataChunk);
// frame 7 counter
dataChunk = mpcRecord->frame7Cnt;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_7_CNT_OFFSET, STATE_FRAME_7_CNT_LEN, dataChunk);
// frame 8 counter
dataChunk = mpcRecord->frame8Cnt;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_8_CNT_OFFSET, STATE_FRAME_8_CNT_LEN, dataChunk);
// frame 1 sent counter
dataChunk = mpcRecord->frame1Sent;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_1_SENT_OFFSET, STATE_FRAME_1_SENT_LEN, dataChunk);
// frame 2 sent counter
dataChunk = mpcRecord->frame2Sent;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_2_SENT_OFFSET, STATE_FRAME_2_SENT_LEN, dataChunk);
// frame 3 sent counter
dataChunk = mpcRecord->frame3Sent;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_3_SENT_OFFSET, STATE_FRAME_3_SENT_LEN, dataChunk);
// frame 4 sent counter
dataChunk = mpcRecord->frame4Sent;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_4_SENT_OFFSET, STATE_FRAME_4_SENT_LEN, dataChunk);
// frame 5 sent counter
dataChunk = mpcRecord->frame5Sent;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_5_SENT_OFFSET, STATE_FRAME_5_SENT_LEN, dataChunk);
// frame 6 sent counter
dataChunk = mpcRecord->frame6Sent;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_6_SENT_OFFSET, STATE_FRAME_6_SENT_LEN, dataChunk);
// frame 7 sent counter
dataChunk = mpcRecord->frame7Sent;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_7_SENT_OFFSET, STATE_FRAME_7_SENT_LEN, dataChunk);
// frame 8 sent counter
dataChunk = mpcRecord->frame8Sent;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_8_SENT_OFFSET, STATE_FRAME_8_SENT_LEN, dataChunk);
// frame 1 received counter
dataChunk = mpcRecord->frame1Recv;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_1_RECV_OFFSET, STATE_FRAME_1_RECV_LEN, dataChunk);
// frame 2 received counter
dataChunk = mpcRecord->frame2Recv;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_2_RECV_OFFSET, STATE_FRAME_2_RECV_LEN, dataChunk);
// frame 3 received counter
dataChunk = mpcRecord->frame3Recv;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_3_RECV_OFFSET, STATE_FRAME_3_RECV_LEN, dataChunk);
// frame 4 received counter
dataChunk = mpcRecord->frame4Recv;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_4_RECV_OFFSET, STATE_FRAME_4_RECV_LEN, dataChunk);
// frame 5 received counter
dataChunk = mpcRecord->frame5Recv;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_5_RECV_OFFSET, STATE_FRAME_5_RECV_LEN, dataChunk);
// frame 6 received counter
dataChunk = mpcRecord->frame6Recv;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_6_RECV_OFFSET, STATE_FRAME_6_RECV_LEN, dataChunk);
// frame 7 received counter
dataChunk = mpcRecord->frame7Recv;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_7_RECV_OFFSET, STATE_FRAME_7_RECV_LEN, dataChunk);
// frame 8 received counter
dataChunk = mpcRecord->frame8Recv;
MPC_InsertChunk(mpcTxMsgBuff, STATE_FRAME_8_RECV_OFFSET, STATE_FRAME_8_RECV_LEN, dataChunk);
// Trajectory pos X
dataChunk = mgmtMsg->Longitude % 1000 ;
MPC_InsertChunk(mpcTxMsgBuff, STATE_TRAJ_X_OFFSET, STATE_TRAJ_X_LEN, dataChunk);
// Trajectory pos Y
dataChunk = mgmtMsg->Latitude % 1000 ;
MPC_InsertChunk(mpcTxMsgBuff, STATE_TRAJ_Y_OFFSET, STATE_TRAJ_Y_LEN, dataChunk);
// Trajectory alpha
dataChunk = 45;
MPC_InsertChunk(mpcTxMsgBuff, STATE_TRAJ_ALPHA_OFFSET, STATE_TRAJ_ALPHA_LEN, dataChunk);
// TODO : Currently DJ is node 1 , only Byte 1 is activate , others is useless
// Topo node 1
dataChunk = BIT(linkInstPtr->myInfo.nodeId - 1);
if (GetNodeNum(linkInstPtr->nodeList) > 1 ) {
for(int i = 1; i <= linkInstPtr->config.netScale; i++){
if (IsNodeInList(linkInstPtr->nodeList, i)) {
dataChunk |= BIT(i-1);
}
}
}
MPC_InsertChunk(mpcTxMsgBuff, STATE_TOPO_1_OFFSET, STATE_TOPO_1_LEN, dataChunk);
// Topo node 2
dataChunk = 0x00;
MPC_InsertChunk(mpcTxMsgBuff, STATE_TOPO_2_OFFSET, STATE_TOPO_2_LEN, dataChunk);
// Topo node 3
dataChunk = 0x00;
MPC_InsertChunk(mpcTxMsgBuff, STATE_TOPO_3_OFFSET, STATE_TOPO_3_LEN, dataChunk);
// Topo node 4
dataChunk = 0x00;
MPC_InsertChunk(mpcTxMsgBuff, STATE_TOPO_4_OFFSET, STATE_TOPO_4_LEN, dataChunk);
// Mgmt message Number
dataChunk = mgmtMsgCnt;
MPC_InsertChunk(mpcTxMsgBuff, MGMT_MSG_NUM_OFFSET, MGMT_MSG_NUM_LEN, dataChunk);
// Svc message Number
dataChunk = svcMsgCnt;
MPC_InsertChunk(mpcTxMsgBuff, SVC_MSG_NUM_OFFSET, SVC_MSG_NUM_LEN, dataChunk);
// Copy msg data
size_t svcLen = mgmtMsgCnt*(72/8*6);
size_t mgmtLen = svcMsgCnt*(2040/8);
memcpy(((uint8_t*)mpcTxMsgBuff->words) + MPC_MSG_STATE_LEN/8, mgmtBuffer, svcLen);
memcpy(((uint8_t*)mpcTxMsgBuff->words) + MPC_MSG_STATE_LEN/8 + mgmtMsgCnt*(72/8*6),
svcBuffer, mgmtLen);
Status = MPC_SendMsg(instPtr, MPC_MSG_STATE,(uint8_t*)mpcTxMsgBuff->words, MPC_MSG_STATE_LEN/8 + svcLen + mgmtLen);
// Status = MPC_SendMsg(instPtr, MPC_MSG_STATE,(uint8_t*)stateMsg->words, MPC_MSG_STATE_LEN/8);
return Status;
}
#endif //_MPC_PCIE
#endif //_MPC_CTRL
datalink814_ge/src/mpc/mpc_ctrl.h
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/*****************************************************************************/
/**
* Description: A brief description of this file
*
* Date: 2022-01-19 00:54
* LastEditors: Fan Hao
* LastEditTime: 2022-03-28 20:24
* Revisions: Rev 0.0
* History:
* [2022-01-19]: Initial version.
* [2022-03-28]: Add general information print function.
*
* Copyright(c) 2022 Beijing Institute of Technology.
* Lab of Communication and Networking
*
******************************************************************************/
#ifndef MPC_CTRL_H_
#define MPC_CTRL_H_
#include <inttypes.h>
#include "../config/app_config.h"
#ifdef _MPC_CTRL
#ifdef _MPC_UART
//...
#endif //_MPC_UART
#ifdef _MPC_PCIE
#include "xbram.h"
#include "../phy_ctrl/phy_ctrl.h"
#include "../linklayer/linklayer814.h"
typedef struct {
const uint16_t head;
uint16_t type;
uint8_t reserve[4];
} MPC_MSG_HEADER;
typedef struct{
uint32_t bramDevId;
uint32_t msgLenMax;
} MPC_CONFIG;
typedef struct{
MPC_CONFIG configs;
XBram pcieBram;
uint8_t* txBaseAddr;
uint8_t* rxBaseAddr;
} MPC_INST;
typedef enum{
MPC_MSG_NONE = 0,
MPC_MSG_TEST = 1,
MPC_MSG_STATE = 2,
} MPC_MSG_TYPE;
// FIXME: Simplify this part.
typedef struct {
uint8_t frame1Cnt;
uint8_t frame2Cnt;
uint8_t frame3Cnt;
uint8_t frame4Cnt;
uint8_t frame5Cnt;
uint8_t frame6Cnt;
uint8_t frame7Cnt;
uint8_t frame8Cnt;
uint8_t frame1CntLast;
uint8_t frame2CntLast;
uint8_t frame3CntLast;
uint8_t frame4CntLast;
uint8_t frame5CntLast;
uint8_t frame6CntLast;
uint8_t frame7CntLast;
uint8_t frame8CntLast;
uint16_t frame1Sent;
uint16_t frame2Sent;
uint16_t frame3Sent;
uint16_t frame4Sent;
uint16_t frame5Sent;
uint16_t frame6Sent;
uint16_t frame7Sent;
uint16_t frame8Sent;
uint16_t frame1Recv;
uint16_t frame2Recv;
uint16_t frame3Recv;
uint16_t frame4Recv;
uint16_t frame5Recv;
uint16_t frame6Recv;
uint16_t frame7Recv;
uint16_t frame8Recv;
} MPC_RECORD;
extern void MPC_PCIESentStart();
extern MPC_RECORD* mpcRecord;
extern MPC_INST* mpcInstPtr;
int MPC_Init(MPC_INST** instPtr, MPC_CONFIG* configPtr);
int MPC_MsgHandler(MPC_INST* instPtr);
int MPC_StateUpload(MPC_INST* instPtr , uint8_t* mgmtBuffer , uint32_t mgmtMsgCnt
, uint8_t* svcBuffer , uint32_t svcMsgCnt , MGMT_MSG_RECORD* mgmtmsg);
int MPC_SendMsg(MPC_INST* instPtr, MPC_MSG_TYPE type, uint8_t* buffer, uint32_t dlen);
#endif //_MPC_PCIE
#endif //_MPC_CTRL
#endif //MPC_CTRL_H_
datalink814_ge/src/mpc/mpc_msg_def.h
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/*
* mpc_msg_def.h
*
* Created on: Sep 19, 2022
*/
#ifndef _MPC_MSG_DEF
#define _MPC_MSG_DEF
#define MPC_MSG_HEAD_LEN 64 //bit
#define MPC_MSG_LEN_MAX 1024 //bit
#define MPC_MSG_LEN_NONE UINT32_MAX
// ** Self Test Message ** //
// Type code
#define MPC_MSG_TEST_CODE 0x00AA
#define MPC_MSG_TEST_LEN 128 // bit
// data segment - self test request message.
#define TEST_REQ_CMD_OFFSET 0
#define TEST_REQ_CMD_LEN 8
#define TEST_REQ_CMD_START 0xAA
#define TEST_REQ_CMD_END 0xFF
#define TEST_MODE_SET_OFFSET 8
#define TEST_MODE_SET_LEN 8
#define TEST_MODE_HEAD 0x01
#define TEST_MODE_MEMBER 0x02
// data segment - self test response message.
#define TEST_REQ_FPGA_ST_OFFSET 0
#define TEST_REQ_FPGA_ST_LEN 8
#define TEST_REQ_AD_ST_OFFSET 8
#define TEST_REQ_AD_ST_LEN 8
#define TEST_REQ_RF_ST_OFFSET 16
#define TEST_REQ_RF_ST_LEN 8
// ** State Report Message ** //
// Type code
#define MPC_MSG_STATE_CODE 0x00FF
#define MPC_MSG_STATE_LEN 544 // bit
// data segment
#define STATE_STAGE_OFFSET 0
#define STATE_STAGE_LEN 8
#define STATE_STAGE_SETUP 0x51
#define STATE_STAGE_RTNE 0x52
#define STATE_STAGE_SVC 0x53
#define STATE_SETUP_TIME_OFFSET 8
#define STATE_SETUP_TIME_LEN 32
#define STATE_NUM_NODE_OFFSET 40
#define STATE_NUM_NODE_LEN 8
#define STATE_FRAME_1_CNT_OFFSET 48
#define STATE_FRAME_1_CNT_LEN 8
#define STATE_FRAME_2_CNT_OFFSET 56
#define STATE_FRAME_2_CNT_LEN 8
#define STATE_FRAME_3_CNT_OFFSET 64
#define STATE_FRAME_3_CNT_LEN 8
#define STATE_FRAME_4_CNT_OFFSET 72
#define STATE_FRAME_4_CNT_LEN 8
#define STATE_FRAME_5_CNT_OFFSET 80
#define STATE_FRAME_5_CNT_LEN 8
#define STATE_FRAME_6_CNT_OFFSET 88
#define STATE_FRAME_6_CNT_LEN 8
#define STATE_FRAME_7_CNT_OFFSET 96
#define STATE_FRAME_7_CNT_LEN 8
#define STATE_FRAME_8_CNT_OFFSET 104
#define STATE_FRAME_8_CNT_LEN 8
#define STATE_FRAME_1_SENT_OFFSET 112
#define STATE_FRAME_1_SENT_LEN 16
#define STATE_FRAME_2_SENT_OFFSET 128
#define STATE_FRAME_2_SENT_LEN 16
#define STATE_FRAME_3_SENT_OFFSET 144
#define STATE_FRAME_3_SENT_LEN 16
#define STATE_FRAME_4_SENT_OFFSET 160
#define STATE_FRAME_4_SENT_LEN 16
#define STATE_FRAME_5_SENT_OFFSET 176
#define STATE_FRAME_5_SENT_LEN 16
#define STATE_FRAME_6_SENT_OFFSET 192
#define STATE_FRAME_6_SENT_LEN 16
#define STATE_FRAME_7_SENT_OFFSET 208
#define STATE_FRAME_7_SENT_LEN 16
#define STATE_FRAME_8_SENT_OFFSET 224
#define STATE_FRAME_8_SENT_LEN 16
#define STATE_FRAME_1_RECV_OFFSET 240
#define STATE_FRAME_1_RECV_LEN 16
#define STATE_FRAME_2_RECV_OFFSET 256
#define STATE_FRAME_2_RECV_LEN 16
#define STATE_FRAME_3_RECV_OFFSET 272
#define STATE_FRAME_3_RECV_LEN 16
#define STATE_FRAME_4_RECV_OFFSET 288
#define STATE_FRAME_4_RECV_LEN 16
#define STATE_FRAME_5_RECV_OFFSET 304
#define STATE_FRAME_5_RECV_LEN 16
#define STATE_FRAME_6_RECV_OFFSET 320
#define STATE_FRAME_6_RECV_LEN 16
#define STATE_FRAME_7_RECV_OFFSET 336
#define STATE_FRAME_7_RECV_LEN 16
#define STATE_FRAME_8_RECV_OFFSET 352
#define STATE_FRAME_8_RECV_LEN 16
#define STATE_TRAJ_X_OFFSET 368
#define STATE_TRAJ_X_LEN 32
#define STATE_TRAJ_Y_OFFSET 400
#define STATE_TRAJ_Y_LEN 32
#define STATE_TRAJ_ALPHA_OFFSET 432
#define STATE_TRAJ_ALPHA_LEN 64
#define STATE_TOPO_1_OFFSET 496
#define STATE_TOPO_1_LEN 8
#define STATE_TOPO_2_OFFSET 504
#define STATE_TOPO_2_LEN 8
#define STATE_TOPO_3_OFFSET 512
#define STATE_TOPO_3_LEN 8
#define STATE_TOPO_4_OFFSET 520
#define STATE_TOPO_4_LEN 8
#define MGMT_MSG_NUM_OFFSET 528
#define MGMT_MSG_NUM_LEN 8
#define SVC_MSG_NUM_OFFSET 536
#define SVC_MSG_NUM_LEN 8
#define STORE_ADDR_START_OFFSET 544
// ** Time SyncAdj Message ** //
// Type code
#define MPC_MSG_TSYNC_CODE 0x00FF
#define MPC_MSG_TSYNC_LEN 128 // bit
// data segment - self test response message.
#define RTT_ADJ_OFFSET 0
#define RTT_ADJ_LEN 32
#define TSYNC_ADJ_OFFSET 32
#define TSYNC_ADJ_LEN 32
#define DOPPLER_OFFSET 64
#define DOPPLER_LEN 32
#endif //_MPC_MSG_DEF