Initial version.

2023-12-20 00:11:03 +08:00
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+/*****************************************************************************/
+/**
+ * Description: A brief description of this file
+ * 
+ * Date: 2022-01-19 00:54
+ * LastEditors: Fan Hao
+ * LastEditTime: 2022-03-28 20:24
+ * Revisions: Rev 0.0
+ * History: 
+ * [2022-01-19]: Initial version.
+ * [2022-03-28]: Add general information print function.
+ * 
+ * Copyright(c) 2022 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ * 
+ ******************************************************************************/
+
+#ifndef MPC_CTRL_H_
+#define MPC_CTRL_H_
+
+#include <inttypes.h>
+#include "../config/app_config.h"
+#ifdef _MPC_CTRL
+#ifdef _MPC_UART
+//...
+#endif //_MPC_UART
+
+#ifdef _MPC_PCIE
+#include "xbram.h"
+#include "../phy_ctrl/phy_ctrl.h"
+#include "../linklayer/linklayer814.h"
+
+typedef struct {
+	const uint16_t head;
+	uint16_t type;
+	uint8_t reserve[4];
+} MPC_MSG_HEADER;
+
+typedef struct{
+	uint32_t bramDevId;
+	uint32_t msgLenMax;
+} MPC_CONFIG;
+
+typedef struct{
+	MPC_CONFIG configs;
+	XBram pcieBram;
+	uint8_t* txBaseAddr;
+	uint8_t* rxBaseAddr;
+} MPC_INST;
+
+typedef enum{
+	MPC_MSG_NONE = 0,
+	MPC_MSG_TEST = 1,
+	MPC_MSG_STATE = 2,
+} MPC_MSG_TYPE;
+
+// FIXME: Simplify this part.
+typedef struct {
+	uint8_t frame1Cnt;
+	uint8_t frame2Cnt;
+	uint8_t frame3Cnt;
+	uint8_t frame4Cnt;
+	uint8_t frame5Cnt;
+	uint8_t frame6Cnt;
+	uint8_t frame7Cnt;
+	uint8_t frame8Cnt;
+	uint8_t frame1CntLast;
+	uint8_t frame2CntLast;
+	uint8_t frame3CntLast;
+	uint8_t frame4CntLast;
+	uint8_t frame5CntLast;
+	uint8_t frame6CntLast;
+	uint8_t frame7CntLast;
+	uint8_t frame8CntLast;
+	uint16_t frame1Sent;
+	uint16_t frame2Sent;
+	uint16_t frame3Sent;
+	uint16_t frame4Sent;
+	uint16_t frame5Sent;
+	uint16_t frame6Sent;
+	uint16_t frame7Sent;
+	uint16_t frame8Sent;
+	uint16_t frame1Recv;
+	uint16_t frame2Recv;
+	uint16_t frame3Recv;
+	uint16_t frame4Recv;
+	uint16_t frame5Recv;
+	uint16_t frame6Recv;
+	uint16_t frame7Recv;
+	uint16_t frame8Recv;
+} MPC_RECORD;
+
+
+extern void MPC_PCIESentStart();
+extern MPC_RECORD* mpcRecord;
+extern MPC_INST* mpcInstPtr;
+
+int MPC_Init(MPC_INST** instPtr, MPC_CONFIG* configPtr);
+int MPC_MsgHandler(MPC_INST* instPtr);
+int MPC_StateUpload(MPC_INST* instPtr ,  uint8_t* mgmtBuffer , uint32_t mgmtMsgCnt
+			, uint8_t* svcBuffer , uint32_t svcMsgCnt , MGMT_MSG_RECORD* mgmtmsg);
+int MPC_SendMsg(MPC_INST* instPtr, MPC_MSG_TYPE type, uint8_t* buffer, uint32_t dlen);
+
+#endif //_MPC_PCIE
+#endif //_MPC_CTRL
+#endif //MPC_CTRL_H_