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Initial version.
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/******************************************************************************
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*
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* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xintc.h
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* @addtogroup intc_v3_9
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* @{
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* @details
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*
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* The Xilinx interrupt controller driver component. This component supports the
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* Xilinx interrupt controller.
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*
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* The interrupt controller driver uses the idea of priority for the various
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* handlers. Priority is an integer within the range of 0 and 31 inclusive with
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* 0 being the highest priority interrupt source.
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*
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* The Xilinx interrupt controller supports the following features:
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*
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* - specific individual interrupt enabling/disabling
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* - specific individual interrupt acknowledging
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* - attaching specific callback function to handle interrupt source
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* - master enable/disable
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* - single callback per interrupt or all pending interrupts handled for
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* each interrupt of the processor
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*
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* The acknowledgement of the interrupt within the interrupt controller is
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* selectable, either prior to the device's handler being called or after
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* the handler is called. This is necessary to support interrupt signal inputs
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* which are either edge or level signals. Edge driven interrupt signals
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* require that the interrupt is acknowledged prior to the interrupt being
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* serviced in order to prevent the loss of interrupts which are occurring
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* extremely close together. A level driven interrupt input signal requires
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* the interrupt to acknowledged after servicing the interrupt to ensure that
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* the interrupt only generates a single interrupt condition.
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*
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* Details about connecting the interrupt handler of the driver are contained
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* in the source file specific to interrupt processing, xintc_intr.c.
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*
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* This driver is intended to be RTOS and processor independent. It works with
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* physical addresses only. Any needs for dynamic memory management, threads
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* or thread mutual exclusion, virtual memory, or cache control must be
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* satisfied by the layer above this driver.
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*
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* <b>Interrupt Vector Tables</b>
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*
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* The interrupt vector table for each interrupt controller device is declared
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* statically in xintc_g.c within the configuration data for each instance.
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* The device ID of the interrupt controller device is used by the driver as a
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* direct index into the configuration data table - to retrieve the vector table
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* for an instance of the interrupt controller. The user should populate the
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* vector table with handlers and callbacks at run-time using the XIntc_Connect()
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* and XIntc_Disconnect() functions.
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*
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* Each vector table entry corresponds to a device that can generate an
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* interrupt. Each entry contains an interrupt handler function and an argument
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* to be passed to the handler when an interrupt occurs. The tools default this
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* argument to the base address of the interrupting device. Note that the
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* device driver interrupt handlers given in this file do not take a base
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* address as an argument, but instead take a pointer to the driver instance.
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* This means that although the table is created statically, the user must still
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* use XIntc_Connect() when the interrupt handler takes an argument other than
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* the base address. This is only to say that the existence of the static vector
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* tables should not mislead the user into thinking they no longer need to
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* register/connect interrupt handlers with this driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a ecm 08/16/01 First release
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* 1.00a rpm 01/09/02 Removed the AckLocation argument from XIntc_Connect().
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* This information is now internal in xintc_g.c.
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* 1.00b jhl 02/13/02 Repartitioned the driver for smaller files
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* 1.00b jhl 04/24/02 Made LookupConfig function global and relocated config
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* data type
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* 1.00c rpm 10/17/03 New release. Support the static vector table created
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* in the xintc_g.c configuration table. Moved vector
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* table and options out of instance structure and into
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* the configuration table.
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* 1.10c mta 03/21/07 Updated to new coding style
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* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
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* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed from
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* all the macro names/definitions.
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* 2.01a sdm 04/27/10 Updated the tcl so that the defintions are generated in
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* the xparameters.h to know whether the optional registers
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* SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
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* This driver doesnot make use of these definitions and does
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* not use the optional registers.
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* 2.03a hvm 05/24/11 Updated the tcl to generate vector Ids for external
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* interrupts. CR565336
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* 2.04a bss 01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
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* and XIntc_SetNormalIntrMode for setting to normal
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* interrupt mode.
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* 2.04a asa 03/19/12 Changed the XIntc_Config struct. The order of entries
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* declared in the structure now matches with the
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* XIntc_ConfigTable generated by the driver tcl.
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* 2.05a bss 08/16/12 Updated to support relocatable vectors in Microblaze,
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* added IntVectorAddr to XIntc_Config for this.
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* Added XIntc_RegisterFastHandler API to register fast
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* interrupt handlers using base address.
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* 2.06a bss 01/28/13 To support Cascade mode:
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* Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
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* XIN_INTC_SECONDARY,XIN_INTC_LAST and
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* XIN_CONTROLLER_MAX_INTRS macros
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* Added NumberofIntrs and IntcType fields in XIntc_Config
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* structure.
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* Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
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* XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
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* XIntc_Acknowledge,XIntc_ConnectFastHandler and
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* XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
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* API in xintc.c
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* Modified XIntc_DeviceInterruptHandler,
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* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
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* XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
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* API in xintc_l.c.
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* Modified XIntc_SetOptions API in xintc_options.c.
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* Modified XIntc_SimulateIntr API in xintc_selftest.c.
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* Modified driver tcl:
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* to check for Cascade mode and generate XPAR_INTC_TYPE
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* for each controller.
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* Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
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* interrupt sources of all Controllers in Cascade mode.
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* 2.07a bss 10/18/13 To support Nested interrupts:
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* Modified XIntc_DeviceInterruptHandler API.
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* Added XIN_ILR_OFFSET macro in xintc_l.h.
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* Modified driver tcl to generate HAS_ILR parameter in
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* xparameters.h
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* 3.0 bss 01/28/13 Modified xintc.c to initialize IVAR register with
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* XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
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* CR#765931.
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* Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
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* correctly(CR#764865).
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*
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* @note
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* For Cascade mode, Interrupt IDs are generated in xparameters.h
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* as shown below:
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*
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* Master/Primary INTC
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* ______
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* | |-0 Secondary INTC
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* | |-. ______
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* | |-. | |-32 Last INTC
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* | |-. | |-. ______
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* |______|<-31------| |-. | |-64
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* | |-. | |-.
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* |______|<-63-------| |-.
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* | |-.
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* |______|-95
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*
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* All driver functions has to be called using DeviceId/
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* InstancePtr/BaseAddress of Primary/Master Controller and
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* Interrupts IDs generated in xparameters.h only.
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* Driver functions takes care of Slave Controllers based on
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* Interrupt ID passed. User must not use Interrupt source/ID
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* 31 of Primary and Secondary controllers to call driver
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* functions.
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*
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* For nested interrupts, XIntc_DeviceInterruptHandler saves
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* microblaze r14 register on entry and restores on exit. This is
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* required since compiler does not support nesting. It enables
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* Microblaze interrupts after blocking further interrupts from
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* the current interrupt number and interrupts below current
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* interrupt proirity by writing to Interrupt Level Register of
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* INTC on entry. On exit, it disables microblaze interrupts and
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* restores ILR register default value(0xFFFFFFFF)back. It is
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* recommended to increase STACK_SIZE in linker script for nested
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* interrupts.
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* 3.0 adk 12/10/13 Updated as per the New Tcl API's
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* 3.0 adk 17/02/14 Fixed the CR:771287 Changes are made in the intc
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* driver tcl.
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* 3.1 adk 8/4/14 Fixed the CR:783248 Changes are made in
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* the test-app tcl
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* 3.2 bss 4/8/14 Fixed driver tcl to handle external interrupt pins
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* correctly (CR#799609).
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* 3.3 adk 11/3/14 added generation of C_HAS_ILR parameter to
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* xparameters.h.Changes are made in the driver tcl file
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* (CR#828046).
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* 3.5 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
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* 3.6 ms 01/23/17 Added xil_printf statement in main function for all
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* examples to ensure that "Successfully ran" and "Failed"
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* strings are available in all examples. This is a fix
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* for CR-965028.
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* ms 03/17/17 Added readme.txt file in examples folder for doxygen
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* generation.
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* 3.7 ms 04/18/17 Modified tcl file to add suffix U for macro definitions
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* of intc in xparameters.h
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* 3.9 adk 19/12/18 If design contains unconnected interrupt pins
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* return proper error message(CR#1018878).
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* </pre>
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*
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******************************************************************************/
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#ifndef XINTC_H /* prevent circular inclusions */
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#define XINTC_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xparameters.h"
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#include "xstatus.h"
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#include "xintc_l.h"
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/************************** Constant Definitions *****************************/
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/**
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* @name Configuration options
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* These options are used in XIntc_SetOptions() to configure the device.
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* @{
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*/
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/**
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* <pre>
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* XIN_SVC_SGL_ISR_OPTION Service the highest priority pending interrupt
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* and then return.
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* XIN_SVC_ALL_ISRS_OPTION Service all of the pending interrupts and then
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* return.
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* </pre>
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*/
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#define XIN_SVC_SGL_ISR_OPTION 1UL
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#define XIN_SVC_ALL_ISRS_OPTION 2UL
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/*@}*/
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/**
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* @name Start modes
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* One of these values is passed to XIntc_Start() to start the device.
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* @{
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*/
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/** Simulation only mode, no hardware interrupts recognized */
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#define XIN_SIMULATION_MODE 0
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/** Real mode, no simulation allowed, hardware interrupts recognized */
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#define XIN_REAL_MODE 1
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/*@}*/
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/**
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* @name Masks to specify Interrupt Controller Mode
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* @{
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*/
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#define XIN_INTC_NOCASCADE 0 /* Normal - No Cascade Mode */
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#define XIN_INTC_PRIMARY 1 /* Master/Primary controller */
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#define XIN_INTC_SECONDARY 2 /* Secondary Slave Controllers */
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#define XIN_INTC_LAST 3 /* Last Slave Controller */
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/*@}*/
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/**
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* @name Mask to specify maximum number of interrupt sources per controller
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* @{
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*/
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#define XIN_CONTROLLER_MAX_INTRS 32 /* Each Controller has 32
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interrupt pins */
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#define XINTC_STANDARD_VECTOR_ADDRESS_WIDTH 32U
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/*@}*/
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/**************************** Type Definitions *******************************/
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/**
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* This typedef contains configuration information for the device.
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*/
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typedef struct {
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u16 DeviceId; /**< Unique ID of device */
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UINTPTR BaseAddress; /**< Register base address */
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u32 AckBeforeService; /**< Ack location per interrupt */
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int FastIntr; /**< Fast Interrupt enabled */
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u32 IntVectorAddr; /**< Interrupt Vector Address */
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int NumberofIntrs; /**< Number of Interrupt sources */
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u8 VectorAddrWidth; /**< Width of vector address */
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u32 Options; /**< Device options */
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int IntcType; /**< Intc type 0 - No Cascade Mode
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1 - primary instance
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2 - secondary instance
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3 - last instance */
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/** Static vector table of interrupt handlers */
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#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
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XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS];
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#else
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XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS];
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#endif
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} XIntc_Config;
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/**
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* The XIntc driver instance data. The user is required to allocate a
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* variable of this type for every intc device in the system. A pointer
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* to a variable of this type is then passed to the driver API functions.
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*/
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typedef struct {
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UINTPTR BaseAddress; /**< Base address of registers */
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u32 IsReady; /**< Device is initialized and ready */
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u32 IsStarted; /**< Device has been started */
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u32 UnhandledInterrupts; /**< Intc Statistics */
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XIntc_Config *CfgPtr; /**< Pointer to instance config entry */
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} XIntc;
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/*
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* Required functions in xintc.c
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*/
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int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId);
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int XIntc_Start(XIntc * InstancePtr, u8 Mode);
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void XIntc_Stop(XIntc * InstancePtr);
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int XIntc_Connect(XIntc * InstancePtr, u8 Id,
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XInterruptHandler Handler, void *CallBackRef);
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void XIntc_Disconnect(XIntc * InstancePtr, u8 Id);
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void XIntc_Enable(XIntc * InstancePtr, u8 Id);
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void XIntc_Disable(XIntc * InstancePtr, u8 Id);
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void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id);
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XIntc_Config *XIntc_LookupConfig(u16 DeviceId);
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int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
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XFastInterruptHandler Handler);
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void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id);
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/*
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* Interrupt functions in xintr_intr.c
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*/
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void XIntc_VoidInterruptHandler(void);
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void XIntc_InterruptHandler(XIntc * InstancePtr);
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/*
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* Options functions in xintc_options.c
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*/
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int XIntc_SetOptions(XIntc * InstancePtr, u32 Options);
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u32 XIntc_GetOptions(XIntc * InstancePtr);
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/*
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* Self-test functions in xintc_selftest.c
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*/
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int XIntc_SelfTest(XIntc * InstancePtr);
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int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id);
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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||||
/** @} */
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