forked from 0xha0/datalink_repo
enhance coherence.
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@@ -206,11 +206,11 @@ int MPC_MsgHandler(MPC_INST* instPtr){
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MPC_GetChunk(mpcRxMsgBuff, TEST_MODE_SET_OFFSET, TEST_MODE_SET_LEN, &dataChunk);
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// FIXME
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if((uint8_t)dataChunk == TEST_MODE_HEAD){
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l2Config.myType = HEAD_NODE;
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l2Config.myType = L2_NODE_HEAD;
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l2Config.myId = 1;
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}
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else{
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l2Config.myType = MEMBER_NODE;
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l2Config.myType = L2_NODE_MEMBER;
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l2Config.myId = 2;
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}
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MPC_InsertChunk(mpcTxMsgBuff, TEST_REQ_FPGA_ST_OFFSET, TEST_REQ_FPGA_ST_LEN, 0x01);
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@@ -313,7 +313,7 @@ int MPC_SendMsg(MPC_INST* instPtr, MPC_MSG_TYPE type, uint8_t* buffer, uint32_t
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*
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******************************************************************************/
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int MPC_StateUpload(MPC_INST* instPtr , uint8_t* mgmtBuffer , uint32_t mgmtMsgCnt ,
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uint8_t* svcBuffer , uint32_t svcMsgCnt , MGMT_MSG_RECORD* mgmtMsg){
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uint8_t* svcBuffer , uint32_t svcMsgCnt , L2_MGMT_MSG_RECORD* mgmtMsg){
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ASSERT(instPtr != NULL);
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int32_t Status = SUCCESS;
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uint64_t dataChunk = 0;
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@@ -323,13 +323,13 @@ int MPC_StateUpload(MPC_INST* instPtr , uint8_t* mgmtBuffer , uint32_t mgmtMsgC
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// Stage
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switch (linkInstPtr->mainState) {
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case INIT_STATE :
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case L2_INIT_STATE :
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dataChunk = STATE_STAGE_SETUP;
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break;
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case INTRA_SEEK_STATE:
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case L2_INTRA_SEEK_STATE:
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dataChunk = STATE_STAGE_RTNE;
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break;
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case NORMAL_STATE :
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case L2_NORMAL_STATE :
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dataChunk = STATE_STAGE_SVC;
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break;
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default:
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@@ -98,7 +98,7 @@ extern MPC_INST* mpcInstPtr;
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int MPC_Init(MPC_INST** instPtr, MPC_CONFIG* configPtr);
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int MPC_MsgHandler(MPC_INST* instPtr);
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int MPC_StateUpload(MPC_INST* instPtr , uint8_t* mgmtBuffer , uint32_t mgmtMsgCnt
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, uint8_t* svcBuffer , uint32_t svcMsgCnt , MGMT_MSG_RECORD* mgmtmsg);
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, uint8_t* svcBuffer , uint32_t svcMsgCnt , L2_MGMT_MSG_RECORD* mgmtmsg);
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int MPC_SendMsg(MPC_INST* instPtr, MPC_MSG_TYPE type, uint8_t* buffer, uint32_t dlen);
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#endif //_MPC_PCIE
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