/*****************************************************************************/
/**
 * Description: Global configurations.
 *
 * Date: 2021-04-28 13:19
 * Last Edit Time: 2022-05-23 20:32
 *
 * Revisions: Rev 0.0
 * History:
 * [2021-04-28]: Initial edition.
 *
 * Copyright(c) 2021 Beijing Institute of Technology.
 * Lab of Communication and Networking
 *
 ******************************************************************************/

#ifndef CONFIG_H_
#define CONFIG_H_

#define XILINX_PLATFORM

#include "xparameters.h"
#include "../util/util.h"

/*********** Indoor Test Mode ************/

/************ Hardware Configs ************/
#define CPU_CLK_HZ XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ
#define FCLK_CLK0_HZ XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ

/********* Zynq Platform Configs **********/

// Check crc validation by computing crc value and comparing.
#define CRC_COMPARE


//Hardware Parameter
#define SPI_INTERFACE_SPI_ENGINE

#define HAVE_SPLIT_GAIN_TABLE	1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
#define HAVE_TDD_SYNTH_TABLE	1 /* only set to 0 in case split_gain_table_mode_enable = 0*/

#define AD9361_DEVICE			1 /* set it 1 if AD9361 device is used, 0 otherwise */
#define AD9364_DEVICE			0 /* set it 1 if AD9364 device is used, 0 otherwise */
#define AD9363A_DEVICE			0 /* set it 1 if AD9363A device is used, 0 otherwise */

#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */
//#define HAVE_DEBUG_MESSAGES /* For Debug purposes only */

#define GPIO_DEVICE_ID				XPAR_AXI_GPIO_DEVICE_ID
#define GPIO_OFFSET					54
#define GPIO_INPUT 					0
#define GPIO_OUTPUT 				1
#define GPIO_DISABLE 				0
#define GPIO_ENABLE 				1

#define AD9516_POWEDOWN_B			0
#define AD9516_RESET_B				1
#define AD9516_SYNC_B				2
#define AD9361_1_TXNRX				3
#define AD9361_1_ENABLE				4
#define AD9361_1_EN_AGC				5
#define AD9361_1_RESET_B			6
#define AD9361_1_CTRL_IN_0			7
#define AD9361_1_CTRL_IN_1			8
#define AD9361_1_CTRL_IN_2			9
#define AD9361_1_CTRL_IN_3			10
#define AD9361_2_TXNRX				11
#define AD9361_2_ENABLE				12
#define AD9361_2_EN_AGC				13
#define AD9361_2_RESET_B			14
#define AD9361_2_CTRL_IN_0			15
#define AD9361_2_CTRL_IN_1			16
#define AD9361_2_CTRL_IN_2			17
#define AD9361_2_CTRL_IN_3			18
#define AD9361_SYNC					19
#define AD9361_RX_FIFO_RST			20

#define AD9361_1_CTRL_OUT_0			0
#define AD9361_1_CTRL_OUT_1			1
#define AD9361_1_CTRL_OUT_2			2
#define AD9361_1_CTRL_OUT_3			3
#define AD9361_1_CTRL_OUT_4			4
#define AD9361_1_CTRL_OUT_5			5
#define AD9361_1_CTRL_OUT_6			6
#define AD9361_1_CTRL_OUT_7			7
#define AD9361_2_CTRL_OUT_0			8
#define AD9361_2_CTRL_OUT_1			9
#define AD9361_2_CTRL_OUT_2			10
#define AD9361_2_CTRL_OUT_3			11
#define AD9361_2_CTRL_OUT_4			12
#define AD9361_2_CTRL_OUT_5			13
#define AD9361_2_CTRL_OUT_6			14
#define AD9361_2_CTRL_OUT_7			15
#define AD9516_REFMON				16
#define AD9516_LOCKDETECT			17
#define AD9516_STARUS				18

#define GPIO_BANK_OUT				1
#define GPIO_BANK_IN				2

#define SPI_DEVICE_ID				0
#define SPI_ENGINE_REF_CLK          FCLK_CLK0_HZ
#define SPI_ENGINE_MAX_SPEED		5000000
#define SPI_ENGINE_BASEADDR			XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define SPI_ENGINE_DATA_WIDTH       8
#define SPI_ENGINE_CS_DELAY			3
#define SPI_CS_AD9516           	0x00
#define SPI_CS_AD9361_1             0x01
#define SPI_CS_AD9361_2             0x02

// Interrupt Configs
#define INTC_DEVICE_ID 				XPAR_AXI_INTC_DEVICE_ID
#define PHY_INTR_ID		XPAR_AXI_INTC_SYSTEM_PHY_IRQ_INTR
#define C2C_TX_INTR_ID	XPAR_AXI_INTC_AXI_DMA_C2C_MM2S_INTROUT_INTR
#define C2C_RX_INTR_ID 	XPAR_AXI_INTC_AXI_DMA_C2C_S2MM_INTROUT_INTR
#define SCUTIMER_INTR_ID 	XPAR_AXI_INTC_AXI_TIMER_0_INTERRUPT_INTR

// C2C configure
#define C2C_AXI_DMA_DEVICE_ID		XPAR_AXI_DMA_C2C_DEVICE_ID
#define C2C_RXBUFF_ADDR_BASE		XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_BASEADDR
#define C2C_TXBUFF_ADDR_BASE		XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_BASEADDR
#define C2C_BUFF_NUM 4
#define C2C_BUFF_SIZE 1024

// Physical configure
#define PHY_CTRL_BASEADDR 			XPAR_PHYC_BASEADDR
#define PHY_RX_BRAM_BUFF_ID 		XPAR_RX_FRAME_BRAM_CTRL_DEVICE_ID
#define PHY_TX_BRAM_BUFF_ID 		XPAR_TX_FRAME_BRAM_CTRL_DEVICE_ID
#define PHY_ANT_CONFIG_BRAM_ID 		XPAR_ANT_CONFIG_BRAM_CTRL_DEVICE_ID
#define PHY_RX_BUFF_BASEADDR 		XPAR_RX_FRAME_BRAM_CTRL_S_AXI_BASEADDR
#define PHY_TX_BUFF_BASEADDR 		XPAR_TX_FRAME_BRAM_CTRL_S_AXI_BASEADDR

//Remote Test
#define GLINK_REMOTE_TEST_ENABLE
#define TIMER_COUNT_MAX 150000000
#define SCUTIMER_DEVICE_ID XPAR_AXI_TIMER_0_DEVICE_ID

//ANT ID
#define ANT_DEVICE_ID 0x0000

#if defined(GLINK_REMOTE_TEST_ENABLE) && !defined(TIMER_COUNT_MAX)
#define TIMER_COUNT_MAX 150000000
#warning Must set a remote test interval after enable remote test.
#warning Use default interval 150000000...
#endif

//XADC ID
#define SYSMON_DEVICE_ID XPAR_XADC_WIZ_0_DEVICE_ID

#endif