forked from gatsby/datalink_repo
951 lines
41 KiB
C
951 lines
41 KiB
C
#ifndef XPARAMETERS_H /* prevent circular inclusions */
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#define XPARAMETERS_H /* by using protection macros */
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/* Definitions for bus frequencies */
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#define XPAR_CPU_M_AXI_DP_FREQ_HZ 150000000
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/******************************************************************/
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/* Canonical definitions for bus frequencies */
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/******************************************************************/
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#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 150000000
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#define XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ 150000000
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/******************************************************************/
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/* Definitions for peripheral MICROBLAZE_PS */
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#define XPAR_MICROBLAZE_PS_ADDR_SIZE 32
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#define XPAR_MICROBLAZE_PS_ADDR_TAG_BITS 17
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#define XPAR_MICROBLAZE_PS_ALLOW_DCACHE_WR 1
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#define XPAR_MICROBLAZE_PS_ALLOW_ICACHE_WR 1
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#define XPAR_MICROBLAZE_PS_AREA_OPTIMIZED 0
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#define XPAR_MICROBLAZE_PS_ASYNC_INTERRUPT 1
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#define XPAR_MICROBLAZE_PS_ASYNC_WAKEUP 3
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#define XPAR_MICROBLAZE_PS_AVOID_PRIMITIVES 0
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#define XPAR_MICROBLAZE_PS_BASE_VECTORS 0x0000000000000000
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#define XPAR_MICROBLAZE_PS_BRANCH_TARGET_CACHE_SIZE 0
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#define XPAR_MICROBLAZE_PS_CACHE_BYTE_SIZE 16384
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#define XPAR_MICROBLAZE_PS_DADDR_SIZE 32
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#define XPAR_MICROBLAZE_PS_DATA_SIZE 32
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#define XPAR_MICROBLAZE_PS_DCACHE_ADDR_TAG 17
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#define XPAR_MICROBLAZE_PS_DCACHE_ALWAYS_USED 0
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#define XPAR_MICROBLAZE_PS_DCACHE_BASEADDR 0x80000000
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#define XPAR_MICROBLAZE_PS_DCACHE_BYTE_SIZE 16384
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#define XPAR_MICROBLAZE_PS_DCACHE_DATA_WIDTH 0
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#define XPAR_MICROBLAZE_PS_DCACHE_FORCE_TAG_LUTRAM 0
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#define XPAR_MICROBLAZE_PS_DCACHE_HIGHADDR 0xFFFFFFFF
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#define XPAR_MICROBLAZE_PS_DCACHE_LINE_LEN 4
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#define XPAR_MICROBLAZE_PS_DCACHE_USE_WRITEBACK 1
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#define XPAR_MICROBLAZE_PS_DCACHE_VICTIMS 0
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#define XPAR_MICROBLAZE_PS_DC_AXI_MON 0
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#define XPAR_MICROBLAZE_PS_DEBUG_COUNTER_WIDTH 32
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#define XPAR_MICROBLAZE_PS_DEBUG_ENABLED 1
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#define XPAR_MICROBLAZE_PS_DEBUG_EVENT_COUNTERS 5
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#define XPAR_MICROBLAZE_PS_DEBUG_EXTERNAL_TRACE 0
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#define XPAR_MICROBLAZE_PS_DEBUG_INTERFACE 0
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#define XPAR_MICROBLAZE_PS_DEBUG_LATENCY_COUNTERS 1
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#define XPAR_MICROBLAZE_PS_DEBUG_PROFILE_SIZE 0
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#define XPAR_MICROBLAZE_PS_DEBUG_TRACE_ASYNC_RESET 0
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#define XPAR_MICROBLAZE_PS_DEBUG_TRACE_SIZE 8192
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#define XPAR_MICROBLAZE_PS_DIV_ZERO_EXCEPTION 1
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#define XPAR_MICROBLAZE_PS_DP_AXI_MON 0
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#define XPAR_MICROBLAZE_PS_DYNAMIC_BUS_SIZING 0
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#define XPAR_MICROBLAZE_PS_D_AXI 1
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#define XPAR_MICROBLAZE_PS_D_LMB 1
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#define XPAR_MICROBLAZE_PS_D_LMB_MON 0
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#define XPAR_MICROBLAZE_PS_ECC_USE_CE_EXCEPTION 0
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#define XPAR_MICROBLAZE_PS_EDGE_IS_POSITIVE 1
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#define XPAR_MICROBLAZE_PS_ENABLE_DISCRETE_PORTS 0
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#define XPAR_MICROBLAZE_PS_ENDIANNESS 1
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#define XPAR_MICROBLAZE_PS_FAULT_TOLERANT 0
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#define XPAR_MICROBLAZE_PS_FPU_EXCEPTION 0
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#define XPAR_MICROBLAZE_PS_FREQ 150000000
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#define XPAR_MICROBLAZE_PS_FSL_EXCEPTION 0
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#define XPAR_MICROBLAZE_PS_FSL_LINKS 0
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#define XPAR_MICROBLAZE_PS_IADDR_SIZE 32
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#define XPAR_MICROBLAZE_PS_ICACHE_ALWAYS_USED 1
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#define XPAR_MICROBLAZE_PS_ICACHE_BASEADDR 0x80000000
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#define XPAR_MICROBLAZE_PS_ICACHE_DATA_WIDTH 0
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#define XPAR_MICROBLAZE_PS_ICACHE_FORCE_TAG_LUTRAM 0
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#define XPAR_MICROBLAZE_PS_ICACHE_HIGHADDR 0xFFFFFFFF
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#define XPAR_MICROBLAZE_PS_ICACHE_LINE_LEN 4
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#define XPAR_MICROBLAZE_PS_ICACHE_STREAMS 0
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#define XPAR_MICROBLAZE_PS_ICACHE_VICTIMS 0
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#define XPAR_MICROBLAZE_PS_IC_AXI_MON 0
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#define XPAR_MICROBLAZE_PS_ILL_OPCODE_EXCEPTION 1
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#define XPAR_MICROBLAZE_PS_IMPRECISE_EXCEPTIONS 0
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#define XPAR_MICROBLAZE_PS_INSTR_SIZE 32
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#define XPAR_MICROBLAZE_PS_INTERCONNECT 2
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#define XPAR_MICROBLAZE_PS_INTERRUPT_IS_EDGE 0
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#define XPAR_MICROBLAZE_PS_INTERRUPT_MON 0
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#define XPAR_MICROBLAZE_PS_IP_AXI_MON 0
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#define XPAR_MICROBLAZE_PS_I_AXI 0
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#define XPAR_MICROBLAZE_PS_I_LMB 1
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#define XPAR_MICROBLAZE_PS_I_LMB_MON 0
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#define XPAR_MICROBLAZE_PS_LMB_DATA_SIZE 32
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#define XPAR_MICROBLAZE_PS_LOCKSTEP_MASTER 0
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#define XPAR_MICROBLAZE_PS_LOCKSTEP_SELECT 0
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#define XPAR_MICROBLAZE_PS_LOCKSTEP_SLAVE 0
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#define XPAR_MICROBLAZE_PS_M0_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M0_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M1_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M1_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M2_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M2_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M3_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M3_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M4_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M4_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M5_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M5_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M6_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M6_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M7_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M7_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M8_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M8_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M9_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M9_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M10_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M10_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M11_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M11_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M12_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M12_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M13_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M13_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M14_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M14_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_M15_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M15_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_MMU_DTLB_SIZE 2
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#define XPAR_MICROBLAZE_PS_MMU_ITLB_SIZE 1
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#define XPAR_MICROBLAZE_PS_MMU_PRIVILEGED_INSTR 0
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#define XPAR_MICROBLAZE_PS_MMU_TLB_ACCESS 3
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#define XPAR_MICROBLAZE_PS_MMU_ZONES 2
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_ADDR_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_ARUSER_WIDTH 5
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_AWUSER_WIDTH 5
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_BUSER_WIDTH 1
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_EXCLUSIVE_ACCESS 0
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_RUSER_WIDTH 1
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_THREAD_ID_WIDTH 1
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_USER_SIGNALS 0
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_USER_VALUE 31
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#define XPAR_MICROBLAZE_PS_M_AXI_DC_WUSER_WIDTH 1
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#define XPAR_MICROBLAZE_PS_M_AXI_DP_ADDR_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M_AXI_DP_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M_AXI_DP_EXCLUSIVE_ACCESS 0
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#define XPAR_MICROBLAZE_PS_M_AXI_DP_THREAD_ID_WIDTH 1
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#define XPAR_MICROBLAZE_PS_M_AXI_D_BUS_EXCEPTION 1
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#define XPAR_MICROBLAZE_PS_M_AXI_IC_ADDR_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M_AXI_IC_ARUSER_WIDTH 5
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#define XPAR_MICROBLAZE_PS_M_AXI_IC_AWUSER_WIDTH 5
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#define XPAR_MICROBLAZE_PS_M_AXI_IC_BUSER_WIDTH 1
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#define XPAR_MICROBLAZE_PS_M_AXI_IC_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M_AXI_IC_RUSER_WIDTH 1
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#define XPAR_MICROBLAZE_PS_M_AXI_IC_THREAD_ID_WIDTH 1
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#define XPAR_MICROBLAZE_PS_M_AXI_IC_USER_SIGNALS 0
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#define XPAR_MICROBLAZE_PS_M_AXI_IC_USER_VALUE 31
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#define XPAR_MICROBLAZE_PS_M_AXI_IC_WUSER_WIDTH 1
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#define XPAR_MICROBLAZE_PS_M_AXI_IP_ADDR_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M_AXI_IP_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_M_AXI_IP_THREAD_ID_WIDTH 1
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#define XPAR_MICROBLAZE_PS_M_AXI_I_BUS_EXCEPTION 1
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#define XPAR_MICROBLAZE_PS_NUMBER_OF_PC_BRK 2
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#define XPAR_MICROBLAZE_PS_NUMBER_OF_RD_ADDR_BRK 0
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#define XPAR_MICROBLAZE_PS_NUMBER_OF_WR_ADDR_BRK 0
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#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_CLK 2
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#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_CLK_DEBUG 2
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#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_CLK_IRQ 1
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#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_DBG_CLK 1
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#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_DBG_TRACE_CLK 2
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#define XPAR_MICROBLAZE_PS_OPCODE_0X0_ILLEGAL 1
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#define XPAR_MICROBLAZE_PS_OPTIMIZATION 0
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#define XPAR_MICROBLAZE_PS_PC_WIDTH 32
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#define XPAR_MICROBLAZE_PS_PIADDR_SIZE 32
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#define XPAR_MICROBLAZE_PS_PVR 0
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#define XPAR_MICROBLAZE_PS_PVR_USER1 0x00
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#define XPAR_MICROBLAZE_PS_PVR_USER2 0x00000000
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#define XPAR_MICROBLAZE_PS_RESET_MSR 0x00000000
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#define XPAR_MICROBLAZE_PS_RESET_MSR_BIP 0
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#define XPAR_MICROBLAZE_PS_RESET_MSR_DCE 0
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#define XPAR_MICROBLAZE_PS_RESET_MSR_EE 0
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#define XPAR_MICROBLAZE_PS_RESET_MSR_EIP 0
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#define XPAR_MICROBLAZE_PS_RESET_MSR_ICE 0
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#define XPAR_MICROBLAZE_PS_RESET_MSR_IE 0
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#define XPAR_MICROBLAZE_PS_S0_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S0_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S1_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S1_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S2_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S2_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S3_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S3_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S4_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S4_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S5_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S5_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S6_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S6_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S7_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S7_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S8_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S8_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S9_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S9_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S10_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S10_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S11_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S11_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S12_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S12_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S13_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S13_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S14_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S14_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_S15_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_PS_S15_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_PS_SCO 0
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#define XPAR_MICROBLAZE_PS_TRACE 0
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#define XPAR_MICROBLAZE_PS_UNALIGNED_EXCEPTIONS 1
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#define XPAR_MICROBLAZE_PS_USE_BARREL 1
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#define XPAR_MICROBLAZE_PS_USE_BRANCH_TARGET_CACHE 0
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#define XPAR_MICROBLAZE_PS_USE_CONFIG_RESET 0
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#define XPAR_MICROBLAZE_PS_USE_DCACHE 1
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#define XPAR_MICROBLAZE_PS_USE_DIV 1
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#define XPAR_MICROBLAZE_PS_USE_EXTENDED_FSL_INSTR 0
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#define XPAR_MICROBLAZE_PS_USE_EXT_BRK 0
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#define XPAR_MICROBLAZE_PS_USE_EXT_NM_BRK 0
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#define XPAR_MICROBLAZE_PS_USE_FPU 0
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#define XPAR_MICROBLAZE_PS_USE_HW_MUL 1
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#define XPAR_MICROBLAZE_PS_USE_ICACHE 1
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#define XPAR_MICROBLAZE_PS_USE_INTERRUPT 1
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#define XPAR_MICROBLAZE_PS_USE_MMU 0
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#define XPAR_MICROBLAZE_PS_USE_MSR_INSTR 1
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#define XPAR_MICROBLAZE_PS_USE_NON_SECURE 0
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#define XPAR_MICROBLAZE_PS_USE_PCMP_INSTR 1
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#define XPAR_MICROBLAZE_PS_USE_REORDER_INSTR 1
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#define XPAR_MICROBLAZE_PS_USE_STACK_PROTECTION 0
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#define XPAR_MICROBLAZE_PS_COMPONENT_NAME system_microblaze_ps_0
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#define XPAR_MICROBLAZE_PS_EDK_IPTYPE PROCESSOR
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#define XPAR_MICROBLAZE_PS_EDK_SPECIAL microblaze
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#define XPAR_MICROBLAZE_PS_G_TEMPLATE_LIST 9
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#define XPAR_MICROBLAZE_PS_G_USE_EXCEPTIONS 1
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/******************************************************************/
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#define XPAR_CPU_ID 0
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#define XPAR_MICROBLAZE_ID 0
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#define XPAR_MICROBLAZE_ADDR_SIZE 32
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#define XPAR_MICROBLAZE_ADDR_TAG_BITS 17
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#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
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#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
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#define XPAR_MICROBLAZE_AREA_OPTIMIZED 0
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#define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1
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#define XPAR_MICROBLAZE_ASYNC_WAKEUP 3
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#define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
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#define XPAR_MICROBLAZE_BASE_VECTORS 0x0000000000000000
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#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
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#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 16384
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#define XPAR_MICROBLAZE_DADDR_SIZE 32
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#define XPAR_MICROBLAZE_DATA_SIZE 32
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#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 17
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#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 0
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#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x80000000
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#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 16384
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#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
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#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
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#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xFFFFFFFF
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#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
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#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 1
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#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0
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#define XPAR_MICROBLAZE_DC_AXI_MON 0
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#define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32
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#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
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#define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5
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#define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0
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#define XPAR_MICROBLAZE_DEBUG_INTERFACE 0
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#define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1
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#define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0
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#define XPAR_MICROBLAZE_DEBUG_TRACE_ASYNC_RESET 0
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#define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192
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#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1
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#define XPAR_MICROBLAZE_DP_AXI_MON 0
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#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
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#define XPAR_MICROBLAZE_D_AXI 1
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#define XPAR_MICROBLAZE_D_LMB 1
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#define XPAR_MICROBLAZE_D_LMB_MON 0
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#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
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#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
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#define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0
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#define XPAR_MICROBLAZE_ENDIANNESS 1
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#define XPAR_MICROBLAZE_FAULT_TOLERANT 0
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#define XPAR_MICROBLAZE_FPU_EXCEPTION 0
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#define XPAR_MICROBLAZE_FREQ 150000000
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#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
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#define XPAR_MICROBLAZE_FSL_LINKS 0
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#define XPAR_MICROBLAZE_IADDR_SIZE 32
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#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1
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#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x80000000
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#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
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#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
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#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xFFFFFFFF
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#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
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#define XPAR_MICROBLAZE_ICACHE_STREAMS 0
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#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0
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#define XPAR_MICROBLAZE_IC_AXI_MON 0
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#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1
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#define XPAR_MICROBLAZE_IMPRECISE_EXCEPTIONS 0
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#define XPAR_MICROBLAZE_INSTR_SIZE 32
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#define XPAR_MICROBLAZE_INTERCONNECT 2
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#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
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#define XPAR_MICROBLAZE_INTERRUPT_MON 0
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#define XPAR_MICROBLAZE_IP_AXI_MON 0
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#define XPAR_MICROBLAZE_I_AXI 0
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#define XPAR_MICROBLAZE_I_LMB 1
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#define XPAR_MICROBLAZE_I_LMB_MON 0
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#define XPAR_MICROBLAZE_LMB_DATA_SIZE 32
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#define XPAR_MICROBLAZE_LOCKSTEP_MASTER 0
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#define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0
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#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
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#define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M0_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M1_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M1_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M2_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M2_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M3_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M3_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M4_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M4_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M5_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M5_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M6_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M6_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M7_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M7_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M8_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M8_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M9_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M9_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M10_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M10_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M11_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M11_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M12_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M12_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M13_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M13_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M14_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M14_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_M15_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M15_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_MMU_DTLB_SIZE 2
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#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 1
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#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
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#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
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#define XPAR_MICROBLAZE_MMU_ZONES 2
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#define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
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#define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
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#define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
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#define XPAR_MICROBLAZE_M_AXI_DC_BUSER_WIDTH 1
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#define XPAR_MICROBLAZE_M_AXI_DC_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M_AXI_DC_EXCLUSIVE_ACCESS 0
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#define XPAR_MICROBLAZE_M_AXI_DC_RUSER_WIDTH 1
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#define XPAR_MICROBLAZE_M_AXI_DC_THREAD_ID_WIDTH 1
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#define XPAR_MICROBLAZE_M_AXI_DC_USER_SIGNALS 0
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#define XPAR_MICROBLAZE_M_AXI_DC_USER_VALUE 31
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#define XPAR_MICROBLAZE_M_AXI_DC_WUSER_WIDTH 1
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#define XPAR_MICROBLAZE_M_AXI_DP_ADDR_WIDTH 32
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#define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
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#define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
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#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1
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#define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
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#define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
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#define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
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#define XPAR_MICROBLAZE_M_AXI_IC_BUSER_WIDTH 1
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#define XPAR_MICROBLAZE_M_AXI_IC_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M_AXI_IC_RUSER_WIDTH 1
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#define XPAR_MICROBLAZE_M_AXI_IC_THREAD_ID_WIDTH 1
|
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#define XPAR_MICROBLAZE_M_AXI_IC_USER_SIGNALS 0
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#define XPAR_MICROBLAZE_M_AXI_IC_USER_VALUE 31
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#define XPAR_MICROBLAZE_M_AXI_IC_WUSER_WIDTH 1
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#define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
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#define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
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#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 1
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#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 2
|
|
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 0
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#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 0
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#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK 2
|
|
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2
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#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1
|
|
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1
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|
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_TRACE_CLK 2
|
|
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1
|
|
#define XPAR_MICROBLAZE_OPTIMIZATION 0
|
|
#define XPAR_MICROBLAZE_PC_WIDTH 32
|
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#define XPAR_MICROBLAZE_PIADDR_SIZE 32
|
|
#define XPAR_MICROBLAZE_PVR 0
|
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#define XPAR_MICROBLAZE_PVR_USER1 0x00
|
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#define XPAR_MICROBLAZE_PVR_USER2 0x00000000
|
|
#define XPAR_MICROBLAZE_RESET_MSR 0x00000000
|
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#define XPAR_MICROBLAZE_RESET_MSR_BIP 0
|
|
#define XPAR_MICROBLAZE_RESET_MSR_DCE 0
|
|
#define XPAR_MICROBLAZE_RESET_MSR_EE 0
|
|
#define XPAR_MICROBLAZE_RESET_MSR_EIP 0
|
|
#define XPAR_MICROBLAZE_RESET_MSR_ICE 0
|
|
#define XPAR_MICROBLAZE_RESET_MSR_IE 0
|
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#define XPAR_MICROBLAZE_S0_AXIS_DATA_WIDTH 32
|
|
#define XPAR_MICROBLAZE_S0_AXIS_PROTOCOL GENERIC
|
|
#define XPAR_MICROBLAZE_S1_AXIS_DATA_WIDTH 32
|
|
#define XPAR_MICROBLAZE_S1_AXIS_PROTOCOL GENERIC
|
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#define XPAR_MICROBLAZE_S2_AXIS_DATA_WIDTH 32
|
|
#define XPAR_MICROBLAZE_S2_AXIS_PROTOCOL GENERIC
|
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#define XPAR_MICROBLAZE_S3_AXIS_DATA_WIDTH 32
|
|
#define XPAR_MICROBLAZE_S3_AXIS_PROTOCOL GENERIC
|
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#define XPAR_MICROBLAZE_S4_AXIS_DATA_WIDTH 32
|
|
#define XPAR_MICROBLAZE_S4_AXIS_PROTOCOL GENERIC
|
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#define XPAR_MICROBLAZE_S5_AXIS_DATA_WIDTH 32
|
|
#define XPAR_MICROBLAZE_S5_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_S6_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_S6_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_S7_AXIS_DATA_WIDTH 32
|
|
#define XPAR_MICROBLAZE_S7_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_S8_AXIS_DATA_WIDTH 32
|
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#define XPAR_MICROBLAZE_S8_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_S9_AXIS_DATA_WIDTH 32
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#define XPAR_MICROBLAZE_S9_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_S10_AXIS_DATA_WIDTH 32
|
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#define XPAR_MICROBLAZE_S10_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_S11_AXIS_DATA_WIDTH 32
|
|
#define XPAR_MICROBLAZE_S11_AXIS_PROTOCOL GENERIC
|
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#define XPAR_MICROBLAZE_S12_AXIS_DATA_WIDTH 32
|
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#define XPAR_MICROBLAZE_S12_AXIS_PROTOCOL GENERIC
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#define XPAR_MICROBLAZE_S13_AXIS_DATA_WIDTH 32
|
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#define XPAR_MICROBLAZE_S13_AXIS_PROTOCOL GENERIC
|
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#define XPAR_MICROBLAZE_S14_AXIS_DATA_WIDTH 32
|
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#define XPAR_MICROBLAZE_S14_AXIS_PROTOCOL GENERIC
|
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#define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
|
|
#define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
|
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#define XPAR_MICROBLAZE_SCO 0
|
|
#define XPAR_MICROBLAZE_TRACE 0
|
|
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1
|
|
#define XPAR_MICROBLAZE_USE_BARREL 1
|
|
#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 0
|
|
#define XPAR_MICROBLAZE_USE_CONFIG_RESET 0
|
|
#define XPAR_MICROBLAZE_USE_DCACHE 1
|
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#define XPAR_MICROBLAZE_USE_DIV 1
|
|
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
|
|
#define XPAR_MICROBLAZE_USE_EXT_BRK 0
|
|
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
|
|
#define XPAR_MICROBLAZE_USE_FPU 0
|
|
#define XPAR_MICROBLAZE_USE_HW_MUL 1
|
|
#define XPAR_MICROBLAZE_USE_ICACHE 1
|
|
#define XPAR_MICROBLAZE_USE_INTERRUPT 1
|
|
#define XPAR_MICROBLAZE_USE_MMU 0
|
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#define XPAR_MICROBLAZE_USE_MSR_INSTR 1
|
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#define XPAR_MICROBLAZE_USE_NON_SECURE 0
|
|
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
|
|
#define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
|
|
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0
|
|
#define XPAR_MICROBLAZE_COMPONENT_NAME system_microblaze_ps_0
|
|
#define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR
|
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#define XPAR_MICROBLAZE_EDK_SPECIAL microblaze
|
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#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 9
|
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#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1
|
|
|
|
/******************************************************************/
|
|
|
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|
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/* Definitions for interface PHYC */
|
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#define XPAR_PHYC_BASEADDR 0x44A10000
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#define XPAR_PHYC_HIGHADDR 0x44A1FFFF
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|
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|
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/* Definitions for interface PHYC */
|
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#define XPAR_PHYC_BASEADDR 0x44A10000
|
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#define XPAR_PHYC_HIGHADDR 0x44A1FFFF
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|
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|
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/******************************************************************/
|
|
|
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/* Platform specific definitions */
|
|
#define PLATFORM_MB
|
|
|
|
/* Definitions for sleep timer configuration */
|
|
#define XSLEEP_TIMER_IS_DEFAULT_TIMER
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|
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|
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/******************************************************************/
|
|
/* Definitions for driver AXIDMA */
|
|
#define XPAR_XAXIDMA_NUM_INSTANCES 1
|
|
|
|
/* Definitions for peripheral AXI_DMA_C2C */
|
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#define XPAR_AXI_DMA_C2C_DEVICE_ID 0
|
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#define XPAR_AXI_DMA_C2C_BASEADDR 0x41E00000
|
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#define XPAR_AXI_DMA_C2C_HIGHADDR 0x41E0FFFF
|
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#define XPAR_AXI_DMA_C2C_SG_INCLUDE_STSCNTRL_STRM 0
|
|
#define XPAR_AXI_DMA_C2C_INCLUDE_MM2S_DRE 1
|
|
#define XPAR_AXI_DMA_C2C_INCLUDE_S2MM_DRE 1
|
|
#define XPAR_AXI_DMA_C2C_INCLUDE_MM2S 1
|
|
#define XPAR_AXI_DMA_C2C_INCLUDE_S2MM 1
|
|
#define XPAR_AXI_DMA_C2C_M_AXI_MM2S_DATA_WIDTH 32
|
|
#define XPAR_AXI_DMA_C2C_M_AXI_S2MM_DATA_WIDTH 32
|
|
#define XPAR_AXI_DMA_C2C_INCLUDE_SG 0
|
|
#define XPAR_AXI_DMA_C2C_ENABLE_MULTI_CHANNEL 0
|
|
#define XPAR_AXI_DMA_C2C_NUM_MM2S_CHANNELS 1
|
|
#define XPAR_AXI_DMA_C2C_NUM_S2MM_CHANNELS 1
|
|
#define XPAR_AXI_DMA_C2C_MM2S_BURST_SIZE 64
|
|
#define XPAR_AXI_DMA_C2C_S2MM_BURST_SIZE 64
|
|
#define XPAR_AXI_DMA_C2C_MICRO_DMA 0
|
|
#define XPAR_AXI_DMA_C2C_ADDR_WIDTH 32
|
|
#define XPAR_AXI_DMA_C2C_SG_LENGTH_WIDTH 14
|
|
|
|
|
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/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral AXI_DMA_C2C */
|
|
#define XPAR_AXIDMA_0_DEVICE_ID XPAR_AXI_DMA_C2C_DEVICE_ID
|
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#define XPAR_AXIDMA_0_BASEADDR 0x41E00000
|
|
#define XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM 0
|
|
#define XPAR_AXIDMA_0_INCLUDE_MM2S 1
|
|
#define XPAR_AXIDMA_0_INCLUDE_MM2S_DRE 1
|
|
#define XPAR_AXIDMA_0_M_AXI_MM2S_DATA_WIDTH 32
|
|
#define XPAR_AXIDMA_0_INCLUDE_S2MM 1
|
|
#define XPAR_AXIDMA_0_INCLUDE_S2MM_DRE 1
|
|
#define XPAR_AXIDMA_0_M_AXI_S2MM_DATA_WIDTH 32
|
|
#define XPAR_AXIDMA_0_INCLUDE_SG 0
|
|
#define XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL 0
|
|
#define XPAR_AXIDMA_0_NUM_MM2S_CHANNELS 1
|
|
#define XPAR_AXIDMA_0_NUM_S2MM_CHANNELS 1
|
|
#define XPAR_AXIDMA_0_MM2S_BURST_SIZE 64
|
|
#define XPAR_AXIDMA_0_S2MM_BURST_SIZE 64
|
|
#define XPAR_AXIDMA_0_MICRO_DMA 0
|
|
#define XPAR_AXIDMA_0_c_addr_width 32
|
|
#define XPAR_AXIDMA_0_c_sg_length_width 14
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver BRAM */
|
|
#define XPAR_XBRAM_NUM_INSTANCES 7U
|
|
|
|
/* Definitions for peripheral ANT_CONFIG_BRAM_CTRL */
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_DEVICE_ID 0U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_DATA_WIDTH 32U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_ECC 0U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_FAULT_INJECT 0U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_WRITE_ACCESS 0U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_BASEADDR 0xC0000000U
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_HIGHADDR 0xC0001FFFU
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_ANT_CONFIG_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
|
|
|
|
|
|
/* Definitions for peripheral C2C_RX_AXI_BRAM_CTRL */
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_DEVICE_ID 1U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_DATA_WIDTH 32U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_ECC 0U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_FAULT_INJECT 0U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_WRITE_ACCESS 0U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_BASEADDR 0xC6000000U
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_HIGHADDR 0xC6001FFFU
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_C2C_RX_AXI_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
|
|
|
|
|
|
/* Definitions for peripheral C2C_TX_AXI_BRAM_CTRL */
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_DEVICE_ID 2U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_DATA_WIDTH 32U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_ECC 0U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_FAULT_INJECT 0U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_WRITE_ACCESS 0U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_BASEADDR 0xC8000000U
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_HIGHADDR 0xC8001FFFU
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_C2C_TX_AXI_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
|
|
|
|
|
|
/* Definitions for peripheral MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
|
|
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID 3U
|
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH 32U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC 0U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT 0U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0U
|
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 2U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x00000000U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFFU
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
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/* Definitions for peripheral MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
|
|
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID 4U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH 32U
|
|
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC 0U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT 0U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0U
|
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0U
|
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0U
|
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1U
|
|
#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS 2U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR 0x00000000U
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFFU
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
|
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#define XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
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/* Definitions for peripheral RX_FRAME_BRAM_CTRL */
|
|
#define XPAR_RX_FRAME_BRAM_CTRL_DEVICE_ID 5U
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#define XPAR_RX_FRAME_BRAM_CTRL_DATA_WIDTH 32U
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#define XPAR_RX_FRAME_BRAM_CTRL_ECC 0U
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#define XPAR_RX_FRAME_BRAM_CTRL_FAULT_INJECT 0U
|
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#define XPAR_RX_FRAME_BRAM_CTRL_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_RX_FRAME_BRAM_CTRL_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_RX_FRAME_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_RX_FRAME_BRAM_CTRL_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_RX_FRAME_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_RX_FRAME_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
|
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#define XPAR_RX_FRAME_BRAM_CTRL_WRITE_ACCESS 0U
|
|
#define XPAR_RX_FRAME_BRAM_CTRL_S_AXI_BASEADDR 0xC4000000U
|
|
#define XPAR_RX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0xC4000FFFU
|
|
#define XPAR_RX_FRAME_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_RX_FRAME_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
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|
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|
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/* Definitions for peripheral TX_FRAME_BRAM_CTRL */
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_DEVICE_ID 6U
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#define XPAR_TX_FRAME_BRAM_CTRL_DATA_WIDTH 32U
|
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#define XPAR_TX_FRAME_BRAM_CTRL_ECC 0U
|
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#define XPAR_TX_FRAME_BRAM_CTRL_FAULT_INJECT 0U
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_WRITE_ACCESS 0U
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_S_AXI_BASEADDR 0xC2000000U
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0xC2000FFFU
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_TX_FRAME_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
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|
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|
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/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral ANT_CONFIG_BRAM_CTRL */
|
|
#define XPAR_BRAM_0_DEVICE_ID XPAR_ANT_CONFIG_BRAM_CTRL_DEVICE_ID
|
|
#define XPAR_BRAM_0_DATA_WIDTH 32U
|
|
#define XPAR_BRAM_0_ECC 0U
|
|
#define XPAR_BRAM_0_FAULT_INJECT 0U
|
|
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0U
|
|
#define XPAR_BRAM_0_WRITE_ACCESS 0U
|
|
#define XPAR_BRAM_0_BASEADDR 0xC0000000U
|
|
#define XPAR_BRAM_0_HIGHADDR 0xC0001FFFU
|
|
#define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU
|
|
|
|
/* Canonical definitions for peripheral C2C_RX_AXI_BRAM_CTRL */
|
|
#define XPAR_BRAM_1_DEVICE_ID XPAR_C2C_RX_AXI_BRAM_CTRL_DEVICE_ID
|
|
#define XPAR_BRAM_1_DATA_WIDTH 32U
|
|
#define XPAR_BRAM_1_ECC 0U
|
|
#define XPAR_BRAM_1_FAULT_INJECT 0U
|
|
#define XPAR_BRAM_1_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_1_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_1_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_BRAM_1_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 0U
|
|
#define XPAR_BRAM_1_WRITE_ACCESS 0U
|
|
#define XPAR_BRAM_1_BASEADDR 0xC6000000U
|
|
#define XPAR_BRAM_1_HIGHADDR 0xC6001FFFU
|
|
#define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU
|
|
|
|
/* Canonical definitions for peripheral C2C_TX_AXI_BRAM_CTRL */
|
|
#define XPAR_BRAM_2_DEVICE_ID XPAR_C2C_TX_AXI_BRAM_CTRL_DEVICE_ID
|
|
#define XPAR_BRAM_2_DATA_WIDTH 32U
|
|
#define XPAR_BRAM_2_ECC 0U
|
|
#define XPAR_BRAM_2_FAULT_INJECT 0U
|
|
#define XPAR_BRAM_2_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_2_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_2_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_BRAM_2_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_BRAM_2_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_BRAM_2_ECC_ONOFF_RESET_VALUE 0U
|
|
#define XPAR_BRAM_2_WRITE_ACCESS 0U
|
|
#define XPAR_BRAM_2_BASEADDR 0xC8000000U
|
|
#define XPAR_BRAM_2_HIGHADDR 0xC8001FFFU
|
|
#define XPAR_BRAM_2_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_BRAM_2_CTRL_HIGHADDR 0xFFFFFFFEU
|
|
|
|
/* Canonical definitions for peripheral MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
|
|
#define XPAR_BRAM_3_DEVICE_ID XPAR_MICROBLAZE_PS_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID
|
|
#define XPAR_BRAM_3_DATA_WIDTH 32U
|
|
#define XPAR_BRAM_3_ECC 0U
|
|
#define XPAR_BRAM_3_FAULT_INJECT 0U
|
|
#define XPAR_BRAM_3_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_3_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_3_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_BRAM_3_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_BRAM_3_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_BRAM_3_ECC_ONOFF_RESET_VALUE 1U
|
|
#define XPAR_BRAM_3_WRITE_ACCESS 2U
|
|
#define XPAR_BRAM_3_BASEADDR 0x00000000U
|
|
#define XPAR_BRAM_3_HIGHADDR 0x0003FFFFU
|
|
#define XPAR_BRAM_3_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_BRAM_3_CTRL_HIGHADDR 0xFFFFFFFEU
|
|
|
|
/* Canonical definitions for peripheral MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
|
|
#define XPAR_BRAM_4_DEVICE_ID XPAR_MICROBLAZE_PS_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID
|
|
#define XPAR_BRAM_4_DATA_WIDTH 32U
|
|
#define XPAR_BRAM_4_ECC 0U
|
|
#define XPAR_BRAM_4_FAULT_INJECT 0U
|
|
#define XPAR_BRAM_4_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_4_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_4_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_BRAM_4_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_BRAM_4_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_BRAM_4_ECC_ONOFF_RESET_VALUE 1U
|
|
#define XPAR_BRAM_4_WRITE_ACCESS 2U
|
|
#define XPAR_BRAM_4_BASEADDR 0x00000000U
|
|
#define XPAR_BRAM_4_HIGHADDR 0x0003FFFFU
|
|
#define XPAR_BRAM_4_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_BRAM_4_CTRL_HIGHADDR 0xFFFFFFFEU
|
|
|
|
/* Canonical definitions for peripheral RX_FRAME_BRAM_CTRL */
|
|
#define XPAR_BRAM_5_DEVICE_ID XPAR_RX_FRAME_BRAM_CTRL_DEVICE_ID
|
|
#define XPAR_BRAM_5_DATA_WIDTH 32U
|
|
#define XPAR_BRAM_5_ECC 0U
|
|
#define XPAR_BRAM_5_FAULT_INJECT 0U
|
|
#define XPAR_BRAM_5_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_5_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_5_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_BRAM_5_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_BRAM_5_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_BRAM_5_ECC_ONOFF_RESET_VALUE 0U
|
|
#define XPAR_BRAM_5_WRITE_ACCESS 0U
|
|
#define XPAR_BRAM_5_BASEADDR 0xC4000000U
|
|
#define XPAR_BRAM_5_HIGHADDR 0xC4000FFFU
|
|
#define XPAR_BRAM_5_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_BRAM_5_CTRL_HIGHADDR 0xFFFFFFFEU
|
|
|
|
/* Canonical definitions for peripheral TX_FRAME_BRAM_CTRL */
|
|
#define XPAR_BRAM_6_DEVICE_ID XPAR_TX_FRAME_BRAM_CTRL_DEVICE_ID
|
|
#define XPAR_BRAM_6_DATA_WIDTH 32U
|
|
#define XPAR_BRAM_6_ECC 0U
|
|
#define XPAR_BRAM_6_FAULT_INJECT 0U
|
|
#define XPAR_BRAM_6_CE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_6_UE_FAILING_REGISTERS 0U
|
|
#define XPAR_BRAM_6_ECC_STATUS_REGISTERS 0U
|
|
#define XPAR_BRAM_6_CE_COUNTER_WIDTH 0U
|
|
#define XPAR_BRAM_6_ECC_ONOFF_REGISTER 0U
|
|
#define XPAR_BRAM_6_ECC_ONOFF_RESET_VALUE 0U
|
|
#define XPAR_BRAM_6_WRITE_ACCESS 0U
|
|
#define XPAR_BRAM_6_BASEADDR 0xC2000000U
|
|
#define XPAR_BRAM_6_HIGHADDR 0xC2000FFFU
|
|
#define XPAR_BRAM_6_CTRL_BASEADDR 0xFFFFFFFFU
|
|
#define XPAR_BRAM_6_CTRL_HIGHADDR 0xFFFFFFFEU
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
|
/* Definitions for peripheral AXI_SPI_ENGINE_AXI_SPI_ENGINE */
|
|
#define XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR 0x44A00000
|
|
#define XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_HIGHADDR 0x44A0FFFF
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver GPIO */
|
|
#define XPAR_XGPIO_NUM_INSTANCES 3
|
|
|
|
/* Definitions for peripheral AXI_GPIO */
|
|
#define XPAR_AXI_GPIO_BASEADDR 0x40000000
|
|
#define XPAR_AXI_GPIO_HIGHADDR 0x4000FFFF
|
|
#define XPAR_AXI_GPIO_DEVICE_ID 0
|
|
#define XPAR_AXI_GPIO_INTERRUPT_PRESENT 0
|
|
#define XPAR_AXI_GPIO_IS_DUAL 1
|
|
|
|
|
|
/* Definitions for peripheral STATUS_GPIO_I */
|
|
#define XPAR_STATUS_GPIO_I_BASEADDR 0x40010000
|
|
#define XPAR_STATUS_GPIO_I_HIGHADDR 0x4001FFFF
|
|
#define XPAR_STATUS_GPIO_I_DEVICE_ID 1
|
|
#define XPAR_STATUS_GPIO_I_INTERRUPT_PRESENT 0
|
|
#define XPAR_STATUS_GPIO_I_IS_DUAL 1
|
|
|
|
|
|
/* Definitions for peripheral STATUS_GPIO_O */
|
|
#define XPAR_STATUS_GPIO_O_BASEADDR 0x40020000
|
|
#define XPAR_STATUS_GPIO_O_HIGHADDR 0x4002FFFF
|
|
#define XPAR_STATUS_GPIO_O_DEVICE_ID 2
|
|
#define XPAR_STATUS_GPIO_O_INTERRUPT_PRESENT 0
|
|
#define XPAR_STATUS_GPIO_O_IS_DUAL 1
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral AXI_GPIO */
|
|
#define XPAR_GPIO_0_BASEADDR 0x40000000
|
|
#define XPAR_GPIO_0_HIGHADDR 0x4000FFFF
|
|
#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_DEVICE_ID
|
|
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
|
|
#define XPAR_GPIO_0_IS_DUAL 1
|
|
|
|
/* Canonical definitions for peripheral STATUS_GPIO_I */
|
|
#define XPAR_GPIO_1_BASEADDR 0x40010000
|
|
#define XPAR_GPIO_1_HIGHADDR 0x4001FFFF
|
|
#define XPAR_GPIO_1_DEVICE_ID XPAR_STATUS_GPIO_I_DEVICE_ID
|
|
#define XPAR_GPIO_1_INTERRUPT_PRESENT 0
|
|
#define XPAR_GPIO_1_IS_DUAL 1
|
|
|
|
/* Canonical definitions for peripheral STATUS_GPIO_O */
|
|
#define XPAR_GPIO_2_BASEADDR 0x40020000
|
|
#define XPAR_GPIO_2_HIGHADDR 0x4002FFFF
|
|
#define XPAR_GPIO_2_DEVICE_ID XPAR_STATUS_GPIO_O_DEVICE_ID
|
|
#define XPAR_GPIO_2_INTERRUPT_PRESENT 0
|
|
#define XPAR_GPIO_2_IS_DUAL 1
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 6
|
|
#define XPAR_XINTC_HAS_IPR 1
|
|
#define XPAR_XINTC_HAS_SIE 1
|
|
#define XPAR_XINTC_HAS_CIE 1
|
|
#define XPAR_XINTC_HAS_IVR 1
|
|
/* Definitions for driver INTC */
|
|
#define XPAR_XINTC_NUM_INSTANCES 1
|
|
|
|
/* Definitions for peripheral AXI_INTC */
|
|
#define XPAR_AXI_INTC_DEVICE_ID 0
|
|
#define XPAR_AXI_INTC_BASEADDR 0x41200000
|
|
#define XPAR_AXI_INTC_HIGHADDR 0x4120FFFF
|
|
#define XPAR_AXI_INTC_KIND_OF_INTR 0xFFFFFFC0
|
|
#define XPAR_AXI_INTC_HAS_FAST 0
|
|
#define XPAR_AXI_INTC_IVAR_RESET_VALUE 0x0000000000000010
|
|
#define XPAR_AXI_INTC_NUM_INTR_INPUTS 6
|
|
#define XPAR_AXI_INTC_ADDR_WIDTH 32
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
|
|
#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
|
|
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_AXI_INTC_DEVICE_ID
|
|
#define XPAR_AXI_INTC_TYPE 0U
|
|
#define XPAR_SYSTEM_PHY_IRQ_MASK 0X000001U
|
|
#define XPAR_AXI_INTC_SYSTEM_PHY_IRQ_INTR 0U
|
|
#define XPAR_AXI_DMA_C2C_MM2S_INTROUT_MASK 0X000002U
|
|
#define XPAR_AXI_INTC_AXI_DMA_C2C_MM2S_INTROUT_INTR 1U
|
|
#define XPAR_AXI_DMA_C2C_S2MM_INTROUT_MASK 0X000004U
|
|
#define XPAR_AXI_INTC_AXI_DMA_C2C_S2MM_INTROUT_INTR 2U
|
|
#define XPAR_SYSTEM_PHY_5MS_MASK 0X000008U
|
|
#define XPAR_AXI_INTC_SYSTEM_PHY_5MS_INTR 3U
|
|
#define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000010U
|
|
#define XPAR_AXI_INTC_AXI_TIMER_0_INTERRUPT_INTR 4U
|
|
#define XPAR_XADC_WIZ_0_IP2INTC_IRPT_MASK 0X000020U
|
|
#define XPAR_AXI_INTC_XADC_WIZ_0_IP2INTC_IRPT_INTR 5U
|
|
|
|
/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral AXI_INTC */
|
|
#define XPAR_INTC_0_DEVICE_ID XPAR_AXI_INTC_DEVICE_ID
|
|
#define XPAR_INTC_0_BASEADDR 0x41200000U
|
|
#define XPAR_INTC_0_HIGHADDR 0x4120FFFFU
|
|
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFC0U
|
|
#define XPAR_INTC_0_HAS_FAST 0U
|
|
#define XPAR_INTC_0_IVAR_RESET_VALUE 0x0000000000000010U
|
|
#define XPAR_INTC_0_NUM_INTR_INPUTS 6U
|
|
#define XPAR_INTC_0_ADDR_WIDTH 32U
|
|
#define XPAR_INTC_0_INTC_TYPE 0U
|
|
|
|
#define XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID XPAR_AXI_INTC_AXI_DMA_C2C_MM2S_INTROUT_INTR
|
|
#define XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID XPAR_AXI_INTC_AXI_DMA_C2C_S2MM_INTROUT_INTR
|
|
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_AXI_INTC_AXI_TIMER_0_INTERRUPT_INTR
|
|
#define XPAR_INTC_0_SYSMON_0_VEC_ID XPAR_AXI_INTC_XADC_WIZ_0_IP2INTC_IRPT_INTR
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver SYSMON */
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#define XPAR_XSYSMON_NUM_INSTANCES 1U
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/* Definitions for peripheral XADC_WIZ_0 */
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#define XPAR_XADC_WIZ_0_IP_TYPE 0U
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#define XPAR_XADC_WIZ_0_DEVICE_ID 0U
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#define XPAR_XADC_WIZ_0_BASEADDR 0x44A20000U
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#define XPAR_XADC_WIZ_0_HIGHADDR 0x44A2FFFFU
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#define XPAR_XADC_WIZ_0_INCLUDE_INTR 1U
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/******************************************************************/
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/* Canonical definitions for peripheral XADC_WIZ_0 */
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#define XPAR_SYSMON_0_IP_TYPE 0U
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#define XPAR_SYSMON_0_DEVICE_ID XPAR_XADC_WIZ_0_DEVICE_ID
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#define XPAR_SYSMON_0_BASEADDR 0x44A20000U
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#define XPAR_SYSMON_0_HIGHADDR 0x44A2FFFFU
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#define XPAR_SYSMON_0_INCLUDE_INTR 1U
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/******************************************************************/
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/* Definitions for driver TMRCTR */
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#define XPAR_XTMRCTR_NUM_INSTANCES 1U
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/* Definitions for peripheral AXI_TIMER_0 */
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#define XPAR_AXI_TIMER_0_DEVICE_ID 0U
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#define XPAR_AXI_TIMER_0_BASEADDR 0x41C00000U
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#define XPAR_AXI_TIMER_0_HIGHADDR 0x41C0FFFFU
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#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 150000000U
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/******************************************************************/
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/* Canonical definitions for peripheral AXI_TIMER_0 */
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#define XPAR_TMRCTR_0_DEVICE_ID 0U
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#define XPAR_TMRCTR_0_BASEADDR 0x41C00000U
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#define XPAR_TMRCTR_0_HIGHADDR 0x41C0FFFFU
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#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ
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/******************************************************************/
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#endif /* end of protection macro */
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