forked from gatsby/datalink_repo
533 lines
22 KiB
C
533 lines
22 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file pvr.h
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*
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* @addtogroup microblaze_pvr_macros Microblaze PVR access routines and macros
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*
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* MicroBlaze processor v5.00.a and later versions have configurable
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* Processor Version Registers (PVRs). The contents of the PVR are captured
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* using the pvr_t data structure, which is defined as an array of 32-bit words,
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* with each word corresponding to a PVR register on hardware. The number of PVR
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* words is determined by the number of PVRs configured in the hardware. You should
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* not attempt to access PVR registers that are not present in hardware, as the
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* pvr_t data structure is resized to hold only as many PVRs as are present in
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* hardware.
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* To access information in the PVR:
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* 1. Use the microblaze_get_pvr() function to populate the PVR data into a pvr_t
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* data structure.
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* 2. In subsequent steps, you can use any one of the PVR access macros list to
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* get individual data stored in the PVR.
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* 3. pvr.h header file must be included to source to use PVR macros.
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*
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* @{
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*
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******************************************************************************/
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#ifndef _PVR_H
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#define _PVR_H
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xparameters.h"
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#include "mb_interface.h"
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#include "bspconfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Defs */
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typedef struct pvr_s {
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#ifdef MICROBLAZE_PVR_FULL
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unsigned int pvr[16];
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#else
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unsigned int pvr[1];
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#endif
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} pvr_t;
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#define getpvr(pvrid, val) asm volatile ("mfs\t%0,rpvr" stringify(pvrid) "\n\t" : "=d" (val))
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/* Basic PVR mask */
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#define MICROBLAZE_PVR0_PVR_FULL_MASK 0x80000000
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#define MICROBLAZE_PVR0_USE_BARREL_MASK 0x40000000
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#define MICROBLAZE_PVR0_USE_DIV_MASK 0x20000000
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#define MICROBLAZE_PVR0_USE_HW_MUL_MASK 0x10000000
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#define MICROBLAZE_PVR0_USE_FPU_MASK 0x08000000
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#define MICROBLAZE_PVR0_USE_EXCEPTION_MASK 0x04000000
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#define MICROBLAZE_PVR0_USE_ICACHE_MASK 0x02000000
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#define MICROBLAZE_PVR0_USE_DCACHE_MASK 0x01000000
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#define MICROBLAZE_PVR0_USE_MMU_MASK 0x00800000
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#define MICROBLAZE_PVR0_USE_BTC_MASK 0x00400000
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#define MICROBLAZE_PVR0_ENDIANNESS_MASK 0x00200000
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#define MICROBLAZE_PVR0_FAULT_TOLERANT_MASK 0x00100000
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#define MICROBLAZE_PVR0_STACK_PROTECTION_MASK 0x00080000
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#define MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK 0x0000FF00
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#define MICROBLAZE_PVR0_USER1_MASK 0x000000FF
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/* User 2 PVR mask */
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#define MICROBLAZE_PVR1_USER2_MASK 0xFFFFFFFF
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/* Configuration PVR masks */
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#define MICROBLAZE_PVR2_D_AXI_MASK 0x80000000
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#define MICROBLAZE_PVR2_D_LMB_MASK 0x40000000
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#define MICROBLAZE_PVR2_D_PLB_MASK 0x02000000
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#define MICROBLAZE_PVR2_I_AXI_MASK 0x20000000
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#define MICROBLAZE_PVR2_I_LMB_MASK 0x10000000
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#define MICROBLAZE_PVR2_I_PLB_MASK 0x01000000
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#define MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
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#define MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
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#define MICROBLAZE_PVR2_INTERCONNECT_MASK 0x00800000
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#define MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK 0x00400000
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#define MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK 0x00080000
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#define MICROBLAZE_PVR2_USE_MSR_INSTR_MASK 0x00020000
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#define MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK 0x00010000
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#define MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK 0x00008000
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#define MICROBLAZE_PVR2_USE_BARREL_MASK 0x00004000
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#define MICROBLAZE_PVR2_USE_DIV_MASK 0x00002000
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#define MICROBLAZE_PVR2_USE_HW_MUL_MASK 0x00001000
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#define MICROBLAZE_PVR2_USE_FPU_MASK 0x00000800
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#define MICROBLAZE_PVR2_USE_FPU2_MASK 0x00000200
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#define MICROBLAZE_PVR2_USE_MUL64_MASK 0x00000400
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#define MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK 0x00000040
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#define MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK 0x00000020
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#define MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK 0x00000010
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#define MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK 0x00000008
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#define MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK 0x00000004
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#define MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK 0x00000100
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#define MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK 0x00000080
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#define MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK 0x00000002
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#define MICROBLAZE_PVR2_FPU_EXCEPTION_MASK 0x00000001
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#define MICROBLAZE_PVR2_FSL_EXCEPTION_MASK 0x00040000
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/* Debug and exception PVR masks */
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#define MICROBLAZE_PVR3_DEBUG_ENABLED_MASK 0x80000000
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#define MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
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#define MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
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#define MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
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#define MICROBLAZE_PVR3_FSL_LINKS_MASK 0x00000380
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#define MICROBLAZE_PVR3_BTC_SIZE_MASK 0x00000007
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/* ICache config PVR masks */
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#define MICROBLAZE_PVR4_USE_ICACHE_MASK 0x80000000
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#define MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
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#define MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
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#define MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
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#define MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
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#define MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK 0x00008000
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#define MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK 0x00002000
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#define MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK 0x00001C00
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#define MICROBLAZE_PVR4_ICACHE_STREAMS_MASK 0x00000300
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#define MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
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#define MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK 0x00000040
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/* DCache config PVR masks */
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#define MICROBLAZE_PVR5_USE_DCACHE_MASK 0x80000000
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#define MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
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#define MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
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#define MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
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#define MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
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#define MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK 0x00008000
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#define MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK 0x00004000
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#define MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK 0x00002000
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#define MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK 0x00001C00
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#define MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
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#define MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK 0x00000040
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#if defined(__arch64__)
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/* ICache base address PVR mask */
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#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFFFFFFFFFF
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/* ICache high address PVR mask */
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#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFFFFFFFFFF
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/* DCache base address PVR mask */
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#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFFFFFFFFFF
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/* DCache high address PVR mask */
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#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFFFFFFFFFF
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#else
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/* ICache base address PVR mask */
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#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
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/* ICache high address PVR mask */
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#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
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/* DCache base address PVR mask */
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#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
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/* DCache high address PVR mask */
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#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
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#endif
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/* Target family PVR mask */
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#define MICROBLAZE_PVR10_TARGET_FAMILY_MASK 0xFF000000
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/* MSR Reset value PVR mask */
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#define MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK 0x000007FF
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/* MMU value PVR mask */
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#define MICROBLAZE_PVR11_MMU_MASK 0xC0000000
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#define MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK 0x38000000
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#define MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK 0x07000000
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#define MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK 0x00C00000
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#define MICROBLAZE_PVR11_MMU_ZONES_MASK 0x003E0000
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#define MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK 0x00010000
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/* PVR access macros */
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/**
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Return non-zero integer if PVR is of type FULL, 0 if basic
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_IS_FULL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_PVR_FULL_MASK)
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/**
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Return non-zero integer if hardware barrel shifter present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BARREL_MASK)
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/**
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Return non-zero integer if hardware divider present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_USE_DIV(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DIV_MASK)
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/**
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Return non-zero integer if hardware multiplier present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_HW_MUL_MASK)
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/**
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Return non-zero integer if hardware floating point unit (FPU) present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_USE_FPU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_FPU_MASK)
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/**
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Return non-zero integer if I-cache present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_ICACHE_MASK)
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/**
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Return non-zero integer if D-cache present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DCACHE_MASK)
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#define MICROBLAZE_PVR_USE_MMU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_MMU_MASK)
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#define MICROBLAZE_PVR_USE_BTC(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BTC_MASK)
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#define MICROBLAZE_PVR_ENDIANNESS(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_ENDIANNESS_MASK)
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#define MICROBLAZE_PVR_FAULT_TOLERANT(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_FAULT_TOLERANT_MASK)
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#define MICROBLAZE_PVR_STACK_PROTECTION(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_STACK_PROTECTION_MASK)
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/**
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Return MicroBlaze processor version encoding. Refer to the MicroBlaze Processor
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Reference Guide (UG081) for mappings from encodings to actual hardware versions.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_MICROBLAZE_VERSION(_pvr) ((_pvr.pvr[0] & MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK) >> 8)
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/**
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Return the USER1 field stored in the PVR.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_USER1(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USER1_MASK)
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/**
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Return the USER2 field stored in the PVR.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_USER2(_pvr) (_pvr.pvr[1] & MICROBLAZE_PVR1_USER2_MASK)
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#define MICROBLAZE_PVR_D_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_AXI_MASK)
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/**
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Return non-zero integer if Data Side PLB
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interface is present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_D_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_LMB_MASK)
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/**
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Return non-zero integer if Data Side PLB interface is present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_D_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_PLB_MASK)
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#define MICROBLAZE_PVR_I_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_AXI_MASK)
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/**
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Return non-zero integer if Instruction Side Local Memory Bus (LMB) interface present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_I_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_LMB_MASK)
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/**
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Return non-zero integer if Instruction Side PLB interface present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_I_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_PLB_MASK)
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/**
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Return non-zero integer if interrupts are configured as edge-triggered.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_INTERRUPT_IS_EDGE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK)
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/**
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Return non-zero integer if interrupts are configured as positive edge triggered.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_EDGE_IS_POSITIVE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK)
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/**
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Return non-zero if MicroBlaze processor has PLB interconnect; otherwise return zero.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERCONNECT_MASK)
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#define MICROBLAZE_PVR_STREAM_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK)
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#define MICROBLAZE_PVR_USE_EXTENDED_FSL_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK)
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#define MICROBLAZE_PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MSR_INSTR_MASK)
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#define MICROBLAZE_PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK)
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#define MICROBLAZE_PVR_AREA_OPTIMIZED(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK)
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/**
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Return non-zero integer if MicroBlaze processor supports 64-bit products for
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multiplies.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MUL64_MASK)
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/**
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Return non-zero integer if opcode 0x0 is treated as an illegal opcode.
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multiplies.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_OPCODE_0x0_ILLEGAL(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK)
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/**
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Return non-zero integer if unaligned exceptions are supported.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_UNALIGNED_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK)
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/**
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Return non-zero integer if illegal opcode exceptions are supported.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_ILL_OPCODE_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK)
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#define MICROBLAZE_PVR_M_AXI_I_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK)
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/**
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Return non-zero integer if I-PLB exceptions are supported.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_IPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK)
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#define MICROBLAZE_PVR_M_AXI_D_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK)
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/**
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Return non-zero integer if I-PLB exceptions are supported.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_DPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK)
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/**
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Return non-zero integer if divide by zero exceptions are supported.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_DIV_ZERO_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK)
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/**
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Return non-zero integer if FPU exceptions are supported.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FPU_EXCEPTION_MASK)
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/**
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Return non-zero integer if FSL exceptions are present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FSL_EXCEPTION_MASK)
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/**
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Return non-zero integer if debug is enabled.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_DEBUG_ENABLED_MASK)
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/**
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Return the number of hardware PC breakpoints available.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_NUMBER_OF_PC_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
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/**
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Return the number of read address hardware watchpoints supported.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
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/**
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Return the number of write address hardware watchpoints supported.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
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/**
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Return the number of FSL links present.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_FSL_LINKS_MASK) >> 7)
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#define MICROBLAZE_PVR_BTC_SIZE(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_BTC_SIZE_MASK)
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/**
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Return the number of address tag bits for the I-cache.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_ICACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
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/**
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Return non-zero if writes to I-caches are allowed.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_ICACHE_ALLOW_WR(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK)
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/**
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Return the length of each I-cache line in bytes.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_ICACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK) >> 21))
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/**
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Return the size of the D-cache in bytes.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_ICACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
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#define MICROBLAZE_PVR_ICACHE_ALWAYS_USED(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK)
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#define MICROBLAZE_PVR_ICACHE_INTERFACE(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK)
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#define MICROBLAZE_PVR_ICACHE_VICTIMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK) >> 10)
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#define MICROBLAZE_PVR_ICACHE_STREAMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_STREAMS_MASK) >> 8)
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#define MICROBLAZE_PVR_ICACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK)
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#define MICROBLAZE_PVR_ICACHE_DATA_WIDTH(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK)
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/**
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Return the number of address tag bits for the D-cache.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_DCACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
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/**
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Return non-zero if writes to D-cache are allowed.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_DCACHE_ALLOW_WR(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK)
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/**
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Return the length of each line in the D-cache in bytes.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_DCACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK) >> 21))
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/**
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Return the size of the D-cache in bytes.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_DCACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
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#define MICROBLAZE_PVR_DCACHE_ALWAYS_USED(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK)
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#define MICROBLAZE_PVR_DCACHE_USE_WRITEBACK(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK)
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#define MICROBLAZE_PVR_DCACHE_INTERFACE(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK)
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#define MICROBLAZE_PVR_DCACHE_VICTIMS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK) >> 10)
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#define MICROBLAZE_PVR_DCACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK)
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#define MICROBLAZE_PVR_DCACHE_DATA_WIDTH(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK)
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/**
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|
Return the base address of the I-cache.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_ICACHE_BASEADDR(_pvr) (_pvr.pvr[6] & MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK)
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/**
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|
Return the high address of the I-cache.
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@param _pvr pvr data structure
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*/
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#define MICROBLAZE_PVR_ICACHE_HIGHADDR(_pvr) (_pvr.pvr[7] & MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK)
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/**
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|
Return the base address of the D-cache.
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|
@param _pvr pvr data structure
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|
*/
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#define MICROBLAZE_PVR_DCACHE_BASEADDR(_pvr) (_pvr.pvr[8] & MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK)
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/**
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|
Return the high address of the D-cache.
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|
@param _pvr pvr data structure
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|
*/
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#define MICROBLAZE_PVR_DCACHE_HIGHADDR(_pvr) (_pvr.pvr[9] & MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK)
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/**
|
|
Return the encoded target family identifier.
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|
@param _pvr pvr data structure
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|
*/
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#define MICROBLAZE_PVR_TARGET_FAMILY(_pvr) ((_pvr.pvr[10] & MICROBLAZE_PVR10_TARGET_FAMILY_MASK) >> 24)
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/**
|
|
Refer to the MicroBlaze Processor Reference Guide (UG081) for mappings from encodings
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|
to target family name strings.
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|
@param _pvr pvr data structure
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|
*/
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#define MICROBLAZE_PVR_MSR_RESET_VALUE(_pvr) (_pvr.pvr[11] & MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK)
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/**
|
|
Returns the value of C_USE_MMU. Refer to the MicroBlaze Processor Reference Guide
|
|
(UG081) for mappings from MMU type values to MMU function.
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|
@param _pvr pvr data structure
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|
*/
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|
#define MICROBLAZE_PVR_MMU_TYPE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_MASK) >> 30)
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#define MICROBLAZE_PVR_MMU_ITLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK) >> 27)
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#define MICROBLAZE_PVR_MMU_DTLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK) >> 24)
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#define MICROBLAZE_PVR_MMU_TLB_ACCESS(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK) >> 22)
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#define MICROBLAZE_PVR_MMU_ZONES(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ZONES_MASK) >> 17)
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#define MICROBLAZE_PVR_MMU_PRIVILEGED_INSTR(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK) >> 16)
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|
|
/* Protos */
|
|
int microblaze_get_pvr (pvr_t *pvr);
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|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif /* _PVR_H */
|
|
/**
|
|
* @} End of "addtogroup microblaze_pvr_macros".
|
|
*/
|