forked from 0xha0/datalink_repo
133 lines
3.5 KiB
C
133 lines
3.5 KiB
C
#include "dev_profile.h"
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#include "../config/app_config.h"
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#include "../drivers/platform/xilinx_gpio.h"
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#include "../drivers/axi_core/spi_engine/spi_engine.h"
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#include "../drivers/frequency/hmc7044/hmc7044.h"
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static struct spi_engine_init_param spi_engine_param = {
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.ref_clk_hz = HMC7044_SPI_ENGINE_REF_CLK,
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.type = SPI_ENGINE,
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.spi_engine_baseaddr = HMC7044_SPI_ENGINE_BASEADDR,
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.cs_delay = HMC7044_SPI_ENGINE_CS_DELAY,
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.data_width = HMC7044_SPI_ENGINE_DATA_WIDTH
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};
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//static struct xil_gpio_init_param xil_gpio_param = {
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// .type = GPIO_PS,
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// .device_id = AD9361_GPIO_DEVICE_ID
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//};
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// hmc7044 spi settings
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static struct spi_init_param hmc7044_spi_init_param = {
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.device_id = HMC7044_SPI_DEVICE_ID,
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.max_speed_hz = HMC7044_SPI_ENGINE_MAX_SPEED,
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.mode = SPI_MODE_4,
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.chip_select = HMC7044_SPI_CS_HMC7044,
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.platform_ops = &spi_eng_platform_ops,
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.extra = &spi_engine_param
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};
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// hmc7044 channel specifications
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struct hmc7044_chan_spec hmc7044_chan_spec[4] = {
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/* AD9361_XTAL */
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{
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.disable = 0,
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.num = 3,
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.divider = 100,
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.coarse_delay = 0,
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.fine_delay = 0,
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.high_performance_mode_dis = true,
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.start_up_mode_dynamic_enable = false,
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.dynamic_driver_enable = false,
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.output_control0_rb4_enable = true,
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.force_mute_enable = false,
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.driver_mode = CML,
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.driver_impedance = INTERNAL_100OHM_PER_PIN,
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.out_mux_mode = CHANNEL_DIV
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},
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/* FPGA_DAC_LOGIC_CLK */
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{
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.disable = 0,
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.num = 4,
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.divider = 10,
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.coarse_delay = 0,
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.fine_delay = 0,
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.high_performance_mode_dis = true,
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.start_up_mode_dynamic_enable = false,
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.dynamic_driver_enable = false,
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.output_control0_rb4_enable = true,
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.force_mute_enable = false,
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.driver_mode = CML,
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.driver_impedance = INTERNAL_100OHM_PER_PIN,
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.out_mux_mode = CHANNEL_DIV
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},
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/* B_AD9361_XTAL */
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{
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.disable = 0,
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.num = 12,
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.divider = 100,
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.coarse_delay = 0,
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.fine_delay = 0,
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.high_performance_mode_dis = false,
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.start_up_mode_dynamic_enable = false,
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.dynamic_driver_enable = false,
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.output_control0_rb4_enable = true,
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.force_mute_enable = false,
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.driver_mode = CML,
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.driver_impedance = INTERNAL_100OHM_PER_PIN,
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.out_mux_mode = CHANNEL_DIV
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},
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/* AD9361_RX_EXT_LO */
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{
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.disable = 0,
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.num = 13,
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.divider = 10,
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.coarse_delay = 0,
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.fine_delay = 0,
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.high_performance_mode_dis = false,
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.start_up_mode_dynamic_enable = false,
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.dynamic_driver_enable = false,
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.output_control0_rb4_enable = true,
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.force_mute_enable = false,
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.driver_mode = CML,
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.driver_impedance = INTERNAL_100OHM_PER_PIN,
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.out_mux_mode = CHANNEL_DIV
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},
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};
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// hmc7044 default configurations
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struct hmc7044_init_param hmc7044_default_init_param = {
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.spi_init = &hmc7044_spi_init_param,
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.clkin_freq = {0, 100000000, 0, 0},
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.vcxo_freq = 100000000,
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.pll2_freq = 2500000000,
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.pll1_loop_bw = 200,
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.sysref_timer_div = 1536,
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.in_buf_mode = {
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BUFFER_DISABLE,
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ENABLE_AC_COUPLE | ENABLE_INTERNAL_TERM | BUFFER_ENABLE,
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BUFFER_DISABLE,
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BUFFER_DISABLE,
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ENABLE_AC_COUPLE | ENABLE_INTERNAL_TERM | BUFFER_ENABLE
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},
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.gpi_ctrl = {
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GPI_DISABLE,
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GPI_DISABLE,
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CHIP_SLEEP_MODE,
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PULSE_GEN_REQUSET
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},
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.gpo_ctrl = {
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PLL1_LOCK_DETECT | GPO_CMOS_MODE,
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PLL2_LOCK_DETECT | GPO_CMOS_MODE,
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GPO_DISABLE,
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GPO_DISABLE
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},
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.num_channels = 4,
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.pll1_ref_prio_ctrl = 0xE4,
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.sync_pin_mode = SYNC_MULTICHIP,
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.high_performance_mode_clock_dist_en = false,
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.pulse_gen_mode = PULSE_ONE,
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.channels = hmc7044_chan_spec
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};
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