diff --git a/.gitignore b/.gitignore index fe36af2..db490e2 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,5 @@ adi_library c/** ip -.tags \ No newline at end of file +.tags +sim/sim_data \ No newline at end of file diff --git a/hdl/ApproxAbs_18bit.v b/hdl/ApproxAbs_18bit.v index f0b975f..a74f614 100644 --- a/hdl/ApproxAbs_18bit.v +++ b/hdl/ApproxAbs_18bit.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/ApproxAbs_v2.v b/hdl/ApproxAbs_v2.v index 9a85724..8c7a8d8 100644 --- a/hdl/ApproxAbs_v2.v +++ b/hdl/ApproxAbs_v2.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/CCSDS_LDPC_DEC_K1024_R12.v b/hdl/CCSDS_LDPC_DEC_K1024_R12.v new file mode 100644 index 0000000..ed74b81 --- /dev/null +++ b/hdl/CCSDS_LDPC_DEC_K1024_R12.v @@ -0,0 +1,145 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: CCSDS_LDPC_DEC_K1024_R12 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module CCSDS_LDPC_DEC_K1024_R12 #( + parameter WIDTH = 4'd8, + parameter MAX_ITER_NUM = 6'd14, + parameter OUT_ONLY_INFORMATION = 1'b0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字 +) ( + input clk, //工作时钟,100MHz + input Rst, //同步复位信号,高有效 + input FrameSync, //帧同步标志,高脉冲 + input Nd, //译码输入数据有效标志,高有效 + input [WIDTH-1:0] Din, //译码输入数据,软信息,数据速率约为12.5Mbps + + output reg LDPC_SyncOut = 1'b0, //LDPC模块帧同步输出信号,高脉冲,指示帧起点 + output reg Rdy = 1'b0, //译码输出信号有效标志,高有效 + output reg [0:0] LDPC_Dout = 1'b0, //译码输出信号 + output reg [8:0] good_frames = 9'd0, //译码好帧计数 + output reg [8:0] bad_frames = 9'd0, //译码坏帧计数 + output reg [8:0] total_frames = 9'd0 //译码总帧计数 +); + + reg rst_MS = 1'd0; + reg framesync_MS = 1'd0; + reg nd_MS = 1'd0; + reg [WIDTH-1:0] din_MS = 8'd0; + reg oe_MS = 1'd0; + wire deal_end_MS; + wire [WIDTH-1:0] dout01_MS; + wire [WIDTH-1:0] dout02_MS; + wire [WIDTH-1:0] dout03_MS; + wire [WIDTH-1:0] dout04_MS; + + always @(posedge clk) begin + rst_MS <= Rst; + framesync_MS <= FrameSync; + nd_MS <= Nd; + din_MS <= Din; + end + //******输入数据的缓存模块 + Message_Store #( + .WIDTH(WIDTH) + ) MS ( + .clk (clk), + .rst_MS (rst_MS), + .framesync_MS(framesync_MS), + .nd_MS (nd_MS), + .din_MS (din_MS), + .oe_MS (oe_MS), + .deal_end_MS (deal_end_MS), + .syncout_MS (syncout_MS), + .rdy_MS (rdy_MS), + .dout01_MS (dout01_MS), + .dout02_MS (dout02_MS), + .dout03_MS (dout03_MS), + .dout04_MS (dout04_MS) + ); + + reg rst = 1'd0; + reg start = 1'd0; + reg framesync = 1'd0; + reg nd = 1'd0; + + reg [WIDTH-1:0] din01 = 8'd0; + reg [WIDTH-1:0] din02 = 8'd0; + reg [WIDTH-1:0] din03 = 8'd0; + reg [WIDTH-1:0] din04 = 8'd0; + + wire ask_din; + wire [ 8:0] gd_frames; + wire [ 8:0] bd_frames; + wire [ 8:0] tl_frames; + + wire ldpc_syncout; + wire rdy; + wire [ 0:0] ldpc_dout; + + always @(posedge clk) begin + rst <= Rst; + start <= deal_end_MS; + framesync <= syncout_MS; + nd <= rdy_MS; + + din01 <= dout01_MS; + din02 <= dout02_MS; + din03 <= dout03_MS; + din04 <= dout04_MS; + + oe_MS <= ask_din; + end + // TOP层译码器输出 + always @(posedge clk) begin + LDPC_SyncOut <= ldpc_syncout; + Rdy <= rdy; + LDPC_Dout <= ldpc_dout; + good_frames <= gd_frames; + bad_frames <= bd_frames; + total_frames <= tl_frames; + end + LDPC_DEC_PRO //译码器的吞吐量=(信息比特数/(一次迭代所需的时钟数*迭代次数))*FPGA工作主频 + #( + .MAX_ITER_NUM(MAX_ITER_NUM), + .WIDTH(WIDTH), + .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION) + ) LDPC_DEC ( + .clk (clk), + .rst (rst), + .start (start), + .framesync (framesync), + .nd (nd), + .din01 (din01), + .din02 (din02), + .din03 (din03), + .din04 (din04), + .ask_din (ask_din), + .gd_frames (gd_frames), + .bd_frames (bd_frames), + .tl_frames (tl_frames), + .ldpc_syncout(ldpc_syncout), + .rdy (rdy), + .ldpc_dout (ldpc_dout) + ); + + +endmodule + diff --git a/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v b/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v index 26bb2ec..4b491f2 100644 --- a/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v +++ b/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/CCSDS_LDPC_ENC_R12.v b/hdl/CCSDS_LDPC_ENC_R12.v index d47a344..28d5379 100644 --- a/hdl/CCSDS_LDPC_ENC_R12.v +++ b/hdl/CCSDS_LDPC_ENC_R12.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/CK_PRO.v b/hdl/CK_PRO.v new file mode 100644 index 0000000..ad459b7 --- /dev/null +++ b/hdl/CK_PRO.v @@ -0,0 +1,386 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: CK_PRO +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module CK_PRO + #( + parameter Index_p1_row_01_dec_01_01=0, Index_p1_row_01_dec_02_01=0, + parameter Index_p1_row_02_dec_02_01=0, Index_p1_row_02_dec_03_01=0, + parameter Index_p1_row_03_dec_03_01=0, Index_p1_row_03_dec_04_01=0, + parameter Index_p1_row_04_dec_04_01=0, Index_p1_row_04_dec_01_01=112, + + parameter Index_p2_row_01_dec_05_01=0, Index_p2_row_01_dec_05_02=25, Index_p2_row_01_dec_08_01=31,Index_p2_row_01_dec_07_01=39, + parameter Index_p2_row_02_dec_06_01=0, Index_p2_row_02_dec_06_02=75, Index_p2_row_02_dec_05_01=23,Index_p2_row_02_dec_08_01=16, + parameter Index_p2_row_03_dec_07_01=0, Index_p2_row_03_dec_07_02=120,Index_p2_row_03_dec_06_01=54,Index_p2_row_03_dec_05_01=0, + parameter Index_p2_row_04_dec_08_01=0, Index_p2_row_04_dec_08_02=93, Index_p2_row_04_dec_07_01=9, Index_p2_row_04_dec_06_01=83, + + parameter Index_p3_row_01_dec_09_01=0, Index_p3_row_01_dec_09_02=13, Index_p3_row_01_dec_11_01=97, Index_p3_row_01_dec_10_01=0, Index_p3_row_01_dec_12_01=34, + parameter Index_p3_row_02_dec_10_01=0, Index_p3_row_02_dec_10_02=69, Index_p3_row_02_dec_12_01=64, Index_p3_row_02_dec_11_01=6, Index_p3_row_02_dec_09_01=98, + parameter Index_p3_row_03_dec_11_01=0, Index_p3_row_03_dec_11_02=127,Index_p3_row_03_dec_09_01=78, Index_p3_row_03_dec_12_01=35, Index_p3_row_03_dec_10_01=26, + parameter Index_p3_row_04_dec_12_01=0, Index_p3_row_04_dec_12_02=29, Index_p3_row_04_dec_10_01=81, Index_p3_row_04_dec_09_01=99, Index_p3_row_04_dec_11_01=59 + ) + ( + input clk, + input rst_OUTCK, + input start_OUTCK, + input nd_OUTCK, + input [0:0] DR_din_01, + input [0:0] DR_din_02, + input [0:0] DR_din_03, + input [0:0] DR_din_04, + input [0:0] DR_din_05, + + output reg [8:0] gd_frames=9'd0,//译码好帧计数 + output reg [8:0] bd_frames=9'd0,//译码坏帧计数 + output reg [8:0] tl_frames=9'd0 //译码总帧数计数 + ); + + reg [127:0] dec_01 = 128'd0, dec_02 = 128'd0, dec_03 = 128'd0, dec_04 = 128'd0; + reg [127:0] dec_05 = 128'd0, dec_06 = 128'd0, dec_07 = 128'd0, dec_08 = 128'd0; + reg [127:0] dec_09 = 128'd0, dec_10 = 128'd0, dec_11 = 128'd0, dec_12 = 128'd0; + reg [127:0] dec_01_d1 = 128'd0, dec_02_d1 = 128'd0, dec_03_d1 = 128'd0, dec_04_d1 = 128'd0; + reg [127:0] dec_05_d1 = 128'd0, dec_06_d1 = 128'd0, dec_07_d1 = 128'd0, dec_08_d1 = 128'd0; + reg [127:0] dec_09_d1 = 128'd0, dec_10_d1 = 128'd0, dec_11_d1 = 128'd0, dec_12_d1 = 128'd0; + + reg [10:0] cnt_CK=11'd0; + reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_end_d5=1'd0,dec_proc=1'd0; + // 产生本模块的计数器 + always @ (posedge clk) begin + if (rst_OUTCK) begin + dec_proc <= 1'd0; + cnt_CK <= 11'd0; + end else begin + if (start_OUTCK) begin + dec_proc <= 1'd1; + cnt_CK <= 11'd0; + end else begin + if (dec_proc) begin + if (cnt_CK < 11'd560) begin + cnt_CK <= cnt_CK + 11'd1; + dec_proc <= dec_proc; + end else begin + cnt_CK <= cnt_CK; + dec_proc <= 1'd0; + end + end else begin + cnt_CK <= cnt_CK; + end + end + end + end + + parameter DELAY_DIN = 11'd0; + always @ (posedge clk) begin + if (rst_OUTCK || start_OUTCK) begin + dec_01 <= 128'd0; dec_01_d1 <= 128'd0; + dec_02 <= 128'd0; dec_02_d1 <= 128'd0; + dec_03 <= 128'd0; dec_03_d1 <= 128'd0; + dec_04 <= 128'd0; dec_04_d1 <= 128'd0; + + dec_05 <= 128'd0; dec_05_d1 <= 128'd0; + dec_06 <= 128'd0; dec_06_d1 <= 128'd0; + dec_07 <= 128'd0; dec_07_d1 <= 128'd0; + dec_08 <= 128'd0; dec_08_d1 <= 128'd0; + + dec_09 <= 128'd0; dec_09_d1 <= 128'd0; + dec_10 <= 128'd0; dec_10_d1 <= 128'd0; + dec_11 <= 128'd0; dec_11_d1 <= 128'd0; + dec_12 <= 128'd0; dec_12_d1 <= 128'd0; + + deal_end <= 1'd0; + end else begin + // 本来3行5列的H矩阵转置后变成5行3列 + // 第1列（4*128=512）个校验子求解过程 + if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin + dec_01[Index_p1_row_01_dec_01_01] <= DR_din_03 ^ DR_din_05; + dec_02[Index_p1_row_01_dec_02_01] <= DR_din_05; + end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin + dec_01[Index_p1_row_01_dec_01_01] <= 1'd0; + dec_02[Index_p1_row_02_dec_02_01] <= DR_din_03 ^ DR_din_05; + dec_03[Index_p1_row_02_dec_03_01] <= DR_din_05; + end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin + dec_03[Index_p1_row_03_dec_03_01] <= DR_din_03 ^ DR_din_05; + dec_04[Index_p1_row_03_dec_04_01] <= DR_din_05; + end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin + dec_04[Index_p1_row_04_dec_04_01] <= DR_din_03 ^ DR_din_05; + dec_01[Index_p1_row_04_dec_01_01] <= DR_din_05; + end else begin + dec_01 <= dec_01; + dec_02 <= dec_02; + dec_03 <= dec_03; + dec_04 <= dec_04; + end + + if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin + dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]} ^ dec_01; + dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]} ^ dec_02; + end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin + dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]} ^ dec_02; + dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]} ^ dec_03; + end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin + dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]} ^ dec_03; + dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]} ^ dec_04; + end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin + dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]} ^ dec_04; + dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]} ^ dec_01; + end else if (cnt_CK == 11'd514 + DELAY_DIN) begin + dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]}; + dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]}; + dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]}; + dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]}; + end else begin + dec_01_d1 <= dec_01_d1; + dec_02_d1 <= dec_02_d1; + dec_03_d1 <= dec_03_d1; + dec_04_d1 <= dec_04_d1; + deal_end <= 1'd0; + end + + + + // 第2列（4*128=512）个校验子求解过程 + if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin + dec_05[Index_p2_row_01_dec_05_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04; + dec_05[Index_p2_row_01_dec_05_02] <= DR_din_05; + dec_08[Index_p2_row_01_dec_08_01] <= DR_din_05; + dec_07[Index_p2_row_01_dec_07_01] <= DR_din_05; + end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin + dec_06[Index_p2_row_02_dec_06_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04; + dec_06[Index_p2_row_02_dec_06_02] <= DR_din_05; + dec_05[Index_p2_row_02_dec_05_01] <= DR_din_05; + dec_05[Index_p2_row_01_dec_05_01] <= 1'd0; + dec_05[Index_p2_row_01_dec_05_02] <= 1'd0; + dec_08[Index_p2_row_02_dec_08_01] <= DR_din_05; + dec_08[Index_p2_row_01_dec_08_01] <= 1'd0; + dec_07[Index_p2_row_01_dec_07_01] <= 1'd0; //xhx + end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin + dec_07[Index_p2_row_03_dec_07_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04; + dec_07[Index_p2_row_03_dec_07_02] <= DR_din_05; + dec_06[Index_p2_row_03_dec_06_01] <= DR_din_05; + dec_06[Index_p2_row_02_dec_06_01] <= 1'd0; + dec_06[Index_p2_row_02_dec_06_02] <= 1'd0; + dec_05[Index_p2_row_03_dec_05_01] <= DR_din_05; + dec_05[Index_p2_row_02_dec_05_01] <= 1'd0; + dec_08[Index_p2_row_02_dec_08_01] <= 1'd0; //xhx + end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin + dec_08[Index_p2_row_04_dec_08_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04; + dec_08[Index_p2_row_04_dec_08_02] <= DR_din_05; + dec_07[Index_p2_row_04_dec_07_01] <= DR_din_05; + dec_07[Index_p2_row_03_dec_07_01] <= 1'd0; + dec_07[Index_p2_row_03_dec_07_02] <= 1'd0; + dec_06[Index_p2_row_04_dec_06_01] <= DR_din_05; + dec_06[Index_p2_row_03_dec_06_01] <= 1'd0; + dec_05[Index_p2_row_03_dec_05_01] <= 1'd0; //xhx + end else begin + dec_05 <= dec_05; + dec_06 <= dec_06; + dec_07 <= dec_07; + dec_08 <= dec_08; + end + + if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin + dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05; + dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07; + dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08; + end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin + dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05; + dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06; + dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08; + end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin + dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05; + dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06; + dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07; + end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin + dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06; + dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07; + dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08; + end else if (cnt_CK == 11'd514 + DELAY_DIN) begin + dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]}; + dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]}; + dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]}; + dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]}; + end else begin + dec_05_d1 <= dec_05_d1; + dec_06_d1 <= dec_06_d1; + dec_07_d1 <= dec_07_d1; + dec_08_d1 <= dec_08_d1; + end + + + // 第3列（4*128=512）个校验子求解过程 + if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin + dec_09[Index_p3_row_01_dec_09_01] <= DR_din_01 ^ DR_din_05; + dec_09[Index_p3_row_01_dec_09_02] <= DR_din_04; + dec_11[Index_p3_row_01_dec_11_01] <= DR_din_02; + dec_10[Index_p3_row_01_dec_10_01] <= DR_din_02; + dec_12[Index_p3_row_01_dec_12_01] <= DR_din_04; + end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin + dec_10[Index_p3_row_02_dec_10_01] <= DR_din_01 ^ DR_din_05; + dec_10[Index_p3_row_02_dec_10_02] <= DR_din_04; + dec_12[Index_p3_row_02_dec_12_01] <= DR_din_02; + dec_12[Index_p3_row_01_dec_12_01] <= 1'd0; + dec_11[Index_p3_row_02_dec_11_01] <= DR_din_02; + dec_11[Index_p3_row_01_dec_11_01] <= 1'd0; + dec_09[Index_p3_row_02_dec_09_01] <= DR_din_04; + dec_09[Index_p3_row_01_dec_09_01] <= 1'd0; + dec_09[Index_p3_row_01_dec_09_02] <= 1'd0; + end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin + dec_11[Index_p3_row_03_dec_11_01] <= DR_din_01 ^ DR_din_05; + dec_11[Index_p3_row_03_dec_11_02] <= DR_din_04; + dec_11[Index_p3_row_02_dec_11_01] <= 1'd0; + dec_09[Index_p3_row_03_dec_09_01] <= DR_din_02; + dec_09[Index_p3_row_02_dec_09_01] <= 1'd0; + dec_12[Index_p3_row_03_dec_12_01] <= DR_din_02; + dec_12[Index_p3_row_02_dec_12_01] <= 1'd0; + dec_10[Index_p3_row_03_dec_10_01] <= DR_din_04; + dec_10[Index_p3_row_02_dec_10_01] <= 1'd0; + dec_10[Index_p3_row_02_dec_10_02] <= 1'd0; + end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin + dec_12[Index_p3_row_04_dec_12_01] <= DR_din_01 ^ DR_din_05; + dec_12[Index_p3_row_04_dec_12_02] <= DR_din_04; + dec_12[Index_p3_row_03_dec_12_01] <= 1'd0; + dec_10[Index_p3_row_04_dec_10_01] <= DR_din_02; + dec_10[Index_p3_row_03_dec_10_01] <= 1'd0; + dec_09[Index_p3_row_04_dec_09_01] <= DR_din_02; + dec_09[Index_p3_row_03_dec_09_01] <= 1'd0; + dec_11[Index_p3_row_04_dec_11_01] <= DR_din_04; + dec_11[Index_p3_row_03_dec_11_01] <= 1'd0; + dec_11[Index_p3_row_03_dec_11_02] <= 1'd0; + end else begin + dec_09 <= dec_09; + dec_10 <= dec_10; + dec_11 <= dec_11; + dec_12 <= dec_12; + end + + if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin + dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09; + dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10; + dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11; + dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12; + end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin + dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09; + dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10; + dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11; + dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12; + end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin + dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09; + dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10; + dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11; + dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12; + end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin + dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09; + dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10; + dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11; + dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12; + end else if (cnt_CK == 11'd514 + DELAY_DIN) begin + dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]}; + dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]}; + dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]}; + dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]}; + end else begin + dec_09_d1 <= dec_09_d1; + dec_10_d1 <= dec_10_d1; + dec_11_d1 <= dec_11_d1; + dec_12_d1 <= dec_12_d1; + end + + // 产生标志位 + if (cnt_CK == 11'd514 + DELAY_DIN) + deal_end <= 1'd1; + else + deal_end <= 1'd0; + end + end + + //2019.02.28添加：打一拍，尝试避免时序问题 + reg deal_end_d6 = 1'd0; + reg flag_judge1 = 1'd0; + reg flag_judge2 = 1'd0; + reg flag_judge3 = 1'd0; + always@(posedge clk) begin + if(rst_OUTCK) begin + flag_judge1 <= 1'd0; + flag_judge2 <= 1'd0; + flag_judge3 <= 1'd0; + end + else begin + if(deal_end_d5) begin + if(dec_01_d1 == 128'd0 && dec_02_d1 == 128'd0 && dec_03_d1 == 128'd0 && dec_04_d1 == 128'd0 ) flag_judge1 <= 1'd0; + else flag_judge1 <= 1'd1; + if(dec_05_d1 == 128'd0 && dec_06_d1 == 128'd0 && dec_07_d1 == 128'd0 && dec_08_d1 == 128'd0 ) flag_judge2 <= 1'd0; + else flag_judge2 <= 1'd1; + if(dec_09_d1 == 128'd0 && dec_10_d1 == 128'd0 && dec_11_d1 == 128'd0 && dec_12_d1 == 128'd0 ) flag_judge3 <= 1'd0; + else flag_judge3 <= 1'd1; + end + else begin + flag_judge1 <= flag_judge1; + flag_judge2 <= flag_judge2; + flag_judge3 <= flag_judge3; + end + end + end + + + always@(posedge clk) begin + if(rst_OUTCK) begin + gd_frames <= 9'd0; + bd_frames <= 9'd0; + tl_frames <= 9'd0; + deal_end_d1 <= 1'd0; + deal_end_d2 <= 1'd0; + deal_end_d3 <= 1'd0; + deal_end_d4 <= 1'd0; + deal_end_d5 <= 1'd0; + deal_end_d6 <= 1'd0; //2019.02.28添加 + end else begin + deal_end_d1 <= deal_end; + deal_end_d2 <= deal_end_d1; + deal_end_d3 <= deal_end_d2; + deal_end_d4 <= deal_end_d3; + deal_end_d5 <= deal_end_d4; + deal_end_d6 <= deal_end_d5; //2019.02.28添加 + if(deal_end_d6) begin + if(flag_judge1 == 1'd0 && flag_judge2 == 1'd0 && flag_judge3 == 1'd0 ) begin + // if(dec_01_d1 == 128'd0 && dec_02_d1 == 128'd0 && dec_03_d1 == 128'd0 && dec_04_d1 == 128'd0 && + // dec_05_d1 == 128'd0 && dec_06_d1 == 128'd0 && dec_07_d1 == 128'd0 && dec_08_d1 == 128'd0 && + // dec_09_d1 == 128'd0 && dec_10_d1 == 128'd0 && dec_11_d1 == 128'd0 && dec_12_d1 == 128'd0 ) begin + gd_frames <= gd_frames + 9'd1; + bd_frames <= bd_frames; + tl_frames <= tl_frames + 9'd1; + end else begin + gd_frames <= gd_frames; + bd_frames <= bd_frames + 9'd1; + tl_frames <= tl_frames + 9'd1; + end + end else begin + gd_frames <= gd_frames; + bd_frames <= bd_frames; + tl_frames <= tl_frames; + end + end + end + + +endmodule + + + diff --git a/hdl/CNU_3din.v b/hdl/CNU_3din.v new file mode 100644 index 0000000..580667e --- /dev/null +++ b/hdl/CNU_3din.v @@ -0,0 +1,107 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: CNU_3din +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module CNU_3din + #(parameter WIDTH = 4'd8)( + input clk, + input [WIDTH-1:0] din01_VN_RU, //变量节点信息输入 + input [WIDTH-1:0] din02_VN_RU, //变量节点信息输入 + input [WIDTH-1:0] din03_VN_RU, //变量节点信息输入 + + output reg [WIDTH-1:0] dout01_RU=8'd0, //更新输出 + output reg [WIDTH-1:0] dout02_RU=8'd0, //更新输出 + output reg [WIDTH-1:0] dout03_RU=8'd0 //更新输出 + );//输出相对输入延时9个clk + + reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0; + reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0; + reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0; + + always @ (posedge clk) begin//求输入数据的绝对值过程 + if(din01_VN_RU[WIDTH-1]) abs01 <= ~din01_VN_RU + 8'd1;else abs01 <= din01_VN_RU; + if(din02_VN_RU[WIDTH-1]) abs02 <= ~din02_VN_RU + 8'd1;else abs02 <= din02_VN_RU; + if(din03_VN_RU[WIDTH-1]) abs03 <= ~din03_VN_RU + 8'd1;else abs03 <= din03_VN_RU; + end + + always @ (posedge clk) begin + abs01_reg0 <= abs01; abs01_reg1 <= abs01_reg0; + abs02_reg0 <= abs02; abs02_reg1 <= abs02_reg0; + abs03_reg0 <= abs03; abs03_reg1 <= abs03_reg0; + end + + reg [WIDTH-1:0] min_level_1_01=8'd0,min_level_1_02=8'd0; + reg [WIDTH-1:0] min_level_2_01=8'd0,min_level_2_02=8'd0; + always @ (posedge clk) begin//第1级分类，两两一组将最小及次小值分开 + min_level_1_01 <= (abs01 < abs02) ? abs01:abs02; + min_level_1_02 <= (abs01 < abs02) ? abs02:abs01; + end + + always @ (posedge clk) begin + min_level_2_01 <= (abs03_reg0= 11'd1 && cnt_CN <= 11'd512) begin + VN1_addr_rd_01_00 <= VN1_addr_rd_01_00 + 9'd1; + VN1_addr_rd_02_00 <= VN1_addr_rd_02_00 + 9'd1; + VN2_addr_rd_01_00 <= VN2_addr_rd_01_00 + 9'd1; + VN2_addr_rd_02_00 <= VN2_addr_rd_02_00 + 9'd1; + VN2_addr_rd_03_00 <= VN2_addr_rd_03_00 + 9'd1; + VN3_addr_rd_01_00 <= VN3_addr_rd_01_00 + 9'd1; + VN3_addr_rd_04_00 <= VN3_addr_rd_04_00 + 9'd1; + VN1_addr_rd_02_01 <= VN1_addr_rd_02_01 + 10'd1; + VN2_addr_rd_04_02 <= VN2_addr_rd_04_02 + 10'd1; + VN2_addr_rd_04_03 <= VN2_addr_rd_04_03 + 10'd1; + VN2_addr_rd_04_04 <= VN2_addr_rd_04_04 + 9'd1; + VN3_addr_rd_02_05 <= VN3_addr_rd_02_05 + 10'd1; + VN3_addr_rd_02_06 <= VN3_addr_rd_02_06 + 10'd1; + VN3_addr_rd_03_07 <= VN3_addr_rd_03_07 + 10'd1; + VN3_addr_rd_03_08 <= VN3_addr_rd_03_08 + 10'd1; + end else begin + VN1_addr_rd_01_00 <= 9'd511; + VN1_addr_rd_02_00 <= 10'd1023; + VN2_addr_rd_01_00 <= 9'd511; + VN2_addr_rd_02_00 <= 9'd511; + VN2_addr_rd_03_00 <= 9'd511; + VN3_addr_rd_01_00 <= 9'd511; + VN3_addr_rd_04_00 <= 9'd511; + VN1_addr_rd_02_01 <= 10'd511; + VN2_addr_rd_04_02 <= 10'd1023; + VN2_addr_rd_04_03 <= 10'd511; + VN2_addr_rd_04_04 <= 9'd511; + VN3_addr_rd_02_05 <= 10'd1023; + VN3_addr_rd_02_06 <= 10'd511; + VN3_addr_rd_03_07 <= 10'd1023; + VN3_addr_rd_03_08 <= 10'd511; + end + end + end + + wire [WIDTH-1:0] din01_VN_RU01; + wire [WIDTH-1:0] din02_VN_RU01; + wire [WIDTH-1:0] din03_VN_RU01; + wire [WIDTH-1:0] dout01_RU01 ; + wire [WIDTH-1:0] dout02_RU01 ; + wire [WIDTH-1:0] dout03_RU01 ; + wire [WIDTH-1:0] din01_VN_RU02; + wire [WIDTH-1:0] din02_VN_RU02; + wire [WIDTH-1:0] din03_VN_RU02; + wire [WIDTH-1:0] din04_VN_RU02; + wire [WIDTH-1:0] din05_VN_RU02; + wire [WIDTH-1:0] din06_VN_RU02; + wire [WIDTH-1:0] dout01_RU02 ; + wire [WIDTH-1:0] dout02_RU02 ; + wire [WIDTH-1:0] dout03_RU02 ; + wire [WIDTH-1:0] dout04_RU02 ; + wire [WIDTH-1:0] dout05_RU02 ; + wire [WIDTH-1:0] dout06_RU02 ; + wire [WIDTH-1:0] din01_VN_RU03; + wire [WIDTH-1:0] din02_VN_RU03; + wire [WIDTH-1:0] din03_VN_RU03; + wire [WIDTH-1:0] din04_VN_RU03; + wire [WIDTH-1:0] din05_VN_RU03; + wire [WIDTH-1:0] din06_VN_RU03; + wire [WIDTH-1:0] dout01_RU03 ; + wire [WIDTH-1:0] dout02_RU03 ; + wire [WIDTH-1:0] dout03_RU03 ; + wire [WIDTH-1:0] dout04_RU03 ; + wire [WIDTH-1:0] dout05_RU03 ; + wire [WIDTH-1:0] dout06_RU03 ; + + + + CNU_3din #(.WIDTH(WIDTH)) RU_01 ( + .clk(clk), + .din01_VN_RU(din01_VN_RU01), + .din02_VN_RU(din02_VN_RU01), + .din03_VN_RU(din03_VN_RU01), + .dout01_RU(dout01_RU01), + .dout02_RU(dout02_RU01), + .dout03_RU(dout03_RU01) + ); + + CNU_6din #(.WIDTH(WIDTH)) RU_02 ( + .clk(clk), + .din01_VN_RU(din01_VN_RU02), + .din02_VN_RU(din02_VN_RU02), + .din03_VN_RU(din03_VN_RU02), + .din04_VN_RU(din04_VN_RU02), + .din05_VN_RU(din05_VN_RU02), + .din06_VN_RU(din06_VN_RU02), + .dout01_RU(dout01_RU02), + .dout02_RU(dout02_RU02), + .dout03_RU(dout03_RU02), + .dout04_RU(dout04_RU02), + .dout05_RU(dout05_RU02), + .dout06_RU(dout06_RU02) + ); + + CNU_6din #(.WIDTH(WIDTH)) RU_03 ( + .clk(clk), + .din01_VN_RU(din01_VN_RU03), + .din02_VN_RU(din02_VN_RU03), + .din03_VN_RU(din03_VN_RU03), + .din04_VN_RU(din04_VN_RU03), + .din05_VN_RU(din05_VN_RU03), + .din06_VN_RU(din06_VN_RU03), + .dout01_RU(dout01_RU03), + .dout02_RU(dout02_RU03), + .dout03_RU(dout03_RU03), + .dout04_RU(dout04_RU03), + .dout05_RU(dout05_RU03), + .dout06_RU(dout06_RU03) + ); + // 设置读操作的时延 + parameter DELAY_RD = 11'd6; + // RU模块的输入 + assign din01_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_01_00 : 8'd0; + assign din02_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_02_00 : 8'd0; + assign din03_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_02_01 : 8'd0; + assign din01_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_01_00 : 8'd0; + assign din02_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_02_00 : 8'd0; + assign din03_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_03_00 : 8'd0; + assign din04_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_02 : 8'd0; + assign din05_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_03 : 8'd0; + assign din06_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_04 : 8'd0; + assign din01_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_01_00 : 8'd0; + assign din02_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_02_05 : 8'd0; + assign din03_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_02_06 : 8'd0; + assign din04_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_03_07 : 8'd0; + assign din05_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_03_08 : 8'd0; + assign din06_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_04_00 : 8'd0; + + // 设置写操作的时延 + parameter DELAY_WR = 11'd15; + + // 控制CN的写使能 + always @ (posedge clk) begin + if(rst_CN) begin + CN_wea <= 1'd0; + end else begin + if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR) + CN_wea <= 1'd1; + else + CN_wea <= 1'd0; + end + end + + // 控制CN存储的写地址 + always @ (posedge clk) begin + if (rst_CN) begin + CN1_addr_wr_01_00 <= 9'd511; + CN1_addr_wr_02_00 <= 10'd1023; + CN2_addr_wr_01_00 <= 9'd511; + CN2_addr_wr_02_00 <= 9'd511; + CN2_addr_wr_03_00 <= 9'd511; + CN3_addr_wr_01_00 <= 9'd511; + CN3_addr_wr_04_00 <= 9'd511; + + CN1_addr_wr_02_01 <= 10'd511; + CN2_addr_wr_04_02 <= 10'd1023; + CN2_addr_wr_04_03 <= 10'd511; + CN2_addr_wr_04_04 <= 9'd511; + CN3_addr_wr_02_05 <= 10'd1023; + CN3_addr_wr_02_06 <= 10'd511; + CN3_addr_wr_03_07 <= 10'd1023; + CN3_addr_wr_03_08 <= 10'd511; + + end else begin + if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR) begin + CN1_addr_wr_01_00 <= CN1_addr_wr_01_00 + 9'd1; + CN1_addr_wr_02_00 <= CN1_addr_wr_02_00 + 9'd1; + CN2_addr_wr_01_00 <= CN2_addr_wr_01_00 + 9'd1; + CN2_addr_wr_02_00 <= CN2_addr_wr_02_00 + 9'd1; + CN2_addr_wr_03_00 <= CN2_addr_wr_03_00 + 9'd1; + CN3_addr_wr_01_00 <= CN3_addr_wr_01_00 + 9'd1; + CN3_addr_wr_04_00 <= CN3_addr_wr_04_00 + 9'd1; + CN1_addr_wr_02_01 <= CN1_addr_wr_02_01 + 10'd1; + CN2_addr_wr_04_02 <= CN2_addr_wr_04_02 + 10'd1; + CN2_addr_wr_04_03 <= CN2_addr_wr_04_03 + 10'd1; + CN2_addr_wr_04_04 <= CN2_addr_wr_04_04 + 9'd1; + CN3_addr_wr_02_05 <= CN3_addr_wr_02_05 + 10'd1; + CN3_addr_wr_02_06 <= CN3_addr_wr_02_06 + 10'd1; + CN3_addr_wr_03_07 <= CN3_addr_wr_03_07 + 10'd1; + CN3_addr_wr_03_08 <= CN3_addr_wr_03_08 + 10'd1; + end else begin + CN1_addr_wr_01_00 <= 9'd511; + CN1_addr_wr_02_00 <= 10'd1023; + CN2_addr_wr_01_00 <= 9'd511; + CN2_addr_wr_02_00 <= 9'd511; + CN2_addr_wr_03_00 <= 9'd511; + CN3_addr_wr_01_00 <= 9'd511; + CN3_addr_wr_04_00 <= 9'd511; + CN1_addr_wr_02_01 <= 10'd511; + CN2_addr_wr_04_02 <= 10'd1023; + CN2_addr_wr_04_03 <= 10'd511; + CN2_addr_wr_04_04 <= 9'd511; + CN3_addr_wr_02_05 <= 10'd1023; + CN3_addr_wr_02_06 <= 10'd511; + CN3_addr_wr_03_07 <= 10'd1023; + CN3_addr_wr_03_08 <= 10'd511; + end + end + end + + // 控制CN的写数据 + always @ (posedge clk) begin + if (rst_CN) begin + CN1_din_01_00 <= 8'd0; + CN1_din_02_00 <= 8'd0; + CN2_din_01_00 <= 8'd0; + CN2_din_02_00 <= 8'd0; + CN2_din_03_00 <= 8'd0; + CN3_din_01_00 <= 8'd0; + CN3_din_04_00 <= 8'd0; + CN1_din_02_01 <= 8'd0; + CN2_din_04_02 <= 8'd0; + CN2_din_04_03 <= 8'd0; + CN2_din_04_04 <= 8'd0; + CN3_din_02_05 <= 8'd0; + CN3_din_02_06 <= 8'd0; + CN3_din_03_07 <= 8'd0; + CN3_din_03_08 <= 8'd0; + end else begin + if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR) begin + CN1_din_01_00 <= dout01_RU01; + CN1_din_02_00 <= dout02_RU01; + CN2_din_01_00 <= dout01_RU02; + CN2_din_02_00 <= dout02_RU02; + CN2_din_03_00 <= dout03_RU02; + CN3_din_01_00 <= dout01_RU03; + CN3_din_04_00 <= dout06_RU03; + CN1_din_02_01 <= dout03_RU01; + CN2_din_04_02 <= dout04_RU02; + CN2_din_04_03 <= dout05_RU02; + CN2_din_04_04 <= dout06_RU02; + CN3_din_02_05 <= dout02_RU03; + CN3_din_02_06 <= dout03_RU03; + CN3_din_03_07 <= dout04_RU03; + CN3_din_03_08 <= dout05_RU03; + end else begin + CN1_din_01_00 <= 8'd0; + CN1_din_02_00 <= 8'd0; + CN2_din_01_00 <= 8'd0; + CN2_din_02_00 <= 8'd0; + CN2_din_03_00 <= 8'd0; + CN3_din_01_00 <= 8'd0; + CN3_din_04_00 <= 8'd0; + CN1_din_02_01 <= 8'd0; + CN2_din_04_02 <= 8'd0; + CN2_din_04_03 <= 8'd0; + CN2_din_04_04 <= 8'd0; + CN3_din_02_05 <= 8'd0; + CN3_din_02_06 <= 8'd0; + CN3_din_03_07 <= 8'd0; + CN3_din_03_08 <= 8'd0; + end + end + end + + //状态指示 + assign end_CN = (cnt_CN == 11'd512 + DELAY_WR + 11'd2) ? 1'd1 : 1'd0; +endmodule + diff --git a/hdl/Chn_Estimate.v b/hdl/Chn_Estimate.v index 1565453..98d1881 100644 --- a/hdl/Chn_Estimate.v +++ b/hdl/Chn_Estimate.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/DAGC_v2.v b/hdl/DAGC_v2.v index 7f725b7..d950b3e 100644 --- a/hdl/DAGC_v2.v +++ b/hdl/DAGC_v2.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/DDS_compensate.v b/hdl/DDS_compensate.v index af305eb..d9a5916 100644 --- a/hdl/DDS_compensate.v +++ b/hdl/DDS_compensate.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/FrameMerge.v b/hdl/FrameMerge.v index 180ccde..492f373 100644 --- a/hdl/FrameMerge.v +++ b/hdl/FrameMerge.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/IQmerge.v b/hdl/IQmerge.v index c566492..19a52a7 100644 --- a/hdl/IQmerge.v +++ b/hdl/IQmerge.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/Interp_half.v b/hdl/Interp_half.v index 59954d4..5e0f8e8 100644 --- a/hdl/Interp_half.v +++ b/hdl/Interp_half.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/Interp_quarter.v b/hdl/Interp_quarter.v index e8af439..18e3572 100644 --- a/hdl/Interp_quarter.v +++ b/hdl/Interp_quarter.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/Interpolation.v b/hdl/Interpolation.v index 138ecd2..9744398 100644 --- a/hdl/Interpolation.v +++ b/hdl/Interpolation.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/LDPC_DEC_PRO.v b/hdl/LDPC_DEC_PRO.v new file mode 100644 index 0000000..1553d37 --- /dev/null +++ b/hdl/LDPC_DEC_PRO.v @@ -0,0 +1,1074 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: LDPC_DEC_PRO +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module LDPC_DEC_PRO #( + parameter MAX_ITER_NUM = 6'd14, + parameter WIDTH = 4'd8, + parameter OUT_ONLY_INFORMATION = 1'd0 +) ( + input clk, //工作时钟 + input rst, //同步复位信号， 高有效 + input start, //开始译码标志， 高脉冲 + input framesync, //帧同步标志，高脉冲 + input nd, //译码输入数据有效标志，高有效 + + input [WIDTH-1:0] din01, //译码输入数据， 软信息， 对应时刻 N + input [WIDTH-1:0] din02, //译码输入数据， 软信息， 对应时刻 N+1*512 + input [WIDTH-1:0] din03, //译码输入数据， 软信息， 对应时刻 N+2*512 + input [WIDTH-1:0] din04, //译码输入数据， 软信息， 对应时刻 N+3*512 + + output reg ask_din = 1'd0, //向上层索要译码数据标志，高脉冲 + + output reg [8:0] gd_frames = 9'd0, //译码好帧计数 + output reg [8:0] bd_frames = 9'd0, //译码坏帧计数 + output reg [8:0] tl_frames = 9'd0, //译码总帧数计数 + + output reg ldpc_syncout = 1'd0, //LDPC 模块帧同步输出信号，高脉冲，指示帧起点 + output reg rdy = 1'd0, //译码输出信号有效标志，高有效 + output reg ldpc_dout = 1'd0 //译码输出信号 +); + + //*****列更新模块信号定义 + reg rst_VN = 1'd0; + reg start_VN = 1'd0; + reg start_frame_VN = 1'd0; //7.23 xhx 在新的一帧数据来临前清零迭代次数的计数 + + reg [WIDTH-1:0] CHNL_dout_01_VN = 8'd0; //信道信息输入 + reg [WIDTH-1:0] CHNL_dout_02_VN = 8'd0; + reg [WIDTH-1:0] CHNL_dout_03_VN = 8'd0; + reg [WIDTH-1:0] CHNL_dout_04_VN = 8'd0; + + reg [WIDTH-1:0] CN1_dout_01_00_VN = 8'd0; + reg [WIDTH-1:0] CN1_dout_02_00_VN = 8'd0; //后面的00代表H阵原模图的IM + reg [WIDTH-1:0] CN1_dout_02_01_VN = 8'd0; //后面的01代表H阵原模图的II1 + reg [WIDTH-1:0] CN2_dout_01_00_VN = 8'd0; + reg [WIDTH-1:0] CN2_dout_02_00_VN = 8'd0; + reg [WIDTH-1:0] CN2_dout_03_00_VN = 8'd0; + reg [WIDTH-1:0] CN2_dout_04_02_VN = 8'd0; //后面的02代表H阵原模图的II2 + reg [WIDTH-1:0] CN2_dout_04_03_VN = 8'd0; //后面的03代表H阵原模图的II3 + reg [WIDTH-1:0] CN2_dout_04_04_VN = 8'd0; //后面的04代表H阵原模图的II4 + reg [WIDTH-1:0] CN3_dout_01_00_VN = 8'd0; + reg [WIDTH-1:0] CN3_dout_02_05_VN = 8'd0; //后面的05代表H阵原模图的II5 + reg [WIDTH-1:0] CN3_dout_02_06_VN = 8'd0; //后面的06代表H阵原模图的II6 + reg [WIDTH-1:0] CN3_dout_03_07_VN = 8'd0; //后面的07代表H阵原模图的II7 + reg [WIDTH-1:0] CN3_dout_03_08_VN = 8'd0; //后面的08代表H阵原模图的II8 + reg [WIDTH-1:0] CN3_dout_04_00_VN = 8'd0; + + wire data_start_VN; + wire data_start_ck_VN; + wire end_VN; + wire ask_din_VN; + wire VN_wea_VN; + wire [ 9:0] CN1_addr_rd_02_00_VN; + wire [ 9:0] CN1_addr_rd_02_01_VN; + wire [ 9:0] CN2_addr_rd_04_02_VN; + wire [ 9:0] CN2_addr_rd_04_03_VN; + wire [ 9:0] CN3_addr_rd_02_05_VN; + wire [ 9:0] CN3_addr_rd_02_06_VN; + wire [ 9:0] CN3_addr_rd_03_07_VN; + wire [ 9:0] CN3_addr_rd_03_08_VN; + wire [ 8:0] CN1_addr_rd_01_00_VN; + wire [ 8:0] CN2_addr_rd_01_00_VN; + wire [ 8:0] CN2_addr_rd_02_00_VN; + wire [ 8:0] CN2_addr_rd_03_00_VN; + wire [ 8:0] CN2_addr_rd_04_04_VN; + wire [ 8:0] CN3_addr_rd_01_00_VN; + wire [ 8:0] CN3_addr_rd_04_00_VN; + + wire [ 8:0] VN1_addr_wr_01_00_VN; + wire [ 9:0] VN1_addr_wr_02_00_VN; + wire [ 9:0] VN1_addr_wr_02_01_VN; + wire [ 8:0] VN2_addr_wr_01_00_VN; + wire [ 8:0] VN2_addr_wr_02_00_VN; + wire [ 8:0] VN2_addr_wr_03_00_VN; + wire [ 9:0] VN2_addr_wr_04_02_VN; + wire [ 9:0] VN2_addr_wr_04_03_VN; + wire [ 8:0] VN2_addr_wr_04_04_VN; + wire [ 8:0] VN3_addr_wr_01_00_VN; + wire [ 9:0] VN3_addr_wr_02_05_VN; + wire [ 9:0] VN3_addr_wr_02_06_VN; + wire [ 9:0] VN3_addr_wr_03_07_VN; + wire [ 9:0] VN3_addr_wr_03_08_VN; + wire [ 8:0] VN3_addr_wr_04_00_VN; + + wire [WIDTH-1:0] VN1_din_01_00_VN; + wire [WIDTH-1:0] VN1_din_02_00_VN; + wire [WIDTH-1:0] VN1_din_02_01_VN; + wire [WIDTH-1:0] VN2_din_01_00_VN; + wire [WIDTH-1:0] VN2_din_02_00_VN; + wire [WIDTH-1:0] VN2_din_03_00_VN; + wire [WIDTH-1:0] VN2_din_04_02_VN; + wire [WIDTH-1:0] VN2_din_04_03_VN; + wire [WIDTH-1:0] VN2_din_04_04_VN; + wire [WIDTH-1:0] VN3_din_01_00_VN; + wire [WIDTH-1:0] VN3_din_02_05_VN; + wire [WIDTH-1:0] VN3_din_02_06_VN; + wire [WIDTH-1:0] VN3_din_03_07_VN; + wire [WIDTH-1:0] VN3_din_03_08_VN; + wire [WIDTH-1:0] VN3_din_04_00_VN; + + wire DR_wea_VN; + wire [ 8:0] DR_addr_wr_VN; + wire DR_din_01_VN; + wire DR_din_02_VN; + wire DR_din_03_VN; + wire DR_din_04_VN; + wire DR_din_05_VN; + + //*****行更新模块信号定义 + reg start_CN = 1'd0; //模块启动信号，高脉冲 + reg rst_CN = 1'd0; + reg [WIDTH-1:0] VN1_dout_01_00_CN = 8'd0; + reg [WIDTH-1:0] VN1_dout_02_00_CN = 8'd0; //后面的00代表H阵原模图的IM + reg [WIDTH-1:0] VN1_dout_02_01_CN = 8'd0; //后面的01代表H阵原模图的II1 + reg [WIDTH-1:0] VN2_dout_01_00_CN = 8'd0; + reg [WIDTH-1:0] VN2_dout_02_00_CN = 8'd0; + reg [WIDTH-1:0] VN2_dout_03_00_CN = 8'd0; + reg [WIDTH-1:0] VN2_dout_04_02_CN = 8'd0; //后面的02代表H阵原模图的II2 + reg [WIDTH-1:0] VN2_dout_04_03_CN = 8'd0; //后面的03代表H阵原模图的II3 + reg [WIDTH-1:0] VN2_dout_04_04_CN = 8'd0; //后面的04代表H阵原模图的II4 + reg [WIDTH-1:0] VN3_dout_01_00_CN = 8'd0; + reg [WIDTH-1:0] VN3_dout_02_05_CN = 8'd0; //后面的05代表H阵原模图的II5 + reg [WIDTH-1:0] VN3_dout_02_06_CN = 8'd0; //后面的06代表H阵原模图的II6 + reg [WIDTH-1:0] VN3_dout_03_07_CN = 8'd0; //后面的07代表H阵原模图的II7 + reg [WIDTH-1:0] VN3_dout_03_08_CN = 8'd0; //后面的08代表H阵原模图的II8 + reg [WIDTH-1:0] VN3_dout_04_00_CN = 8'd0; + + wire [ 9:0] VN1_addr_rd_02_00_CN; + wire [ 9:0] VN1_addr_rd_02_01_CN; + wire [ 9:0] VN2_addr_rd_04_02_CN; + wire [ 9:0] VN2_addr_rd_04_03_CN; + wire [ 9:0] VN3_addr_rd_02_05_CN; + wire [ 9:0] VN3_addr_rd_02_06_CN; + wire [ 9:0] VN3_addr_rd_03_07_CN; + wire [ 9:0] VN3_addr_rd_03_08_CN; + wire [ 8:0] VN1_addr_rd_01_00_CN; + wire [ 8:0] VN2_addr_rd_01_00_CN; + wire [ 8:0] VN2_addr_rd_02_00_CN; + wire [ 8:0] VN2_addr_rd_03_00_CN; + wire [ 8:0] VN2_addr_rd_04_04_CN; + wire [ 8:0] VN3_addr_rd_01_00_CN; + wire [ 8:0] VN3_addr_rd_04_00_CN; + + wire CN_wea_CN; + + wire [ 8:0] CN1_addr_wr_01_00_CN; + wire [ 9:0] CN1_addr_wr_02_00_CN; + wire [ 9:0] CN1_addr_wr_02_01_CN; + wire [ 8:0] CN2_addr_wr_01_00_CN; + wire [ 8:0] CN2_addr_wr_02_00_CN; + wire [ 8:0] CN2_addr_wr_03_00_CN; + wire [ 9:0] CN2_addr_wr_04_02_CN; + wire [ 9:0] CN2_addr_wr_04_03_CN; + wire [ 8:0] CN2_addr_wr_04_04_CN; + wire [ 8:0] CN3_addr_wr_01_00_CN; + wire [ 9:0] CN3_addr_wr_02_05_CN; + wire [ 9:0] CN3_addr_wr_02_06_CN; + wire [ 9:0] CN3_addr_wr_03_07_CN; + wire [ 9:0] CN3_addr_wr_03_08_CN; + wire [ 8:0] CN3_addr_wr_04_00_CN; + + wire [WIDTH-1:0] CN1_din_01_00_CN; + wire [WIDTH-1:0] CN1_din_02_00_CN; + wire [WIDTH-1:0] CN1_din_02_01_CN; + wire [WIDTH-1:0] CN2_din_01_00_CN; + wire [WIDTH-1:0] CN2_din_02_00_CN; + wire [WIDTH-1:0] CN2_din_03_00_CN; + wire [WIDTH-1:0] CN2_din_04_02_CN; + wire [WIDTH-1:0] CN2_din_04_03_CN; + wire [WIDTH-1:0] CN2_din_04_04_CN; + wire [WIDTH-1:0] CN3_din_01_00_CN; + wire [WIDTH-1:0] CN3_din_02_05_CN; + wire [WIDTH-1:0] CN3_din_02_06_CN; + wire [WIDTH-1:0] CN3_din_03_07_CN; + wire [WIDTH-1:0] CN3_din_03_08_CN; + wire [WIDTH-1:0] CN3_din_04_00_CN; + + + wire end_CN; //模块结束标志，高脉冲 + + //*****校验节点信息存储RAM信号定义 + reg CN_wea = 1'd0; + + //RAM写地址，H阵第１行 + reg [ 8:0] CN1_addr_wr_01_00 = 9'd511; + reg [ 9:0] CN1_addr_wr_02_00 = 10'd1023; + reg [ 9:0] CN1_addr_wr_02_01 = 10'd511; + //RAM写地址，H阵第２行 + reg [ 8:0] CN2_addr_wr_01_00 = 9'd511; + reg [ 8:0] CN2_addr_wr_02_00 = 9'd511; + reg [ 8:0] CN2_addr_wr_03_00 = 9'd511; + reg [ 9:0] CN2_addr_wr_04_02 = 10'd1023; + reg [ 9:0] CN2_addr_wr_04_03 = 10'd511; + reg [ 8:0] CN2_addr_wr_04_04 = 9'd511; + //RAM写地址，H阵第３行 + reg [ 8:0] CN3_addr_wr_01_00 = 9'd511; + reg [ 9:0] CN3_addr_wr_02_05 = 10'd1023; + reg [ 9:0] CN3_addr_wr_02_06 = 10'd511; + reg [ 9:0] CN3_addr_wr_03_07 = 10'd1023; + reg [ 9:0] CN3_addr_wr_03_08 = 10'd511; + reg [ 8:0] CN3_addr_wr_04_00 = 9'd511; + + //RAM写数据，H阵第１行 + reg [WIDTH-1:0] CN1_din_01_00 = 8'd0; + reg [WIDTH-1:0] CN1_din_02_00 = 8'd0; + reg [WIDTH-1:0] CN1_din_02_01 = 8'd0; + //RAM写数据，H阵第２行 + reg [WIDTH-1:0] CN2_din_01_00 = 8'd0; + reg [WIDTH-1:0] CN2_din_02_00 = 8'd0; + reg [WIDTH-1:0] CN2_din_03_00 = 8'd0; + reg [WIDTH-1:0] CN2_din_04_02 = 8'd0; + reg [WIDTH-1:0] CN2_din_04_03 = 8'd0; + reg [WIDTH-1:0] CN2_din_04_04 = 8'd0; + //RAM写数据，H阵第３行 + reg [WIDTH-1:0] CN3_din_01_00 = 8'd0; + reg [WIDTH-1:0] CN3_din_02_05 = 8'd0; + reg [WIDTH-1:0] CN3_din_02_06 = 8'd0; + reg [WIDTH-1:0] CN3_din_03_07 = 8'd0; + reg [WIDTH-1:0] CN3_din_03_08 = 8'd0; + reg [WIDTH-1:0] CN3_din_04_00 = 8'd0; + + + //RAM读地址，H阵第１行 + reg [ 8:0] CN1_addr_rd_01_00 = 9'd511; + //RAM读地址，H阵第２行 + reg [ 8:0] CN2_addr_rd_01_00 = 9'd511; + reg [ 8:0] CN2_addr_rd_02_00 = 9'd511; //7.23 xhx 因为IM&II1，II2&II3,II5&II6,II7&II8是两两写在真双口RAM中，读写地址是同一个，需要分情况考虑 + reg [ 8:0] CN2_addr_rd_03_00 = 9'd511; + reg [ 8:0] CN2_addr_rd_04_04 = 9'd511; + //RAM读地址，H阵第３行 + reg [ 8:0] CN3_addr_rd_01_00 = 9'd511; + reg [ 8:0] CN3_addr_rd_04_00 = 9'd511; + + //RAM数据输出，H阵第１行 + wire [WIDTH-1:0] CN1_dout_01_00; + wire [WIDTH-1:0] CN1_dout_02_00; //后面的00代表H阵原模图的IM + wire [WIDTH-1:0] CN1_dout_02_01; //后面的01代表H阵原模图的II1 + //RAM数据输出，H阵第２行 + wire [WIDTH-1:0] CN2_dout_01_00; + wire [WIDTH-1:0] CN2_dout_02_00; + wire [WIDTH-1:0] CN2_dout_03_00; + wire [WIDTH-1:0] CN2_dout_04_02; //后面的02代表H阵原模图的II2 + wire [WIDTH-1:0] CN2_dout_04_03; //后面的03代表H阵原模图的II3 + wire [WIDTH-1:0] CN2_dout_04_04; //后面的04代表H阵原模图的II4 + //RAM数据输出，H阵第３行 + wire [WIDTH-1:0] CN3_dout_01_00; + wire [WIDTH-1:0] CN3_dout_02_05; //后面的05代表H阵原模图的II5 + wire [WIDTH-1:0] CN3_dout_02_06; //后面的06代表H阵原模图的II6 + wire [WIDTH-1:0] CN3_dout_03_07; //后面的07代表H阵原模图的II7 + wire [WIDTH-1:0] CN3_dout_03_08; //后面的08代表H阵原模图的II8 + wire [WIDTH-1:0] CN3_dout_04_00; + + + //*****变量节点信息存储RAM信号定义 + reg VN_wea = 1'd0; + + //RAM写地址，H阵第１行 + reg [ 8:0] VN1_addr_wr_01_00 = 9'd511; + reg [ 9:0] VN1_addr_wr_02_00 = 10'd1023; + reg [ 9:0] VN1_addr_wr_02_01 = 10'd511; + //RAM写地址，H阵第２行 + reg [ 8:0] VN2_addr_wr_01_00 = 9'd511; + reg [ 8:0] VN2_addr_wr_02_00 = 9'd511; + reg [ 8:0] VN2_addr_wr_03_00 = 9'd511; + reg [ 9:0] VN2_addr_wr_04_02 = 10'd1023; + reg [ 9:0] VN2_addr_wr_04_03 = 10'd511; + reg [ 8:0] VN2_addr_wr_04_04 = 9'd511; + //RAM写地址，H阵第３行 + reg [ 8:0] VN3_addr_wr_01_00 = 9'd511; + reg [ 9:0] VN3_addr_wr_02_05 = 10'd1023; + reg [ 9:0] VN3_addr_wr_02_06 = 10'd511; + reg [ 9:0] VN3_addr_wr_03_07 = 10'd1023; + reg [ 9:0] VN3_addr_wr_03_08 = 10'd511; + reg [ 8:0] VN3_addr_wr_04_00 = 9'd511; + + + //RAM写数据，H阵第１行 + reg [WIDTH-1:0] VN1_din_01_00 = 8'd0; + reg [WIDTH-1:0] VN1_din_02_00 = 8'd0; + reg [WIDTH-1:0] VN1_din_02_01 = 8'd0; + //RAM写数据，H阵第２行 + reg [WIDTH-1:0] VN2_din_01_00 = 8'd0; + reg [WIDTH-1:0] VN2_din_02_00 = 8'd0; + reg [WIDTH-1:0] VN2_din_03_00 = 8'd0; + reg [WIDTH-1:0] VN2_din_04_02 = 8'd0; + reg [WIDTH-1:0] VN2_din_04_03 = 8'd0; + reg [WIDTH-1:0] VN2_din_04_04 = 8'd0; + //RAM写数据，H阵第３行 + reg [WIDTH-1:0] VN3_din_01_00 = 8'd0; + reg [WIDTH-1:0] VN3_din_02_05 = 8'd0; + reg [WIDTH-1:0] VN3_din_02_06 = 8'd0; + reg [WIDTH-1:0] VN3_din_03_07 = 8'd0; + reg [WIDTH-1:0] VN3_din_03_08 = 8'd0; + reg [WIDTH-1:0] VN3_din_04_00 = 8'd0; + + + //RAM读地址，H阵第１行 + reg [ 8:0] VN1_addr_rd_01_00 = 9'd511; + //RAM读地址，H阵第２行 + reg [ 8:0] VN2_addr_rd_01_00 = 9'd511; + reg [ 8:0] VN2_addr_rd_02_00 = 9'd511; + reg [ 8:0] VN2_addr_rd_03_00 = 9'd511; //7.23 xhx 同CN_RAM读地址 + reg [ 8:0] VN2_addr_rd_04_04 = 9'd511; + //RAM读地址，H阵第３行 + reg [ 8:0] VN3_addr_rd_01_00 = 9'd511; + reg [ 8:0] VN3_addr_rd_04_00 = 9'd511; + + //RAM数据输出，H阵第１行 + wire [WIDTH-1:0] VN1_dout_01_00; + wire [WIDTH-1:0] VN1_dout_02_00; //后面的00代表H阵原模图的IM + wire [WIDTH-1:0] VN1_dout_02_01; //后面的01代表H阵原模图的II1 + //RAM数据输出，H阵第２行 + wire [WIDTH-1:0] VN2_dout_01_00; + wire [WIDTH-1:0] VN2_dout_02_00; + wire [WIDTH-1:0] VN2_dout_03_00; + wire [WIDTH-1:0] VN2_dout_04_02; //后面的02代表H阵原模图的II2 + wire [WIDTH-1:0] VN2_dout_04_03; //后面的03代表H阵原模图的II3 + wire [WIDTH-1:0] VN2_dout_04_04; //后面的04代表H阵原模图的II4 + //RAM数据输出，H阵第３行 + wire [WIDTH-1:0] VN3_dout_01_00; + wire [WIDTH-1:0] VN3_dout_02_05; //后面的05代表H阵原模图的II5 + wire [WIDTH-1:0] VN3_dout_02_06; //后面的06代表H阵原模图的II6 + wire [WIDTH-1:0] VN3_dout_03_07; //后面的07代表H阵原模图的II7 + wire [WIDTH-1:0] VN3_dout_03_08; //后面的08代表H阵原模图的II8 + wire [WIDTH-1:0] VN3_dout_04_00; + + //*****判决结果存储RAM信号定义 + reg [ 0:0] DR_wea = 1'd0; + reg [ 8:0] DR_addr_wr = 9'd511; + + reg [ 0:0] DR_din_01 = 1'd0; + reg [ 0:0] DR_din_02 = 1'd0; + reg [ 0:0] DR_din_03 = 1'd0; + reg [ 0:0] DR_din_04 = 1'd0; + // reg [0:0] DR_din_05=1'd0; + + reg [ 8:0] DR_addr_rd_01 = 9'd511; + reg [ 8:0] DR_addr_rd_02 = 9'd511; + reg [ 8:0] DR_addr_rd_03 = 9'd511; + reg [ 8:0] DR_addr_rd_04 = 9'd511; + // reg [8:0] DR_addr_rd_05=9'd511; + + wire DR_dout_01; + wire DR_dout_02; + wire DR_dout_03; + wire DR_dout_04; + // wire DR_dout_05; + + reg Switch_VN_CN = 1'd0; + // Switch_VN_CN用于指示当前处于VN更新状态（值为0）还是CN更新状态（值为1） + // 由于存储器用的是True dual RAM，因此要考虑读写地址线相同的RAM在VN及CN + // 状态对应不同的地址，因此不能在上述两种状态下对其赋不同的值，故需要该 + // 该变量指示当前状态。 + always @(posedge clk) begin + if (rst) Switch_VN_CN <= 1'd0; + else begin + if (start_VN) Switch_VN_CN <= 1'd0; + else if (start_CN) Switch_VN_CN <= 1'd1; + else Switch_VN_CN <= Switch_VN_CN; + end + end + + //******列更新模块 + //输入信号 + always @(posedge clk) begin + rst_VN <= rst; + start_VN <= (rst) ? 1'd0 : ((start || end_CN) ? 1'd1 : 1'd0); + start_frame_VN <= start; + CHNL_dout_01_VN <= din01; + CHNL_dout_02_VN <= din02; + CHNL_dout_03_VN <= din03; + CHNL_dout_04_VN <= din04; + + CN1_dout_01_00_VN <= CN1_dout_01_00; + CN1_dout_02_00_VN <= CN1_dout_02_00; + CN1_dout_02_01_VN <= CN1_dout_02_01; + CN2_dout_01_00_VN <= CN2_dout_01_00; + CN2_dout_02_00_VN <= CN2_dout_02_00; + CN2_dout_03_00_VN <= CN2_dout_03_00; + CN2_dout_04_02_VN <= CN2_dout_04_02; + CN2_dout_04_03_VN <= CN2_dout_04_03; + CN2_dout_04_04_VN <= CN2_dout_04_04; + CN3_dout_01_00_VN <= CN3_dout_01_00; + CN3_dout_02_05_VN <= CN3_dout_02_05; + CN3_dout_02_06_VN <= CN3_dout_02_06; + CN3_dout_03_07_VN <= CN3_dout_03_07; + CN3_dout_03_08_VN <= CN3_dout_03_08; + CN3_dout_04_00_VN <= CN3_dout_04_00; + end + + // 输出信号 // Switch_VN_CN用于指示当前处于VN更新状态（值为0）还是CN更新状态（值为1） + always @(posedge clk) begin + CN1_addr_wr_02_00 <= (Switch_VN_CN == 1'd0) ? CN1_addr_rd_02_00_VN : CN1_addr_wr_02_00_CN; + CN1_addr_wr_02_01 <= (Switch_VN_CN == 1'd0) ? CN1_addr_rd_02_01_VN : CN1_addr_wr_02_01_CN; + CN2_addr_wr_04_02 <= (Switch_VN_CN == 1'd0) ? CN2_addr_rd_04_02_VN : CN2_addr_wr_04_02_CN; + CN2_addr_wr_04_03 <= (Switch_VN_CN == 1'd0) ? CN2_addr_rd_04_03_VN : CN2_addr_wr_04_03_CN; + CN3_addr_wr_02_05 <= (Switch_VN_CN == 1'd0) ? CN3_addr_rd_02_05_VN : CN3_addr_wr_02_05_CN; + CN3_addr_wr_02_06 <= (Switch_VN_CN == 1'd0) ? CN3_addr_rd_02_06_VN : CN3_addr_wr_02_06_CN; + CN3_addr_wr_03_07 <= (Switch_VN_CN == 1'd0) ? CN3_addr_rd_03_07_VN : CN3_addr_wr_03_07_CN; + CN3_addr_wr_03_08 <= (Switch_VN_CN == 1'd0) ? CN3_addr_rd_03_08_VN : CN3_addr_wr_03_08_CN; + + CN1_addr_rd_01_00 <= CN1_addr_rd_01_00_VN; + CN2_addr_rd_01_00 <= CN2_addr_rd_01_00_VN; + CN2_addr_rd_02_00 <= CN2_addr_rd_02_00_VN; + CN2_addr_rd_03_00 <= CN2_addr_rd_03_00_VN; + CN2_addr_rd_04_04 <= CN2_addr_rd_04_04_VN; + CN3_addr_rd_01_00 <= CN3_addr_rd_01_00_VN; + CN3_addr_rd_04_00 <= CN3_addr_rd_04_00_VN; + + VN1_addr_wr_01_00 <= VN1_addr_wr_01_00_VN; + VN2_addr_wr_01_00 <= VN2_addr_wr_01_00_VN; + VN2_addr_wr_02_00 <= VN2_addr_wr_02_00_VN; + VN2_addr_wr_03_00 <= VN2_addr_wr_03_00_VN; + VN2_addr_wr_04_04 <= VN2_addr_wr_04_04_VN; + VN3_addr_wr_01_00 <= VN3_addr_wr_01_00_VN; + VN3_addr_wr_04_00 <= VN3_addr_wr_04_00_VN; + + VN_wea <= VN_wea_VN; + + VN1_din_01_00 <= VN1_din_01_00_VN; + VN1_din_02_00 <= VN1_din_02_00_VN; + VN1_din_02_01 <= VN1_din_02_01_VN; + VN2_din_01_00 <= VN2_din_01_00_VN; + VN2_din_02_00 <= VN2_din_02_00_VN; + VN2_din_03_00 <= VN2_din_03_00_VN; + VN2_din_04_02 <= VN2_din_04_02_VN; + VN2_din_04_03 <= VN2_din_04_03_VN; + VN2_din_04_04 <= VN2_din_04_04_VN; + VN3_din_01_00 <= VN3_din_01_00_VN; + VN3_din_02_05 <= VN3_din_02_05_VN; + VN3_din_02_06 <= VN3_din_02_06_VN; + VN3_din_03_07 <= VN3_din_03_07_VN; + VN3_din_03_08 <= VN3_din_03_08_VN; + VN3_din_04_00 <= VN3_din_04_00_VN; + + DR_wea <= DR_wea_VN; + DR_addr_wr <= DR_addr_wr_VN; + DR_din_01 <= DR_din_01_VN; + DR_din_02 <= DR_din_02_VN; + DR_din_03 <= DR_din_03_VN; + DR_din_04 <= DR_din_04_VN; + // DR_din_05 <= DR_din_05_VN; + + + end + + //******行更新模块 + // 输入信号 + always @(posedge clk) begin + rst_CN <= rst; + start_CN <= end_VN; + VN1_dout_01_00_CN <= VN1_dout_01_00; + VN1_dout_02_00_CN <= VN1_dout_02_00; + VN1_dout_02_01_CN <= VN1_dout_02_01; + VN2_dout_01_00_CN <= VN2_dout_01_00; + VN2_dout_02_00_CN <= VN2_dout_02_00; + VN2_dout_03_00_CN <= VN2_dout_03_00; + VN2_dout_04_02_CN <= VN2_dout_04_02; + VN2_dout_04_03_CN <= VN2_dout_04_03; + VN2_dout_04_04_CN <= VN2_dout_04_04; + VN3_dout_01_00_CN <= VN3_dout_01_00; + VN3_dout_02_05_CN <= VN3_dout_02_05; + VN3_dout_02_06_CN <= VN3_dout_02_06; + VN3_dout_03_07_CN <= VN3_dout_03_07; + VN3_dout_03_08_CN <= VN3_dout_03_08; + VN3_dout_04_00_CN <= VN3_dout_04_00; + end + + // 输出信号 // Switch_VN_CN用于指示当前处于VN更新状态（值为0）还是CN更新状态（值为1） + always @(posedge clk) begin + VN1_addr_wr_02_00 <= (Switch_VN_CN == 1'd1) ? VN1_addr_rd_02_00_CN : VN1_addr_wr_02_00_VN; + VN1_addr_wr_02_01 <= (Switch_VN_CN == 1'd1) ? VN1_addr_rd_02_01_CN : VN1_addr_wr_02_01_VN; + VN2_addr_wr_04_02 <= (Switch_VN_CN == 1'd1) ? VN2_addr_rd_04_02_CN : VN2_addr_wr_04_02_VN; + VN2_addr_wr_04_03 <= (Switch_VN_CN == 1'd1) ? VN2_addr_rd_04_03_CN : VN2_addr_wr_04_03_VN; + VN3_addr_wr_02_05 <= (Switch_VN_CN == 1'd1) ? VN3_addr_rd_02_05_CN : VN3_addr_wr_02_05_VN; + VN3_addr_wr_02_06 <= (Switch_VN_CN == 1'd1) ? VN3_addr_rd_02_06_CN : VN3_addr_wr_02_06_VN; + VN3_addr_wr_03_07 <= (Switch_VN_CN == 1'd1) ? VN3_addr_rd_03_07_CN : VN3_addr_wr_03_07_VN; + VN3_addr_wr_03_08 <= (Switch_VN_CN == 1'd1) ? VN3_addr_rd_03_08_CN : VN3_addr_wr_03_08_VN; + + VN1_addr_rd_01_00 <= VN1_addr_rd_01_00_CN; + VN2_addr_rd_01_00 <= VN2_addr_rd_01_00_CN; + VN2_addr_rd_02_00 <= VN2_addr_rd_02_00_CN; + VN2_addr_rd_03_00 <= VN2_addr_rd_03_00_CN; + VN2_addr_rd_04_04 <= VN2_addr_rd_04_04_CN; + VN3_addr_rd_01_00 <= VN3_addr_rd_01_00_CN; + VN3_addr_rd_04_00 <= VN3_addr_rd_04_00_CN; + + CN_wea <= CN_wea_CN; + + CN1_addr_wr_01_00 <= CN1_addr_wr_01_00_CN; + CN2_addr_wr_01_00 <= CN2_addr_wr_01_00_CN; + CN2_addr_wr_02_00 <= CN2_addr_wr_02_00_CN; + CN2_addr_wr_03_00 <= CN2_addr_wr_03_00_CN; + CN2_addr_wr_04_04 <= CN2_addr_wr_04_04_CN; + CN3_addr_wr_01_00 <= CN3_addr_wr_01_00_CN; + CN3_addr_wr_04_00 <= CN3_addr_wr_04_00_CN; + + CN1_din_01_00 <= CN1_din_01_00_CN; + CN1_din_02_00 <= CN1_din_02_00_CN; + CN1_din_02_01 <= CN1_din_02_01_CN; + CN2_din_01_00 <= CN2_din_01_00_CN; + CN2_din_02_00 <= CN2_din_02_00_CN; + CN2_din_03_00 <= CN2_din_03_00_CN; + CN2_din_04_02 <= CN2_din_04_02_CN; + CN2_din_04_03 <= CN2_din_04_03_CN; + CN2_din_04_04 <= CN2_din_04_04_CN; + CN3_din_01_00 <= CN3_din_01_00_CN; + CN3_din_02_05 <= CN3_din_02_05_CN; + CN3_din_02_06 <= CN3_din_02_06_CN; + CN3_din_03_07 <= CN3_din_03_07_CN; + CN3_din_03_08 <= CN3_din_03_08_CN; + CN3_din_04_00 <= CN3_din_04_00_CN; + end + + VN_PRO #( + .MAX_ITER_NUM(MAX_ITER_NUM), + .WIDTH(WIDTH) + ) inst_VN_PRO ( + .clk (clk), + .rst_VN (rst_VN), + .start_VN (start_VN), + .start_frame_VN (start_frame_VN), + .CHNL_dout_01 (CHNL_dout_01_VN), + .CHNL_dout_02 (CHNL_dout_02_VN), + .CHNL_dout_03 (CHNL_dout_03_VN), + .CHNL_dout_04 (CHNL_dout_04_VN), + .CN1_dout_01_00 (CN1_dout_01_00_VN), + .CN1_dout_02_00 (CN1_dout_02_00_VN), + .CN1_dout_02_01 (CN1_dout_02_01_VN), + .CN2_dout_01_00 (CN2_dout_01_00_VN), + .CN2_dout_02_00 (CN2_dout_02_00_VN), + .CN2_dout_03_00 (CN2_dout_03_00_VN), + .CN2_dout_04_02 (CN2_dout_04_02_VN), + .CN2_dout_04_03 (CN2_dout_04_03_VN), + .CN2_dout_04_04 (CN2_dout_04_04_VN), + .CN3_dout_01_00 (CN3_dout_01_00_VN), + .CN3_dout_02_05 (CN3_dout_02_05_VN), + .CN3_dout_02_06 (CN3_dout_02_06_VN), + .CN3_dout_03_07 (CN3_dout_03_07_VN), + .CN3_dout_03_08 (CN3_dout_03_08_VN), + .CN3_dout_04_00 (CN3_dout_04_00_VN), + .ask_din (ask_din_VN), + .CN1_addr_rd_01_00(CN1_addr_rd_01_00_VN), + .CN1_addr_rd_02_00(CN1_addr_rd_02_00_VN), + .CN1_addr_rd_02_01(CN1_addr_rd_02_01_VN), + .CN2_addr_rd_01_00(CN2_addr_rd_01_00_VN), + .CN2_addr_rd_02_00(CN2_addr_rd_02_00_VN), + .CN2_addr_rd_03_00(CN2_addr_rd_03_00_VN), + .CN2_addr_rd_04_02(CN2_addr_rd_04_02_VN), + .CN2_addr_rd_04_03(CN2_addr_rd_04_03_VN), + .CN2_addr_rd_04_04(CN2_addr_rd_04_04_VN), + .CN3_addr_rd_01_00(CN3_addr_rd_01_00_VN), + .CN3_addr_rd_02_05(CN3_addr_rd_02_05_VN), + .CN3_addr_rd_02_06(CN3_addr_rd_02_06_VN), + .CN3_addr_rd_03_07(CN3_addr_rd_03_07_VN), + .CN3_addr_rd_03_08(CN3_addr_rd_03_08_VN), + .CN3_addr_rd_04_00(CN3_addr_rd_04_00_VN), + .VN_wea (VN_wea_VN), + .VN1_addr_wr_01_00(VN1_addr_wr_01_00_VN), + .VN1_addr_wr_02_00(VN1_addr_wr_02_00_VN), + .VN1_addr_wr_02_01(VN1_addr_wr_02_01_VN), + .VN2_addr_wr_01_00(VN2_addr_wr_01_00_VN), + .VN2_addr_wr_02_00(VN2_addr_wr_02_00_VN), + .VN2_addr_wr_03_00(VN2_addr_wr_03_00_VN), + .VN2_addr_wr_04_02(VN2_addr_wr_04_02_VN), + .VN2_addr_wr_04_03(VN2_addr_wr_04_03_VN), + .VN2_addr_wr_04_04(VN2_addr_wr_04_04_VN), + .VN3_addr_wr_01_00(VN3_addr_wr_01_00_VN), + .VN3_addr_wr_02_05(VN3_addr_wr_02_05_VN), + .VN3_addr_wr_02_06(VN3_addr_wr_02_06_VN), + .VN3_addr_wr_03_07(VN3_addr_wr_03_07_VN), + .VN3_addr_wr_03_08(VN3_addr_wr_03_08_VN), + .VN3_addr_wr_04_00(VN3_addr_wr_04_00_VN), + .VN1_din_01_00 (VN1_din_01_00_VN), + .VN1_din_02_00 (VN1_din_02_00_VN), + .VN1_din_02_01 (VN1_din_02_01_VN), + .VN2_din_01_00 (VN2_din_01_00_VN), + .VN2_din_02_00 (VN2_din_02_00_VN), + .VN2_din_03_00 (VN2_din_03_00_VN), + .VN2_din_04_02 (VN2_din_04_02_VN), + .VN2_din_04_03 (VN2_din_04_03_VN), + .VN2_din_04_04 (VN2_din_04_04_VN), + .VN3_din_01_00 (VN3_din_01_00_VN), + .VN3_din_02_05 (VN3_din_02_05_VN), + .VN3_din_02_06 (VN3_din_02_06_VN), + .VN3_din_03_07 (VN3_din_03_07_VN), + .VN3_din_03_08 (VN3_din_03_08_VN), + .VN3_din_04_00 (VN3_din_04_00_VN), + .DR_wea (DR_wea_VN), + .DR_addr_wr (DR_addr_wr_VN), + .DR_din_01 (DR_din_01_VN), + .DR_din_02 (DR_din_02_VN), + .DR_din_03 (DR_din_03_VN), + .DR_din_04 (DR_din_04_VN), + .DR_din_05 (DR_din_05_VN), + .data_start_ck_VN (data_start_ck_VN), + .data_start_VN (data_start_VN), + .end_VN (end_VN) + ); + + + + CN_PRO #( + .WIDTH(WIDTH) + ) inst_CN_PRO ( + .clk (clk), + .rst_CN (rst_CN), + .start_CN (start_CN), + .VN1_dout_01_00 (VN1_dout_01_00_CN), + .VN1_dout_02_00 (VN1_dout_02_00_CN), + .VN1_dout_02_01 (VN1_dout_02_01_CN), + .VN2_dout_01_00 (VN2_dout_01_00_CN), + .VN2_dout_02_00 (VN2_dout_02_00_CN), + .VN2_dout_03_00 (VN2_dout_03_00_CN), + .VN2_dout_04_02 (VN2_dout_04_02_CN), + .VN2_dout_04_03 (VN2_dout_04_03_CN), + .VN2_dout_04_04 (VN2_dout_04_04_CN), + .VN3_dout_01_00 (VN3_dout_01_00_CN), + .VN3_dout_02_05 (VN3_dout_02_05_CN), + .VN3_dout_02_06 (VN3_dout_02_06_CN), + .VN3_dout_03_07 (VN3_dout_03_07_CN), + .VN3_dout_03_08 (VN3_dout_03_08_CN), + .VN3_dout_04_00 (VN3_dout_04_00_CN), + .VN1_addr_rd_01_00(VN1_addr_rd_01_00_CN), + .VN1_addr_rd_02_00(VN1_addr_rd_02_00_CN), + .VN1_addr_rd_02_01(VN1_addr_rd_02_01_CN), + .VN2_addr_rd_01_00(VN2_addr_rd_01_00_CN), + .VN2_addr_rd_02_00(VN2_addr_rd_02_00_CN), + .VN2_addr_rd_03_00(VN2_addr_rd_03_00_CN), + .VN2_addr_rd_04_02(VN2_addr_rd_04_02_CN), + .VN2_addr_rd_04_03(VN2_addr_rd_04_03_CN), + .VN2_addr_rd_04_04(VN2_addr_rd_04_04_CN), + .VN3_addr_rd_01_00(VN3_addr_rd_01_00_CN), + .VN3_addr_rd_02_05(VN3_addr_rd_02_05_CN), + .VN3_addr_rd_02_06(VN3_addr_rd_02_06_CN), + .VN3_addr_rd_03_07(VN3_addr_rd_03_07_CN), + .VN3_addr_rd_03_08(VN3_addr_rd_03_08_CN), + .VN3_addr_rd_04_00(VN3_addr_rd_04_00_CN), + .CN_wea (CN_wea_CN), + .CN1_addr_wr_01_00(CN1_addr_wr_01_00_CN), + .CN1_addr_wr_02_00(CN1_addr_wr_02_00_CN), + .CN1_addr_wr_02_01(CN1_addr_wr_02_01_CN), + .CN2_addr_wr_01_00(CN2_addr_wr_01_00_CN), + .CN2_addr_wr_02_00(CN2_addr_wr_02_00_CN), + .CN2_addr_wr_03_00(CN2_addr_wr_03_00_CN), + .CN2_addr_wr_04_02(CN2_addr_wr_04_02_CN), + .CN2_addr_wr_04_03(CN2_addr_wr_04_03_CN), + .CN2_addr_wr_04_04(CN2_addr_wr_04_04_CN), + .CN3_addr_wr_01_00(CN3_addr_wr_01_00_CN), + .CN3_addr_wr_02_05(CN3_addr_wr_02_05_CN), + .CN3_addr_wr_02_06(CN3_addr_wr_02_06_CN), + .CN3_addr_wr_03_07(CN3_addr_wr_03_07_CN), + .CN3_addr_wr_03_08(CN3_addr_wr_03_08_CN), + .CN3_addr_wr_04_00(CN3_addr_wr_04_00_CN), + .CN1_din_01_00 (CN1_din_01_00_CN), + .CN1_din_02_00 (CN1_din_02_00_CN), + .CN1_din_02_01 (CN1_din_02_01_CN), + .CN2_din_01_00 (CN2_din_01_00_CN), + .CN2_din_02_00 (CN2_din_02_00_CN), + .CN2_din_03_00 (CN2_din_03_00_CN), + .CN2_din_04_02 (CN2_din_04_02_CN), + .CN2_din_04_03 (CN2_din_04_03_CN), + .CN2_din_04_04 (CN2_din_04_04_CN), + .CN3_din_01_00 (CN3_din_01_00_CN), + .CN3_din_02_05 (CN3_din_02_05_CN), + .CN3_din_02_06 (CN3_din_02_06_CN), + .CN3_din_03_07 (CN3_din_03_07_CN), + .CN3_din_03_08 (CN3_din_03_08_CN), + .CN3_din_04_00 (CN3_din_04_00_CN), + .end_CN (end_CN) + ); + + //******译码结果校验模块 + // 输入信号 + reg rst_CK = 1'd0; + reg start_CK = 1'd0; + reg nd_CK = 1'd0; + reg DR_din_01_CK = 1'd0; + reg DR_din_02_CK = 1'd0; + reg DR_din_03_CK = 1'd0; + reg DR_din_04_CK = 1'd0; + reg DR_din_05_CK = 1'd0; + + always @(posedge clk) begin + rst_CK <= rst; + start_CK <= data_start_ck_VN; + nd_CK <= DR_wea_VN; + DR_din_01_CK <= DR_din_01_VN; + DR_din_02_CK <= DR_din_02_VN; + DR_din_03_CK <= DR_din_03_VN; + DR_din_04_CK <= DR_din_04_VN; + DR_din_05_CK <= DR_din_05_VN; + end + + // 输出信号 + wire [8:0] gd_frames_CK; + wire [8:0] bd_frames_CK; + wire [8:0] tl_frames_CK; + always @(posedge clk) begin + gd_frames <= gd_frames_CK; + bd_frames <= bd_frames_CK; + tl_frames <= tl_frames_CK; + end + CK_PRO inst_CK_PRO ( + .clk (clk), + .rst_OUTCK (rst_CK), + .start_OUTCK(start_CK), + .nd_OUTCK (nd_CK), + .DR_din_01 (DR_din_01_CK), + .DR_din_02 (DR_din_02_CK), + .DR_din_03 (DR_din_03_CK), + .DR_din_04 (DR_din_04_CK), + .DR_din_05 (DR_din_05_CK), + .gd_frames (gd_frames_CK), + .bd_frames (bd_frames_CK), + .tl_frames (tl_frames_CK) + ); + //******译码结果输出模块 + // 输入信号 + reg start_OUT = 1'd0; + reg rst_OUT = 1'd0; + reg DR_dout_01_OUT = 1'd0; + reg DR_dout_02_OUT = 1'd0; + reg DR_dout_03_OUT = 1'd0; + reg DR_dout_04_OUT = 1'd0; + + always @(posedge clk) begin + start_OUT <= data_start_VN; + rst_OUT <= rst; + DR_dout_01_OUT <= DR_dout_01; + DR_dout_02_OUT <= DR_dout_02; + DR_dout_03_OUT <= DR_dout_03; + DR_dout_04_OUT <= DR_dout_04; + end + // 输出信号 + wire ldpc_syncout_OUT; + wire rdy_OUT; + wire ldpc_dout_OUT; + wire [8:0] DR_addr_rd_01_OUT; + wire [8:0] DR_addr_rd_02_OUT; + wire [8:0] DR_addr_rd_03_OUT; + wire [8:0] DR_addr_rd_04_OUT; + + always @(posedge clk) begin + DR_addr_rd_01 <= DR_addr_rd_01_OUT; + DR_addr_rd_02 <= DR_addr_rd_02_OUT; + DR_addr_rd_03 <= DR_addr_rd_03_OUT; + DR_addr_rd_04 <= DR_addr_rd_04_OUT; + ldpc_syncout <= ldpc_syncout_OUT; + rdy <= rdy_OUT; + ldpc_dout <= ldpc_dout_OUT; + ask_din <= ask_din_VN; + end + OUT_PRO #( + .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION) + ) inst_OUT_PRO ( + .clk (clk), + .rst_OUT (rst_OUT), + .start_OUT (start_OUT), + .DR_dout_01 (DR_dout_01_OUT), + .DR_dout_02 (DR_dout_02_OUT), + .DR_dout_03 (DR_dout_03_OUT), + .DR_dout_04 (DR_dout_04_OUT), + .DR_addr_rd_01 (DR_addr_rd_01_OUT), + .DR_addr_rd_02 (DR_addr_rd_02_OUT), + .DR_addr_rd_03 (DR_addr_rd_03_OUT), + .DR_addr_rd_04 (DR_addr_rd_04_OUT), + .ldpc_syncout_OUT(ldpc_syncout_OUT), + .rdy_OUT (rdy_OUT), + .ldpc_dout_OUT (ldpc_dout_OUT) + ); + //******校验节点信息存储RAM + // H阵第1行 + RAM_512X1_8 RAM_CN_01 ( + .clka (clk), + .wea (CN_wea), + .addra(CN1_addr_wr_01_00), + .dina (CN1_din_01_00), + .clkb (clk), + .addrb(CN1_addr_rd_01_00), + .doutb(CN1_dout_01_00) + ); + RAM_512X2_8 RAM_CN_02 ( + .clka (clk), + .wea (CN_wea), + .addra(CN1_addr_wr_02_00), + .dina (CN1_din_02_00), + .douta(CN1_dout_02_00), + .clkb (clk), + .web (CN_wea), + .addrb(CN1_addr_wr_02_01), + .dinb (CN1_din_02_01), + .doutb(CN1_dout_02_01) + ); + // H阵第2行 + RAM_512X1_8 RAM_CN_03 ( + .clka (clk), + .wea (CN_wea), + .addra(CN2_addr_wr_01_00), + .dina (CN2_din_01_00), + .clkb (clk), + .addrb(CN2_addr_rd_01_00), + .doutb(CN2_dout_01_00) + ); + RAM_512X1_8 RAM_CN_04 ( + .clka (clk), + .wea (CN_wea), + .addra(CN2_addr_wr_02_00), + .dina (CN2_din_02_00), + .clkb (clk), + .addrb(CN2_addr_rd_02_00), + .doutb(CN2_dout_02_00) + ); + RAM_512X1_8 RAM_CN_05 ( + .clka (clk), + .wea (CN_wea), + .addra(CN2_addr_wr_03_00), + .dina (CN2_din_03_00), + .clkb (clk), + .addrb(CN2_addr_rd_03_00), + .doutb(CN2_dout_03_00) + ); + RAM_512X2_8 RAM_CN_06 ( + .clka (clk), + .wea (CN_wea), + .addra(CN2_addr_wr_04_02), + .dina (CN2_din_04_02), + .douta(CN2_dout_04_02), + .clkb (clk), + .web (CN_wea), + .addrb(CN2_addr_wr_04_03), + .dinb (CN2_din_04_03), + .doutb(CN2_dout_04_03) + ); + RAM_512X1_8 RAM_CN_07 ( + .clka (clk), + .wea (CN_wea), + .addra(CN2_addr_wr_04_04), + .dina (CN2_din_04_04), + .clkb (clk), + .addrb(CN2_addr_rd_04_04), + .doutb(CN2_dout_04_04) + ); + // H阵第3行 + RAM_512X1_8 RAM_CN_08 ( + .clka (clk), + .wea (CN_wea), + .addra(CN3_addr_wr_01_00), + .dina (CN3_din_01_00), + .clkb (clk), + .addrb(CN3_addr_rd_01_00), + .doutb(CN3_dout_01_00) + ); + RAM_512X2_8 RAM_CN_09 ( + .clka (clk), + .wea (CN_wea), + .addra(CN3_addr_wr_02_05), + .dina (CN3_din_02_05), + .douta(CN3_dout_02_05), + .clkb (clk), + .web (CN_wea), + .addrb(CN3_addr_wr_02_06), + .dinb (CN3_din_02_06), + .doutb(CN3_dout_02_06) + ); + RAM_512X2_8 RAM_CN_10 ( + .clka (clk), + .wea (CN_wea), + .addra(CN3_addr_wr_03_07), + .dina (CN3_din_03_07), + .douta(CN3_dout_03_07), + .clkb (clk), + .web (CN_wea), + .addrb(CN3_addr_wr_03_08), + .dinb (CN3_din_03_08), + .doutb(CN3_dout_03_08) + ); + RAM_512X1_8 RAM_CN_11 ( + .clka (clk), + .wea (CN_wea), + .addra(CN3_addr_wr_04_00), + .dina (CN3_din_04_00), + .clkb (clk), + .addrb(CN3_addr_rd_04_00), + .doutb(CN3_dout_04_00) + ); + + //******变量节点信息存储RAM + // H阵第1行，注意H阵第1行第3列不进行列VN的列更新 + RAM_512X1_8 RAM_VN_01 ( + .clka (clk), + .wea (VN_wea), + .addra(VN1_addr_wr_01_00), + .dina (VN1_din_01_00), + .clkb (clk), + .addrb(VN1_addr_rd_01_00), + .doutb(VN1_dout_01_00) + ); + RAM_512X2_8 RAM_VN_02 ( + .clka (clk), + .wea (VN_wea), + .addra(VN1_addr_wr_02_00), + .dina (VN1_din_02_00), + .douta(VN1_dout_02_00), + .clkb (clk), + .web (VN_wea), + .addrb(VN1_addr_wr_02_01), + .dinb (VN1_din_02_01), + .doutb(VN1_dout_02_01) + ); + // H阵第2行 + RAM_512X1_8 RAM_VN_03 ( + .clka (clk), + .wea (VN_wea), + .addra(VN2_addr_wr_01_00), + .dina (VN2_din_01_00), + .clkb (clk), + .addrb(VN2_addr_rd_01_00), + .doutb(VN2_dout_01_00) + ); + RAM_512X1_8 RAM_VN_04 ( + .clka (clk), + .wea (VN_wea), + .addra(VN2_addr_wr_02_00), + .dina (VN2_din_02_00), + .clkb (clk), + .addrb(VN2_addr_rd_02_00), + .doutb(VN2_dout_02_00) + ); + RAM_512X1_8 RAM_VN_05 ( + .clka (clk), + .wea (VN_wea), + .addra(VN2_addr_wr_03_00), + .dina (VN2_din_03_00), + .clkb (clk), + .addrb(VN2_addr_rd_03_00), + .doutb(VN2_dout_03_00) + ); + RAM_512X2_8 RAM_VN_06 ( + .clka (clk), + .wea (VN_wea), + .addra(VN2_addr_wr_04_02), + .dina (VN2_din_04_02), + .douta(VN2_dout_04_02), + .clkb (clk), + .web (VN_wea), + .addrb(VN2_addr_wr_04_03), + .dinb (VN2_din_04_03), + .doutb(VN2_dout_04_03) + ); + RAM_512X1_8 RAM_VN_07 ( + .clka (clk), + .wea (VN_wea), + .addra(VN2_addr_wr_04_04), + .dina (VN2_din_04_04), + .clkb (clk), + .addrb(VN2_addr_rd_04_04), + .doutb(VN2_dout_04_04) + ); + // H阵第3行 + RAM_512X1_8 RAM_VN_08 ( + .clka (clk), + .wea (VN_wea), + .addra(VN3_addr_wr_01_00), + .dina (VN3_din_01_00), + .clkb (clk), + .addrb(VN3_addr_rd_01_00), + .doutb(VN3_dout_01_00) + ); + RAM_512X2_8 RAM_VN_09 ( + .clka (clk), + .wea (VN_wea), + .addra(VN3_addr_wr_02_05), + .dina (VN3_din_02_05), + .douta(VN3_dout_02_05), + .clkb (clk), + .web (VN_wea), + .addrb(VN3_addr_wr_02_06), + .dinb (VN3_din_02_06), + .doutb(VN3_dout_02_06) + ); + RAM_512X2_8 RAM_VN_10 ( + .clka (clk), + .wea (VN_wea), + .addra(VN3_addr_wr_03_07), + .dina (VN3_din_03_07), + .douta(VN3_dout_03_07), + .clkb (clk), + .web (VN_wea), + .addrb(VN3_addr_wr_03_08), + .dinb (VN3_din_03_08), + .doutb(VN3_dout_03_08) + ); + RAM_512X1_8 RAM_VN_11 ( + .clka (clk), + .wea (VN_wea), + .addra(VN3_addr_wr_04_00), + .dina (VN3_din_04_00), + .clkb (clk), + .addrb(VN3_addr_rd_04_00), + .doutb(VN3_dout_04_00) + ); + + + //******判决结果信息存储RAM + //注意：对于码率为1/2的CCSDS码而言，真正的码字存储在RAM_DR_01~RAM_DR_04中，RAM_DR_05只是在验证HC’==0时用。 + RAM_512_1 RAM_DR_01 ( + .clka (clk), + .wea (DR_wea), + .addra(DR_addr_wr), + .dina (DR_din_01), + .clkb (clk), + .addrb(DR_addr_rd_01), + .doutb(DR_dout_01) + ); + RAM_512_1 RAM_DR_02 ( + .clka (clk), + .wea (DR_wea), + .addra(DR_addr_wr), + .dina (DR_din_02), + .clkb (clk), + .addrb(DR_addr_rd_02), + .doutb(DR_dout_02) + ); + RAM_512_1 RAM_DR_03 ( + .clka (clk), + .wea (DR_wea), + .addra(DR_addr_wr), + .dina (DR_din_03), + .clkb (clk), + .addrb(DR_addr_rd_03), + .doutb(DR_dout_03) + ); + RAM_512_1 RAM_DR_04 ( + .clka (clk), + .wea (DR_wea), + .addra(DR_addr_wr), + .dina (DR_din_04), + .clkb (clk), + .addrb(DR_addr_rd_04), + .doutb(DR_dout_04) + ); + // RAM_512_1 RAM_DR_05 (.clka(clk),.wea(DR_wea),.addra(DR_addr_wr),.dina(DR_din_05),.clkb(clk),.addrb(DR_addr_rd_05),.doutb(DR_dout_05)); + +endmodule + diff --git a/hdl/LDPC_TopManage_2.v b/hdl/LDPC_TopManage_2.v new file mode 100644 index 0000000..c1a9382 --- /dev/null +++ b/hdl/LDPC_TopManage_2.v @@ -0,0 +1,193 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: LDPC_TopManage_2 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module LDPC_TopManage_2 #( + parameter WIDTH = 4'd8 +) ( + input clk, //工作时钟,100MHz + input Rst, //同步复位信号,高有效 + input FrameSync_TM, //帧同步标志,高脉冲 + input Nd_TM, //译码输入数据有效标志,高有效 + input [WIDTH-1:0] Din_TM, //译码输入数据,软信息 + //A + output FrameSync_A_TM, //帧同步标志,高脉冲 + output Nd_A_TM, //译码输入数据有效标志,高有效 + output [WIDTH-1:0] Din_A_TM, //译码输入数据,软信息 + //B + output FrameSync_B_TM, //帧同步标志,高脉冲 + output Nd_B_TM, //译码输入数据有效标志,高有效 + output [WIDTH-1:0] Din_B_TM, //译码输入数据,软信息 + // flag A + input LDPC_SyncOut_A_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点 + input Rdy_A_TM, //译码输出信号有效标志,高有效 + input [ 0:0] LDPC_Dout_A_TM, //译码输出信号 + input [ 8:0] good_frames_A_TM, //译码好帧计数 + input [ 8:0] bad_frames_A_TM, //译码坏帧计数 + input [ 8:0] total_frames_A_TM, //译码总帧数计数 + //flag B + input LDPC_SyncOut_B_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点 + input Rdy_B_TM, //译码输出信号有效标志,高有效 + input [ 0:0] LDPC_Dout_B_TM, //译码输出信号 + input [ 8:0] good_frames_B_TM, //译码好帧计数 + input [ 8:0] bad_frames_B_TM, //译码坏帧计数 + input [ 8:0] total_frames_B_TM, //译码总帧数计数 + //result + output LDPC_SyncOut_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点 + output Rdy_TM, //译码输出信号有效标志,高有效 + output [ 0:0] LDPC_Dout_TM, //译码输出信号 + output [ 8:0] good_frames_TM, //译码好帧计数 + output [ 8:0] bad_frames_TM, //译码坏帧计数 + output [ 8:0] total_frames_TM //译码总帧数计数 +); + + reg FrameSync_TM_reg0, FrameSync_TM_reg1; + reg Nd_TM_reg0, Nd_TM_reg1; + reg [WIDTH-1:0] Din_TM_reg0, Din_TM_reg1; + + //******输入过程控制 + always @(posedge clk) begin //接收数据缓存过程 + FrameSync_TM_reg0 <= FrameSync_TM; + FrameSync_TM_reg1 <= FrameSync_TM_reg0; + Nd_TM_reg0 <= Nd_TM; + Nd_TM_reg1 <= Nd_TM_reg0; + Din_TM_reg0 <= Din_TM; + Din_TM_reg1 <= Din_TM_reg0; + end + + reg [0:0] flag_switch_in = 1'b1; + always @(posedge clk) begin //输入乒乓控制过程 + if (Rst) begin + flag_switch_in <= 1'd1; + end + else begin + if (FrameSync_TM) begin + flag_switch_in <= ~flag_switch_in; + end + else flag_switch_in <= flag_switch_in; + end + end + + assign FrameSync_A_TM = (flag_switch_in == 1'b0) ? FrameSync_TM_reg1 : 1'b0; + assign Nd_A_TM = (flag_switch_in == 1'b0) ? Nd_TM_reg1 : 1'b0; + assign Din_A_TM = (flag_switch_in == 1'b0) ? Din_TM_reg1 : 8'd0; + + assign FrameSync_B_TM = (flag_switch_in == 1'b1) ? FrameSync_TM_reg1 : 1'b0; + assign Nd_B_TM = (flag_switch_in == 1'b1) ? Nd_TM_reg1 : 1'b0; + assign Din_B_TM = (flag_switch_in == 1'b1) ? Din_TM_reg1 : 8'd0; + + reg LDPC_SyncOut_A_TM_reg0, LDPC_SyncOut_A_TM_reg1; + reg Rdy_A_TM_reg0, Rdy_A_TM_reg1; + reg [0:0] LDPC_Dout_A_TM_reg0, LDPC_Dout_A_TM_reg1; + reg [8:0] good_frames_A_TM_reg0, good_frames_A_TM_reg1; + reg [8:0] bad_frames_A_TM_reg0, bad_frames_A_TM_reg1; + reg [8:0] total_frames_A_TM_reg0, total_frames_A_TM_reg1; + + reg LDPC_SyncOut_B_TM_reg0, LDPC_SyncOut_B_TM_reg1; + reg Rdy_B_TM_reg0, Rdy_B_TM_reg1; + reg [0:0] LDPC_Dout_B_TM_reg0, LDPC_Dout_B_TM_reg1; + reg [8:0] good_frames_B_TM_reg0, good_frames_B_TM_reg1; + reg [8:0] bad_frames_B_TM_reg0, bad_frames_B_TM_reg1; + reg [8:0] total_frames_B_TM_reg0, total_frames_B_TM_reg1; + + //******输入过程控制 + always @(posedge clk) begin //输出数据缓存过程 + if (Rst) begin + LDPC_SyncOut_A_TM_reg0 <= 1'b0; + LDPC_SyncOut_A_TM_reg1 <= 1'b0; + Rdy_A_TM_reg0 <= 1'b0; + Rdy_A_TM_reg1 <= 1'b0; + LDPC_Dout_A_TM_reg0 <= 1'b0; + LDPC_Dout_A_TM_reg1 <= 1'b0; + good_frames_A_TM_reg0 <= 9'd0; + good_frames_A_TM_reg1 <= 9'd0; + bad_frames_A_TM_reg0 <= 9'd0; + bad_frames_A_TM_reg1 <= 9'd0; + total_frames_A_TM_reg0 <= 9'd0; + total_frames_A_TM_reg1 <= 9'd0; + + LDPC_SyncOut_B_TM_reg0 <= 1'b0; + LDPC_SyncOut_B_TM_reg1 <= 1'b0; + Rdy_B_TM_reg0 <= 1'b0; + Rdy_B_TM_reg1 <= 1'b0; + LDPC_Dout_B_TM_reg0 <= 1'b0; + LDPC_Dout_B_TM_reg1 <= 1'b0; + good_frames_B_TM_reg0 <= 9'd0; + good_frames_B_TM_reg1 <= 9'd0; + bad_frames_B_TM_reg0 <= 9'd0; + bad_frames_B_TM_reg1 <= 9'd0; + total_frames_B_TM_reg0 <= 9'd0; + total_frames_B_TM_reg1 <= 9'd0; + end + else begin + LDPC_SyncOut_A_TM_reg0 <= LDPC_SyncOut_A_TM; + LDPC_SyncOut_A_TM_reg1 <= LDPC_SyncOut_A_TM_reg0; + Rdy_A_TM_reg0 <= Rdy_A_TM; + Rdy_A_TM_reg1 <= Rdy_A_TM_reg0; + LDPC_Dout_A_TM_reg0 <= LDPC_Dout_A_TM; + LDPC_Dout_A_TM_reg1 <= LDPC_Dout_A_TM_reg0; + good_frames_A_TM_reg0 <= good_frames_A_TM; + good_frames_A_TM_reg1 <= good_frames_A_TM_reg0; + bad_frames_A_TM_reg0 <= bad_frames_A_TM; + bad_frames_A_TM_reg1 <= bad_frames_A_TM_reg0; + total_frames_A_TM_reg0 <= total_frames_A_TM; + total_frames_A_TM_reg1 <= total_frames_A_TM_reg0; + + LDPC_SyncOut_B_TM_reg0 <= LDPC_SyncOut_B_TM; + LDPC_SyncOut_B_TM_reg1 <= LDPC_SyncOut_B_TM_reg0; + Rdy_B_TM_reg0 <= Rdy_B_TM; + Rdy_B_TM_reg1 <= Rdy_B_TM_reg0; + LDPC_Dout_B_TM_reg0 <= LDPC_Dout_B_TM; + LDPC_Dout_B_TM_reg1 <= LDPC_Dout_B_TM_reg0; + good_frames_B_TM_reg0 <= good_frames_B_TM; + good_frames_B_TM_reg1 <= good_frames_B_TM_reg0; + bad_frames_B_TM_reg0 <= bad_frames_B_TM; + bad_frames_B_TM_reg1 <= bad_frames_B_TM_reg0; + total_frames_B_TM_reg0 <= total_frames_B_TM; + total_frames_B_TM_reg1 <= total_frames_B_TM_reg0; + end + end + + reg [0:0] flag_switch_out = 1'b1; + always @(posedge clk) begin //输出乒乓控制过程 + if (Rst) begin + flag_switch_out <= 1'd1; + end + else begin + if (LDPC_SyncOut_A_TM || LDPC_SyncOut_B_TM) flag_switch_out <= ~flag_switch_out; + else flag_switch_out <= flag_switch_out; + end + end + + assign LDPC_SyncOut_TM = (flag_switch_out == 1'b0) ? LDPC_SyncOut_A_TM_reg1 : LDPC_SyncOut_B_TM_reg1; + assign Rdy_TM = (flag_switch_out == 1'b0) ? Rdy_A_TM_reg1 : Rdy_B_TM_reg1; + assign LDPC_Dout_TM = (flag_switch_out == 1'b0) ? LDPC_Dout_A_TM_reg1 : LDPC_Dout_B_TM_reg1; + + assign good_frames_TM = good_frames_B_TM_reg1 + good_frames_A_TM_reg1; + assign bad_frames_TM = bad_frames_B_TM_reg1 + bad_frames_A_TM_reg1; + assign total_frames_TM = total_frames_B_TM_reg1 + total_frames_A_TM_reg1; + + + + + + +endmodule diff --git a/hdl/MF_Top.v b/hdl/MF_Top.v index 6686c24..d751a7d 100644 --- a/hdl/MF_Top.v +++ b/hdl/MF_Top.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/MagnitudeEstimator.v b/hdl/MagnitudeEstimator.v index c2a057f..3a38e3b 100644 --- a/hdl/MagnitudeEstimator.v +++ b/hdl/MagnitudeEstimator.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns module MagnitudeEstimator #( parameter VEC_WIDTH = 21 diff --git a/hdl/Message_Store.v b/hdl/Message_Store.v new file mode 100644 index 0000000..3bff3ab --- /dev/null +++ b/hdl/Message_Store.v @@ -0,0 +1,385 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: Message_Store +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Message_Store #( + parameter WIDTH = 4'd8 +) ( + input clk, + input rst_MS, + input framesync_MS, //帧同步标志，高脉冲 + input nd_MS, //译码输入数据有效标志，高有效 + input [WIDTH-1:0] din_MS, //译码输入软信息 + input [ 0:0] oe_MS, //使能输出信号，高脉冲 + + output deal_end_MS, //转换完成标志 + output syncout_MS, //高脉冲 + output rdy_MS, //高有效的连续信号 + output reg [WIDTH-1:0] dout01_MS = 8'd0, // 输出数据 + output reg [WIDTH-1:0] dout02_MS = 8'd0, + output reg [WIDTH-1:0] dout03_MS = 8'd0, + output reg [WIDTH-1:0] dout04_MS = 8'd0 +); + reg [10:0] cnt_MS = 11'd0; + reg flag_end = 1'd0; + + always @(posedge clk) begin + if (rst_MS) begin + flag_end <= 11'd0; + end + else begin + if (framesync_MS) flag_end <= 1'd1; + else if (nd_MS && cnt_MS == 11'd2047) flag_end <= 1'd0; + else flag_end <= flag_end; + end + end + + // 产生基准计数 + always @(posedge clk) begin + if (rst_MS) begin + cnt_MS <= 11'd0; + end + else begin + if (flag_end) begin + if (nd_MS) cnt_MS <= cnt_MS + 11'd1; + else begin + cnt_MS <= cnt_MS; + end + end + else begin + cnt_MS <= cnt_MS; + end + end + end + + reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 = 1'd0, wea2_03 = 1'd0, wea2_04 = 1'd0; + reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'd511, addr_wr2_01 = 9'd511, addr_wr2_02 = 9'd511, addr_wr2_03 = 9'd511, addr_wr2_04 = 9'd511; + reg [WIDTH-1:0] din1_01 = 8'd0, din1_02 = 8'd0, din1_03 = 8'd0, din1_04 = 8'd0, din2_01 = 8'd0, din2_02 = 8'd0, din2_03 = 8'd0, din2_04 = 8'd0; + reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'd511, addr_rd2_01 = 9'd511, addr_rd2_02 = 9'd511, addr_rd2_03 = 9'd511, addr_rd2_04 = 9'd511; + wire [WIDTH-1:0] dout1_01, dout1_02, dout1_03, dout1_04, dout2_01, dout2_02, dout2_03, dout2_04; + + RAM_512_8 Lp1_01 ( + .clka (clk), + .wea (wea1_01), + .addra(addr_wr1_01), + .dina (din1_01), + .clkb (clk), + .addrb(addr_rd1_01), + .doutb(dout1_01) + ); + RAM_512_8 Lp1_02 ( + .clka (clk), + .wea (wea1_02), + .addra(addr_wr1_02), + .dina (din1_02), + .clkb (clk), + .addrb(addr_rd1_02), + .doutb(dout1_02) + ); + RAM_512_8 Lp1_03 ( + .clka (clk), + .wea (wea1_03), + .addra(addr_wr1_03), + .dina (din1_03), + .clkb (clk), + .addrb(addr_rd1_03), + .doutb(dout1_03) + ); + RAM_512_8 Lp1_04 ( + .clka (clk), + .wea (wea1_04), + .addra(addr_wr1_04), + .dina (din1_04), + .clkb (clk), + .addrb(addr_rd1_04), + .doutb(dout1_04) + ); + RAM_512_8 Lp2_01 ( + .clka (clk), + .wea (wea2_01), + .addra(addr_wr2_01), + .dina (din2_01), + .clkb (clk), + .addrb(addr_rd2_01), + .doutb(dout2_01) + ); + RAM_512_8 Lp2_02 ( + .clka (clk), + .wea (wea2_02), + .addra(addr_wr2_02), + .dina (din2_02), + .clkb (clk), + .addrb(addr_rd2_02), + .doutb(dout2_02) + ); + RAM_512_8 Lp2_03 ( + .clka (clk), + .wea (wea2_03), + .addra(addr_wr2_03), + .dina (din2_03), + .clkb (clk), + .addrb(addr_rd2_03), + .doutb(dout2_03) + ); + RAM_512_8 Lp2_04 ( + .clka (clk), + .wea (wea2_04), + .addra(addr_wr2_04), + .dina (din2_04), + .clkb (clk), + .addrb(addr_rd2_04), + .doutb(dout2_04) + ); + + reg flag_switch_MS = 1'd0; + always @(posedge clk) begin + if (rst_MS) flag_switch_MS <= 1'd0; + else begin + if (nd_MS && cnt_MS == 11'd2047) flag_switch_MS <= ~flag_switch_MS; + else flag_switch_MS <= flag_switch_MS; + end + end + + // 乒乓写缓存过程 + always @(posedge clk) begin + if (rst_MS) begin + wea1_01 <= 1'd0; + wea1_02 <= 1'd0; + wea1_03 <= 1'd0; + wea1_04 <= 1'd0; + wea2_01 <= 1'd0; + wea2_02 <= 1'd0; + wea2_03 <= 1'd0; + wea2_04 <= 1'd0; + addr_wr1_01 <= 9'd511; + addr_wr1_02 <= 9'd511; + addr_wr1_03 <= 9'd511; + addr_wr1_04 <= 9'd511; + addr_wr2_01 <= 9'd511; + addr_wr2_02 <= 9'd511; + addr_wr2_03 <= 9'd511; + addr_wr2_04 <= 9'd511; + din1_01 <= 8'd0; + din1_02 <= 8'd0; + din1_03 <= 8'd0; + din1_04 <= 8'd0; + din2_01 <= 8'd0; + din2_02 <= 8'd0; + din2_03 <= 8'd0; + din2_04 <= 8'd0; + end + else begin + if (nd_MS) //所有的写操作均在nd_MS有效时进行 + if (flag_switch_MS == 1'd0) begin //写第一个缓存区 + if (cnt_MS >= 11'd0 && cnt_MS < 11'd512) begin + wea1_01 <= 1'd1; + addr_wr1_01 <= addr_wr1_01 + 9'd1; + din1_01 <= din_MS; + end + else if (cnt_MS >= 11'd512 && cnt_MS < 11'd1024) begin + wea1_02 <= 1'd1; + addr_wr1_02 <= addr_wr1_02 + 9'd1; + din1_02 <= din_MS; + wea1_01 <= 1'd0; + end + else if (cnt_MS >= 11'd1024 && cnt_MS < 11'd1536) begin + wea1_03 <= 1'd1; + addr_wr1_03 <= addr_wr1_03 + 9'd1; + din1_03 <= din_MS; + wea1_02 <= 1'd0; + end + else if (cnt_MS >= 11'd1536 && cnt_MS <= 11'd2047) begin + wea1_04 <= 1'd1; + addr_wr1_04 <= addr_wr1_04 + 9'd1; + din1_04 <= din_MS; + wea1_03 <= 1'd0; + end + end + else begin + if (cnt_MS >= 11'd0 && cnt_MS < 11'd512) begin + wea2_01 <= 1'd1; + addr_wr2_01 <= addr_wr2_01 + 9'd1; + din2_01 <= din_MS; + end + else if (cnt_MS >= 11'd512 && cnt_MS < 11'd1024) begin + wea2_02 <= 1'd1; + addr_wr2_02 <= addr_wr2_02 + 9'd1; + din2_02 <= din_MS; + wea2_01 <= 1'd0; + end + else if (cnt_MS >= 11'd1024 && cnt_MS < 11'd1536) begin + wea2_03 <= 1'd1; + addr_wr2_03 <= addr_wr2_03 + 9'd1; + din2_03 <= din_MS; + wea2_02 <= 1'd0; + end + else if (cnt_MS >= 11'd1536 && cnt_MS <= 11'd2047) begin + wea2_04 <= 1'd1; + addr_wr2_04 <= addr_wr2_04 + 9'd1; + din2_04 <= din_MS; + wea2_03 <= 1'd0; + end + end + else begin + wea1_01 <= 1'd0; + wea1_02 <= 1'd0; + wea1_03 <= 1'd0; + wea1_04 <= 1'd0; + wea2_01 <= 1'd0; + wea2_02 <= 1'd0; + wea2_03 <= 1'd0; + wea2_04 <= 1'd0; + din1_01 <= 8'd0; + din1_02 <= 8'd0; + din1_03 <= 8'd0; + din1_04 <= 8'd0; + din2_01 <= 8'd0; + din2_02 <= 8'd0; + din2_03 <= 8'd0; + din2_04 <= 8'd0; + addr_wr1_01 <= addr_wr1_01; + addr_wr1_02 <= addr_wr1_02; + addr_wr1_03 <= addr_wr1_03; + addr_wr1_04 <= addr_wr1_04; + addr_wr2_01 <= addr_wr2_01; + addr_wr2_02 <= addr_wr2_02; + addr_wr2_03 <= addr_wr2_03; + addr_wr2_04 <= addr_wr2_04; + end + end + end + + reg flag_out = 1'd0; + reg [10:0] cnt_out_MS = 11'd0; + // 产生输出计数器 + always @(posedge clk) begin + if (rst_MS) begin + flag_out <= 1'd0; + cnt_out_MS <= 11'd0; + end + else begin + if (oe_MS) begin + flag_out <= 1'd1; + cnt_out_MS <= 11'd0; + end + else begin + if (flag_out && cnt_out_MS < 11'd540) begin + cnt_out_MS <= cnt_out_MS + 11'd1; + end + else begin + flag_out <= 1'd0; + cnt_out_MS <= cnt_out_MS; + end + end + end + end + + + // 控制输出缓存地址 + always @(posedge clk) begin + if (rst_MS) begin + addr_rd1_01 <= 9'd511; + addr_rd1_02 <= 9'd511; + addr_rd1_03 <= 9'd511; + addr_rd1_04 <= 9'd511; + addr_rd2_01 <= 9'd511; + addr_rd2_02 <= 9'd511; + addr_rd2_03 <= 9'd511; + addr_rd2_04 <= 9'd511; + end + else begin + if (flag_switch_MS) begin // 输出缓存１中的数据 + if (cnt_out_MS >= 11'd1 && cnt_out_MS <= 11'd512) begin + addr_rd1_01 <= addr_rd1_01 + 9'd1; + addr_rd1_02 <= addr_rd1_02 + 9'd1; + addr_rd1_03 <= addr_rd1_03 + 9'd1; + addr_rd1_04 <= addr_rd1_04 + 9'd1; + end + else begin + addr_rd1_01 <= 9'd511; + addr_rd1_02 <= 9'd511; + addr_rd1_03 <= 9'd511; + addr_rd1_04 <= 9'd511; + end + end + else begin // 输出缓存2中的数据 + if (cnt_out_MS >= 11'd1 && cnt_out_MS <= 11'd512) begin + addr_rd2_01 <= addr_rd2_01 + 9'd1; + addr_rd2_02 <= addr_rd2_02 + 9'd1; + addr_rd2_03 <= addr_rd2_03 + 9'd1; + addr_rd2_04 <= addr_rd2_04 + 9'd1; + end + else begin + addr_rd2_01 <= 9'd511; + addr_rd2_02 <= 9'd511; + addr_rd2_03 <= 9'd511; + addr_rd2_04 <= 9'd511; + end + end + end + end + + // 输出缓存数据到译码器 + always @(posedge clk) begin + if (rst_MS) begin + dout01_MS <= 8'd0; + dout02_MS <= 8'd0; + dout03_MS <= 8'd0; + dout04_MS <= 8'd0; + end + else begin + if (flag_switch_MS) begin + if (cnt_out_MS >= 11'd5 && cnt_out_MS <= 11'd516) begin + dout01_MS <= dout1_01; + dout02_MS <= dout1_02; + dout03_MS <= dout1_03; + dout04_MS <= dout1_04; + end + else begin + dout01_MS <= 8'd0; + dout02_MS <= 8'd0; + dout03_MS <= 8'd0; + dout04_MS <= 8'd0; + end + end + else begin + if (cnt_out_MS >= 11'd5 && cnt_out_MS <= 11'd516) begin + dout01_MS <= dout2_01; + dout02_MS <= dout2_02; + dout03_MS <= dout2_03; + dout04_MS <= dout2_04; + end + else begin + dout01_MS <= 8'd0; + dout02_MS <= 8'd0; + dout03_MS <= 8'd0; + dout04_MS <= 8'd0; + end + end + end + end + // 输出处理完成、同步脉冲和使能标志 + assign deal_end_MS = (cnt_MS == 11'd2047 && nd_MS) ? 1'd1 : 1'd0; + assign syncout_MS = (cnt_out_MS == 11'd5) ? 1'd1 : 1'd0; + assign rdy_MS = (cnt_out_MS >= 11'd6 && cnt_out_MS <= 11'd517) ? 1'd1 : 1'd0; + +endmodule + diff --git a/hdl/Noise_Estimate.v b/hdl/Noise_Estimate.v index 8bcdcb0..e940e9f 100644 --- a/hdl/Noise_Estimate.v +++ b/hdl/Noise_Estimate.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/Normalization_Factor_0_8125.v b/hdl/Normalization_Factor_0_8125.v new file mode 100644 index 0000000..5773a93 --- /dev/null +++ b/hdl/Normalization_Factor_0_8125.v @@ -0,0 +1,60 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 21:27:25 01/18/2018 +// Design Name: +// Module Name: Normalization_Factor_0_8125 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Normalization_Factor_0_8125 #( + parameter WIDTH = 4'd8 +) ( + input clk, + input [WIDTH-1:0] din_NF, //输入为非负数 + output reg [WIDTH-1:0] dout_NF = 8'd0 //输出相对输入延时3个时钟周期 +); + + reg [WIDTH-1:0] din_NF_reg0 = 8'd0, din_NF_reg1 = 8'd0; + reg [WIDTH-1:0] sum_1 = 8'd0, sum_2 = 8'd0; + always @(posedge clk) begin + din_NF_reg0 <= din_NF; + din_NF_reg1 <= din_NF_reg0; + end + always @(posedge clk) begin //对输入数据乘以系数0.8125 + sum_1 <= (din_NF >> 1) + (din_NF >> 2); + sum_2 <= sum_1 + (din_NF_reg0 >> 4); + case ({ + din_NF_reg1[3:0] + }) //matlab中用round函数，verilog中默认是floor函数 + 4'b0000: dout_NF <= sum_2 + 8'd0; + 4'b0001: dout_NF <= sum_2 + 8'd1; + 4'b0010: dout_NF <= sum_2 + 8'd1; + 4'b0011: dout_NF <= sum_2 + 8'd1; + 4'b0100: dout_NF <= sum_2 + 8'd0; + 4'b0101: dout_NF <= sum_2 + 8'd1; + 4'b0110: dout_NF <= sum_2 + 8'd1; //32个数，0~15和16~31的数是一样的，所以用din_NF_reg1&4'b1111， + 4'b0111: dout_NF <= sum_2 + 8'd2; //例如，din_NF_reg1=6'd19,经过din_NF_reg1&4'b1111之后，变成了6'd3 + 4'b1000: dout_NF <= sum_2 + 8'd1; + 4'b1001: dout_NF <= sum_2 + 8'd1; + 4'b1010: dout_NF <= sum_2 + 8'd1; + 4'b1011: dout_NF <= sum_2 + 8'd2; + 4'b1100: dout_NF <= sum_2 + 8'd1; + 4'b1101: dout_NF <= sum_2 + 8'd2; + 4'b1110: dout_NF <= sum_2 + 8'd1; + 4'b1111: dout_NF <= sum_2 + 8'd2; + default: dout_NF <= 8'd0; + endcase + end +endmodule diff --git a/hdl/OUT_PRO.v b/hdl/OUT_PRO.v new file mode 100644 index 0000000..54c182a --- /dev/null +++ b/hdl/OUT_PRO.v @@ -0,0 +1,144 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: OUT_PRO +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module OUT_PRO + #( + parameter OUT_ONLY_INFORMATION = 1'd0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字 + ) + ( + input clk, + input rst_OUT, + input start_OUT, + + input [0:0] DR_dout_01, + input [0:0] DR_dout_02, + input [0:0] DR_dout_03, + input [0:0] DR_dout_04, + + output reg [8:0] DR_addr_rd_01=9'd511, + output reg [8:0] DR_addr_rd_02=9'd511, + output reg [8:0] DR_addr_rd_03=9'd511, + output reg [8:0] DR_addr_rd_04=9'd511, + + output ldpc_syncout_OUT, + output rdy_OUT, + output reg [0:0] ldpc_dout_OUT=1'd0 + ); + + reg [11:0] cnt_OUT=12'd0; + reg flag_OUT=1'd0; + always @ (posedge clk) begin//产生该模块的计数基准 + if(rst_OUT) begin + cnt_OUT <= 12'd0; + flag_OUT <= 1'b0; + end else begin + if(start_OUT) begin + flag_OUT <= 1'b1; + cnt_OUT <= 12'd0; + end else begin + if(flag_OUT) begin + if(cnt_OUT<12'd2080)begin + flag_OUT <= flag_OUT; + cnt_OUT <= cnt_OUT + 12'd1; + end else begin + cnt_OUT <= cnt_OUT; + flag_OUT <= 1'b0; + end + end else begin + cnt_OUT <= cnt_OUT; + end + end + end + end + // 控制DR的读地址 + always @ (posedge clk) begin + if (rst_OUT) begin + DR_addr_rd_01 <= 9'd511; + DR_addr_rd_02 <= 9'd511; + DR_addr_rd_03 <= 9'd511; + DR_addr_rd_04 <= 9'd511; + end else begin + if (OUT_ONLY_INFORMATION) begin // 只输出信息位 + if (cnt_OUT >= 12'd1 && cnt_OUT <= 12'd512) + DR_addr_rd_01 <= DR_addr_rd_01 + 9'd1; + else if (cnt_OUT >= 12'd513 && cnt_OUT <= 12'd1024) + DR_addr_rd_02 <= DR_addr_rd_02 + 9'd1; + else begin + DR_addr_rd_01 <= 9'd511; + DR_addr_rd_02 <= 9'd511; + end + end else begin // 输出整个码字 + if (cnt_OUT >= 12'd1 && cnt_OUT <= 12'd512) + DR_addr_rd_01 <= DR_addr_rd_01 + 9'd1; + else if (cnt_OUT >= 12'd513 && cnt_OUT <= 12'd1024) + DR_addr_rd_02 <= DR_addr_rd_02 + 9'd1; + else if (cnt_OUT >= 12'd1025 && cnt_OUT <= 12'd1536) + DR_addr_rd_03 <= DR_addr_rd_03 + 9'd1; + else if (cnt_OUT >= 12'd1537 && cnt_OUT <= 12'd2048) + DR_addr_rd_04 <= DR_addr_rd_04 + 9'd1; + else begin + DR_addr_rd_01 <= 9'd511; + DR_addr_rd_02 <= 9'd511; + DR_addr_rd_03 <= 9'd511; + DR_addr_rd_04 <= 9'd511; + end + end + end + end + + parameter DELAY_OUT = 4'd6; + // 控制DR的输出数据到译码器的输出 + always @ (posedge clk) begin + if (rst_OUT) begin + ldpc_dout_OUT <= 1'd0; + end else begin + if (OUT_ONLY_INFORMATION) begin // 只输出信息位 + if (cnt_OUT >= 12'd1 + DELAY_OUT && cnt_OUT <= 12'd512 + DELAY_OUT) + ldpc_dout_OUT <= DR_dout_01; + else if (cnt_OUT >= 12'd513 + DELAY_OUT && cnt_OUT <= 12'd1024 + DELAY_OUT) + ldpc_dout_OUT <= DR_dout_02; + else + ldpc_dout_OUT <= 1'd0; + end else begin // 输出整个码字 + if (cnt_OUT >= 12'd1 + DELAY_OUT && cnt_OUT <= 12'd512 + DELAY_OUT) + ldpc_dout_OUT <= DR_dout_01; + else if (cnt_OUT >= 12'd513 + DELAY_OUT && cnt_OUT <= 12'd1024 + DELAY_OUT) + ldpc_dout_OUT <= DR_dout_02; + else if (cnt_OUT >= 12'd1025 + DELAY_OUT && cnt_OUT <= 12'd1536 + DELAY_OUT) + ldpc_dout_OUT <= DR_dout_03; + else if (cnt_OUT >= 12'd1537 + DELAY_OUT && cnt_OUT <= 12'd2048 + DELAY_OUT) + ldpc_dout_OUT <= DR_dout_04; + else + ldpc_dout_OUT <= 1'd0; + end + end + end + + // 产生状态指示标志 + assign ldpc_syncout_OUT = (cnt_OUT == 12'd1 + DELAY_OUT) ? 1'd1 : 1'd0; + + assign rdy_OUT = (OUT_ONLY_INFORMATION == 1'd0) ? + ((cnt_OUT >= 12'd1 + DELAY_OUT + 12'd1 && cnt_OUT <= 12'd2048 + DELAY_OUT + 12'd1) ? 1'd1 : 1'd0) : + ((cnt_OUT >= 12'd1 + DELAY_OUT + 12'd1 && cnt_OUT <= 12'd1024 + DELAY_OUT + 12'd1) ? 1'd1 : 1'd0); + +endmodule + diff --git a/hdl/Out_Process_R12.v b/hdl/Out_Process_R12.v index 6eb2136..7ff68be 100644 --- a/hdl/Out_Process_R12.v +++ b/hdl/Out_Process_R12.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/PAPR.v b/hdl/PAPR.v index e1c0827..103767b 100644 --- a/hdl/PAPR.v +++ b/hdl/PAPR.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns // +------------------------------+ // | | diff --git a/hdl/RecvTop.v b/hdl/RecvTop.v index d9f4ad7..5c6c80e 100644 --- a/hdl/RecvTop.v +++ b/hdl/RecvTop.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: @@ -19,104 +19,103 @@ // ////////////////////////////////////////////////////////////////////////////////// module RecvTop ( - input clk, - input clk2, - input clk_60M_mac, - input clk_4x, - input rst, - input rst2, - - input [11:0] dini, - input [11:0] dinq, - - output [3:0] ad9361_ctrl_in, - - output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 - output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 - - input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60 - - //debug - //trigger - output rst_TimeSync, - output rst_freq, - output DAGC_rdy, - output framesync, //帧同步峰 - output framesync_delay, //帧同步峰，与频率补偿输出对应 - output framesync_tsync, //帧同步标志，与TSync输出对应 - output IntpARdy, //TSync输出nd - output nd_SC_FDE_dout, //SC_FDE输出nd - output framerdy, //一帧译码结果存储完毕标志 - output reg flag_bercount = 1'd0, - output reg flag_badframe = 1'd0, - output reg flag_ber = 1'd0, - //各模块输出，星座图 - output [11:0] dc_removal_dout_i, //MGC_adaptation、去直流输出 - output [11:0] dc_removal_dout_q, - output [ 9:0] matchfilterout_i, //MF输出 - output [ 9:0] matchfilterout_q, - output [ 9:0] DAGC_out_i, //DAGC输出 - output [ 9:0] DAGC_out_q, - output [ 9:0] freqdataout_i, //频率补偿输出 - output [ 9:0] freqdataout_q, - output [ 9:0] IntpOuti, //TSync输出 - output [ 9:0] IntpOutq, - output [ 9:0] SC_FDE_douti, //SC_FDE输出 - output [ 9:0] SC_FDE_doutq, - //MGC_adaptation - output [24:0] mean_temp, - output [12:0] acc_mean, - output [ 4:0] state_mgc, - output mgc1_rdy, - output flag_state_mgc, - output [ 2:0] state_rst, - output flag_overflow, - output flag_small, - //DC - output [11:0] dc_value_i, - output [11:0] dc_value_q, - output flag_dc, - //DAGC - output flag_agch, - output flag_agcl, - output flag_agc_power, - output [12:0] agc_ref, - output [12:0] agc_check, - //power test - output flag_powerabsh, - output flag_powerabsl, - output flag_abs_power, - output [10:0] abs_ref, - output [10:0] abs_check, - //TSync - output [ 3:0] flag_clk_4bit, //位同步选取通道结果 - //SC_FDE,溢出标志 - output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14 - output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18 - output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 - output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 - output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 - output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 - output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28 - output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11 - output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 - output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 - output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16 - output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16 - output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 - output flagoverflow_FDE_dataout_29to10q, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 - output reg flagoverflow = 1'd0, //总溢出标志 - output Pilot_rdy_hide1_d1, - + input clk, + input clk_2x, // clk_2x + input clk_4x, + input rst, + input rst2, // TODO： delete the signal + // phy wave + input [11:0] dini, + input [11:0] dinq, + // mgc control + output [ 3:0] ad9361_ctrl_in, + //vio + input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路 + input EQUenable_vio, //为1时启用均衡 + input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29 + input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60 + // stop signal + output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 + output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 + // mac frame header output [63:0] recvNetData, - output recvNetDataNd, - input debug_loss + output recvNetDataNd ); - reg [7:0] cnt_mgc_delay; - wire mgc_start; - wire flag_mgc_done; // level flag - wire flag_mgc_done_4x; // level flag + wire rst_TimeSync; + wire rst_freq; + wire DAGC_rdy; + wire framesync; //帧同步峰 + wire framesync_delay; //帧同步峰，与频率补偿输出对应 + wire framesync_tsync; //帧同步标志，与TSync输出对应 + wire IntpARdy; //TSync输出nd + wire nd_SC_FDE_dout; //SC_FDE输出nd + wire framerdy; //一帧译码结果存储完毕标志 + reg flag_bercount = 1'd0; + reg flag_badframe = 1'd0; + reg flag_ber = 1'd0; + wire [11:0] dc_removal_dout_i; //MGC_adaptation、去直流输出 + wire [11:0] dc_removal_dout_q; + wire [ 9:0] matchfilterout_i; //MF输出 + wire [ 9:0] matchfilterout_q; + wire [ 9:0] DAGC_out_i; //DAGC输出 + wire [ 9:0] DAGC_out_q; + wire [ 9:0] freqdataout_i; //频率补偿输出 + wire [ 9:0] freqdataout_q; + wire [ 9:0] IntpOuti; //TSync输出 + wire [ 9:0] IntpOutq; + wire [ 9:0] SC_FDE_douti; //SC_FDE输出 + wire [ 9:0] SC_FDE_doutq; + wire [24:0] mean_temp; + wire [12:0] acc_mean; + wire [ 4:0] state_mgc; + wire mgc1_rdy; + wire flag_state_mgc; + wire [ 2:0] state_rst; + wire flag_overflow; + wire flag_small; + wire [11:0] dc_value_i; + wire [11:0] dc_value_q; + wire flag_dc; + wire flag_agch; + wire flag_agcl; + wire flag_agc_power; + wire [12:0] agc_ref; + wire [12:0] agc_check; + wire flag_powerabsh; + wire flag_powerabsl; + wire flag_abs_power; + wire [10:0] abs_ref; + wire [10:0] abs_check; + wire [ 3:0] flag_clk_4bit; //位同步选取通道结果 + wire flagoverflow_fftpilot_26to14; //第1个fft结果截位，即导频fft结果的截位，26截到14 + wire flagoverflow_ChnZF_26to18; //第2个fft结果截位，即ZF信道估计结果的截位，26截到18 + wire flagoverflow_comdiv_34to20i; //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 + wire flagoverflow_comdiv_34to20q; //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 + wire flagoverflow_ifftzero_29to17i; //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 + wire flagoverflow_ifftzero_29to17q; //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 + wire flagoverflow_MMSEdiv_divisor_31to28; //第2个除法器，即MMSE除法的分母截位，31截到28 + wire flagoverflow_divmmse_34to11; //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11 + wire flagoverflow_ifftindata_28to20i; //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 + wire flagoverflow_ifftindata_28to20q; //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 + wire flagoverflow_fftdata_26to16i; //数据段ow的fft输出截位，26截到16 + wire flagoverflow_fftdata_26to16q; //数据段ow的fft输出截位，26截到16 + wire flagoverflow_FDE_dataout_29to10i; //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 + wire flagoverflow_FDE_dataout_29to10q; //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 + reg flagoverflow = 1'd0; //总溢出标志 + wire Pilot_rdy_hide1_d1; + + + + + + + reg [ 7:0] cnt_mgc_delay; + wire mgc_start; + wire flag_mgc_done; // level flag + wire flag_mgc_done_4x; // level flag + + // startup delay always @(posedge clk) begin if (rst) begin cnt_mgc_delay <= 0; @@ -131,6 +130,7 @@ module RecvTop ( assign mgc_start = (cnt_mgc_delay == 8'hFE); + // * MGC module ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ( .clk (clk), .rst (rst), @@ -141,6 +141,8 @@ module RecvTop ( .flag_mgc_done (flag_mgc_done) ); + + reg MF_rdy; // flag_mgc_done_d1 wire MF_rst; // flag_mgc_done_pulse_d2 always @(posedge clk) begin @@ -197,24 +199,25 @@ module RecvTop ( end - + wire mf_fir_s_tready_i; + wire mf_fir_s_tready_q; // Match filter fir_match_interp4 u_fir_match_filter_interp4_i ( - .aclk (clk), // input wire aclk - .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid - .s_axis_data_tready(), // output wire s_axis_data_tready - .s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata - .m_axis_data_tvalid(), // output wire m_axis_data_tvalid - .m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata + .aclk (clk), // input wire aclk + .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid + .s_axis_data_tready(mf_fir_s_tready_i), // output wire s_axis_data_tready + .s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid(), // output wire m_axis_data_tvalid + .m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata ); fir_match_interp4 u_fir_match_filter_interp4_q ( - .aclk (clk), // input wire aclk - .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid - .s_axis_data_tready(), // output wire s_axis_data_tready - .s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata - .m_axis_data_tvalid(), // output wire m_axis_data_tvalid - .m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata + .aclk (clk), // input wire aclk + .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid + .s_axis_data_tready(mf_fir_s_tready_q), // output wire s_axis_data_tready + .s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid(), // output wire m_axis_data_tvalid + .m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata ); // CDC into clk_4x @@ -252,24 +255,31 @@ module RecvTop ( .m_axis_data_tdata (dmf_tdata_interp4_q) ); + localparam CNT_CHU_SEQ_SYNC_MAX = 8;//! should not less than 3 due to the minimum rst of aresetn + wire [21:0] mag; wire mag_valid; wire frame_sync_4x; wire frame_sync_pulse; // in domain clk reg flag_frame_sync; // active high level - // calc the magnitude + wire rst_frame_sync; // derive from frame sync pulse + reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos + + assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX)); + + //* calc the magnitude MagnitudeEstimator #( .VEC_WIDTH(21) ) u_MagnitudeEstimator ( .clk (clk_4x), .rst (rst), .vec_valid(dmf_tvalid_interp4_i), - .I (dmf_tdata_interp4_i), - .Q (dmf_tdata_interp4_q), + .I (dmf_tdata_interp4_i[20:0]), + .Q (dmf_tdata_interp4_q[20:0]), .mag (mag), .mag_valid(mag_valid) ); - // frame sync threashold judgement + //* frame sync threashold judgement PAPR #( .MAG_WIDTH (22), .WINDOW_DEPTH(1023) @@ -279,41 +289,47 @@ module RecvTop ( .vec_mag (mag), .mag_valid (mag_valid), .frame_sync (frame_sync_4x), - .frame_sync_pulse() + .frame_sync_pulse() // under clk_4x ); + always @(posedge clk) begin + if (frame_sync_pulse) begin + cnt_chu_seq_sync <= 1; + end + // avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks) + else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX) begin + cnt_chu_seq_sync <= cnt_chu_seq_sync + 1; + end + else begin + cnt_chu_seq_sync <= 0; + end + end + always @(posedge clk) begin if (rst) begin flag_frame_sync <= 0; end - else if (frame_sync_pulse) begin + else if (cnt_chu_seq_sync == CNT_CHU_SEQ_SYNC_MAX) begin flag_frame_sync <= 1; end else begin flag_frame_sync <= flag_frame_sync; end end - // wire [9:0] DAGC_out_i; - // wire [9:0] DAGC_out_q; - wire [9:0] FrameSync_douti; - wire [9:0] FrameSync_doutq; - wire dagc_rdy; - wire mgc_rdy; - wire rst_dagc; - //帧同步模块 - - assign FrameSync_dini = DAGC_out_i; - assign FrameSync_dinq = DAGC_out_q; - // wire framesync; + wire [ 9:0] FrameSync_douti; + wire [ 9:0] FrameSync_doutq; + wire dagc_rdy; + wire mgc_rdy; + wire rst_dagc; // * lost the connection with other nodes - reg [20:0] cnt_lost; - reg framelost; + reg [20:0] cnt_lost; + reg framelost; always @(posedge clk) begin - if (Pilot_rdy_hide1_d1) begin + if (rst_frame_sync) begin cnt_lost <= 21'd0; framelost <= 1'b0; end @@ -353,13 +369,7 @@ module RecvTop ( ); - //载波频偏补偿 - // wire [9:0] freqdataout_i; - // wire [9:0] freqdataout_q; - // wire framesync_delay; - wire data_save; //debug用，暂不需使用 - // wire rst_freq; - + // CFO estimation freqestm freqestm ( .clk (clk), .rst (mgc_start), @@ -376,18 +386,17 @@ module RecvTop ( //位同步 wire [1:0] cnt_tsync; - // wire framesync_tsync; //帧同步标志 TimeSync_top TimeSync_top ( .clk (clk), - .rst (Pilot_rdy_hide1_d1), + .rst (rst_frame_sync), .dini (freqdataout_i), .dinq (freqdataout_q), .rdy (IntpARdy), .douti (IntpOuti), .doutq (IntpOutq), .vio_tsync_inter16(vio_tsync_inter16), - .framesync (framesync_delay), //帧同步标志 - .framesync_tsync (framesync_tsync), //帧同步标志 + .framesync (framesync_delay), //帧同步标志 + .framesync_tsync (framesync_tsync), //帧同步标志 //debug .cnt_tsync (cnt_tsync), .flag_clk_4bit (flag_clk_4bit) @@ -398,15 +407,13 @@ module RecvTop ( // SC-FDE - SC_FDE_TOP SC_FDE_TOP_djy ( - .clk(clk), - .rst(Pilot_rdy_hide1_d1), - - .EQUenable_vio(EQUenable_vio), //为1时启用均衡 - .Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29 - - .flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐 + .clk (clk), + .rst (rst_frame_sync), + // param + .EQUenable_vio (EQUenable_vio), //为1时启用均衡 + .Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29 + .flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐 .nd (IntpARdy), .dini (IntpOuti), .dinq (IntpOutq), @@ -414,20 +421,20 @@ module RecvTop ( .SC_FDE_douti (SC_FDE_douti), .SC_FDE_doutq (SC_FDE_doutq), // debug,溢出标志 - .flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14), - .flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18), - .flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i), - .flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q), - .flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i), - .flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q), - .flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28), - .flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11), - .flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i), - .flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q), - .flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i), - .flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q), - .flagoverflow_FDE_dataout_29to10i (flagoverflow_FDE_dataout_29to10i), - .flagoverflow_FDE_dataout_29to10q (flagoverflow_FDE_dataout_29to10q) + .flagoverflow_fftpilot_26to14 (), + .flagoverflow_ChnZF_26to18 (), + .flagoverflow_comdiv_34to20i (), + .flagoverflow_comdiv_34to20q (), + .flagoverflow_ifftzero_29to17i (), + .flagoverflow_ifftzero_29to17q (), + .flagoverflow_MMSEdiv_divisor_31to28(), + .flagoverflow_divmmse_34to11 (), + .flagoverflow_ifftindata_28to20i (), + .flagoverflow_ifftindata_28to20q (), + .flagoverflow_fftdata_26to16i (), + .flagoverflow_fftdata_26to16q (), + .flagoverflow_FDE_dataout_29to10i (), + .flagoverflow_FDE_dataout_29to10q () ); @@ -436,7 +443,7 @@ module RecvTop ( wire [9:0] phase_adjust_doutq; phase_adjust phase_adjust ( .clk (clk), - .rst (Pilot_rdy_hide1_d1), + .rst (rst_frame_sync), .din_i (SC_FDE_douti), .din_q (SC_FDE_doutq), .nd (nd_SC_FDE_dout), @@ -452,8 +459,8 @@ module RecvTop ( IQmerge IQmerge ( .clk (clk), - .clk2 (clk2), - .rst (rst2 || Pilot_rdy_hide1_d1), + .clk2 (clk_2x), + .rst (rst2 || rst_frame_sync), .nd (phase_adjust_rdy), .framesync (framesync_tsync), .dini (phase_adjust_douti), @@ -469,9 +476,10 @@ module RecvTop ( wire [8:0] good_frames; wire [8:0] bad_frames; wire [8:0] total_frames; + CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode ( - .clk (clk2), - .Rst (rst2 || Pilot_rdy_hide1_d1), + .clk (clk_2x), + .Rst (rst2 || rst_frame_sync), .FrameSync (ldpcsyncin), .Nd (IQmergerdy), .Din (IQmergedout), @@ -487,89 +495,6 @@ module RecvTop ( - wire flag_notbyte; //为1时说明得到的有效数据不以字节为单位 - wire [ 1:0] state_ram; - wire berstart_1d; - wire bercompare; - wire [16:0] bercount; - wire [16:0] bercount_max; - wire [16:0] ROMaddra_d2; - wire RAMdout_d1; - wire validnd_new_new; - wire [63:0] stop_temp_new; - wire flag_stop_0; //给shx，拉高1个clk表示当前时帧有效数据接收完毕 - wire [16:0] addr_stop_0; - wire [ 2:0] cnt_8; - wire state_8; - wire rdy_scramble; - wire dout_scramble; - wire [16:0] RAMaddra; //比较误码率 - wire [16:0] ROMaddra; //比较误码率 - wire nd_ber; - - FrameMerge FrameMerge ( - .clk (clk2), - .rst (Pilot_rdy_hide1_d1), - .rst2(rst2), - .sync(LDPC_SyncOut), - .nd (LDPC_Rdy), - .din (LDPC_Dout), - - .vio_stopbit(vio_stopbit), - - .frameIDnd(Pilot_rdy_hide1_d1), - .clk2 (clk_60M_mac), - .framerdy (framerdy), - - .recv_addr_new_0 (recv_addr_new_0), - .recv_addr_new_1 (recv_addr_new_1), - .recv_addr_new_2 (recv_addr_new_2), - .recv_addr_new_3 (recv_addr_new_3), - .recv_data_new_0 (recv_data_new_0), - .recv_data_new_1 (recv_data_new_1), - .recv_data_new_2 (recv_data_new_2), - .recv_data_new_3 (recv_data_new_3), - .RAMaddra_write_0(RAMaddra_write_0), - .RAMaddra_write_1(RAMaddra_write_1), - .RAMaddra_write_2(RAMaddra_write_2), - .RAMaddra_write_3(RAMaddra_write_3), - .RAMaddra_new_0 (RAMaddra_new_0), - .RAMaddra_new_1 (RAMaddra_new_1), - .RAMaddra_new_2 (RAMaddra_new_2), - .RAMaddra_new_3 (RAMaddra_new_3), - - .flag_notbyte(flag_notbyte), - .state_ram (state_ram), - .flag_stop (flag_stop), //给shx，拉高8个clk表示当前时帧有效数据接收完毕 - .addr_stop (addr_stop), //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 - //debug - .berstart_1d (berstart_1d), - .bercompare (bercompare), - .bercount (bercount), - .bercount_max(bercount_max), - .ROMaddra_d2 (ROMaddra_d2), - .RAMdout_d1 (RAMdout_d1), - - .validnd_new_new(validnd_new_new), - - .stop_temp_new(stop_temp_new), - - .flag_stop_0(flag_stop_0), - .addr_stop_0(addr_stop_0), - .cnt_8 (cnt_8), - .state_8 (state_8), - - .rdy_scramble (rdy_scramble), - .dout_scramble(dout_scramble), - - .RAMaddra (RAMaddra), - .ROMaddra (ROMaddra), - .nd_ber (nd_ber), - .recvNetData (recvNetData), - .recvNetDataNd(recvNetDataNd) - ); - - // ***** cdc ***** xpm_cdc_single #( .DEST_SYNC_FF (2), // DECIMAL; range: 2-10 @@ -586,8 +511,8 @@ module RecvTop ( xpm_cdc_pulse #( .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 - .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values - .REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output + .INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output .RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset .SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages ) xpm_cdc_frame_sync_pulse_inst ( diff --git a/hdl/SCFDE_recv_FrameSync.v b/hdl/SCFDE_recv_FrameSync.v index d2cc648..723679c 100644 --- a/hdl/SCFDE_recv_FrameSync.v +++ b/hdl/SCFDE_recv_FrameSync.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/SC_FDE_TOP.v b/hdl/SC_FDE_TOP.v index dd453e9..09470e6 100644 --- a/hdl/SC_FDE_TOP.v +++ b/hdl/SC_FDE_TOP.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: @@ -20,665 +20,540 @@ ////////////////////////////////////////////////////////////////////////////////// -module SC_FDE_TOP( - input clk, - input rst, - - input EQUenable_vio, //为1时启用均衡 - - input [7:0] Zerozone_vio, //零域估计，默认值为8'd29 - - input flag_ow_left, //在一帧内，与第一个数据段的pilot的ow第一个nd对齐 - input nd, - input [9:0] dini, - input [9:0] dinq, - - output nd_SC_FDE_dout, - output [9:0] SC_FDE_douti, - output [9:0] SC_FDE_doutq, - - // debug,溢出标志 - output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14 - output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18 - output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 - output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 - output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 - output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 - output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28 - output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11 - - output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 - output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 - output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16 - output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16 - output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 - output flagoverflow_FDE_dataout_29to10q //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 +module SC_FDE_TOP ( + input clk, + input rst, + + input EQUenable_vio, //为1时启用均衡 + + input [7:0] Zerozone_vio, //零域估计，默认值为8'd29 + + input flag_ow_left, //在一帧内，与第一个数据段的pilot的ow第一个nd对齐 + input nd, + input [9:0] dini, + input [9:0] dinq, + + output nd_SC_FDE_dout, + output [9:0] SC_FDE_douti, + output [9:0] SC_FDE_doutq, + + // debug,溢出标志 + output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14 + output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18 + output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 + output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 + output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 + output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 + output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28 + output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11 + + output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 + output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 + output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16 + output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16 + output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 + output flagoverflow_FDE_dataout_29to10q //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 +); + + + + //-----------------------------------------导频和数据ow的缓存--------------------------------------------// + //----------------------还负责计算正负导频头的和与差。流水得到结果用于信道估计----------------------------// + //数据的fifo，4个 + wire [9:0] din_data1i; + wire [9:0] din_data1q; + wire wr_en_data1; + wire [9:0] din_data2i; + wire [9:0] din_data2q; + wire wr_en_data2; + wire flag_dataow; //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取 + wire flag_ChnEstFFT_done; //信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出) + //正负导频段的加减结果 + wire nd_pilot2; + wire [9:0] pilot_datai; + wire [9:0] pilot_dataq; + wire [9:0] pilot_noisei; + wire [9:0] pilot_noiseq; + + data_ow data_ow_djy ( + .clk (clk), + .rst (rst), + .flag_ow_left(flag_ow_left), + .nd (nd), + .dini (dini), + .dinq (dinq), + + .din_data1i (din_data1i), + .din_data1q (din_data1q), + .wr_en_data1(wr_en_data1), + .din_data2i (din_data2i), + .din_data2q (din_data2q), + .wr_en_data2(wr_en_data2), + .flag_dataow(flag_dataow), //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取 + + .nd_pilot2 (nd_pilot2), + .pilot_datai (pilot_datai), + .pilot_dataq (pilot_dataq), + .pilot_noisei(pilot_noisei), + .pilot_noiseq(pilot_noiseq) ); - - - - //-----------------------------------------导频和数据ow的缓存--------------------------------------------// - //----------------------还负责计算正负导频头的和与差。流水得到结果用于信道估计----------------------------// - //数据的fifo，4个 - wire [9:0] din_data1i; - wire [9:0] din_data1q; - wire wr_en_data1; - wire [9:0] din_data2i; - wire [9:0] din_data2q; - wire wr_en_data2; - wire flag_dataow; //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取 - wire flag_ChnEstFFT_done; //信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出) - //正负导频段的加减结果 - wire nd_pilot2; - wire [9:0] pilot_datai; - wire [9:0] pilot_dataq; - wire [9:0] pilot_noisei; - wire [9:0] pilot_noiseq; - - data_ow data_ow_djy ( - .clk (clk), - .rst (rst), - .flag_ow_left (flag_ow_left), - .nd (nd), - .dini (dini), - .dinq (dinq), - - .din_data1i (din_data1i), - .din_data1q (din_data1q), - .wr_en_data1 (wr_en_data1), - .din_data2i (din_data2i), - .din_data2q (din_data2q), - .wr_en_data2 (wr_en_data2), - .flag_dataow (flag_dataow), //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取 - - .nd_pilot2 (nd_pilot2), - .pilot_datai (pilot_datai), - .pilot_dataq (pilot_dataq), - .pilot_noisei (pilot_noisei), - .pilot_noiseq (pilot_noiseq) - ); - - //-------------------------------------------data数据ow的fifo，4个--------------------------------------------// - wire rd_en_data1; - wire [9:0] dout_data1i; - wire full_data1i; - wire empty_data1i; - fifo_ow256 fifo_data_ow1i ( - .rst (rst), // input wire rst - .wr_clk (clk), // input wire wr_clk - .rd_clk (clk), // input wire rd_clk - .din (din_data1i), // input wire [9 : 0] din - .wr_en (wr_en_data1), // input wire wr_en - .rd_en (rd_en_data1), // input wire rd_en - .dout (dout_data1i), // output wire [9 : 0] dout - .full (full_data1i), // output wire full - .empty (empty_data1i) // output wire empty - ); - - wire [9:0] dout_data1q; - wire full_data1q; - wire empty_data1q; - fifo_ow256 fifo_data_ow1q ( - .rst (rst), // input wire rst - .wr_clk (clk), // input wire wr_clk - .rd_clk (clk), // input wire rd_clk - .din (din_data1q), // input wire [9 : 0] din - .wr_en (wr_en_data1), // input wire wr_en - .rd_en (rd_en_data1), // input wire rd_en - .dout (dout_data1q), // output wire [9 : 0] dout - .full (full_data1q), // output wire full - .empty (empty_data1q) // output wire empty - ); - - wire rd_en_data2; - wire [9:0] dout_data2i; - wire full_data2i; - wire empty_data2i; - fifo_ow256 fifo_data_ow2i ( - .rst (rst), // input wire rst - .wr_clk (clk), // input wire wr_clk - .rd_clk (clk), // input wire rd_clk - .din (din_data2i), // input wire [9 : 0] din - .wr_en (wr_en_data2), // input wire wr_en - .rd_en (rd_en_data2), // input wire rd_en - .dout (dout_data2i), // output wire [9 : 0] dout - .full (full_data2i), // output wire full - .empty (empty_data2i) // output wire empty - ); - - wire [9:0] dout_data2q; - wire full_data2q; - wire empty_data2q; - fifo_ow256 fifo_data_ow2q ( - .rst (rst), // input wire rst - .wr_clk (clk), // input wire wr_clk - .rd_clk (clk), // input wire rd_clk - .din (din_data2q), // input wire [9 : 0] din - .wr_en (wr_en_data2), // input wire wr_en - .rd_en (rd_en_data2), // input wire rd_en - .dout (dout_data2q), // output wire [9 : 0] dout - .full (full_data2q), // output wire full - .empty (empty_data2q) // output wire empty - ); - - - - - - - - - //-----------------------------------------------------噪声估计--------------------------------------------------// - //--------------------------------------------噪声估计结果放大了256*49倍-----------------------------------------// - //噪声估计结果 - wire nd_EstNoise; - wire [27:0] EstNoise_i; - wire [27:0] EstNoise_q; - - Noise_Estimate Noise_Estimate_djy ( - .clk (clk), - .rst (rst), - .nd_pilot2 (nd_pilot2), - .pilot_noisei (pilot_noisei), - .pilot_noiseq (pilot_noiseq), - - .nd_EstNoise (nd_EstNoise), - .EstNoise_i (EstNoise_i), - .EstNoise_q (EstNoise_q) - ); - - - - - - - - - //------------------------------------------fft核，及其输入输出控制器------------------------------------------// - reg fft_config_tvalid = 1'd0; - wire fft_config_tready; - reg [16:0] fft_in_i = 17'd0; - reg [16:0] fft_in_q = 17'd0; - reg fft_in_nd = 1'd0; - wire fft_in_tready; - wire[63:0] fft_out_tdata; - wire[25:0] fft_out_i; - wire[25:0] fft_out_q; - wire fft_out_nd; - wire[7:0] fft_index; - - assign fft_out_i = fft_out_tdata[25:0]; - assign fft_out_q = fft_out_tdata[57:32]; - - wire m_axis_data_tlast; - wire event_frame_started; - wire event_tlast_unexpected; - wire event_tlast_missing; - wire event_status_channel_halt; - wire event_data_in_channel_halt; - wire event_data_out_channel_halt; - - fft_256 fft_256 ( - .aclk (clk), // input wire aclk - .aresetn (~rst), // input wire aresetn低有效复位，每次帧结束后复位8clk，满足核要求 - .s_axis_config_tdata (8'd1), // input wire [7 : 0] s_axis_config_tdata - .s_axis_config_tvalid (fft_config_tvalid), // input wire s_axis_config_tvalid - .s_axis_config_tready (fft_config_tready), // output wire s_axis_config_tready - - .s_axis_data_tdata ({7'd0,fft_in_q,7'd0,fft_in_i}), // input wire [47 : 0] s_axis_data_tdata - .s_axis_data_tvalid (fft_in_nd), // input wire s_axis_data_tvalid - .s_axis_data_tready (fft_in_tready), // output wire s_axis_data_tready - .s_axis_data_tlast (1'd0), // input wire s_axis_data_tlastn不用给这个信号 - - .m_axis_data_tdata (fft_out_tdata), // output wire [63 : 0] m_axis_data_tdata - .m_axis_data_tuser (fft_index), // output wire [7 : 0] m_axis_data_tuser - .m_axis_data_tvalid (fft_out_nd), // output wire m_axis_data_tvalid - .m_axis_data_tready (1'd1), // input wire m_axis_data_tready - .m_axis_data_tlast (m_axis_data_tlast), // output wire m_axis_data_tlast - - .event_frame_started (event_frame_started), // output wire event_frame_started - .event_tlast_unexpected (event_tlast_unexpected), // output wire event_tlast_unexpected - .event_tlast_missing (event_tlast_missing), // output wire event_tlast_missing - .event_status_channel_halt (event_status_channel_halt), // output wire event_status_channel_halt - .event_data_in_channel_halt (event_data_in_channel_halt), // output wire event_data_in_channel_halt - .event_data_out_channel_halt (event_data_out_channel_halt) // output wire event_data_out_channel_halt - ); - - - reg [1:0] state_fft = 2'd0; - wire nd_pilotfft; - wire [16:0] fft_in_i_pilot; - wire [16:0] fft_in_q_pilot; - wire nd_datafft; - wire [16:0] fft_in_i_data; - wire [16:0] fft_in_q_data; - - always @(posedge clk)begin - if(rst)begin - fft_config_tvalid <= 1'd0; - fft_in_i <= 17'd0; - fft_in_q <= 17'd0; - fft_in_nd <= 1'd0; - state_fft <= 2'd0; - end - else begin - case(state_fft) - //帧间复位结束后，先等待fft_config_tvalid拉高，说明fft核允许配置，先写入一次fft配置 - 2'd0:begin - if(fft_config_tready) begin - fft_config_tvalid <= 1'd1; - fft_in_nd <= 1'd0; - state_fft <= state_fft + 2'd1; - end - else begin - fft_config_tvalid <= 1'd0; - fft_in_nd <= 1'd0; - state_fft <= state_fft; - end - end - //每帧一开始fft核输入交给信道估计模块，直到flag_ChnEstFFT_done到来，说明信道估计两次fft输入完毕(Chn_Estimate给出) - 2'd1:begin - fft_config_tvalid <= 1'd0; - if(flag_ChnEstFFT_done) begin - fft_in_i <= fft_in_i_data; - fft_in_q <= fft_in_q_data; - fft_in_nd <= nd_datafft; - state_fft <= state_fft + 2'd1; - end - else begin - fft_in_i <= fft_in_i_pilot; - fft_in_q <= fft_in_q_pilot; - fft_in_nd <= nd_pilotfft; - state_fft <= state_fft; - end - end - //nd_pilot2拉高，说明下一个征服导频头处理完毕，fft输入控制权交还信道估计模块 - 2'd2:begin - fft_config_tvalid <= 1'd0; - if(nd_pilot2) begin - fft_in_i <= fft_in_i_pilot; - fft_in_q <= fft_in_q_pilot; - fft_in_nd <= nd_pilotfft; - state_fft <= 2'd1; - end - else begin - fft_in_i <= fft_in_i_data; - fft_in_q <= fft_in_q_data; - fft_in_nd <= nd_datafft; - state_fft <= state_fft; - end - end - default:state_fft <= 2'd0; - endcase - end - end - - - - - - - - //------------------------------------------ifft核，及其输入输出控制器------------------------------------------// - reg ifft_config_tvalid = 1'd0; - wire ifft_config_tready; - reg [19:0] ifft_in_i = 20'd0; - reg [19:0] ifft_in_q = 20'd0; - reg ifft_in_nd = 1'd0; - wire ifft_in_tready; - wire[63:0] ifft_out_tdata; - wire[28:0] ifft_out_i; - wire[28:0] ifft_out_q; - wire ifft_out_nd; - wire[7:0] ifft_index; - - assign ifft_out_i = ifft_out_tdata[28:0]; - assign ifft_out_q = ifft_out_tdata[60:32]; - - wire m_axis_data_tlast_ifft; - wire event_frame_started_ifft; - wire event_tlast_unexpected_ifft; - wire event_tlast_missing_ifft; - wire event_status_channel_halt_ifft; - wire event_data_in_channel_halt_ifft; - wire event_data_out_channel_halt_ifft; - - ifft_256 ifft_256 ( - .aclk (clk), // input wire aclk - .aresetn (~rst), // input wire aresetn - - .s_axis_config_tdata (8'd0), // input wire [7 : 0] s_axis_config_tdata - .s_axis_config_tvalid (ifft_config_tvalid), // input wire s_axis_config_tvalid - .s_axis_config_tready (ifft_config_tready), // output wire s_axis_config_tready - - .s_axis_data_tdata ({4'd0,ifft_in_q,4'd0,ifft_in_i}), // input wire [47 : 0] s_axis_data_tdata - .s_axis_data_tvalid (ifft_in_nd), // input wire s_axis_data_tvalid - .s_axis_data_tready (ifft_in_tready), // output wire s_axis_data_tready - .s_axis_data_tlast (1'd0), // input wire s_axis_data_tlast - - .m_axis_data_tdata (ifft_out_tdata), // output wire [63 : 0] m_axis_data_tdata - .m_axis_data_tuser (ifft_index), // output wire [7 : 0] m_axis_data_tuser - .m_axis_data_tvalid (ifft_out_nd), // output wire m_axis_data_tvalid - .m_axis_data_tready (1'd1), // input wire m_axis_data_tready - .m_axis_data_tlast (m_axis_data_tlast_ifft), // output wire m_axis_data_tlast - - .event_frame_started (event_frame_started_ifft), // output wire event_frame_started - .event_tlast_unexpected (event_tlast_unexpected_ifft), // output wire event_tlast_unexpected - .event_tlast_missing (event_tlast_missing_ifft), // output wire event_tlast_missing - .event_status_channel_halt (event_status_channel_halt_ifft), // output wire event_status_channel_halt - .event_data_in_channel_halt (event_data_in_channel_halt_ifft), // output wire event_data_in_channel_halt - .event_data_out_channel_halt (event_data_out_channel_halt_ifft) // output wire event_data_out_channel_halt - ); - - - reg [1:0] state_ifft = 2'd0; - wire nd_pilotifft; - wire [19:0] ifft_in_i_pilot; - wire [19:0] ifft_in_q_pilot; - wire nd_dataifft; - wire [19:0] ifft_in_i_data; - wire [19:0] ifft_in_q_data; - - always @(posedge clk)begin - if(rst)begin - ifft_config_tvalid <= 1'd0; - ifft_in_i <= 20'd0; - ifft_in_q <= 20'd0; - ifft_in_nd <= 1'd0; - state_ifft <= 2'd0; - end - else begin - case(state_ifft) - //帧间复位结束后，先等待ifft_config_tvalid拉高，说明ifft核允许配置，先写入一次ifft配置 - 2'd0:begin - if(ifft_config_tready) begin - ifft_config_tvalid <= 1'd1; - ifft_in_nd <= 1'd0; - state_ifft <= state_ifft + 2'd1; - end - else begin - ifft_config_tvalid <= 1'd0; - ifft_in_nd <= 1'd0; - state_ifft <= state_ifft; - end - end - //每帧一开始ifft核输入交给信道估计模块，直到flag_ChnEstFFT_done到来，说明信道估计两次fft输入完毕(Chn_Estimate给出) - 2'd1:begin - ifft_config_tvalid <= 1'd0; - if(flag_ChnEstFFT_done) begin - ifft_in_i <= ifft_in_i_data; - ifft_in_q <= ifft_in_q_data; - ifft_in_nd <= nd_dataifft; - state_ifft <= state_ifft + 2'd1; - end - else begin - ifft_in_i <= ifft_in_i_pilot; - ifft_in_q <= ifft_in_q_pilot; - ifft_in_nd <= nd_pilotifft; - state_ifft <= state_ifft; - end - end - //nd_pilot2拉高，说明下一个征服导频头处理完毕，ifft输入控制权交还信道估计模块 - 2'd2:begin - ifft_config_tvalid <= 1'd0; - if(nd_pilot2) begin - ifft_in_i <= ifft_in_i_pilot; - ifft_in_q <= ifft_in_q_pilot; - ifft_in_nd <= nd_pilotifft; - state_ifft <= 2'd1; - end - else begin - ifft_in_i <= ifft_in_i_data; - ifft_in_q <= ifft_in_q_data; - ifft_in_nd <= nd_dataifft; - state_ifft <= state_ifft; - end - end - default:state_ifft <= 2'd0; - endcase - end - end - - - - - - - //----------------------------------------------------MMSE信道估计结果RAM--------------------------------------------------// - wire write_MMSE_wea; - wire [7:0] addrin_MMSE; - wire [7:0] addrout_MMSE; - wire [21:0] din_MMSE; - wire [21:0] dout_MMSE; - - RAM_ChnEst_MMSE RAM_ChnEst_MMSE ( - .clka (clk), // input wire clka - .wea (write_MMSE_wea), // input wire [0 : 0] wea - .addra (addrin_MMSE), // input wire [7 : 0] addra - .dina (din_MMSE), // input wire [21 : 0] dina - .clkb (clk), // input wire clkb - .addrb (addrout_MMSE), // input wire [7 : 0] addrb - .doutb (dout_MMSE) // output wire [21 : 0] doutb - ); - - - - - - - - //----------------------------------------------------MMSE信道估计模块--------------------------------------------------// - Chn_Estimate Chn_Estimate_djy ( - .clk (clk), - .rst (rst), - //零域估计，默认值为8'd29 - .Zerozone_vio (Zerozone_vio), - //增强导频序列 - .nd_pilot2 (nd_pilot2), - .pilot_datai (pilot_datai), - .pilot_dataq (pilot_dataq), - //噪声估计结果 - .nd_EstNoise (nd_EstNoise), - .EstNoise_i (EstNoise_i), - .EstNoise_q (EstNoise_q), - //fft核 - .fft_out_i (fft_out_i), - .fft_out_q (fft_out_q), - .fft_out_nd (fft_out_nd), - .fft_index (fft_index), - .fft_in_i (fft_in_i_pilot), - .fft_in_q (fft_in_q_pilot), - .fft_in_nd (nd_pilotfft), - //ifft核 - .ifft_out_i (ifft_out_i), - .ifft_out_q (ifft_out_q), - .ifft_out_nd (ifft_out_nd), - .ifft_index (ifft_index), - .ifft_in_i (ifft_in_i_pilot), - .ifft_in_q (ifft_in_q_pilot), - .ifft_in_nd (nd_pilotifft), - //信道估计两次fft输入完毕后拉高1clk - .flag_ChnEstFFT_done (flag_ChnEstFFT_done), //信道估计两次fft输入完毕后拉高1clk - //MMSE信道估计结果RAM - .write_MMSE_wea (write_MMSE_wea), - .addrin_MMSE (addrin_MMSE), - .din_MMSE (din_MMSE), - //debug,溢出标志 - .flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14), //第1个fft结果截位，即导频fft结果的截位，26截到14 - .flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18), //第2个fft结果截位，即ZF信道估计结果的截位，26截到18 - .flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i), //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到20 - .flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q), //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到20 - .flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i), //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 - .flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q), //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 - .flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28), //第2个除法器，即MMSE除法的分母截位，31截到28 - .flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11) //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11 - ); - - - - - - - - //------------------------------------------------------------均衡模块-------------------------------------------------------// - - data_equalizer data_equalizer_djy ( - .clk (clk), - .rst (rst), - .EQUenable_vio (EQUenable_vio), - //进程flag - .nd_pilot2 (nd_pilot2), - .flag_ChnEstFFT_done(flag_ChnEstFFT_done), //信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出) - //数据的fifo，4个 - .dout_data1i (dout_data1i), - .dout_data1q (dout_data1q), - .rd_en_data1 (rd_en_data1), - .dout_data2i (dout_data2i), - .dout_data2q (dout_data2q), - .rd_en_data2 (rd_en_data2), - .flag_dataow (flag_dataow), //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取 - //fft核 - .fft_out_i (fft_out_i), - .fft_out_q (fft_out_q), - .fft_out_nd (fft_out_nd), - .fft_index (fft_index), - .fft_in_i (fft_in_i_data), - .fft_in_q (fft_in_q_data), - .fft_in_nd (nd_datafft), - //ifft核 - .ifft_out_i (ifft_out_i), - .ifft_out_q (ifft_out_q), - .ifft_out_nd (ifft_out_nd), - .ifft_index (ifft_index), - .ifft_in_i (ifft_in_i_data), - .ifft_in_q (ifft_in_q_data), - .ifft_in_nd (nd_dataifft), - //MMSE信道估计结果RAM - .addrout_MMSE (addrout_MMSE), - .dout_MMSE (dout_MMSE), - //均衡结果输出 - .nd_SC_FDE_dout (nd_SC_FDE_dout), - .SC_FDE_douti (SC_FDE_douti), - .SC_FDE_doutq (SC_FDE_doutq), - //debug,溢出标志 - .flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i), //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 - .flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q), //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 - .flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i), //数据段ow的fft输出截位，26截到16 - .flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q), //数据段ow的fft输出截位，26截到16 - .flagoverflow_FDE_dataout_29to10i (flagoverflow_FDE_dataout_29to10i), //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 - .flagoverflow_FDE_dataout_29to10q (flagoverflow_FDE_dataout_29to10q) //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 + //-------------------------------------------data数据ow的fifo，4个--------------------------------------------// + wire rd_en_data1; + wire [9:0] dout_data1i; + wire full_data1i; + wire empty_data1i; + fifo_ow256 fifo_data_ow1i ( + .rst (rst), // input wire rst + .wr_clk(clk), // input wire wr_clk + .rd_clk(clk), // input wire rd_clk + .din (din_data1i), // input wire [9 : 0] din + .wr_en (wr_en_data1), // input wire wr_en + .rd_en (rd_en_data1), // input wire rd_en + .dout (dout_data1i), // output wire [9 : 0] dout + .full (full_data1i), // output wire full + .empty (empty_data1i) // output wire empty ); - - - - - - //-----------------------------------------------------------------------写测试文件---------------------------------------------------------------------// - //----------------------------------------验证data_ow----------------------------------// - // integer handle02; - // integer handle03; - // integer handle04; - // integer handle05; - // integer handle06; - // integer handle07; - // integer handle08; - // reg enable1 = 0; - // initial begin - // handle01=$fopen("pilot_datai.txt","w"); $fclose(handle01); - // handle02=$fopen("pilot_dataq.txt","w"); $fclose(handle02); - // handle03=$fopen("pilot_noisei.txt","w"); $fclose(handle03); - // handle04=$fopen("pilot_noiseq.txt","w"); $fclose(handle04); - - // handle05=$fopen("din_data1i.txt","w"); $fclose(handle05); - // handle06=$fopen("din_data1q.txt","w"); $fclose(handle06); - // handle07=$fopen("din_data2i.txt","w"); $fclose(handle07); - // handle08=$fopen("din_data2q.txt","w"); $fclose(handle08); - - // #10; - // enable1 = 1; - // end - // always@(posedge clk)begin - // if(enable1)begin - // if(nd_pilot2)begin - // handle01=$fopen("pilot_datai.txt","a+");$fwrite(handle01,"%d\n",$signed(pilot_datai));$fclose(handle01); - // handle02=$fopen("pilot_dataq.txt","a+");$fwrite(handle02,"%d\n",$signed(pilot_dataq));$fclose(handle02); - // handle03=$fopen("pilot_noisei.txt","a+");$fwrite(handle03,"%d\n",$signed(pilot_noisei));$fclose(handle03); - // handle04=$fopen("pilot_noiseq.txt","a+");$fwrite(handle04,"%d\n",$signed(pilot_noiseq));$fclose(handle04); - // end - // if(wr_en_data1)begin - // handle05=$fopen("din_data1i.txt","a+");$fwrite(handle05,"%d\n",$signed(din_data1i));$fclose(handle05); - // handle06=$fopen("din_data1q.txt","a+");$fwrite(handle06,"%d\n",$signed(din_data1q));$fclose(handle06); - // end - // if(wr_en_data2)begin - // handle07=$fopen("din_data2i.txt","a+");$fwrite(handle07,"%d\n",$signed(din_data2i));$fclose(handle07); - // handle08=$fopen("din_data2q.txt","a+");$fwrite(handle08,"%d\n",$signed(din_data2q));$fclose(handle08); - // end - // end - // end - - - - // ----------------------------------------验证data_ow----------------------------------// - // integer handle01; - // integer handle02; - // integer handle03; - // integer handle04; - // integer handle05; - // integer handle06; - // integer handle07; - // integer handle08; - // integer handle09; - // integer handle10; + wire [9:0] dout_data1q; + wire full_data1q; + wire empty_data1q; + fifo_ow256 fifo_data_ow1q ( + .rst (rst), // input wire rst + .wr_clk(clk), // input wire wr_clk + .rd_clk(clk), // input wire rd_clk + .din (din_data1q), // input wire [9 : 0] din + .wr_en (wr_en_data1), // input wire wr_en + .rd_en (rd_en_data1), // input wire rd_en + .dout (dout_data1q), // output wire [9 : 0] dout + .full (full_data1q), // output wire full + .empty (empty_data1q) // output wire empty + ); - // reg enable1 = 0; - // initial begin - // handle01=$fopen("fft_out_i.txt","w"); $fclose(handle01); - // handle02=$fopen("fft_out_q.txt","w"); $fclose(handle02); - // handle03=$fopen("ifft_out_i.txt","w"); $fclose(handle03); - // handle04=$fopen("ifft_out_q.txt","w"); $fclose(handle04); - // handle05=$fopen("fft_in_i.txt","w"); $fclose(handle05); - // handle06=$fopen("fft_in_q.txt","w"); $fclose(handle06); - // handle07=$fopen("ifft_in_i.txt","w"); $fclose(handle07); - // handle08=$fopen("ifft_in_q.txt","w"); $fclose(handle08); - // handle09=$fopen("SC_FDE_douti.txt","w"); $fclose(handle09); - // handle10=$fopen("SC_FDE_doutq.txt","w"); $fclose(handle10); - - // #10; - // enable1 = 1; - // end + wire rd_en_data2; + wire [9:0] dout_data2i; + wire full_data2i; + wire empty_data2i; + fifo_ow256 fifo_data_ow2i ( + .rst (rst), // input wire rst + .wr_clk(clk), // input wire wr_clk + .rd_clk(clk), // input wire rd_clk + .din (din_data2i), // input wire [9 : 0] din + .wr_en (wr_en_data2), // input wire wr_en + .rd_en (rd_en_data2), // input wire rd_en + .dout (dout_data2i), // output wire [9 : 0] dout + .full (full_data2i), // output wire full + .empty (empty_data2i) // output wire empty + ); - // always@(posedge clk)begin - // if(enable1)begin - // if(fft_out_nd)begin - // handle01=$fopen("fft_out_i.txt","a+");$fwrite(handle01,"%d\n",$signed(fft_out_i));$fclose(handle01); - // handle02=$fopen("fft_out_q.txt","a+");$fwrite(handle02,"%d\n",$signed(fft_out_q));$fclose(handle02); - // end - // if(ifft_out_nd)begin - // handle03=$fopen("ifft_out_i.txt","a+");$fwrite(handle03,"%d\n",$signed(ifft_out_i));$fclose(handle03); - // handle04=$fopen("ifft_out_q.txt","a+");$fwrite(handle04,"%d\n",$signed(ifft_out_q));$fclose(handle04); - // end - // if(fft_in_nd)begin - // handle05=$fopen("fft_in_i.txt","a+");$fwrite(handle05,"%d\n",$signed(fft_in_i));$fclose(handle05); - // handle06=$fopen("fft_in_q.txt","a+");$fwrite(handle06,"%d\n",$signed(fft_in_q));$fclose(handle06); - // end - // if(ifft_in_nd)begin - // handle07=$fopen("ifft_in_i.txt","a+");$fwrite(handle07,"%d\n",$signed(ifft_in_i));$fclose(handle07); - // handle08=$fopen("ifft_in_q.txt","a+");$fwrite(handle08,"%d\n",$signed(ifft_in_q));$fclose(handle08); - // end - // if(nd_SC_FDE_dout)begin - // handle09=$fopen("SC_FDE_douti.txt","a+");$fwrite(handle09,"%d\n",$signed(SC_FDE_douti));$fclose(handle09); - // handle10=$fopen("SC_FDE_doutq.txt","a+");$fwrite(handle10,"%d\n",$signed(SC_FDE_doutq));$fclose(handle10); - // end - // end - // end + wire [9:0] dout_data2q; + wire full_data2q; + wire empty_data2q; + fifo_ow256 fifo_data_ow2q ( + .rst (rst), // input wire rst + .wr_clk(clk), // input wire wr_clk + .rd_clk(clk), // input wire rd_clk + .din (din_data2q), // input wire [9 : 0] din + .wr_en (wr_en_data2), // input wire wr_en + .rd_en (rd_en_data2), // input wire rd_en + .dout (dout_data2q), // output wire [9 : 0] dout + .full (full_data2q), // output wire full + .empty (empty_data2q) // output wire empty + ); + + + + + + + + + //-----------------------------------------------------噪声估计--------------------------------------------------// + //--------------------------------------------噪声估计结果放大了256*49倍-----------------------------------------// + //噪声估计结果 + wire nd_EstNoise; + wire [27:0] EstNoise_i; + wire [27:0] EstNoise_q; + + Noise_Estimate Noise_Estimate_djy ( + .clk(clk), + .rst(rst), + + .nd_pilot2 (nd_pilot2), + .pilot_noisei(pilot_noisei), + .pilot_noiseq(pilot_noiseq), + + .nd_EstNoise(nd_EstNoise), + .EstNoise_i (EstNoise_i), + .EstNoise_q (EstNoise_q) + ); + + + + + + + + + //------------------------------------------fft核，及其输入输出控制器------------------------------------------// + reg fft_config_tvalid = 1'd0; + wire fft_config_tready; + reg [16:0] fft_in_i = 17'd0; + reg [16:0] fft_in_q = 17'd0; + reg fft_in_nd = 1'd0; + wire fft_in_tready; + wire [63:0] fft_out_tdata; + wire [25:0] fft_out_i; + wire [25:0] fft_out_q; + wire fft_out_nd; + wire [ 7:0] fft_index; + + assign fft_out_i = fft_out_tdata[25:0]; + assign fft_out_q = fft_out_tdata[57:32]; + + wire m_axis_data_tlast; + wire event_frame_started; + wire event_tlast_unexpected; + wire event_tlast_missing; + wire event_status_channel_halt; + wire event_data_in_channel_halt; + wire event_data_out_channel_halt; + + fft_256 fft_256 ( + .aclk (clk), // input wire aclk + .aresetn (~rst), // input wire aresetn低有效复位，每次帧结束后复位8clk，满足核要求 + .s_axis_config_tdata (8'd1), // input wire [7 : 0] s_axis_config_tdata + .s_axis_config_tvalid (fft_config_tvalid), // input wire s_axis_config_tvalid + .s_axis_config_tready (fft_config_tready), // output wire s_axis_config_tready + // s data + .s_axis_data_tdata ({7'd0, fft_in_q, 7'd0, fft_in_i}), // input wire [47 : 0] s_axis_data_tdata + .s_axis_data_tvalid (fft_in_nd), // input wire s_axis_data_tvalid + .s_axis_data_tready (fft_in_tready), // output wire s_axis_data_tready + .s_axis_data_tlast (1'd0), // input wire s_axis_data_tlastn不用给这个信号 + // m data + .m_axis_data_tdata (fft_out_tdata), // output wire [63 : 0] m_axis_data_tdata + .m_axis_data_tuser (fft_index), // output wire [7 : 0] m_axis_data_tuser + .m_axis_data_tvalid (fft_out_nd), // output wire m_axis_data_tvalid + .m_axis_data_tready (1'd1), // input wire m_axis_data_tready + .m_axis_data_tlast (m_axis_data_tlast), // output wire m_axis_data_tlast + //flag + .event_frame_started (event_frame_started), // output wire event_frame_started + .event_tlast_unexpected (event_tlast_unexpected), // output wire event_tlast_unexpected + .event_tlast_missing (event_tlast_missing), // output wire event_tlast_missing + .event_status_channel_halt (event_status_channel_halt), // output wire event_status_channel_halt + .event_data_in_channel_halt (event_data_in_channel_halt), // output wire event_data_in_channel_halt + .event_data_out_channel_halt(event_data_out_channel_halt) // output wire event_data_out_channel_halt + ); + + + reg [ 1:0] state_fft = 2'd0; + wire nd_pilotfft; + wire [16:0] fft_in_i_pilot; + wire [16:0] fft_in_q_pilot; + wire nd_datafft; + wire [16:0] fft_in_i_data; + wire [16:0] fft_in_q_data; + + always @(posedge clk) begin + if (rst) begin + fft_config_tvalid <= 1'd0; + fft_in_i <= 17'd0; + fft_in_q <= 17'd0; + fft_in_nd <= 1'd0; + state_fft <= 2'd0; + end + else begin + case (state_fft) + //帧间复位结束后，先等待fft_config_tvalid拉高，说明fft核允许配置，先写入一次fft配置 + 2'd0: begin + if (fft_config_tready) begin + fft_config_tvalid <= 1'd1; + fft_in_nd <= 1'd0; + state_fft <= state_fft + 2'd1; + end + else begin + fft_config_tvalid <= 1'd0; + fft_in_nd <= 1'd0; + state_fft <= state_fft; + end + end + //每帧一开始fft核输入交给信道估计模块，直到flag_ChnEstFFT_done到来，说明信道估计两次fft输入完毕(Chn_Estimate给出) + 2'd1: begin + fft_config_tvalid <= 1'd0; + if (flag_ChnEstFFT_done) begin + fft_in_i <= fft_in_i_data; + fft_in_q <= fft_in_q_data; + fft_in_nd <= nd_datafft; + state_fft <= state_fft + 2'd1; + end + else begin + fft_in_i <= fft_in_i_pilot; + fft_in_q <= fft_in_q_pilot; + fft_in_nd <= nd_pilotfft; + state_fft <= state_fft; + end + end + //nd_pilot2拉高，说明下一个征服导频头处理完毕，fft输入控制权交还信道估计模块 + 2'd2: begin + fft_config_tvalid <= 1'd0; + if (nd_pilot2) begin + fft_in_i <= fft_in_i_pilot; + fft_in_q <= fft_in_q_pilot; + fft_in_nd <= nd_pilotfft; + state_fft <= 2'd1; + end + else begin + fft_in_i <= fft_in_i_data; + fft_in_q <= fft_in_q_data; + fft_in_nd <= nd_datafft; + state_fft <= state_fft; + end + end + default: state_fft <= 2'd0; + endcase + end + end + + + + //------------------------------------------ifft核，及其输入输出控制器------------------------------------------// + reg ifft_config_tvalid = 1'd0; + wire ifft_config_tready; + reg [19:0] ifft_in_i = 20'd0; + reg [19:0] ifft_in_q = 20'd0; + reg ifft_in_nd = 1'd0; + wire ifft_in_tready; + wire [63:0] ifft_out_tdata; + wire [28:0] ifft_out_i; + wire [28:0] ifft_out_q; + wire ifft_out_nd; + wire [ 7:0] ifft_index; + + assign ifft_out_i = ifft_out_tdata[28:0]; + assign ifft_out_q = ifft_out_tdata[60:32]; + + wire m_axis_data_tlast_ifft; + wire event_frame_started_ifft; + wire event_tlast_unexpected_ifft; + wire event_tlast_missing_ifft; + wire event_status_channel_halt_ifft; + wire event_data_in_channel_halt_ifft; + wire event_data_out_channel_halt_ifft; + + ifft_256 ifft_256 ( + .aclk (clk), // input wire aclk + .aresetn(~rst), // input wire aresetn + + .s_axis_config_tdata (8'd0), // input wire [7 : 0] s_axis_config_tdata + .s_axis_config_tvalid(ifft_config_tvalid), // input wire s_axis_config_tvalid + .s_axis_config_tready(ifft_config_tready), // output wire s_axis_config_tready + + .s_axis_data_tdata ({4'd0, ifft_in_q, 4'd0, ifft_in_i}), // input wire [47 : 0] s_axis_data_tdata + .s_axis_data_tvalid(ifft_in_nd), // input wire s_axis_data_tvalid + .s_axis_data_tready(ifft_in_tready), // output wire s_axis_data_tready + .s_axis_data_tlast (1'd0), // input wire s_axis_data_tlast + + .m_axis_data_tdata (ifft_out_tdata), // output wire [63 : 0] m_axis_data_tdata + .m_axis_data_tuser (ifft_index), // output wire [7 : 0] m_axis_data_tuser + .m_axis_data_tvalid(ifft_out_nd), // output wire m_axis_data_tvalid + .m_axis_data_tready(1'd1), // input wire m_axis_data_tready + .m_axis_data_tlast (m_axis_data_tlast_ifft), // output wire m_axis_data_tlast + + .event_frame_started (event_frame_started_ifft), // output wire event_frame_started + .event_tlast_unexpected (event_tlast_unexpected_ifft), // output wire event_tlast_unexpected + .event_tlast_missing (event_tlast_missing_ifft), // output wire event_tlast_missing + .event_status_channel_halt (event_status_channel_halt_ifft), // output wire event_status_channel_halt + .event_data_in_channel_halt (event_data_in_channel_halt_ifft), // output wire event_data_in_channel_halt + .event_data_out_channel_halt(event_data_out_channel_halt_ifft) // output wire event_data_out_channel_halt + ); + + + reg [ 1:0] state_ifft = 2'd0; + wire nd_pilotifft; + wire [19:0] ifft_in_i_pilot; + wire [19:0] ifft_in_q_pilot; + wire nd_dataifft; + wire [19:0] ifft_in_i_data; + wire [19:0] ifft_in_q_data; + + always @(posedge clk) begin + if (rst) begin + ifft_config_tvalid <= 1'd0; + ifft_in_i <= 20'd0; + ifft_in_q <= 20'd0; + ifft_in_nd <= 1'd0; + state_ifft <= 2'd0; + end + else begin + case (state_ifft) + //帧间复位结束后，先等待ifft_config_tvalid拉高，说明ifft核允许配置，先写入一次ifft配置 + 2'd0: begin + if (ifft_config_tready) begin + ifft_config_tvalid <= 1'd1; + ifft_in_nd <= 1'd0; + state_ifft <= state_ifft + 2'd1; + end + else begin + ifft_config_tvalid <= 1'd0; + ifft_in_nd <= 1'd0; + state_ifft <= state_ifft; + end + end + //每帧一开始ifft核输入交给信道估计模块，直到flag_ChnEstFFT_done到来，说明信道估计两次fft输入完毕(Chn_Estimate给出) + 2'd1: begin + ifft_config_tvalid <= 1'd0; + if (flag_ChnEstFFT_done) begin + ifft_in_i <= ifft_in_i_data; + ifft_in_q <= ifft_in_q_data; + ifft_in_nd <= nd_dataifft; + state_ifft <= state_ifft + 2'd1; + end + else begin + ifft_in_i <= ifft_in_i_pilot; + ifft_in_q <= ifft_in_q_pilot; + ifft_in_nd <= nd_pilotifft; + state_ifft <= state_ifft; + end + end + //nd_pilot2拉高，说明下一个征服导频头处理完毕，ifft输入控制权交还信道估计模块 + 2'd2: begin + ifft_config_tvalid <= 1'd0; + if (nd_pilot2) begin + ifft_in_i <= ifft_in_i_pilot; + ifft_in_q <= ifft_in_q_pilot; + ifft_in_nd <= nd_pilotifft; + state_ifft <= 2'd1; + end + else begin + ifft_in_i <= ifft_in_i_data; + ifft_in_q <= ifft_in_q_data; + ifft_in_nd <= nd_dataifft; + state_ifft <= state_ifft; + end + end + default: state_ifft <= 2'd0; + endcase + end + end + + + //----------------------------------------------------MMSE信道估计结果RAM--------------------------------------------------// + wire write_MMSE_wea; + wire [ 7:0] addrin_MMSE; + wire [ 7:0] addrout_MMSE; + wire [21:0] din_MMSE; + wire [21:0] dout_MMSE; + + RAM_ChnEst_MMSE RAM_ChnEst_MMSE ( + .clka (clk), // input wire clka + .wea (write_MMSE_wea), // input wire [0 : 0] wea + .addra(addrin_MMSE), // input wire [7 : 0] addra + .dina (din_MMSE), // input wire [21 : 0] dina + .clkb (clk), // input wire clkb + .addrb(addrout_MMSE), // input wire [7 : 0] addrb + .doutb(dout_MMSE) // output wire [21 : 0] doutb + ); + + //----------------------------------------------------MMSE信道估计模块--------------------------------------------------// + Chn_Estimate Chn_Estimate_djy ( + .clk (clk), + .rst (rst), + //零域估计，默认值为8'd29 + .Zerozone_vio (Zerozone_vio), + //增强导频序列 + .nd_pilot2 (nd_pilot2), + .pilot_datai (pilot_datai), + .pilot_dataq (pilot_dataq), + //噪声估计结果 + .nd_EstNoise (nd_EstNoise), + .EstNoise_i (EstNoise_i), + .EstNoise_q (EstNoise_q), + //fft核 + .fft_out_i (fft_out_i), + .fft_out_q (fft_out_q), + .fft_out_nd (fft_out_nd), + .fft_index (fft_index), + .fft_in_i (fft_in_i_pilot), + .fft_in_q (fft_in_q_pilot), + .fft_in_nd (nd_pilotfft), + //ifft核 + .ifft_out_i (ifft_out_i), + .ifft_out_q (ifft_out_q), + .ifft_out_nd (ifft_out_nd), + .ifft_index (ifft_index), + .ifft_in_i (ifft_in_i_pilot), + .ifft_in_q (ifft_in_q_pilot), + .ifft_in_nd (nd_pilotifft), + //信道估计两次fft输入完毕后拉高1clk + .flag_ChnEstFFT_done (flag_ChnEstFFT_done), //信道估计两次fft输入完毕后拉高1clk + //MMSE信道估计结果RAM + .write_MMSE_wea (write_MMSE_wea), + .addrin_MMSE (addrin_MMSE), + .din_MMSE (din_MMSE), + //debug,溢出标志 + .flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14), //第1个fft结果截位，即导频fft结果的截位，26截到14 + .flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18), //第2个fft结果截位，即ZF信道估计结果的截位，26截到18 + .flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i), //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到20 + .flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q), //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到20 + .flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i), //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 + .flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q), //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 + .flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28), //第2个除法器，即MMSE除法的分母截位，31截到28 + .flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11) //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11 + ); + + //------------------------------------------------------------均衡模块-------------------------------------------------------// + + data_equalizer data_equalizer_djy ( + .clk (clk), + .rst (rst), + .EQUenable_vio (EQUenable_vio), + //进程flag + .nd_pilot2 (nd_pilot2), + .flag_ChnEstFFT_done (flag_ChnEstFFT_done), //信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出) + //数据的fifo，4个 + .dout_data1i (dout_data1i), + .dout_data1q (dout_data1q), + .rd_en_data1 (rd_en_data1), + .dout_data2i (dout_data2i), + .dout_data2q (dout_data2q), + .rd_en_data2 (rd_en_data2), + .flag_dataow (flag_dataow), //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取 + //fft核 + .fft_out_i (fft_out_i), + .fft_out_q (fft_out_q), + .fft_out_nd (fft_out_nd), + .fft_index (fft_index), + .fft_in_i (fft_in_i_data), + .fft_in_q (fft_in_q_data), + .fft_in_nd (nd_datafft), + //ifft核 + .ifft_out_i (ifft_out_i), + .ifft_out_q (ifft_out_q), + .ifft_out_nd (ifft_out_nd), + .ifft_index (ifft_index), + .ifft_in_i (ifft_in_i_data), + .ifft_in_q (ifft_in_q_data), + .ifft_in_nd (nd_dataifft), + //MMSE信道估计结果RAM + .addrout_MMSE (addrout_MMSE), + .dout_MMSE (dout_MMSE), + //均衡结果输出 + .nd_SC_FDE_dout (nd_SC_FDE_dout), + .SC_FDE_douti (SC_FDE_douti), + .SC_FDE_doutq (SC_FDE_doutq), + //debug,溢出标志 + .flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i), //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 + .flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q), //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 + .flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i), //数据段ow的fft输出截位，26截到16 + .flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q), //数据段ow的fft输出截位，26截到16 + .flagoverflow_FDE_dataout_29to10i(flagoverflow_FDE_dataout_29to10i), //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 + .flagoverflow_FDE_dataout_29to10q(flagoverflow_FDE_dataout_29to10q) //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 + ); - endmodule diff --git a/hdl/TSync_Abs_new16.v b/hdl/TSync_Abs_new16.v index 7b1085b..3e5fb5d 100644 --- a/hdl/TSync_Abs_new16.v +++ b/hdl/TSync_Abs_new16.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/TSync_Abs_new4.v b/hdl/TSync_Abs_new4.v index f7edd6c..f40a2ed 100644 --- a/hdl/TSync_Abs_new4.v +++ b/hdl/TSync_Abs_new4.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/TimeSync_top.v b/hdl/TimeSync_top.v index 253f373..9a33423 100644 --- a/hdl/TimeSync_top.v +++ b/hdl/TimeSync_top.v @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/hdl/VNU_1din.v b/hdl/VNU_1din.v new file mode 100644 index 0000000..f75727d --- /dev/null +++ b/hdl/VNU_1din.v @@ -0,0 +1,78 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: VNU_1din +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module VNU_1din( + input clk, + input [7:0] din01_CN_CU, //校验节点信息输入 + input [7:0] din02_CHNL_CU, //信道信息输入 + + output reg [7:0] dout01_CU=8'd0,//校验节点更新输出 + output reg [0:0] dout02_result_CU=1'd0//判决结果输出 + );//输出相对输入延时8个周期(8) + + reg [8:0] sum=9'd0; + + reg [0:0] result_reg0=1'd0; + reg [0:0] result_reg1=1'd0; + reg [0:0] result_reg2=1'd0; + reg [0:0] result_reg3=1'd0; + reg [0:0] result_reg4=1'd0; + + reg [8:0] din01_CN_CU_9bit=9'd0; + reg [8:0] din02_CHNL_CU_9bit=9'd0; + + reg [7:0] din02_CHNL_CU_reg0=8'd0; + reg [7:0] din02_CHNL_CU_reg1=8'd0; + reg [7:0] din02_CHNL_CU_reg2=8'd0; + reg [7:0] din02_CHNL_CU_reg3=8'd0; + reg [7:0] din02_CHNL_CU_reg4=8'd0; + reg [7:0] din02_CHNL_CU_reg5=8'd0; + reg [7:0] din02_CHNL_CU_reg6=8'd0; + + always @ (posedge clk) begin//先把输入转换为9bit + din01_CN_CU_9bit <= {din01_CN_CU[7],din01_CN_CU[7:0]}; + din02_CHNL_CU_9bit <= {din02_CHNL_CU[7],din02_CHNL_CU[7:0]}; + end + + always @ (posedge clk) begin//结果更新过程 + sum <= din01_CN_CU_9bit + din02_CHNL_CU_9bit; + result_reg0 <= {sum[8]}; + + result_reg1 <= result_reg0; + result_reg2 <= result_reg1; + result_reg3 <= result_reg2; + result_reg4 <= result_reg3; + dout02_result_CU <= result_reg4; + end + + always @ (posedge clk) begin + din02_CHNL_CU_reg0 <= din02_CHNL_CU; + din02_CHNL_CU_reg1 <= din02_CHNL_CU_reg0; + din02_CHNL_CU_reg2 <= din02_CHNL_CU_reg1; + din02_CHNL_CU_reg3 <= din02_CHNL_CU_reg2; + din02_CHNL_CU_reg4 <= din02_CHNL_CU_reg3; + din02_CHNL_CU_reg5 <= din02_CHNL_CU_reg4; + din02_CHNL_CU_reg6 <= din02_CHNL_CU_reg5; + dout01_CU <= din02_CHNL_CU_reg6; + end +endmodule + diff --git a/hdl/VNU_2din.v b/hdl/VNU_2din.v new file mode 100644 index 0000000..c09ecb4 --- /dev/null +++ b/hdl/VNU_2din.v @@ -0,0 +1,143 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: VNU_2din +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module VNU_2din(//注意：所有的输入数据同时进来本模块，即数据clk是对齐的 + input clk, + input [7:0] din01_CN_CU, //校验节点信息输入 + input [7:0] din02_CN_CU, //校验节点信息输入 + + input [7:0] din03_CHNL_CU, //信道信息输入 + + output reg [7:0] dout01_CU=8'd0, //校验节点更新输出 + output reg [7:0] dout02_CU=8'd0, //校验节点更新输出 + output reg [0:0] dout03_result_CU=1'd0 //判决结果输出 + );//输出相对输入延时8个周期(8) + reg [9:0] din01_CN_CU_10bit=10'd0,din01_CN_CU_10bit_reg0=10'd0,din01_CN_CU_10bit_reg1=10'd0; + reg [9:0] din02_CN_CU_10bit=10'd0,din02_CN_CU_10bit_reg0=10'd0,din02_CN_CU_10bit_reg1=10'd0; + + + reg [9:0] din03_CHNL_CU_10bit=10'd0; + reg [9:0] din03_CHNL_CU_10bit_reg0=10'd0; + + reg [9:0] sum1=10'd0; + reg [9:0] sum=10'd0; + + reg [9:0] minus1=10'd0; + reg [9:0] minus2=10'd0; + + reg [9:0] minus1_reg0=10'd0; + reg [9:0] minus2_reg0=10'd0; + + + reg [9:0] minus1_reg1=10'd0; + reg [9:0] minus2_reg1=10'd0; + + reg [9:0] minus1_reg2=10'd0; + reg [9:0] minus2_reg2=10'd0; + + reg [9:0] minus1_abs=10'd0; + reg [9:0] minus2_abs=10'd0; + + reg [0:0] result_reg0=1'd0; + reg [0:0] result_reg1=1'd0; + reg [0:0] result_reg2=1'd0; + reg [0:0] result_reg3=1'd0; + + + always @ (posedge clk) begin//先把输入转换为10bit + din01_CN_CU_10bit <= {{2{din01_CN_CU[7]}},din01_CN_CU[7:0]}; + din02_CN_CU_10bit <= {{2{din02_CN_CU[7]}},din02_CN_CU[7:0]}; + din03_CHNL_CU_10bit <= {{2{din03_CHNL_CU[7]}},din03_CHNL_CU[7:0]}; + end + + always @ (posedge clk) begin//流水延时过程 + din01_CN_CU_10bit_reg0 <= din01_CN_CU_10bit; + din02_CN_CU_10bit_reg0 <= din02_CN_CU_10bit; + + din01_CN_CU_10bit_reg1 <= din01_CN_CU_10bit_reg0; + din02_CN_CU_10bit_reg1 <= din02_CN_CU_10bit_reg0; + + din03_CHNL_CU_10bit_reg0 <= din03_CHNL_CU_10bit; + + minus1_reg0 <= minus1; + minus2_reg0 <= minus2; + + minus1_reg1 <= minus1_reg0; + minus2_reg1 <= minus2_reg0; + + minus1_reg2 <= minus1_reg1; + minus2_reg2 <= minus2_reg1; + end + + + always @ (posedge clk) begin //结果更新过程 + sum1 <= din01_CN_CU_10bit + din02_CN_CU_10bit; + sum <= sum1 + din03_CHNL_CU_10bit_reg0; + + result_reg0 <= {sum[9]}; + result_reg1 <= result_reg0; + result_reg2 <= result_reg1; + result_reg3 <= result_reg2; + dout03_result_CU <= result_reg3; + + minus1 <= sum - din01_CN_CU_10bit_reg1; + minus2 <= sum - din02_CN_CU_10bit_reg1; + + if(minus1_reg1[9])//限幅前求绝对值操作 + minus1_abs <= ~minus1_reg1 + 10'd1; + else + minus1_abs <= minus1_reg1; + if(minus1_reg2[9]) begin//限幅操作 + if(minus1_abs>10'd127) + dout01_CU <= -8'd127; + else + dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]}; + // dout01_CU <= minus1_reg2; + end else begin + if(minus1_abs>10'd127) + dout01_CU <= 8'd127; + else + dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]}; + // dout01_CU <= minus1_reg2; + end + + if(minus2_reg1[9])//限幅前求绝对值操作 + minus2_abs <= ~minus2_reg1 + 10'd1; + else + minus2_abs <= minus2_reg1; + if(minus2_reg2[9]) begin//限幅操作 + if(minus2_abs>10'd127) + dout02_CU <= -8'd127; + else + dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]}; + // dout02_CU <= minus2_reg2; + end else begin + if(minus2_abs>10'd127) + dout02_CU <= 8'd127; + else + dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]}; + // dout02_CU <= minus2_reg2; + end + end + +endmodule + diff --git a/hdl/VNU_3din.v b/hdl/VNU_3din.v new file mode 100644 index 0000000..7ba20e0 --- /dev/null +++ b/hdl/VNU_3din.v @@ -0,0 +1,179 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: VNU_3din +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module VNU_3din( + input clk, + input [7:0] din01_CN_CU, //校验节点信息输入 + input [7:0] din02_CN_CU, //校验节点信息输入 + input [7:0] din03_CN_CU, //校验节点信息输入 + + input [7:0] din04_CHNL_CU, //信道信息输入 + + output reg [7:0] dout01_CU=8'd0,//校验节点更新输出 + output reg [7:0] dout02_CU=8'd0,//校验节点更新输出 + output reg [7:0] dout03_CU=8'd0,//校验节点更新输出 + + output reg [0:0] dout04_result_CU=1'd0//判决结果输出 + );//输出相对输入延时8个周期(8) + + reg [9:0] din01_CN_CU_10bit=10'd0; + reg [9:0] din02_CN_CU_10bit=10'd0; + reg [9:0] din03_CN_CU_10bit=10'd0; + + reg [9:0] din01_CN_CU_10bit_reg0=10'd0; + reg [9:0] din02_CN_CU_10bit_reg0=10'd0; + reg [9:0] din03_CN_CU_10bit_reg0=10'd0; + + reg [9:0] din01_CN_CU_10bit_reg1=10'd0; + reg [9:0] din02_CN_CU_10bit_reg1=10'd0; + reg [9:0] din03_CN_CU_10bit_reg1=10'd0; + + reg [9:0] din04_CHNL_CU_10bit=10'd0; + + reg [9:0] sum1=10'd0; + reg [9:0] sum2=10'd0; + reg [9:0] sum=10'd0; + + reg [9:0] minus1=10'd0; + reg [9:0] minus2=10'd0; + reg [9:0] minus3=10'd0; + + reg [9:0] minus1_reg0=10'd0; + reg [9:0] minus2_reg0=10'd0; + reg [9:0] minus3_reg0=10'd0; + + reg [9:0] minus1_reg1=10'd0; + reg [9:0] minus2_reg1=10'd0; + reg [9:0] minus3_reg1=10'd0; + + reg [9:0] minus1_reg2=10'd0; + reg [9:0] minus2_reg2=10'd0; + reg [9:0] minus3_reg2=10'd0; + + reg [9:0] minus1_abs=10'd0; + reg [9:0] minus2_abs=10'd0; + reg [9:0] minus3_abs=10'd0; + + reg [0:0] result_reg0=1'd0; + reg [0:0] result_reg1=1'd0; + reg [0:0] result_reg2=1'd0; + reg [0:0] result_reg3=1'd0; + always @ (posedge clk) begin//先把输入转换为10bit + din01_CN_CU_10bit <= {{2{din01_CN_CU[7]}},din01_CN_CU[7:0]}; + din02_CN_CU_10bit <= {{2{din02_CN_CU[7]}},din02_CN_CU[7:0]}; + din03_CN_CU_10bit <= {{2{din03_CN_CU[7]}},din03_CN_CU[7:0]}; + din04_CHNL_CU_10bit <= {{2{din04_CHNL_CU[7]}},din04_CHNL_CU[7:0]}; + end + + always @ (posedge clk) begin//流水延时过程 + din01_CN_CU_10bit_reg0 <= din01_CN_CU_10bit; + din02_CN_CU_10bit_reg0 <= din02_CN_CU_10bit; + din03_CN_CU_10bit_reg0 <= din03_CN_CU_10bit; + + din01_CN_CU_10bit_reg1 <= din01_CN_CU_10bit_reg0; + din02_CN_CU_10bit_reg1 <= din02_CN_CU_10bit_reg0; + din03_CN_CU_10bit_reg1 <= din03_CN_CU_10bit_reg0; + + minus1_reg0 <= minus1; + minus2_reg0 <= minus2; + minus3_reg0 <= minus3; + + minus1_reg1 <= minus1_reg0; + minus2_reg1 <= minus2_reg0; + minus3_reg1 <= minus3_reg0; + + minus1_reg2 <= minus1_reg1; + minus2_reg2 <= minus2_reg1; + minus3_reg2 <= minus3_reg1; + end + + always @ (posedge clk) begin//结果更新过程 + sum1 <= din01_CN_CU_10bit + din02_CN_CU_10bit; + sum2 <= din03_CN_CU_10bit + din04_CHNL_CU_10bit; + sum <= sum1 + sum2; + + result_reg0 <= {sum[9]}; + result_reg1 <= result_reg0; + result_reg2 <= result_reg1; + result_reg3 <= result_reg2; + dout04_result_CU <= result_reg3; + minus1 <= sum - din01_CN_CU_10bit_reg1; + minus2 <= sum - din02_CN_CU_10bit_reg1; + minus3 <= sum - din03_CN_CU_10bit_reg1; + + if(minus1_reg1[9])//限幅前求绝对值操作 + minus1_abs <= ~minus1_reg1 + 10'd1; + else + minus1_abs <= minus1_reg1; + if(minus1_reg2[9]) begin//限幅操作 + if(minus1_abs>10'd127) + dout01_CU <= -8'd127; + else + dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]}; + // dout01_CU <= minus1_reg2; + end else begin + if(minus1_abs>10'd127) + dout01_CU <= 8'd127; + else + dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]}; + // dout01_CU <= minus1_reg2; + end + + if(minus2_reg1[9])//限幅前求绝对值操作 + minus2_abs <= ~minus2_reg1 + 10'd1; + else + minus2_abs <= minus2_reg1; + if(minus2_reg2[9]) begin//限幅操作 + if(minus2_abs>10'd127) + dout02_CU <= -8'd127; + else + dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]}; + // dout02_CU <= minus2_reg2; + end else begin + if(minus2_abs>10'd127) + dout02_CU <= 8'd127; + else + dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]}; + // dout02_CU <= minus2_reg2; + end + + if(minus3_reg1[9])//限幅前求绝对值操作 + minus3_abs <= ~minus3_reg1 + 10'd1; + else + minus3_abs <= minus3_reg1; + if(minus3_reg2[9]) begin//限幅操作 + if(minus3_abs>10'd127) + dout03_CU <= -8'd127; + else + dout03_CU <= {minus3_reg2[9],minus3_reg2[6:0]}; + // dout03_CU <= minus3_reg2; + end else begin + if(minus3_abs>10'd127) + dout03_CU <= 8'd127; + else + dout03_CU <= {minus3_reg2[9],minus3_reg2[6:0]}; + // dout03_CU <= minus3_reg2; + end + end + +endmodule + diff --git a/hdl/VNU_6din.v b/hdl/VNU_6din.v new file mode 100644 index 0000000..9d3dadd --- /dev/null +++ b/hdl/VNU_6din.v @@ -0,0 +1,292 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: VNU_6din +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module VNU_6din( + input clk, + input [7:0] din01_CN_CU, //校验节点信息输入 + input [7:0] din02_CN_CU, //校验节点信息输入 + input [7:0] din03_CN_CU, //校验节点信息输入 + input [7:0] din04_CN_CU, //校验节点信息输入 + input [7:0] din05_CN_CU, //校验节点信息输入 + input [7:0] din06_CN_CU, //校验节点信息输入 + + input [7:0] din07_CHNL_CU, //信道信息输入 + + output reg [7:0] dout01_CU=8'd0,//校验节点更新输出 + output reg [7:0] dout02_CU=8'd0,//校验节点更新输出 + output reg [7:0] dout03_CU=8'd0,//校验节点更新输出 + output reg [7:0] dout04_CU=8'd0,//校验节点更新输出 + output reg [7:0] dout05_CU=8'd0,//校验节点更新输出 + output reg [7:0] dout06_CU=8'd0,//校验节点更新输出 + + output reg [0:0] dout07_result_CU=1'd0//判决结果输出 + );//输出相对输入延时8个周期 + + reg [10:0] din01_CN_CU_11bit=11'd0; + reg [10:0] din02_CN_CU_11bit=11'd0; + reg [10:0] din03_CN_CU_11bit=11'd0; + reg [10:0] din04_CN_CU_11bit=11'd0; + reg [10:0] din05_CN_CU_11bit=11'd0; + reg [10:0] din06_CN_CU_11bit=11'd0; + + reg [10:0] din01_CN_CU_11bit_reg0=11'd0; + reg [10:0] din02_CN_CU_11bit_reg0=11'd0; + reg [10:0] din03_CN_CU_11bit_reg0=11'd0; + reg [10:0] din04_CN_CU_11bit_reg0=11'd0; + reg [10:0] din05_CN_CU_11bit_reg0=11'd0; + reg [10:0] din06_CN_CU_11bit_reg0=11'd0; + + reg [10:0] din01_CN_CU_11bit_reg1=11'd0; + reg [10:0] din02_CN_CU_11bit_reg1=11'd0; + reg [10:0] din03_CN_CU_11bit_reg1=11'd0; + reg [10:0] din04_CN_CU_11bit_reg1=11'd0; + reg [10:0] din05_CN_CU_11bit_reg1=11'd0; + reg [10:0] din06_CN_CU_11bit_reg1=11'd0; + + reg [10:0] din01_CN_CU_11bit_reg2=11'd0; + reg [10:0] din02_CN_CU_11bit_reg2=11'd0; + reg [10:0] din03_CN_CU_11bit_reg2=11'd0; + reg [10:0] din04_CN_CU_11bit_reg2=11'd0; + reg [10:0] din05_CN_CU_11bit_reg2=11'd0; + reg [10:0] din06_CN_CU_11bit_reg2=11'd0; + + reg [10:0] din07_CHNL_CU_11bit=11'd0; + reg [10:0] din07_CHNL_CU_11bit_reg0=11'd0; + + + reg [10:0] sum1=11'd0; + reg [10:0] sum2=11'd0; + reg [10:0] sum3=11'd0; + reg [10:0] sum4=11'd0; + reg [10:0] sum5=11'd0; + reg [10:0] sum=11'd0; + + reg [10:0] minus1=11'd0; + reg [10:0] minus2=11'd0; + reg [10:0] minus3=11'd0; + reg [10:0] minus4=11'd0; + reg [10:0] minus5=11'd0; + reg [10:0] minus6=11'd0; + + reg [10:0] minus1_reg0=11'd0; + reg [10:0] minus2_reg0=11'd0; + reg [10:0] minus3_reg0=11'd0; + reg [10:0] minus4_reg0=11'd0; + reg [10:0] minus5_reg0=11'd0; + reg [10:0] minus6_reg0=11'd0; + + reg [10:0] minus1_reg1=11'd0; + reg [10:0] minus2_reg1=11'd0; + reg [10:0] minus3_reg1=11'd0; + reg [10:0] minus4_reg1=11'd0; + reg [10:0] minus5_reg1=11'd0; + reg [10:0] minus6_reg1=11'd0; + + reg [10:0] minus1_abs=11'd0; + reg [10:0] minus2_abs=11'd0; + reg [10:0] minus3_abs=11'd0; + reg [10:0] minus4_abs=11'd0; + reg [10:0] minus5_abs=11'd0; + reg [10:0] minus6_abs=11'd0; + + reg [0:0] result_reg0=1'd0; + reg [0:0] result_reg1=1'd0; + reg [0:0] result_reg2=1'd0; + + + always @ (posedge clk) begin//先把输入转换为11bit + din01_CN_CU_11bit <= {{3{din01_CN_CU[7]}},din01_CN_CU[7:0]}; + din02_CN_CU_11bit <= {{3{din02_CN_CU[7]}},din02_CN_CU[7:0]}; + din03_CN_CU_11bit <= {{3{din03_CN_CU[7]}},din03_CN_CU[7:0]}; + din04_CN_CU_11bit <= {{3{din04_CN_CU[7]}},din04_CN_CU[7:0]}; + din05_CN_CU_11bit <= {{3{din05_CN_CU[7]}},din05_CN_CU[7:0]}; + din06_CN_CU_11bit <= {{3{din06_CN_CU[7]}},din06_CN_CU[7:0]}; + din07_CHNL_CU_11bit <= {{3{din07_CHNL_CU[7]}},din07_CHNL_CU[7:0]}; + end + + always @ (posedge clk) begin//流水延时过程 + din01_CN_CU_11bit_reg0 <= din01_CN_CU_11bit; + din02_CN_CU_11bit_reg0 <= din02_CN_CU_11bit; + din03_CN_CU_11bit_reg0 <= din03_CN_CU_11bit; + din04_CN_CU_11bit_reg0 <= din04_CN_CU_11bit; + din05_CN_CU_11bit_reg0 <= din05_CN_CU_11bit; + din06_CN_CU_11bit_reg0 <= din06_CN_CU_11bit; + din07_CHNL_CU_11bit_reg0 <= din07_CHNL_CU_11bit; + + din01_CN_CU_11bit_reg1 <= din01_CN_CU_11bit_reg0; + din02_CN_CU_11bit_reg1 <= din02_CN_CU_11bit_reg0; + din03_CN_CU_11bit_reg1 <= din03_CN_CU_11bit_reg0; + din04_CN_CU_11bit_reg1 <= din04_CN_CU_11bit_reg0; + din05_CN_CU_11bit_reg1 <= din05_CN_CU_11bit_reg0; + din06_CN_CU_11bit_reg1 <= din06_CN_CU_11bit_reg0; + + din01_CN_CU_11bit_reg2 <= din01_CN_CU_11bit_reg1; + din02_CN_CU_11bit_reg2 <= din02_CN_CU_11bit_reg1; + din03_CN_CU_11bit_reg2 <= din03_CN_CU_11bit_reg1; + din04_CN_CU_11bit_reg2 <= din04_CN_CU_11bit_reg1; + din05_CN_CU_11bit_reg2 <= din05_CN_CU_11bit_reg1; + din06_CN_CU_11bit_reg2 <= din06_CN_CU_11bit_reg1; + + minus1_reg0 <= minus1; + minus2_reg0 <= minus2; + minus3_reg0 <= minus3; + minus4_reg0 <= minus4; + minus5_reg0 <= minus5; + minus6_reg0 <= minus6; + + minus1_reg1 <= minus1_reg0; + minus2_reg1 <= minus2_reg0; + minus3_reg1 <= minus3_reg0; + minus4_reg1 <= minus4_reg0; + minus5_reg1 <= minus5_reg0; + minus6_reg1 <= minus6_reg0; + end + + always @ (posedge clk) begin//结果更新过程 + sum1 <= din01_CN_CU_11bit + din02_CN_CU_11bit; + sum2 <= din03_CN_CU_11bit + din04_CN_CU_11bit; + sum3 <= din05_CN_CU_11bit + din06_CN_CU_11bit; + sum4 <= sum1 + sum2; + sum5 <= sum3 + din07_CHNL_CU_11bit_reg0; + sum <= sum4 + sum5; + + result_reg0 <= {sum[10]}; + result_reg1 <= result_reg0; + result_reg2 <= result_reg1; + dout07_result_CU <= result_reg2; + minus1 <= sum - din01_CN_CU_11bit_reg2; + minus2 <= sum - din02_CN_CU_11bit_reg2; + minus3 <= sum - din03_CN_CU_11bit_reg2; + minus4 <= sum - din04_CN_CU_11bit_reg2; + minus5 <= sum - din05_CN_CU_11bit_reg2; + minus6 <= sum - din06_CN_CU_11bit_reg2; + + if(minus1_reg0[10])//限幅前求绝对值操作 + minus1_abs <= ~minus1_reg0 + 11'd1; + else + minus1_abs <= minus1_reg0; + if(minus1_reg1[10]) begin//限幅操作 + if(minus1_abs>11'd127) + dout01_CU <= -8'd127; + else + dout01_CU <= {minus1_reg1[10],minus1_reg1[6:0]}; + // dout01_CU <= minus1_reg1; + end else begin + if(minus1_abs>11'd127) + dout01_CU <= 8'd127; + else + dout01_CU <= {minus1_reg1[10],minus1_reg1[6:0]}; + // dout01_CU <= minus1_reg1; + end + + if(minus2_reg0[10])//限幅前求绝对值操作 + minus2_abs <= ~minus2_reg0 + 11'd1; + else + minus2_abs <= minus2_reg0; + if(minus2_reg1[10]) begin//限幅操作 + if(minus2_abs>11'd127) + dout02_CU <= -8'd127; + else + dout02_CU <= {minus2_reg1[10],minus2_reg1[6:0]}; + // dout02_CU <= minus2_reg1; + end else begin + if(minus2_abs>11'd127) + dout02_CU <= 8'd127; + else + dout02_CU <= {minus2_reg1[10],minus2_reg1[6:0]}; + // dout02_CU <= minus2_reg1; + end + + if(minus3_reg0[10])//限幅前求绝对值操作 + minus3_abs <= ~minus3_reg0 + 11'd1; + else + minus3_abs <= minus3_reg0; + if(minus3_reg1[10]) begin//限幅操作 + if(minus3_abs>11'd127) + dout03_CU <= -8'd127; + else + dout03_CU <= {minus3_reg1[10],minus3_reg1[6:0]}; + // dout03_CU <= minus3_reg1; + end else begin + if(minus3_abs>11'd127) + dout03_CU <= 8'd127; + else + dout03_CU <= {minus3_reg1[10],minus3_reg1[6:0]}; + // dout03_CU <= minus3_reg1; + end + + if(minus4_reg0[10])//限幅前求绝对值操作 + minus4_abs <= ~minus4_reg0 + 11'd1; + else + minus4_abs <= minus4_reg0; + if(minus4_reg1[10]) begin//限幅操作 + if(minus4_abs>11'd127) + dout04_CU <= -8'd127; + else + dout04_CU <= {minus4_reg1[10],minus4_reg1[6:0]}; + // dout04_CU <= minus4_reg1; + end else begin + if(minus4_abs>11'd127) + dout04_CU <= 8'd127; + else + dout04_CU <= {minus4_reg1[10],minus4_reg1[6:0]}; + // dout04_CU <= minus4_reg1; + end + + if(minus5_reg0[10])//限幅前求绝对值操作 + minus5_abs <= ~minus5_reg0 + 11'd1; + else + minus5_abs <= minus5_reg0; + if(minus5_reg1[10]) begin//限幅操作 + if(minus5_abs>11'd127) + dout05_CU <= -8'd127; + else + dout05_CU <= {minus5_reg1[10],minus5_reg1[6:0]}; + // dout05_CU <= minus5_reg1; + end else begin + if(minus5_abs>11'd127) + dout05_CU <= 8'd127; + else + dout05_CU <= {minus5_reg1[10],minus5_reg1[6:0]}; + // dout05_CU <= minus5_reg1; + end + + if(minus6_reg0[10])//限幅前求绝对值操作 + minus6_abs <= ~minus6_reg0 + 11'd1; + else + minus6_abs <= minus6_reg0; + if(minus6_reg1[10]) begin//限幅操作 + if(minus6_abs>11'd127) + dout06_CU <= -8'd127; + else + dout06_CU <= {minus6_reg1[10],minus6_reg1[6:0]}; + // dout06_CU <= minus6_reg1; + end else begin + if(minus6_abs>11'd127) + dout06_CU <= 8'd127; + else + dout06_CU <= {minus6_reg1[10],minus6_reg1[6:0]}; + // dout06_CU <= minus6_reg1; + end + end +endmodule + diff --git a/hdl/VN_PRO.v b/hdl/VN_PRO.v new file mode 100644 index 0000000..11cb552 --- /dev/null +++ b/hdl/VN_PRO.v @@ -0,0 +1,937 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/18 23:18:07 +// Design Name: +// Module Name: VN_PRO +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module VN_PRO + #( + parameter MAX_ITER_NUM = 6'd14, //最大迭代次数 + parameter WIDTH = 4'd8 + ) + ( + input clk, + input rst_VN, + input start_VN, // VN更新启动脉冲 + input start_frame_VN, // VN更新启动脉冲(新的1帧的开始) + + input [WIDTH-1:0] CHNL_dout_01,//信道信息输入 + input [WIDTH-1:0] CHNL_dout_02, + input [WIDTH-1:0] CHNL_dout_03, + input [WIDTH-1:0] CHNL_dout_04, + + //校验节点信息输入，H阵第１行 + input [WIDTH-1:0] CN1_dout_01_00, + input [WIDTH-1:0] CN1_dout_02_00, //后面的00代表H阵原模图的IM + input [WIDTH-1:0] CN1_dout_02_01, //后面的01代表H阵原模图的II1 + + + input [WIDTH-1:0] CN2_dout_01_00, + input [WIDTH-1:0] CN2_dout_02_00, + input [WIDTH-1:0] CN2_dout_03_00, + input [WIDTH-1:0] CN2_dout_04_02, //后面的02代表H阵原模图的II2 + input [WIDTH-1:0] CN2_dout_04_03, //后面的03代表H阵原模图的II3 + input [WIDTH-1:0] CN2_dout_04_04, //后面的04代表H阵原模图的II4 + //校验节点信息输入，H阵第３行 + input [WIDTH-1:0] CN3_dout_01_00, + input [WIDTH-1:0] CN3_dout_02_05, //后面的05代表H阵原模图的II5 + input [WIDTH-1:0] CN3_dout_02_06, //后面的06代表H阵原模图的II6 + input [WIDTH-1:0] CN3_dout_03_07, //后面的07代表H阵原模图的II7 + input [WIDTH-1:0] CN3_dout_03_08, //后面的08代表H阵原模图的II8 + input [WIDTH-1:0] CN3_dout_04_00, + + + output ask_din, //向数据缓存区请求信道数据 + + //校验节点信息读地址，H阵第１行 + output reg [8:0] CN1_addr_rd_01_00=9'd511, + output reg [9:0] CN1_addr_rd_02_00=10'd1023, + output reg [9:0] CN1_addr_rd_02_01=10'd511, + + //校验节点信息读地址，H阵第２行 + output reg [8:0] CN2_addr_rd_01_00=9'd511, + output reg [8:0] CN2_addr_rd_02_00=9'd511, + output reg [8:0] CN2_addr_rd_03_00=9'd511, + output reg [9:0] CN2_addr_rd_04_02=10'd1023, + output reg [9:0] CN2_addr_rd_04_03=10'd511, + output reg [8:0] CN2_addr_rd_04_04=9'd511, + + //校验节点信息读地址，H阵第３行 + output reg [8:0] CN3_addr_rd_01_00=9'd511, + output reg [9:0] CN3_addr_rd_02_05=10'd1023, + output reg [9:0] CN3_addr_rd_02_06=10'd511, + output reg [9:0] CN3_addr_rd_03_07=10'd1023, + output reg [9:0] CN3_addr_rd_03_08=10'd511, + output reg [8:0] CN3_addr_rd_04_00=9'd511, + + //变量节点写使能 + output reg [0:0] VN_wea=1'd0, + + //变量节点写地址，H阵第１行 + output reg [8:0] VN1_addr_wr_01_00=9'd511, + output reg [9:0] VN1_addr_wr_02_00=10'd1023, + output reg [9:0] VN1_addr_wr_02_01=10'd511, + + //变量节点写地址，H阵第２行 + output reg [8:0] VN2_addr_wr_01_00=9'd511, + output reg [8:0] VN2_addr_wr_02_00=9'd511, + output reg [8:0] VN2_addr_wr_03_00=9'd511, + output reg [9:0] VN2_addr_wr_04_02=10'd1023, + output reg [9:0] VN2_addr_wr_04_03=10'd511, + output reg [8:0] VN2_addr_wr_04_04=9'd511, + + //变量节点写地址，H阵第３行 + output reg [8:0] VN3_addr_wr_01_00=9'd511, + output reg [9:0] VN3_addr_wr_02_05=10'd1023, + output reg [9:0] VN3_addr_wr_02_06=10'd511, + output reg [9:0] VN3_addr_wr_03_07=10'd1023, + output reg [9:0] VN3_addr_wr_03_08=10'd511, + output reg [8:0] VN3_addr_wr_04_00=9'd511, + + + //变量节点写数据，H阵第１行 + output reg [WIDTH-1:0] VN1_din_01_00=8'd0, + output reg [WIDTH-1:0] VN1_din_02_00=8'd0, + output reg [WIDTH-1:0] VN1_din_02_01=8'd0, + + //变量节点写数据，H阵第２行 + output reg [WIDTH-1:0] VN2_din_01_00=8'd0, + output reg [WIDTH-1:0] VN2_din_02_00=8'd0, + output reg [WIDTH-1:0] VN2_din_03_00=8'd0, + output reg [WIDTH-1:0] VN2_din_04_02=8'd0, + output reg [WIDTH-1:0] VN2_din_04_03=8'd0, + output reg [WIDTH-1:0] VN2_din_04_04=8'd0, + + //变量节点写数据，H阵第３行 + output reg [WIDTH-1:0] VN3_din_01_00=8'd0, + output reg [WIDTH-1:0] VN3_din_02_05=8'd0, + output reg [WIDTH-1:0] VN3_din_02_06=8'd0, + output reg [WIDTH-1:0] VN3_din_03_07=8'd0, + output reg [WIDTH-1:0] VN3_din_03_08=8'd0, + output reg [WIDTH-1:0] VN3_din_04_00=8'd0, + + //判决结果写使能 + output reg [0:0] DR_wea=8'd0, + + //判决结果写地址 + output reg [8:0] DR_addr_wr=9'd511, + + output reg [0:0] DR_din_01=1'd0, //判决结果写数据 + output reg [0:0] DR_din_02=1'd0, + output reg [0:0] DR_din_03=1'd0, + output reg [0:0] DR_din_04=1'd0, + output reg [0:0] DR_din_05=1'd0, + + + output data_start_ck_VN, //产生判决结果数据开始存储标志，高脉冲 + output data_start_VN, //产生判决结果数据可以输出标志，高脉冲 + output end_VN //模块结束标志，高脉冲 + ); + + assign ask_din = (rst_VN) ? 1'd0 : ((start_VN) ? 1'd1:1'd0); + + reg [5:0] iter_num = 6'd0; + // 迭代次数控制 + always @ (posedge clk) begin + if (rst_VN || start_frame_VN) begin + iter_num <= 6'd0; + end else begin + if(end_VN) + if (iter_num < MAX_ITER_NUM) + iter_num <= iter_num + 6'd1; + else + iter_num <= iter_num; + else + iter_num <= iter_num; + end + end + + reg [10:0] cnt_VN= 11'd0,cnt_2_VN= 11'd0; + reg flag_VN=1'd0; + // 产生该模块的计数基准 + always @ (posedge clk) begin + if(rst_VN) begin + cnt_VN <= 11'd0; + cnt_2_VN <= 11'd0; + flag_VN <= 1'b0; + end else begin + if(start_VN) begin + flag_VN <= 1'b1; + cnt_VN <= 11'd0; + cnt_2_VN <= 11'd0; + end else begin + if(flag_VN) begin + if(cnt_VN<11'd560)begin + flag_VN <= flag_VN; + cnt_VN <= cnt_VN + 11'd1; + end else begin + cnt_VN <= cnt_VN; + flag_VN<= 1'b0; + end + if(cnt_2_VN<11'd560)begin + flag_VN <= flag_VN; + cnt_2_VN <= cnt_2_VN + 11'd1; + end else begin + cnt_2_VN <= cnt_2_VN; + flag_VN<= 1'b0; + end + end else begin + cnt_VN <= cnt_VN; + cnt_2_VN <= cnt_2_VN; + end + end + end + end + + parameter DELAY_RD = 11'd3; + + // 对所有IM进行CN地址操作 + always @ (posedge clk) begin + if (rst_VN) begin + CN1_addr_rd_01_00 <= 9'd511; + CN1_addr_rd_02_00 <= 10'd1023; + CN2_addr_rd_01_00 <= 9'd511; + CN2_addr_rd_02_00 <= 9'd511; + CN2_addr_rd_03_00 <= 9'd511; + CN3_addr_rd_01_00 <= 9'd511; + CN3_addr_rd_04_00 <= 9'd511; + end else begin + if (cnt_VN >= 11'd1 + DELAY_RD && cnt_VN <= 11'd512 + DELAY_RD) begin + CN1_addr_rd_01_00 <= CN1_addr_rd_01_00 + 9'd1; + CN1_addr_rd_02_00 <= CN1_addr_rd_02_00 + 10'd1; + CN2_addr_rd_01_00 <= CN2_addr_rd_01_00 + 9'd1; + CN2_addr_rd_02_00 <= CN2_addr_rd_02_00 + 9'd1; + CN2_addr_rd_03_00 <= CN2_addr_rd_03_00 + 9'd1; + CN3_addr_rd_01_00 <= CN3_addr_rd_01_00 + 9'd1; + CN3_addr_rd_04_00 <= CN3_addr_rd_04_00 + 9'd1; + end else begin + CN1_addr_rd_01_00 <= 9'd511; + CN1_addr_rd_02_00 <= 10'd1023; + CN2_addr_rd_01_00 <= 9'd511; + CN2_addr_rd_02_00 <= 9'd511; + CN2_addr_rd_03_00 <= 9'd511; + CN3_addr_rd_01_00 <= 9'd511; + CN3_addr_rd_04_00 <= 9'd511; + end + end + end + + reg first_flag_cn_01=1'd1,first_flag_cn_02=1'd1,first_flag_cn_03=1'd1,first_flag_cn_04=1'd1; + reg first_flag_cn_05=1'd1,first_flag_cn_06=1'd1,first_flag_cn_07=1'd1,first_flag_cn_08=1'd1; + reg first_flag_vn_01=1'd1,first_flag_vn_02=1'd1,first_flag_vn_03=1'd1,first_flag_vn_04=1'd1; + reg first_flag_vn_05=1'd1,first_flag_vn_06=1'd1,first_flag_vn_07=1'd1,first_flag_vn_08=1'd1; + + // 对II1-II8进行CN地址操作 + always @ (posedge clk) begin + if (rst_VN) begin + CN1_addr_rd_02_01 <= 10'd639; + CN2_addr_rd_04_02 <= 10'd24; + CN2_addr_rd_04_03 <= 10'd926; + CN2_addr_rd_04_04 <= 9'd294; + CN3_addr_rd_02_05 <= 10'd352; + CN3_addr_rd_02_06 <= 10'd639; + CN3_addr_rd_03_07 <= 10'd12; + CN3_addr_rd_03_08 <= 10'd929; + first_flag_cn_01 <= 1'd1; + first_flag_cn_02 <= 1'd1; + first_flag_cn_03 <= 1'd1; + first_flag_cn_04 <= 1'd1; + first_flag_cn_05 <= 1'd1; + first_flag_cn_06 <= 1'd1; + first_flag_cn_07 <= 1'd1; + first_flag_cn_08 <= 1'd1; + end else begin + if (cnt_VN >= 11'd1 + DELAY_RD && cnt_VN <= 11'd512 + DELAY_RD) begin + //对II1地址进行操作，确保初始化地址先加1 + if (first_flag_cn_05) begin + CN1_addr_rd_02_01 <= CN1_addr_rd_02_01 + 10'd1; + first_flag_cn_05 <= 1'd0; + end else begin + if (CN1_addr_rd_02_01 == 10'd1023) + CN1_addr_rd_02_01 <= 10'd624; + else if (CN1_addr_rd_02_01 == 10'd639) + CN1_addr_rd_02_01 <= 10'd512; + else + CN1_addr_rd_02_01 <= CN1_addr_rd_02_01 + 10'd1; + end + // 对II2地址进行操作 + if (first_flag_cn_06) begin + CN2_addr_rd_04_02 <= CN2_addr_rd_04_02 + 10'd1; + first_flag_cn_06<= 1'd0; + end else begin + if (CN2_addr_rd_04_02 == 10'd127) + CN2_addr_rd_04_02 <= 10'd0; + else if (CN2_addr_rd_04_02 == 10'd24) + CN2_addr_rd_04_02 <= 10'd203; + else if (CN2_addr_rd_04_02 == 10'd255) + CN2_addr_rd_04_02 <= 10'd128; + else if (CN2_addr_rd_04_02 == 10'd202) + CN2_addr_rd_04_02 <= 10'd376; + else if (CN2_addr_rd_04_02 == 10'd383) + CN2_addr_rd_04_02 <= 10'd256; + else if (CN2_addr_rd_04_02 == 10'd375) + CN2_addr_rd_04_02 <= 10'd477; + else if (CN2_addr_rd_04_02 == 10'd511) + CN2_addr_rd_04_02 <= 10'd384; + else + CN2_addr_rd_04_02 <= CN2_addr_rd_04_02 + 10'd1; + end + // 对II3地址进行操作 + if (first_flag_cn_07) begin + CN2_addr_rd_04_03 <= CN2_addr_rd_04_03 + 10'd1; + first_flag_cn_07 <= 1'd0; + end else begin + if (CN2_addr_rd_04_03 == 10'd1023) + CN2_addr_rd_04_03 <= 10'd896; + else if (CN2_addr_rd_04_03 == 10'd926) + CN2_addr_rd_04_03 <= 10'd535; + else if (CN2_addr_rd_04_03 == 10'd639) + CN2_addr_rd_04_03 <= 10'd512; + else if (CN2_addr_rd_04_03 == 10'd534) + CN2_addr_rd_04_03 <= 10'd694; + else if (CN2_addr_rd_04_03 == 10'd767) + CN2_addr_rd_04_03 <= 10'd640; + else if (CN2_addr_rd_04_03 == 10'd693) + CN2_addr_rd_04_03 <= 10'd777; + else if (CN2_addr_rd_04_03 == 10'd895) + CN2_addr_rd_04_03 <= 10'd768; + else + CN2_addr_rd_04_03 <= CN2_addr_rd_04_03 + 10'd1; + end + // 对II4地址进行操作 + if (first_flag_cn_08) begin + CN2_addr_rd_04_04 <= CN2_addr_rd_04_04 + 9'd1; + first_flag_cn_08 <= 1'd0; + end else begin + if (CN2_addr_rd_04_04 == 9'd383) + CN2_addr_rd_04_04 <= 9'd256; + else if (CN2_addr_rd_04_04 == 9'd294) + CN2_addr_rd_04_04 <= 9'd400; + else if (CN2_addr_rd_04_04 == 9'd511) + CN2_addr_rd_04_04 <= 9'd384; + else if (CN2_addr_rd_04_04 == 9'd399) + CN2_addr_rd_04_04 <= 9'd0; + else if (CN2_addr_rd_04_04 == 9'd127) + CN2_addr_rd_04_04 <= 9'd211; + else if (CN2_addr_rd_04_04 == 9'd255) + CN2_addr_rd_04_04 <= 9'd128; + else + CN2_addr_rd_04_04 <= CN2_addr_rd_04_04 + 9'd1; + end + // 对II5地址进行操作 + if (first_flag_cn_01) begin //确保初始化地址先加1 + CN3_addr_rd_02_05 <= CN3_addr_rd_02_05 + 10'd1; + first_flag_cn_01 <= 1'd0; + end else begin + if (CN3_addr_rd_02_05 == 10'd383) + CN3_addr_rd_02_05 <= 10'd256; + else if (CN3_addr_rd_02_05 == 10'd352) + CN3_addr_rd_02_05 <= 10'd448; + else if (CN3_addr_rd_02_05 == 10'd511) + CN3_addr_rd_02_05 <= 10'd384; + else if (CN3_addr_rd_02_05 == 10'd447) + CN3_addr_rd_02_05 <= 10'd78; + else if (CN3_addr_rd_02_05 == 10'd127) + CN3_addr_rd_02_05 <= 10'd0; + else if (CN3_addr_rd_02_05 == 10'd77) + CN3_addr_rd_02_05 <= 10'd209; + else if (CN3_addr_rd_02_05 == 10'd255) + CN3_addr_rd_02_05 <= 10'd128; + else + CN3_addr_rd_02_05 <= CN3_addr_rd_02_05 + 10'd1; + end + // 对II6地址进行操作 + if (first_flag_cn_02) begin + CN3_addr_rd_02_06 <= CN3_addr_rd_02_06 + 10'd1; + first_flag_cn_02 <= 1'd0; + end else begin + if (CN3_addr_rd_02_06 == 10'd767) + CN3_addr_rd_02_06 <= 10'd774; + else if (CN3_addr_rd_02_06 == 10'd895) + CN3_addr_rd_02_06 <= 10'd768; + else if (CN3_addr_rd_02_06 == 10'd773) + CN3_addr_rd_02_06 <= 10'd931; + else if (CN3_addr_rd_02_06 == 10'd1023) + CN3_addr_rd_02_06 <= 10'd896; + else if (CN3_addr_rd_02_06 == 10'd930) + CN3_addr_rd_02_06 <= 10'd611; + else if (CN3_addr_rd_02_06 == 10'd639) + CN3_addr_rd_02_06 <= 10'd512; + else + CN3_addr_rd_02_06 <= CN3_addr_rd_02_06 + 10'd1; + end + // 对II7地址进行操作 + if (first_flag_cn_03) begin //确保初始化地址先加1 + CN3_addr_rd_03_07 <= CN3_addr_rd_03_07 + 10'd1; + first_flag_cn_03 <= 1'd0; + end else begin + if (CN3_addr_rd_03_07 == 10'd127) + CN3_addr_rd_03_07 <= 10'd0; + else if (CN3_addr_rd_03_07 == 10'd12) + CN3_addr_rd_03_07 <= 10'd197; + else if (CN3_addr_rd_03_07 == 10'd255) + CN3_addr_rd_03_07 <= 10'd128; + else if (CN3_addr_rd_03_07 == 10'd196) + CN3_addr_rd_03_07 <= 10'd383; + else if (CN3_addr_rd_03_07 == 10'd383) + CN3_addr_rd_03_07 <= 10'd256; + else if (CN3_addr_rd_03_07 == 10'd382) + CN3_addr_rd_03_07 <= 10'd413; + else if (CN3_addr_rd_03_07 == 10'd511) + CN3_addr_rd_03_07 <= 10'd384; + else + CN3_addr_rd_03_07 <= CN3_addr_rd_03_07 + 10'd1; + end + // 对II8地址进行操作 + if (first_flag_cn_04) begin + CN3_addr_rd_03_08 <= CN3_addr_rd_03_08 + 10'd1; + first_flag_cn_04 <= 1'd0; + end else begin + if (CN3_addr_rd_03_08 == 10'd1023) + CN3_addr_rd_03_08 <= 10'd896; + else if (CN3_addr_rd_03_08 == 10'd929) + CN3_addr_rd_03_08 <= 10'd610; + else if (CN3_addr_rd_03_08 == 10'd639) + CN3_addr_rd_03_08 <= 10'd512; + else if (CN3_addr_rd_03_08 == 10'd609) + CN3_addr_rd_03_08 <= 10'd666; + else if (CN3_addr_rd_03_08 == 10'd767) + CN3_addr_rd_03_08 <= 10'd640; + else if (CN3_addr_rd_03_08 == 10'd665) + CN3_addr_rd_03_08 <= 10'd827; + else if (CN3_addr_rd_03_08 == 10'd895) + CN3_addr_rd_03_08 <= 10'd768; + else + CN3_addr_rd_03_08 <= CN3_addr_rd_03_08 + 10'd1; + end + end else begin + CN1_addr_rd_02_01 <= 10'd639; + CN2_addr_rd_04_02 <= 10'd24; + CN2_addr_rd_04_03 <= 10'd926; + CN2_addr_rd_04_04 <= 9'd294; + CN3_addr_rd_02_05 <= 10'd352; + CN3_addr_rd_02_06 <= 10'd639; + CN3_addr_rd_03_07 <= 10'd12; + CN3_addr_rd_03_08 <= 10'd929; + first_flag_cn_01 <= 1'd1; + first_flag_cn_02 <= 1'd1; + first_flag_cn_03 <= 1'd1; + first_flag_cn_04 <= 1'd1; + first_flag_cn_05 <= 1'd1; + first_flag_cn_06 <= 1'd1; + first_flag_cn_07 <= 1'd1; + first_flag_cn_08 <= 1'd1; + end + end + end + + wire [WIDTH-1:0] din01_CN_CU01; //第1列更新处理单元信号定义 + wire [WIDTH-1:0] din02_CN_CU01; + wire [WIDTH-1:0] din03_CHNL_CU01; + wire [WIDTH-1:0] dout01_CU01; + wire [WIDTH-1:0] dout02_CU01; + wire [0:0] dout03_result_CU01; + + wire [WIDTH-1:0] din01_CN_CU02; //第2列更新处理单元信号定义 + wire [WIDTH-1:0] din02_CN_CU02; + wire [WIDTH-1:0] din03_CN_CU02; + wire [WIDTH-1:0] din04_CHNL_CU02; + wire [WIDTH-1:0] dout01_CU02; + wire [WIDTH-1:0] dout02_CU02; + wire [WIDTH-1:0] dout03_CU02; + wire [0:0] dout04_result_CU02; + + wire [WIDTH-1:0] din01_CN_CU03; //第3列更新处理单元信号定义 + wire [WIDTH-1:0] din02_CHNL_CU03; + wire [WIDTH-1:0] dout01_CU03; + wire [0:0] dout02_result_CU03; + + wire [WIDTH-1:0] din01_CN_CU04; //第4列更新处理单元信号定义 + wire [WIDTH-1:0] din02_CN_CU04; + wire [WIDTH-1:0] din03_CN_CU04; + wire [WIDTH-1:0] din04_CHNL_CU04; + wire [WIDTH-1:0] dout01_CU04; + wire [WIDTH-1:0] dout02_CU04; + wire [WIDTH-1:0] dout03_CU04; + wire [0:0] dout04_result_CU04; + + wire [WIDTH-1:0] din01_CN_CU05; //第5列更新处理单元信号定义 + wire [WIDTH-1:0] din02_CN_CU05; + wire [WIDTH-1:0] din03_CN_CU05; + wire [WIDTH-1:0] din04_CN_CU05; + wire [WIDTH-1:0] din05_CN_CU05; + wire [WIDTH-1:0] din06_CN_CU05; + wire [WIDTH-1:0] din07_CHNL_CU05; + wire [WIDTH-1:0] dout01_CU05; + wire [WIDTH-1:0] dout02_CU05; + wire [WIDTH-1:0] dout03_CU05; + wire [WIDTH-1:0] dout04_CU05; + wire [WIDTH-1:0] dout05_CU05; + wire [WIDTH-1:0] dout06_CU05; + wire [0:0] dout07_result_CU05; + + // CU模块的输入 + assign din01_CN_CU01 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_01_00; + assign din02_CN_CU01 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_01_00; + + assign din01_CN_CU02 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_02_00; + assign din02_CN_CU02 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_02_05; + assign din03_CN_CU02 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_02_06; + + assign din01_CN_CU03 = (iter_num == 6'd0) ? 8'd0 : CN1_dout_01_00; + + assign din01_CN_CU04 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_03_00; + assign din02_CN_CU04 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_03_07; + assign din03_CN_CU04 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_03_08; + + assign din01_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN1_dout_02_00; + assign din02_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN1_dout_02_01; + assign din03_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_04_02; + assign din04_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_04_03; + assign din05_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_04_04; + assign din06_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_04_00; + + assign din03_CHNL_CU01 = CHNL_dout_01; + assign din04_CHNL_CU02 = CHNL_dout_02; + assign din02_CHNL_CU03 = CHNL_dout_03; + assign din04_CHNL_CU04 = CHNL_dout_04; + assign din07_CHNL_CU05 = 8'd0; //信道传输的数据只有2048bit，这里H矩阵是2560bit，所以在后512位上补0 + + + + VNU_2din CU_01 ( + .clk(clk), + .din01_CN_CU(din01_CN_CU01), + .din02_CN_CU(din02_CN_CU01), + .din03_CHNL_CU(din03_CHNL_CU01), + .dout01_CU(dout01_CU01), + .dout02_CU(dout02_CU01), + .dout03_result_CU(dout03_result_CU01)); + + VNU_3din CU_02 ( + .clk(clk), + .din01_CN_CU(din01_CN_CU02), + .din02_CN_CU(din02_CN_CU02), + .din03_CN_CU(din03_CN_CU02), + .din04_CHNL_CU(din04_CHNL_CU02), + .dout01_CU(dout01_CU02), + .dout02_CU(dout02_CU02), + .dout03_CU(dout03_CU02), + .dout04_result_CU(dout04_result_CU02) + ); + + VNU_1din CU_03 (.clk(clk), + .din01_CN_CU(din01_CN_CU03), + .din02_CHNL_CU(din02_CHNL_CU03), + .dout01_CU(dout01_CU03), + .dout02_result_CU(dout02_result_CU03)); + + VNU_3din CU_04 ( + .clk(clk), + .din01_CN_CU(din01_CN_CU04), + .din02_CN_CU(din02_CN_CU04), + .din03_CN_CU(din03_CN_CU04), + .din04_CHNL_CU(din04_CHNL_CU04), + .dout01_CU(dout01_CU04), + .dout02_CU(dout02_CU04), + .dout03_CU(dout03_CU04), + .dout04_result_CU(dout04_result_CU04) + ); + + VNU_6din CU_05 ( + .clk(clk), + .din01_CN_CU(din01_CN_CU05), + .din02_CN_CU(din02_CN_CU05), + .din03_CN_CU(din03_CN_CU05), + .din04_CN_CU(din04_CN_CU05), + .din05_CN_CU(din05_CN_CU05), + .din06_CN_CU(din06_CN_CU05), + .din07_CHNL_CU(din07_CHNL_CU05), + .dout01_CU(dout01_CU05), + .dout02_CU(dout02_CU05), + .dout03_CU(dout03_CU05), + .dout04_CU(dout04_CU05), + .dout05_CU(dout05_CU05), + .dout06_CU(dout06_CU05), + .dout07_result_CU(dout07_result_CU05) + ); + + + // 设置写操作的时延 + parameter DELAY_WR = 11'd17; + + // 控制VN的写使能 + always @ (posedge clk) begin + if(rst_VN) begin + VN_wea <= 1'd0; + end else begin + if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) + VN_wea <= 1'd1; + else + VN_wea <= 1'd0; + end + end + + // 控制VN存储的写地址(所有IM) + always @ (posedge clk) begin + if (rst_VN) begin + VN1_addr_wr_01_00 <= 9'd511; + VN1_addr_wr_02_00 <= 10'd1023; + VN2_addr_wr_01_00 <= 9'd511; + VN2_addr_wr_02_00 <= 9'd511; + VN2_addr_wr_03_00 <= 9'd511; + VN3_addr_wr_01_00 <= 9'd511; + VN3_addr_wr_04_00 <= 9'd511; + end else begin + if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin + VN1_addr_wr_01_00 <= VN1_addr_wr_01_00 + 9'd1; + VN1_addr_wr_02_00 <= VN1_addr_wr_02_00 + 10'd1; + VN2_addr_wr_01_00 <= VN2_addr_wr_01_00 + 9'd1; + VN2_addr_wr_02_00 <= VN2_addr_wr_02_00 + 9'd1; + VN2_addr_wr_03_00 <= VN2_addr_wr_03_00 + 9'd1; + VN3_addr_wr_01_00 <= VN3_addr_wr_01_00 + 9'd1; + VN3_addr_wr_04_00 <= VN3_addr_wr_04_00 + 9'd1; + end else begin + VN1_addr_wr_01_00 <= 9'd511; + VN1_addr_wr_02_00 <= 10'd1023; + VN2_addr_wr_01_00 <= 9'd511; + VN2_addr_wr_02_00 <= 9'd511; + VN2_addr_wr_03_00 <= 9'd511; + VN3_addr_wr_01_00 <= 9'd511; + VN3_addr_wr_04_00 <= 9'd511; + end + end + end + + // 控制VN存储的写地址(II1-II8) + always @ (posedge clk) begin + if (rst_VN) begin + VN1_addr_wr_02_01 <= 10'd639; + VN2_addr_wr_04_02 <= 10'd24; + VN2_addr_wr_04_03 <= 10'd926; + VN2_addr_wr_04_04 <= 9'd294; + VN3_addr_wr_02_05 <= 10'd352; + VN3_addr_wr_02_06 <= 10'd639; + VN3_addr_wr_03_07 <= 10'd12; + VN3_addr_wr_03_08 <= 10'd929; + first_flag_vn_01 <= 1'd1; + first_flag_vn_02 <= 1'd1; + first_flag_vn_03 <= 1'd1; + first_flag_vn_04 <= 1'd1; + first_flag_vn_05 <= 1'd1; + first_flag_vn_06 <= 1'd1; + first_flag_vn_07 <= 1'd1; + first_flag_vn_08 <= 1'd1; + end else begin + if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin + //对II1地址进行操作，确保初始化地址先加1 + if (first_flag_vn_05) begin + VN1_addr_wr_02_01 <= VN1_addr_wr_02_01 + 10'd1; + first_flag_vn_05 <= 1'd0; + end else begin + if (VN1_addr_wr_02_01 == 10'd1023) + VN1_addr_wr_02_01 <= 10'd624; + else if (VN1_addr_wr_02_01 == 10'd639) + VN1_addr_wr_02_01 <= 10'd512; + else + VN1_addr_wr_02_01 <= VN1_addr_wr_02_01 + 10'd1; + end + // 对II2地址进行操作 + if (first_flag_vn_06) begin + VN2_addr_wr_04_02 <= VN2_addr_wr_04_02 + 10'd1; + first_flag_vn_06<= 1'd0; + end else begin + if (VN2_addr_wr_04_02 == 10'd127) + VN2_addr_wr_04_02 <= 10'd0; + else if (VN2_addr_wr_04_02 == 10'd24) + VN2_addr_wr_04_02 <= 10'd203; + else if (VN2_addr_wr_04_02 == 10'd255) + VN2_addr_wr_04_02 <= 10'd128; + else if (VN2_addr_wr_04_02 == 10'd202) + VN2_addr_wr_04_02 <= 10'd376; + else if (VN2_addr_wr_04_02 == 10'd383) + VN2_addr_wr_04_02 <= 10'd256; + else if (VN2_addr_wr_04_02 == 10'd375) + VN2_addr_wr_04_02 <= 10'd477; + else if (VN2_addr_wr_04_02 == 10'd511) + VN2_addr_wr_04_02 <= 10'd384; + else + VN2_addr_wr_04_02 <= VN2_addr_wr_04_02 + 10'd1; + end + // 对II3地址进行操作 + if (first_flag_vn_07) begin + VN2_addr_wr_04_03 <= VN2_addr_wr_04_03 + 10'd1; + first_flag_vn_07 <= 1'd0; + end else begin + if (VN2_addr_wr_04_03 == 10'd1023) + VN2_addr_wr_04_03 <= 10'd896; + else if (VN2_addr_wr_04_03 == 10'd926) + VN2_addr_wr_04_03 <= 10'd535; + else if (VN2_addr_wr_04_03 == 10'd639) + VN2_addr_wr_04_03 <= 10'd512; + else if (VN2_addr_wr_04_03 == 10'd534) + VN2_addr_wr_04_03 <= 10'd694; + else if (VN2_addr_wr_04_03 == 10'd767) + VN2_addr_wr_04_03 <= 10'd640; + else if (VN2_addr_wr_04_03 == 10'd693) + VN2_addr_wr_04_03 <= 10'd777; + else if (VN2_addr_wr_04_03 == 10'd895) + VN2_addr_wr_04_03 <= 10'd768; + else + VN2_addr_wr_04_03 <= VN2_addr_wr_04_03 + 10'd1; + end + // 对II4地址进行操作 + if (first_flag_vn_08) begin + VN2_addr_wr_04_04 <= VN2_addr_wr_04_04 + 9'd1; + first_flag_vn_08 <= 1'd0; + end else begin + if (VN2_addr_wr_04_04 == 9'd383) + VN2_addr_wr_04_04 <= 9'd256; + else if (VN2_addr_wr_04_04 == 9'd294) + VN2_addr_wr_04_04 <= 9'd400; + else if (VN2_addr_wr_04_04 == 9'd511) + VN2_addr_wr_04_04 <= 9'd384; + else if (VN2_addr_wr_04_04 == 9'd399) + VN2_addr_wr_04_04 <= 9'd0; + else if (VN2_addr_wr_04_04 == 9'd127) + VN2_addr_wr_04_04 <= 9'd211; + else if (VN2_addr_wr_04_04 == 9'd255) + VN2_addr_wr_04_04 <= 9'd128; + else + VN2_addr_wr_04_04 <= VN2_addr_wr_04_04 + 9'd1; + end + // 对II5地址进行操作 + if (first_flag_vn_01) begin //确保初始化地址先加1 + VN3_addr_wr_02_05 <= VN3_addr_wr_02_05 + 10'd1; + first_flag_vn_01 <= 1'd0; + end else begin + if (VN3_addr_wr_02_05 == 10'd383) + VN3_addr_wr_02_05 <= 10'd256; + else if (VN3_addr_wr_02_05 == 10'd352) + VN3_addr_wr_02_05 <= 10'd448; + else if (VN3_addr_wr_02_05 == 10'd511) + VN3_addr_wr_02_05 <= 10'd384; + else if (VN3_addr_wr_02_05 == 10'd447) + VN3_addr_wr_02_05 <= 10'd78; + else if (VN3_addr_wr_02_05 == 10'd127) + VN3_addr_wr_02_05 <= 10'd0; + else if (VN3_addr_wr_02_05 == 10'd77) + VN3_addr_wr_02_05 <= 10'd209; + else if (VN3_addr_wr_02_05 == 10'd255) + VN3_addr_wr_02_05 <= 10'd128; + else + VN3_addr_wr_02_05 <= VN3_addr_wr_02_05 + 10'd1; + end + // 对II6地址进行操作 + if (first_flag_vn_02) begin + VN3_addr_wr_02_06 <= VN3_addr_wr_02_06 + 10'd1; + first_flag_vn_02 <= 1'd0; + end else begin + if (VN3_addr_wr_02_06 == 10'd767) + VN3_addr_wr_02_06 <= 10'd774; + else if (VN3_addr_wr_02_06 == 10'd895) + VN3_addr_wr_02_06 <= 10'd768; + else if (VN3_addr_wr_02_06 == 10'd773) + VN3_addr_wr_02_06 <= 10'd931; + else if (VN3_addr_wr_02_06 == 10'd1023) + VN3_addr_wr_02_06 <= 10'd896; + else if (VN3_addr_wr_02_06 == 10'd930) + VN3_addr_wr_02_06 <= 10'd611; + else if (VN3_addr_wr_02_06 == 10'd639) + VN3_addr_wr_02_06 <= 10'd512; + else + VN3_addr_wr_02_06 <= VN3_addr_wr_02_06 + 10'd1; + end + // 对II7地址进行操作 + if (first_flag_vn_03) begin //确保初始化地址先加1 + VN3_addr_wr_03_07 <= VN3_addr_wr_03_07 + 10'd1; + first_flag_vn_03 <= 1'd0; + end else begin + if (VN3_addr_wr_03_07 == 10'd127) + VN3_addr_wr_03_07 <= 10'd0; + else if (VN3_addr_wr_03_07 == 10'd12) + VN3_addr_wr_03_07 <= 10'd197; + else if (VN3_addr_wr_03_07 == 10'd255) + VN3_addr_wr_03_07 <= 10'd128; + else if (VN3_addr_wr_03_07 == 10'd196) + VN3_addr_wr_03_07 <= 10'd383; + else if (VN3_addr_wr_03_07 == 10'd383) + VN3_addr_wr_03_07 <= 10'd256; + else if (VN3_addr_wr_03_07 == 10'd382) + VN3_addr_wr_03_07 <= 10'd413; + else if (VN3_addr_wr_03_07 == 10'd511) + VN3_addr_wr_03_07 <= 10'd384; + else + VN3_addr_wr_03_07 <= VN3_addr_wr_03_07 + 10'd1; + end + // 对II8地址进行操作 + if (first_flag_vn_04) begin + VN3_addr_wr_03_08 <= VN3_addr_wr_03_08 + 10'd1; + first_flag_vn_04 <= 1'd0; + end else begin + if (VN3_addr_wr_03_08 == 10'd1023) + VN3_addr_wr_03_08 <= 10'd896; + else if (VN3_addr_wr_03_08 == 10'd929) + VN3_addr_wr_03_08 <= 10'd610; + else if (VN3_addr_wr_03_08 == 10'd639) + VN3_addr_wr_03_08 <= 10'd512; + else if (VN3_addr_wr_03_08 == 10'd609) + VN3_addr_wr_03_08 <= 10'd666; + else if (VN3_addr_wr_03_08 == 10'd767) + VN3_addr_wr_03_08 <= 10'd640; + else if (VN3_addr_wr_03_08 == 10'd665) + VN3_addr_wr_03_08 <= 10'd827; + else if (VN3_addr_wr_03_08 == 10'd895) + VN3_addr_wr_03_08 <= 10'd768; + else + VN3_addr_wr_03_08 <= VN3_addr_wr_03_08 + 10'd1; + end + end else begin + VN1_addr_wr_02_01 <= 10'd639; + VN2_addr_wr_04_02 <= 10'd24; + VN2_addr_wr_04_03 <= 10'd926; + VN2_addr_wr_04_04 <= 9'd294; + VN3_addr_wr_02_05 <= 10'd352; + VN3_addr_wr_02_06 <= 10'd639; + VN3_addr_wr_03_07 <= 10'd12; + VN3_addr_wr_03_08 <= 10'd929; + first_flag_vn_01 <= 1'd1; + first_flag_vn_02 <= 1'd1; + first_flag_vn_03 <= 1'd1; + first_flag_vn_04 <= 1'd1; + first_flag_vn_05 <= 1'd1; + first_flag_vn_06 <= 1'd1; + first_flag_vn_07 <= 1'd1; + first_flag_vn_08 <= 1'd1; + end + end + end + + // 控制VN的写数据 + always @ (posedge clk) begin + if (rst_VN) begin + VN1_din_01_00 <= 8'd0; + VN1_din_02_00 <= 8'd0; + VN2_din_01_00 <= 8'd0; + VN2_din_02_00 <= 8'd0; + VN2_din_03_00 <= 8'd0; + VN3_din_01_00 <= 8'd0; + VN3_din_04_00 <= 8'd0; + VN1_din_02_01 <= 8'd0; + VN2_din_04_02 <= 8'd0; + VN2_din_04_03 <= 8'd0; + VN2_din_04_04 <= 8'd0; + VN3_din_02_05 <= 8'd0; + VN3_din_02_06 <= 8'd0; + VN3_din_03_07 <= 8'd0; + VN3_din_03_08 <= 8'd0; + end else begin + if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin + VN1_din_01_00 <= dout01_CU03; + VN1_din_02_00 <= dout01_CU05; + VN2_din_01_00 <= dout01_CU01; + VN2_din_02_00 <= dout01_CU02; + VN2_din_03_00 <= dout01_CU04; + VN3_din_01_00 <= dout02_CU01; + VN3_din_04_00 <= dout06_CU05; + VN1_din_02_01 <= dout02_CU05; + VN2_din_04_02 <= dout03_CU05; + VN2_din_04_03 <= dout04_CU05; + VN2_din_04_04 <= dout05_CU05; + VN3_din_02_05 <= dout02_CU02; + VN3_din_02_06 <= dout03_CU02; + VN3_din_03_07 <= dout02_CU04; + VN3_din_03_08 <= dout03_CU04; + end else begin + VN1_din_01_00 <= 8'd0; + VN1_din_02_00 <= 8'd0; + VN2_din_01_00 <= 8'd0; + VN2_din_02_00 <= 8'd0; + VN2_din_03_00 <= 8'd0; + VN3_din_01_00 <= 8'd0; + VN3_din_04_00 <= 8'd0; + VN1_din_02_01 <= 8'd0; + VN2_din_04_02 <= 8'd0; + VN2_din_04_03 <= 8'd0; + VN2_din_04_04 <= 8'd0; + VN3_din_02_05 <= 8'd0; + VN3_din_02_06 <= 8'd0; + VN3_din_03_07 <= 8'd0; + VN3_din_03_08 <= 8'd0; + end + end + end + + // 控制DR的写使能 + always @ (posedge clk) begin + if(rst_VN) begin + DR_wea <= 1'd0; + end else begin + if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR && iter_num == MAX_ITER_NUM - 1) + // 对写全能用迭代次数进行限制，防止输出译码结果时有新的数据写入 + DR_wea <= 1'd1; + else + DR_wea <= 1'd0; + end + end + + // 控制DR存储的写地址 + always @ (posedge clk) begin + if (rst_VN) begin + DR_addr_wr <= 9'd511; + end else begin + if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) + DR_addr_wr <= DR_addr_wr + 9'd1; + else + DR_addr_wr <= 9'd511; + end + end + + // 控制DR存储的写数据 + always @ (posedge clk) begin + if (rst_VN) begin + DR_din_01 <= 1'd0; + DR_din_02 <= 1'd0; + DR_din_03 <= 1'd0; + DR_din_04 <= 1'd0; + DR_din_05 <= 1'd0; + end else begin + if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin + DR_din_01 <= dout03_result_CU01; + DR_din_02 <= dout04_result_CU02; + DR_din_03 <= dout02_result_CU03; + DR_din_04 <= dout04_result_CU04; + DR_din_05 <= dout07_result_CU05; + end else begin + DR_din_01 <= 1'd0; + DR_din_02 <= 1'd0; + DR_din_03 <= 1'd0; + DR_din_04 <= 1'd0; + DR_din_05 <= 1'd0; + end + end + end + + //状态指示 + assign data_start_ck_VN = (cnt_VN == 11'd1 + DELAY_WR - 11'd1 && iter_num == MAX_ITER_NUM - 1) ? 1'd1 : 1'd0; + assign data_start_VN = (cnt_VN == 11'd512 + DELAY_WR + 11'd1 && iter_num == MAX_ITER_NUM - 1) ? 1'd1 : 1'd0; + assign end_VN = (cnt_VN == 11'd512 + DELAY_WR + 11'd2 && iter_num <= MAX_ITER_NUM - 2) ? 1'd1 : 1'd0; + +endmodule + diff --git a/hdl/abs_min_4din.v b/hdl/abs_min_4din.v new file mode 100644 index 0000000..846e2b4 --- /dev/null +++ b/hdl/abs_min_4din.v @@ -0,0 +1,51 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 21:36:07 01/20/2018 +// Design Name: +// Module Name: abs_min_4din +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module abs_min_4din #( + parameter WIDTH = 4'd8 +) ( + input clk, + input [WIDTH-1:0] din01, //din01