From 145e8c09302936d6df9e4c517ae8e6b30a885b9f Mon Sep 17 00:00:00 2001 From: ZoroGH Date: Fri, 2 Aug 2024 20:51:37 +0800 Subject: [PATCH] fix(top): reverse iq in recv --- .tags | 1988 +++++++++++++++++++++++++++++------ contraint/mm7020_timing.xdc | 2 +- hdl/PAPR.v | 21 +- hdl/RecvTop.v | 90 +- hdl/ad9361_mgc_pin_ctrl.v | 16 +- hdl/net_city.v | 48 +- hdl/power_measure.v | 2 +- hdl/system_top.v | 155 +-- hdl/tdma.v | 72 +- sim/tb_tdma.v | 55 +- util.tcl | 38 + 11 files changed, 1918 insertions(+), 569 deletions(-) create mode 100644 util.tcl diff --git a/.tags b/.tags index aaefb5b..fa149df 100644 --- a/.tags +++ b/.tags @@ -59,7 +59,7 @@ ADDRESS_WIDTH_DEST adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam ADD ADDRESS_WIDTH_SRC adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam ADDRESS_WIDTH_SRC = BURST_LEN_WIDTH_SRC + ID_WIDTH - 1;$/;" c module:axi_dmac_burst_memory ADDR_MASK adi_library/axi_dmac/tb/regmap_tb.v /^ localparam ADDR_MASK = {{DMA_AXI_ADDR_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};$/;" c module:dmac_regmap_tb ADD_OR_SUB_N adi_library/common/ad_addsub.v /^ parameter ADD_OR_SUB_N = 0) ($/;" c module:ad_addsub -AGC_HEADER_LEN hdl/Transmitter.v /^ parameter AGC_HEADER_LEN = 2130,$/;" c module:Transmitter +AGC_HEADER_LEN hdl/Transmitter.v /^ parameter AGC_HEADER_LEN = 10586,$/;" c module:Transmitter ALLOW_ABORT adi_library/axi_dmac/data_mover.v /^ parameter ALLOW_ABORT = 0) ($/;" c module:dmac_data_mover ALLOW_ASYM_MEM adi_library/axi_dmac/axi_dmac.v /^ parameter ALLOW_ASYM_MEM = 0$/;" c module:axi_dmac ALLOW_ASYM_MEM adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter ALLOW_ASYM_MEM = 0$/;" c module:axi_dmac_burst_memory @@ -208,7 +208,7 @@ BIG_ENDIAN adi_library/util_axis_resize/util_axis_resize.v /^ parameter BIG_END BIT_COUNTER_CARRY adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1);$/;" c module:spi_engine_execution BIT_COUNTER_CLEAR adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};$/;" c module:spi_engine_execution BIT_COUNTER_WIDTH adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :$/;" c module:spi_engine_execution -BLOCK_NUM hdl/Transmitter.v /^ parameter BLOCK_NUM = 28,$/;" c module:Transmitter +BLOCK_NUM hdl/Transmitter.v /^ parameter BLOCK_NUM = 42,$/;" c module:Transmitter BUFR_DIVIDE adi_library/xilinx/common/ad_serdes_clk.v /^ localparam BUFR_DIVIDE = (DDR_OR_SDR_N == 1'b1) ? SERDES_FACTOR \/ 2 : SERDES_FACTOR;$/;" c module:ad_serdes_clk BUF_THRESHOLD_HI adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ localparam BUF_THRESHOLD_HI = 6'd60;$/;" c module:axi_adcfifo_rd BUF_THRESHOLD_HI adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ localparam BUF_THRESHOLD_HI = 8'd250;$/;" c module:axi_adcfifo_wr @@ -265,7 +265,8 @@ C1 adi_library/common/ad_csc.v /^ input signed [MUL_COEF_DW-1:0] C1,$/;" p m C2 adi_library/common/ad_csc.v /^ input signed [MUL_COEF_DW-1:0] C2,$/;" p module:ad_csc C3 adi_library/common/ad_csc.v /^ input signed [MUL_COEF_DW-1:0] C3,$/;" p module:ad_csc C4 adi_library/common/ad_csc.v /^ input signed [SUM_COEF_DW-1:0] C4,$/;" p module:ad_csc -CCSDS_LDPC_DEC_K1024_R12_TOPP hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^module CCSDS_LDPC_DEC_K1024_R12_TOPP$/;" m +CCSDS_LDPC_DEC_K1024_R12 hdl/CCSDS_LDPC_DEC_K1024_R12.v /^module CCSDS_LDPC_DEC_K1024_R12 #($/;" m +CCSDS_LDPC_DEC_K1024_R12_TOPP hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^module CCSDS_LDPC_DEC_K1024_R12_TOPP #($/;" m CCSDS_LDPC_ENC_R12 hdl/CCSDS_LDPC_ENC_R12.v /^module CCSDS_LDPC_ENC_R12($/;" m CE adi_library/common/ad_addsub.v /^ input CE);$/;" p module:ad_addsub CHANNEL_DATA_WIDTH adi_library/util_bsplit/util_bsplit.v /^ parameter CHANNEL_DATA_WIDTH = 1,$/;" c module:util_bsplit @@ -274,9 +275,18 @@ CHANNEL_DATA_WIDTH adi_library/util_pack/util_pack_common/pack_shell.v /^ local CHANNEL_DATA_WIDTH adi_library/util_pack/util_upack2/util_upack2.v /^localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;$/;" c module:util_upack2 CHANNEL_ID adi_library/common/up_adc_channel.v /^ parameter CHANNEL_ID = 4'h0,$/;" c module:up_adc_channel CHANNEL_ID adi_library/common/up_dac_channel.v /^ parameter CHANNEL_ID = 4'h0,$/;" c module:up_dac_channel -CHU_SEQ_LEN hdl/Transmitter.v /^ parameter CHU_SEQ_LEN = 128,$/;" c module:Transmitter +CHNL_dout_01 hdl/VN_PRO.v /^ input [WIDTH-1:0] CHNL_dout_01,\/\/信道信息输入$/;" p module:VN_PRO +CHNL_dout_01_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CHNL_dout_01_VN = 8'd0; \/\/信道信息输入$/;" r module:LDPC_DEC_PRO +CHNL_dout_02 hdl/VN_PRO.v /^ input [WIDTH-1:0] CHNL_dout_02, $/;" p module:VN_PRO +CHNL_dout_02_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CHNL_dout_02_VN = 8'd0;$/;" r module:LDPC_DEC_PRO +CHNL_dout_03 hdl/VN_PRO.v /^ input [WIDTH-1:0] CHNL_dout_03, $/;" p module:VN_PRO +CHNL_dout_03_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CHNL_dout_03_VN = 8'd0;$/;" r module:LDPC_DEC_PRO +CHNL_dout_04 hdl/VN_PRO.v /^ input [WIDTH-1:0] CHNL_dout_04, $/;" p module:VN_PRO +CHNL_dout_04_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CHNL_dout_04_VN = 8'd0;$/;" r module:LDPC_DEC_PRO +CHU_SEQ_LEN hdl/Transmitter.v /^ parameter CHU_SEQ_LEN = 256,$/;" c module:Transmitter CH_HSPMUX adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] CH_HSPMUX = 16'b0010010000100100,$/;" c module:util_adxcvr CH_HSPMUX adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] CH_HSPMUX = 16'b0010010000100100,$/;" c module:util_adxcvr_xch +CK_PRO hdl/CK_PRO.v /^module CK_PRO$/;" m CLKIN_DS_OR_SE_N adi_library/xilinx/common/ad_serdes_clk.v /^ parameter CLKIN_DS_OR_SE_N = 1,$/;" c module:ad_serdes_clk CLK_EDGE_SEL adi_library/common/up_dac_common.v /^ parameter [ 0:0] CLK_EDGE_SEL = 1'b0,$/;" c module:up_dac_common CLK_PERIOD sim/tb_Receiver.v /^ localparam CLK_PERIOD = 20_0;$/;" c module:tb_Receiver @@ -289,11 +299,184 @@ CMD_TRANSFER adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v CMD_WRITE adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam CMD_WRITE = 2'b10;$/;" c module:spi_engine_execution CMOS_LVDS_N adi_library/xilinx/common/ad_serdes_in.v /^ parameter CMOS_LVDS_N = 0,$/;" c module:ad_serdes_in CMOS_LVDS_N adi_library/xilinx/common/ad_serdes_out.v /^ parameter CMOS_LVDS_N = 0,$/;" c module:ad_serdes_out +CN1_addr_rd_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN1_addr_rd_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN1_addr_rd_01_00 hdl/VN_PRO.v /^ output reg [8:0] CN1_addr_rd_01_00=9'd511,$/;" p module:VN_PRO +CN1_addr_rd_01_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN1_addr_rd_01_00_VN;$/;" n module:LDPC_DEC_PRO +CN1_addr_rd_02_00 hdl/VN_PRO.v /^ output reg [9:0] CN1_addr_rd_02_00=10'd1023,$/;" p module:VN_PRO +CN1_addr_rd_02_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN1_addr_rd_02_00_VN;$/;" n module:LDPC_DEC_PRO +CN1_addr_rd_02_01 hdl/VN_PRO.v /^ output reg [9:0] CN1_addr_rd_02_01=10'd511,$/;" p module:VN_PRO +CN1_addr_rd_02_01_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN1_addr_rd_02_01_VN;$/;" n module:LDPC_DEC_PRO +CN1_addr_wr_01_00 hdl/CN_PRO.v /^ output reg [8:0] CN1_addr_wr_01_00=9'd511,$/;" p module:CN_PRO +CN1_addr_wr_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN1_addr_wr_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN1_addr_wr_01_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN1_addr_wr_01_00_CN;$/;" n module:LDPC_DEC_PRO +CN1_addr_wr_02_00 hdl/CN_PRO.v /^ output reg [9:0] CN1_addr_wr_02_00=10'd1023,$/;" p module:CN_PRO +CN1_addr_wr_02_00 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] CN1_addr_wr_02_00 = 10'd1023;$/;" r module:LDPC_DEC_PRO +CN1_addr_wr_02_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN1_addr_wr_02_00_CN;$/;" n module:LDPC_DEC_PRO +CN1_addr_wr_02_01 hdl/CN_PRO.v /^ output reg [9:0] CN1_addr_wr_02_01=10'd511,$/;" p module:CN_PRO +CN1_addr_wr_02_01 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] CN1_addr_wr_02_01 = 10'd511;$/;" r module:LDPC_DEC_PRO +CN1_addr_wr_02_01_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN1_addr_wr_02_01_CN;$/;" n module:LDPC_DEC_PRO +CN1_din_01_00 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN1_din_01_00=8'd0,$/;" p module:CN_PRO +CN1_din_01_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN1_din_01_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN1_din_01_00_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN1_din_01_00_CN;$/;" n module:LDPC_DEC_PRO +CN1_din_02_00 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN1_din_02_00=8'd0,$/;" p module:CN_PRO +CN1_din_02_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN1_din_02_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN1_din_02_00_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN1_din_02_00_CN;$/;" n module:LDPC_DEC_PRO +CN1_din_02_01 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN1_din_02_01=8'd0,$/;" p module:CN_PRO +CN1_din_02_01 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN1_din_02_01 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN1_din_02_01_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN1_din_02_01_CN;$/;" n module:LDPC_DEC_PRO +CN1_dout_01_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN1_dout_01_00;$/;" n module:LDPC_DEC_PRO +CN1_dout_01_00 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN1_dout_01_00, $/;" p module:VN_PRO +CN1_dout_01_00_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN1_dout_01_00_VN = 8'd0;$/;" r module:LDPC_DEC_PRO +CN1_dout_02_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN1_dout_02_00; \/\/后面的00代表H阵原模图的IM$/;" n module:LDPC_DEC_PRO +CN1_dout_02_00 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN1_dout_02_00, \/\/后面的00代表H阵原模图的IM$/;" p module:VN_PRO +CN1_dout_02_00_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN1_dout_02_00_VN = 8'd0; \/\/后面的00代表H阵原模图的IM$/;" r module:LDPC_DEC_PRO +CN1_dout_02_01 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN1_dout_02_01; \/\/后面的01代表H阵原模图的II1$/;" n module:LDPC_DEC_PRO +CN1_dout_02_01 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN1_dout_02_01, \/\/后面的01代表H阵原模图的II1$/;" p module:VN_PRO +CN1_dout_02_01_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN1_dout_02_01_VN = 8'd0; \/\/后面的01代表H阵原模图的II1$/;" r module:LDPC_DEC_PRO CN1_half hdl/Interp_half.v /^ CN1_half CN1_half (.CLK(clk), .A(din_n1), .P(multquartern1)); $/;" i module:Interp_half typeref:module:CN1_half CN1_quarter hdl/Interp_quarter.v /^ CN1 CN1_quarter (.CLK(clk), .A(din_t0), .P(multquartern1)); $/;" i module:Interp_quarter typeref:module:CN1 +CN2_addr_rd_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN2_addr_rd_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN2_addr_rd_01_00 hdl/VN_PRO.v /^ output reg [8:0] CN2_addr_rd_01_00=9'd511,$/;" p module:VN_PRO +CN2_addr_rd_01_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN2_addr_rd_01_00_VN;$/;" n module:LDPC_DEC_PRO +CN2_addr_rd_02_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN2_addr_rd_02_00 = 9'd511; \/\/7.23 xhx 因为IM&II1，II2&II3,II5&II6,II/;" r module:LDPC_DEC_PRO +CN2_addr_rd_02_00 hdl/VN_PRO.v /^ output reg [8:0] CN2_addr_rd_02_00=9'd511,$/;" p module:VN_PRO +CN2_addr_rd_02_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN2_addr_rd_02_00_VN;$/;" n module:LDPC_DEC_PRO +CN2_addr_rd_03_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN2_addr_rd_03_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN2_addr_rd_03_00 hdl/VN_PRO.v /^ output reg [8:0] CN2_addr_rd_03_00=9'd511,$/;" p module:VN_PRO +CN2_addr_rd_03_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN2_addr_rd_03_00_VN;$/;" n module:LDPC_DEC_PRO +CN2_addr_rd_04_02 hdl/VN_PRO.v /^ output reg [9:0] CN2_addr_rd_04_02=10'd1023,$/;" p module:VN_PRO +CN2_addr_rd_04_02_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN2_addr_rd_04_02_VN;$/;" n module:LDPC_DEC_PRO +CN2_addr_rd_04_03 hdl/VN_PRO.v /^ output reg [9:0] CN2_addr_rd_04_03=10'd511,$/;" p module:VN_PRO +CN2_addr_rd_04_03_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN2_addr_rd_04_03_VN;$/;" n module:LDPC_DEC_PRO +CN2_addr_rd_04_04 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN2_addr_rd_04_04 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN2_addr_rd_04_04 hdl/VN_PRO.v /^ output reg [8:0] CN2_addr_rd_04_04=9'd511,$/;" p module:VN_PRO +CN2_addr_rd_04_04_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN2_addr_rd_04_04_VN;$/;" n module:LDPC_DEC_PRO +CN2_addr_wr_01_00 hdl/CN_PRO.v /^ output reg [8:0] CN2_addr_wr_01_00=9'd511,$/;" p module:CN_PRO +CN2_addr_wr_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN2_addr_wr_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN2_addr_wr_01_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN2_addr_wr_01_00_CN;$/;" n module:LDPC_DEC_PRO +CN2_addr_wr_02_00 hdl/CN_PRO.v /^ output reg [8:0] CN2_addr_wr_02_00=9'd511,$/;" p module:CN_PRO +CN2_addr_wr_02_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN2_addr_wr_02_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN2_addr_wr_02_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN2_addr_wr_02_00_CN;$/;" n module:LDPC_DEC_PRO +CN2_addr_wr_03_00 hdl/CN_PRO.v /^ output reg [8:0] CN2_addr_wr_03_00=9'd511,$/;" p module:CN_PRO +CN2_addr_wr_03_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN2_addr_wr_03_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN2_addr_wr_03_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN2_addr_wr_03_00_CN;$/;" n module:LDPC_DEC_PRO +CN2_addr_wr_04_02 hdl/CN_PRO.v /^ output reg [9:0] CN2_addr_wr_04_02=10'd1023,$/;" p module:CN_PRO +CN2_addr_wr_04_02 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] CN2_addr_wr_04_02 = 10'd1023;$/;" r module:LDPC_DEC_PRO +CN2_addr_wr_04_02_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN2_addr_wr_04_02_CN;$/;" n module:LDPC_DEC_PRO +CN2_addr_wr_04_03 hdl/CN_PRO.v /^ output reg [9:0] CN2_addr_wr_04_03=10'd511,$/;" p module:CN_PRO +CN2_addr_wr_04_03 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] CN2_addr_wr_04_03 = 10'd511;$/;" r module:LDPC_DEC_PRO +CN2_addr_wr_04_03_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN2_addr_wr_04_03_CN;$/;" n module:LDPC_DEC_PRO +CN2_addr_wr_04_04 hdl/CN_PRO.v /^ output reg [8:0] CN2_addr_wr_04_04=9'd511,$/;" p module:CN_PRO +CN2_addr_wr_04_04 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN2_addr_wr_04_04 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN2_addr_wr_04_04_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN2_addr_wr_04_04_CN;$/;" n module:LDPC_DEC_PRO +CN2_din_01_00 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN2_din_01_00=8'd0,$/;" p module:CN_PRO +CN2_din_01_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_din_01_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN2_din_01_00_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_din_01_00_CN;$/;" n module:LDPC_DEC_PRO +CN2_din_02_00 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN2_din_02_00=8'd0,$/;" p module:CN_PRO +CN2_din_02_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_din_02_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN2_din_02_00_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_din_02_00_CN;$/;" n module:LDPC_DEC_PRO +CN2_din_03_00 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN2_din_03_00=8'd0,$/;" p module:CN_PRO +CN2_din_03_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_din_03_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN2_din_03_00_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_din_03_00_CN;$/;" n module:LDPC_DEC_PRO +CN2_din_04_02 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN2_din_04_02=8'd0,$/;" p module:CN_PRO +CN2_din_04_02 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_din_04_02 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN2_din_04_02_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_din_04_02_CN;$/;" n module:LDPC_DEC_PRO +CN2_din_04_03 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN2_din_04_03=8'd0,$/;" p module:CN_PRO +CN2_din_04_03 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_din_04_03 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN2_din_04_03_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_din_04_03_CN;$/;" n module:LDPC_DEC_PRO +CN2_din_04_04 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN2_din_04_04=8'd0,$/;" p module:CN_PRO +CN2_din_04_04 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_din_04_04 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN2_din_04_04_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_din_04_04_CN;$/;" n module:LDPC_DEC_PRO +CN2_dout_01_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_dout_01_00;$/;" n module:LDPC_DEC_PRO +CN2_dout_01_00 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN2_dout_01_00,$/;" p module:VN_PRO +CN2_dout_01_00_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_dout_01_00_VN = 8'd0;$/;" r module:LDPC_DEC_PRO +CN2_dout_02_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_dout_02_00;$/;" n module:LDPC_DEC_PRO +CN2_dout_02_00 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN2_dout_02_00,$/;" p module:VN_PRO +CN2_dout_02_00_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_dout_02_00_VN = 8'd0;$/;" r module:LDPC_DEC_PRO +CN2_dout_03_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_dout_03_00;$/;" n module:LDPC_DEC_PRO +CN2_dout_03_00 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN2_dout_03_00,$/;" p module:VN_PRO +CN2_dout_03_00_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_dout_03_00_VN = 8'd0;$/;" r module:LDPC_DEC_PRO +CN2_dout_04_02 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_dout_04_02; \/\/后面的02代表H阵原模图的II2$/;" n module:LDPC_DEC_PRO +CN2_dout_04_02 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN2_dout_04_02, \/\/后面的02代表H阵原模图的II2$/;" p module:VN_PRO +CN2_dout_04_02_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_dout_04_02_VN = 8'd0; \/\/后面的02代表H阵原模图的II2$/;" r module:LDPC_DEC_PRO +CN2_dout_04_03 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_dout_04_03; \/\/后面的03代表H阵原模图的II3$/;" n module:LDPC_DEC_PRO +CN2_dout_04_03 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN2_dout_04_03, \/\/后面的03代表H阵原模图的II3$/;" p module:VN_PRO +CN2_dout_04_03_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_dout_04_03_VN = 8'd0; \/\/后面的03代表H阵原模图的II3$/;" r module:LDPC_DEC_PRO +CN2_dout_04_04 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN2_dout_04_04; \/\/后面的04代表H阵原模图的II4$/;" n module:LDPC_DEC_PRO +CN2_dout_04_04 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN2_dout_04_04, \/\/后面的04代表H阵原模图的II4$/;" p module:VN_PRO +CN2_dout_04_04_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN2_dout_04_04_VN = 8'd0; \/\/后面的04代表H阵原模图的II4$/;" r module:LDPC_DEC_PRO CN2_quarter hdl/Interp_quarter.v /^ CN2 CN2_quarter (.CLK(clk), .A(din_p1), .P(multquartern2)); $/;" i module:Interp_quarter typeref:module:CN2 +CN3_addr_rd_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN3_addr_rd_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN3_addr_rd_01_00 hdl/VN_PRO.v /^ output reg [8:0] CN3_addr_rd_01_00=9'd511,$/;" p module:VN_PRO +CN3_addr_rd_01_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN3_addr_rd_01_00_VN;$/;" n module:LDPC_DEC_PRO +CN3_addr_rd_02_05 hdl/VN_PRO.v /^ output reg [9:0] CN3_addr_rd_02_05=10'd1023,$/;" p module:VN_PRO +CN3_addr_rd_02_05_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN3_addr_rd_02_05_VN;$/;" n module:LDPC_DEC_PRO +CN3_addr_rd_02_06 hdl/VN_PRO.v /^ output reg [9:0] CN3_addr_rd_02_06=10'd511,$/;" p module:VN_PRO +CN3_addr_rd_02_06_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN3_addr_rd_02_06_VN;$/;" n module:LDPC_DEC_PRO +CN3_addr_rd_03_07 hdl/VN_PRO.v /^ output reg [9:0] CN3_addr_rd_03_07=10'd1023,$/;" p module:VN_PRO +CN3_addr_rd_03_07_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN3_addr_rd_03_07_VN;$/;" n module:LDPC_DEC_PRO +CN3_addr_rd_03_08 hdl/VN_PRO.v /^ output reg [9:0] CN3_addr_rd_03_08=10'd511,$/;" p module:VN_PRO +CN3_addr_rd_03_08_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN3_addr_rd_03_08_VN;$/;" n module:LDPC_DEC_PRO +CN3_addr_rd_04_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN3_addr_rd_04_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN3_addr_rd_04_00 hdl/VN_PRO.v /^ output reg [8:0] CN3_addr_rd_04_00=9'd511,$/;" p module:VN_PRO +CN3_addr_rd_04_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN3_addr_rd_04_00_VN;$/;" n module:LDPC_DEC_PRO +CN3_addr_wr_01_00 hdl/CN_PRO.v /^ output reg [8:0] CN3_addr_wr_01_00=9'd511,$/;" p module:CN_PRO +CN3_addr_wr_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN3_addr_wr_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN3_addr_wr_01_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN3_addr_wr_01_00_CN;$/;" n module:LDPC_DEC_PRO +CN3_addr_wr_02_05 hdl/CN_PRO.v /^ output reg [9:0] CN3_addr_wr_02_05=10'd1023,$/;" p module:CN_PRO +CN3_addr_wr_02_05 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] CN3_addr_wr_02_05 = 10'd1023;$/;" r module:LDPC_DEC_PRO +CN3_addr_wr_02_05_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN3_addr_wr_02_05_CN;$/;" n module:LDPC_DEC_PRO +CN3_addr_wr_02_06 hdl/CN_PRO.v /^ output reg [9:0] CN3_addr_wr_02_06=10'd511,$/;" p module:CN_PRO +CN3_addr_wr_02_06 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] CN3_addr_wr_02_06 = 10'd511;$/;" r module:LDPC_DEC_PRO +CN3_addr_wr_02_06_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN3_addr_wr_02_06_CN;$/;" n module:LDPC_DEC_PRO +CN3_addr_wr_03_07 hdl/CN_PRO.v /^ output reg [9:0] CN3_addr_wr_03_07=10'd1023,$/;" p module:CN_PRO +CN3_addr_wr_03_07 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] CN3_addr_wr_03_07 = 10'd1023;$/;" r module:LDPC_DEC_PRO +CN3_addr_wr_03_07_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN3_addr_wr_03_07_CN;$/;" n module:LDPC_DEC_PRO +CN3_addr_wr_03_08 hdl/CN_PRO.v /^ output reg [9:0] CN3_addr_wr_03_08=10'd511,$/;" p module:CN_PRO +CN3_addr_wr_03_08 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] CN3_addr_wr_03_08 = 10'd511;$/;" r module:LDPC_DEC_PRO +CN3_addr_wr_03_08_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] CN3_addr_wr_03_08_CN;$/;" n module:LDPC_DEC_PRO +CN3_addr_wr_04_00 hdl/CN_PRO.v /^ output reg [8:0] CN3_addr_wr_04_00=9'd511,$/;" p module:CN_PRO +CN3_addr_wr_04_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] CN3_addr_wr_04_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +CN3_addr_wr_04_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] CN3_addr_wr_04_00_CN;$/;" n module:LDPC_DEC_PRO +CN3_din_01_00 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN3_din_01_00=8'd0,$/;" p module:CN_PRO +CN3_din_01_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_din_01_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN3_din_01_00_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_din_01_00_CN;$/;" n module:LDPC_DEC_PRO +CN3_din_02_05 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN3_din_02_05=8'd0,$/;" p module:CN_PRO +CN3_din_02_05 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_din_02_05 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN3_din_02_05_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_din_02_05_CN;$/;" n module:LDPC_DEC_PRO +CN3_din_02_06 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN3_din_02_06=8'd0,$/;" p module:CN_PRO +CN3_din_02_06 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_din_02_06 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN3_din_02_06_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_din_02_06_CN;$/;" n module:LDPC_DEC_PRO +CN3_din_03_07 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN3_din_03_07=8'd0,$/;" p module:CN_PRO +CN3_din_03_07 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_din_03_07 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN3_din_03_07_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_din_03_07_CN;$/;" n module:LDPC_DEC_PRO +CN3_din_03_08 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN3_din_03_08=8'd0,$/;" p module:CN_PRO +CN3_din_03_08 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_din_03_08 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN3_din_03_08_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_din_03_08_CN;$/;" n module:LDPC_DEC_PRO +CN3_din_04_00 hdl/CN_PRO.v /^ output reg [WIDTH-1:0] CN3_din_04_00=8'd0,$/;" p module:CN_PRO +CN3_din_04_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_din_04_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +CN3_din_04_00_CN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_din_04_00_CN;$/;" n module:LDPC_DEC_PRO +CN3_dout_01_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_dout_01_00;$/;" n module:LDPC_DEC_PRO +CN3_dout_01_00 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN3_dout_01_00,$/;" p module:VN_PRO +CN3_dout_01_00_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_dout_01_00_VN = 8'd0;$/;" r module:LDPC_DEC_PRO +CN3_dout_02_05 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_dout_02_05; \/\/后面的05代表H阵原模图的II5$/;" n module:LDPC_DEC_PRO +CN3_dout_02_05 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN3_dout_02_05, \/\/后面的05代表H阵原模图的II5$/;" p module:VN_PRO +CN3_dout_02_05_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_dout_02_05_VN = 8'd0; \/\/后面的05代表H阵原模图的II5$/;" r module:LDPC_DEC_PRO +CN3_dout_02_06 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_dout_02_06; \/\/后面的06代表H阵原模图的II6$/;" n module:LDPC_DEC_PRO +CN3_dout_02_06 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN3_dout_02_06, \/\/后面的06代表H阵原模图的II6$/;" p module:VN_PRO +CN3_dout_02_06_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_dout_02_06_VN = 8'd0; \/\/后面的06代表H阵原模图的II6$/;" r module:LDPC_DEC_PRO +CN3_dout_03_07 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_dout_03_07; \/\/后面的07代表H阵原模图的II7$/;" n module:LDPC_DEC_PRO +CN3_dout_03_07 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN3_dout_03_07, \/\/后面的07代表H阵原模图的II7$/;" p module:VN_PRO +CN3_dout_03_07_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_dout_03_07_VN = 8'd0; \/\/后面的07代表H阵原模图的II7$/;" r module:LDPC_DEC_PRO +CN3_dout_03_08 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_dout_03_08; \/\/后面的08代表H阵原模图的II8$/;" n module:LDPC_DEC_PRO +CN3_dout_03_08 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN3_dout_03_08, \/\/后面的08代表H阵原模图的II8$/;" p module:VN_PRO +CN3_dout_03_08_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_dout_03_08_VN = 8'd0; \/\/后面的08代表H阵原模图的II8$/;" r module:LDPC_DEC_PRO +CN3_dout_04_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] CN3_dout_04_00;$/;" n module:LDPC_DEC_PRO +CN3_dout_04_00 hdl/VN_PRO.v /^ input [WIDTH-1:0] CN3_dout_04_00,$/;" p module:VN_PRO +CN3_dout_04_00_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_dout_04_00_VN = 8'd0;$/;" r module:LDPC_DEC_PRO CNT_ADJUST_TIMES_MAX hdl/power_measure.v /^ localparam CNT_ADJUST_TIMES_MAX = 25;$/;" c module:power_measure CNT_AMP_TOO_HIGH_THRESHOLD hdl/power_measure.v /^ localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;$/;" c module:power_measure +CNT_CHU_SEQ_SYNC_MAX hdl/RecvTop.v /^ localparam CNT_CHU_SEQ_SYNC_MAX = 40; \/\/! should not less than 3 due to the minimum rst o/;" c module:RecvTop CNT_IN_MAX hdl/enc_control.v /^ localparam CNT_IN_MAX = ENC_IN_LEN \/ INPUT_DATA_WIDTH;$/;" c module:enc_control CNT_IN_MAX sim/tb_width_convert.v /^ localparam CNT_IN_MAX = 32;$/;" c module:tb_width_convert CNT_IN_WIDTH hdl/enc_control.v /^ localparam CNT_IN_WIDTH = $clog2(CNT_IN_MAX);$/;" c module:enc_control @@ -304,6 +487,12 @@ CNT_OUT_WIDTH hdl/enc_control.v /^ localparam CNT_OUT_WIDTH = $clog2(CNT_OUT_ CNT_W adi_library/common/ad_pnmon.v /^ localparam CNT_W = $clog2(OOS_THRESHOLD);$/;" c module:ad_pnmon CNT_WAIT_9361_MAX hdl/power_measure.v /^ localparam CNT_WAIT_9361_MAX = 80; \/\/* 等待周期数$/;" c module:power_measure CNT_WIDTH hdl/add_prefix.v /^ localparam CNT_WIDTH = $clog2(DATA_LEN);$/;" c module:add_prefix +CNU_3din hdl/CNU_3din.v /^module CNU_3din$/;" m +CNU_6din hdl/CNU_6din.v /^module CNU_6din$/;" m +CN_PRO hdl/CN_PRO.v /^module CN_PRO$/;" m +CN_wea hdl/CN_PRO.v /^ output reg [0:0] CN_wea=1'd0,$/;" p module:CN_PRO +CN_wea hdl/LDPC_DEC_PRO.v /^ reg CN_wea = 1'd0;$/;" r module:LDPC_DEC_PRO +CN_wea_CN hdl/LDPC_DEC_PRO.v /^ wire CN_wea_CN;$/;" n module:LDPC_DEC_PRO COMMON_ID adi_library/common/up_adc_channel.v /^ parameter COMMON_ID = 6'h01,$/;" c module:up_adc_channel COMMON_ID adi_library/common/up_adc_common.v /^ parameter COMMON_ID = 6'h00,$/;" c module:up_adc_common COMMON_ID adi_library/common/up_dac_channel.v /^ parameter COMMON_ID = 6'h11,$/;" c module:up_dac_channel @@ -341,6 +530,11 @@ CS_PIN adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ parameter CS_ CT0_half hdl/Interp_half.v /^ CN1_half CT0_half (.CLK(clk), .A(din_t0), .P(multquartert0)); $/;" i module:Interp_half typeref:module:CN1_half CT0_quarter hdl/Interp_quarter.v /^ CT0 CT0_quarter (.CLK(clk), .A(din_n1), .P(multquartert0)); $/;" i module:Interp_quarter typeref:module:CT0 CTRL_WIDTH adi_library/util_pack/util_pack_common/pack_network.v /^ localparam CTRL_WIDTH = 2**PORT_ADDRESS_WIDTH * NUM_STAGES * MUX_ORDER;$/;" c module:pack_network +CU_01 hdl/VN_PRO.v /^ VNU_2din CU_01 ($/;" i module:VN_PRO typeref:module:VNU_2din +CU_02 hdl/VN_PRO.v /^ VNU_3din CU_02 ($/;" i module:VN_PRO typeref:module:VNU_3din +CU_03 hdl/VN_PRO.v /^ VNU_1din CU_03 (.clk(clk),$/;" i module:VN_PRO typeref:module:VNU_1din +CU_04 hdl/VN_PRO.v /^ VNU_3din CU_04 ($/;" i module:VN_PRO typeref:module:VNU_3din +CU_05 hdl/VN_PRO.v /^ VNU_6din CU_05 ($/;" i module:VN_PRO typeref:module:VNU_6din CYCLIC adi_library/axi_dmac/axi_dmac.v /^ parameter CYCLIC = 1,$/;" c module:axi_dmac C_T_WIDTH adi_library/common/ad_dds_2.v /^ localparam C_T_WIDTH = (DDS_D_DW > DDS_DW) ? (DDS_D_DW - DDS_DW) : (DDS_DW - DDS_D_DW);$/;" c module:ad_dds_2 ChnEst_ZF_i hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i = 18'd0;$/;" r module:Chn_Estimate @@ -378,12 +572,12 @@ ChnEst_comdiv_ad hdl/Chn_Estimate.v /^MUL_FDE ChnEst_comdiv_ad ($/;" i module:Ch ChnEst_comdiv_bc hdl/Chn_Estimate.v /^MUL_FDE ChnEst_comdiv_bc ($/;" i module:Chn_Estimate typeref:module:MUL_FDE ChnEst_comdiv_bd hdl/Chn_Estimate.v /^MUL_FDE ChnEst_comdiv_bd ($/;" i module:Chn_Estimate typeref:module:MUL_FDE Chn_Estimate hdl/Chn_Estimate.v /^module Chn_Estimate($/;" m -Chn_Estimate_djy hdl/SC_FDE_TOP.v /^ Chn_Estimate Chn_Estimate_djy ($/;" i module:SC_FDE_TOP typeref:module:Chn_Estimate +Chn_Estimate_djy hdl/SC_FDE_TOP.v /^ Chn_Estimate Chn_Estimate_djy ($/;" i module:SC_FDE_TOP typeref:module:Chn_Estimate ComMul_EstNoise hdl/Noise_Estimate.v /^ ComMul_EstNoise ComMul_EstNoise ($/;" i module:Noise_Estimate typeref:module:ComMul_EstNoise ComMul_Noisei hdl/Noise_Estimate.v /^ wire [19:0] ComMul_Noisei;$/;" n module:Noise_Estimate ComMul_Noiseq hdl/Noise_Estimate.v /^ wire [19:0] ComMul_Noiseq;$/;" n module:Noise_Estimate -CompMultIP1 hdl/phase_adjust.v /^ CompMultIP CompMultIP1 ($/;" i module:phase_adjust typeref:module:CompMultIP -CompMultIP2 hdl/phase_adjust.v /^ CompMultIP2 CompMultIP2 ($/;" i module:phase_adjust typeref:module:CompMultIP2 +CompMultIP1 hdl/phase_adjust.v /^ CompMultIP CompMultIP1 ($/;" i module:phase_adjust typeref:module:CompMultIP +CompMultIP2 hdl/phase_adjust.v /^ CompMultIP2 CompMultIP2 ($/;" i module:phase_adjust typeref:module:CompMultIP2 CrYCb_data adi_library/common/ad_csc_CrYCb2RGB.v /^ input [23:0] CrYCb_data,$/;" p module:ad_csc_CrYCb2RGB CrYCb_data adi_library/common/ad_csc_RGB2CrYCb.v /^ output [23:0] CrYCb_data);$/;" p module:ad_csc_RGB2CrYCb CrYCb_sync adi_library/common/ad_csc_CrYCb2RGB.v /^ input [DELAY_DATA_WIDTH-1:0] CrYCb_sync,$/;" p module:ad_csc_CrYCb2RGB @@ -399,10 +593,10 @@ DAGC_LUT_rom hdl/DAGC_v2.v /^ DAGC_LUT_rom DAGC_LUT_rom ($/;" i module:DAGC_v DAGC_mul_10bit12_i hdl/DAGC_v2.v /^ DAGC_mul_10bit12 DAGC_mul_10bit12_i ($/;" i module:DAGC_v2 typeref:module:DAGC_mul_10bit12 DAGC_mul_10bit12_q hdl/DAGC_v2.v /^ DAGC_mul_10bit12 DAGC_mul_10bit12_q ($/;" i module:DAGC_v2 typeref:module:DAGC_mul_10bit12 DAGC_out_i hdl/DAGC_v2.v /^ output reg [9:0] DAGC_out_i = 10'd0,$/;" p module:DAGC_v2 -DAGC_out_i hdl/RecvTop.v /^ output [ 9:0] DAGC_out_i, \/\/DAGC输出$/;" p module:RecvTop +DAGC_out_i hdl/RecvTop.v /^ wire [ 9:0] DAGC_out_i; \/\/DAGC输出$/;" n module:RecvTop DAGC_out_q hdl/DAGC_v2.v /^ output reg [9:0] DAGC_out_q = 10'd0,$/;" p module:DAGC_v2 -DAGC_out_q hdl/RecvTop.v /^ output [ 9:0] DAGC_out_q,$/;" p module:RecvTop -DAGC_rdy hdl/RecvTop.v /^ output DAGC_rdy,$/;" p module:RecvTop +DAGC_out_q hdl/RecvTop.v /^ wire [ 9:0] DAGC_out_q;$/;" n module:RecvTop +DAGC_rdy hdl/RecvTop.v /^ wire DAGC_rdy;$/;" n module:RecvTop DAGC_v2 hdl/DAGC_v2.v /^module DAGC_v2 ($/;" m DAGC_v2 hdl/RecvTop.v /^ DAGC_v2 DAGC_v2 ($/;" i module:RecvTop typeref:module:DAGC_v2 DATAFORMAT_DISABLE adi_library/common/up_adc_channel.v /^ parameter DATAFORMAT_DISABLE = 0,$/;" c module:up_adc_channel @@ -491,9 +685,15 @@ DELAY_DATA_WIDTH adi_library/common/ad_dds_sine.v /^ parameter DELAY_DATA_WID DELAY_DATA_WIDTH adi_library/common/ad_ss_422to444.v /^ parameter DELAY_DATA_WIDTH = 16) ($/;" c module:ad_ss_422to444 DELAY_DATA_WIDTH adi_library/common/ad_ss_444to422.v /^ parameter DELAY_DATA_WIDTH = 16) ($/;" c module:ad_ss_444to422 DELAY_DATA_WIDTH adi_library/xilinx/common/ad_mul.v /^ parameter DELAY_DATA_WIDTH = 16) ($/;" c module:ad_mul +DELAY_DIN hdl/CK_PRO.v /^ parameter DELAY_DIN = 11'd0;$/;" c module:CK_PRO DELAY_DW adi_library/common/ad_csc.v /^ parameter DELAY_DW = 16,$/;" c module:ad_csc DELAY_DW adi_library/common/ad_dds_cordic_pipe.v /^ parameter DELAY_DW = 1,$/;" c module:ad_dds_cordic_pipe DELAY_DW adi_library/common/ad_dds_sine_cordic.v /^ parameter DELAY_DW = 1) ($/;" c module:ad_dds_sine_cordic +DELAY_OUT hdl/OUT_PRO.v /^ parameter DELAY_OUT = 4'd6;$/;" c module:OUT_PRO +DELAY_RD hdl/CN_PRO.v /^ parameter DELAY_RD = 11'd6; $/;" c module:CN_PRO +DELAY_RD hdl/VN_PRO.v /^ parameter DELAY_RD = 11'd3; $/;" c module:VN_PRO +DELAY_WR hdl/CN_PRO.v /^ parameter DELAY_WR = 11'd15;$/;" c module:CN_PRO +DELAY_WR hdl/VN_PRO.v /^ parameter DELAY_WR = 11'd17; $/;" c module:VN_PRO DEPTH hdl/shift_reg.v /^ parameter DEPTH = 4$/;" c module:shift_reg DEST_SRC_RATIO adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam DEST_SRC_RATIO = DMA_DATA_WIDTH_DEST\/DMA_DATA_WIDTH_SRC;$/;" c module:axi_dmac_response_manager DEST_SRC_RATIO_WIDTH adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam DEST_SRC_RATIO_WIDTH = DEST_SRC_RATIO > 64 ? 7 :$/;" c module:axi_dmac_response_manager @@ -607,6 +807,60 @@ DRP_DISABLE adi_library/common/up_dac_common.v /^ parameter DRP_DISABLE DRP_WIDTH adi_library/common/up_delay_cntrl.v /^ parameter DRP_WIDTH = 5,$/;" c module:up_delay_cntrl DRP_WIDTH adi_library/xilinx/common/ad_serdes_in.v /^ parameter DRP_WIDTH = 5,$/;" c module:ad_serdes_in DR_OQ_DDR adi_library/xilinx/common/ad_serdes_out.v /^ localparam DR_OQ_DDR = DDR_OR_SDR_N == 1'b1 ? "DDR": "SDR";$/;" c module:ad_serdes_out +DR_addr_rd_01 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] DR_addr_rd_01 = 9'd511;$/;" r module:LDPC_DEC_PRO +DR_addr_rd_01 hdl/OUT_PRO.v /^ output reg [8:0] DR_addr_rd_01=9'd511,$/;" p module:OUT_PRO +DR_addr_rd_01_OUT hdl/LDPC_DEC_PRO.v /^ wire [8:0] DR_addr_rd_01_OUT;$/;" n module:LDPC_DEC_PRO +DR_addr_rd_02 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] DR_addr_rd_02 = 9'd511;$/;" r module:LDPC_DEC_PRO +DR_addr_rd_02 hdl/OUT_PRO.v /^ output reg [8:0] DR_addr_rd_02=9'd511,$/;" p module:OUT_PRO +DR_addr_rd_02_OUT hdl/LDPC_DEC_PRO.v /^ wire [8:0] DR_addr_rd_02_OUT;$/;" n module:LDPC_DEC_PRO +DR_addr_rd_03 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] DR_addr_rd_03 = 9'd511;$/;" r module:LDPC_DEC_PRO +DR_addr_rd_03 hdl/OUT_PRO.v /^ output reg [8:0] DR_addr_rd_03=9'd511,$/;" p module:OUT_PRO +DR_addr_rd_03_OUT hdl/LDPC_DEC_PRO.v /^ wire [8:0] DR_addr_rd_03_OUT;$/;" n module:LDPC_DEC_PRO +DR_addr_rd_04 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] DR_addr_rd_04 = 9'd511;$/;" r module:LDPC_DEC_PRO +DR_addr_rd_04 hdl/OUT_PRO.v /^ output reg [8:0] DR_addr_rd_04=9'd511,$/;" p module:OUT_PRO +DR_addr_rd_04_OUT hdl/LDPC_DEC_PRO.v /^ wire [8:0] DR_addr_rd_04_OUT;$/;" n module:LDPC_DEC_PRO +DR_addr_wr hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] DR_addr_wr = 9'd511;$/;" r module:LDPC_DEC_PRO +DR_addr_wr hdl/VN_PRO.v /^ output reg [8:0] DR_addr_wr=9'd511, $/;" p module:VN_PRO +DR_addr_wr_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] DR_addr_wr_VN;$/;" n module:LDPC_DEC_PRO +DR_din_01 hdl/CK_PRO.v /^ input [0:0] DR_din_01,$/;" p module:CK_PRO +DR_din_01 hdl/LDPC_DEC_PRO.v /^ reg [ 0:0] DR_din_01 = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_din_01 hdl/VN_PRO.v /^ output reg [0:0] DR_din_01=1'd0, \/\/判决结果写数据$/;" p module:VN_PRO +DR_din_01_CK hdl/LDPC_DEC_PRO.v /^ reg DR_din_01_CK = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_din_01_VN hdl/LDPC_DEC_PRO.v /^ wire DR_din_01_VN;$/;" n module:LDPC_DEC_PRO +DR_din_02 hdl/CK_PRO.v /^ input [0:0] DR_din_02,$/;" p module:CK_PRO +DR_din_02 hdl/LDPC_DEC_PRO.v /^ reg [ 0:0] DR_din_02 = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_din_02 hdl/VN_PRO.v /^ output reg [0:0] DR_din_02=1'd0,$/;" p module:VN_PRO +DR_din_02_CK hdl/LDPC_DEC_PRO.v /^ reg DR_din_02_CK = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_din_02_VN hdl/LDPC_DEC_PRO.v /^ wire DR_din_02_VN;$/;" n module:LDPC_DEC_PRO +DR_din_03 hdl/CK_PRO.v /^ input [0:0] DR_din_03,$/;" p module:CK_PRO +DR_din_03 hdl/LDPC_DEC_PRO.v /^ reg [ 0:0] DR_din_03 = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_din_03 hdl/VN_PRO.v /^ output reg [0:0] DR_din_03=1'd0,$/;" p module:VN_PRO +DR_din_03_CK hdl/LDPC_DEC_PRO.v /^ reg DR_din_03_CK = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_din_03_VN hdl/LDPC_DEC_PRO.v /^ wire DR_din_03_VN;$/;" n module:LDPC_DEC_PRO +DR_din_04 hdl/CK_PRO.v /^ input [0:0] DR_din_04,$/;" p module:CK_PRO +DR_din_04 hdl/LDPC_DEC_PRO.v /^ reg [ 0:0] DR_din_04 = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_din_04 hdl/VN_PRO.v /^ output reg [0:0] DR_din_04=1'd0,$/;" p module:VN_PRO +DR_din_04_CK hdl/LDPC_DEC_PRO.v /^ reg DR_din_04_CK = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_din_04_VN hdl/LDPC_DEC_PRO.v /^ wire DR_din_04_VN;$/;" n module:LDPC_DEC_PRO +DR_din_05 hdl/CK_PRO.v /^ input [0:0] DR_din_05,$/;" p module:CK_PRO +DR_din_05 hdl/VN_PRO.v /^ output reg [0:0] DR_din_05=1'd0,$/;" p module:VN_PRO +DR_din_05_CK hdl/LDPC_DEC_PRO.v /^ reg DR_din_05_CK = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_din_05_VN hdl/LDPC_DEC_PRO.v /^ wire DR_din_05_VN;$/;" n module:LDPC_DEC_PRO +DR_dout_01 hdl/LDPC_DEC_PRO.v /^ wire DR_dout_01;$/;" n module:LDPC_DEC_PRO +DR_dout_01 hdl/OUT_PRO.v /^ input [0:0] DR_dout_01,$/;" p module:OUT_PRO +DR_dout_01_OUT hdl/LDPC_DEC_PRO.v /^ reg DR_dout_01_OUT = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_dout_02 hdl/LDPC_DEC_PRO.v /^ wire DR_dout_02;$/;" n module:LDPC_DEC_PRO +DR_dout_02 hdl/OUT_PRO.v /^ input [0:0] DR_dout_02,$/;" p module:OUT_PRO +DR_dout_02_OUT hdl/LDPC_DEC_PRO.v /^ reg DR_dout_02_OUT = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_dout_03 hdl/LDPC_DEC_PRO.v /^ wire DR_dout_03;$/;" n module:LDPC_DEC_PRO +DR_dout_03 hdl/OUT_PRO.v /^ input [0:0] DR_dout_03,$/;" p module:OUT_PRO +DR_dout_03_OUT hdl/LDPC_DEC_PRO.v /^ reg DR_dout_03_OUT = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_dout_04 hdl/LDPC_DEC_PRO.v /^ wire DR_dout_04;$/;" n module:LDPC_DEC_PRO +DR_dout_04 hdl/OUT_PRO.v /^ input [0:0] DR_dout_04,$/;" p module:OUT_PRO +DR_dout_04_OUT hdl/LDPC_DEC_PRO.v /^ reg DR_dout_04_OUT = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_wea hdl/LDPC_DEC_PRO.v /^ reg [ 0:0] DR_wea = 1'd0;$/;" r module:LDPC_DEC_PRO +DR_wea hdl/VN_PRO.v /^ output reg [0:0] DR_wea=8'd0,$/;" p module:VN_PRO +DR_wea_VN hdl/LDPC_DEC_PRO.v /^ wire DR_wea_VN;$/;" n module:LDPC_DEC_PRO DW adi_library/common/ad_csc_CrYCb2RGB.v /^ localparam DW = DELAY_DATA_WIDTH - 1;$/;" c module:ad_csc_CrYCb2RGB DW adi_library/common/ad_csc_RGB2CrYCb.v /^ localparam DW = DELAY_DATA_WIDTH - 1;$/;" c module:ad_csc_RGB2CrYCb DW adi_library/common/ad_pngen.v /^ parameter DW = 16$/;" c module:ad_pngen @@ -619,9 +873,12 @@ Demod_ovrflw hdl/DDS_compensate.v /^ output Demod_ovrflw;$/;" p module:DDS_compe Demod_ovrflw hdl/freqestm.v /^ wire Demod_ovrflw;$/;" n module:freqestm Demod_ovrflw_i hdl/DDS_compensate.v /^ wire Demod_ovrflw_i,Demod_ovrflw_q;$/;" n module:DDS_compensate Demod_ovrflw_q hdl/DDS_compensate.v /^ wire Demod_ovrflw_i,Demod_ovrflw_q;$/;" n module:DDS_compensate -Din hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input [WIDTH-1:0] Din, \/\/译码输入数据,软信息$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP -Din_A_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [WIDTH-1:0] Din_A_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP -Din_B_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [WIDTH-1:0] Din_B_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Din hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ input [WIDTH-1:0] Din, \/\/译码输入数据,软信息,数据速率约为12.5Mbps$/;" p module:CCSDS_LDPC_DEC_K1024_R12 +Din hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input [WIDTH-1:0] Din, \/\/译码输入数据,软信息$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Din_A_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [WIDTH-1:0] Din_A_TM;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Din_A_TM hdl/LDPC_TopManage_2.v /^ output [WIDTH-1:0] Din_A_TM, \/\/译码输入数据,软信息$/;" p module:LDPC_TopManage_2 +Din_B_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [WIDTH-1:0] Din_B_TM;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Din_B_TM hdl/LDPC_TopManage_2.v /^ output [WIDTH-1:0] Din_B_TM, \/\/译码输入数据,软信息$/;" p module:LDPC_TopManage_2 Din_I hdl/ApproxAbs_18bit.v /^ input [17:0] Din_I,$/;" p module:ApproxAbs_18bit Din_I hdl/ApproxAbs_v2.v /^ input [9:0] Din_I,$/;" p module:ApproxAbs_v2 Din_I hdl/DAGC_v2.v /^ reg [ 9:0] Din_I = 10'd0;$/;" r module:DAGC_v2 @@ -636,6 +893,9 @@ Din_Q_D1 hdl/ApproxAbs_18bit.v /^ reg [17:0] Din_Q_D1; $/;" r module:ApproxAbs_1 Din_Q_D1 hdl/ApproxAbs_v2.v /^ reg [9:0] Din_Q_D1;$/;" r module:ApproxAbs_v2 Din_Q_neg hdl/ApproxAbs_18bit.v /^ reg [17:0] Din_Q_neg;$/;" r module:ApproxAbs_18bit Din_Q_neg hdl/ApproxAbs_v2.v /^ reg [9:0] Din_Q_neg;$/;" r module:ApproxAbs_v2 +Din_TM hdl/LDPC_TopManage_2.v /^ input [WIDTH-1:0] Din_TM, \/\/译码输入数据,软信息$/;" p module:LDPC_TopManage_2 +Din_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg [WIDTH-1:0] Din_TM_reg0, Din_TM_reg1;$/;" r module:LDPC_TopManage_2 +Din_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg [WIDTH-1:0] Din_TM_reg0, Din_TM_reg1;$/;" r module:LDPC_TopManage_2 Dout hdl/ApproxAbs_18bit.v /^ output reg [18:0] Dout,$/;" p module:ApproxAbs_18bit Dout hdl/ApproxAbs_v2.v /^ output reg [10:0] Dout = 11'd0,$/;" p module:ApproxAbs_v2 Dout hdl/DAGC_v2.v /^ wire [10:0] Dout;$/;" n module:DAGC_v2 @@ -654,7 +914,8 @@ ENABLE_RANDOM adi_library/util_pack/tb/cpack_tb.v /^ parameter ENABLE_RANDOM = ENABLE_RANDOM adi_library/util_pack/tb/upack_tb.v /^ parameter ENABLE_RANDOM = 0;$/;" c module:upack_tb ENC_IN_LEN hdl/enc_control.v /^ parameter ENC_IN_LEN = 1024,$/;" c module:enc_control ENC_OUT_LEN hdl/enc_control.v /^ parameter ENC_OUT_LEN = 2048,$/;" c module:enc_control -EQUenable_vio hdl/SC_FDE_TOP.v /^ input EQUenable_vio, \/\/为1时启用均衡$/;" p module:SC_FDE_TOP +EQUenable_vio hdl/RecvTop.v /^ input EQUenable_vio, \/\/为1时启用均衡$/;" p module:RecvTop +EQUenable_vio hdl/SC_FDE_TOP.v /^ input EQUenable_vio, \/\/为1时启用均衡$/;" p module:SC_FDE_TOP EQUenable_vio hdl/data_equalizer.v /^ input EQUenable_vio,$/;" p module:data_equalizer ES_DRP_CTRL_ADDR adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [11:0] ES_DRP_CTRL_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03d : (XCVR_TYPE == GTHE3/;" c module:axi_adxcvr_es ES_DRP_ECNT_ADDR adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [11:0] ES_DRP_ECNT_ADDR = (XCVR_TYPE == GTXE2) ? 12'h14f : (XCVR_TYPE == GTHE3/;" c module:axi_adxcvr_es @@ -716,10 +977,10 @@ Encoder_Nd_d2 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Nd_d2 = 1'd0;$/;" r Encoder_SyncIn hdl/CCSDS_LDPC_ENC_R12.v /^ input Encoder_SyncIn,$/;" p module:CCSDS_LDPC_ENC_R12 EstNoise_i hdl/Chn_Estimate.v /^ input [27:0] EstNoise_i,$/;" p module:Chn_Estimate EstNoise_i hdl/Noise_Estimate.v /^ output reg [27:0] EstNoise_i = 28'd0,$/;" p module:Noise_Estimate -EstNoise_i hdl/SC_FDE_TOP.v /^ wire [27:0] EstNoise_i;$/;" n module:SC_FDE_TOP +EstNoise_i hdl/SC_FDE_TOP.v /^ wire [27:0] EstNoise_i;$/;" n module:SC_FDE_TOP EstNoise_q hdl/Chn_Estimate.v /^ input [27:0] EstNoise_q,$/;" p module:Chn_Estimate EstNoise_q hdl/Noise_Estimate.v /^ output reg [27:0] EstNoise_q = 28'd0 \/\/应当为0$/;" p module:Noise_Estimate -EstNoise_q hdl/SC_FDE_TOP.v /^ wire [27:0] EstNoise_q;$/;" n module:SC_FDE_TOP +EstNoise_q hdl/SC_FDE_TOP.v /^ wire [27:0] EstNoise_q;$/;" n module:SC_FDE_TOP FIFO_BYPASS adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0;$/;" c module:axi_dacfifo FIFO_SIZE adi_library/axi_dmac/axi_dmac.v /^ parameter FIFO_SIZE = 8, \/\/ In bursts$/;" c module:axi_dmac FIFO_SIZE adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter FIFO_SIZE = 8,$/;" c module:axi_dmac_transfer @@ -748,12 +1009,17 @@ FPGA_VOLTAGE adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [15:0] FPGA_VOLTAGE adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [15:0] FPGA_VOLTAGE = 0,$/;" c module:axi_adxcvr_up FRAME_HEADER_LEN hdl/Transmitter.v /^ parameter FRAME_HEADER_LEN = 512,$/;" c module:Transmitter FrameMerge hdl/FrameMerge.v /^module FrameMerge($/;" m -FrameMerge hdl/RecvTop.v /^ FrameMerge FrameMerge ($/;" i module:RecvTop typeref:module:FrameMerge -FrameSync hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input FrameSync, \/\/帧同步标志,高脉冲$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP -FrameSync_A_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire FrameSync_A_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP -FrameSync_B_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire FrameSync_B_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP -FrameSync_douti hdl/RecvTop.v /^ wire [9:0] FrameSync_douti;$/;" n module:RecvTop -FrameSync_doutq hdl/RecvTop.v /^ wire [9:0] FrameSync_doutq;$/;" n module:RecvTop +FrameSync hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ input FrameSync, \/\/帧同步标志,高脉冲$/;" p module:CCSDS_LDPC_DEC_K1024_R12 +FrameSync hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input FrameSync, \/\/帧同步标志,高脉冲$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +FrameSync_A_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire FrameSync_A_TM;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +FrameSync_A_TM hdl/LDPC_TopManage_2.v /^ output FrameSync_A_TM, \/\/帧同步标志,高脉冲$/;" p module:LDPC_TopManage_2 +FrameSync_B_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire FrameSync_B_TM;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +FrameSync_B_TM hdl/LDPC_TopManage_2.v /^ output FrameSync_B_TM, \/\/帧同步标志,高脉冲$/;" p module:LDPC_TopManage_2 +FrameSync_TM hdl/LDPC_TopManage_2.v /^ input FrameSync_TM, \/\/帧同步标志,高脉冲$/;" p module:LDPC_TopManage_2 +FrameSync_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg FrameSync_TM_reg0, FrameSync_TM_reg1;$/;" r module:LDPC_TopManage_2 +FrameSync_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg FrameSync_TM_reg0, FrameSync_TM_reg1;$/;" r module:LDPC_TopManage_2 +FrameSync_douti hdl/RecvTop.v /^ wire [ 9:0] FrameSync_douti;$/;" n module:RecvTop +FrameSync_doutq hdl/RecvTop.v /^ wire [ 9:0] FrameSync_doutq;$/;" n module:RecvTop GAP_LEN hdl/Transmitter.v /^ parameter GAP_LEN = 160$/;" c module:Transmitter GEN_ASYNC_RESET adi_library/axi_dmac/axi_dmac_reset_manager.v /^localparam GEN_ASYNC_RESET = {$/;" c module:axi_dmac_reset_manager GPIO_DISABLE adi_library/common/up_adc_common.v /^ parameter GPIO_DISABLE = 0,$/;" c module:up_adc_common @@ -877,6 +1143,50 @@ IQmerge hdl/IQmerge.v /^module IQmerge($/;" m IQmerge hdl/RecvTop.v /^ IQmerge IQmerge ($/;" i module:RecvTop typeref:module:IQmerge IQmergedout hdl/RecvTop.v /^ wire [7:0] IQmergedout;$/;" n module:RecvTop IQmergerdy hdl/RecvTop.v /^ wire IQmergerdy;$/;" n module:RecvTop +Index_p1_row_01_dec_01_01 hdl/CK_PRO.v /^ parameter Index_p1_row_01_dec_01_01=0, Index_p1_row_01_dec_02_01=0,$/;" c module:CK_PRO +Index_p1_row_01_dec_02_01 hdl/CK_PRO.v /^ parameter Index_p1_row_01_dec_01_01=0, Index_p1_row_01_dec_02_01=0,$/;" c module:CK_PRO +Index_p1_row_02_dec_02_01 hdl/CK_PRO.v /^ parameter Index_p1_row_02_dec_02_01=0, Index_p1_row_02_dec_03_01=0,$/;" c module:CK_PRO +Index_p1_row_02_dec_03_01 hdl/CK_PRO.v /^ parameter Index_p1_row_02_dec_02_01=0, Index_p1_row_02_dec_03_01=0,$/;" c module:CK_PRO +Index_p1_row_03_dec_03_01 hdl/CK_PRO.v /^ parameter Index_p1_row_03_dec_03_01=0, Index_p1_row_03_dec_04_01=0,$/;" c module:CK_PRO +Index_p1_row_03_dec_04_01 hdl/CK_PRO.v /^ parameter Index_p1_row_03_dec_03_01=0, Index_p1_row_03_dec_04_01=0,$/;" c module:CK_PRO +Index_p1_row_04_dec_01_01 hdl/CK_PRO.v /^ parameter Index_p1_row_04_dec_04_01=0, Index_p1_row_04_dec_01_01=112,$/;" c module:CK_PRO +Index_p1_row_04_dec_04_01 hdl/CK_PRO.v /^ parameter Index_p1_row_04_dec_04_01=0, Index_p1_row_04_dec_01_01=112,$/;" c module:CK_PRO +Index_p2_row_01_dec_05_01 hdl/CK_PRO.v /^ parameter Index_p2_row_01_dec_05_01=0, Index_p2_row_01_dec_05_02=25, Index_p2_row_01_dec/;" c module:CK_PRO +Index_p2_row_01_dec_05_02 hdl/CK_PRO.v /^ parameter Index_p2_row_01_dec_05_01=0, Index_p2_row_01_dec_05_02=25, Index_p2_row_01_dec/;" c module:CK_PRO +Index_p2_row_01_dec_07_01 hdl/CK_PRO.v /^ parameter Index_p2_row_01_dec_05_01=0, Index_p2_row_01_dec_05_02=25, Index_p2_row_01_dec/;" c module:CK_PRO +Index_p2_row_01_dec_08_01 hdl/CK_PRO.v /^ parameter Index_p2_row_01_dec_05_01=0, Index_p2_row_01_dec_05_02=25, Index_p2_row_01_dec/;" c module:CK_PRO +Index_p2_row_02_dec_05_01 hdl/CK_PRO.v /^ parameter Index_p2_row_02_dec_06_01=0, Index_p2_row_02_dec_06_02=75, Index_p2_row_02_dec/;" c module:CK_PRO +Index_p2_row_02_dec_06_01 hdl/CK_PRO.v /^ parameter Index_p2_row_02_dec_06_01=0, Index_p2_row_02_dec_06_02=75, Index_p2_row_02_dec/;" c module:CK_PRO +Index_p2_row_02_dec_06_02 hdl/CK_PRO.v /^ parameter Index_p2_row_02_dec_06_01=0, Index_p2_row_02_dec_06_02=75, Index_p2_row_02_dec/;" c module:CK_PRO +Index_p2_row_02_dec_08_01 hdl/CK_PRO.v /^ parameter Index_p2_row_02_dec_06_01=0, Index_p2_row_02_dec_06_02=75, Index_p2_row_02_dec/;" c module:CK_PRO +Index_p2_row_03_dec_05_01 hdl/CK_PRO.v /^ parameter Index_p2_row_03_dec_07_01=0, Index_p2_row_03_dec_07_02=120,Index_p2_row_03_dec/;" c module:CK_PRO +Index_p2_row_03_dec_06_01 hdl/CK_PRO.v /^ parameter Index_p2_row_03_dec_07_01=0, Index_p2_row_03_dec_07_02=120,Index_p2_row_03_dec/;" c module:CK_PRO +Index_p2_row_03_dec_07_01 hdl/CK_PRO.v /^ parameter Index_p2_row_03_dec_07_01=0, Index_p2_row_03_dec_07_02=120,Index_p2_row_03_dec/;" c module:CK_PRO +Index_p2_row_03_dec_07_02 hdl/CK_PRO.v /^ parameter Index_p2_row_03_dec_07_01=0, Index_p2_row_03_dec_07_02=120,Index_p2_row_03_dec/;" c module:CK_PRO +Index_p2_row_04_dec_06_01 hdl/CK_PRO.v /^ parameter Index_p2_row_04_dec_08_01=0, Index_p2_row_04_dec_08_02=93, Index_p2_row_04_dec/;" c module:CK_PRO +Index_p2_row_04_dec_07_01 hdl/CK_PRO.v /^ parameter Index_p2_row_04_dec_08_01=0, Index_p2_row_04_dec_08_02=93, Index_p2_row_04_dec/;" c module:CK_PRO +Index_p2_row_04_dec_08_01 hdl/CK_PRO.v /^ parameter Index_p2_row_04_dec_08_01=0, Index_p2_row_04_dec_08_02=93, Index_p2_row_04_dec/;" c module:CK_PRO +Index_p2_row_04_dec_08_02 hdl/CK_PRO.v /^ parameter Index_p2_row_04_dec_08_01=0, Index_p2_row_04_dec_08_02=93, Index_p2_row_04_dec/;" c module:CK_PRO +Index_p3_row_01_dec_09_01 hdl/CK_PRO.v /^ parameter Index_p3_row_01_dec_09_01=0, Index_p3_row_01_dec_09_02=13, Index_p3_row_01_dec/;" c module:CK_PRO +Index_p3_row_01_dec_09_02 hdl/CK_PRO.v /^ parameter Index_p3_row_01_dec_09_01=0, Index_p3_row_01_dec_09_02=13, Index_p3_row_01_dec/;" c module:CK_PRO +Index_p3_row_01_dec_10_01 hdl/CK_PRO.v /^ parameter Index_p3_row_01_dec_09_01=0, Index_p3_row_01_dec_09_02=13, Index_p3_row_01_dec/;" c module:CK_PRO +Index_p3_row_01_dec_11_01 hdl/CK_PRO.v /^ parameter Index_p3_row_01_dec_09_01=0, Index_p3_row_01_dec_09_02=13, Index_p3_row_01_dec/;" c module:CK_PRO +Index_p3_row_01_dec_12_01 hdl/CK_PRO.v /^ parameter Index_p3_row_01_dec_09_01=0, Index_p3_row_01_dec_09_02=13, Index_p3_row_01_dec/;" c module:CK_PRO +Index_p3_row_02_dec_09_01 hdl/CK_PRO.v /^ parameter Index_p3_row_02_dec_10_01=0, Index_p3_row_02_dec_10_02=69, Index_p3_row_02_dec/;" c module:CK_PRO +Index_p3_row_02_dec_10_01 hdl/CK_PRO.v /^ parameter Index_p3_row_02_dec_10_01=0, Index_p3_row_02_dec_10_02=69, Index_p3_row_02_dec/;" c module:CK_PRO +Index_p3_row_02_dec_10_02 hdl/CK_PRO.v /^ parameter Index_p3_row_02_dec_10_01=0, Index_p3_row_02_dec_10_02=69, Index_p3_row_02_dec/;" c module:CK_PRO +Index_p3_row_02_dec_11_01 hdl/CK_PRO.v /^ parameter Index_p3_row_02_dec_10_01=0, Index_p3_row_02_dec_10_02=69, Index_p3_row_02_dec/;" c module:CK_PRO +Index_p3_row_02_dec_12_01 hdl/CK_PRO.v /^ parameter Index_p3_row_02_dec_10_01=0, Index_p3_row_02_dec_10_02=69, Index_p3_row_02_dec/;" c module:CK_PRO +Index_p3_row_03_dec_09_01 hdl/CK_PRO.v /^ parameter Index_p3_row_03_dec_11_01=0, Index_p3_row_03_dec_11_02=127,Index_p3_row_03_dec/;" c module:CK_PRO +Index_p3_row_03_dec_10_01 hdl/CK_PRO.v /^ parameter Index_p3_row_03_dec_11_01=0, Index_p3_row_03_dec_11_02=127,Index_p3_row_03_dec/;" c module:CK_PRO +Index_p3_row_03_dec_11_01 hdl/CK_PRO.v /^ parameter Index_p3_row_03_dec_11_01=0, Index_p3_row_03_dec_11_02=127,Index_p3_row_03_dec/;" c module:CK_PRO +Index_p3_row_03_dec_11_02 hdl/CK_PRO.v /^ parameter Index_p3_row_03_dec_11_01=0, Index_p3_row_03_dec_11_02=127,Index_p3_row_03_dec/;" c module:CK_PRO +Index_p3_row_03_dec_12_01 hdl/CK_PRO.v /^ parameter Index_p3_row_03_dec_11_01=0, Index_p3_row_03_dec_11_02=127,Index_p3_row_03_dec/;" c module:CK_PRO +Index_p3_row_04_dec_09_01 hdl/CK_PRO.v /^ parameter Index_p3_row_04_dec_12_01=0, Index_p3_row_04_dec_12_02=29, Index_p3_row_04_dec/;" c module:CK_PRO +Index_p3_row_04_dec_10_01 hdl/CK_PRO.v /^ parameter Index_p3_row_04_dec_12_01=0, Index_p3_row_04_dec_12_02=29, Index_p3_row_04_dec/;" c module:CK_PRO +Index_p3_row_04_dec_11_01 hdl/CK_PRO.v /^ parameter Index_p3_row_04_dec_12_01=0, Index_p3_row_04_dec_12_02=29, Index_p3_row_04_dec/;" c module:CK_PRO +Index_p3_row_04_dec_12_01 hdl/CK_PRO.v /^ parameter Index_p3_row_04_dec_12_01=0, Index_p3_row_04_dec_12_02=29, Index_p3_row_04_dec/;" c module:CK_PRO +Index_p3_row_04_dec_12_02 hdl/CK_PRO.v /^ parameter Index_p3_row_04_dec_12_01=0, Index_p3_row_04_dec_12_02=29, Index_p3_row_04_dec/;" c module:CK_PRO Interp_half hdl/Interp_half.v /^module Interp_half($/;" m Interp_halfi hdl/Interpolation.v /^ Interp_half Interp_halfi (.clk(clk), .din_p1(dini_p1), .din_t0(dini_t0), .din_n1(dini_n1), .din/;" i module:Interpolation typeref:module:Interp_half Interp_halfq hdl/Interpolation.v /^ Interp_half Interp_halfq (.clk(clk), .din_p1(dinq_p1), .din_t0(dinq_t0), .din_n1(dinq_n1), .din/;" i module:Interpolation typeref:module:Interp_half @@ -895,20 +1205,39 @@ InterpdoutqC hdl/TimeSync_top.v /^ wire [9:0] InterpdoutqC;$/;" n module:TimeSyn InterpdoutqD hdl/TimeSync_top.v /^ wire [9:0] InterpdoutqD;$/;" n module:TimeSync_top Interpolation hdl/Interpolation.v /^module Interpolation($/;" m Interpolation hdl/TimeSync_top.v /^ Interpolation Interpolation ($/;" i module:TimeSync_top typeref:module:Interpolation -IntpARdy hdl/RecvTop.v /^ output IntpARdy, \/\/TSync输出nd$/;" p module:RecvTop -IntpOuti hdl/RecvTop.v /^ output [ 9:0] IntpOuti, \/\/TSync输出$/;" p module:RecvTop -IntpOutq hdl/RecvTop.v /^ output [ 9:0] IntpOutq,$/;" p module:RecvTop +IntpARdy hdl/RecvTop.v /^ wire IntpARdy; \/\/TSync输出nd$/;" n module:RecvTop +IntpOuti hdl/RecvTop.v /^ wire [ 9:0] IntpOuti; \/\/TSync输出$/;" n module:RecvTop +IntpOutq hdl/RecvTop.v /^ wire [ 9:0] IntpOutq;$/;" n module:RecvTop L adi_library/util_cic/cic_comb.v /^ localparam L = k == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (j+1);$/;" c module:cic_comb L adi_library/util_cic/cic_int.v /^ localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1);$/;" c module:cic_int -LDPC_Dout hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output [0:0] LDPC_Dout, \/\/译码输出信号,MSB输出$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_DEC hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ ) LDPC_DEC ($/;" i module:CCSDS_LDPC_DEC_K1024_R12 typeref:module:LDPC_DEC_PRO +LDPC_DEC_PRO hdl/LDPC_DEC_PRO.v /^module LDPC_DEC_PRO #($/;" m +LDPC_Dout hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ output reg [0:0] LDPC_Dout = 1'b0, \/\/译码输出信号$/;" p module:CCSDS_LDPC_DEC_K1024_R12 +LDPC_Dout hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output [0:0] LDPC_Dout, \/\/译码输出信号,MSB输出$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_Dout hdl/RecvTop.v /^ wire LDPC_Dout;$/;" n module:RecvTop -LDPC_Dout_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [0:0] LDPC_Dout_A;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP -LDPC_Dout_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [0:0] LDPC_Dout_B;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_Dout_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [ 0:0] LDPC_Dout_A;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_Dout_A_TM hdl/LDPC_TopManage_2.v /^ input [ 0:0] LDPC_Dout_A_TM, \/\/译码输出信号$/;" p module:LDPC_TopManage_2 +LDPC_Dout_A_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg [0:0] LDPC_Dout_A_TM_reg0, LDPC_Dout_A_TM_reg1;$/;" r module:LDPC_TopManage_2 +LDPC_Dout_A_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg [0:0] LDPC_Dout_A_TM_reg0, LDPC_Dout_A_TM_reg1;$/;" r module:LDPC_TopManage_2 +LDPC_Dout_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [ 0:0] LDPC_Dout_B;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_Dout_B_TM hdl/LDPC_TopManage_2.v /^ input [ 0:0] LDPC_Dout_B_TM, \/\/译码输出信号 $/;" p module:LDPC_TopManage_2 +LDPC_Dout_B_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg [0:0] LDPC_Dout_B_TM_reg0, LDPC_Dout_B_TM_reg1;$/;" r module:LDPC_TopManage_2 +LDPC_Dout_B_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg [0:0] LDPC_Dout_B_TM_reg0, LDPC_Dout_B_TM_reg1;$/;" r module:LDPC_TopManage_2 +LDPC_Dout_TM hdl/LDPC_TopManage_2.v /^ output [ 0:0] LDPC_Dout_TM, \/\/译码输出信号$/;" p module:LDPC_TopManage_2 LDPC_Rdy hdl/RecvTop.v /^ wire LDPC_Rdy;$/;" n module:RecvTop -LDPC_SyncOut hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output LDPC_SyncOut, \/\/LDPC 模块帧同步输出信号,高脉冲,指示帧起点$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_SyncOut hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ output reg LDPC_SyncOut = 1'b0, \/\/LDPC模块帧同步输出信号,高脉冲,指示帧/;" p module:CCSDS_LDPC_DEC_K1024_R12 +LDPC_SyncOut hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output LDPC_SyncOut, \/\/LDPC 模块帧同步输出信号,高脉冲,指示帧起点$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_SyncOut hdl/RecvTop.v /^ wire LDPC_SyncOut;$/;" n module:RecvTop -LDPC_SyncOut_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire LDPC_SyncOut_A; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP -LDPC_SyncOut_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire LDPC_SyncOut_B; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_SyncOut_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire LDPC_SyncOut_A;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_SyncOut_A_TM hdl/LDPC_TopManage_2.v /^ input LDPC_SyncOut_A_TM, \/\/LDPC 模块帧同步输出信号,高脉冲,指示/;" p module:LDPC_TopManage_2 +LDPC_SyncOut_A_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg LDPC_SyncOut_A_TM_reg0, LDPC_SyncOut_A_TM_reg1;$/;" r module:LDPC_TopManage_2 +LDPC_SyncOut_A_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg LDPC_SyncOut_A_TM_reg0, LDPC_SyncOut_A_TM_reg1;$/;" r module:LDPC_TopManage_2 +LDPC_SyncOut_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire LDPC_SyncOut_B;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_SyncOut_B_TM hdl/LDPC_TopManage_2.v /^ input LDPC_SyncOut_B_TM, \/\/LDPC 模块帧同步输出信号,高脉冲,指示/;" p module:LDPC_TopManage_2 +LDPC_SyncOut_B_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg LDPC_SyncOut_B_TM_reg0, LDPC_SyncOut_B_TM_reg1;$/;" r module:LDPC_TopManage_2 +LDPC_SyncOut_B_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg LDPC_SyncOut_B_TM_reg0, LDPC_SyncOut_B_TM_reg1;$/;" r module:LDPC_TopManage_2 +LDPC_SyncOut_TM hdl/LDPC_TopManage_2.v /^ output LDPC_SyncOut_TM, \/\/LDPC 模块帧同步输出信号,高脉冲,指示/;" p module:LDPC_TopManage_2 +LDPC_TopManage_2 hdl/LDPC_TopManage_2.v /^module LDPC_TopManage_2 #($/;" m LDPC_decode hdl/RecvTop.v /^ CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode ($/;" i module:RecvTop typeref:module:CCSDS_LDPC_DEC_K1024_R12_TOPP LENGTH_ALIGN adi_library/axi_dmac/tb/regmap_tb.v /^ localparam LENGTH_ALIGN = 2;$/;" c module:dmac_regmap_tb LENGTH_ALIGN_MASK adi_library/axi_dmac/tb/regmap_tb.v /^ localparam LENGTH_ALIGN_MASK = {LENGTH_ALIGN{1'b1}};$/;" c module:dmac_regmap_tb @@ -918,6 +1247,14 @@ LENGTH_WIDTH adi_library/axi_dmac/src_axi_stream.v /^ parameter LENGTH_WIDTH = LPM_OR_DFE_N adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter LPM_OR_DFE_N = 1,$/;" c module:axi_adxcvr LPM_OR_DFE_N adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter LPM_OR_DFE_N = 1,$/;" c module:axi_adxcvr_up LUT_FSCALE adi_library/common/ad_dds_sine_cordic.v /^ localparam LUT_FSCALE = 1 << (PHASE_DW);$/;" c module:ad_dds_sine_cordic +Lp1_01 hdl/Message_Store.v /^ RAM_512_8 Lp1_01 ($/;" i module:Message_Store typeref:module:RAM_512_8 +Lp1_02 hdl/Message_Store.v /^ RAM_512_8 Lp1_02 ($/;" i module:Message_Store typeref:module:RAM_512_8 +Lp1_03 hdl/Message_Store.v /^ RAM_512_8 Lp1_03 ($/;" i module:Message_Store typeref:module:RAM_512_8 +Lp1_04 hdl/Message_Store.v /^ RAM_512_8 Lp1_04 ($/;" i module:Message_Store typeref:module:RAM_512_8 +Lp2_01 hdl/Message_Store.v /^ RAM_512_8 Lp2_01 ($/;" i module:Message_Store typeref:module:RAM_512_8 +Lp2_02 hdl/Message_Store.v /^ RAM_512_8 Lp2_02 ($/;" i module:Message_Store typeref:module:RAM_512_8 +Lp2_03 hdl/Message_Store.v /^ RAM_512_8 Lp2_03 ($/;" i module:Message_Store typeref:module:RAM_512_8 +Lp2_04 hdl/Message_Store.v /^ RAM_512_8 Lp2_04 ($/;" i module:Message_Store typeref:module:RAM_512_8 MAG_WIDTH hdl/PAPR.v /^ parameter MAG_WIDTH = 22,$/;" c module:PAPR MASTER_DATA_WIDTH adi_library/util_axis_resize/util_axis_resize.v /^ parameter MASTER_DATA_WIDTH = 64,$/;" c module:util_axis_resize MAX_BEATS_PER_BURST adi_library/axi_dmac/address_generator.v /^localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}};$/;" c module:dmac_address_generator @@ -927,7 +1264,10 @@ MAX_BYTES_PER_BURST adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter MAX_B MAX_BYTES_PER_BURST adi_library/axi_dmac/dest_axi_mm.v /^ parameter MAX_BYTES_PER_BURST = 128,$/;" c module:dmac_dest_mm_axi MAX_BYTES_PER_BURST adi_library/axi_dmac/request_arb.v /^ parameter MAX_BYTES_PER_BURST = 128,$/;" c module:dmac_request_arb MAX_DEPTH adi_library/util_var_fifo/util_var_fifo.v /^ localparam MAX_DEPTH = (2 ** ADDRESS_WIDTH) - 1;$/;" c module:util_var_fifo -MAX_ITER_NUM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ parameter MAX_ITER_NUM = 6'd14, \/\/最大迭代次数常量 /;" c module:CCSDS_LDPC_DEC_K1024_R12_TOPP +MAX_ITER_NUM hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ parameter MAX_ITER_NUM = 6'd14,$/;" c module:CCSDS_LDPC_DEC_K1024_R12 +MAX_ITER_NUM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ parameter MAX_ITER_NUM = 6'd14, \/\/最大迭代次数常量 /;" c module:CCSDS_LDPC_DEC_K1024_R12_TOPP +MAX_ITER_NUM hdl/LDPC_DEC_PRO.v /^ parameter MAX_ITER_NUM = 6'd14,$/;" c module:LDPC_DEC_PRO +MAX_ITER_NUM hdl/VN_PRO.v /^ parameter MAX_ITER_NUM = 6'd14, \/\/最大迭代次数$/;" c module:VN_PRO MAX_LATENCY adi_library/axi_dmac/tb/axi_read_slave.v /^ parameter MAX_LATENCY = 48$/;" c module:axi_read_slave MAX_LATENCY adi_library/axi_dmac/tb/axi_slave.v /^ parameter MAX_LATENCY = 32$/;" c module:axi_slave MAX_LENGTH adi_library/axi_dmac/address_generator.v /^localparam MAX_LENGTH = {BEATS_PER_BURST_WIDTH{1'b1}};$/;" c module:dmac_address_generator @@ -950,14 +1290,13 @@ MEM_SIZE adi_library/common/ad_mem_asym.v /^ localparam MEM_SIZE = 2 ** MEM_AD MF12p5_12bit_i hdl/MF_Top.v /^ MF12p5_12bit MF12p5_12bit_i ($/;" i module:MF_Top typeref:module:MF12p5_12bit MF12p5_12bit_q hdl/MF_Top.v /^ MF12p5_12bit MF12p5_12bit_q ($/;" i module:MF_Top typeref:module:MF12p5_12bit MF_Top hdl/MF_Top.v /^module MF_Top ($/;" m -MF_Top hdl/RecvTop.v /^ MF_Top MF_Top ($/;" i module:RecvTop typeref:module:MF_Top MF_m_axis_data_tdata_i hdl/MF_Top.v /^ wire [31:0] MF_m_axis_data_tdata_i;$/;" n module:MF_Top MF_m_axis_data_tdata_q hdl/MF_Top.v /^ wire [31:0] MF_m_axis_data_tdata_q;$/;" n module:MF_Top MF_rdy hdl/MF_Top.v /^ output reg MF_rdy,$/;" p module:MF_Top -MF_rdy hdl/RecvTop.v /^ wire MF_rdy;$/;" n module:RecvTop +MF_rdy hdl/RecvTop.v /^ reg MF_rdy; \/\/ flag_mgc_done_d1$/;" r module:RecvTop MF_rdy_d1 hdl/MF_Top.v /^ reg MF_rdy_d1;$/;" r module:MF_Top MF_rst hdl/MF_Top.v /^ output reg MF_rst$/;" p module:MF_Top -MF_rst hdl/RecvTop.v /^ wire MF_rst;$/;" n module:RecvTop +MF_rst hdl/RecvTop.v /^ wire MF_rst; \/\/ flag_mgc_done_pulse_d2$/;" n module:RecvTop MIN_LATENCY adi_library/axi_dmac/tb/axi_read_slave.v /^ parameter MIN_LATENCY = 48,$/;" c module:axi_read_slave MIN_LATENCY adi_library/axi_dmac/tb/axi_slave.v /^ parameter MIN_LATENCY = 16,$/;" c module:axi_slave MIN_STAGE adi_library/util_pack/util_pack_common/pack_ctrl.v /^ parameter MIN_STAGE = 0,$/;" c module:pack_ctrl @@ -986,6 +1325,7 @@ MMCM_VCO_MUL adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_VCO_MU MMCM_VCO_MUL adi_library/xilinx/common/ad_serdes_clk.v /^ parameter MMCM_VCO_MUL = 12.000,$/;" c module:ad_serdes_clk MM_IF_TYPE adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter MM_IF_TYPE = 0,$/;" c module:axi_spi_engine MODULE_VERSION hdl/phy_control.v /^ localparam MODULE_VERSION = 'h000001;$/;" c module:phy_control +MS hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ ) MS ($/;" i module:CCSDS_LDPC_DEC_K1024_R12 typeref:module:Message_Store MSB_WIDTH adi_library/common/util_axis_upscale.v /^ localparam MSB_WIDTH = UDATA_WIDTH - DATA_WIDTH;$/;" c module:util_axis_upscale MUL_COEF_DW adi_library/common/ad_csc.v /^ parameter MUL_COEF_DW = 17,$/;" c module:ad_csc MUL_DW adi_library/common/ad_csc.v /^ localparam MUL_DW = MUL_COEF_DW + PIXEL_WD -1;$/;" c module:ad_csc @@ -998,6 +1338,7 @@ M_MEM_RATIO adi_library/util_wfifo/util_wfifo.v /^ localparam M_MEM_RATIO = DO M_SEQ hdl/frame_sync.v /^ parameter [511:0] M_SEQ =512'b11111111100001111011100001011001101101111010000111001100001001/;" c module:frame_sync M_SEQ_REVERSE hdl/frame_sync.v /^ parameter [511:0] M_SEQ_REVERSE =512'b000000111101111100010111001100100000100101001110110100/;" c module:frame_sync MagnitudeEstimator hdl/MagnitudeEstimator.v /^module MagnitudeEstimator #($/;" m +Message_Store hdl/Message_Store.v /^module Message_Store #($/;" m MultFreq hdl/DDS_compensate.v /^ComplexMult12x12_4dly MultFreq ($/;" i module:DDS_compensate typeref:module:ComplexMult12x12_4dly Multouti01 hdl/freqestm.v /^ wire [20:0] Multouti01;$/;" n module:freqestm Multouti01_head hdl/freqestm.v /^ wire [ 2:0] Multouti01_head;$/;" n module:freqestm @@ -1007,6 +1348,15 @@ ND hdl/ApproxAbs_18bit.v /^ input ND,$/;" p module:ApproxAbs_18bit ND hdl/ApproxAbs_v2.v /^ input ND,$/;" p module:ApproxAbs_v2 ND hdl/DAGC_v2.v /^ reg ND = 1'd0;$/;" r module:DAGC_v2 NEG_EDGE adi_library/common/ad_edge_detect.v /^ localparam NEG_EDGE = 1;$/;" c module:ad_edge_detect +NF01 hdl/CNU_3din.v /^ Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF01 (.clk(clk),.din_NF(abs01_update),.dout_NF(/;" i module:CNU_3din typeref:module:Normalization_Factor_0_8125 +NF01 hdl/CNU_6din.v /^ Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF01 (.clk(clk),.din_NF(abs01_update),.dout_NF(/;" i module:CNU_6din typeref:module:Normalization_Factor_0_8125 +NF02 hdl/CNU_3din.v /^ Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF02 (.clk(clk),.din_NF(abs02_update),.dout_NF(/;" i module:CNU_3din typeref:module:Normalization_Factor_0_8125 +NF02 hdl/CNU_6din.v /^ Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF02 (.clk(clk),.din_NF(abs02_update),.dout_NF(/;" i module:CNU_6din typeref:module:Normalization_Factor_0_8125 +NF03 hdl/CNU_3din.v /^ Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF03 (.clk(clk),.din_NF(abs03_update),.dout_NF(/;" i module:CNU_3din typeref:module:Normalization_Factor_0_8125 +NF03 hdl/CNU_6din.v /^ Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF03 (.clk(clk),.din_NF(abs03_update),.dout_NF(/;" i module:CNU_6din typeref:module:Normalization_Factor_0_8125 +NF04 hdl/CNU_6din.v /^ Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF04 (.clk(clk),.din_NF(abs04_update),.dout_NF(/;" i module:CNU_6din typeref:module:Normalization_Factor_0_8125 +NF05 hdl/CNU_6din.v /^ Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF05 (.clk(clk),.din_NF(abs05_update),.dout_NF(/;" i module:CNU_6din typeref:module:Normalization_Factor_0_8125 +NF06 hdl/CNU_6din.v /^ Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF06 (.clk(clk),.din_NF(abs06_update),.dout_NF(/;" i module:CNU_6din typeref:module:Normalization_Factor_0_8125 NONE adi_library/xilinx/common/ad_data_in.v /^ localparam NONE = -1;$/;" c module:ad_data_in NONE adi_library/xilinx/common/ad_data_out.v /^ localparam NONE = -1;$/;" c module:ad_data_out NON_POWER_OF_TWO adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam NON_POWER_OF_TWO = NUM_OF_CHANNELS > 2;$/;" c module:pack_shell @@ -1058,11 +1408,18 @@ NUM_STAGES adi_library/util_pack/util_pack_common/pack_interconnect.v /^ parame NUM_STAGES adi_library/util_pack/util_pack_common/pack_network.v /^ parameter NUM_STAGES = 1,$/;" c module:pack_network NUM_STAGES adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam NUM_STAGES = PACK ? (i == 0 ? SAMPLE_ADDRESS_WIDTH \/ 2 : SAMPLE_ADDRESS_WIDT/;" c block:pack_shell.gen_network NUM_SWITCHES adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam NUM_SWITCHES = NUM_PORTS \/ z;$/;" c module:pack_interconnect -Nd hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input Nd, \/\/译码输入数据有效标志,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP -Nd_A_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Nd_A_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP -Nd_B_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Nd_B_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Nd hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ input Nd, \/\/译码输入数据有效标志,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12 +Nd hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input Nd, \/\/译码输入数据有效标志,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Nd_A_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Nd_A_TM;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Nd_A_TM hdl/LDPC_TopManage_2.v /^ output Nd_A_TM, \/\/译码输入数据有效标志,高有效$/;" p module:LDPC_TopManage_2 +Nd_B_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Nd_B_TM;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Nd_B_TM hdl/LDPC_TopManage_2.v /^ output Nd_B_TM, \/\/译码输入数据有效标志,高有效$/;" p module:LDPC_TopManage_2 +Nd_TM hdl/LDPC_TopManage_2.v /^ input Nd_TM, \/\/译码输入数据有效标志,高有效$/;" p module:LDPC_TopManage_2 +Nd_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg Nd_TM_reg0, Nd_TM_reg1;$/;" r module:LDPC_TopManage_2 +Nd_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg Nd_TM_reg0, Nd_TM_reg1;$/;" r module:LDPC_TopManage_2 Noise_Estimate hdl/Noise_Estimate.v /^module Noise_Estimate($/;" m -Noise_Estimate_djy hdl/SC_FDE_TOP.v /^ Noise_Estimate Noise_Estimate_djy ($/;" i module:SC_FDE_TOP typeref:module:Noise_Estimate +Noise_Estimate_djy hdl/SC_FDE_TOP.v /^ Noise_Estimate Noise_Estimate_djy ($/;" i module:SC_FDE_TOP typeref:module:Noise_Estimate +Normalization_Factor_0_8125 hdl/Normalization_Factor_0_8125.v /^module Normalization_Factor_0_8125 #($/;" m OCTETS_PER_BEAT adi_library/common/ad_xcvr_rx_if.v /^ parameter OCTETS_PER_BEAT = 4,$/;" c module:ad_xcvr_rx_if OCTETS_PER_SAMPLE adi_library/common/ad_datafmt.v /^ parameter OCTETS_PER_SAMPLE = 2,$/;" c module:ad_datafmt OFF adi_library/common/ad_tdd_control.v /^ localparam [ 0:0] OFF = 0;$/;" c module:ad_tdd_control @@ -1073,7 +1430,11 @@ OOS_THRESHOLD adi_library/common/ad_pnmon.v /^ parameter OOS_THRESHOLD = 16,$/; OUTPUT_WIDTH hdl/width_convert.v /^ parameter OUTPUT_WIDTH = 2$/;" c module:width_convert OUT_CLK_SEL adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [ 2:0] OUT_CLK_SEL = 3'd4) ($/;" c module:axi_adxcvr OUT_CLK_SEL adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 2:0] OUT_CLK_SEL = 3'd4) ($/;" c module:axi_adxcvr_up -OUT_ONLY_INFORMATION hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ parameter OUT_ONLY_INFORMATION = 1'b0 \/\/译码输出格式选择标志，1:只输出/;" c module:CCSDS_LDPC_DEC_K1024_R12_TOPP +OUT_ONLY_INFORMATION hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ parameter OUT_ONLY_INFORMATION = 1'b0 \/\/译码输出格式选择标志，1:只输出信息/;" c module:CCSDS_LDPC_DEC_K1024_R12 +OUT_ONLY_INFORMATION hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ parameter OUT_ONLY_INFORMATION = 1'b1 \/\/译码输出格式选择标志，1:只输出信/;" c module:CCSDS_LDPC_DEC_K1024_R12_TOPP +OUT_ONLY_INFORMATION hdl/LDPC_DEC_PRO.v /^ parameter OUT_ONLY_INFORMATION = 1'd0$/;" c module:LDPC_DEC_PRO +OUT_ONLY_INFORMATION hdl/OUT_PRO.v /^ parameter OUT_ONLY_INFORMATION = 1'd0 \/\/译码输出格式选择标志，1:只输出信/;" c module:OUT_PRO +OUT_PRO hdl/OUT_PRO.v /^module OUT_PRO$/;" m Out_Info_bit hdl/CCSDS_LDPC_ENC_R12.v /^ reg Out_Info_bit = 1'd0;$/;" r module:CCSDS_LDPC_ENC_R12 Out_Process_R12 hdl/CCSDS_LDPC_ENC_R12.v /^ Out_Process_R12 Out_Process_R12($/;" i module:CCSDS_LDPC_ENC_R12 typeref:module:Out_Process_R12 Out_Process_R12 hdl/Out_Process_R12.v /^module Out_Process_R12($/;" m @@ -1089,7 +1450,7 @@ PCORE_VERSION adi_library/common/up_hdmi_tx.v /^ localparam PCORE_VERSION = 32 PCORE_VERSION adi_library/common/up_pmod.v /^ localparam PCORE_VERSION = 32'h00010001;$/;" c module:up_pmod PCORE_VERSION adi_library/common/up_tdd_cntrl.v /^ localparam PCORE_VERSION = 32'h00010061;$/;" c module:up_tdd_cntrl PCORE_VERSION adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ localparam PCORE_VERSION = 'h010071;$/;" c module:axi_spi_engine -PHASE1_LEN hdl/Transmitter.v /^ parameter PHASE1_LEN = 2112, \/\/ (8 cp + 256 sym)* 8 ( total 2048 valid sym)$/;" c module:Transmitter +PHASE1_LEN hdl/Transmitter.v /^ parameter PHASE1_LEN = 2880, \/\/ (32 cp + 256 sym)* 10 ( total 2880 valid sym)$/;" c module:Transmitter PHASE_DW adi_library/common/ad_dds.v /^ parameter PHASE_DW = 16,$/;" c module:ad_dds PHASE_DW adi_library/common/ad_dds_2.v /^ parameter PHASE_DW = 16,$/;" c module:ad_dds_2 PHASE_DW adi_library/common/ad_dds_sine_cordic.v /^ parameter PHASE_DW = 16,$/;" c module:ad_dds_sine_cordic @@ -1112,17 +1473,16 @@ POR_CFG adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] POS_EDGE adi_library/common/ad_edge_detect.v /^ localparam POS_EDGE = 0;$/;" c module:ad_edge_detect PPF0_CFG adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] PPF0_CFG = 16'b0000011000000000,$/;" c module:util_adxcvr PPF0_CFG adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] PPF0_CFG = 16'b0000011000000000,$/;" c module:util_adxcvr_xcm -PREFIX_LEN hdl/Transmitter.v /^ parameter PREFIX_LEN = 8,$/;" c module:Transmitter -PREFIX_LEN hdl/add_prefix.v /^ parameter PREFIX_LEN = 8$/;" c module:add_prefix +PREFIX_LEN hdl/Transmitter.v /^ parameter PREFIX_LEN = 32,$/;" c module:Transmitter +PREFIX_LEN hdl/add_prefix.v /^ parameter PREFIX_LEN = 32$/;" c module:add_prefix PREIQ_FREQ_BST adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer PREIQ_FREQ_BST = 0,$/;" c module:util_adxcvr PREIQ_FREQ_BST adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer PREIQ_FREQ_BST = 0,$/;" c module:util_adxcvr_xch PULSE_PERIOD adi_library/common/util_pulse_gen.v /^ parameter PULSE_PERIOD = 100000000)( \/\/ t_period * clk_freq$/;" c module:util_pulse_gen PULSE_PERIOD hdl/ad9361_mgc_pin_ctrl.v /^ localparam PULSE_PERIOD = 5;$/;" c module:ad9361_mgc_pin_ctrl PULSE_WIDTH adi_library/common/util_pulse_gen.v /^ parameter PULSE_WIDTH = 7,$/;" c module:util_pulse_gen P_DW adi_library/common/ad_dds_cordic_pipe.v /^ parameter P_DW = 16,$/;" c module:ad_dds_cordic_pipe -Pilot_rdy hdl/RecvTop.v /^ wire Pilot_rdy;$/;" n module:RecvTop Pilot_rdy hdl/SCFDE_recv_FrameSync.v /^ output reg Pilot_rdy = 1'b0, \/\/出峰后88个clk后拉高1clk，对齐导频/;" p module:SCFDE_recv_FrameSync -Pilot_rdy_hide1_d1 hdl/RecvTop.v /^ output Pilot_rdy_hide1_d1,$/;" p module:RecvTop +Pilot_rdy_hide1_d1 hdl/RecvTop.v /^ wire Pilot_rdy_hide1_d1;$/;" n module:RecvTop Pilot_rdy_hide1_d1 hdl/SCFDE_recv_FrameSync.v /^ output reg Pilot_rdy_hide1_d1 = 1'b0$/;" p module:SCFDE_recv_FrameSync Q hdl/MagnitudeEstimator.v /^ input [VEC_WIDTH-1:0] Q,$/;" p module:MagnitudeEstimator QPLL_CFG adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [26:0] QPLL_CFG = 27'h0680181,$/;" c module:util_adxcvr @@ -1156,15 +1516,40 @@ QPLL_LPF adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_REFCLK_DIV adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer QPLL_REFCLK_DIV = 1,$/;" c module:util_adxcvr QPLL_REFCLK_DIV adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter integer QPLL_REFCLK_DIV = 1,$/;" c module:util_adxcvr_xcm Q_OR_I_N adi_library/common/ad_iqcor.v /^ parameter Q_OR_I_N = 0,$/;" c module:ad_iqcor -RAM_ChnEst_MMSE hdl/SC_FDE_TOP.v /^ RAM_ChnEst_MMSE RAM_ChnEst_MMSE ($/;" i module:SC_FDE_TOP typeref:module:RAM_ChnEst_MMSE +RAM_CN_01 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_CN_01 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_CN_02 hdl/LDPC_DEC_PRO.v /^ RAM_512X2_8 RAM_CN_02 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X2_8 +RAM_CN_03 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_CN_03 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_CN_04 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_CN_04 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_CN_05 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_CN_05 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_CN_06 hdl/LDPC_DEC_PRO.v /^ RAM_512X2_8 RAM_CN_06 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X2_8 +RAM_CN_07 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_CN_07 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_CN_08 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_CN_08 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_CN_09 hdl/LDPC_DEC_PRO.v /^ RAM_512X2_8 RAM_CN_09 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X2_8 +RAM_CN_10 hdl/LDPC_DEC_PRO.v /^ RAM_512X2_8 RAM_CN_10 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X2_8 +RAM_CN_11 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_CN_11 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_ChnEst_MMSE hdl/SC_FDE_TOP.v /^ RAM_ChnEst_MMSE RAM_ChnEst_MMSE ($/;" i module:SC_FDE_TOP typeref:module:RAM_ChnEst_MMSE +RAM_DR_01 hdl/LDPC_DEC_PRO.v /^ RAM_512_1 RAM_DR_01 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512_1 +RAM_DR_02 hdl/LDPC_DEC_PRO.v /^ RAM_512_1 RAM_DR_02 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512_1 +RAM_DR_03 hdl/LDPC_DEC_PRO.v /^ RAM_512_1 RAM_DR_03 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512_1 +RAM_DR_04 hdl/LDPC_DEC_PRO.v /^ RAM_512_1 RAM_DR_04 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512_1 RAM_IQmerge hdl/IQmerge.v /^ RAM_IQmerge RAM_IQmerge ($/;" i module:IQmerge typeref:module:RAM_IQmerge +RAM_VN_01 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_VN_01 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_VN_02 hdl/LDPC_DEC_PRO.v /^ RAM_512X2_8 RAM_VN_02 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X2_8 +RAM_VN_03 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_VN_03 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_VN_04 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_VN_04 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_VN_05 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_VN_05 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_VN_06 hdl/LDPC_DEC_PRO.v /^ RAM_512X2_8 RAM_VN_06 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X2_8 +RAM_VN_07 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_VN_07 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_VN_08 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_VN_08 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 +RAM_VN_09 hdl/LDPC_DEC_PRO.v /^ RAM_512X2_8 RAM_VN_09 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X2_8 +RAM_VN_10 hdl/LDPC_DEC_PRO.v /^ RAM_512X2_8 RAM_VN_10 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X2_8 +RAM_VN_11 hdl/LDPC_DEC_PRO.v /^ RAM_512X1_8 RAM_VN_11 ($/;" i module:LDPC_DEC_PRO typeref:module:RAM_512X1_8 RAM_merge_0 hdl/FrameMerge.v /^ RAM_merge RAM_merge_0 ($/;" i module:FrameMerge typeref:module:RAM_merge -RAM_phase hdl/phase_adjust.v /^ RAM_phase RAM_phase ($/;" i module:phase_adjust typeref:module:RAM_phase +RAM_phase hdl/phase_adjust.v /^ RAM_phase RAM_phase ($/;" i module:phase_adjust typeref:module:RAM_phase RAM_recvnew_0 hdl/FrameMerge.v /^ RAM_recvnew RAM_recvnew_0 ($/;" i module:FrameMerge typeref:module:RAM_recvnew RAM_recvnew_1 hdl/FrameMerge.v /^ RAM_recvnew RAM_recvnew_1 ($/;" i module:FrameMerge typeref:module:RAM_recvnew RAM_recvnew_2 hdl/FrameMerge.v /^ RAM_recvnew RAM_recvnew_2 ($/;" i module:FrameMerge typeref:module:RAM_recvnew RAMaddra hdl/FrameMerge.v /^ output reg [16:0] RAMaddra = 17'd0, \/\/比较误码率$/;" p module:FrameMerge -RAMaddra hdl/RecvTop.v /^ wire [16:0] RAMaddra; \/\/比较误码率$/;" n module:RecvTop RAMaddra_new_0 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_new_0 = 17'd0,$/;" p module:FrameMerge RAMaddra_new_0_d1 hdl/FrameMerge.v /^ reg [16:0] RAMaddra_new_0_d1 = 17'd0;$/;" r module:FrameMerge RAMaddra_new_1 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_new_1 = 17'd0,$/;" p module:FrameMerge @@ -1181,7 +1566,6 @@ RAMaddra_write_3 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_write_3 = 17'd0, RAMaddrb hdl/FrameMerge.v /^ reg [16:0] RAMaddrb = 17'd0;$/;" r module:FrameMerge RAMdout hdl/FrameMerge.v /^ wire RAMdout;$/;" n module:FrameMerge RAMdout_d1 hdl/FrameMerge.v /^ output reg RAMdout_d1 = 1'd0,$/;" p module:FrameMerge -RAMdout_d1 hdl/RecvTop.v /^ wire RAMdout_d1;$/;" n module:RecvTop RATE adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [ 2:0] RATE = 3'd0,$/;" c module:axi_adxcvr RATE adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 2:0] RATE = 3'd0,$/;" c module:axi_adxcvr_up RATIO adi_library/axi_dmac/axi_dmac_resize_dest.v /^ localparam RATIO = DATA_WIDTH_MEM \/ DATA_WIDTH_DEST;$/;" c module:axi_dmac_resize_dest @@ -1209,13 +1593,14 @@ RGB_sync adi_library/common/ad_csc_CrYCb2RGB.v /^ output [DELAY_DATA_WIDTH RGB_sync adi_library/common/ad_csc_RGB2CrYCb.v /^ input [DELAY_DATA_WIDTH-1:0] RGB_sync,$/;" p module:ad_csc_RGB2CrYCb ROM_ber hdl/FrameMerge.v /^ ROM_ber ROM_ber ($/;" i module:FrameMerge typeref:module:ROM_ber ROMaddra hdl/FrameMerge.v /^ output reg [16:0] ROMaddra = 17'd0, \/\/比较误码率$/;" p module:FrameMerge -ROMaddra hdl/RecvTop.v /^ wire [16:0] ROMaddra; \/\/比较误码率$/;" n module:RecvTop ROMaddra_d1 hdl/FrameMerge.v /^ reg [16:0] ROMaddra_d1 = 17'd0;$/;" r module:FrameMerge ROMaddra_d2 hdl/FrameMerge.v /^ output reg [16:0] ROMaddra_d2 = 17'd0,$/;" p module:FrameMerge -ROMaddra_d2 hdl/RecvTop.v /^ wire [16:0] ROMaddra_d2;$/;" n module:RecvTop ROMdout hdl/FrameMerge.v /^ wire ROMdout;$/;" n module:FrameMerge RTX_BUF_CML_CTRL adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [2:0] RTX_BUF_CML_CTRL = 3'b011,$/;" c module:util_adxcvr RTX_BUF_CML_CTRL adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [2:0] RTX_BUF_CML_CTRL = 3'b011,$/;" c module:util_adxcvr_xch +RU_01 hdl/CN_PRO.v /^ CNU_3din #(.WIDTH(WIDTH)) RU_01 ($/;" i module:CN_PRO typeref:module:CNU_3din +RU_02 hdl/CN_PRO.v /^ CNU_6din #(.WIDTH(WIDTH)) RU_02 ($/;" i module:CN_PRO typeref:module:CNU_6din +RU_03 hdl/CN_PRO.v /^ CNU_6din #(.WIDTH(WIDTH)) RU_03 ($/;" i module:CN_PRO typeref:module:CNU_6din RXCDR_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010,$/;" c module:util_adxcvr RXCDR_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010,$/;" c module:util_adxcvr_xch RXCDR_CFG2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RXCDR_CFG2 = 16'b0000001001101001,$/;" c module:util_adxcvr @@ -1255,9 +1640,17 @@ RX_XMODE_SEL adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [ 0:0] RX_XMODE_SEL adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [ 0:0] RX_XMODE_SEL = 1'b1,$/;" c module:util_adxcvr_xch Rdy hdl/ApproxAbs_18bit.v /^ output reg Rdy $/;" p module:ApproxAbs_18bit Rdy hdl/ApproxAbs_v2.v /^ output reg Rdy = 1'b0$/;" p module:ApproxAbs_v2 -Rdy hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output Rdy, \/\/译码输出信号有效标志,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP -Rdy_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Rdy_A; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP -Rdy_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Rdy_B; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Rdy hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ output reg Rdy = 1'b0, \/\/译码输出信号有效标志,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12 +Rdy hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output Rdy, \/\/译码输出信号有效标志,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Rdy_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Rdy_A;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Rdy_A_TM hdl/LDPC_TopManage_2.v /^ input Rdy_A_TM, \/\/译码输出信号有效标志,高有效$/;" p module:LDPC_TopManage_2 +Rdy_A_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg Rdy_A_TM_reg0, Rdy_A_TM_reg1;$/;" r module:LDPC_TopManage_2 +Rdy_A_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg Rdy_A_TM_reg0, Rdy_A_TM_reg1;$/;" r module:LDPC_TopManage_2 +Rdy_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Rdy_B;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Rdy_B_TM hdl/LDPC_TopManage_2.v /^ input Rdy_B_TM, \/\/译码输出信号有效标志,高有效$/;" p module:LDPC_TopManage_2 +Rdy_B_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg Rdy_B_TM_reg0, Rdy_B_TM_reg1;$/;" r module:LDPC_TopManage_2 +Rdy_B_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg Rdy_B_TM_reg0, Rdy_B_TM_reg1;$/;" r module:LDPC_TopManage_2 +Rdy_TM hdl/LDPC_TopManage_2.v /^ output Rdy_TM, \/\/译码输出信号有效标志,高有效$/;" p module:LDPC_TopManage_2 Rdy_abs hdl/DAGC_v2.v /^ wire [ 0:0] Rdy_abs;$/;" n module:DAGC_v2 Rdy_b1 hdl/ApproxAbs_18bit.v /^ reg Rdy_b1 = 1'b0;$/;" r module:ApproxAbs_18bit Rdy_b1 hdl/ApproxAbs_v2.v /^ reg Rdy_b1 = 1'b0;$/;" r module:ApproxAbs_v2 @@ -1271,7 +1664,9 @@ Rdy_b5 hdl/ApproxAbs_18bit.v /^ reg Rdy_b5 = 1'b0;$/;" r module:ApproxAbs_18bit Rdy_b5 hdl/ApproxAbs_v2.v /^ reg Rdy_b5 = 1'b0;$/;" r module:ApproxAbs_v2 Receiver hdl/Receiver.v /^module Receiver ($/;" m RecvTop hdl/RecvTop.v /^module RecvTop ($/;" m -Rst hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input Rst, \/\/同步复位信号,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Rst hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ input Rst, \/\/同步复位信号,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12 +Rst hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input Rst, \/\/同步复位信号,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Rst hdl/LDPC_TopManage_2.v /^ input Rst, \/\/同步复位信号,高有效$/;" p module:LDPC_TopManage_2 SAMPLES_PER_CHANNEL adi_library/util_pack/tb/cpack_tb.v /^ parameter SAMPLES_PER_CHANNEL = 1;$/;" c module:cpack_tb SAMPLES_PER_CHANNEL adi_library/util_pack/tb/underflow_tb.v /^ parameter SAMPLES_PER_CHANNEL = 4;$/;" c module:upack2_underflow_tb SAMPLES_PER_CHANNEL adi_library/util_pack/tb/upack_tb.v /^ parameter SAMPLES_PER_CHANNEL = 1;$/;" c module:upack_tb @@ -1288,15 +1683,14 @@ SAMPLE_DATA_WIDTH adi_library/util_pack/util_upack2/util_upack2.v /^ parameter SAMPLE_DATA_WIDTH adi_library/util_pack/util_upack2/util_upack2_impl.v /^ parameter SAMPLE_DATA_WIDTH = 16$/;" c module:util_upack2_impl SCALE_ONLY adi_library/common/ad_iqcor.v /^ parameter SCALE_ONLY = 0,$/;" c module:ad_iqcor SCFDE_recv_FrameSync hdl/SCFDE_recv_FrameSync.v /^module SCFDE_recv_FrameSync ($/;" m -SCFDE_recv_FrameSync_inst hdl/RecvTop.v /^ SCFDE_recv_FrameSync SCFDE_recv_FrameSync_inst ($/;" i module:RecvTop typeref:module:SCFDE_recv_FrameSync -SC_FDE_TOP hdl/SC_FDE_TOP.v /^module SC_FDE_TOP($/;" m +SC_FDE_TOP hdl/SC_FDE_TOP.v /^module SC_FDE_TOP ($/;" m SC_FDE_TOP_djy hdl/RecvTop.v /^ SC_FDE_TOP SC_FDE_TOP_djy ($/;" i module:RecvTop typeref:module:SC_FDE_TOP SC_FDE_commul hdl/data_equalizer.v /^ SC_FDE_commul SC_FDE_commul ($/;" i module:data_equalizer typeref:module:SC_FDE_commul -SC_FDE_douti hdl/RecvTop.v /^ output [ 9:0] SC_FDE_douti, \/\/SC_FDE输出$/;" p module:RecvTop -SC_FDE_douti hdl/SC_FDE_TOP.v /^ output [9:0] SC_FDE_douti,$/;" p module:SC_FDE_TOP +SC_FDE_douti hdl/RecvTop.v /^ wire [ 9:0] SC_FDE_douti; \/\/SC_FDE输出$/;" n module:RecvTop +SC_FDE_douti hdl/SC_FDE_TOP.v /^ output [9:0] SC_FDE_douti,$/;" p module:SC_FDE_TOP SC_FDE_douti hdl/data_equalizer.v /^ output reg [9:0] SC_FDE_douti = 10'd0,$/;" p module:data_equalizer -SC_FDE_doutq hdl/RecvTop.v /^ output [ 9:0] SC_FDE_doutq,$/;" p module:RecvTop -SC_FDE_doutq hdl/SC_FDE_TOP.v /^ output [9:0] SC_FDE_doutq,$/;" p module:SC_FDE_TOP +SC_FDE_doutq hdl/RecvTop.v /^ wire [ 9:0] SC_FDE_doutq;$/;" n module:RecvTop +SC_FDE_doutq hdl/SC_FDE_TOP.v /^ output [9:0] SC_FDE_doutq,$/;" p module:SC_FDE_TOP SC_FDE_doutq hdl/data_equalizer.v /^ output reg [9:0] SC_FDE_doutq = 10'd0,$/;" p module:data_equalizer SDI_DELAY adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ parameter [1:0] SDI_DELAY = 2'b00) ($/;" c module:spi_engine_execution SDI_FIFO_ADDRESS_WIDTH adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter SDI_FIFO_ADDRESS_WIDTH = 5,$/;" c module:axi_spi_engine @@ -1324,6 +1718,7 @@ SINGLE_ENDED adi_library/xilinx/common/ad_data_in.v /^ parameter SINGLE_ENDED SINGLE_ENDED adi_library/xilinx/common/ad_data_out.v /^ parameter SINGLE_ENDED = 0,$/;" c module:ad_data_out SLAVE_DATA_WIDTH adi_library/util_axis_resize/util_axis_resize.v /^ parameter SLAVE_DATA_WIDTH = 64,$/;" c module:util_axis_resize SLOT_LEN hdl/tdma.v /^ parameter SLOT_LEN = 1250000,$/;" c module:tdma +SLOT_TIME hdl/net_city.v /^ localparam SLOT_TIME = 750000; \/\/ 15ms$/;" c module:net_city SPEED_GRADE adi_library/common/up_adc_common.v /^ parameter [ 7:0] SPEED_GRADE = 0,$/;" c module:up_adc_common SPEED_GRADE adi_library/common/up_clkgen.v /^ parameter [ 7:0] SPEED_GRADE = 0,$/;" c module:up_clkgen SPEED_GRADE adi_library/common/up_dac_common.v /^ parameter [ 7:0] SPEED_GRADE = 0,$/;" c module:up_dac_common @@ -1390,9 +1785,9 @@ S_WAIT_GAP hdl/Transmitter.v /^ localparam [3:0] S_WAIT_GAP = 4'd6; \/\/ wai S_WAIT_HOP hdl/Transmitter.v /^ localparam [3:0] S_WAIT_HOP = 4'd5;$/;" c module:Transmitter S_WAIT_LDPC_OUT hdl/enc_control.v /^ localparam [3:0] S_WAIT_LDPC_OUT = 4'd2;$/;" c module:enc_control Scramble hdl/FrameMerge.v /^ Scramble Scramble ($/;" i module:FrameMerge typeref:module:Scramble +Switch_VN_CN hdl/LDPC_DEC_PRO.v /^ reg Switch_VN_CN = 1'd0;$/;" r module:LDPC_DEC_PRO Sync_i hdl/SCFDE_recv_FrameSync.v /^ output reg [9:0] Sync_i = 10'd0,$/;" p module:SCFDE_recv_FrameSync Sync_q hdl/SCFDE_recv_FrameSync.v /^ output reg [9:0] Sync_q = 10'd0,$/;" p module:SCFDE_recv_FrameSync -Sync_rdy hdl/RecvTop.v /^ wire Sync_rdy;$/;" n module:RecvTop Sync_rdy hdl/SCFDE_recv_FrameSync.v /^ output reg Sync_rdy = 1'b0, \/\/判断出峰的标志位，出峰后拉高1c/;" p module:SCFDE_recv_FrameSync TB_sys sim/TB_sys.v /^module TB_sys ();$/;" m TDD_SYNC_PERIOD adi_library/util_tdd_sync/util_tdd_sync.v /^ parameter TDD_SYNC_PERIOD = 100000000) ($/;" c module:util_tdd_sync @@ -1402,7 +1797,7 @@ TIMEOUT adi_library/axi_dmac/tb/regmap_tb.v /^ `define TIMEOUT 1000000$/;" d mo TIMEOUT adi_library/axi_dmac/tb/reset_manager_tb.v /^ `define TIMEOUT 1000000$/;" d module:dmac_reset_manager_tb TIMEOUT adi_library/util_pack/tb/cpack_tb.v /^ `define TIMEOUT 1500000$/;" d module:cpack_tb TIMEOUT adi_library/util_pack/tb/upack_tb.v /^ `define TIMEOUT 1500000$/;" d module:upack_tb -TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ TM ($/;" i module:CCSDS_LDPC_DEC_K1024_R12_TOPP typeref:module:LDPC_TopManage_2 +TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ ) TM ($/;" i module:CCSDS_LDPC_DEC_K1024_R12_TOPP typeref:module:LDPC_TopManage_2 TOTAL_DATA_WIDTH adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ localparam TOTAL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;$/;" c module:util_cpack2_impl TOTAL_DATA_WIDTH adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam TOTAL_DATA_WIDTH = PORT_DATA_WIDTH * NUM_PORTS;$/;" c module:pack_interconnect TOTAL_DATA_WIDTH adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam TOTAL_DATA_WIDTH = CHANNEL_DATA_WIDTH * NUM_OF_CHANNELS;$/;" c module:pack_shell @@ -1501,7 +1896,197 @@ VERSION adi_library/common/up_adc_common.v /^ localparam VERSION = 32'h000a016 VERSION adi_library/common/up_dac_common.v /^ localparam VERSION = 32'h00090162;$/;" c module:up_dac_common VERSION adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ localparam [31:0] VERSION = 32'h00110161;$/;" c module:axi_adxcvr_up VERSION adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ localparam [31:0] VERSION = 32'h00100161;$/;" c module:axi_xcvrlb -WIDTH hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ parameter WIDTH = 4'd8, \/\/量化比特$/;" c module:CCSDS_LDPC_DEC_K1024_R12_TOPP +VN1_addr_rd_01_00 hdl/CN_PRO.v /^ output reg [8:0] VN1_addr_rd_01_00=9'd511,$/;" p module:CN_PRO +VN1_addr_rd_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN1_addr_rd_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN1_addr_rd_01_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN1_addr_rd_01_00_CN;$/;" n module:LDPC_DEC_PRO +VN1_addr_rd_02_00 hdl/CN_PRO.v /^ output reg [9:0] VN1_addr_rd_02_00=10'd1023,$/;" p module:CN_PRO +VN1_addr_rd_02_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN1_addr_rd_02_00_CN;$/;" n module:LDPC_DEC_PRO +VN1_addr_rd_02_01 hdl/CN_PRO.v /^ output reg [9:0] VN1_addr_rd_02_01=10'd511,$/;" p module:CN_PRO +VN1_addr_rd_02_01_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN1_addr_rd_02_01_CN;$/;" n module:LDPC_DEC_PRO +VN1_addr_wr_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN1_addr_wr_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN1_addr_wr_01_00 hdl/VN_PRO.v /^ output reg [8:0] VN1_addr_wr_01_00=9'd511,$/;" p module:VN_PRO +VN1_addr_wr_01_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN1_addr_wr_01_00_VN;$/;" n module:LDPC_DEC_PRO +VN1_addr_wr_02_00 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] VN1_addr_wr_02_00 = 10'd1023;$/;" r module:LDPC_DEC_PRO +VN1_addr_wr_02_00 hdl/VN_PRO.v /^ output reg [9:0] VN1_addr_wr_02_00=10'd1023,$/;" p module:VN_PRO +VN1_addr_wr_02_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN1_addr_wr_02_00_VN;$/;" n module:LDPC_DEC_PRO +VN1_addr_wr_02_01 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] VN1_addr_wr_02_01 = 10'd511;$/;" r module:LDPC_DEC_PRO +VN1_addr_wr_02_01 hdl/VN_PRO.v /^ output reg [9:0] VN1_addr_wr_02_01=10'd511,$/;" p module:VN_PRO +VN1_addr_wr_02_01_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN1_addr_wr_02_01_VN;$/;" n module:LDPC_DEC_PRO +VN1_din_01_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN1_din_01_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN1_din_01_00 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN1_din_01_00=8'd0,$/;" p module:VN_PRO +VN1_din_01_00_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN1_din_01_00_VN;$/;" n module:LDPC_DEC_PRO +VN1_din_02_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN1_din_02_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN1_din_02_00 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN1_din_02_00=8'd0,$/;" p module:VN_PRO +VN1_din_02_00_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN1_din_02_00_VN;$/;" n module:LDPC_DEC_PRO +VN1_din_02_01 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN1_din_02_01 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN1_din_02_01 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN1_din_02_01=8'd0,$/;" p module:VN_PRO +VN1_din_02_01_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN1_din_02_01_VN;$/;" n module:LDPC_DEC_PRO +VN1_dout_01_00 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN1_dout_01_00, $/;" p module:CN_PRO +VN1_dout_01_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN1_dout_01_00;$/;" n module:LDPC_DEC_PRO +VN1_dout_01_00_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN1_dout_01_00_CN = 8'd0;$/;" r module:LDPC_DEC_PRO +VN1_dout_02_00 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN1_dout_02_00, \/\/后面的00代表H阵原模图的IM$/;" p module:CN_PRO +VN1_dout_02_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN1_dout_02_00; \/\/后面的00代表H阵原模图的IM$/;" n module:LDPC_DEC_PRO +VN1_dout_02_00_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN1_dout_02_00_CN = 8'd0; \/\/后面的00代表H阵原模图的IM$/;" r module:LDPC_DEC_PRO +VN1_dout_02_01 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN1_dout_02_01, \/\/后面的01代表H阵原模图的II1$/;" p module:CN_PRO +VN1_dout_02_01 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN1_dout_02_01; \/\/后面的01代表H阵原模图的II1$/;" n module:LDPC_DEC_PRO +VN1_dout_02_01_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN1_dout_02_01_CN = 8'd0; \/\/后面的01代表H阵原模图的II1$/;" r module:LDPC_DEC_PRO +VN2_addr_rd_01_00 hdl/CN_PRO.v /^ output reg [8:0] VN2_addr_rd_01_00=9'd511,$/;" p module:CN_PRO +VN2_addr_rd_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN2_addr_rd_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN2_addr_rd_01_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN2_addr_rd_01_00_CN;$/;" n module:LDPC_DEC_PRO +VN2_addr_rd_02_00 hdl/CN_PRO.v /^ output reg [8:0] VN2_addr_rd_02_00=9'd511,$/;" p module:CN_PRO +VN2_addr_rd_02_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN2_addr_rd_02_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN2_addr_rd_02_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN2_addr_rd_02_00_CN;$/;" n module:LDPC_DEC_PRO +VN2_addr_rd_03_00 hdl/CN_PRO.v /^ output reg [8:0] VN2_addr_rd_03_00=9'd511,$/;" p module:CN_PRO +VN2_addr_rd_03_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN2_addr_rd_03_00 = 9'd511; \/\/7.23 xhx 同CN_RAM读地址$/;" r module:LDPC_DEC_PRO +VN2_addr_rd_03_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN2_addr_rd_03_00_CN;$/;" n module:LDPC_DEC_PRO +VN2_addr_rd_04_02 hdl/CN_PRO.v /^ output reg [9:0] VN2_addr_rd_04_02=10'd1023,$/;" p module:CN_PRO +VN2_addr_rd_04_02_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN2_addr_rd_04_02_CN;$/;" n module:LDPC_DEC_PRO +VN2_addr_rd_04_03 hdl/CN_PRO.v /^ output reg [9:0] VN2_addr_rd_04_03=10'd511,$/;" p module:CN_PRO +VN2_addr_rd_04_03_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN2_addr_rd_04_03_CN;$/;" n module:LDPC_DEC_PRO +VN2_addr_rd_04_04 hdl/CN_PRO.v /^ output reg [8:0] VN2_addr_rd_04_04=9'd511,$/;" p module:CN_PRO +VN2_addr_rd_04_04 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN2_addr_rd_04_04 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN2_addr_rd_04_04_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN2_addr_rd_04_04_CN;$/;" n module:LDPC_DEC_PRO +VN2_addr_wr_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN2_addr_wr_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN2_addr_wr_01_00 hdl/VN_PRO.v /^ output reg [8:0] VN2_addr_wr_01_00=9'd511,$/;" p module:VN_PRO +VN2_addr_wr_01_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN2_addr_wr_01_00_VN;$/;" n module:LDPC_DEC_PRO +VN2_addr_wr_02_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN2_addr_wr_02_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN2_addr_wr_02_00 hdl/VN_PRO.v /^ output reg [8:0] VN2_addr_wr_02_00=9'd511,$/;" p module:VN_PRO +VN2_addr_wr_02_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN2_addr_wr_02_00_VN;$/;" n module:LDPC_DEC_PRO +VN2_addr_wr_03_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN2_addr_wr_03_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN2_addr_wr_03_00 hdl/VN_PRO.v /^ output reg [8:0] VN2_addr_wr_03_00=9'd511,$/;" p module:VN_PRO +VN2_addr_wr_03_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN2_addr_wr_03_00_VN;$/;" n module:LDPC_DEC_PRO +VN2_addr_wr_04_02 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] VN2_addr_wr_04_02 = 10'd1023;$/;" r module:LDPC_DEC_PRO +VN2_addr_wr_04_02 hdl/VN_PRO.v /^ output reg [9:0] VN2_addr_wr_04_02=10'd1023,$/;" p module:VN_PRO +VN2_addr_wr_04_02_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN2_addr_wr_04_02_VN;$/;" n module:LDPC_DEC_PRO +VN2_addr_wr_04_03 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] VN2_addr_wr_04_03 = 10'd511;$/;" r module:LDPC_DEC_PRO +VN2_addr_wr_04_03 hdl/VN_PRO.v /^ output reg [9:0] VN2_addr_wr_04_03=10'd511,$/;" p module:VN_PRO +VN2_addr_wr_04_03_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN2_addr_wr_04_03_VN;$/;" n module:LDPC_DEC_PRO +VN2_addr_wr_04_04 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN2_addr_wr_04_04 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN2_addr_wr_04_04 hdl/VN_PRO.v /^ output reg [8:0] VN2_addr_wr_04_04=9'd511,$/;" p module:VN_PRO +VN2_addr_wr_04_04_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN2_addr_wr_04_04_VN;$/;" n module:LDPC_DEC_PRO +VN2_din_01_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_din_01_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN2_din_01_00 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN2_din_01_00=8'd0,$/;" p module:VN_PRO +VN2_din_01_00_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_din_01_00_VN;$/;" n module:LDPC_DEC_PRO +VN2_din_02_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_din_02_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN2_din_02_00 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN2_din_02_00=8'd0,$/;" p module:VN_PRO +VN2_din_02_00_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_din_02_00_VN;$/;" n module:LDPC_DEC_PRO +VN2_din_03_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_din_03_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN2_din_03_00 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN2_din_03_00=8'd0,$/;" p module:VN_PRO +VN2_din_03_00_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_din_03_00_VN;$/;" n module:LDPC_DEC_PRO +VN2_din_04_02 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_din_04_02 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN2_din_04_02 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN2_din_04_02=8'd0,$/;" p module:VN_PRO +VN2_din_04_02_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_din_04_02_VN;$/;" n module:LDPC_DEC_PRO +VN2_din_04_03 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_din_04_03 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN2_din_04_03 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN2_din_04_03=8'd0,$/;" p module:VN_PRO +VN2_din_04_03_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_din_04_03_VN;$/;" n module:LDPC_DEC_PRO +VN2_din_04_04 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_din_04_04 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN2_din_04_04 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN2_din_04_04=8'd0,$/;" p module:VN_PRO +VN2_din_04_04_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_din_04_04_VN;$/;" n module:LDPC_DEC_PRO +VN2_dout_01_00 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN2_dout_01_00,$/;" p module:CN_PRO +VN2_dout_01_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_dout_01_00;$/;" n module:LDPC_DEC_PRO +VN2_dout_01_00_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_dout_01_00_CN = 8'd0;$/;" r module:LDPC_DEC_PRO +VN2_dout_02_00 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN2_dout_02_00,$/;" p module:CN_PRO +VN2_dout_02_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_dout_02_00;$/;" n module:LDPC_DEC_PRO +VN2_dout_02_00_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_dout_02_00_CN = 8'd0;$/;" r module:LDPC_DEC_PRO +VN2_dout_03_00 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN2_dout_03_00,$/;" p module:CN_PRO +VN2_dout_03_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_dout_03_00;$/;" n module:LDPC_DEC_PRO +VN2_dout_03_00_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_dout_03_00_CN = 8'd0;$/;" r module:LDPC_DEC_PRO +VN2_dout_04_02 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN2_dout_04_02, \/\/后面的02代表H阵原模图的II2$/;" p module:CN_PRO +VN2_dout_04_02 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_dout_04_02; \/\/后面的02代表H阵原模图的II2$/;" n module:LDPC_DEC_PRO +VN2_dout_04_02_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_dout_04_02_CN = 8'd0; \/\/后面的02代表H阵原模图的II2$/;" r module:LDPC_DEC_PRO +VN2_dout_04_03 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN2_dout_04_03, \/\/后面的03代表H阵原模图的II3$/;" p module:CN_PRO +VN2_dout_04_03 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_dout_04_03; \/\/后面的03代表H阵原模图的II3$/;" n module:LDPC_DEC_PRO +VN2_dout_04_03_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_dout_04_03_CN = 8'd0; \/\/后面的03代表H阵原模图的II3$/;" r module:LDPC_DEC_PRO +VN2_dout_04_04 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN2_dout_04_04, \/\/后面的04代表H阵原模图的II4$/;" p module:CN_PRO +VN2_dout_04_04 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN2_dout_04_04; \/\/后面的04代表H阵原模图的II4$/;" n module:LDPC_DEC_PRO +VN2_dout_04_04_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN2_dout_04_04_CN = 8'd0; \/\/后面的04代表H阵原模图的II4$/;" r module:LDPC_DEC_PRO +VN3_addr_rd_01_00 hdl/CN_PRO.v /^ output reg [8:0] VN3_addr_rd_01_00=9'd511,$/;" p module:CN_PRO +VN3_addr_rd_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN3_addr_rd_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN3_addr_rd_01_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN3_addr_rd_01_00_CN;$/;" n module:LDPC_DEC_PRO +VN3_addr_rd_02_05 hdl/CN_PRO.v /^ output reg [9:0] VN3_addr_rd_02_05=10'd1023,$/;" p module:CN_PRO +VN3_addr_rd_02_05_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN3_addr_rd_02_05_CN;$/;" n module:LDPC_DEC_PRO +VN3_addr_rd_02_06 hdl/CN_PRO.v /^ output reg [9:0] VN3_addr_rd_02_06=10'd511,$/;" p module:CN_PRO +VN3_addr_rd_02_06_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN3_addr_rd_02_06_CN;$/;" n module:LDPC_DEC_PRO +VN3_addr_rd_03_07 hdl/CN_PRO.v /^ output reg [9:0] VN3_addr_rd_03_07=10'd1023,$/;" p module:CN_PRO +VN3_addr_rd_03_07_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN3_addr_rd_03_07_CN;$/;" n module:LDPC_DEC_PRO +VN3_addr_rd_03_08 hdl/CN_PRO.v /^ output reg [9:0] VN3_addr_rd_03_08=10'd511,$/;" p module:CN_PRO +VN3_addr_rd_03_08_CN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN3_addr_rd_03_08_CN;$/;" n module:LDPC_DEC_PRO +VN3_addr_rd_04_00 hdl/CN_PRO.v /^ output reg [8:0] VN3_addr_rd_04_00=9'd511,$/;" p module:CN_PRO +VN3_addr_rd_04_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN3_addr_rd_04_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN3_addr_rd_04_00_CN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN3_addr_rd_04_00_CN;$/;" n module:LDPC_DEC_PRO +VN3_addr_wr_01_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN3_addr_wr_01_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN3_addr_wr_01_00 hdl/VN_PRO.v /^ output reg [8:0] VN3_addr_wr_01_00=9'd511,$/;" p module:VN_PRO +VN3_addr_wr_01_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN3_addr_wr_01_00_VN;$/;" n module:LDPC_DEC_PRO +VN3_addr_wr_02_05 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] VN3_addr_wr_02_05 = 10'd1023;$/;" r module:LDPC_DEC_PRO +VN3_addr_wr_02_05 hdl/VN_PRO.v /^ output reg [9:0] VN3_addr_wr_02_05=10'd1023,$/;" p module:VN_PRO +VN3_addr_wr_02_05_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN3_addr_wr_02_05_VN;$/;" n module:LDPC_DEC_PRO +VN3_addr_wr_02_06 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] VN3_addr_wr_02_06 = 10'd511;$/;" r module:LDPC_DEC_PRO +VN3_addr_wr_02_06 hdl/VN_PRO.v /^ output reg [9:0] VN3_addr_wr_02_06=10'd511,$/;" p module:VN_PRO +VN3_addr_wr_02_06_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN3_addr_wr_02_06_VN;$/;" n module:LDPC_DEC_PRO +VN3_addr_wr_03_07 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] VN3_addr_wr_03_07 = 10'd1023;$/;" r module:LDPC_DEC_PRO +VN3_addr_wr_03_07 hdl/VN_PRO.v /^ output reg [9:0] VN3_addr_wr_03_07=10'd1023,$/;" p module:VN_PRO +VN3_addr_wr_03_07_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN3_addr_wr_03_07_VN;$/;" n module:LDPC_DEC_PRO +VN3_addr_wr_03_08 hdl/LDPC_DEC_PRO.v /^ reg [ 9:0] VN3_addr_wr_03_08 = 10'd511;$/;" r module:LDPC_DEC_PRO +VN3_addr_wr_03_08 hdl/VN_PRO.v /^ output reg [9:0] VN3_addr_wr_03_08=10'd511,$/;" p module:VN_PRO +VN3_addr_wr_03_08_VN hdl/LDPC_DEC_PRO.v /^ wire [ 9:0] VN3_addr_wr_03_08_VN;$/;" n module:LDPC_DEC_PRO +VN3_addr_wr_04_00 hdl/LDPC_DEC_PRO.v /^ reg [ 8:0] VN3_addr_wr_04_00 = 9'd511;$/;" r module:LDPC_DEC_PRO +VN3_addr_wr_04_00 hdl/VN_PRO.v /^ output reg [8:0] VN3_addr_wr_04_00=9'd511,$/;" p module:VN_PRO +VN3_addr_wr_04_00_VN hdl/LDPC_DEC_PRO.v /^ wire [ 8:0] VN3_addr_wr_04_00_VN;$/;" n module:LDPC_DEC_PRO +VN3_din_01_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_din_01_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN3_din_01_00 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN3_din_01_00=8'd0,$/;" p module:VN_PRO +VN3_din_01_00_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_din_01_00_VN;$/;" n module:LDPC_DEC_PRO +VN3_din_02_05 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_din_02_05 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN3_din_02_05 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN3_din_02_05=8'd0,$/;" p module:VN_PRO +VN3_din_02_05_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_din_02_05_VN;$/;" n module:LDPC_DEC_PRO +VN3_din_02_06 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_din_02_06 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN3_din_02_06 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN3_din_02_06=8'd0,$/;" p module:VN_PRO +VN3_din_02_06_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_din_02_06_VN;$/;" n module:LDPC_DEC_PRO +VN3_din_03_07 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_din_03_07 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN3_din_03_07 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN3_din_03_07=8'd0,$/;" p module:VN_PRO +VN3_din_03_07_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_din_03_07_VN;$/;" n module:LDPC_DEC_PRO +VN3_din_03_08 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_din_03_08 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN3_din_03_08 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN3_din_03_08=8'd0,$/;" p module:VN_PRO +VN3_din_03_08_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_din_03_08_VN;$/;" n module:LDPC_DEC_PRO +VN3_din_04_00 hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_din_04_00 = 8'd0;$/;" r module:LDPC_DEC_PRO +VN3_din_04_00 hdl/VN_PRO.v /^ output reg [WIDTH-1:0] VN3_din_04_00=8'd0,$/;" p module:VN_PRO +VN3_din_04_00_VN hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_din_04_00_VN;$/;" n module:LDPC_DEC_PRO +VN3_dout_01_00 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN3_dout_01_00,$/;" p module:CN_PRO +VN3_dout_01_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_dout_01_00;$/;" n module:LDPC_DEC_PRO +VN3_dout_01_00_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_dout_01_00_CN = 8'd0;$/;" r module:LDPC_DEC_PRO +VN3_dout_02_05 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN3_dout_02_05, \/\/后面的05代表H阵原模图的II5$/;" p module:CN_PRO +VN3_dout_02_05 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_dout_02_05; \/\/后面的05代表H阵原模图的II5$/;" n module:LDPC_DEC_PRO +VN3_dout_02_05_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_dout_02_05_CN = 8'd0; \/\/后面的05代表H阵原模图的II5$/;" r module:LDPC_DEC_PRO +VN3_dout_02_06 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN3_dout_02_06, \/\/后面的06代表H阵原模图的II6$/;" p module:CN_PRO +VN3_dout_02_06 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_dout_02_06; \/\/后面的06代表H阵原模图的II6$/;" n module:LDPC_DEC_PRO +VN3_dout_02_06_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_dout_02_06_CN = 8'd0; \/\/后面的06代表H阵原模图的II6$/;" r module:LDPC_DEC_PRO +VN3_dout_03_07 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN3_dout_03_07, \/\/后面的07代表H阵原模图的II7$/;" p module:CN_PRO +VN3_dout_03_07 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_dout_03_07; \/\/后面的07代表H阵原模图的II7$/;" n module:LDPC_DEC_PRO +VN3_dout_03_07_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_dout_03_07_CN = 8'd0; \/\/后面的07代表H阵原模图的II7$/;" r module:LDPC_DEC_PRO +VN3_dout_03_08 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN3_dout_03_08, \/\/后面的08代表H阵原模图的II8$/;" p module:CN_PRO +VN3_dout_03_08 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_dout_03_08; \/\/后面的08代表H阵原模图的II8$/;" n module:LDPC_DEC_PRO +VN3_dout_03_08_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_dout_03_08_CN = 8'd0; \/\/后面的08代表H阵原模图的II8$/;" r module:LDPC_DEC_PRO +VN3_dout_04_00 hdl/CN_PRO.v /^ input [WIDTH-1:0] VN3_dout_04_00,$/;" p module:CN_PRO +VN3_dout_04_00 hdl/LDPC_DEC_PRO.v /^ wire [WIDTH-1:0] VN3_dout_04_00;$/;" n module:LDPC_DEC_PRO +VN3_dout_04_00_CN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] VN3_dout_04_00_CN = 8'd0;$/;" r module:LDPC_DEC_PRO +VNU_1din hdl/VNU_1din.v /^module VNU_1din($/;" m +VNU_2din hdl/VNU_2din.v /^module VNU_2din(\/\/注意：所有的输入数据同时进来本模块，即数据clk是对齐的$/;" m +VNU_3din hdl/VNU_3din.v /^module VNU_3din($/;" m +VNU_6din hdl/VNU_6din.v /^module VNU_6din($/;" m +VN_PRO hdl/VN_PRO.v /^module VN_PRO$/;" m +VN_wea hdl/LDPC_DEC_PRO.v /^ reg VN_wea = 1'd0;$/;" r module:LDPC_DEC_PRO +VN_wea hdl/VN_PRO.v /^ output reg [0:0] VN_wea=1'd0,$/;" p module:VN_PRO +VN_wea_VN hdl/LDPC_DEC_PRO.v /^ wire VN_wea_VN;$/;" n module:LDPC_DEC_PRO +WIDTH hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ parameter WIDTH = 4'd8,$/;" c module:CCSDS_LDPC_DEC_K1024_R12 +WIDTH hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ parameter WIDTH = 4'd8, \/\/量化比特$/;" c module:CCSDS_LDPC_DEC_K1024_R12_TOPP +WIDTH hdl/CNU_3din.v /^ #(parameter WIDTH = 4'd8)($/;" c module:CNU_3din +WIDTH hdl/CNU_6din.v /^ #(parameter WIDTH = 4'd8)$/;" c module:CNU_6din +WIDTH hdl/CN_PRO.v /^ parameter WIDTH = 4'd8$/;" c module:CN_PRO +WIDTH hdl/LDPC_DEC_PRO.v /^ parameter WIDTH = 4'd8,$/;" c module:LDPC_DEC_PRO +WIDTH hdl/LDPC_TopManage_2.v /^ parameter WIDTH = 4'd8$/;" c module:LDPC_TopManage_2 +WIDTH hdl/Message_Store.v /^ parameter WIDTH = 4'd8$/;" c module:Message_Store +WIDTH hdl/Normalization_Factor_0_8125.v /^ parameter WIDTH = 4'd8$/;" c module:Normalization_Factor_0_8125 +WIDTH hdl/VN_PRO.v /^ parameter WIDTH = 4'd8$/;" c module:VN_PRO +WIDTH hdl/abs_min_4din.v /^ parameter WIDTH = 4'd8$/;" c module:abs_min_4din WIDTH hdl/add_prefix.v /^ parameter WIDTH = 2,$/;" c module:add_prefix WIDTH_DEST adi_library/axi_dmac/tb/dma_read_tb.v /^ parameter WIDTH_DEST = 32;$/;" c module:dmac_dma_read_tb WIDTH_DEST adi_library/axi_dmac/tb/dma_write_tb.v /^ parameter WIDTH_DEST = 32;$/;" c module:dmac_dma_write_tb @@ -1537,7 +2122,8 @@ X_FSCALE adi_library/common/ad_dds_sine_cordic.v /^ localparam X_FSCALE = 1 << X_VALUE adi_library/common/ad_dds_sine_cordic.v /^ localparam [CORDIC_DW-1:0] X_VALUE = ((X_FSCALE\/2)\/(1.64676))-APROX_DW_GAIN_ERR;$/;" c module:ad_dds_sine_cordic YCbCr_2_RGB adi_library/common/ad_csc.v /^ parameter YCbCr_2_RGB = 0) ($/;" c module:ad_csc Zerozone_vio hdl/Chn_Estimate.v /^ input [7:0] Zerozone_vio,$/;" p module:Chn_Estimate -Zerozone_vio hdl/SC_FDE_TOP.v /^ input [7:0] Zerozone_vio, \/\/零域估计，默认值为8'd29$/;" p module:SC_FDE_TOP +Zerozone_vio hdl/RecvTop.v /^ input [ 7:0] Zerozone_vio, \/\/零域估计，默认值为8'd29$/;" p module:RecvTop +Zerozone_vio hdl/SC_FDE_TOP.v /^ input [7:0] Zerozone_vio, \/\/零域估计，默认值为8'd29$/;" p module:SC_FDE_TOP _dest_diag_level_bursts adi_library/axi_dmac/axi_dmac_burst_memory.v /^ reg [ID_WIDTH-1:0] _dest_diag_level_bursts = 'h0;$/;" r module:axi_dmac_burst_memory _m_axis_level adi_library/util_axis_fifo/util_axis_fifo.v /^ wire [ADDRESS_WIDTH:0] _m_axis_level;$/;" n module:util_axis_fifo _m_axis_raddr adi_library/util_axis_fifo/address_gray.v /^reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;$/;" r module:fifo_address_gray @@ -1556,13 +2142,56 @@ a adi_library/axi_dmac/request_arb.v /^ input [ID_WIDTH-1:0] a;$/;" p function: abort_req adi_library/axi_dmac/axi_dmac_transfer.v /^wire abort_req;$/;" n module:axi_dmac_transfer abort_req adi_library/axi_dmac/request_arb.v /^ output abort_req,$/;" p module:dmac_request_arb abort_req adi_library/axi_dmac/request_generator.v /^ output abort_req,$/;" p module:dmac_request_generator +abs01 hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0;$/;" r module:CNU_3din +abs01 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0,abs01_reg2=8'd0,min_level_1_01=8'/;" r module:CNU_6din +abs01_reg0 hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0;$/;" r module:CNU_3din +abs01_reg0 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0,abs01_reg2=8'd0,min_level_1_01=8'/;" r module:CNU_6din +abs01_reg1 hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0;$/;" r module:CNU_3din +abs01_reg1 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0,abs01_reg2=8'd0,min_level_1_01=8'/;" r module:CNU_6din +abs01_reg2 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0,abs01_reg2=8'd0,min_level_1_01=8'/;" r module:CNU_6din +abs01_update hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs01_update=8'd0,abs02_update=8'd0,abs03_update=8'd0;$/;" r module:CNU_3din +abs01_update hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs01_update=8'd0;$/;" r module:CNU_6din +abs02 hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0;$/;" r module:CNU_3din +abs02 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0,abs02_reg2=8'd0,min_level_1_02=8'/;" r module:CNU_6din +abs02_reg0 hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0;$/;" r module:CNU_3din +abs02_reg0 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0,abs02_reg2=8'd0,min_level_1_02=8'/;" r module:CNU_6din +abs02_reg1 hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0;$/;" r module:CNU_3din +abs02_reg1 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0,abs02_reg2=8'd0,min_level_1_02=8'/;" r module:CNU_6din +abs02_reg2 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0,abs02_reg2=8'd0,min_level_1_02=8'/;" r module:CNU_6din +abs02_update hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs01_update=8'd0,abs02_update=8'd0,abs03_update=8'd0;$/;" r module:CNU_3din +abs02_update hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs02_update=8'd0;$/;" r module:CNU_6din +abs03 hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0;$/;" r module:CNU_3din +abs03 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0,abs03_reg2=8'd0,min_level_1_03=8'/;" r module:CNU_6din +abs03_reg0 hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0;$/;" r module:CNU_3din +abs03_reg0 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0,abs03_reg2=8'd0,min_level_1_03=8'/;" r module:CNU_6din +abs03_reg1 hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0;$/;" r module:CNU_3din +abs03_reg1 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0,abs03_reg2=8'd0,min_level_1_03=8'/;" r module:CNU_6din +abs03_reg2 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0,abs03_reg2=8'd0,min_level_1_03=8'/;" r module:CNU_6din +abs03_update hdl/CNU_3din.v /^ reg [WIDTH-1:0] abs01_update=8'd0,abs02_update=8'd0,abs03_update=8'd0;$/;" r module:CNU_3din +abs03_update hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs03_update=8'd0;$/;" r module:CNU_6din +abs04 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs04=8'd0,abs04_reg0=8'd0,abs04_reg1=8'd0,abs04_reg2=8'd0,min_level_1_04=8'/;" r module:CNU_6din +abs04_reg0 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs04=8'd0,abs04_reg0=8'd0,abs04_reg1=8'd0,abs04_reg2=8'd0,min_level_1_04=8'/;" r module:CNU_6din +abs04_reg1 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs04=8'd0,abs04_reg0=8'd0,abs04_reg1=8'd0,abs04_reg2=8'd0,min_level_1_04=8'/;" r module:CNU_6din +abs04_reg2 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs04=8'd0,abs04_reg0=8'd0,abs04_reg1=8'd0,abs04_reg2=8'd0,min_level_1_04=8'/;" r module:CNU_6din +abs04_update hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs04_update=8'd0;$/;" r module:CNU_6din +abs05 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs05=8'd0,abs05_reg0=8'd0,abs05_reg1=8'd0,abs05_reg2=8'd0,min_level_1_05=8'/;" r module:CNU_6din +abs05_reg0 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs05=8'd0,abs05_reg0=8'd0,abs05_reg1=8'd0,abs05_reg2=8'd0,min_level_1_05=8'/;" r module:CNU_6din +abs05_reg1 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs05=8'd0,abs05_reg0=8'd0,abs05_reg1=8'd0,abs05_reg2=8'd0,min_level_1_05=8'/;" r module:CNU_6din +abs05_reg2 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs05=8'd0,abs05_reg0=8'd0,abs05_reg1=8'd0,abs05_reg2=8'd0,min_level_1_05=8'/;" r module:CNU_6din +abs05_update hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs05_update=8'd0;$/;" r module:CNU_6din +abs06 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs06=8'd0,abs06_reg0=8'd0,abs06_reg1=8'd0,abs06_reg2=8'd0,min_level_1_06=8'/;" r module:CNU_6din +abs06_reg0 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs06=8'd0,abs06_reg0=8'd0,abs06_reg1=8'd0,abs06_reg2=8'd0,min_level_1_06=8'/;" r module:CNU_6din +abs06_reg1 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs06=8'd0,abs06_reg0=8'd0,abs06_reg1=8'd0,abs06_reg2=8'd0,min_level_1_06=8'/;" r module:CNU_6din +abs06_reg2 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs06=8'd0,abs06_reg0=8'd0,abs06_reg1=8'd0,abs06_reg2=8'd0,min_level_1_06=8'/;" r module:CNU_6din +abs06_update hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs06_update=8'd0;$/;" r module:CNU_6din abs_ZF hdl/Chn_Estimate.v /^wire [18:0] abs_ZF;$/;" n module:Chn_Estimate abs_ZF_nd hdl/Chn_Estimate.v /^wire abs_ZF_nd;$/;" n module:Chn_Estimate -abs_check hdl/RecvTop.v /^ output [10:0] abs_check,$/;" p module:RecvTop +abs_check hdl/RecvTop.v /^ wire [10:0] abs_check;$/;" n module:RecvTop abs_i hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] abs_i;$/;" r module:MagnitudeEstimator +abs_min_4din hdl/abs_min_4din.v /^module abs_min_4din #($/;" m abs_pilot2 hdl/Chn_Estimate.v /^abs_pilot2 abs_pilot2 ($/;" i module:Chn_Estimate typeref:module:abs_pilot2 abs_q hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] abs_q;$/;" r module:MagnitudeEstimator -abs_ref hdl/RecvTop.v /^ output [10:0] abs_ref,$/;" p module:RecvTop +abs_ref hdl/RecvTop.v /^ wire [10:0] abs_ref;$/;" n module:RecvTop acc1 adi_library/common/util_dec256sinc24b.v /^ reg [36:0] acc1 = 37'h0;$/;" r module:util_dec256sinc24b acc1_s adi_library/common/util_dec256sinc24b.v /^ wire [36:0] acc1_s;$/;" n module:util_dec256sinc24b acc2 adi_library/common/util_dec256sinc24b.v /^ reg [36:0] acc2 = 37'h0;$/;" r module:util_dec256sinc24b @@ -1612,7 +2241,7 @@ acc_16 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_16 = 20'd0;$/;" r module:TSync_Ab acc_16_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_16_reg = 20'd0;$/;" r module:TSync_Abs_new16 acc_com_i hdl/freqestm.v /^ reg [31:0] acc_com_i;$/;" r module:freqestm acc_com_q hdl/freqestm.v /^ reg [31:0] acc_com_q;$/;" r module:freqestm -acc_mean hdl/RecvTop.v /^ output [12:0] acc_mean,$/;" p module:RecvTop +acc_mean hdl/RecvTop.v /^ wire [12:0] acc_mean;$/;" n module:RecvTop acc_rdy hdl/freqestm.v /^ reg acc_rdy;$/;" r module:freqestm acked adi_library/axi_dmac/splitter.v /^reg [NUM_M-1:0] acked;$/;" r module:splitter aclk adi_library/util_fir_dec/util_fir_dec.v /^ input aclk,$/;" p module:util_fir_dec @@ -1625,7 +2254,7 @@ active adi_library/axi_dmac/dest_fifo_inf.v /^reg active = 1'b0;$/;" r module:dm active adi_library/axi_dmac/response_handler.v /^wire active = id != request_id;$/;" n module:dmac_response_handler active adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg active,$/;" p module:spi_engine_execution active adi_library/util_cic/cic_comb.v /^reg active = 1'b0;$/;" r module:cic_comb -ad9361_ctrl_in hdl/RecvTop.v /^ output [3:0] ad9361_ctrl_in,$/;" p module:RecvTop +ad9361_ctrl_in hdl/RecvTop.v /^ output [ 3:0] ad9361_ctrl_in,$/;" p module:RecvTop ad9361_ctrl_in hdl/ad9361_mgc_pin_ctrl.v /^ output wire [ 3:0] ad9361_ctrl_in,$/;" p module:ad9361_mgc_pin_ctrl ad9361_ctrl_in hdl/system_top.v /^ output wire [ 3:0] ad9361_ctrl_in, \/\/ ad9361 control in pins, for fastlock control$/;" p module:system_top ad9361_dp_fdd_1r1t hdl/ad9361_dp_fdd_1r1t.v /^module ad9361_dp_fdd_1r1t ($/;" m @@ -1635,24 +2264,31 @@ ad9361_enable hdl/system_top.v /^ output ad9361_enable, \/\/ ad9361_mgc_pin_ctrl hdl/ad9361_mgc_pin_ctrl.v /^module ad9361_mgc_pin_ctrl ($/;" m ad9361_reset_b hdl/system_top.v /^ output ad9361_reset_b, \/\/ asynchronous reset, active low$/;" p module:system_top ad9361_rx_clk hdl/system_top.v /^ input ad9361_rx_clk, \/\/ ad9361 receive data clock output$/;" p module:system_top +ad9361_rx_clk sim/tb_sys_tx_rx_e_d.v /^ reg ad9361_rx_clk = 0; \/\/ 50MHz 20ns$/;" r module:tb_sys_tx_rx_e_d ad9361_rx_clk sim/tb_tx_with_enc.v /^ reg ad9361_rx_clk = 0; \/\/ 50MHz$/;" r module:tb_tx_with_enc ad9361_rx_data hdl/system_top.v /^ input [11:0] ad9361_rx_data, \/\/ ad9361 receive data $/;" p module:system_top ad9361_rx_data_i hdl/Receiver.v /^ input [11:0] ad9361_rx_data_i,$/;" p module:Receiver ad9361_rx_data_i hdl/system_top.v /^ wire [11:0] ad9361_rx_data_i;$/;" n module:system_top ad9361_rx_data_i sim/TB_sys.v /^ wire [11:0] ad9361_rx_data_i;$/;" n module:TB_sys ad9361_rx_data_i sim/tb_Receiver.v /^ reg [11:0] ad9361_rx_data_i;$/;" r module:tb_Receiver +ad9361_rx_data_i sim/tb_recv_top.v /^ reg signed [11:0] ad9361_rx_data_i;$/;" r module:tb_recv_top +ad9361_rx_data_i sim/tb_sys_tx_rx_e_d.v /^ wire [11:0] ad9361_rx_data_i;$/;" n module:tb_sys_tx_rx_e_d ad9361_rx_data_i sim/tb_tx_with_enc.v /^ wire [11:0] ad9361_rx_data_i;$/;" n module:tb_tx_with_enc ad9361_rx_data_q hdl/Receiver.v /^ input [11:0] ad9361_rx_data_q,$/;" p module:Receiver ad9361_rx_data_q hdl/system_top.v /^ wire [11:0] ad9361_rx_data_q;$/;" n module:system_top ad9361_rx_data_q sim/TB_sys.v /^ wire [11:0] ad9361_rx_data_q;$/;" n module:TB_sys ad9361_rx_data_q sim/tb_Receiver.v /^ reg [11:0] ad9361_rx_data_q;$/;" r module:tb_Receiver +ad9361_rx_data_q sim/tb_recv_top.v /^ reg signed [11:0] ad9361_rx_data_q;$/;" r module:tb_recv_top +ad9361_rx_data_q sim/tb_sys_tx_rx_e_d.v /^ wire [11:0] ad9361_rx_data_q;$/;" n module:tb_sys_tx_rx_e_d ad9361_rx_data_q sim/tb_tx_with_enc.v /^ wire [11:0] ad9361_rx_data_q;$/;" n module:tb_tx_with_enc ad9361_rx_frame hdl/system_top.v /^ input ad9361_rx_frame, \/\/ ad9361 receive data frame output signal, indicat/;" p module:system_top ad9361_rx_frame_i hdl/system_top.v /^ wire ad9361_rx_frame_i;$/;" n module:system_top ad9361_rx_frame_i sim/TB_sys.v /^ wire ad9361_rx_frame_i;$/;" n module:TB_sys +ad9361_rx_frame_i sim/tb_sys_tx_rx_e_d.v /^ wire ad9361_rx_frame_i;$/;" n module:tb_sys_tx_rx_e_d ad9361_rx_frame_i sim/tb_tx_with_enc.v /^ wire ad9361_rx_frame_i;$/;" n module:tb_tx_with_enc ad9361_rx_frame_q hdl/system_top.v /^ wire ad9361_rx_frame_q;$/;" n module:system_top ad9361_rx_frame_q sim/TB_sys.v /^ wire ad9361_rx_frame_q;$/;" n module:TB_sys +ad9361_rx_frame_q sim/tb_sys_tx_rx_e_d.v /^ wire ad9361_rx_frame_q;$/;" n module:tb_sys_tx_rx_e_d ad9361_rx_frame_q sim/tb_tx_with_enc.v /^ wire ad9361_rx_frame_q;$/;" n module:tb_tx_with_enc ad9361_spi_clk hdl/ad9361_spi_interface.v /^ output ad9361_spi_clk,$/;" p module:ad9361_spi_interface ad9361_spi_clk hdl/system_top.v /^ output ad9361_spi_clk,$/;" p module:system_top @@ -1668,10 +2304,12 @@ ad9361_tx_data hdl/system_top.v /^ output [11:0] ad9361_tx_data, \/\ ad9361_tx_data_i hdl/Transmitter.v /^ output wire [11:0] ad9361_tx_data_i,$/;" p module:Transmitter ad9361_tx_data_i hdl/system_top.v /^ wire [11:0] ad9361_tx_data_i;$/;" n module:system_top ad9361_tx_data_i sim/TB_sys.v /^ wire [11:0] ad9361_tx_data_i;$/;" n module:TB_sys +ad9361_tx_data_i sim/tb_sys_tx_rx_e_d.v /^ wire [11:0] ad9361_tx_data_i;$/;" n module:tb_sys_tx_rx_e_d ad9361_tx_data_i sim/tb_tx_with_enc.v /^ wire [11:0] ad9361_tx_data_i;$/;" n module:tb_tx_with_enc ad9361_tx_data_q hdl/Transmitter.v /^ output wire [11:0] ad9361_tx_data_q,$/;" p module:Transmitter ad9361_tx_data_q hdl/system_top.v /^ wire [11:0] ad9361_tx_data_q;$/;" n module:system_top ad9361_tx_data_q sim/TB_sys.v /^ wire [11:0] ad9361_tx_data_q;$/;" n module:TB_sys +ad9361_tx_data_q sim/tb_sys_tx_rx_e_d.v /^ wire [11:0] ad9361_tx_data_q;$/;" n module:tb_sys_tx_rx_e_d ad9361_tx_data_q sim/tb_tx_with_enc.v /^ wire [11:0] ad9361_tx_data_q;$/;" n module:tb_tx_with_enc ad9361_tx_frame hdl/system_top.v /^ output ad9361_tx_frame, \/\/ ad9361 transmit data frame input signal, indicat/;" p module:system_top ad9361_txnrx hdl/system_top.v /^ output ad9361_txnrx, \/\/ logic low selects the RX, logic high selects the/;" p module:system_top @@ -1844,29 +2482,44 @@ addr_fft_piloti hdl/Chn_Estimate.v /^reg [7:0] addr_fft_piloti = 8'd0;$/;" r mod addr_fft_pilotq hdl/Chn_Estimate.v /^reg [7:0] addr_fft_pilotq = 8'd0;$/;" r module:Chn_Estimate addr_lut hdl/DAGC_v2.v /^ reg [10:0] addr_lut = 11'd0;$/;" r module:DAGC_v2 addr_r adi_library/util_var_fifo/util_var_fifo.v /^ output [ADDRESS_WIDTH-1:0] addr_r,$/;" p module:util_var_fifo +addr_rd1_01 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'/;" r module:Message_Store +addr_rd1_02 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'/;" r module:Message_Store +addr_rd1_03 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'/;" r module:Message_Store +addr_rd1_04 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'/;" r module:Message_Store +addr_rd2_01 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'/;" r module:Message_Store +addr_rd2_02 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'/;" r module:Message_Store +addr_rd2_03 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'/;" r module:Message_Store +addr_rd2_04 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'/;" r module:Message_Store addr_ready adi_library/axi_dmac/address_generator.v /^ input addr_ready,$/;" p module:dmac_address_generator addr_stop hdl/FrameMerge.v /^ output reg [16:0] addr_stop = 17'd0, \/\/给shx，拉高一个clk,与flag_stop对齐，指示/;" p module:FrameMerge -addr_stop hdl/RecvTop.v /^ output [16:0] addr_stop, \/\/给shx，拉高8个clk,与flag_stop对齐，指示位置与最/;" p module:RecvTop +addr_stop hdl/RecvTop.v /^ output [16:0] addr_stop, \/\/给shx，拉高8个clk,与flag_stop对齐，指示/;" p module:RecvTop addr_stop_0 hdl/FrameMerge.v /^ output [16:0] addr_stop_0, $/;" p module:FrameMerge -addr_stop_0 hdl/RecvTop.v /^ wire [16:0] addr_stop_0;$/;" n module:RecvTop addr_tx_test hdl/Transmitter.v /^ reg [12:0] addr_tx_test = 'd0;$/;" r module:Transmitter addr_valid adi_library/axi_dmac/address_generator.v /^ output reg addr_valid,$/;" p module:dmac_address_generator addr_valid_d1 adi_library/axi_dmac/address_generator.v /^reg addr_valid_d1;$/;" r module:dmac_address_generator addr_w adi_library/util_var_fifo/util_var_fifo.v /^ output [ADDRESS_WIDTH-1:0] addr_w,$/;" p module:util_var_fifo +addr_wr1_01 hdl/Message_Store.v /^ reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'/;" r module:Message_Store +addr_wr1_02 hdl/Message_Store.v /^ reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'/;" r module:Message_Store +addr_wr1_03 hdl/Message_Store.v /^ reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'/;" r module:Message_Store +addr_wr1_04 hdl/Message_Store.v /^ reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'/;" r module:Message_Store +addr_wr2_01 hdl/Message_Store.v /^ reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'/;" r module:Message_Store +addr_wr2_02 hdl/Message_Store.v /^ reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'/;" r module:Message_Store +addr_wr2_03 hdl/Message_Store.v /^ reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'/;" r module:Message_Store +addr_wr2_04 hdl/Message_Store.v /^ reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'/;" r module:Message_Store addra adi_library/common/ad_mem.v /^ input [(ADDRESS_WIDTH-1):0] addra,$/;" p module:ad_mem addra adi_library/common/ad_mem_asym.v /^ input [A_ADDRESS_WIDTH-1:0] addra,$/;" p module:ad_mem_asym addra adi_library/util_var_fifo/util_var_fifo.v /^ reg [ADDRESS_WIDTH-1:0] addra = 'd0;$/;" r module:util_var_fifo addra hdl/IQmerge.v /^ reg [9:0] addra = 10'd0;$/;" r module:IQmerge -addra hdl/phase_adjust.v /^ reg [7:0] addra = 8'd0;$/;" r module:phase_adjust +addra hdl/phase_adjust.v /^ reg [ 7:0] addra = 8'd0;$/;" r module:phase_adjust addra_pilot01 hdl/freqestm.v /^ reg [11:0] addra_pilot01;$/;" r module:freqestm addra_pilot02 hdl/freqestm.v /^ reg [11:0] addra_pilot02;$/;" r module:freqestm addradelay hdl/IQmerge.v /^ reg [9:0] addradelay = 10'd0;$/;" r module:IQmerge -addradelay hdl/phase_adjust.v /^ reg [9:0] addradelay = 10'd0;$/;" r module:phase_adjust +addradelay hdl/phase_adjust.v /^ reg [ 9:0] addradelay = 10'd0;$/;" r module:phase_adjust addrb adi_library/common/ad_mem.v /^ input [(ADDRESS_WIDTH-1):0] addrb,$/;" p module:ad_mem addrb adi_library/common/ad_mem_asym.v /^ input [B_ADDRESS_WIDTH-1:0] addrb,$/;" p module:ad_mem_asym addrb adi_library/util_var_fifo/util_var_fifo.v /^ reg [ADDRESS_WIDTH-1:0] addrb = 'd0;$/;" r module:util_var_fifo addrb hdl/IQmerge.v /^ reg [10:0] addrb = 11'd0;$/;" r module:IQmerge -addrb hdl/phase_adjust.v /^ reg [7:0] addrb = 8'd0;$/;" r module:phase_adjust +addrb hdl/phase_adjust.v /^ reg [ 7:0] addrb = 8'd0;$/;" r module:phase_adjust addrb_pilot01 hdl/freqestm.v /^ reg [11:0] addrb_pilot01;$/;" r module:freqestm addrb_pilot02 hdl/freqestm.v /^ reg [11:0] addrb_pilot02;$/;" r module:freqestm address adi_library/axi_dmac/address_generator.v /^reg [DMA_ADDR_WIDTH-BYTES_PER_BEAT_WIDTH-1:0] address = 'h00;$/;" r module:dmac_address_generator @@ -1878,14 +2531,16 @@ address_id adi_library/axi_dmac/dest_axi_mm.v /^ output [ID_WIDTH-1:0] address_id adi_library/axi_dmac/src_axi_mm.v /^ output [ID_WIDTH-1:0] address_id,$/;" p module:dmac_src_mm_axi addrin_1 hdl/DAGC_v2.v /^ reg [11:0] addrin_1 = 12'd0;$/;" r module:DAGC_v2 addrin_MMSE hdl/Chn_Estimate.v /^ output reg [7:0] addrin_MMSE = 8'd0,$/;" p module:Chn_Estimate -addrin_MMSE hdl/SC_FDE_TOP.v /^ wire [7:0] addrin_MMSE;$/;" n module:SC_FDE_TOP +addrin_MMSE hdl/SC_FDE_TOP.v /^ wire [ 7:0] addrin_MMSE;$/;" n module:SC_FDE_TOP addrout_1 hdl/DAGC_v2.v /^ reg [11:0] addrout_1 = 12'd0;$/;" r module:DAGC_v2 -addrout_MMSE hdl/SC_FDE_TOP.v /^ wire [7:0] addrout_MMSE;$/;" n module:SC_FDE_TOP +addrout_MMSE hdl/SC_FDE_TOP.v /^ wire [ 7:0] addrout_MMSE;$/;" n module:SC_FDE_TOP addrout_MMSE hdl/data_equalizer.v /^ output reg [7:0] addrout_MMSE = 8'd0,$/;" p module:data_equalizer +agc_addr hdl/Transmitter.v /^ reg [13:0] agc_addr;$/;" r module:Transmitter agc_check hdl/DAGC_v2.v /^ output reg [12:0] agc_check = 13'd0,$/;" p module:DAGC_v2 -agc_check hdl/RecvTop.v /^ output [12:0] agc_check,$/;" p module:RecvTop +agc_check hdl/RecvTop.v /^ wire [12:0] agc_check;$/;" n module:RecvTop +agc_data hdl/Transmitter.v /^ wire [ 1:0] agc_data;$/;" n module:Transmitter agc_ref hdl/DAGC_v2.v /^ output reg [12:0] agc_ref = 13'd0,$/;" p module:DAGC_v2 -agc_ref hdl/RecvTop.v /^ output [12:0] agc_ref,$/;" p module:RecvTop +agc_ref hdl/RecvTop.v /^ wire [12:0] agc_ref;$/;" n module:RecvTop agc_ref_h hdl/DAGC_v2.v /^ reg [14:0] agc_ref_h = 15'd0;$/;" r module:DAGC_v2 agc_ref_l hdl/DAGC_v2.v /^ reg [12:0] agc_ref_l = 13'd0;$/;" r module:DAGC_v2 agc_ref_temp hdl/DAGC_v2.v /^ reg [22:0] agc_ref_temp = 23'd0;$/;" r module:DAGC_v2 @@ -1916,9 +2571,13 @@ arsize adi_library/axi_dmac/tb/axi_read_slave.v /^ input [2:0] arsize,$/;" p mo arsize adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [2:0] arsize;$/;" n module:dmac_dma_read_shutdown_tb arsize adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [2:0] arsize;$/;" n module:dmac_dma_read_tb arvalid adi_library/axi_dmac/tb/axi_read_slave.v /^ input arvalid,$/;" p module:axi_read_slave +ask_din hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ wire ask_din;$/;" n module:CCSDS_LDPC_DEC_K1024_R12 +ask_din hdl/LDPC_DEC_PRO.v /^ output reg ask_din = 1'd0, \/\/向上层索要译码数据标志，高脉冲 $/;" p module:LDPC_DEC_PRO +ask_din hdl/VN_PRO.v /^ output ask_din, \/\/向数据缓存区请求信道数据$/;" p module:VN_PRO +ask_din_VN hdl/LDPC_DEC_PRO.v /^ wire ask_din_VN;$/;" n module:LDPC_DEC_PRO atan2_freq hdl/freqestm.v /^ atan2_freq atan2_freq ($/;" i module:freqestm typeref:module:atan2_freq -atan2_phase hdl/phase_adjust.v /^ atan2_phase atan2_phase ($/;" i module:phase_adjust typeref:module:atan2_phase -atan2_rotate hdl/phase_adjust.v /^ atan2_rotate atan2_rotate ($/;" i module:phase_adjust typeref:module:atan2_rotate +atan2_phase hdl/phase_adjust.v /^ atan2_phase atan2_phase ($/;" i module:phase_adjust typeref:module:atan2_phase +atan2_rotate hdl/phase_adjust.v /^ atan2_rotate atan2_rotate ($/;" i module:phase_adjust typeref:module:atan2_rotate atan_table adi_library/common/ad_dds_sine_cordic.v /^ wire [ PHASE_DW-1:0] atan_table[0:CORDIC_DW-2];$/;" n module:ad_dds_sine_cordic average_1024 hdl/SCFDE_recv_FrameSync.v /^ average_1024 average_1024 ($/;" i module:SCFDE_recv_FrameSync typeref:module:average_1024 average_add10 hdl/SCFDE_recv_FrameSync.v /^ wire [19:0] average_add10;$/;" n module:SCFDE_recv_FrameSync @@ -2297,10 +2956,18 @@ b adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [7:0] b;$/;" r fun b2g adi_library/common/ad_b2g.v /^ function [DATA_WIDTH-1:0] b2g;$/;" f module:ad_b2g b2g adi_library/util_cdc/sync_gray.v /^ function [DATA_WIDTH-1:0] b2g;$/;" f module:sync_gray b2g adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ function [7:0] b2g;$/;" f module:axi_adcfifo_wr -bad_frames hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output [8:0] bad_frames, \/\/译码坏帧计数$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +bad_frames hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ output reg [8:0] bad_frames = 9'd0, \/\/译码坏帧计数$/;" p module:CCSDS_LDPC_DEC_K1024_R12 +bad_frames hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output [8:0] bad_frames, \/\/译码坏帧计数$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP bad_frames hdl/RecvTop.v /^ wire [8:0] bad_frames;$/;" n module:RecvTop -bad_frames_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [8:0] bad_frames_A; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP -bad_frames_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [8:0] bad_frames_B; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +bad_frames_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [ 8:0] bad_frames_A;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +bad_frames_A_TM hdl/LDPC_TopManage_2.v /^ input [ 8:0] bad_frames_A_TM, \/\/译码坏帧计数$/;" p module:LDPC_TopManage_2 +bad_frames_A_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg [8:0] bad_frames_A_TM_reg0, bad_frames_A_TM_reg1;$/;" r module:LDPC_TopManage_2 +bad_frames_A_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg [8:0] bad_frames_A_TM_reg0, bad_frames_A_TM_reg1;$/;" r module:LDPC_TopManage_2 +bad_frames_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [ 8:0] bad_frames_B;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +bad_frames_B_TM hdl/LDPC_TopManage_2.v /^ input [ 8:0] bad_frames_B_TM, \/\/译码坏帧计数$/;" p module:LDPC_TopManage_2 +bad_frames_B_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg [8:0] bad_frames_B_TM_reg0, bad_frames_B_TM_reg1;$/;" r module:LDPC_TopManage_2 +bad_frames_B_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg [8:0] bad_frames_B_TM_reg0, bad_frames_B_TM_reg1;$/;" r module:LDPC_TopManage_2 +bad_frames_TM hdl/LDPC_TopManage_2.v /^ output [ 8:0] bad_frames_TM, \/\/译码坏帧计数$/;" p module:LDPC_TopManage_2 bagcnt hdl/FrameMerge.v /^ reg [8:0] bagcnt = 9'd0;$/;" r module:FrameMerge bagcount hdl/IQmerge.v /^ reg [8:0] bagcount = 9'd0;$/;" r module:IQmerge base adi_library/util_pack/util_pack_common/pack_ctrl.v /^ localparam base = i*MUX_ORDER;$/;" c block:pack_ctrl.demux_gen_outer @@ -2313,6 +2980,10 @@ bb_wave_out_q hdl/Transmitter.v /^ reg [31:0] bb_wave_out_q; \/\/ shape fil bb_wave_out_q_interp16 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_q_interp16;$/;" n module:Transmitter bb_wave_out_q_interp4 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_q_interp4;$/;" n module:Transmitter bb_wave_out_q_interp8 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_q_interp8;$/;" n module:Transmitter +bd_frames hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ wire [ 8:0] bd_frames;$/;" n module:CCSDS_LDPC_DEC_K1024_R12 +bd_frames hdl/CK_PRO.v /^ output reg [8:0] bd_frames=9'd0,\/\/译码坏帧计数$/;" p module:CK_PRO +bd_frames hdl/LDPC_DEC_PRO.v /^ output reg [8:0] bd_frames = 9'd0, \/\/译码坏帧计数$/;" p module:LDPC_DEC_PRO +bd_frames_CK hdl/LDPC_DEC_PRO.v /^ wire [8:0] bd_frames_CK;$/;" n module:LDPC_DEC_PRO beat_ack adi_library/axi_dmac/tb/axi_slave.v /^ input beat_ack,$/;" p module:axi_slave beat_addr adi_library/axi_dmac/tb/axi_read_slave.v /^wire [31:0] beat_addr;$/;" n module:axi_read_slave beat_addr adi_library/axi_dmac/tb/axi_slave.v /^ output [31:0] beat_addr,$/;" p module:axi_slave @@ -2323,14 +2994,10 @@ beat_last adi_library/axi_dmac/tb/axi_slave.v /^ output beat_last$/;" p module: beat_last adi_library/axi_dmac/tb/axi_write_slave.v /^wire beat_last;$/;" n module:axi_write_slave beat_stb adi_library/axi_dmac/tb/axi_slave.v /^ output beat_stb,$/;" p module:axi_slave bercompare hdl/FrameMerge.v /^ output reg bercompare = 1'b0,$/;" p module:FrameMerge -bercompare hdl/RecvTop.v /^ wire bercompare;$/;" n module:RecvTop bercount hdl/FrameMerge.v /^ output reg [16:0] bercount = 17'd0,$/;" p module:FrameMerge -bercount hdl/RecvTop.v /^ wire [16:0] bercount;$/;" n module:RecvTop bercount_max hdl/FrameMerge.v /^ output reg [16:0] bercount_max = 17'd0,$/;" p module:FrameMerge -bercount_max hdl/RecvTop.v /^ wire [16:0] bercount_max;$/;" n module:RecvTop berstart hdl/FrameMerge.v /^ reg berstart = 1'b0;$/;" r module:FrameMerge berstart_1d hdl/FrameMerge.v /^ output reg berstart_1d = 1'b0,$/;" p module:FrameMerge -berstart_1d hdl/RecvTop.v /^ wire berstart_1d;$/;" n module:RecvTop bit_counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];$/;" n module:spi_engine_execution bl_mem adi_library/axi_dmac/dest_axi_mm.v /^reg [BYTES_PER_BURST_WIDTH+1-1:0] bl_mem [0:2**(ID_WIDTH)-1];$/;" r module:dmac_dest_mm_axi bl_ready adi_library/axi_dmac/address_generator.v /^ output reg bl_ready,$/;" p module:dmac_address_generator @@ -2403,7 +3070,7 @@ check_all_registers adi_library/axi_dmac/tb/regmap_tb.v /^ task check_all_regis check_clk_num hdl/CCSDS_LDPC_ENC_R12.v /^ reg [10:0] check_clk_num = 11'd0;$/;" r module:CCSDS_LDPC_ENC_R12 check_clk_num hdl/Out_Process_R12.v /^ input [10:0] check_clk_num, \/\/校验比特个数$/;" p module:Out_Process_R12 chu_seq hdl/Transmitter.v /^ wire [31:0] chu_seq;$/;" n module:Transmitter -chu_seq_addr hdl/Transmitter.v /^ reg [ 6:0] chu_seq_addr;$/;" r module:Transmitter +chu_seq_addr hdl/Transmitter.v /^ reg [ 7:0] chu_seq_addr = 0;$/;" r module:Transmitter cic_comb adi_library/util_cic/cic_comb.v /^module cic_comb #($/;" m cic_int adi_library/util_cic/cic_int.v /^module cic_int #($/;" m clk adi_library/axi_dmac/address_generator.v /^ input clk,$/;" p module:dmac_address_generator @@ -2478,8 +3145,13 @@ clk adi_library/xilinx/common/ad_serdes_out.v /^ input cl clk adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ input clk,$/;" p module:util_clkdiv clk hdl/ApproxAbs_18bit.v /^ input clk,$/;" p module:ApproxAbs_18bit clk hdl/ApproxAbs_v2.v /^ input clk,$/;" p module:ApproxAbs_v2 -clk hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input clk, \/\/工作时钟,100MHz$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +clk hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ input clk, \/\/工作时钟,100MHz$/;" p module:CCSDS_LDPC_DEC_K1024_R12 +clk hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input clk, \/\/工作时钟,100MHz$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP clk hdl/CCSDS_LDPC_ENC_R12.v /^ input clk,$/;" p module:CCSDS_LDPC_ENC_R12 +clk hdl/CK_PRO.v /^ input clk,$/;" p module:CK_PRO +clk hdl/CNU_3din.v /^ input clk,$/;" p module:CNU_3din +clk hdl/CNU_6din.v /^ input clk,$/;" p module:CNU_6din +clk hdl/CN_PRO.v /^ input clk,$/;" p module:CN_PRO clk hdl/Chn_Estimate.v /^ input clk,$/;" p module:Chn_Estimate clk hdl/DAGC_v2.v /^ input clk,$/;" p module:DAGC_v2 clk hdl/DDS_compensate.v /^ input clk;$/;" p module:DDS_compensate @@ -2488,19 +3160,30 @@ clk hdl/IQmerge.v /^ input clk,$/;" p module:IQmerge clk hdl/Interp_half.v /^ input clk,$/;" p module:Interp_half clk hdl/Interp_quarter.v /^ input clk,$/;" p module:Interp_quarter clk hdl/Interpolation.v /^ input clk,$/;" p module:Interpolation +clk hdl/LDPC_DEC_PRO.v /^ input clk, \/\/工作时钟$/;" p module:LDPC_DEC_PRO +clk hdl/LDPC_TopManage_2.v /^ input clk, \/\/工作时钟,100MHz$/;" p module:LDPC_TopManage_2 clk hdl/MF_Top.v /^ input clk,$/;" p module:MF_Top clk hdl/MagnitudeEstimator.v /^ input clk,$/;" p module:MagnitudeEstimator +clk hdl/Message_Store.v /^ input clk,$/;" p module:Message_Store clk hdl/Noise_Estimate.v /^ input clk,$/;" p module:Noise_Estimate +clk hdl/Normalization_Factor_0_8125.v /^ input clk,$/;" p module:Normalization_Factor_0_8125 +clk hdl/OUT_PRO.v /^ input clk,$/;" p module:OUT_PRO clk hdl/Out_Process_R12.v /^ input clk,$/;" p module:Out_Process_R12 -clk hdl/PAPR.v /^ input clk, $/;" p module:PAPR +clk hdl/PAPR.v /^ input clk,$/;" p module:PAPR clk hdl/Receiver.v /^ input clk,$/;" p module:Receiver -clk hdl/RecvTop.v /^ input clk,$/;" p module:RecvTop +clk hdl/RecvTop.v /^ input clk,$/;" p module:RecvTop clk hdl/SCFDE_recv_FrameSync.v /^ input clk,$/;" p module:SCFDE_recv_FrameSync -clk hdl/SC_FDE_TOP.v /^ input clk,$/;" p module:SC_FDE_TOP +clk hdl/SC_FDE_TOP.v /^ input clk,$/;" p module:SC_FDE_TOP clk hdl/TSync_Abs_new16.v /^ input clk,$/;" p module:TSync_Abs_new16 clk hdl/TSync_Abs_new4.v /^ input clk,$/;" p module:TSync_Abs_new4 clk hdl/TimeSync_top.v /^ input clk,$/;" p module:TimeSync_top clk hdl/Transmitter.v /^ input wire clk,$/;" p module:Transmitter +clk hdl/VNU_1din.v /^ input clk,$/;" p module:VNU_1din +clk hdl/VNU_2din.v /^ input clk,$/;" p module:VNU_2din +clk hdl/VNU_3din.v /^ input clk,$/;" p module:VNU_3din +clk hdl/VNU_6din.v /^ input clk,$/;" p module:VNU_6din +clk hdl/VN_PRO.v /^ input clk,$/;" p module:VN_PRO +clk hdl/abs_min_4din.v /^ input clk,$/;" p module:abs_min_4din clk hdl/ad9361_mgc_pin_ctrl.v /^ input clk,$/;" p module:ad9361_mgc_pin_ctrl clk hdl/add_prefix.v /^ input clk,$/;" p module:add_prefix clk hdl/data_equalizer.v /^ input clk,$/;" p module:data_equalizer @@ -2508,11 +3191,12 @@ clk hdl/data_ow.v /^ input clk,$/;" p module:data_ow clk hdl/enc_control.v /^ input clk,$/;" p module:enc_control clk hdl/frame_sync.v /^ input clk,$/;" p module:frame_sync clk hdl/freqestm.v /^ input clk,$/;" p module:freqestm -clk hdl/phase_adjust.v /^ input clk,$/;" p module:phase_adjust +clk hdl/net_city.v /^ input clk,$/;" p module:net_city +clk hdl/phase_adjust.v /^ input clk,$/;" p module:phase_adjust clk hdl/phy_control.v /^ input clk, \/\/ can be floating if ASYNC_CLK == 0$/;" p module:phy_control clk hdl/power_measure.v /^ input clk,$/;" p module:power_measure clk hdl/shift_reg.v /^ input clk,$/;" p module:shift_reg -clk hdl/tdma.v /^ input clk,$/;" p module:tdma +clk hdl/tdma.v /^ input clk,$/;" p module:tdma clk hdl/trunc_25to12_2dly.v /^ input clk;$/;" p module:trunc_25to12_2dly clk hdl/width_convert.v /^ input clk,$/;" p module:width_convert clk sim/TB_sys.v /^ reg clk;$/;" r module:TB_sys @@ -2520,36 +3204,43 @@ clk sim/tb_Receiver.v /^ reg clk;$/;" r module:tb_Receiver clk sim/tb_Transmitter.v /^ reg clk = 1;$/;" r module:tb_Transmitter clk sim/tb_add_prefix.v /^ reg clk = 0;$/;" r module:tb_add_prefix clk sim/tb_enc_control.v /^ reg clk = 1;$/;" r module:tb_enc_control +clk sim/tb_recv_top.v /^ reg clk = 0;$/;" r module:tb_recv_top clk sim/tb_tdma.v /^ reg clk = 1;$/;" r module:tb_tdma clk sim/tb_width_convert.v /^ reg clk = 1;$/;" r module:tb_width_convert clk2 adi_library/xilinx/common/ad_mmcm_drp.v /^ input clk2,$/;" p module:ad_mmcm_drp clk2 hdl/FrameMerge.v /^ input clk2,$/;" p module:FrameMerge clk2 hdl/IQmerge.v /^ input clk2,$/;" p module:IQmerge -clk2 hdl/RecvTop.v /^ input clk2,$/;" p module:RecvTop clk_100msps adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ wire clk_100msps;$/;" n module:util_gmii_to_rgmii clk_125m adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input clk_125m,$/;" p module:util_gmii_to_rgmii clk_1x hdl/system_top.v /^ wire clk_1x;$/;" n module:system_top clk_1x sim/TB_sys.v /^ wire clk_1x;$/;" n module:TB_sys +clk_1x sim/tb_sys_tx_rx_e_d.v /^ wire clk_1x;$/;" n module:tb_sys_tx_rx_e_d clk_1x sim/tb_tx_with_enc.v /^ wire clk_1x;$/;" n module:tb_tx_with_enc clk_20m adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input clk_20m,$/;" p module:util_gmii_to_rgmii clk_25m adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input clk_25m,$/;" p module:util_gmii_to_rgmii clk_2_5_divide adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) clk_2_5_divide ($/;" i module:util_gmii_to_rgmii typeref:module:BUFR clk_2_5m adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ wire clk_2_5m;$/;" n module:util_gmii_to_rgmii clk_2x hdl/Receiver.v /^ input clk_2x,$/;" p module:Receiver +clk_2x hdl/RecvTop.v /^ input clk_2x, \/\/ clk_2x$/;" p module:RecvTop clk_2x hdl/system_top.v /^ wire clk_2x;$/;" n module:system_top clk_2x sim/TB_sys.v /^ wire clk_2x;$/;" n module:TB_sys clk_2x sim/tb_Receiver.v /^ reg clk_2x;$/;" r module:tb_Receiver +clk_2x sim/tb_recv_top.v /^ reg clk_2x = 0;$/;" r module:tb_recv_top +clk_2x sim/tb_sys_tx_rx_e_d.v /^ wire clk_2x;$/;" n module:tb_sys_tx_rx_e_d clk_2x sim/tb_tx_with_enc.v /^ wire clk_2x;$/;" n module:tb_tx_with_enc clk_4x hdl/Receiver.v /^ input clk_4x,$/;" p module:Receiver +clk_4x hdl/RecvTop.v /^ input clk_4x,$/;" p module:RecvTop clk_4x hdl/system_top.v /^ wire clk_4x;$/;" n module:system_top clk_4x sim/TB_sys.v /^ wire clk_4x;$/;" n module:TB_sys clk_4x sim/tb_Receiver.v /^ reg clk_4x;$/;" r module:tb_Receiver +clk_4x sim/tb_recv_top.v /^ reg clk_4x = 0;$/;" r module:tb_recv_top +clk_4x sim/tb_sys_tx_rx_e_d.v /^ wire clk_4x;$/;" n module:tb_sys_tx_rx_e_d clk_4x sim/tb_tx_with_enc.v /^ wire clk_4x;$/;" n module:tb_tx_with_enc -clk_60M_mac hdl/RecvTop.v /^ input clk_60M_mac,$/;" p module:RecvTop clk_a adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg clk_a = 1'b0;$/;" r module:dmac_reset_manager_tb clk_b adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg clk_b = 1'b0;$/;" r module:dmac_reset_manager_tb clk_c adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg clk_c = 1'b0;$/;" r module:dmac_reset_manager_tb clk_crystal hdl/system_top.v /^ input clk_crystal,$/;" p module:system_top +clk_crystal sim/tb_sys_tx_rx_e_d.v /^ reg clk_crystal = 0; \/\/ 40MHz 25ns$/;" r module:tb_sys_tx_rx_e_d clk_crystal sim/tb_tx_with_enc.v /^ reg clk_crystal = 0; \/\/ 25MHz$/;" r module:tb_tx_with_enc clk_data_src hdl/Transmitter.v /^ output wire clk_data_src,$/;" p module:Transmitter clk_div adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [7:0] clk_div = DEFAULT_CLK_DIV;$/;" r module:spi_engine_execution @@ -2575,6 +3266,7 @@ clk_net_byte hdl/FrameMerge.v /^ reg [7:0] clk_net_byte;$/;" r module:FrameMe clk_out adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ output clk_out$/;" p module:util_clkdiv clk_poweron hdl/system_top.v /^ wire clk_poweron;$/;" n module:system_top clk_poweron sim/TB_sys.v /^ wire clk_poweron;$/;" n module:TB_sys +clk_poweron sim/tb_sys_tx_rx_e_d.v /^ wire clk_poweron;$/;" n module:tb_sys_tx_rx_e_d clk_poweron sim/tb_tx_with_enc.v /^ wire clk_poweron;$/;" n module:tb_tx_with_enc clk_sel adi_library/common/up_clkgen.v /^ output clk_sel,$/;" p module:up_clkgen clk_sel adi_library/xilinx/common/ad_mmcm_drp.v /^ input clk_sel,$/;" p module:ad_mmcm_drp @@ -2583,6 +3275,7 @@ clk_tx sim/tb_Transmitter.v /^ reg clk_tx = 1;$/;" r module:tb_Transmitter clk_tx sim/tb_tdma.v /^ reg clk_tx = 1;$/;" r module:tb_tdma clk_tx_data_src hdl/system_top.v /^ wire clk_tx_data_src;$/;" n module:system_top clk_tx_data_src sim/TB_sys.v /^ wire clk_tx_data_src;$/;" n module:TB_sys +clk_tx_data_src sim/tb_sys_tx_rx_e_d.v /^ wire clk_tx_data_src;$/;" n module:tb_sys_tx_rx_e_d clk_tx_data_src sim/tb_tx_with_enc.v /^ wire clk_tx_data_src;$/;" n module:tb_tx_with_enc clk_tx_mux0 adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) clk_tx_mux0 ($/;" i module:util_gmii_to_rgmii typeref:module:BUFGMUX clk_tx_mux1 adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) clk_tx_mux1 ($/;" i module:util_gmii_to_rgmii typeref:module:BUFGMUX @@ -2612,7 +3305,7 @@ cmd_valid adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ out cnt hdl/PAPR.v /^ reg [ 5:0] cnt;$/;" r module:PAPR cnt hdl/TSync_Abs_new16.v /^ output reg [1:0] cnt = 2'd0, \/\/12.5$/;" p module:TSync_Abs_new16 cnt hdl/TSync_Abs_new4.v /^ output reg [1:0] cnt = 2'd0, \/\/12.5$/;" p module:TSync_Abs_new4 -cnt hdl/tdma.v /^ reg [15:0] cnt;$/;" r module:tdma +cnt hdl/tdma.v /^ reg [23:0] cnt; $/;" r module:tdma cnt hdl/width_convert.v /^ reg [$clog2(CNT_MAX) - 1 : 0] cnt;$/;" r module:width_convert cnt sim/TB_sys.v /^ reg [31:0] cnt;$/;" r module:TB_sys cnt_1024 hdl/TSync_Abs_new16.v /^ reg [9:0] cnt_1024 = 10'd0;$/;" r module:TSync_Abs_new16 @@ -2621,11 +3314,13 @@ cnt_10data hdl/data_ow.v /^ reg [3:0] cnt_10data = 1'd0;$/;" r module:data_ow cnt_128 hdl/TSync_Abs_new16.v /^ reg [6:0] cnt_128 = 7'd0;$/;" r module:TSync_Abs_new16 cnt_128 hdl/TSync_Abs_new4.v /^ reg [6:0] cnt_128 = 7'd0;$/;" r module:TSync_Abs_new4 cnt_16 hdl/TimeSync_top.v /^ wire [1:0] cnt_16;$/;" n module:TimeSync_top +cnt_1s hdl/net_city.v /^ reg [31:0] cnt_1s = 32'd0;$/;" r module:net_city cnt_256 hdl/TSync_Abs_new16.v /^ reg [7:0] cnt_256 = 8'd0;$/;" r module:TSync_Abs_new16 cnt_256 hdl/TSync_Abs_new4.v /^ reg [7:0] cnt_256 = 8'd0;$/;" r module:TSync_Abs_new4 cnt_256 hdl/data_equalizer.v /^ reg [7:0] cnt_256 = 8'd0;$/;" r module:data_equalizer cnt_256 hdl/data_ow.v /^ reg [7:0] cnt_256 = 8'd0;$/;" r module:data_ow cnt_256pilot hdl/data_ow.v /^ reg [7:0] cnt_256pilot = 8'd0;$/;" r module:data_ow +cnt_2_VN hdl/VN_PRO.v /^ reg [10:0] cnt_VN= 11'd0,cnt_2_VN= 11'd0;$/;" r module:VN_PRO cnt_4 hdl/TSync_Abs_new16.v /^ reg [1:0] cnt_4 =2'd0;$/;" r module:TSync_Abs_new16 cnt_4 hdl/TSync_Abs_new4.v /^ reg [1:0] cnt_4 =2'd0;$/;" r module:TSync_Abs_new4 cnt_4 hdl/TimeSync_top.v /^ wire [1:0] cnt_4;$/;" n module:TimeSync_top @@ -2640,7 +3335,11 @@ cnt_6 hdl/freqestm.v /^ reg [ 3:0] cnt_6;$/;" r module:freqestm cnt_64 hdl/TSync_Abs_new16.v /^ reg [5:0] cnt_64 = 6'd0;$/;" r module:TSync_Abs_new16 cnt_64 hdl/TSync_Abs_new4.v /^ reg [5:0] cnt_64 = 6'd0;$/;" r module:TSync_Abs_new4 cnt_8 hdl/FrameMerge.v /^ output reg [2:0] cnt_8 = 3'b0,$/;" p module:FrameMerge -cnt_8 hdl/RecvTop.v /^ wire [ 2:0] cnt_8;$/;" n module:RecvTop +cnt_CK hdl/CK_PRO.v /^ reg [10:0] cnt_CK=11'd0;$/;" r module:CK_PRO +cnt_CN hdl/CN_PRO.v /^ reg [10:0] cnt_CN=11'd0;$/;" r module:CN_PRO +cnt_MS hdl/Message_Store.v /^ reg [10:0] cnt_MS = 11'd0;$/;" r module:Message_Store +cnt_OUT hdl/OUT_PRO.v /^ reg [11:0] cnt_OUT=12'd0;$/;" r module:OUT_PRO +cnt_VN hdl/VN_PRO.v /^ reg [10:0] cnt_VN= 11'd0,cnt_2_VN= 11'd0;$/;" r module:VN_PRO cnt_add_prefix_in hdl/enc_control.v /^ reg [ 2:0] cnt_add_prefix_in;$/;" r module:enc_control cnt_adjust_times hdl/power_measure.v /^ reg [ 7:0] cnt_adjust_times;$/;" r module:power_measure cnt_agc_send hdl/Transmitter.v /^ reg [15:0] cnt_agc_send; \/\/ agc symbols have been sent$/;" r module:Transmitter @@ -2648,9 +3347,11 @@ cnt_amp_too_high hdl/power_measure.v /^ reg [ 3:0] cnt_amp_too_high; \/\/ fo cnt_bag hdl/freqestm.v /^ reg [ 7:0] cnt_bag;$/;" r module:freqestm cnt_blocks_send hdl/Transmitter.v /^ reg [15:0] cnt_blocks_send; \/\/ blocks have been sent$/;" r module:Transmitter cnt_chu_send hdl/Transmitter.v /^ reg [15:0] cnt_chu_send;$/;" r module:Transmitter +cnt_chu_seq_sync hdl/RecvTop.v /^ reg [ 7:0] cnt_chu_seq_sync; \/\/ frame sync delay to chu seq sample start pos$/;" r module:RecvTop cnt_cp hdl/freqestm.v /^ reg [11:0] cnt_cp;$/;" r module:freqestm cnt_data_in sim/tb_width_convert.v /^ reg [3:0] cnt_data_in;$/;" r module:tb_width_convert cnt_databag hdl/DAGC_v2.v /^ reg [14:0] cnt_databag = 15'd0;$/;" r module:DAGC_v2 +cnt_delay sim/tb_sys_tx_rx_e_d.v /^ reg [ 3:0] cnt_delay = 0;$/;" r module:tb_sys_tx_rx_e_d cnt_din hdl/CCSDS_LDPC_ENC_R12.v /^ reg [10:0] cnt_din = 11'd0; \/\/输入1024个时钟$/;" r module:CCSDS_LDPC_ENC_R12 cnt_din_d1 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [10:0] cnt_din_d1 = 11'd0;$/;" r module:CCSDS_LDPC_ENC_R12 cnt_din_d2 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [10:0] cnt_din_d2 = 11'd0;$/;" r module:CCSDS_LDPC_ENC_R12 @@ -2658,21 +3359,24 @@ cnt_div sim/tb_enc_control.v /^ reg [ 1:0] cnt_div = 0;$/;" r module:tb_enc_ cnt_encode_valid hdl/CCSDS_LDPC_ENC_R12.v /^ reg [9:0] cnt_encode_valid = 10'd0;$/;" r module:CCSDS_LDPC_ENC_R12 cnt_fifo hdl/freqestm.v /^ reg [15:0] cnt_fifo;$/;" r module:freqestm cnt_fifo_out_valid hdl/Receiver.v /^ reg [ 2:0] cnt_fifo_out_valid;$/;" r module:Receiver +cnt_fifo_out_valid hdl/RecvTop.v /^ reg [ 2:0] cnt_fifo_out_valid;$/;" r module:RecvTop cnt_fifo_out_valid_sel hdl/Receiver.v /^ reg [ 2:0] cnt_fifo_out_valid_sel; \/\/ 根据speed mode对应的计数器边界值$/;" r module:Receiver +cnt_fifo_out_valid_sel hdl/RecvTop.v /^ reg [ 2:0] cnt_fifo_out_valid_sel = 1; \/\/ 根据speed mode对应的计数器边界值$/;" r module:RecvTop cnt_frame hdl/freqestm.v /^ reg [14:0] cnt_frame;$/;" r module:freqestm -cnt_h hdl/tdma.v /^ reg [ 7:0] cnt_h;$/;" r module:tdma cnt_in hdl/add_prefix.v /^ reg [CNT_WIDTH : 0] cnt_in;$/;" r module:add_prefix cnt_in hdl/enc_control.v /^ reg [ CNT_IN_WIDTH : 0] cnt_in; \/\/ 多留1bit$/;" r module:enc_control cnt_in sim/tb_width_convert.v /^ reg [5:0] cnt_in;$/;" r module:tb_width_convert +cnt_inter_slot hdl/net_city.v /^ reg [31:0] cnt_inter_slot = 32'd0;$/;" r module:net_city cnt_interp hdl/Transmitter.v /^ reg [ 3:0] cnt_interp;$/;" r module:Transmitter -cnt_l hdl/tdma.v /^ reg [15:0] cnt_l;$/;" r module:tdma -cnt_lost hdl/RecvTop.v /^ reg [20:0] cnt_lost;$/;" r module:RecvTop +cnt_lost hdl/RecvTop.v /^ reg [20:0] cnt_lost;$/;" r module:RecvTop cnt_measuring hdl/power_measure.v /^ reg [15:0] cnt_measuring;$/;" r module:power_measure -cnt_mgc_delay hdl/RecvTop.v /^ reg [7:0] cnt_mgc_delay;$/;" r module:RecvTop +cnt_mgc_delay hdl/RecvTop.v /^ reg [ 7:0] cnt_mgc_delay;$/;" r module:RecvTop cnt_net hdl/FrameMerge.v /^ reg [6:0] cnt_net;$/;" r module:FrameMerge +cnt_other hdl/net_city.v /^ reg [31:0] cnt_other = 32'd0;$/;" r module:net_city cnt_out hdl/add_prefix.v /^ reg [ CNT_WIDTH:0] cnt_out;$/;" r module:add_prefix cnt_out hdl/enc_control.v /^ reg [CNT_OUT_WIDTH : 0] cnt_out; \/\/ 多留1bit$/;" r module:enc_control -cnt_phase hdl/phase_adjust.v /^ reg [9:0] cnt_phase;$/;" r module:phase_adjust +cnt_out_MS hdl/Message_Store.v /^ reg [10:0] cnt_out_MS = 11'd0;$/;" r module:Message_Store +cnt_phase hdl/phase_adjust.v /^ reg [ 9:0] cnt_phase;$/;" r module:phase_adjust cnt_pilot hdl/freqestm.v /^ reg [11:0] cnt_pilot;$/;" r module:freqestm cnt_process hdl/freqestm.v /^ reg [11:0] cnt_process;$/;" r module:freqestm cnt_pulse_width hdl/ad9361_mgc_pin_ctrl.v /^ reg [3:0] cnt_pulse_width;$/;" r module:ad9361_mgc_pin_ctrl @@ -2684,8 +3388,10 @@ cnt_startup hdl/Receiver.v /^ reg [ 8:0] cnt_startup;$/;" r module:Receiver cnt_startup hdl/power_measure.v /^ reg [ 7:0] cnt_startup; \/\/ set rx gain to max each time start posedge comes$/;" r module:power_measure cnt_startup sim/tb_width_convert.v /^ reg [5:0] cnt_startup;$/;" r module:tb_width_convert cnt_sym_send hdl/Transmitter.v /^ reg [15:0] cnt_sym_send; \/\/ symbols have been sent$/;" r module:Transmitter +cnt_trans_slot hdl/net_city.v /^ reg [31:0] cnt_trans_slot = 32'd0;$/;" r module:net_city cnt_tsync hdl/RecvTop.v /^ wire [1:0] cnt_tsync;$/;" n module:RecvTop cnt_tsync hdl/TimeSync_top.v /^ output reg [1:0] cnt_tsync = 2'd0,\/\/12.5$/;" p module:TimeSync_top +cnt_video_slot hdl/net_city.v /^ reg [07:0] cnt_video_slot = 8'd0;$/;" r module:net_city cnt_wait hdl/Transmitter.v /^ reg [15:0] cnt_wait; \/\/ wait cnt max 65535 period, 50M -> 1.3ms$/;" r module:Transmitter cnt_wait_9361 hdl/power_measure.v /^ reg [15:0] cnt_wait_9361;$/;" r module:power_measure color1 adi_library/common/ad_csc.v /^ wire signed [8:0] color1;$/;" n module:ad_csc @@ -2723,6 +3429,7 @@ completion_req_valid adi_library/axi_dmac/request_generator.v /^ output reg com completion_transfer_id adi_library/axi_dmac/axi_dmac_response_manager.v /^ input [1:0] completion_transfer_id$/;" p module:axi_dmac_response_manager completion_transfer_id adi_library/axi_dmac/request_arb.v /^wire [1:0] completion_transfer_id;$/;" n module:dmac_request_arb completion_transfer_id adi_library/axi_dmac/request_generator.v /^ output [1:0] completion_transfer_id,$/;" p module:dmac_request_generator +connect_node hdl/net_city.v /^ reg [07:0] connect_node = 8'd0;$/;" r module:net_city core_clk adi_library/common/ad_sysref_gen.v /^ input core_clk,$/;" p module:ad_sysref_gen cos_addr hdl/DDS_compensate.v /^ reg [12:0] cos_addr = 0,sin_addr = -13'd2048;$/;" r module:DDS_compensate cos_dout hdl/DDS_compensate.v /^ wire [11:0] cos_dout,sin_dout;$/;" n module:DDS_compensate @@ -2846,6 +3553,7 @@ ctrl_sync_id_init adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v ctrl_sync_id_load adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg ctrl_sync_id_load = 1'b0;$/;" r module:spi_engine_offload cur_burst_length adi_library/axi_dmac/request_generator.v /^reg [BURSTS_PER_TRANSFER_WIDTH-1:0] cur_burst_length = 'h00;$/;" r module:dmac_request_generator cur_req_xlast adi_library/axi_dmac/request_generator.v /^reg cur_req_xlast;$/;" r module:dmac_request_generator +cur_slot hdl/net_city.v /^ reg [07:0] cur_slot = 8'd0;$/;" r module:net_city cur_transfer_id adi_library/axi_dmac/request_generator.v /^reg cur_transfer_id = 1'b0;$/;" r module:dmac_request_generator current_state adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ reg [ 1:0] current_state = IDLE;$/;" r module:mdc_mdio cycle_out_cnt hdl/Out_Process_R12.v /^ reg [10:0] cycle_out_cnt = 11'd0;$/;" r module:Out_Process_R12 @@ -3025,7 +3733,7 @@ dac_xfer_req_d adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_xfer_req_m adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [ 2:0] dac_xfer_req_m = 3'b0;$/;" r module:axi_dacfifo_rd dac_xfer_req_m1 adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_xfer_req_m1 = 1'b0;$/;" r module:util_dacfifo dagc_rdy hdl/DAGC_v2.v /^ output reg dagc_rdy,$/;" p module:DAGC_v2 -dagc_rdy hdl/RecvTop.v /^ wire dagc_rdy;$/;" n module:RecvTop +dagc_rdy hdl/RecvTop.v /^ wire dagc_rdy;$/;" n module:RecvTop dagc_rdy_d0 hdl/DAGC_v2.v /^ reg dagc_rdy_d0;$/;" r module:DAGC_v2 dagc_rdy_d1 hdl/DAGC_v2.v /^ reg dagc_rdy_d1;$/;" r module:DAGC_v2 dagc_rdy_d2 hdl/DAGC_v2.v /^ reg dagc_rdy_d2;$/;" r module:DAGC_v2 @@ -3078,7 +3786,7 @@ data_eot adi_library/axi_dmac/dest_axi_stream.v /^ input data_eot,$/;" p module data_eot adi_library/axi_dmac/dest_fifo_inf.v /^ input data_eot,$/;" p module:dmac_dest_fifo_inf data_eot adi_library/axi_dmac/request_arb.v /^wire data_eot = eot_mem_dest[data_id];$/;" n module:dmac_request_arb data_equalizer hdl/data_equalizer.v /^module data_equalizer($/;" m -data_equalizer_djy hdl/SC_FDE_TOP.v /^ data_equalizer data_equalizer_djy ($/;" i module:SC_FDE_TOP typeref:module:data_equalizer +data_equalizer_djy hdl/SC_FDE_TOP.v /^ data_equalizer data_equalizer_djy ($/;" i module:SC_FDE_TOP typeref:module:data_equalizer data_i hdl/frame_sync.v /^ input [11:0] data_i,$/;" p module:frame_sync data_i hdl/power_measure.v /^ input wire [11:0] data_i,$/;" p module:power_measure data_i_abs hdl/power_measure.v /^ reg [11:0] data_i_abs;$/;" r module:power_measure @@ -3166,7 +3874,7 @@ data_out_valid sim/tb_add_prefix.v /^ wire data_out_valid;$/;" n modul data_out_valid sim/tb_width_convert.v /^ wire data_out_valid;$/;" n module:tb_width_convert data_out_valid_s adi_library/util_var_fifo/util_var_fifo.v /^ wire data_out_valid_s;$/;" n module:util_var_fifo data_ow hdl/data_ow.v /^module data_ow($/;" m -data_ow_djy hdl/SC_FDE_TOP.v /^ data_ow data_ow_djy ($/;" i module:SC_FDE_TOP typeref:module:data_ow +data_ow_djy hdl/SC_FDE_TOP.v /^ data_ow data_ow_djy ($/;" i module:SC_FDE_TOP typeref:module:data_ow data_p adi_library/xilinx/common/ad_mul.v /^ output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p,$/;" p module:ad_mul data_q hdl/frame_sync.v /^ input [11:0] data_q,$/;" p module:frame_sync data_q hdl/power_measure.v /^ input wire [11:0] data_q,$/;" p module:power_measure @@ -3191,7 +3899,6 @@ data_s6 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s6 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s6,$/;" p module:ad_serdes_out data_s7 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s7, \/\/ 1st bit received$/;" p module:ad_serdes_in data_s7 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s7, \/\/ last bit to be transmitted$/;" p module:ad_serdes_out -data_save hdl/RecvTop.v /^ wire data_save; \/\/debug用，暂不需使用$/;" n module:RecvTop data_save hdl/freqestm.v /^ output reg data_save,$/;" p module:freqestm data_sdi_shift adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ reg [DATA_WIDTH-1:0] data_sdi_shift;$/;" r block:spi_engine_execution.g_sdi_shift_reg data_sdo_shift adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;$/;" r module:spi_engine_execution @@ -3199,9 +3906,13 @@ data_shift1_s adi_library/xilinx/common/ad_serdes_in.v /^ wire [(DATA_WIDTH- data_shift2_s adi_library/xilinx/common/ad_serdes_in.v /^ wire [(DATA_WIDTH-1):0] data_shift2_s;$/;" n module:ad_serdes_in data_src_count hdl/enc_control.v /^ input [ 31:0] data_src_count,$/;" p module:enc_control data_src_count sim/tb_enc_control.v /^ reg [31:0] data_src_count;$/;" r module:tb_enc_control +data_start_VN hdl/LDPC_DEC_PRO.v /^ wire data_start_VN;$/;" n module:LDPC_DEC_PRO +data_start_VN hdl/VN_PRO.v /^ output data_start_VN, \/\/产生判决结果数据可以输出标志，高脉冲 /;" p module:VN_PRO +data_start_ck_VN hdl/LDPC_DEC_PRO.v /^ wire data_start_ck_VN;$/;" n module:LDPC_DEC_PRO +data_start_ck_VN hdl/VN_PRO.v /^ output data_start_ck_VN, \/\/产生判决结果数据开始存储标志，高脉冲$/;" p module:VN_PRO data_sum hdl/PAPR.v /^ reg [SUM_WIDTH-1:0] data_sum;$/;" r module:PAPR data_t adi_library/xilinx/common/ad_serdes_out.v /^ wire [(DATA_WIDTH-1):0] data_t;$/;" n module:ad_serdes_out -data_tx_test hdl/Transmitter.v /^ wire [7:0] data_tx_test;$/;" n module:Transmitter +data_tx_test hdl/Transmitter.v /^ wire [ 7:0] data_tx_test;$/;" n module:Transmitter data_valid adi_library/util_extract/util_extract.v /^ input data_valid,$/;" p module:util_extract data_wr_en adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ wire data_wr_en = fifo_wr_en[0];$/;" n module:util_cpack2_impl dataa_x adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) input [ D_DW-1:0] dataa_x,$/;" p module:ad_dds_cordic_pipe @@ -3280,10 +3991,10 @@ dbuf adi_library/common/util_delay.v /^ reg [DATA_WIDTH-1:0] dbuf[ dc_offset adi_library/xilinx/common/ad_dcfilter.v /^ reg [47:0] dc_offset = 'd0;$/;" r module:ad_dcfilter dc_offset_d adi_library/xilinx/common/ad_dcfilter.v /^ reg [47:0] dc_offset_d = 'd0;$/;" r module:ad_dcfilter dc_offset_s adi_library/xilinx/common/ad_dcfilter.v /^ wire [47:0] dc_offset_s;$/;" n module:ad_dcfilter -dc_removal_dout_i hdl/RecvTop.v /^ output [11:0] dc_removal_dout_i, \/\/MGC_adaptation、去直流输出$/;" p module:RecvTop -dc_removal_dout_q hdl/RecvTop.v /^ output [11:0] dc_removal_dout_q,$/;" p module:RecvTop -dc_value_i hdl/RecvTop.v /^ output [11:0] dc_value_i,$/;" p module:RecvTop -dc_value_q hdl/RecvTop.v /^ output [11:0] dc_value_q,$/;" p module:RecvTop +dc_removal_dout_i hdl/RecvTop.v /^ wire [11:0] dc_removal_dout_i; \/\/MGC_adaptation、去直流输出$/;" n module:RecvTop +dc_removal_dout_q hdl/RecvTop.v /^ wire [11:0] dc_removal_dout_q;$/;" n module:RecvTop +dc_value_i hdl/RecvTop.v /^ wire [11:0] dc_value_i;$/;" n module:RecvTop +dc_value_q hdl/RecvTop.v /^ wire [11:0] dc_value_q;$/;" n module:RecvTop dcfilt_coeff adi_library/xilinx/common/ad_dcfilter.v /^ input [15:0] dcfilt_coeff,$/;" p module:ad_dcfilter dcfilt_coeff_d adi_library/xilinx/common/ad_dcfilter.v /^ reg [15:0] dcfilt_coeff_d = 'd0;$/;" r module:ad_dcfilter dcfilt_enb adi_library/xilinx/common/ad_dcfilter.v /^ input dcfilt_enb,$/;" p module:ad_dcfilter @@ -3336,8 +4047,41 @@ dds_update hdl/DDS_compensate.v /^ reg dds_update = 0; \/\/ identifier of update dds_update_d1 hdl/DDS_compensate.v /^ reg dds_update_d1 = 0,dds_update_d2 = 0;$/;" r module:DDS_compensate dds_update_d2 hdl/DDS_compensate.v /^ reg dds_update_d1 = 0,dds_update_d2 = 0;$/;" r module:DDS_compensate dds_update_df hdl/DDS_compensate.v /^ reg [DDS_width:0] dds_update_df = 0;$/;" r module:DDS_compensate -debug_loss hdl/RecvTop.v /^ input debug_loss$/;" p module:RecvTop +deal_end hdl/CK_PRO.v /^ reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_e/;" r module:CK_PRO +deal_end_MS hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ wire deal_end_MS;$/;" n module:CCSDS_LDPC_DEC_K1024_R12 +deal_end_MS hdl/Message_Store.v /^ output deal_end_MS, \/\/转换完成标志$/;" p module:Message_Store +deal_end_d1 hdl/CK_PRO.v /^ reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_e/;" r module:CK_PRO +deal_end_d2 hdl/CK_PRO.v /^ reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_e/;" r module:CK_PRO +deal_end_d3 hdl/CK_PRO.v /^ reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_e/;" r module:CK_PRO +deal_end_d4 hdl/CK_PRO.v /^ reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_e/;" r module:CK_PRO +deal_end_d5 hdl/CK_PRO.v /^ reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_e/;" r module:CK_PRO +deal_end_d6 hdl/CK_PRO.v /^ reg deal_end_d6 = 1'd0;$/;" r module:CK_PRO debug_loss hdl/SCFDE_recv_FrameSync.v /^ input debug_loss,$/;" p module:SCFDE_recv_FrameSync +dec_01 hdl/CK_PRO.v /^ reg [127:0] dec_01 = 128'd0, dec_02 = 128'd0, dec_03 = 128'd0, dec_04 = 128'd0;$/;" r module:CK_PRO +dec_01_d1 hdl/CK_PRO.v /^ reg [127:0] dec_01_d1 = 128'd0, dec_02_d1 = 128'd0, dec_03_d1 = 128'd0, dec_04_d1 = 128'd0;$/;" r module:CK_PRO +dec_02 hdl/CK_PRO.v /^ reg [127:0] dec_01 = 128'd0, dec_02 = 128'd0, dec_03 = 128'd0, dec_04 = 128'd0;$/;" r module:CK_PRO +dec_02_d1 hdl/CK_PRO.v /^ reg [127:0] dec_01_d1 = 128'd0, dec_02_d1 = 128'd0, dec_03_d1 = 128'd0, dec_04_d1 = 128'd0;$/;" r module:CK_PRO +dec_03 hdl/CK_PRO.v /^ reg [127:0] dec_01 = 128'd0, dec_02 = 128'd0, dec_03 = 128'd0, dec_04 = 128'd0;$/;" r module:CK_PRO +dec_03_d1 hdl/CK_PRO.v /^ reg [127:0] dec_01_d1 = 128'd0, dec_02_d1 = 128'd0, dec_03_d1 = 128'd0, dec_04_d1 = 128'd0;$/;" r module:CK_PRO +dec_04 hdl/CK_PRO.v /^ reg [127:0] dec_01 = 128'd0, dec_02 = 128'd0, dec_03 = 128'd0, dec_04 = 128'd0;$/;" r module:CK_PRO +dec_04_d1 hdl/CK_PRO.v /^ reg [127:0] dec_01_d1 = 128'd0, dec_02_d1 = 128'd0, dec_03_d1 = 128'd0, dec_04_d1 = 128'd0;$/;" r module:CK_PRO +dec_05 hdl/CK_PRO.v /^ reg [127:0] dec_05 = 128'd0, dec_06 = 128'd0, dec_07 = 128'd0, dec_08 = 128'd0;$/;" r module:CK_PRO +dec_05_d1 hdl/CK_PRO.v /^ reg [127:0] dec_05_d1 = 128'd0, dec_06_d1 = 128'd0, dec_07_d1 = 128'd0, dec_08_d1 = 128'd0;$/;" r module:CK_PRO +dec_06 hdl/CK_PRO.v /^ reg [127:0] dec_05 = 128'd0, dec_06 = 128'd0, dec_07 = 128'd0, dec_08 = 128'd0;$/;" r module:CK_PRO +dec_06_d1 hdl/CK_PRO.v /^ reg [127:0] dec_05_d1 = 128'd0, dec_06_d1 = 128'd0, dec_07_d1 = 128'd0, dec_08_d1 = 128'd0;$/;" r module:CK_PRO +dec_07 hdl/CK_PRO.v /^ reg [127:0] dec_05 = 128'd0, dec_06 = 128'd0, dec_07 = 128'd0, dec_08 = 128'd0;$/;" r module:CK_PRO +dec_07_d1 hdl/CK_PRO.v /^ reg [127:0] dec_05_d1 = 128'd0, dec_06_d1 = 128'd0, dec_07_d1 = 128'd0, dec_08_d1 = 128'd0;$/;" r module:CK_PRO +dec_08 hdl/CK_PRO.v /^ reg [127:0] dec_05 = 128'd0, dec_06 = 128'd0, dec_07 = 128'd0, dec_08 = 128'd0;$/;" r module:CK_PRO +dec_08_d1 hdl/CK_PRO.v /^ reg [127:0] dec_05_d1 = 128'd0, dec_06_d1 = 128'd0, dec_07_d1 = 128'd0, dec_08_d1 = 128'd0;$/;" r module:CK_PRO +dec_09 hdl/CK_PRO.v /^ reg [127:0] dec_09 = 128'd0, dec_10 = 128'd0, dec_11 = 128'd0, dec_12 = 128'd0;$/;" r module:CK_PRO +dec_09_d1 hdl/CK_PRO.v /^ reg [127:0] dec_09_d1 = 128'd0, dec_10_d1 = 128'd0, dec_11_d1 = 128'd0, dec_12_d1 = 128'd0;$/;" r module:CK_PRO +dec_10 hdl/CK_PRO.v /^ reg [127:0] dec_09 = 128'd0, dec_10 = 128'd0, dec_11 = 128'd0, dec_12 = 128'd0;$/;" r module:CK_PRO +dec_10_d1 hdl/CK_PRO.v /^ reg [127:0] dec_09_d1 = 128'd0, dec_10_d1 = 128'd0, dec_11_d1 = 128'd0, dec_12_d1 = 128'd0;$/;" r module:CK_PRO +dec_11 hdl/CK_PRO.v /^ reg [127:0] dec_09 = 128'd0, dec_10 = 128'd0, dec_11 = 128'd0, dec_12 = 128'd0;$/;" r module:CK_PRO +dec_11_d1 hdl/CK_PRO.v /^ reg [127:0] dec_09_d1 = 128'd0, dec_10_d1 = 128'd0, dec_11_d1 = 128'd0, dec_12_d1 = 128'd0;$/;" r module:CK_PRO +dec_12 hdl/CK_PRO.v /^ reg [127:0] dec_09 = 128'd0, dec_10 = 128'd0, dec_11 = 128'd0, dec_12 = 128'd0;$/;" r module:CK_PRO +dec_12_d1 hdl/CK_PRO.v /^ reg [127:0] dec_09_d1 = 128'd0, dec_10_d1 = 128'd0, dec_11_d1 = 128'd0, dec_12_d1 = 128'd0;$/;" r module:CK_PRO +dec_proc hdl/CK_PRO.v /^ reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_e/;" r module:CK_PRO dec_pulse hdl/ad9361_mgc_pin_ctrl.v /^ wire dec_pulse;$/;" n module:ad9361_mgc_pin_ctrl dec_rate adi_library/common/util_dec256sinc24b.v /^ input [15:0] dec_rate);$/;" p module:util_dec256sinc24b decimate adi_library/util_fir_dec/util_fir_dec.v /^ input decimate,$/;" p module:util_fir_dec @@ -3512,19 +4256,157 @@ din adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ input [31:0] din;$/;" p f din hdl/FrameMerge.v /^ input din,$/;" p module:FrameMerge din hdl/shift_reg.v /^ input [DATA_WIDTH-1:0] din,$/;" p module:shift_reg din hdl/trunc_25to12_2dly.v /^ input [24:0] din;$/;" p module:trunc_25to12_2dly +din01 hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ reg [WIDTH-1:0] din01 = 8'd0;$/;" r module:CCSDS_LDPC_DEC_K1024_R12 +din01 hdl/LDPC_DEC_PRO.v /^ input [WIDTH-1:0] din01, \/\/译码输入数据， 软信息， 对应时刻 N$/;" p module:LDPC_DEC_PRO +din01 hdl/abs_min_4din.v /^ input [WIDTH-1:0] din01, \/\/din01 (b) ? (a) : (b)}$/;" d module:ad_mem_asym max adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ `define max(a,b) {(a) > (b) ? (a) : (b)}$/;" d module:axi_dacfifo_rd max adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ `define max(a,b) {(a) > (b) ? (a) : (b)}$/;" d module:axi_dacfifo_wr @@ -5920,6 +6985,8 @@ max_component1 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] max_component1 max_component2 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] max_component2;$/;" r module:MagnitudeEstimator max_component3 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] max_component3;$/;" r module:MagnitudeEstimator max_res hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] max_res;$/;" r module:MagnitudeEstimator +max_slot_num hdl/net_city.v /^ input [07:0] max_slot_num,$/;" p module:net_city +max_slot_num hdl/system_top.v /^ wire [ 7:0] max_slot_num;$/;" n module:system_top mdc_mdio adi_library/util_gmii_to_rgmii/mdc_mdio.v /^module mdc_mdio #($/;" m mdc_mdio_in adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) mdc_mdio_in($/;" i module:util_gmii_to_rgmii typeref:module:mdc_mdio mdio_in_r adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ input mdio_in_r,$/;" p module:mdc_mdio @@ -5928,7 +6995,7 @@ mdio_in_w adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ input mdio_in_w adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input mdio_in_w,$/;" p module:util_gmii_to_rgmii mdio_mdc adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ input mdio_mdc,$/;" p module:mdc_mdio mdio_mdc adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input mdio_mdc,$/;" p module:util_gmii_to_rgmii -mean_temp hdl/RecvTop.v /^ output [24:0] mean_temp,$/;" p module:RecvTop +mean_temp hdl/RecvTop.v /^ wire [24:0] mean_temp;$/;" n module:RecvTop measured_burst_length adi_library/axi_dmac/axi_dmac_response_manager.v /^ output reg [BYTES_PER_BURST_WIDTH-1:0] measured_burst_length = 'h0,$/;" p module:axi_dmac_response_manager measured_burst_length adi_library/axi_dmac/request_arb.v /^ output [BYTES_PER_BURST_WIDTH-1:0] measured_burst_length,$/;" p module:dmac_request_arb measured_last_burst_length adi_library/axi_dmac/address_generator.v /^ input [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,$/;" p module:dmac_address_generator @@ -5937,6 +7004,7 @@ measured_last_burst_length adi_library/axi_dmac/dest_axi_mm.v /^ input [BEATS_P measured_last_burst_length adi_library/axi_dmac/src_axi_mm.v /^ output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,$/;" p module:dmac_src_mm_axi measured_last_burst_length adi_library/axi_dmac/src_axi_stream.v /^ output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,$/;" p module:dmac_src_axi_stream measured_last_burst_length adi_library/axi_dmac/src_fifo_inf.v /^ output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,$/;" p module:dmac_src_fifo_inf +mem sim/tb_sys_tx_rx_e_d.v /^ reg [31:0] mem [0:31]; \/\/ 1024 bit$/;" r module:tb_sys_tx_rx_e_d mem_data adi_library/axi_dmac/axi_dmac_resize_dest.v /^ input [DATA_WIDTH_MEM-1:0] mem_data,$/;" p module:axi_dmac_resize_dest mem_data adi_library/axi_dmac/axi_dmac_resize_src.v /^ output [DATA_WIDTH_MEM-1:0] mem_data,$/;" p module:axi_dmac_resize_src mem_data_last adi_library/axi_dmac/axi_dmac_resize_dest.v /^ input mem_data_last,$/;" p module:axi_dmac_resize_dest @@ -5948,7 +7016,9 @@ mem_data_valid adi_library/axi_dmac/axi_dmac_resize_dest.v /^ input mem_data_va mem_data_valid adi_library/axi_dmac/axi_dmac_resize_src.v /^ output mem_data_valid,$/;" p module:axi_dmac_resize_src mem_data_valid_bytes adi_library/axi_dmac/axi_dmac_resize_src.v /^ output [BYTES_PER_BEAT_WIDTH_MEM-1:0] mem_data_valid_bytes,$/;" p module:axi_dmac_resize_src mem_i sim/tb_Receiver.v /^ reg [11:0] mem_i [10000:0];$/;" r module:tb_Receiver +mem_i sim/tb_recv_top.v /^ reg [11:0] mem_i [0:637049];$/;" r module:tb_recv_top mem_q sim/tb_Receiver.v /^ reg [11:0] mem_q [10000:0];$/;" r module:tb_Receiver +mem_q sim/tb_recv_top.v /^ reg [11:0] mem_q [0:637049];$/;" r module:tb_recv_top memread adi_library/common/ad_mem_asym.v /^ always @(posedge clkb) begin : memread$/;" b module:ad_mem_asym memwrite adi_library/common/ad_mem_asym.v /^ always @(posedge clka) begin : memwrite$/;" b module:ad_mem_asym message adi_library/axi_dmac/tb/regmap_tb.v /^ input [255:0] message;$/;" p task:dmac_regmap_tb.check_all_registers @@ -5957,21 +7027,25 @@ mf_data_i hdl/Receiver.v /^ reg [11:0] mf_data_i;$/;" r module:Receiver mf_data_interp16_i hdl/Receiver.v /^ wire [31:0] mf_data_interp16_i;$/;" n module:Receiver mf_data_interp16_q hdl/Receiver.v /^ wire [31:0] mf_data_interp16_q;$/;" n module:Receiver mf_data_interp4_i hdl/Receiver.v /^ wire [31:0] mf_data_interp4_i;$/;" n module:Receiver +mf_data_interp4_i hdl/RecvTop.v /^ wire [31:0] mf_data_interp4_i;$/;" n module:RecvTop mf_data_interp4_q hdl/Receiver.v /^ wire [31:0] mf_data_interp4_q;$/;" n module:Receiver +mf_data_interp4_q hdl/RecvTop.v /^ wire [31:0] mf_data_interp4_q;$/;" n module:RecvTop mf_data_q hdl/Receiver.v /^ reg [11:0] mf_data_q;$/;" r module:Receiver +mf_fir_s_tready_i hdl/RecvTop.v /^ wire mf_fir_s_tready_i;$/;" n module:RecvTop +mf_fir_s_tready_q hdl/RecvTop.v /^ wire mf_fir_s_tready_q;$/;" n module:RecvTop mf_i hdl/DAGC_v2.v /^ wire [ 9:0] mf_i;$/;" n module:DAGC_v2 mf_q hdl/DAGC_v2.v /^ wire [ 9:0] mf_q;$/;" n module:DAGC_v2 mgc1_rdy hdl/DAGC_v2.v /^ input mgc1_rdy,$/;" p module:DAGC_v2 -mgc1_rdy hdl/RecvTop.v /^ output mgc1_rdy,$/;" p module:RecvTop +mgc1_rdy hdl/RecvTop.v /^ wire mgc1_rdy;$/;" n module:RecvTop mgc_rdy hdl/DAGC_v2.v /^ output reg mgc_rdy,$/;" p module:DAGC_v2 -mgc_rdy hdl/RecvTop.v /^ wire mgc_rdy;$/;" n module:RecvTop +mgc_rdy hdl/RecvTop.v /^ wire mgc_rdy;$/;" n module:RecvTop mgc_rdy hdl/freqestm.v /^ input mgc_rdy,$/;" p module:freqestm mgc_rdy_d0 hdl/DAGC_v2.v /^ reg mgc_rdy_d0;$/;" r module:DAGC_v2 mgc_rdy_d1 hdl/DAGC_v2.v /^ reg mgc_rdy_d1;$/;" r module:DAGC_v2 mgc_rdy_d2 hdl/DAGC_v2.v /^ reg mgc_rdy_d2;$/;" r module:DAGC_v2 mgc_rdy_d3 hdl/DAGC_v2.v /^ reg mgc_rdy_d3;$/;" r module:DAGC_v2 mgc_rdy_d4 hdl/DAGC_v2.v /^ reg mgc_rdy_d4;$/;" r module:DAGC_v2 -mgc_start hdl/RecvTop.v /^ wire mgc_start;$/;" n module:RecvTop +mgc_start hdl/RecvTop.v /^ wire mgc_start;$/;" n module:RecvTop min adi_library/common/ad_mem_asym.v /^ `define min(a,b) {(a) < (b) ? (a) : (b)}$/;" d module:ad_mem_asym min adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ `define min(a,b) {(a) < (b) ? (a) : (b)}$/;" d module:axi_dacfifo_rd min adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ `define min(a,b) {(a) < (b) ? (a) : (b)}$/;" d module:axi_dacfifo_wr @@ -5979,7 +7053,72 @@ min hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] min;$/;" r module:Magnitu min_component1 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] min_component1;$/;" r module:MagnitudeEstimator min_component2 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] min_component2;$/;" r module:MagnitudeEstimator min_component3 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] min_component3;$/;" r module:MagnitudeEstimator +min_level_1_01 hdl/CNU_3din.v /^ reg [WIDTH-1:0] min_level_1_01=8'd0,min_level_1_02=8'd0;$/;" r module:CNU_3din +min_level_1_01 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0,abs01_reg2=8'd0,min_level_1_01=8'/;" r module:CNU_6din +min_level_1_02 hdl/CNU_3din.v /^ reg [WIDTH-1:0] min_level_1_01=8'd0,min_level_1_02=8'd0;$/;" r module:CNU_3din +min_level_1_02 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0,abs02_reg2=8'd0,min_level_1_02=8'/;" r module:CNU_6din +min_level_1_03 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0,abs03_reg2=8'd0,min_level_1_03=8'/;" r module:CNU_6din +min_level_1_04 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs04=8'd0,abs04_reg0=8'd0,abs04_reg1=8'd0,abs04_reg2=8'd0,min_level_1_04=8'/;" r module:CNU_6din +min_level_1_05 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs05=8'd0,abs05_reg0=8'd0,abs05_reg1=8'd0,abs05_reg2=8'd0,min_level_1_05=8'/;" r module:CNU_6din +min_level_1_05_reg0 hdl/CNU_6din.v /^ reg [WIDTH-1:0] min_level_1_05_reg0=8'd0,min_level_1_06_reg0=8'd0;$/;" r module:CNU_6din +min_level_1_06 hdl/CNU_6din.v /^ reg [WIDTH-1:0] abs06=8'd0,abs06_reg0=8'd0,abs06_reg1=8'd0,abs06_reg2=8'd0,min_level_1_06=8'/;" r module:CNU_6din +min_level_1_06_reg0 hdl/CNU_6din.v /^ reg [WIDTH-1:0] min_level_1_05_reg0=8'd0,min_level_1_06_reg0=8'd0;$/;" r module:CNU_6din +min_level_2_01 hdl/CNU_3din.v /^ reg [WIDTH-1:0] min_level_2_01=8'd0,min_level_2_02=8'd0;$/;" r module:CNU_3din +min_level_2_01 hdl/CNU_6din.v /^ wire [WIDTH-1:0] min_level_2_01,min_level_2_02,min_level_3_01,min_level_3_02;$/;" n module:CNU_6din +min_level_2_02 hdl/CNU_3din.v /^ reg [WIDTH-1:0] min_level_2_01=8'd0,min_level_2_02=8'd0;$/;" r module:CNU_3din +min_level_2_02 hdl/CNU_6din.v /^ wire [WIDTH-1:0] min_level_2_01,min_level_2_02,min_level_3_01,min_level_3_02;$/;" n module:CNU_6din +min_level_3_01 hdl/CNU_6din.v /^ wire [WIDTH-1:0] min_level_2_01,min_level_2_02,min_level_3_01,min_level_3_02;$/;" n module:CNU_6din +min_level_3_02 hdl/CNU_6din.v /^ wire [WIDTH-1:0] min_level_2_01,min_level_2_02,min_level_3_01,min_level_3_02;$/;" n module:CNU_6din min_res hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] min_res;$/;" r module:MagnitudeEstimator +minus1 hdl/VNU_2din.v /^ reg [9:0] minus1=10'd0;$/;" r module:VNU_2din +minus1 hdl/VNU_3din.v /^ reg [9:0] minus1=10'd0;$/;" r module:VNU_3din +minus1 hdl/VNU_6din.v /^ reg [10:0] minus1=11'd0;$/;" r module:VNU_6din +minus1_abs hdl/VNU_2din.v /^ reg [9:0] minus1_abs=10'd0;$/;" r module:VNU_2din +minus1_abs hdl/VNU_3din.v /^ reg [9:0] minus1_abs=10'd0;$/;" r module:VNU_3din +minus1_abs hdl/VNU_6din.v /^ reg [10:0] minus1_abs=11'd0;$/;" r module:VNU_6din +minus1_reg0 hdl/VNU_2din.v /^ reg [9:0] minus1_reg0=10'd0;$/;" r module:VNU_2din +minus1_reg0 hdl/VNU_3din.v /^ reg [9:0] minus1_reg0=10'd0;$/;" r module:VNU_3din +minus1_reg0 hdl/VNU_6din.v /^ reg [10:0] minus1_reg0=11'd0;$/;" r module:VNU_6din +minus1_reg1 hdl/VNU_2din.v /^ reg [9:0] minus1_reg1=10'd0;$/;" r module:VNU_2din +minus1_reg1 hdl/VNU_3din.v /^ reg [9:0] minus1_reg1=10'd0;$/;" r module:VNU_3din +minus1_reg1 hdl/VNU_6din.v /^ reg [10:0] minus1_reg1=11'd0;$/;" r module:VNU_6din +minus1_reg2 hdl/VNU_2din.v /^ reg [9:0] minus1_reg2=10'd0;$/;" r module:VNU_2din +minus1_reg2 hdl/VNU_3din.v /^ reg [9:0] minus1_reg2=10'd0;$/;" r module:VNU_3din +minus2 hdl/VNU_2din.v /^ reg [9:0] minus2=10'd0;$/;" r module:VNU_2din +minus2 hdl/VNU_3din.v /^ reg [9:0] minus2=10'd0;$/;" r module:VNU_3din +minus2 hdl/VNU_6din.v /^ reg [10:0] minus2=11'd0;$/;" r module:VNU_6din +minus2_abs hdl/VNU_2din.v /^ reg [9:0] minus2_abs=10'd0;$/;" r module:VNU_2din +minus2_abs hdl/VNU_3din.v /^ reg [9:0] minus2_abs=10'd0;$/;" r module:VNU_3din +minus2_abs hdl/VNU_6din.v /^ reg [10:0] minus2_abs=11'd0;$/;" r module:VNU_6din +minus2_reg0 hdl/VNU_2din.v /^ reg [9:0] minus2_reg0=10'd0;$/;" r module:VNU_2din +minus2_reg0 hdl/VNU_3din.v /^ reg [9:0] minus2_reg0=10'd0;$/;" r module:VNU_3din +minus2_reg0 hdl/VNU_6din.v /^ reg [10:0] minus2_reg0=11'd0;$/;" r module:VNU_6din +minus2_reg1 hdl/VNU_2din.v /^ reg [9:0] minus2_reg1=10'd0;$/;" r module:VNU_2din +minus2_reg1 hdl/VNU_3din.v /^ reg [9:0] minus2_reg1=10'd0;$/;" r module:VNU_3din +minus2_reg1 hdl/VNU_6din.v /^ reg [10:0] minus2_reg1=11'd0;$/;" r module:VNU_6din +minus2_reg2 hdl/VNU_2din.v /^ reg [9:0] minus2_reg2=10'd0;$/;" r module:VNU_2din +minus2_reg2 hdl/VNU_3din.v /^ reg [9:0] minus2_reg2=10'd0;$/;" r module:VNU_3din +minus3 hdl/VNU_3din.v /^ reg [9:0] minus3=10'd0;$/;" r module:VNU_3din +minus3 hdl/VNU_6din.v /^ reg [10:0] minus3=11'd0;$/;" r module:VNU_6din +minus3_abs hdl/VNU_3din.v /^ reg [9:0] minus3_abs=10'd0;$/;" r module:VNU_3din +minus3_abs hdl/VNU_6din.v /^ reg [10:0] minus3_abs=11'd0;$/;" r module:VNU_6din +minus3_reg0 hdl/VNU_3din.v /^ reg [9:0] minus3_reg0=10'd0;$/;" r module:VNU_3din +minus3_reg0 hdl/VNU_6din.v /^ reg [10:0] minus3_reg0=11'd0;$/;" r module:VNU_6din +minus3_reg1 hdl/VNU_3din.v /^ reg [9:0] minus3_reg1=10'd0;$/;" r module:VNU_3din +minus3_reg1 hdl/VNU_6din.v /^ reg [10:0] minus3_reg1=11'd0;$/;" r module:VNU_6din +minus3_reg2 hdl/VNU_3din.v /^ reg [9:0] minus3_reg2=10'd0;$/;" r module:VNU_3din +minus4 hdl/VNU_6din.v /^ reg [10:0] minus4=11'd0;$/;" r module:VNU_6din +minus4_abs hdl/VNU_6din.v /^ reg [10:0] minus4_abs=11'd0;$/;" r module:VNU_6din +minus4_reg0 hdl/VNU_6din.v /^ reg [10:0] minus4_reg0=11'd0;$/;" r module:VNU_6din +minus4_reg1 hdl/VNU_6din.v /^ reg [10:0] minus4_reg1=11'd0;$/;" r module:VNU_6din +minus5 hdl/VNU_6din.v /^ reg [10:0] minus5=11'd0;$/;" r module:VNU_6din +minus5_abs hdl/VNU_6din.v /^ reg [10:0] minus5_abs=11'd0;$/;" r module:VNU_6din +minus5_reg0 hdl/VNU_6din.v /^ reg [10:0] minus5_reg0=11'd0;$/;" r module:VNU_6din +minus5_reg1 hdl/VNU_6din.v /^ reg [10:0] minus5_reg1=11'd0;$/;" r module:VNU_6din +minus6 hdl/VNU_6din.v /^ reg [10:0] minus6=11'd0;$/;" r module:VNU_6din +minus6_abs hdl/VNU_6din.v /^ reg [10:0] minus6_abs=11'd0;$/;" r module:VNU_6din +minus6_reg0 hdl/VNU_6din.v /^ reg [10:0] minus6_reg0=11'd0;$/;" r module:VNU_6din +minus6_reg1 hdl/VNU_6din.v /^ reg [10:0] minus6_reg1=11'd0;$/;" r module:VNU_6din mmcm_clk_0 adi_library/xilinx/common/ad_mmcm_drp.v /^ output mmcm_clk_0,$/;" p module:ad_mmcm_drp mmcm_clk_0_s adi_library/xilinx/common/ad_mmcm_drp.v /^ wire mmcm_clk_0_s;$/;" n module:ad_mmcm_drp mmcm_clk_1 adi_library/xilinx/common/ad_mmcm_drp.v /^ output mmcm_clk_1,$/;" p module:ad_mmcm_drp @@ -6032,11 +7171,13 @@ n adi_library/util_pack/util_pack_common/pack_ctrl.v /^ integer n;$/;" r module n adi_library/util_rfifo/util_rfifo.v /^ genvar n;$/;" r module:util_rfifo n adi_library/util_wfifo/util_wfifo.v /^ genvar n;$/;" r module:util_wfifo n adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ genvar n;$/;" r module:axi_xcvrlb +nd hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ reg nd = 1'd0;$/;" r module:CCSDS_LDPC_DEC_K1024_R12 nd hdl/FrameMerge.v /^ input nd,$/;" p module:FrameMerge nd hdl/IQmerge.v /^ input nd,$/;" p module:IQmerge -nd hdl/SC_FDE_TOP.v /^ input nd,$/;" p module:SC_FDE_TOP +nd hdl/LDPC_DEC_PRO.v /^ input nd, \/\/译码输入数据有效标志，高有效$/;" p module:LDPC_DEC_PRO +nd hdl/SC_FDE_TOP.v /^ input nd,$/;" p module:SC_FDE_TOP nd hdl/data_ow.v /^ input nd,$/;" p module:data_ow -nd hdl/phase_adjust.v /^ input nd,$/;" p module:phase_adjust +nd hdl/phase_adjust.v /^ input nd,$/;" p module:phase_adjust nd_1 hdl/TSync_Abs_new16.v /^ reg nd_1 = 1'd0;$/;" r module:TSync_Abs_new16 nd_1 hdl/TSync_Abs_new4.v /^ reg nd_1 = 1'd0;$/;" r module:TSync_Abs_new4 nd_2 hdl/TSync_Abs_new16.v /^ reg nd_2 = 1'd0;$/;" r module:TSync_Abs_new16 @@ -6051,11 +7192,15 @@ nd_6 hdl/TSync_Abs_new16.v /^ reg nd_6 = 1'd0;$/;" r module:TSync_Abs_new16 nd_6 hdl/TSync_Abs_new4.v /^ reg nd_6 = 1'd0;$/;" r module:TSync_Abs_new4 nd_7 hdl/TSync_Abs_new16.v /^ reg nd_7 = 1'd0;$/;" r module:TSync_Abs_new16 nd_7 hdl/TSync_Abs_new4.v /^ reg nd_7 = 1'd0;$/;" r module:TSync_Abs_new4 +nd_CK hdl/LDPC_DEC_PRO.v /^ reg nd_CK = 1'd0;$/;" r module:LDPC_DEC_PRO nd_EstNoise hdl/Chn_Estimate.v /^ input nd_EstNoise,$/;" p module:Chn_Estimate nd_EstNoise hdl/Noise_Estimate.v /^ output reg nd_EstNoise = 1'd0,$/;" p module:Noise_Estimate -nd_EstNoise hdl/SC_FDE_TOP.v /^ wire nd_EstNoise;$/;" n module:SC_FDE_TOP -nd_SC_FDE_dout hdl/RecvTop.v /^ output nd_SC_FDE_dout, \/\/SC_FDE输出nd$/;" p module:RecvTop -nd_SC_FDE_dout hdl/SC_FDE_TOP.v /^ output nd_SC_FDE_dout,$/;" p module:SC_FDE_TOP +nd_EstNoise hdl/SC_FDE_TOP.v /^ wire nd_EstNoise;$/;" n module:SC_FDE_TOP +nd_MS hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ reg nd_MS = 1'd0;$/;" r module:CCSDS_LDPC_DEC_K1024_R12 +nd_MS hdl/Message_Store.v /^ input nd_MS, \/\/译码输入数据有效标志，高有效$/;" p module:Message_Store +nd_OUTCK hdl/CK_PRO.v /^ input nd_OUTCK,$/;" p module:CK_PRO +nd_SC_FDE_dout hdl/RecvTop.v /^ wire nd_SC_FDE_dout; \/\/SC_FDE输出nd$/;" n module:RecvTop +nd_SC_FDE_dout hdl/SC_FDE_TOP.v /^ output nd_SC_FDE_dout,$/;" p module:SC_FDE_TOP nd_SC_FDE_dout hdl/data_equalizer.v /^ output reg nd_SC_FDE_dout = 1'd0,$/;" p module:data_equalizer nd_acc hdl/TSync_Abs_new16.v /^ reg nd_acc = 1'd0;$/;" r module:TSync_Abs_new16 nd_acc hdl/TSync_Abs_new4.v /^ reg nd_acc = 1'd0;$/;" r module:TSync_Abs_new4 @@ -6066,13 +7211,12 @@ nd_acc2 hdl/TSync_Abs_new4.v /^ reg nd_acc2 = 1'd0;$/;" r module:TSync_Abs_new4 nd_acc3 hdl/TSync_Abs_new16.v /^ reg nd_acc3 = 1'd0;$/;" r module:TSync_Abs_new16 nd_acc4 hdl/TSync_Abs_new16.v /^ reg nd_acc4 = 1'd0;$/;" r module:TSync_Abs_new16 nd_ber hdl/FrameMerge.v /^ output reg [0:0] nd_ber = 1'd0, \/\/比较误码率$/;" p module:FrameMerge -nd_ber hdl/RecvTop.v /^ wire nd_ber;$/;" n module:RecvTop nd_comdiv_mulin hdl/Chn_Estimate.v /^reg [0:0] nd_comdiv_mulin = 1'd0;$/;" r module:Chn_Estimate nd_comdiv_mulout hdl/Chn_Estimate.v /^reg [0:0] nd_comdiv_mulout = 1'd0;$/;" r module:Chn_Estimate nd_comdiv_mulout_d1 hdl/Chn_Estimate.v /^reg [0:0] nd_comdiv_mulout_d1 = 1'd0;$/;" r module:Chn_Estimate nd_comdiv_mulout_d2 hdl/Chn_Estimate.v /^reg [0:0] nd_comdiv_mulout_d2 = 1'd0;$/;" r module:Chn_Estimate -nd_datafft hdl/SC_FDE_TOP.v /^ wire nd_datafft;$/;" n module:SC_FDE_TOP -nd_dataifft hdl/SC_FDE_TOP.v /^ wire nd_dataifft;$/;" n module:SC_FDE_TOP +nd_datafft hdl/SC_FDE_TOP.v /^ wire nd_datafft;$/;" n module:SC_FDE_TOP +nd_dataifft hdl/SC_FDE_TOP.v /^ wire nd_dataifft;$/;" n module:SC_FDE_TOP nd_flag hdl/TSync_Abs_new16.v /^ reg nd_flag = 1'd0;$/;" r module:TSync_Abs_new16 nd_flag hdl/TSync_Abs_new4.v /^ reg nd_flag = 1'd0;$/;" r module:TSync_Abs_new4 nd_noise_d0 hdl/Noise_Estimate.v /^ reg nd_noise_d0 = 1'd0;$/;" r module:Noise_Estimate @@ -6085,11 +7229,11 @@ nd_noise_d6 hdl/Noise_Estimate.v /^ reg nd_noise_d6 = 1'd0;$/;" r module:Noise nd_pilot hdl/data_ow.v /^ reg [0:0] nd_pilot = 1'd0;$/;" r module:data_ow nd_pilot2 hdl/Chn_Estimate.v /^ input nd_pilot2,$/;" p module:Chn_Estimate nd_pilot2 hdl/Noise_Estimate.v /^ input nd_pilot2,$/;" p module:Noise_Estimate -nd_pilot2 hdl/SC_FDE_TOP.v /^ wire nd_pilot2;$/;" n module:SC_FDE_TOP +nd_pilot2 hdl/SC_FDE_TOP.v /^ wire nd_pilot2;$/;" n module:SC_FDE_TOP nd_pilot2 hdl/data_equalizer.v /^ input nd_pilot2,$/;" p module:data_equalizer nd_pilot2 hdl/data_ow.v /^ output reg nd_pilot2 = 1'd0,$/;" p module:data_ow -nd_pilotfft hdl/SC_FDE_TOP.v /^ wire nd_pilotfft;$/;" n module:SC_FDE_TOP -nd_pilotifft hdl/SC_FDE_TOP.v /^ wire nd_pilotifft;$/;" n module:SC_FDE_TOP +nd_pilotfft hdl/SC_FDE_TOP.v /^ wire nd_pilotfft;$/;" n module:SC_FDE_TOP +nd_pilotifft hdl/SC_FDE_TOP.v /^ wire nd_pilotifft;$/;" n module:SC_FDE_TOP nd_recvnet_dout hdl/FrameMerge.v /^ reg nd_recvnet_dout; $/;" r module:FrameMerge nd_recvnet_dout_d1 hdl/FrameMerge.v /^ reg nd_recvnet_dout_d1;$/;" r module:FrameMerge nd_recvnet_dout_d2 hdl/FrameMerge.v /^ reg nd_recvnet_dout_d2;$/;" r module:FrameMerge @@ -6098,9 +7242,11 @@ nd_recvnet_dout_d4 hdl/FrameMerge.v /^ reg nd_recvnet_dout_d4;$/;" r module:Fram nd_stop_new hdl/FrameMerge.v /^ reg nd_stop_new = 1'd0;$/;" r module:FrameMerge needs_reset adi_library/axi_dmac/axi_dmac_reset_manager.v /^reg needs_reset = 1'b0;$/;" r module:axi_dmac_reset_manager needs_sync adi_library/axi_dmac/data_mover.v /^reg needs_sync = 1'b0;$/;" r module:dmac_data_mover +net_city hdl/net_city.v /^module net_city ($/;" m next_enable adi_library/util_pack/tb/cpack_tb.v /^ reg [NUM_OF_CHANNELS-1:0] next_enable = 'h1;$/;" r module:cpack_tb next_enable adi_library/util_pack/tb/upack_tb.v /^ reg [NUM_OF_CHANNELS-1:0] next_enable = 'h1;$/;" r module:upack_tb next_state adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ reg [ 1:0] next_state = IDLE;$/;" r module:mdc_mdio +node_id hdl/system_top.v /^ wire [ 7:0] node_id;$/;" n module:system_top noisei hdl/Noise_Estimate.v /^ reg [9:0] noisei = 10'd0;$/;" r module:Noise_Estimate noiseq hdl/Noise_Estimate.v /^ reg [9:0] noiseq = 10'd0;$/;" r module:Noise_Estimate noiseqh hdl/Noise_Estimate.v /^ reg [9:0] noiseqh = 10'd0;$/;" r module:Noise_Estimate @@ -6114,6 +7260,8 @@ num_beats adi_library/axi_dmac/axi_dmac_resize_src.v /^ reg [RATIO_WIDTH-1:0] n nx_completion_req_valid adi_library/axi_dmac/request_generator.v /^reg nx_completion_req_valid;$/;" r module:dmac_request_generator nx_state adi_library/axi_dmac/axi_dmac_response_manager.v /^reg [2:0] nx_state;$/;" r module:axi_dmac_response_manager nx_state adi_library/axi_dmac/request_generator.v /^reg [2:0] nx_state;$/;" r module:dmac_request_generator +oe_MS hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ reg oe_MS = 1'd0;$/;" r module:CCSDS_LDPC_DEC_K1024_R12 +oe_MS hdl/Message_Store.v /^ input [ 0:0] oe_MS, \/\/使能输出信号，高脉冲$/;" p module:Message_Store offload0_cmd_wr_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output [15:0] offload0_cmd_wr_data,$/;" p module:axi_spi_engine offload0_cmd_wr_en adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output offload0_cmd_wr_en,$/;" p module:axi_spi_engine offload0_enable adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output offload0_enable,$/;" p module:axi_spi_engine @@ -6211,44 +7359,49 @@ pending_events adi_library/util_cdc/sync_event.v /^wire [NUM_OF_EVENTS-1:0] pend phase adi_library/xilinx/common/ad_serdes_clk.v /^ output [ 7:0] phase,$/;" p module:ad_serdes_clk phase adi_library/xilinx/common/ad_serdes_in.v /^ input [ 7:0] phase,$/;" p module:ad_serdes_in phase_adjust hdl/RecvTop.v /^ phase_adjust phase_adjust ($/;" i module:RecvTop typeref:module:phase_adjust -phase_adjust hdl/phase_adjust.v /^module phase_adjust($/;" m +phase_adjust hdl/phase_adjust.v /^module phase_adjust ($/;" m phase_adjust_douti hdl/RecvTop.v /^ wire [9:0] phase_adjust_douti;$/;" n module:RecvTop phase_adjust_doutq hdl/RecvTop.v /^ wire [9:0] phase_adjust_doutq;$/;" n module:RecvTop phase_adjust_rdy hdl/RecvTop.v /^ wire phase_adjust_rdy;$/;" n module:RecvTop -phase_estm hdl/phase_adjust.v /^ reg [9:0] phase_estm;$/;" r module:phase_adjust -phase_final hdl/phase_adjust.v /^ reg [9:0] phase_final;$/;" r module:phase_adjust +phase_estm hdl/phase_adjust.v /^ reg [ 9:0] phase_estm;$/;" r module:phase_adjust +phase_final hdl/phase_adjust.v /^ reg [ 9:0] phase_final;$/;" r module:phase_adjust phase_out hdl/freqestm.v /^ wire [ 9:0] phase_out;$/;" n module:freqestm -phase_out hdl/phase_adjust.v /^ wire [9:0] phase_out;$/;" n module:phase_adjust +phase_out hdl/phase_adjust.v /^ wire [ 9:0] phase_out;$/;" n module:phase_adjust phase_out_head hdl/freqestm.v /^ wire [ 5:0] phase_out_head;$/;" n module:freqestm -phase_out_head hdl/phase_adjust.v /^ wire [5:0] phase_out_head;$/;" n module:phase_adjust -phase_pi hdl/phase_adjust.v /^ reg [9:0] phase_pi = 10'b0110010010;$/;" r module:phase_adjust +phase_out_head hdl/phase_adjust.v /^ wire [ 5:0] phase_out_head;$/;" n module:phase_adjust +phase_pi hdl/phase_adjust.v /^ reg [ 9:0] phase_pi = 10'b0110010010;$/;" r module:phase_adjust phase_reg hdl/freqestm.v /^ reg [ 9:0] phase_reg;$/;" r module:freqestm -phase_shengyu hdl/phase_adjust.v /^ reg [9:0] phase_shengyu;$/;" r module:phase_adjust +phase_shengyu hdl/phase_adjust.v /^ reg [ 9:0] phase_shengyu;$/;" r module:phase_adjust phaserdy hdl/freqestm.v /^ wire phaserdy;$/;" n module:freqestm -phaserdy hdl/phase_adjust.v /^ wire phaserdy;$/;" n module:phase_adjust +phaserdy hdl/phase_adjust.v /^ wire phaserdy;$/;" n module:phase_adjust phy_control hdl/phy_control.v /^module phy_control #($/;" m phy_cr_reg hdl/phy_control.v /^ reg [31:0] phy_cr_reg = 32'h0;$/;" r module:phy_control phy_rst hdl/phy_control.v /^ output wire phy_rst,$/;" p module:phy_control phy_rst hdl/system_top.v /^ wire phy_rst;$/;" n module:system_top +phy_rst sim/tb_sys_tx_rx_e_d.v /^ wire phy_rst;$/;" n module:tb_sys_tx_rx_e_d phy_rst_ps hdl/system_top.v /^ wire phy_rst_ps;$/;" n module:system_top +phy_rst_ps sim/tb_sys_tx_rx_e_d.v /^ wire phy_rst_ps;$/;" n module:tb_sys_tx_rx_e_d phy_rst_vio hdl/system_top.v /^ wire phy_rst_vio;$/;" n module:system_top +phy_rst_vio sim/tb_sys_tx_rx_e_d.v /^ wire phy_rst_vio;$/;" n module:tb_sys_tx_rx_e_d phy_sr_reg hdl/phy_control.v /^ reg [31:0] phy_sr_reg = 32'h0;$/;" r module:phy_control phy_tx_test_flag hdl/phy_control.v /^ output wire phy_tx_test_flag$/;" p module:phy_control phy_tx_test_flag hdl/system_top.v /^ wire phy_tx_test_flag;$/;" n module:system_top +phy_tx_test_flag sim/tb_sys_tx_rx_e_d.v /^ wire phy_tx_test_flag;$/;" n module:tb_sys_tx_rx_e_d phy_tx_test_flag_vio hdl/system_top.v /^ wire phy_tx_test_flag_vio;$/;" n module:system_top +phy_tx_test_flag_vio sim/tb_sys_tx_rx_e_d.v /^ wire phy_tx_test_flag_vio;$/;" n module:tb_sys_tx_rx_e_d pilot_datai hdl/Chn_Estimate.v /^ input [9:0] pilot_datai,$/;" p module:Chn_Estimate -pilot_datai hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_datai;$/;" n module:SC_FDE_TOP +pilot_datai hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_datai;$/;" n module:SC_FDE_TOP pilot_datai hdl/data_ow.v /^ output reg [9:0] pilot_datai = 10'd0,$/;" p module:data_ow pilot_dataq hdl/Chn_Estimate.v /^ input [9:0] pilot_dataq,$/;" p module:Chn_Estimate -pilot_dataq hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_dataq;$/;" n module:SC_FDE_TOP +pilot_dataq hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_dataq;$/;" n module:SC_FDE_TOP pilot_dataq hdl/data_ow.v /^ output reg [9:0] pilot_dataq = 10'd0,$/;" p module:data_ow pilot_diffi hdl/data_ow.v /^ reg [10:0] pilot_diffi = 11'd0;$/;" r module:data_ow pilot_diffq hdl/data_ow.v /^ reg [10:0] pilot_diffq = 11'd0;$/;" r module:data_ow pilot_noisei hdl/Noise_Estimate.v /^ input [9:0] pilot_noisei,$/;" p module:Noise_Estimate -pilot_noisei hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_noisei;$/;" n module:SC_FDE_TOP +pilot_noisei hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_noisei;$/;" n module:SC_FDE_TOP pilot_noisei hdl/data_ow.v /^ output reg [9:0] pilot_noisei = 10'd0,$/;" p module:data_ow pilot_noiseq hdl/Noise_Estimate.v /^ input [9:0] pilot_noiseq,$/;" p module:Noise_Estimate -pilot_noiseq hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_noiseq;$/;" n module:SC_FDE_TOP +pilot_noiseq hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_noiseq;$/;" n module:SC_FDE_TOP pilot_noiseq hdl/data_ow.v /^ output reg [9:0] pilot_noiseq = 10'd0$/;" p module:data_ow pilot_sumi hdl/data_ow.v /^ reg [10:0] pilot_sumi = 11'd0;$/;" r module:data_ow pilot_sumq hdl/data_ow.v /^ reg [10:0] pilot_sumq = 11'd0;$/;" r module:data_ow @@ -6275,6 +7428,7 @@ power_measure_done_pulse hdl/ad9361_mgc_pin_ctrl.v /^ wire power_measur power_measure_done_pulse hdl/power_measure.v /^ output reg power_measure_done_pulse$/;" p module:power_measure poweron_locked hdl/system_top.v /^ wire poweron_locked;$/;" n module:system_top poweron_locked sim/TB_sys.v /^ wire poweron_locked;$/;" n module:TB_sys +poweron_locked sim/tb_sys_tx_rx_e_d.v /^ wire poweron_locked;$/;" n module:tb_sys_tx_rx_e_d poweron_locked sim/tb_tx_with_enc.v /^ wire poweron_locked;$/;" n module:tb_tx_with_enc pps_posedge_s adi_library/common/ad_pps_receiver.v /^ wire pps_posedge_s;$/;" n module:ad_pps_receiver pps_rcounter adi_library/common/ad_pps_receiver.v /^ reg [31:0] pps_rcounter = 32'b0;$/;" r module:ad_pps_receiver @@ -6353,21 +7507,25 @@ ram_pilotb hdl/freqestm.v /^ ram_pilot ram_pilotb ($/;" i module:freqestm typ rcnt adi_library/common/ad_axis_inf_rx.v /^ reg [ 2:0] rcnt = 'd0;$/;" r module:ad_axis_inf_rx rd_en hdl/DAGC_v2.v /^ reg rd_en = 1'b0;$/;" r module:DAGC_v2 rd_en hdl/freqestm.v /^ reg rd_en;$/;" r module:freqestm -rd_en_data1 hdl/SC_FDE_TOP.v /^ wire rd_en_data1;$/;" n module:SC_FDE_TOP +rd_en_data1 hdl/SC_FDE_TOP.v /^ wire rd_en_data1;$/;" n module:SC_FDE_TOP rd_en_data1 hdl/data_equalizer.v /^ output reg rd_en_data1 = 1'd0,$/;" p module:data_equalizer -rd_en_data2 hdl/SC_FDE_TOP.v /^ wire rd_en_data2;$/;" n module:SC_FDE_TOP +rd_en_data2 hdl/SC_FDE_TOP.v /^ wire rd_en_data2;$/;" n module:SC_FDE_TOP rd_en_data2 hdl/data_equalizer.v /^ output reg rd_en_data2 = 1'd0,$/;" p module:data_equalizer rd_en_pilot hdl/data_ow.v /^ reg rd_en_pilot = 1'd0;$/;" r module:data_ow rdata adi_library/axi_dmac/tb/axi_read_slave.v /^ output [DATA_WIDTH-1:0] rdata,$/;" p module:axi_read_slave rdata adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [31:0] rdata;$/;" n module:dmac_dma_read_shutdown_tb rdata adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [WIDTH_SRC-1:0] rdata;$/;" n module:dmac_dma_read_tb +rdy hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ wire rdy;$/;" n module:CCSDS_LDPC_DEC_K1024_R12 rdy hdl/IQmerge.v /^ output reg rdy = 1'b0,$/;" p module:IQmerge +rdy hdl/LDPC_DEC_PRO.v /^ output reg rdy = 1'd0, \/\/译码输出信号有效标志，高有效$/;" p module:LDPC_DEC_PRO rdy hdl/TimeSync_top.v /^ output reg rdy = 1'd0,$/;" p module:TimeSync_top -rdy hdl/phase_adjust.v /^ output reg rdy,$/;" p module:phase_adjust +rdy hdl/phase_adjust.v /^ output reg rdy,$/;" p module:phase_adjust rdy_16 hdl/TimeSync_top.v /^ wire rdy_16;$/;" n module:TimeSync_top rdy_4 hdl/TimeSync_top.v /^ wire rdy_4;$/;" n module:TimeSync_top +rdy_MS hdl/Message_Store.v /^ output rdy_MS, \/\/高有效的连续信号$/;" p module:Message_Store +rdy_OUT hdl/LDPC_DEC_PRO.v /^ wire rdy_OUT;$/;" n module:LDPC_DEC_PRO +rdy_OUT hdl/OUT_PRO.v /^ output rdy_OUT,$/;" p module:OUT_PRO rdy_scramble hdl/FrameMerge.v /^ output rdy_scramble,$/;" p module:FrameMerge -rdy_scramble hdl/RecvTop.v /^ wire rdy_scramble;$/;" n module:RecvTop rea adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ input rea,$/;" p module:axi_dacfifo_address_buffer read adi_library/util_axis_fifo/address_sync.v /^wire read = m_axis_ready & m_axis_valid;$/;" n module:fifo_address_sync read_match adi_library/axi_dmac/tb/regmap_tb.v /^ reg read_match = 1'b1;$/;" r module:dmac_regmap_tb @@ -6385,17 +7543,24 @@ ready_counter adi_library/util_fir_int/util_fir_int.v /^ reg [2:0] ready_coun reb adi_library/common/ad_mem.v /^ input reb,$/;" p module:ad_mem reb adi_library/common/ad_mem_asym.v /^ input reb,$/;" p module:ad_mem_asym recvNetData hdl/FrameMerge.v /^ output reg [63:0] recvNetData,$/;" p module:FrameMerge -recvNetData hdl/RecvTop.v /^ output [63:0] recvNetData,$/;" p module:RecvTop +recvNetData hdl/RecvTop.v /^ output [63:0] recvNetData,$/;" p module:RecvTop recvNetDataNd hdl/FrameMerge.v /^ output reg recvNetDataNd$/;" p module:FrameMerge -recvNetDataNd hdl/RecvTop.v /^ output recvNetDataNd,$/;" p module:RecvTop +recvNetDataNd hdl/RecvTop.v /^ output recvNetDataNd$/;" p module:RecvTop recv_addr_new_0 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_0,$/;" p module:FrameMerge recv_addr_new_1 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_1,$/;" p module:FrameMerge recv_addr_new_2 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_2,$/;" p module:FrameMerge recv_addr_new_3 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_3,$/;" p module:FrameMerge +recv_connect_node hdl/net_city.v /^ reg [07:0] recv_connect_node = 8'd0;$/;" r module:net_city recv_data_new_0 hdl/FrameMerge.v /^ output [7:0] recv_data_new_0,$/;" p module:FrameMerge recv_data_new_1 hdl/FrameMerge.v /^ output [7:0] recv_data_new_1,$/;" p module:FrameMerge recv_data_new_2 hdl/FrameMerge.v /^ output [7:0] recv_data_new_2,$/;" p module:FrameMerge recv_data_new_3 hdl/FrameMerge.v /^ output [7:0] recv_data_new_3,$/;" p module:FrameMerge +recv_id hdl/net_city.v /^ output reg [07:0] recv_id = 8'd0,$/;" p module:net_city +recv_net_data hdl/net_city.v /^ input [63:0] recv_net_data,$/;" p module:net_city +recv_net_data_nd hdl/net_city.v /^ input recv_net_data_nd,$/;" p module:net_city +recv_video_id01 hdl/net_city.v /^ reg [07:0] recv_video_id01 = 8'd0;$/;" r module:net_city +recv_video_id02 hdl/net_city.v /^ reg [07:0] recv_video_id02 = 8'd0;$/;" r module:net_city +recv_video_id03 hdl/net_city.v /^ reg [07:0] recv_video_id03 = 8'd0;$/;" r module:net_city ref_clk adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input ref_clk,$/;" p module:axi_xcvrlb ref_clk adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ input ref_clk,$/;" p module:axi_xcvrlb_1 reg_add11 hdl/SCFDE_recv_FrameSync.v /^ wire [19:0] reg_add11;$/;" n module:SCFDE_recv_FrameSync @@ -6673,6 +7838,22 @@ response_valid adi_library/axi_dmac/dest_axi_mm.v /^ output response_valid adi_library/axi_dmac/dest_axi_stream.v /^ output response_valid,$/;" p module:dmac_dest_axi_stream response_valid adi_library/axi_dmac/dest_fifo_inf.v /^ output response_valid,$/;" p module:dmac_dest_fifo_inf response_valid adi_library/axi_dmac/request_arb.v /^ output response_valid,$/;" p module:dmac_request_arb +result_reg0 hdl/VNU_1din.v /^ reg [0:0] result_reg0=1'd0;$/;" r module:VNU_1din +result_reg0 hdl/VNU_2din.v /^ reg [0:0] result_reg0=1'd0;$/;" r module:VNU_2din +result_reg0 hdl/VNU_3din.v /^ reg [0:0] result_reg0=1'd0;$/;" r module:VNU_3din +result_reg0 hdl/VNU_6din.v /^ reg [0:0] result_reg0=1'd0;$/;" r module:VNU_6din +result_reg1 hdl/VNU_1din.v /^ reg [0:0] result_reg1=1'd0; $/;" r module:VNU_1din +result_reg1 hdl/VNU_2din.v /^ reg [0:0] result_reg1=1'd0; $/;" r module:VNU_2din +result_reg1 hdl/VNU_3din.v /^ reg [0:0] result_reg1=1'd0; $/;" r module:VNU_3din +result_reg1 hdl/VNU_6din.v /^ reg [0:0] result_reg1=1'd0;$/;" r module:VNU_6din +result_reg2 hdl/VNU_1din.v /^ reg [0:0] result_reg2=1'd0;$/;" r module:VNU_1din +result_reg2 hdl/VNU_2din.v /^ reg [0:0] result_reg2=1'd0; $/;" r module:VNU_2din +result_reg2 hdl/VNU_3din.v /^ reg [0:0] result_reg2=1'd0;$/;" r module:VNU_3din +result_reg2 hdl/VNU_6din.v /^ reg [0:0] result_reg2=1'd0;$/;" r module:VNU_6din +result_reg3 hdl/VNU_1din.v /^ reg [0:0] result_reg3=1'd0;$/;" r module:VNU_1din +result_reg3 hdl/VNU_2din.v /^ reg [0:0] result_reg3=1'd0; $/;" r module:VNU_2din +result_reg3 hdl/VNU_3din.v /^ reg [0:0] result_reg3=1'd0;$/;" r module:VNU_3din +result_reg4 hdl/VNU_1din.v /^ reg [0:0] result_reg4=1'd0;$/;" r module:VNU_1din result_x adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) output reg [ D_DW-1:0] result_x,$/;" p module:ad_dds_cordic_pipe result_y adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) output reg [ D_DW-1:0] result_y,$/;" p module:ad_dds_cordic_pipe result_z adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) output reg [ P_DW-1:0] result_z,$/;" p module:ad_dds_cordic_pipe @@ -6725,13 +7906,13 @@ room adi_library/util_axis_fifo/address_sync.v /^reg [ADDRESS_WIDTH:0] room = MA rotate adi_library/util_pack/util_pack_common/pack_ctrl.v /^ input [PORT_ADDRESS_WIDTH-1:0] rotate,$/;" p module:pack_ctrl rotate adi_library/util_pack/util_pack_common/pack_network.v /^ input [PORT_ADDRESS_WIDTH-1:0] rotate,$/;" p module:pack_network rotate adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [SAMPLE_ADDRESS_WIDTH-1:0] rotate = 'h00;$/;" r module:pack_shell -rotate_headi hdl/phase_adjust.v /^ wire [5:0] rotate_headi;$/;" n module:phase_adjust -rotate_headq hdl/phase_adjust.v /^ wire [5:0] rotate_headq;$/;" n module:phase_adjust +rotate_headi hdl/phase_adjust.v /^ wire [5:0] rotate_headi;$/;" n module:phase_adjust +rotate_headq hdl/phase_adjust.v /^ wire [5:0] rotate_headq;$/;" n module:phase_adjust rotate_msb adi_library/util_pack/util_pack_common/pack_shell.v /^ reg rotate_msb = 1'b0;$/;" r block:pack_shell.gen_input_buffer -rotate_nd hdl/phase_adjust.v /^ reg rotate_nd;$/;" r module:phase_adjust +rotate_nd hdl/phase_adjust.v /^ reg rotate_nd;$/;" r module:phase_adjust rotate_next adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [SAMPLE_ADDRESS_WIDTH:0] rotate_next;$/;" r block:pack_shell.gen_input_buffer rotate_next_next adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [SAMPLE_ADDRESS_WIDTH:0] rotate_next_next;$/;" n block:pack_shell.gen_input_buffer -rotate_rdy hdl/phase_adjust.v /^ wire rotate_rdy;$/;" n module:phase_adjust +rotate_rdy hdl/phase_adjust.v /^ wire rotate_rdy;$/;" n module:phase_adjust rotation adi_library/common/ad_dds_sine_cordic.v /^ for (i=0; i < PHASE_DW-1; i=i+1) begin: rotation$/;" b module:ad_dds_sine_cordic rready adi_library/axi_dmac/tb/axi_read_slave.v /^ input rready,$/;" p module:axi_read_slave rready adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire rready;$/;" n module:dmac_dma_read_shutdown_tb @@ -6754,21 +7935,23 @@ rst adi_library/xilinx/common/ad_data_clk.v /^ input rst,$/;" p m rst adi_library/xilinx/common/ad_serdes_clk.v /^ input rst,$/;" p module:ad_serdes_clk rst adi_library/xilinx/common/ad_serdes_in.v /^ input rst,$/;" p module:ad_serdes_in rst adi_library/xilinx/common/ad_serdes_out.v /^ input rst,$/;" p module:ad_serdes_out +rst hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ reg rst = 1'd0;$/;" r module:CCSDS_LDPC_DEC_K1024_R12 rst hdl/CCSDS_LDPC_ENC_R12.v /^ input rst,$/;" p module:CCSDS_LDPC_ENC_R12 rst hdl/Chn_Estimate.v /^ input rst,$/;" p module:Chn_Estimate rst hdl/DAGC_v2.v /^ input rst,$/;" p module:DAGC_v2 rst hdl/DDS_compensate.v /^ input rst;$/;" p module:DDS_compensate rst hdl/FrameMerge.v /^ input rst,$/;" p module:FrameMerge rst hdl/IQmerge.v /^ input rst,$/;" p module:IQmerge +rst hdl/LDPC_DEC_PRO.v /^ input rst, \/\/同步复位信号， 高有效$/;" p module:LDPC_DEC_PRO rst hdl/MF_Top.v /^ input rst,$/;" p module:MF_Top rst hdl/MagnitudeEstimator.v /^ input rst,$/;" p module:MagnitudeEstimator rst hdl/Noise_Estimate.v /^ input rst,$/;" p module:Noise_Estimate rst hdl/Out_Process_R12.v /^ input rst,$/;" p module:Out_Process_R12 rst hdl/PAPR.v /^ input rst,$/;" p module:PAPR rst hdl/Receiver.v /^ input rst,$/;" p module:Receiver -rst hdl/RecvTop.v /^ input rst,$/;" p module:RecvTop +rst hdl/RecvTop.v /^ input rst,$/;" p module:RecvTop rst hdl/SCFDE_recv_FrameSync.v /^ input rst,$/;" p module:SCFDE_recv_FrameSync -rst hdl/SC_FDE_TOP.v /^ input rst,$/;" p module:SC_FDE_TOP +rst hdl/SC_FDE_TOP.v /^ input rst,$/;" p module:SC_FDE_TOP rst hdl/TSync_Abs_new16.v /^ input rst,$/;" p module:TSync_Abs_new16 rst hdl/TSync_Abs_new4.v /^ input rst,$/;" p module:TSync_Abs_new4 rst hdl/TimeSync_top.v /^ input rst,$/;" p module:TimeSync_top @@ -6779,34 +7962,51 @@ rst hdl/data_ow.v /^ input rst,$/;" p module:data_ow rst hdl/enc_control.v /^ input rst,$/;" p module:enc_control rst hdl/frame_sync.v /^ input rst,$/;" p module:frame_sync rst hdl/freqestm.v /^ input rst,$/;" p module:freqestm -rst hdl/phase_adjust.v /^ input rst,$/;" p module:phase_adjust +rst hdl/net_city.v /^ wire rst;$/;" n module:net_city +rst hdl/phase_adjust.v /^ input rst,$/;" p module:phase_adjust rst hdl/power_measure.v /^ input rst,$/;" p module:power_measure rst hdl/shift_reg.v /^ (* max_fanout = 256 *) input rst,$/;" p module:shift_reg -rst hdl/tdma.v /^ input rst,$/;" p module:tdma +rst hdl/tdma.v /^ input rst,$/;" p module:tdma rst hdl/width_convert.v /^ input rst,$/;" p module:width_convert rst sim/tb_Receiver.v /^ reg rst;$/;" r module:tb_Receiver rst sim/tb_Transmitter.v /^ reg rst = 1;$/;" r module:tb_Transmitter rst sim/tb_add_prefix.v /^ reg rst = 0;$/;" r module:tb_add_prefix rst sim/tb_enc_control.v /^ reg rst = 1;$/;" r module:tb_enc_control +rst sim/tb_recv_top.v /^ reg rst = 1;$/;" r module:tb_recv_top rst sim/tb_tdma.v /^ reg rst = 1;$/;" r module:tb_tdma rst sim/tb_width_convert.v /^ reg rst = 1;$/;" r module:tb_width_convert rst2 hdl/FrameMerge.v /^ input rst2,$/;" p module:FrameMerge -rst2 hdl/RecvTop.v /^ input rst2,$/;" p module:RecvTop +rst2 hdl/RecvTop.v /^ input rst2, \/\/ TODO： delete the signal$/;" p module:RecvTop rst_1 hdl/SCFDE_recv_FrameSync.v /^ reg rst_1 = 1'b0;$/;" r module:SCFDE_recv_FrameSync rst_1_cnt hdl/SCFDE_recv_FrameSync.v /^ reg [7:0] rst_1_cnt = 8'b0;$/;" r module:SCFDE_recv_FrameSync -rst_TimeSync hdl/RecvTop.v /^ output rst_TimeSync,$/;" p module:RecvTop +rst_CK hdl/LDPC_DEC_PRO.v /^ reg rst_CK = 1'd0;$/;" r module:LDPC_DEC_PRO +rst_CN hdl/CN_PRO.v /^ input rst_CN,$/;" p module:CN_PRO +rst_CN hdl/LDPC_DEC_PRO.v /^ reg rst_CN = 1'd0;$/;" r module:LDPC_DEC_PRO +rst_MS hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ reg rst_MS = 1'd0;$/;" r module:CCSDS_LDPC_DEC_K1024_R12 +rst_MS hdl/Message_Store.v /^ input rst_MS,$/;" p module:Message_Store +rst_OUT hdl/LDPC_DEC_PRO.v /^ reg rst_OUT = 1'd0;$/;" r module:LDPC_DEC_PRO +rst_OUT hdl/OUT_PRO.v /^ input rst_OUT,$/;" p module:OUT_PRO +rst_OUTCK hdl/CK_PRO.v /^ input rst_OUTCK,$/;" p module:CK_PRO +rst_TimeSync hdl/RecvTop.v /^ wire rst_TimeSync;$/;" n module:RecvTop +rst_VN hdl/LDPC_DEC_PRO.v /^ reg rst_VN = 1'd0;$/;" r module:LDPC_DEC_PRO +rst_VN hdl/VN_PRO.v /^ input rst_VN,$/;" p module:VN_PRO rst_async adi_library/common/ad_rst.v /^ input rst_async,$/;" p module:ad_rst rst_async_d1 adi_library/common/ad_rst.v /^ reg rst_async_d1 = 1'd1;$/;" r module:ad_rst rst_async_d2 adi_library/common/ad_rst.v /^ reg rst_async_d2 = 1'd1;$/;" r module:ad_rst rst_dagc hdl/DAGC_v2.v /^ output reg rst_dagc$/;" p module:DAGC_v2 -rst_dagc hdl/RecvTop.v /^ wire rst_dagc;$/;" n module:RecvTop -rst_freq hdl/RecvTop.v /^ output rst_freq,$/;" p module:RecvTop +rst_dagc hdl/RecvTop.v /^ wire rst_dagc;$/;" n module:RecvTop +rst_frame_sync hdl/RecvTop.v /^ wire rst_frame_sync; \/\/ derive from frame sync pulse $/;" n module:RecvTop +rst_freq hdl/RecvTop.v /^ wire rst_freq;$/;" n module:RecvTop rst_freq hdl/freqestm.v /^ output reg rst_freq$/;" p module:freqestm +rst_initial hdl/net_city.v /^ input rst_initial,$/;" p module:net_city +rst_manual hdl/net_city.v /^ input rst_manual, \/\/manual$/;" p module:net_city +rst_manual hdl/system_top.v /^ wire rst_manual;$/;" n module:system_top rst_ready hdl/SCFDE_recv_FrameSync.v /^ input rst_ready,$/;" p module:SCFDE_recv_FrameSync rst_sync adi_library/common/ad_rst.v /^ reg rst_sync = 1'd1;$/;" r module:ad_rst rst_sync_d adi_library/common/ad_rst.v /^ reg rst_sync_d = 1'd1;$/;" r module:ad_rst rst_sys hdl/system_top.v /^ wire rst_sys;$/;" n module:system_top rst_sys sim/TB_sys.v /^ wire rst_sys;$/;" n module:TB_sys +rst_sys sim/tb_sys_tx_rx_e_d.v /^ wire rst_sys;$/;" n module:tb_sys_tx_rx_e_d rst_sys sim/tb_tx_with_enc.v /^ wire rst_sys;$/;" n module:tb_tx_with_enc rstn adi_library/common/ad_rst.v /^ output rstn,$/;" p module:ad_rst rstn adi_library/common/util_pulse_gen.v /^ input rstn,$/;" p module:util_pulse_gen @@ -7019,6 +8219,9 @@ rx_pn_oos_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire rx_ rx_rate_m1 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [ 2:0] rx_rate_m1 = 'd0;$/;" r module:util_adxcvr_xch rx_rate_m2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [ 2:0] rx_rate_m2 = 'd0;$/;" r module:util_adxcvr_xch rx_reset_d1 adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ reg rx_reset_d1;$/;" r module:util_gmii_to_rgmii +rx_rst hdl/net_city.v /^ output reg rx_rst,$/;" p module:net_city +rx_rst hdl/system_top.v /^ wire rx_rst;$/;" n module:system_top +rx_rst hdl/tdma.v /^ (* KEEP = "TRUE" *) output rx_rst$/;" p module:tdma rx_rst_done_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire rx_rst_done_s;$/;" n module:util_adxcvr_xch rx_sof adi_library/common/ad_xcvr_rx_if.v /^ output reg rx_sof,$/;" p module:ad_xcvr_rx_if rx_status_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire rx_status_s;$/;" n module:axi_xcvrlb_1 @@ -7430,11 +8633,27 @@ select_path adi_library/common/ad_bus_mux.v /^ input select_ send_data_ready hdl/Transmitter.v /^ input wire send_data_ready,$/;" p module:Transmitter send_over hdl/Transmitter.v /^ output reg send_over,$/;" p module:Transmitter send_start hdl/Transmitter.v /^ input wire send_start,$/;" p module:Transmitter +send_start sim/tb_sys_tx_rx_e_d.v /^ reg send_start = 0;$/;" r module:tb_sys_tx_rx_e_d serdes_shift1_s adi_library/xilinx/common/ad_serdes_out.v /^ wire [(DATA_WIDTH-1):0] serdes_shift1_s;$/;" n module:ad_serdes_out serdes_shift2_s adi_library/xilinx/common/ad_serdes_out.v /^ wire [(DATA_WIDTH-1):0] serdes_shift2_s;$/;" n module:ad_serdes_out set_reset_reg_value adi_library/axi_dmac/tb/regmap_tb.v /^ task set_reset_reg_value;$/;" t module:dmac_regmap_tb +sgn hdl/CNU_3din.v /^ reg [2:0] sgn=3'd0,sgn_reg0=3'd0;$/;" r module:CNU_3din +sgn hdl/CNU_6din.v /^ reg [5:0] sgn=6'd0,sgn_reg0=6'd0,sgn_reg1=6'd0;$/;" r module:CNU_6din +sgn_reg0 hdl/CNU_3din.v /^ reg [2:0] sgn=3'd0,sgn_reg0=3'd0;$/;" r module:CNU_3din +sgn_reg0 hdl/CNU_6din.v /^ reg [5:0] sgn=6'd0,sgn_reg0=6'd0,sgn_reg1=6'd0;$/;" r module:CNU_6din +sgn_reg1 hdl/CNU_6din.v /^ reg [5:0] sgn=6'd0,sgn_reg0=6'd0,sgn_reg1=6'd0;$/;" r module:CNU_6din sgn_shift_x adi_library/common/ad_dds_cordic_pipe.v /^ wire [ D_DW-1:0] sgn_shift_x;$/;" n module:ad_dds_cordic_pipe sgn_shift_y adi_library/common/ad_dds_cordic_pipe.v /^ wire [ D_DW-1:0] sgn_shift_y;$/;" n module:ad_dds_cordic_pipe +sgn_update hdl/CNU_3din.v /^ reg [2:0] sgn_update=3'd0,sgn_update_reg0=3'd0,sgn_update_reg1=3'd0,sgn_update_reg2=3'd0,sgn/;" r module:CNU_3din +sgn_update hdl/CNU_6din.v /^ reg [5:0] sgn_update=6'd0,sgn_update_reg0=6'd0,sgn_update_reg1=6'd0,sgn_update_reg2=6'd0,sgn/;" r module:CNU_6din +sgn_update_reg0 hdl/CNU_3din.v /^ reg [2:0] sgn_update=3'd0,sgn_update_reg0=3'd0,sgn_update_reg1=3'd0,sgn_update_reg2=3'd0,sgn/;" r module:CNU_3din +sgn_update_reg0 hdl/CNU_6din.v /^ reg [5:0] sgn_update=6'd0,sgn_update_reg0=6'd0,sgn_update_reg1=6'd0,sgn_update_reg2=6'd0,sgn/;" r module:CNU_6din +sgn_update_reg1 hdl/CNU_3din.v /^ reg [2:0] sgn_update=3'd0,sgn_update_reg0=3'd0,sgn_update_reg1=3'd0,sgn_update_reg2=3'd0,sgn/;" r module:CNU_3din +sgn_update_reg1 hdl/CNU_6din.v /^ reg [5:0] sgn_update=6'd0,sgn_update_reg0=6'd0,sgn_update_reg1=6'd0,sgn_update_reg2=6'd0,sgn/;" r module:CNU_6din +sgn_update_reg2 hdl/CNU_3din.v /^ reg [2:0] sgn_update=3'd0,sgn_update_reg0=3'd0,sgn_update_reg1=3'd0,sgn_update_reg2=3'd0,sgn/;" r module:CNU_3din +sgn_update_reg2 hdl/CNU_6din.v /^ reg [5:0] sgn_update=6'd0,sgn_update_reg0=6'd0,sgn_update_reg1=6'd0,sgn_update_reg2=6'd0,sgn/;" r module:CNU_6din +sgn_update_reg3 hdl/CNU_3din.v /^ reg [2:0] sgn_update=3'd0,sgn_update_reg0=3'd0,sgn_update_reg1=3'd0,sgn_update_reg2=3'd0,sgn/;" r module:CNU_3din +sgn_update_reg3 hdl/CNU_6din.v /^ reg [5:0] sgn_update=6'd0,sgn_update_reg0=6'd0,sgn_update_reg1=6'd0,sgn_update_reg2=6'd0,sgn/;" r module:CNU_6din shift_each_reg hdl/shift_reg.v /^ for (shift_reg_cnt = 0; shift_reg_cnt < DEPTH; shift_reg_cnt = shift_reg_cnt + 1) be/;" b module:shift_reg shift_out hdl/add_prefix.v /^ wire [ WIDTH-1:0] shift_out;$/;" n module:add_prefix shift_r adi_library/util_cic/cic_comb.v /^ for (i = L; i <= H; i = i + 1) begin: shift_r$/;" b module:cic_comb @@ -7482,6 +8701,7 @@ source_id adi_library/axi_dmac/src_axi_stream.v /^ output [ID_WIDTH-1:0] source speed_mode hdl/Receiver.v /^ input [ 2:0] speed_mode,$/;" p module:Receiver speed_mode hdl/Transmitter.v /^ input wire [ 2:0] speed_mode,$/;" p module:Transmitter speed_mode hdl/system_top.v /^ wire [ 2:0] speed_mode;$/;" n module:system_top +speed_mode sim/tb_sys_tx_rx_e_d.v /^ wire [ 2:0] speed_mode;$/;" n module:tb_sys_tx_rx_e_d speed_select adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ output reg [ 1:0] speed_select,$/;" p module:mdc_mdio speed_selection adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ wire [ 1:0] speed_selection; \/\/ 1x gigabit, 01 100Mbps, 00 10mbps$/;" n module:util_gmii_to_rgmii spi_active adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg spi_active = 1'b0;$/;" r module:spi_engine_offload @@ -7533,10 +8753,10 @@ splitter adi_library/axi_dmac/splitter.v /^module splitter #($/;" m squ_abs_ZF hdl/Chn_Estimate.v /^wire [29:0] squ_abs_ZF;$/;" n module:Chn_Estimate squ_abs_ZF1 hdl/Chn_Estimate.v /^squ_abs_ZF squ_abs_ZF1 ($/;" i module:Chn_Estimate typeref:module:squ_abs_ZF squ_abs_ZF_nd hdl/Chn_Estimate.v /^reg squ_abs_ZF_nd = 1'd0;$/;" r module:Chn_Estimate -square2i hdl/phase_adjust.v /^ wire [11:0] square2i;$/;" n module:phase_adjust -square2q hdl/phase_adjust.v /^ wire [11:0] square2q;$/;" n module:phase_adjust -squarei hdl/phase_adjust.v /^ wire [10:0] squarei;$/;" n module:phase_adjust -squareq hdl/phase_adjust.v /^ wire [10:0] squareq;$/;" n module:phase_adjust +square2i hdl/phase_adjust.v /^ wire [11:0] square2i;$/;" n module:phase_adjust +square2q hdl/phase_adjust.v /^ wire [11:0] square2q;$/;" n module:phase_adjust +squarei hdl/phase_adjust.v /^ wire [10:0] squarei;$/;" n module:phase_adjust +squareq hdl/phase_adjust.v /^ wire [10:0] squareq;$/;" n module:phase_adjust src_address adi_library/axi_dmac/2d_transfer.v /^reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_address = 'h00;$/;" r module:dmac_2d_transfer src_address_eot adi_library/axi_dmac/request_arb.v /^wire src_address_eot = eot_mem_src[src_address_id];$/;" n module:dmac_request_arb src_address_id adi_library/axi_dmac/axi_dmac.v /^wire [ID_WIDTH-1:0] src_address_id;$/;" n module:axi_dmac @@ -7628,13 +8848,24 @@ src_throttler_enabled adi_library/axi_dmac/request_arb.v /^reg src_throttler_ena src_valid adi_library/axi_dmac/request_arb.v /^wire src_valid;$/;" n module:dmac_request_arb src_valid_bytes adi_library/axi_dmac/request_arb.v /^wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_valid_bytes;$/;" n module:dmac_request_arb src_waddr adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [ADDRESS_WIDTH_SRC-1:0] src_waddr;$/;" n module:axi_dmac_burst_memory +start hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ reg start = 1'd0;$/;" r module:CCSDS_LDPC_DEC_K1024_R12 +start hdl/LDPC_DEC_PRO.v /^ input start, \/\/开始译码标志， 高脉冲$/;" p module:LDPC_DEC_PRO start hdl/MF_Top.v /^ input start,$/;" p module:MF_Top start hdl/ad9361_mgc_pin_ctrl.v /^ input start,$/;" p module:ad9361_mgc_pin_ctrl -start hdl/ad9361_mgc_pin_ctrl.v /^ wire start;$/;" n module:ad9361_mgc_pin_ctrl start hdl/add_prefix.v /^ input start,$/;" p module:add_prefix start hdl/power_measure.v /^ input start,$/;" p module:power_measure start sim/tb_add_prefix.v /^ reg start;$/;" r module:tb_add_prefix +start_CK hdl/LDPC_DEC_PRO.v /^ reg start_CK = 1'd0;$/;" r module:LDPC_DEC_PRO +start_CN hdl/CN_PRO.v /^ input start_CN, \/\/模块启动信号，高脉冲$/;" p module:CN_PRO +start_CN hdl/LDPC_DEC_PRO.v /^ reg start_CN = 1'd0; \/\/模块启动信号，高脉冲$/;" r module:LDPC_DEC_PRO +start_OUT hdl/LDPC_DEC_PRO.v /^ reg start_OUT = 1'd0;$/;" r module:LDPC_DEC_PRO +start_OUT hdl/OUT_PRO.v /^ input start_OUT,$/;" p module:OUT_PRO +start_OUTCK hdl/CK_PRO.v /^ input start_OUTCK,$/;" p module:CK_PRO +start_VN hdl/LDPC_DEC_PRO.v /^ reg start_VN = 1'd0;$/;" r module:LDPC_DEC_PRO +start_VN hdl/VN_PRO.v /^ input start_VN, \/\/ VN更新启动脉冲$/;" p module:VN_PRO start_d1 hdl/ad9361_mgc_pin_ctrl.v /^ reg start_d1;$/;" r module:ad9361_mgc_pin_ctrl +start_frame_VN hdl/LDPC_DEC_PRO.v /^ reg start_frame_VN = 1'd0; \/\/7.23 xhx 在新的一帧数据来临前清零迭/;" r module:LDPC_DEC_PRO +start_frame_VN hdl/VN_PRO.v /^ input start_frame_VN, \/\/ VN更新启动脉冲(新的1帧的开始)$/;" p module:VN_PRO start_posedge hdl/ad9361_mgc_pin_ctrl.v /^ wire start_posedge;$/;" n module:ad9361_mgc_pin_ctrl startup hdl/Receiver.v /^ wire startup;$/;" n module:Receiver startup_4x hdl/Receiver.v /^ wire startup_4x;$/;" n module:Receiver @@ -7646,28 +8877,27 @@ state adi_library/axi_dmac/request_generator.v /^reg [2:0] state = STATE_IDLE;$/ state adi_library/util_cic/cic_comb.v /^reg [DATA_WIDTH-1:0] state = 'h00;$/;" r module:cic_comb state adi_library/util_cic/cic_int.v /^reg [DATA_WIDTH-1:0] state = 'h00;$/;" r module:cic_int state_8 hdl/FrameMerge.v /^ output reg state_8 = 1'd0,$/;" p module:FrameMerge -state_8 hdl/RecvTop.v /^ wire state_8;$/;" n module:RecvTop state_agc hdl/DAGC_v2.v /^ reg [ 3:0] state_agc = 4'd0;$/;" r module:DAGC_v2 -state_fft hdl/SC_FDE_TOP.v /^ reg [1:0] state_fft = 2'd0;$/;" r module:SC_FDE_TOP +state_fft hdl/SC_FDE_TOP.v /^ reg [ 1:0] state_fft = 2'd0;$/;" r module:SC_FDE_TOP state_fftin hdl/data_equalizer.v /^ reg [3:0] state_fftin = 4'd0;$/;" r module:data_equalizer state_fftout hdl/data_equalizer.v /^ reg [1:0] state_fftout = 2'd0;$/;" r module:data_equalizer state_fifo hdl/freqestm.v /^ reg [ 2:0] state_fifo;$/;" r module:freqestm state_flag_overflow1 hdl/Chn_Estimate.v /^reg [1:0] state_flag_overflow1 = 2'd0;$/;" r module:Chn_Estimate state_framesync hdl/SCFDE_recv_FrameSync.v /^ reg [ 3:0] state_framesync;$/;" r module:SCFDE_recv_FrameSync state_freq hdl/freqestm.v /^ reg [ 4:0] state_freq;$/;" r module:freqestm -state_ifft hdl/SC_FDE_TOP.v /^ reg [1:0] state_ifft = 2'd0;$/;" r module:SC_FDE_TOP -state_mgc hdl/RecvTop.v /^ output [ 4:0] state_mgc,$/;" p module:RecvTop +state_ifft hdl/SC_FDE_TOP.v /^ reg [ 1:0] state_ifft = 2'd0;$/;" r module:SC_FDE_TOP +state_mgc hdl/RecvTop.v /^ wire [ 4:0] state_mgc;$/;" n module:RecvTop +state_net hdl/net_city.v /^ reg [07:0] state_net = 8'd0;$/;" r module:net_city state_noise hdl/Noise_Estimate.v /^ reg state_noise = 1'd0;$/;" r module:Noise_Estimate state_ow hdl/data_ow.v /^ reg [4:0] state_ow = 5'd0;$/;" r module:data_ow -state_phase hdl/phase_adjust.v /^ reg [3:0] state_phase;$/;" r module:phase_adjust +state_phase hdl/phase_adjust.v /^ reg [ 3:0] state_phase;$/;" r module:phase_adjust state_pilot hdl/data_ow.v /^ reg [2:0] state_pilot = 3'd0;$/;" r module:data_ow state_pilot_div hdl/Chn_Estimate.v /^reg [4:0] state_pilot_div = 5'd0;$/;" r module:Chn_Estimate state_pilot_fft hdl/Chn_Estimate.v /^reg [4:0] state_pilot_fft = 5'd0;$/;" r module:Chn_Estimate state_pilot_ifft hdl/Chn_Estimate.v /^reg [1:0] state_pilot_ifft = 2'd0;$/;" r module:Chn_Estimate state_ram hdl/FrameMerge.v /^ output reg [1:0] state_ram = 2'd0,$/;" p module:FrameMerge -state_ram hdl/RecvTop.v /^ wire [ 1:0] state_ram;$/;" n module:RecvTop state_recv hdl/FrameMerge.v /^ reg [1:0] state_recv;$/;" r module:FrameMerge -state_rst hdl/RecvTop.v /^ output [ 2:0] state_rst,$/;" p module:RecvTop +state_rst hdl/RecvTop.v /^ wire [ 2:0] state_rst;$/;" n module:RecvTop state_storage hdl/DAGC_v2.v /^ reg [ 2:0] state_storage = 3'd0;$/;" r module:DAGC_v2 state_tsync4 hdl/TSync_Abs_new16.v /^ reg [2:0] state_tsync4 = 3'd0;$/;" r module:TSync_Abs_new16 state_tsync4 hdl/TSync_Abs_new4.v /^ reg [2:0] state_tsync4 = 3'd0;$/;" r module:TSync_Abs_new4 @@ -7675,15 +8905,28 @@ status_sync_data adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v status_sync_ready adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input status_sync_ready,$/;" p module:spi_engine_offload status_sync_valid adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output status_sync_valid,$/;" p module:spi_engine_offload stop_temp_new hdl/FrameMerge.v /^ output reg [63:0] stop_temp_new = 64'd0,$/;" p module:FrameMerge -stop_temp_new hdl/RecvTop.v /^ wire [63:0] stop_temp_new;$/;" n module:RecvTop storage adi_library/util_cic/cic_comb.v /^reg [SEQ-1:0] storage[0:DATA_WIDTH-1];$/;" r module:cic_comb storage_out adi_library/util_cic/cic_comb.v /^wire [DATA_WIDTH-1:0] storage_out;$/;" n module:cic_comb strb adi_library/axi_dmac/axi_dmac_resize_dest.v /^ reg [DATA_WIDTH_MEM\/8-1:0] strb = {DATA_WIDTH_MEM\/8{1'b1}};$/;" r module:axi_dmac_resize_dest sum adi_library/util_cic/cic_int.v /^wire [DATA_WIDTH-1:0] sum;$/;" n module:cic_int -sum256i hdl/phase_adjust.v /^ reg [19:0] sum256i = 20'd0;$/;" r module:phase_adjust -sum256q hdl/phase_adjust.v /^ reg [19:0] sum256q = 20'd0; $/;" r module:phase_adjust +sum hdl/VNU_1din.v /^ reg [8:0] sum=9'd0;$/;" r module:VNU_1din +sum hdl/VNU_2din.v /^ reg [9:0] sum=10'd0;$/;" r module:VNU_2din +sum hdl/VNU_3din.v /^ reg [9:0] sum=10'd0;$/;" r module:VNU_3din +sum hdl/VNU_6din.v /^ reg [10:0] sum=11'd0;$/;" r module:VNU_6din +sum1 hdl/VNU_2din.v /^ reg [9:0] sum1=10'd0;$/;" r module:VNU_2din +sum1 hdl/VNU_3din.v /^ reg [9:0] sum1=10'd0;$/;" r module:VNU_3din +sum1 hdl/VNU_6din.v /^ reg [10:0] sum1=11'd0;$/;" r module:VNU_6din +sum2 hdl/VNU_3din.v /^ reg [9:0] sum2=10'd0;$/;" r module:VNU_3din +sum2 hdl/VNU_6din.v /^ reg [10:0] sum2=11'd0;$/;" r module:VNU_6din +sum256i hdl/phase_adjust.v /^ reg [19:0] sum256i = 20'd0;$/;" r module:phase_adjust +sum256q hdl/phase_adjust.v /^ reg [19:0] sum256q = 20'd0;$/;" r module:phase_adjust +sum3 hdl/VNU_6din.v /^ reg [10:0] sum3=11'd0;$/;" r module:VNU_6din +sum4 hdl/VNU_6din.v /^ reg [10:0] sum4=11'd0;$/;" r module:VNU_6din +sum5 hdl/VNU_6din.v /^ reg [10:0] sum5=11'd0;$/;" r module:VNU_6din +sum_1 hdl/Normalization_Factor_0_8125.v /^ reg [WIDTH-1:0] sum_1 = 8'd0, sum_2 = 8'd0;$/;" r module:Normalization_Factor_0_8125 +sum_2 hdl/Normalization_Factor_0_8125.v /^ reg [WIDTH-1:0] sum_1 = 8'd0, sum_2 = 8'd0;$/;" r module:Normalization_Factor_0_8125 sum_i hdl/frame_sync.v /^ wire [17:0] sum_i [511:0];$/;" n module:frame_sync -sum_rdy hdl/phase_adjust.v /^ reg sum_rdy;$/;" r module:phase_adjust +sum_rdy hdl/phase_adjust.v /^ reg sum_rdy;$/;" r module:phase_adjust sumquarter1 hdl/Interp_half.v /^ reg [14:0] sumquarter1 = 15'd0;$/;" r module:Interp_half sumquarter1 hdl/Interp_quarter.v /^ reg [16:0] sumquarter1 = 17'd0;$/;" r module:Interp_quarter sumquarter2 hdl/Interp_half.v /^ reg [14:0] sumquarter2 = 15'd0;$/;" r module:Interp_half @@ -7727,6 +8970,7 @@ sync_rewind adi_library/axi_dmac/request_arb.v /^sync_event #(.ASYNC_CLK(ASYNC_C sync_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input sync_valid,$/;" p module:axi_spi_engine sync_valid adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg sync_valid,$/;" p module:spi_engine_execution sync_valid adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input sync_valid,$/;" p module:spi_engine_offload +syncout_MS hdl/Message_Store.v /^ output syncout_MS, \/\/高脉冲$/;" p module:Message_Store sys_clk_sel_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire [ 1:0] sys_clk_sel_0;$/;" n module:util_adxcvr sys_clk_sel_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire [ 1:0] sys_clk_sel_12;$/;" n module:util_adxcvr sys_clk_sel_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire [ 1:0] sys_clk_sel_4;$/;" n module:util_adxcvr @@ -7743,6 +8987,8 @@ tb_Transmitter sim/tb_Transmitter.v /^module tb_Transmitter ();$/;" m tb_add_prefix sim/tb_add_prefix.v /^module tb_add_prefix ();$/;" m tb_enc_control sim/tb_enc_control.v /^module tb_enc_control ();$/;" m tb_led sim/tb_led.v /^module tb_led($/;" m +tb_recv_top sim/tb_recv_top.v /^module tb_recv_top ();$/;" m +tb_sys_tx_rx_e_d sim/tb_sys_tx_rx_e_d.v /^module tb_sys_tx_rx_e_d ();$/;" m tb_tdma sim/tb_tdma.v /^module tb_tdma ();$/;" m tb_tx_with_enc sim/tb_tx_with_enc.v /^module tb_tx_with_enc ();$/;" m tb_width_convert sim/tb_width_convert.v /^module tb_width_convert ();$/;" m @@ -7875,6 +9121,10 @@ three_wire adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ tic_hop_m sim/tb_tdma.v /^ wire tic_hop_m;$/;" n module:tb_tdma tic_hop_s sim/tb_tdma.v /^ wire tic_hop_s;$/;" n module:tb_tdma timestamp adi_library/axi_dmac/tb/axi_slave.v /^reg [31:0] timestamp = 'h00;$/;" r module:axi_slave +tl_frames hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ wire [ 8:0] tl_frames;$/;" n module:CCSDS_LDPC_DEC_K1024_R12 +tl_frames hdl/CK_PRO.v /^ output reg [8:0] tl_frames=9'd0 \/\/译码总帧数计数$/;" p module:CK_PRO +tl_frames hdl/LDPC_DEC_PRO.v /^ output reg [8:0] tl_frames = 9'd0, \/\/译码总帧数计数 $/;" p module:LDPC_DEC_PRO +tl_frames_CK hdl/LDPC_DEC_PRO.v /^ wire [8:0] tl_frames_CK;$/;" n module:LDPC_DEC_PRO to_complete_count adi_library/axi_dmac/axi_dmac_response_manager.v /^reg [1:0] to_complete_count = 'h0;$/;" r module:axi_dmac_response_manager tone_1_freq_word adi_library/common/ad_dds.v /^ input [ PHASE_DW-1:0] tone_1_freq_word,$/;" p module:ad_dds tone_1_init_offset adi_library/common/ad_dds.v /^ input [ 15:0] tone_1_init_offset,$/;" p module:ad_dds @@ -7882,10 +9132,23 @@ tone_1_scale adi_library/common/ad_dds.v /^ input [ 15:0] tone_2_freq_word adi_library/common/ad_dds.v /^ input [ PHASE_DW-1:0] tone_2_freq_word,$/;" p module:ad_dds tone_2_init_offset adi_library/common/ad_dds.v /^ input [ 15:0] tone_2_init_offset,$/;" p module:ad_dds tone_2_scale adi_library/common/ad_dds.v /^ input [ 15:0] tone_2_scale,$/;" p module:ad_dds -total_frames hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output [8:0] total_frames \/\/译码总帧数计数 $/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +total_frames hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ output reg [8:0] total_frames = 9'd0 \/\/译码总帧计数$/;" p module:CCSDS_LDPC_DEC_K1024_R12 +total_frames hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output [8:0] total_frames \/\/译码总帧数计数 $/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP total_frames hdl/RecvTop.v /^ wire [8:0] total_frames;$/;" n module:RecvTop -total_frames_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [8:0] total_frames_A; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP -total_frames_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [8:0] total_frames_B; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +total_frames_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [ 8:0] total_frames_A;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +total_frames_A_TM hdl/LDPC_TopManage_2.v /^ input [ 8:0] total_frames_A_TM, \/\/译码总帧数计数 $/;" p module:LDPC_TopManage_2 +total_frames_A_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg [8:0] total_frames_A_TM_reg0, total_frames_A_TM_reg1;$/;" r module:LDPC_TopManage_2 +total_frames_A_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg [8:0] total_frames_A_TM_reg0, total_frames_A_TM_reg1;$/;" r module:LDPC_TopManage_2 +total_frames_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [ 8:0] total_frames_B;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +total_frames_B_TM hdl/LDPC_TopManage_2.v /^ input [ 8:0] total_frames_B_TM, \/\/译码总帧数计数 $/;" p module:LDPC_TopManage_2 +total_frames_B_TM_reg0 hdl/LDPC_TopManage_2.v /^ reg [8:0] total_frames_B_TM_reg0, total_frames_B_TM_reg1;$/;" r module:LDPC_TopManage_2 +total_frames_B_TM_reg1 hdl/LDPC_TopManage_2.v /^ reg [8:0] total_frames_B_TM_reg0, total_frames_B_TM_reg1;$/;" r module:LDPC_TopManage_2 +total_frames_TM hdl/LDPC_TopManage_2.v /^ output [ 8:0] total_frames_TM \/\/译码总帧数计数 $/;" p module:LDPC_TopManage_2 +trans_net_data hdl/net_city.v /^ output reg [63:0] trans_net_data = 64'd0,$/;" p module:net_city +trans_net_data_reg hdl/net_city.v /^ reg [63:0] trans_net_data_reg = 64'd0;$/;" r module:net_city +trans_video_id01 hdl/net_city.v /^ reg [07:0] trans_video_id01;$/;" r module:net_city +trans_video_id02 hdl/net_city.v /^ reg [07:0] trans_video_id02;$/;" r module:net_city +trans_video_id03 hdl/net_city.v /^ reg [07:0] trans_video_id03;$/;" r module:net_city transfer adi_library/axi_dmac/tb/dma_read_tb.v /^ ) transfer ($/;" i module:dmac_dma_read_tb typeref:module:axi_dmac_transfer transfer_abort adi_library/axi_dmac/data_mover.v /^ reg transfer_abort = 1'b0;$/;" r module:dmac_data_mover transfer_abort_s adi_library/axi_dmac/data_mover.v /^wire transfer_abort_s;$/;" n module:dmac_data_mover @@ -8008,19 +9271,25 @@ tx_data_p adi_library/xilinx/common/ad_data_out.v /^ input tx_dat tx_data_q hdl/ad9361_dp_fdd_1r1t.v /^ input [11:0] tx_data_q,$/;" p module:ad9361_dp_fdd_1r1t tx_data_src_count hdl/system_top.v /^ wire [31:0] tx_data_src_count;$/;" n module:system_top tx_data_src_count sim/TB_sys.v /^ wire [31:0] tx_data_src_count;$/;" n module:TB_sys +tx_data_src_count sim/tb_sys_tx_rx_e_d.v /^ reg [31:0] tx_data_src_count;$/;" r module:tb_sys_tx_rx_e_d tx_data_src_count sim/tb_tx_with_enc.v /^ wire [31:0] tx_data_src_count;$/;" n module:tb_tx_with_enc tx_data_src_tdata hdl/Transmitter.v /^ input wire [31:0] tx_data_src_tdata,$/;" p module:Transmitter tx_data_src_tdata hdl/system_top.v /^ wire [31:0] tx_data_src_tdata;$/;" n module:system_top tx_data_src_tdata sim/TB_sys.v /^ wire [15:0] tx_data_src_tdata;$/;" n module:TB_sys +tx_data_src_tdata sim/tb_sys_tx_rx_e_d.v /^ reg [31:0] tx_data_src_tdata;$/;" r module:tb_sys_tx_rx_e_d tx_data_src_tdata sim/tb_tx_with_enc.v /^ wire [31:0] tx_data_src_tdata;$/;" n module:tb_tx_with_enc tx_data_src_tready hdl/Transmitter.v /^ output reg tx_data_src_tready,$/;" p module:Transmitter tx_data_src_tready hdl/system_top.v /^ wire tx_data_src_tready;$/;" n module:system_top tx_data_src_tready sim/TB_sys.v /^ wire tx_data_src_tready;$/;" n module:TB_sys +tx_data_src_tready sim/tb_sys_tx_rx_e_d.v /^ wire tx_data_src_tready;$/;" n module:tb_sys_tx_rx_e_d tx_data_src_tready sim/tb_tx_with_enc.v /^ wire tx_data_src_tready;$/;" n module:tb_tx_with_enc tx_data_src_tvalid hdl/Transmitter.v /^ input wire tx_data_src_tvalid,$/;" p module:Transmitter tx_data_src_tvalid hdl/system_top.v /^ wire tx_data_src_tvalid;$/;" n module:system_top tx_data_src_tvalid sim/TB_sys.v /^ wire tx_data_src_tvalid;$/;" n module:TB_sys +tx_data_src_tvalid sim/tb_sys_tx_rx_e_d.v /^ reg tx_data_src_tvalid;$/;" r module:tb_sys_tx_rx_e_d tx_data_src_tvalid sim/tb_tx_with_enc.v /^ wire tx_data_src_tvalid;$/;" n module:tb_tx_with_enc +tx_done hdl/net_city.v /^ input wire tx_done$/;" p module:net_city +tx_done hdl/system_top.v /^ wire tx_done;$/;" n module:system_top tx_frame hdl/ad9361_dp_fdd_1r1t.v /^ output tx_frame$/;" p module:ad9361_dp_fdd_1r1t tx_n adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output [(NUM_OF_LANES-1):0] tx_n,$/;" p module:axi_xcvrlb tx_n adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ output tx_n,$/;" p module:axi_xcvrlb_1 @@ -8053,11 +9322,16 @@ tx_rate_m2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [ 2:0] tx_reset_d1 adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ reg tx_reset_d1;$/;" r module:util_gmii_to_rgmii tx_reset_sync adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ reg tx_reset_sync;$/;" r module:util_gmii_to_rgmii tx_rst_done_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire tx_rst_done_s;$/;" n module:util_adxcvr_xch -tx_start hdl/tdma.v /^ output tx_start$/;" p module:tdma +tx_start hdl/net_city.v /^ output reg tx_start = 1'b0, \/\/ pulse$/;" p module:net_city +tx_start hdl/tdma.v /^ (* KEEP = "TRUE" *) output tx_start,$/;" p module:tdma tx_start_m sim/tb_tdma.v /^ wire tx_start_m;$/;" n module:tb_tdma tx_start_s sim/tb_tdma.v /^ wire tx_start_s;$/;" n module:tb_tdma +tx_start_vio hdl/system_top.v /^ wire tx_start_vio;$/;" n module:system_top +tx_start_vio_d1 hdl/system_top.v /^ reg tx_start_vio_d1;$/;" r module:system_top +tx_start_vio_pos hdl/system_top.v /^ wire tx_start_vio_pos;$/;" n module:system_top tx_sys_clk_sel_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [ 1:0] tx_sys_clk_sel_s;$/;" n module:util_adxcvr_xch tx_test_flag hdl/system_top.v /^ wire tx_test_flag;$/;" n module:system_top +tx_test_flag sim/tb_sys_tx_rx_e_d.v /^ wire tx_test_flag;$/;" n module:tb_sys_tx_rx_e_d tx_test_flag sim/tb_tx_with_enc.v /^ wire tx_test_flag;$/;" n module:tb_tx_with_enc tx_test_flag_ps sim/tb_tx_with_enc.v /^ wire tx_test_flag_ps;$/;" n module:tb_tx_with_enc type_s adi_library/common/ad_datafmt.v /^ wire type_s;$/;" n module:ad_datafmt @@ -8067,53 +9341,66 @@ u_MM7020_BD_wrapper hdl/system_top.v /^ MM7020_BD_wrapper u_MM7020_BD_wrapper u_MM7020_BD_wrapper sim/TB_sys.v /^ MM7020_BD_wrapper u_MM7020_BD_wrapper ($/;" i module:TB_sys typeref:module:MM7020_BD_wrapper u_MM7020_BD_wrapper sim/tb_tx_with_enc.v /^ MM7020_BD_wrapper u_MM7020_BD_wrapper ($/;" i module:tb_tx_with_enc typeref:module:MM7020_BD_wrapper u_MagnitudeEstimator hdl/Receiver.v /^ ) u_MagnitudeEstimator ($/;" i module:Receiver typeref:module:MagnitudeEstimator +u_MagnitudeEstimator hdl/RecvTop.v /^ ) u_MagnitudeEstimator ($/;" i module:RecvTop typeref:module:MagnitudeEstimator u_PAPR hdl/Receiver.v /^ ) u_PAPR ($/;" i module:Receiver typeref:module:PAPR +u_PAPR hdl/RecvTop.v /^ ) u_PAPR ($/;" i module:RecvTop typeref:module:PAPR u_Receiver sim/tb_Receiver.v /^ Receiver u_Receiver ($/;" i module:tb_Receiver typeref:module:Receiver +u_RecvTop hdl/system_top.v /^ RecvTop u_RecvTop ($/;" i module:system_top typeref:module:RecvTop +u_RecvTop sim/tb_recv_top.v /^ RecvTop u_RecvTop ($/;" i module:tb_recv_top typeref:module:RecvTop +u_RecvTop sim/tb_sys_tx_rx_e_d.v /^ RecvTop u_RecvTop ($/;" i module:tb_sys_tx_rx_e_d typeref:module:RecvTop +u_Transmitter hdl/system_top.v /^ Transmitter u_Transmitter ($/;" i module:system_top typeref:module:Transmitter u_Transmitter sim/tb_Transmitter.v /^ ) u_Transmitter ($/;" i module:tb_Transmitter typeref:module:Transmitter +u_Transmitter sim/tb_sys_tx_rx_e_d.v /^ ) u_Transmitter ($/;" i module:tb_sys_tx_rx_e_d typeref:module:Transmitter u_Transmitter sim/tb_tx_with_enc.v /^ Transmitter u_Transmitter ($/;" i module:tb_tx_with_enc typeref:module:Transmitter u_ad9361_mgc_pin_ctrl hdl/RecvTop.v /^ ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ($/;" i module:RecvTop typeref:module:ad9361_mgc_pin_ctrl -u_ad9361_mgc_pin_ctrl hdl/system_top.v /^ ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ($/;" i module:system_top typeref:module:ad9361_mgc_pin_ctrl u_add_prefix hdl/enc_control.v /^ ) u_add_prefix ($/;" i module:enc_control typeref:module:add_prefix u_add_prefix sim/tb_add_prefix.v /^ ) u_add_prefix ($/;" i module:tb_add_prefix typeref:module:add_prefix u_adder_i hdl/frame_sync.v /^ adder_iq u_adder_i ($/;" i block:frame_sync.adder_gen_block typeref:module:adder_iq +u_bram_agc_header hdl/Transmitter.v /^ bram_agc_header u_bram_agc_header ($/;" i module:Transmitter typeref:module:bram_agc_header u_bram_chu_seq hdl/Transmitter.v /^ bram_chu_seq u_bram_chu_seq ($/;" i module:Transmitter typeref:module:bram_chu_seq u_bram_m_seqs_512 hdl/Transmitter.v /^ bram_m_seqs_512 u_bram_m_seqs_512 ($/;" i module:Transmitter typeref:module:bram_m_seqs_512 u_bram_tx_test hdl/Transmitter.v /^ bram_tx_test u_bram_tx_test ($/;" i module:Transmitter typeref:module:bram_tx_test u_clk_wiz_baseband hdl/system_top.v /^ clk_wiz_baseband u_clk_wiz_baseband ($/;" i module:system_top typeref:module:clk_wiz_baseband u_clk_wiz_baseband sim/TB_sys.v /^ clk_wiz_baseband u_clk_wiz_baseband ($/;" i module:TB_sys typeref:module:clk_wiz_baseband +u_clk_wiz_baseband sim/tb_sys_tx_rx_e_d.v /^ clk_wiz_baseband u_clk_wiz_baseband ($/;" i module:tb_sys_tx_rx_e_d typeref:module:clk_wiz_baseband u_clk_wiz_baseband sim/tb_tx_with_enc.v /^ clk_wiz_baseband u_clk_wiz_baseband ($/;" i module:tb_tx_with_enc typeref:module:clk_wiz_baseband u_clk_wiz_poweron hdl/system_top.v /^ clk_wiz_poweron u_clk_wiz_poweron ($/;" i module:system_top typeref:module:clk_wiz_poweron u_clk_wiz_poweron sim/TB_sys.v /^ clk_wiz_poweron u_clk_wiz_poweron ($/;" i module:TB_sys typeref:module:clk_wiz_poweron +u_clk_wiz_poweron sim/tb_sys_tx_rx_e_d.v /^ clk_wiz_poweron u_clk_wiz_poweron ($/;" i module:tb_sys_tx_rx_e_d typeref:module:clk_wiz_poweron u_clk_wiz_poweron sim/tb_tx_with_enc.v /^ clk_wiz_poweron u_clk_wiz_poweron ($/;" i module:tb_tx_with_enc typeref:module:clk_wiz_poweron +u_enc_control hdl/system_top.v /^ enc_control u_enc_control ($/;" i module:system_top typeref:module:enc_control u_enc_control sim/tb_enc_control.v /^ enc_control u_enc_control ($/;" i module:tb_enc_control typeref:module:enc_control +u_enc_control sim/tb_sys_tx_rx_e_d.v /^ enc_control u_enc_control ($/;" i module:tb_sys_tx_rx_e_d typeref:module:enc_control u_enc_control sim/tb_tx_with_enc.v /^ enc_control u_enc_control ($/;" i module:tb_tx_with_enc typeref:module:enc_control u_fifo_enc_out hdl/enc_control.v /^ fifo_enc_out u_fifo_enc_out ($/;" i module:enc_control typeref:module:fifo_enc_out u_fifo_shift hdl/Receiver.v /^ fifo_shift u_fifo_shift ($/;" i module:Receiver typeref:module:fifo_shift +u_fifo_shift hdl/RecvTop.v /^ fifo_shift u_fifo_shift ($/;" i module:RecvTop typeref:module:fifo_shift u_fifo_width_convert_1_2 hdl/enc_control.v /^ fifo_width_convert_1_2 u_fifo_width_convert_1_2 ($/;" i module:enc_control typeref:module:fifo_width_convert_1_2 u_fir_dmf_interp4_i hdl/Receiver.v /^ fir_dmf_interp4 u_fir_dmf_interp4_i ($/;" i module:Receiver typeref:module:fir_dmf_interp4 +u_fir_dmf_interp4_i hdl/RecvTop.v /^ fir_dmf_interp4 u_fir_dmf_interp4_i ($/;" i module:RecvTop typeref:module:fir_dmf_interp4 u_fir_dmf_interp4_q hdl/Receiver.v /^ fir_dmf_interp4 u_fir_dmf_interp4_q ($/;" i module:Receiver typeref:module:fir_dmf_interp4 +u_fir_dmf_interp4_q hdl/RecvTop.v /^ fir_dmf_interp4 u_fir_dmf_interp4_q ($/;" i module:RecvTop typeref:module:fir_dmf_interp4 u_fir_match_filter_interp4_i hdl/Receiver.v /^ fir_match_interp4 u_fir_match_filter_interp4_i ($/;" i module:Receiver typeref:module:fir_match_interp4 +u_fir_match_filter_interp4_i hdl/RecvTop.v /^ fir_match_interp4 u_fir_match_filter_interp4_i ($/;" i module:RecvTop typeref:module:fir_match_interp4 u_fir_match_filter_interp4_q hdl/Receiver.v /^ fir_match_interp4 u_fir_match_filter_interp4_q ($/;" i module:Receiver typeref:module:fir_match_interp4 +u_fir_match_filter_interp4_q hdl/RecvTop.v /^ fir_match_interp4 u_fir_match_filter_interp4_q ($/;" i module:RecvTop typeref:module:fir_match_interp4 u_fir_shape_interp16_i hdl/Transmitter.v /^ fir_shape_interp16 u_fir_shape_interp16_i ($/;" i module:Transmitter typeref:module:fir_shape_interp16 u_fir_shape_interp16_q hdl/Transmitter.v /^ fir_shape_interp16 u_fir_shape_interp16_q ($/;" i module:Transmitter typeref:module:fir_shape_interp16 u_fir_shape_interp4_i hdl/Transmitter.v /^ fir_shape_interp4 u_fir_shape_interp4_i ($/;" i module:Transmitter typeref:module:fir_shape_interp4 u_fir_shape_interp4_q hdl/Transmitter.v /^ fir_shape_interp4 u_fir_shape_interp4_q ($/;" i module:Transmitter typeref:module:fir_shape_interp4 u_fir_shape_interp8_i hdl/Transmitter.v /^ fir_shape_interp8 u_fir_shape_interp8_i ($/;" i module:Transmitter typeref:module:fir_shape_interp8 u_fir_shape_interp8_q hdl/Transmitter.v /^ fir_shape_interp8 u_fir_shape_interp8_q ($/;" i module:Transmitter typeref:module:fir_shape_interp8 -u_ila_ad9361_mgc hdl/ad9361_mgc_pin_ctrl.v /^ ila_ad9361_mgc u_ila_ad9361_mgc ($/;" i module:ad9361_mgc_pin_ctrl typeref:module:ila_ad9361_mgc -u_ila_ad9361_rx hdl/system_top.v /^ ila_ad9361_rx u_ila_ad9361_rx ($/;" i module:system_top typeref:module:ila_ad9361_rx -u_ila_ad9361_tx hdl/system_top.v /^ ila_ad9361_tx u_ila_ad9361_tx ($/;" i module:system_top typeref:module:ila_ad9361_tx u_ila_frame_sync hdl/PAPR.v /^ ila_frame_sync u_ila_frame_sync ($/;" i module:PAPR typeref:module:ila_frame_sync +u_ila_recv_top hdl/RecvTop.v /^ ila_recv_top u_ila_recv_top ($/;" i module:RecvTop typeref:module:ila_recv_top u_ila_transmitter hdl/Transmitter.v /^ ila_transmitter u_ila_transmitter ($/;" i module:Transmitter typeref:module:ila_transmitter +u_net_city hdl/system_top.v /^ net_city u_net_city ($/;" i module:system_top typeref:module:net_city u_power_measure hdl/ad9361_mgc_pin_ctrl.v /^ power_measure u_power_measure ($/;" i module:ad9361_mgc_pin_ctrl typeref:module:power_measure u_shift256_8 hdl/add_prefix.v /^ shift256_8 u_shift256_8 ($/;" i module:add_prefix typeref:module:shift256_8 u_shift_reg hdl/PAPR.v /^ ) u_shift_reg ($/;" i module:PAPR typeref:module:shift_reg u_tdma sim/tb_tx_with_enc.v /^ ) u_tdma ($/;" i module:tb_tx_with_enc typeref:module:tdma u_tdma_master sim/tb_tdma.v /^ ) u_tdma_master ($/;" i module:tb_tdma typeref:module:tdma u_tdma_slave sim/tb_tdma.v /^ ) u_tdma_slave ($/;" i module:tb_tdma typeref:module:tdma -u_vio_gpio hdl/system_top.v /^ vio_gpio u_vio_gpio ($/;" i module:system_top typeref:module:vio_gpio u_vio_phy_control hdl/system_top.v /^ vio_phy_control u_vio_phy_control ($/;" i module:system_top typeref:module:vio_phy_control -u_vio_tx_speed_mode hdl/system_top.v /^ vio_tx_speed_mode u_vio_tx_speed_mode ($/;" i module:system_top typeref:module:vio_tx_speed_mode u_width_convert hdl/enc_control.v /^ ) u_width_convert ($/;" i module:enc_control typeref:module:width_convert u_width_convert sim/tb_width_convert.v /^ ) u_width_convert ($/;" i module:tb_width_convert typeref:module:width_convert uart_rx hdl/system_top.v /^ input uart_rx,$/;" p module:system_top @@ -10449,7 +11736,6 @@ validnd_new_1d hdl/FrameMerge.v /^ reg validnd_new_1d = 1'b0;$/;" r module:Frame validnd_new_delay hdl/FrameMerge.v /^ wire validnd_new_delay;$/;" n module:FrameMerge validnd_new_delay_d1 hdl/FrameMerge.v /^ reg validnd_new_delay_d1;$/;" r module:FrameMerge validnd_new_new hdl/FrameMerge.v /^ output reg validnd_new_new = 1'b0,$/;" p module:FrameMerge -validnd_new_new hdl/RecvTop.v /^ wire validnd_new_new;$/;" n module:RecvTop value adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] value;$/;" p task:dmac_regmap_tb.set_reset_reg_value value adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] value;$/;" p task:dmac_regmap_tb.write_reg value adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] value;$/;" p task:dmac_regmap_tb.write_reg_and_update @@ -10471,10 +11757,14 @@ vec_mag_d3 hdl/PAPR.v /^ reg [MAG_WIDTH-1:0] vec_mag_d3;$/;" r module:PAPR vec_valid hdl/MagnitudeEstimator.v /^ input vec_valid,$/;" p module:MagnitudeEstimator vec_valid_d1 hdl/MagnitudeEstimator.v /^ reg vec_valid_d1;$/;" r module:MagnitudeEstimator vec_valid_d2 hdl/MagnitudeEstimator.v /^ reg vec_valid_d2;$/;" r module:MagnitudeEstimator +video_id01 hdl/net_city.v /^ input [07:0] video_id01,$/;" p module:net_city +video_id02 hdl/net_city.v /^ input [07:0] video_id02,$/;" p module:net_city +video_id03 hdl/net_city.v /^ input [07:0] video_id03,$/;" p module:net_city vio_powertest_h hdl/DAGC_v2.v /^ input [1:0] vio_powertest_h,$/;" p module:DAGC_v2 vio_powertest_l hdl/DAGC_v2.v /^ input [1:0] vio_powertest_l,$/;" p module:DAGC_v2 vio_stopbit hdl/FrameMerge.v /^ input [6:0] vio_stopbit,$/;" p module:FrameMerge -vio_stopbit hdl/RecvTop.v /^ input [6:0] vio_stopbit, \/\/寻找停止位，默认值为7'd60$/;" p module:RecvTop +vio_stopbit hdl/RecvTop.v /^ input [ 6:0] vio_stopbit, \/\/寻找停止位，默认值为7'd60$/;" p module:RecvTop +vio_tsync_inter16 hdl/RecvTop.v /^ input vio_tsync_inter16, \/\/为1的时候启用内插，从16倍过采样中挑/;" p module:RecvTop vio_tsync_inter16 hdl/TimeSync_top.v /^ input vio_tsync_inter16,\/\/12.5$/;" p module:TimeSync_top vtc_cnt adi_library/xilinx/common/ad_serdes_in.v /^ reg [4:0] vtc_cnt = {5{1'b1}};$/;" r block:ad_serdes_in.g_data w adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam w = PORT_DATA_WIDTH;$/;" c module:pack_interconnect @@ -10502,6 +11792,14 @@ we hdl/shift_reg.v /^ input we,$/;" wea adi_library/common/ad_mem.v /^ input wea,$/;" p module:ad_mem wea adi_library/common/ad_mem_asym.v /^ input wea,$/;" p module:ad_mem_asym wea adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ input wea,$/;" p module:axi_dacfifo_address_buffer +wea1_01 hdl/Message_Store.v /^ reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 /;" r module:Message_Store +wea1_02 hdl/Message_Store.v /^ reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 /;" r module:Message_Store +wea1_03 hdl/Message_Store.v /^ reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 /;" r module:Message_Store +wea1_04 hdl/Message_Store.v /^ reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 /;" r module:Message_Store +wea2_01 hdl/Message_Store.v /^ reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 /;" r module:Message_Store +wea2_02 hdl/Message_Store.v /^ reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 /;" r module:Message_Store +wea2_03 hdl/Message_Store.v /^ reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 /;" r module:Message_Store +wea2_04 hdl/Message_Store.v /^ reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 /;" r module:Message_Store wea_01 hdl/freqestm.v /^ reg wea_01;$/;" r module:freqestm wea_02 hdl/freqestm.v /^ reg wea_02;$/;" r module:freqestm wea_1 hdl/DAGC_v2.v /^ reg wea_1 = 1'd0;$/;" r module:DAGC_v2 @@ -10523,9 +11821,9 @@ word_en adi_library/common/util_dec256sinc24b.v /^ reg word_en = 1'b0;$ word_length adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [7:0] word_length = DATA_WIDTH;$/;" r module:spi_engine_execution wr_en hdl/freqestm.v /^ reg wr_en;$/;" r module:freqestm wr_en_232 hdl/FrameMerge.v /^ reg wr_en_232;$/;" r module:FrameMerge -wr_en_data1 hdl/SC_FDE_TOP.v /^ wire wr_en_data1;$/;" n module:SC_FDE_TOP +wr_en_data1 hdl/SC_FDE_TOP.v /^ wire wr_en_data1;$/;" n module:SC_FDE_TOP wr_en_data1 hdl/data_ow.v /^ output reg wr_en_data1 = 1'd0,$/;" p module:data_ow -wr_en_data2 hdl/SC_FDE_TOP.v /^ wire wr_en_data2;$/;" n module:SC_FDE_TOP +wr_en_data2 hdl/SC_FDE_TOP.v /^ wire wr_en_data2;$/;" n module:SC_FDE_TOP wr_en_data2 hdl/data_ow.v /^ output reg wr_en_data2 = 1'd0,$/;" p module:data_ow wr_en_pilot1 hdl/data_ow.v /^ reg wr_en_pilot1 = 1'd0;$/;" r module:data_ow wr_en_pilot2 hdl/data_ow.v /^ reg wr_en_pilot2 = 1'd0;$/;" r module:data_ow @@ -10534,7 +11832,7 @@ wready adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire wready;$/;" n mo wready adi_library/axi_dmac/tb/dma_write_tb.v /^ wire wready;$/;" n module:dmac_dma_write_tb write adi_library/util_axis_fifo/address_sync.v /^wire write = s_axis_ready & s_axis_valid;$/;" n module:fifo_address_sync write_MMSE_wea hdl/Chn_Estimate.v /^ output reg write_MMSE_wea = 1'd0,$/;" p module:Chn_Estimate -write_MMSE_wea hdl/SC_FDE_TOP.v /^ wire write_MMSE_wea;$/;" n module:SC_FDE_TOP +write_MMSE_wea hdl/SC_FDE_TOP.v /^ wire write_MMSE_wea;$/;" n module:SC_FDE_TOP write_reg adi_library/axi_dmac/tb/regmap_tb.v /^ task write_reg;$/;" t module:dmac_regmap_tb write_reg_and_update adi_library/axi_dmac/tb/regmap_tb.v /^ task write_reg_and_update;$/;" t module:dmac_regmap_tb writevalid hdl/IQmerge.v /^ reg [1:0] writevalid = 2'd0;$/;" r module:IQmerge @@ -10552,10 +11850,16 @@ xfer_req adi_library/axi_dmac/data_mover.v /^ output xfer_req,$/;" p module:dma xfer_req adi_library/axi_dmac/dest_axi_stream.v /^ output xfer_req,$/;" p module:dmac_dest_axi_stream xfer_req adi_library/axi_dmac/dest_fifo_inf.v /^ output xfer_req,$/;" p module:dmac_dest_fifo_inf xfer_req adi_library/axi_dmac/src_fifo_inf.v /^ output xfer_req,$/;" p module:dmac_src_fifo_inf +xor_level_1_01 hdl/CNU_3din.v /^ reg xor_level_1_01=1'd0;$/;" r module:CNU_3din +xor_level_1_01 hdl/CNU_6din.v /^ reg xor_level_1_01=1'd0,xor_level_1_02=1'd0,xor_level_2_01=1'd0;$/;" r module:CNU_6din +xor_level_1_02 hdl/CNU_6din.v /^ reg xor_level_1_01=1'd0,xor_level_1_02=1'd0,xor_level_2_01=1'd0;$/;" r module:CNU_6din +xor_level_2_01 hdl/CNU_6din.v /^ reg xor_level_1_01=1'd0,xor_level_1_02=1'd0,xor_level_2_01=1'd0;$/;" r module:CNU_6din xpm_cdc_frame_sync_pulse_inst hdl/Receiver.v /^ ) xpm_cdc_frame_sync_pulse_inst ($/;" i module:Receiver typeref:module:xpm_cdc_pulse +xpm_cdc_frame_sync_pulse_inst hdl/RecvTop.v /^ ) xpm_cdc_frame_sync_pulse_inst ($/;" i module:RecvTop typeref:module:xpm_cdc_pulse xpm_cdc_single_inst hdl/enc_control.v /^ ) xpm_cdc_single_inst ($/;" i module:enc_control typeref:module:xpm_cdc_single xpm_cdc_single_tx_test_flag_ps_inst hdl/system_top.v /^ ) xpm_cdc_single_tx_test_flag_ps_inst ($/;" i module:system_top typeref:module:xpm_cdc_single xpm_cdc_startup_inst hdl/Receiver.v /^ ) xpm_cdc_startup_inst ($/;" i module:Receiver typeref:module:xpm_cdc_single +xpm_cdc_startup_inst hdl/RecvTop.v /^ ) xpm_cdc_startup_inst ($/;" i module:RecvTop typeref:module:xpm_cdc_single xpm_cdc_sync_rst_inst hdl/Receiver.v /^ ) xpm_cdc_sync_rst_inst ($/;" i module:Receiver typeref:module:xpm_cdc_sync_rst xpm_cdc_sync_rst_phy_rst_inst hdl/system_top.v /^ ) xpm_cdc_sync_rst_phy_rst_inst ($/;" i module:system_top typeref:module:xpm_cdc_sync_rst y0 adi_library/common/ad_dds_sine_cordic.v /^ reg [CORDIC_DW-1:0] y0 = 'd0;$/;" r module:ad_dds_sine_cordic diff --git a/contraint/mm7020_timing.xdc b/contraint/mm7020_timing.xdc index a5bd3d5..892e7bc 100644 --- a/contraint/mm7020_timing.xdc +++ b/contraint/mm7020_timing.xdc @@ -1,4 +1,4 @@ set_property MAX_FANOUT 512 [get_nets *u_RecvTop/mag*] # set_property MAX_FANOUT 512 [get_nets u_Receiver/mag_valid] # set_false_path -through [get_nets u_Receiver/rst] -set_false_path -through [get_nets u_RecvTop/SR[0]] \ No newline at end of file +# set_false_path -through [get_nets u_RecvTop/SR[0]] \ No newline at end of file diff --git a/hdl/PAPR.v b/hdl/PAPR.v index 103767b..a79fe46 100644 --- a/hdl/PAPR.v +++ b/hdl/PAPR.v @@ -27,7 +27,7 @@ module PAPR #( parameter WINDOW_DEPTH = 1023 // parameter GATE = 8 ) ( - input clk, + input clk, input rst, input [MAG_WIDTH-1:0] vec_mag, input mag_valid, @@ -64,11 +64,6 @@ module PAPR #( // accumulate ==> average ==> papr wire [MAG_WIDTH-1:0] vec_mag_1024; reg [ 5:0] cnt; - // shift_1024 shift_1024 ( - // .D (vec_mag), // input wire [21 : 0] D - // .CLK(clk), // input wire CLK - // .Q (vec_mag_1024) // output wire [21 : 0] Q - // ); shift_reg #( .DATA_WIDTH(MAG_WIDTH), @@ -144,22 +139,10 @@ module PAPR #( end - // ******** Wire & Reg ******** - - // ******** Assingment ******** - - // ******** Logic Block ******** - - // ******** Inst ******** - - // ******** Debug ******** - - // NOTE: comment - ila_frame_sync u_ila_frame_sync ( .clk (clk), // input wire clk .probe0(vec_mag), // input wire [21:0] probe0 - .probe1(mag_valid), // input wire [0:0] probe1 + .probe1(data_avg), // input wire [21:0] probe0 .probe2(frame_sync) // input wire [0:0] probe2 ); diff --git a/hdl/RecvTop.v b/hdl/RecvTop.v index f85a607..f6ac6c2 100644 --- a/hdl/RecvTop.v +++ b/hdl/RecvTop.v @@ -20,24 +20,25 @@ ////////////////////////////////////////////////////////////////////////////////// module RecvTop ( input clk, - input clk_2x, // clk_2x + input clk_2x, // clk_2x input clk_4x, input rst, - input rst2, // TODO： delete the signal + input rst2, // TODO： delete the signal // phy wave input [11:0] dini, input [11:0] dinq, // mgc control output [ 3:0] ad9361_ctrl_in, - output wire frame_sync_pulse, // in domain clk + output wire flag_mgc_done_pulse, // active high pulse signal + output wire frame_sync_pulse, // in domain clk //vio - input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路 - input EQUenable_vio, //为1时启用均衡 - input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29 - input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60 + input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路 + input EQUenable_vio, //为1时启用均衡 + input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29 + input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60 // stop signal - output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 - output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 + output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 + output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 // mac frame header output [63:0] recvNetData, output recvNetDataNd @@ -47,7 +48,7 @@ module RecvTop ( wire rst_freq; wire DAGC_rdy; wire framesync; //帧同步峰 - wire framesync_delay; //帧同步峰，与频率补偿输出对应 + wire flag_cfo_done; //帧同步峰，与频率补偿输出对应 wire framesync_tsync; //帧同步标志，与TSync输出对应 wire IntpARdy; //TSync输出nd wire nd_SC_FDE_dout; //SC_FDE输出nd @@ -133,13 +134,14 @@ module RecvTop ( // * MGC module ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ( - .clk (clk), - .rst (rst), - .start (mgc_start), - .rx_data_i (dini), - .rx_data_q (dinq), - .ad9361_ctrl_in(ad9361_ctrl_in), - .flag_mgc_done (flag_mgc_done) + .clk (clk), + .rst (rst), + .start (mgc_start), + .rx_data_i (dini), + .rx_data_q (dinq), + .ad9361_ctrl_in (ad9361_ctrl_in), + .flag_mgc_done_pulse(flag_mgc_done_pulse), + .flag_mgc_done (flag_mgc_done) ); @@ -256,6 +258,7 @@ module RecvTop ( .m_axis_data_tdata (dmf_tdata_interp4_q) ); + wire [7:0] cnt_chu_seq_sync_max_vio; localparam CNT_CHU_SEQ_SYNC_MAX = 40; //! should not less than 3 due to the minimum rst of aresetn wire [21:0] mag; @@ -266,7 +269,7 @@ module RecvTop ( wire rst_frame_sync; // derive from frame sync pulse reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos - assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX)); + assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio)); //* calc the magnitude MagnitudeEstimator #( @@ -298,7 +301,7 @@ module RecvTop ( cnt_chu_seq_sync <= 1; end // avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks) - else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX) begin + else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio) begin cnt_chu_seq_sync <= cnt_chu_seq_sync + 1; end else begin @@ -310,7 +313,7 @@ module RecvTop ( if (rst) begin flag_frame_sync <= 0; end - else if (cnt_chu_seq_sync == CNT_CHU_SEQ_SYNC_MAX) begin + else if (cnt_chu_seq_sync == cnt_chu_seq_sync_max_vio) begin flag_frame_sync <= 1; end else begin @@ -380,7 +383,7 @@ module RecvTop ( .datain_q (DAGC_out_q), .dataout_i (freqdataout_i), .dataout_q (freqdataout_q), - .framesync_delay(framesync_delay), + .framesync_delay(flag_cfo_done), .data_save (data_save), .rst_freq (rst_freq) ); @@ -396,7 +399,7 @@ module RecvTop ( .douti (IntpOuti), .doutq (IntpOutq), .vio_tsync_inter16(vio_tsync_inter16), - .framesync (framesync_delay), //帧同步标志 + .framesync (flag_cfo_done), //帧同步标志 .framesync_tsync (framesync_tsync), //帧同步标志 //debug .cnt_tsync (cnt_tsync), @@ -536,24 +539,35 @@ module RecvTop ( // ***** debug ***** + vio_recv_top u_vio_recv_top ( + .clk (clk), + .probe_out0(cnt_chu_seq_sync_max_vio) + ); + ila_recv_top u_ila_recv_top ( .clk (clk), - .probe0 (flag_mgc_done), // width: 1 - .probe1 (flag_frame_sync), // width: 1 - .probe2 (mf_data_interp4_q), // width: 32 - .probe3 (mf_data_interp4_i), // width: 32 - .probe4 (freqestm.freq_out), // width: 14 - .probe5 (freqdataout_i), // width: 10 - .probe6 (freqdataout_q), // width: 10 - .probe7 (nd_SC_FDE_dout), // width: 1 - .probe8 (SC_FDE_douti), // width: 10 - .probe9 (SC_FDE_doutq), // width: 10 - .probe10(LDPC_SyncOut), // width: 1 - .probe11(LDPC_Rdy), // width: 1 - .probe12(LDPC_Dout), // width: 1 - .probe13(bad_frames), // width: 9 - .probe14(total_frames), // width: 9 - .probe15(mgc_start) // width: 1 + .probe0 (dini), // width: 12 + .probe1 (dinq), // width: 12 + .probe2 (mf_data_interp4_i[29-:12]), // width: 12 + .probe3 (mf_data_interp4_q[29-:12]), // width: 12 + .probe4 (flag_mgc_done), // width: 1 + .probe5 (flag_frame_sync), // width: 1 + .probe6 (flag_cfo_done), // width: 1 + .probe7 (freqdataout_i), // width: 10 + .probe8 (freqdataout_q), // width: 10 + .probe9 (IntpARdy), // width: 1 + .probe10(IntpOuti), // width: 10 + .probe11(IntpOutq), // width: 10 + .probe12(nd_SC_FDE_dout), // width: 1 + .probe13(SC_FDE_douti), // width: 10 + .probe14(SC_FDE_doutq), // width: 10 + .probe15(phase_adjust_rdy), // width: 1 + .probe16(phase_adjust_douti), // width: 10 + .probe17(phase_adjust_doutq), // width: 10 + .probe18(LDPC_Rdy), // width: 1 + .probe19(LDPC_Dout), // width: 1 + .probe20(good_frames), // width: 9 + .probe21(bad_frames) // width: 9 ); diff --git a/hdl/ad9361_mgc_pin_ctrl.v b/hdl/ad9361_mgc_pin_ctrl.v index 2ef9a09..5eee16a 100644 --- a/hdl/ad9361_mgc_pin_ctrl.v +++ b/hdl/ad9361_mgc_pin_ctrl.v @@ -21,7 +21,8 @@ module ad9361_mgc_pin_ctrl ( input [11:0] rx_data_q, // this port is from zynq to ad9361 output wire [ 3:0] ad9361_ctrl_in, - output reg flag_mgc_done = 0 // active high level signal + output wire flag_mgc_done_pulse, // active high pulse signal + output reg flag_mgc_done = 0 // active high level signal ); @@ -54,14 +55,15 @@ module ad9361_mgc_pin_ctrl ( reg [2:0] ns; // ******** Assingment ******** - assign ad9361_ctrl_in[0] = inc_pulse; - assign ad9361_ctrl_in[1] = dec_pulse; + assign ad9361_ctrl_in[0] = inc_pulse; + assign ad9361_ctrl_in[1] = dec_pulse; - assign flag_adjust = flag_too_high | flag_too_low; - assign inc_pulse = (cs == S_INC); - assign dec_pulse = (cs == S_DEC); + assign flag_adjust = flag_too_high | flag_too_low; + assign inc_pulse = (cs == S_INC); + assign dec_pulse = (cs == S_DEC); - assign start_posedge = start & ~start_d1; + assign start_posedge = start & ~start_d1; + assign flag_mgc_done_pulse = power_measure_done_pulse; // ******** Logic Block ******** diff --git a/hdl/net_city.v b/hdl/net_city.v index 84ab267..faed090 100644 --- a/hdl/net_city.v +++ b/hdl/net_city.v @@ -75,7 +75,7 @@ module net_city ( always @(posedge clk) begin if (rst) begin - rx_rst <= 1; + rx_rst <= 0; end else if (tx_start) begin rx_rst <= 1; @@ -211,31 +211,29 @@ module net_city ( end 8'd50: begin - if (recv_net_data_nd) begin - if (recv_net_data[23:00] == 24'h7e5a33) begin - state_net <= 8'd51; - is_net <= 1'b1; + // if (recv_net_data_nd) begin + // if (recv_net_data[23:00] == 24'h7e5a33) begin + state_net <= 8'd51; + is_net <= 1'b1; + cnt_trans_slot <= cnt_trans_slot + 32'd1; + cnt_inter_slot <= cnt_inter_slot + 32'd1; + recv_id <= recv_net_data[63:56]; + recv_video_id01 <= recv_net_data[55:48]; + recv_video_id02 <= recv_net_data[47:40]; + recv_video_id03 <= recv_net_data[39:32]; + recv_connect_node <= recv_net_data[31:24]; + // end + // else begin + // state_net <= 8'd200; + // is_net <= 1'b0; - cnt_trans_slot <= cnt_trans_slot + 32'd1; - cnt_inter_slot <= cnt_inter_slot + 32'd1; - - recv_id <= recv_net_data[63:56]; - recv_video_id01 <= recv_net_data[55:48]; - recv_video_id02 <= recv_net_data[47:40]; - recv_video_id03 <= recv_net_data[39:32]; - recv_connect_node <= recv_net_data[31:24]; - end - else begin - state_net <= 8'd200; - is_net <= 1'b0; - - cnt_trans_slot <= cnt_inter_slot + 32'd1; - end - end - else begin - cnt_trans_slot <= cnt_trans_slot + 32'd1; - cnt_inter_slot <= cnt_inter_slot + 32'd1; - end + // cnt_trans_slot <= cnt_inter_slot + 32'd1; + // end + // end + // else begin + // cnt_trans_slot <= cnt_trans_slot + 32'd1; + // cnt_inter_slot <= cnt_inter_slot + 32'd1; + // end end 8'd51: begin state_net <= 8'd200; diff --git a/hdl/power_measure.v b/hdl/power_measure.v index ebdf975..56f90e4 100644 --- a/hdl/power_measure.v +++ b/hdl/power_measure.v @@ -30,7 +30,7 @@ module power_measure ( ); localparam CNT_WAIT_9361_MAX = 80; //* 等待周期数 - localparam CNT_MEASURING_MAX = 512; // * 观察64个周期 + localparam CNT_MEASURING_MAX = 256; // * 观察64个周期 localparam CNT_ADJUST_TIMES_MAX = 25; localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6; // ******** Wire & Reg ******** diff --git a/hdl/system_top.v b/hdl/system_top.v index d2e86f6..df66262 100644 --- a/hdl/system_top.v +++ b/hdl/system_top.v @@ -89,6 +89,7 @@ module system_top ( wire tx_data_src_tvalid; // tx signal wire tx_test_flag; + wire flag_mgc_done_pulse; // baseband signal wire [11:0] ad9361_rx_data_i; @@ -98,6 +99,13 @@ module system_top ( wire [11:0] ad9361_tx_data_i; wire [11:0] ad9361_tx_data_q; wire [ 2:0] speed_mode; + // mux + wire bb_tx_iq_reverse; + wire bb_rx_iq_reverse; + wire [11:0] bb_tx_i; + wire [11:0] bb_tx_q; + wire [11:0] bb_rx_i; + wire [11:0] bb_rx_q; // phy control signal wire phy_rst_vio; @@ -126,15 +134,20 @@ module system_top ( // ******** Assingment ******** - assign ad9361_tx_clk = clk_1x; - assign rst_sys = ~poweron_locked; + assign ad9361_tx_clk = clk_1x; + assign rst_sys = ~poweron_locked; // ad9361 control - assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control - assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control - assign ad9361_reset_b = gpio_o[2]; // ad9361 reset - assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx + assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control + assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control + assign ad9361_reset_b = gpio_o[2]; // ad9361 reset + assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx + assign ad9361_tx_data_i = bb_tx_iq_reverse ? bb_tx_q : bb_tx_i; + assign ad9361_tx_data_q = bb_tx_iq_reverse ? bb_tx_i : bb_tx_q; + assign bb_rx_i = bb_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i; + assign bb_rx_q = bb_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q; + // ******** Logic Block ******** // ******** Inst ******** @@ -196,7 +209,7 @@ module system_top ( .gpio_t (gpio_t), // intr pl to ps .pl2ps_intr2 (intr_2ps), - .pl2ps_intr3 (pl2ps_intr3), + .pl2ps_intr3 (flag_mgc_done_pulse), // tx fifo .tx_data_src_count (tx_data_src_count), .tx_data_src_tdata (tx_data_src_tdata), @@ -211,44 +224,47 @@ module system_top ( ); - // tdma #( - // .SLOT_LEN (750000), // 50MHz--> 15ms - // .TIC_TO_PS_LEN (700000), - // .TIC_FRAME_SYNC(42344) - // ) u_tdma ( - // .clk (clk_1x), - // .rst (rst_sys), - // .flag_is_master (0), - // .flag_frame_sync(frame_sync_pulse), - // .intr_2ps (intr_2ps), - // .tx_start (tx_start), - // .rx_rst (rx_rst) - // ); - - net_city u_net_city ( - .clk (clk_1x), - .rst_initial (rst_sys), - .rst_manual (rst_manual), - .tx_start (tx_start), - .trans_net_data (), - .flag_video_send (), - .recv_id (), - .frame_sync (frame_sync_pulse), - .recv_net_data_nd(1), - .recv_net_data (0), - .frame_sync_time (42344), - .id_num (node_id), - .max_slot_num (max_slot_num), - .video_id01 (0), - .video_id02 (0), - .video_id03 (0), - .is_net (), - .flag_to_uc (), - .intr_ps (intr_2ps), - .rx_rst (rx_rst), - .tx_done (tx_done) + tdma #( + .SLOT_LEN (750000), // 50MHz--> 15ms + .TIC_TO_PS_LEN (700000), + .TIC_FRAME_SYNC(42344) + // .SLOT_LEN (625001), // 50MHz--> 15ms + // .TIC_TO_PS_LEN (575000), + // .TIC_FRAME_SYNC(42344) + ) u_tdma ( + .clk (clk_1x), + .rst (rst_sys), + .flag_is_master (flag_is_master), + .flag_frame_sync(frame_sync_pulse), + .intr_2ps (intr_2ps), + .tx_start (tx_start), + .rx_rst (rx_rst) ); + // net_city u_net_city ( + // .clk (clk_1x), + // .rst_initial (rst_sys), + // .rst_manual (rst_manual), + // .tx_start (tx_start), + // .trans_net_data (), + // .flag_video_send (), + // .recv_id (), + // .frame_sync (frame_sync_pulse), + // .recv_net_data_nd(1'b1), + // .recv_net_data (64'd0), + // .frame_sync_time (42344), + // .id_num (node_id), + // .max_slot_num (max_slot_num), + // .video_id01 (0), + // .video_id02 (0), + // .video_id03 (0), + // .is_net (), + // .flag_to_uc (), + // .intr_ps (intr_2ps), + // .rx_rst (rx_rst), + // .tx_done (tx_done) + // ); + // ---- PHY layer logic start @@ -278,30 +294,31 @@ module system_top ( .tx_data_src_tready(enc_fifo_rd_en), .tx_data_src_tvalid(~enc_fifo_empty), .hopping_freq (), - .ad9361_tx_data_i (ad9361_tx_data_i), - .ad9361_tx_data_q (ad9361_tx_data_q), + .ad9361_tx_data_i (bb_tx_i), + .ad9361_tx_data_q (bb_tx_q), .test (tx_test_flag | phy_tx_test_flag_vio), .hop_wait (100) ); RecvTop u_RecvTop ( - .clk (clk_1x), - .clk_2x (clk_2x), - .clk_4x (clk_4x), - .rst (rst_sys | rx_rst | phy_rst), - .rst2 (rst_sys | phy_rst), - .dini (ad9361_rx_data_i), - .dinq (ad9361_rx_data_q), - .ad9361_ctrl_in (ad9361_ctrl_in), - .frame_sync_pulse (frame_sync_pulse), - .vio_tsync_inter16(1), - .EQUenable_vio (1), - .Zerozone_vio (8'd29), - .vio_stopbit (7'd60), - .flag_stop (flag_stop), - .addr_stop (addr_stop), - .recvNetData (recvNetData), - .recvNetDataNd (recvNetDataNd) + .clk (clk_1x), + .clk_2x (clk_2x), + .clk_4x (clk_4x), + .rst (rst_sys | rx_rst | phy_rst), + .rst2 (rst_sys | phy_rst), + .dini (bb_rx_i), + .dinq (bb_rx_q), + .ad9361_ctrl_in (ad9361_ctrl_in), + .flag_mgc_done_pulse(flag_mgc_done_pulse), + .frame_sync_pulse (frame_sync_pulse), + .vio_tsync_inter16 (1), + .EQUenable_vio (1), + .Zerozone_vio (8'd29), + .vio_stopbit (7'd60), + .flag_stop (flag_stop), + .addr_stop (addr_stop), + .recvNetData (recvNetData), + .recvNetDataNd (recvNetDataNd) ); @@ -361,7 +378,7 @@ module system_top ( // .clk (ad9361_rx_clk), // .probe0(ad9361_rx_data_i), // .probe1(ad9361_rx_data_q), - // .probe2(u_ad9361_mgc_pin_ctrl.flag_adjust) + // .probe2(u_RecvTop.flag_mgc_done) // ); // ila_ad9361_tx u_ila_ad9361_tx ( @@ -381,13 +398,13 @@ module system_top ( intr_2ps_vio_d1 <= intr_2ps_vio; end + + vio_phy_control u_vio_phy_control ( - .clk (clk_1x), // input wire clk - .probe_out0(rst_manual), // output wire [0 : 0] - .probe_out1(node_id), // output wire [7 : 0] - .probe_out2(max_slot_num), // output wire [7 : 0] - .probe_out3(intr_2ps_vio), // output wire [0 : 0] - .probe_out4(tx_start_vio) // output wire [0 : 0] + .clk (clk_1x), // input wire clk + .probe_out0(flag_is_master), // output wire [0 : 0] + .probe_out1(bb_tx_iq_reverse), // output wire [0 : 0] + .probe_out2(bb_rx_iq_reverse) // output wire [0 : 0] ); diff --git a/hdl/tdma.v b/hdl/tdma.v index d283d72..28d03e5 100644 --- a/hdl/tdma.v +++ b/hdl/tdma.v @@ -14,29 +14,36 @@ // ! PLEASE MAKE SURE THE PARAMETER ARE VALID // ! WHEN U INSTANTIATE THIS MODULE module tdma #( - parameter SLOT_LEN = 1250000, - parameter TIC_TO_PS_LEN = 1200000, - parameter TIC_FRAME_SYNC = 42272 + parameter SLOT_LEN = 750000, + parameter TIC_TO_PS_LEN = 700000, + parameter TIC_FRAME_SYNC = 42344 ) ( - input clk, - input rst, - input flag_is_master, // TODO: refactor it to parameters - input flag_frame_sync, - output intr_2ps, - (* KEEP = "TRUE" *) output tx_start, - (* KEEP = "TRUE" *) output rx_rst + input clk, + input rst, + input flag_is_master, // TODO: refactor it to parameters + input flag_frame_sync, + output intr_2ps, + output tx_start, + output reg rx_rst ); // TODO: 需要检查综合后电路是否会被优化 // BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化 + // ******** Wire & Reg ******** + reg flag_is_tx_slot; + reg [23:0] cnt; + // ******** Assingment ******** + assign tx_start = flag_is_master & (cnt == 16'd10); + assign intr_2ps = flag_is_master & (cnt == TIC_TO_PS_LEN - 1); + // ******** Logic Block ******** - reg [23:0] cnt; + always @(posedge clk) begin if (rst) begin cnt <= 0; @@ -48,7 +55,7 @@ module tdma #( end else begin // master - if (cnt < SLOT_LEN) begin + if (cnt < SLOT_LEN - 1) begin cnt <= cnt + 1; end else begin @@ -57,26 +64,47 @@ module tdma #( end end end - assign tx_start = flag_is_tx_slot & (cnt == 16'd10); - assign rx_rst = flag_is_tx_slot | (~flag_is_tx_slot & (cnt <= 16'd10)); - assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN); + always @(posedge clk) begin - if (rst) begin - flag_is_tx_slot <= 0; + if (flag_is_master) begin + rx_rst <= 1; end - else if (!flag_is_master && flag_frame_sync) begin - flag_is_tx_slot <= 0; - end - else if (cnt == 16'd1) begin - flag_is_tx_slot <= ~flag_is_tx_slot; + else begin + rx_rst <= flag_is_master | (cnt <= 16'd4); end end + // always @(posedge clk) begin + // if (rst) begin + // flag_is_tx_slot <= 0; + // end + // else if (!flag_is_master && flag_frame_sync) begin + // flag_is_tx_slot <= 0; + // end + // else if (cnt == 16'd1) begin + // flag_is_tx_slot <= ~flag_is_tx_slot; + // end + // end + + + // ******** Inst ******** // ******** Debug ******** + + ila_mac_layer u_ila_mac_layer ( + .clk (clk), + .probe0(cnt), // width: 24 + .probe1(tx_start), // width: 1 + .probe2(rx_rst), // width: 1 + .probe3(flag_is_master), // width: 1 + .probe4(intr_2ps), // width: 1 + .probe5(flag_frame_sync) // width: 1 + ); + + endmodule diff --git a/sim/tb_tdma.v b/sim/tb_tdma.v index 53c3eb8..8cafbda 100644 --- a/sim/tb_tdma.v +++ b/sim/tb_tdma.v @@ -22,60 +22,25 @@ module tb_tdma (); - - reg clk = 1; - reg clk_tx = 1; reg rst = 1; always #1 clk <= ~clk; initial begin - #1000 rst <= 1'b0; + #10 rst <= 1'b0; end - wire flag_frame_sync_m; - reg flag_frame_sync_s = 0; - wire intr_2ps_m; - wire intr_2ps_s; - wire tic_hop_m; - wire tic_hop_s; - wire tx_start_m; - wire tx_start_s; - - assign flag_frame_sync_m = 1'b0; - tdma #( - .SLOT_LEN (1250000), - .TIC_TO_PS_LEN (1200000), - .TIC_FRAME_SYNC(42272) - ) u_tdma_master ( + .SLOT_LEN (625000), // 50MHz--> 15ms + .TIC_TO_PS_LEN (575000), + .TIC_FRAME_SYNC(42344) + ) u_tdma ( .clk (clk), .rst (rst), - .flag_is_master (1'b1), - .flag_frame_sync(flag_frame_sync_m), - .intr_2ps (intr_2ps_m), - // .tic_hop (tic_hop_m), - .tx_start (tx_start_m) + .flag_is_master (1), + .flag_frame_sync(0), + .intr_2ps (intr_2ps), + .tx_start (tx_start), + .rx_rst (rx_rst) ); - - tdma #( - .SLOT_LEN (20000), - .TIC_TO_PS_LEN (18000), - .TIC_FRAME_SYNC(2000) - ) u_tdma_slave ( - .clk (clk), - .rst (rst), - .flag_is_master (1'b0), - .flag_frame_sync(flag_frame_sync_s), - .intr_2ps (intr_2ps_s), - // .tic_hop (tic_hop_s), - .tx_start (tx_start_s) - ); - - - initial begin - #12000 flag_frame_sync_s <= 1'b1; - #3 flag_frame_sync_s <= 1'b0; - end - endmodule diff --git a/util.tcl b/util.tcl new file mode 100644 index 0000000..105b389 --- /dev/null +++ b/util.tcl @@ -0,0 +1,38 @@ +# this is a demo create ip using tcl script + +# create a new ip ila named ila_rx2, if the ip already exists, skip create_ip step +create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_tdma +# set the ip property +set_property -dict [list \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_NUM_OF_PROBES {22} \ + CONFIG.C_PROBE0_WIDTH {12} \ + CONFIG.C_PROBE1_WIDTH {12} \ + CONFIG.C_PROBE2_WIDTH {12} \ + CONFIG.C_PROBE3_WIDTH {12} \ + CONFIG.C_PROBE4_WIDTH {1} \ + CONFIG.C_PROBE5_WIDTH {1} \ + CONFIG.C_PROBE6_WIDTH {1} \ + CONFIG.C_PROBE7_WIDTH {10} \ + CONFIG.C_PROBE8_WIDTH {10} \ + CONFIG.C_PROBE9_WIDTH {1} \ + CONFIG.C_PROBE10_WIDTH {10} \ + CONFIG.C_PROBE11_WIDTH {10} \ + CONFIG.C_PROBE12_WIDTH {1} \ + CONFIG.C_PROBE13_WIDTH {10} \ + CONFIG.C_PROBE14_WIDTH {10} \ + CONFIG.C_PROBE15_WIDTH {1} \ + CONFIG.C_PROBE16_WIDTH {10} \ + CONFIG.C_PROBE17_WIDTH {10} \ + CONFIG.C_PROBE18_WIDTH {1} \ + CONFIG.C_PROBE19_WIDTH {1} \ + CONFIG.C_PROBE20_WIDTH {9} \ + CONFIG.C_PROBE21_WIDTH {9} \ + +] [get_ips ila_recv_top] + + +set_property -dict [list \ + CONFIG.C_NUM_OF_PROBES {6} \ + CONFIG.C_PROBE0_WIDTH {24} \ +] [get_ips ila_tdma]