From 26c24ae5b2e122f38252b3197208661dcfc74c5a Mon Sep 17 00:00:00 2001
From: ZoroGH <zoro.ghc@gmail.com>
Date: Fri, 11 Oct 2024 12:11:08 +0800
Subject: [PATCH] bugfix(tdma): fix 3.125 frame sync tic pos(param)

---
 hdl/phy_control.v |  8 +++++++-
 hdl/system_top.v  |  3 +++
 hdl/tdma.v        | 25 +++++++++----------------
 3 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/hdl/phy_control.v b/hdl/phy_control.v
index e722930..a5a8b89 100644
--- a/hdl/phy_control.v
+++ b/hdl/phy_control.v
@@ -74,7 +74,8 @@ module phy_control #(
     output wire [31:0] tdma_tic_2_ps,
     output wire [31:0] tdma_id_cfg,
     output wire        tdma_recv_cur_slot_id_valid,
-    output wire [ 7:0] tdma_recv_cur_slot_id
+    output wire [ 7:0] tdma_recv_cur_slot_id,
+    output wire [31:0] tdma_frame_sync_tic
 
     //--- ADD YOUR OWN PORTS END
 );
@@ -344,6 +345,7 @@ module phy_control #(
     localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
     localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
     localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
+    localparam integer TDMA_FRAME_SYNC_TIC = 'h0000_0018 >> 2;
 
     // Register definitions
     reg [31:0] phy_cr_reg = 32'h0;
@@ -352,6 +354,7 @@ module phy_control #(
     reg [31:0] tdma_tic_2_ps_reg = 32'h0;
     reg [31:0] tdma_id_cfg_reg = 32'h0;  // 2B zero pad, 1B slot num, 1B local id
     reg [31:0] tdma_recv_id_reg = 32'h0;
+    reg [31:0] tdma_frame_sync_tic_reg = 32'h0;
 
     // Register Reading
     always @(posedge local_clk) begin
@@ -378,6 +381,7 @@ module phy_control #(
                     TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
                     TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
                     TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
+                    TDMA_FRAME_SYNC_TIC: tdma_frame_sync_tic_reg <= up_wdata_s;
                 endcase
             end
             else begin
@@ -403,6 +407,8 @@ module phy_control #(
     // received mac frame 
     assign tdma_recv_cur_slot_id       = tdma_recv_id_reg[7:0];
     assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
+    // frame sync tic
+    assign tdma_frame_sync_tic         = tdma_frame_sync_tic_reg;
 
     vio_phy_param u_vio_phy_param (
         .clk      (local_clk),
diff --git a/hdl/system_top.v b/hdl/system_top.v
index 93c3032..cc8e575 100644
--- a/hdl/system_top.v
+++ b/hdl/system_top.v
@@ -127,6 +127,7 @@ module system_top (
     wire [31:0] tdma_id_cfg;
     wire        tdma_recv_cur_slot_id_valid;
     wire [ 7:0] tdma_recv_cur_slot_id;
+    wire [31:0] tdma_frame_sync_tic;
 
 
     // tx signal
@@ -257,6 +258,7 @@ module system_top (
         .tdma_id_cfg                (tdma_id_cfg),
         .tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
         .tdma_recv_cur_slot_id      (tdma_recv_cur_slot_id),
+        .tdma_frame_sync_tic        (tdma_frame_sync_tic),
         // uart 
         .uart_rx                    (uart_rx),
         .uart_tx                    (uart_tx)
@@ -269,6 +271,7 @@ module system_top (
         .tdma_slot_len             (tdma_slot_len[23:0]),
         .tdma_tic_2_ps             (tdma_tic_2_ps[23:0]),
         .tdma_slot_num             (tdma_id_cfg[15:8]),
+        .tdma_frame_sync_tic       (tdma_frame_sync_tic[23:0]),
         .local_id                  (tdma_id_cfg[7:0]),
         .recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
         .recevied_cur_slot_id      (tdma_recv_cur_slot_id),
diff --git a/hdl/tdma.v b/hdl/tdma.v
index a7007b7..ff37b03 100644
--- a/hdl/tdma.v
+++ b/hdl/tdma.v
@@ -13,9 +13,7 @@
 
 // ! PLEASE MAKE SURE THE PARAMETER ARE VALID 
 // ! WHEN U INSTANTIATE THIS MODULE
-module tdma #(
-    parameter TIC_FRAME_SYNC = 44432
-) (
+module tdma (
     input              clk,
     input              rst,
     // PHY parameter
@@ -24,6 +22,7 @@ module tdma #(
     input  wire [23:0] tdma_slot_len,
     input  wire [23:0] tdma_tic_2_ps,
     input  wire [ 7:0] tdma_slot_num,
+    input  wire [23:0] tdma_frame_sync_tic,
     input  wire [ 7:0] local_id,                    // ID number for this device
     // update while received valid     
     input  wire        recevied_cur_slot_id_valid,  // recevied ID number of the frame
@@ -102,15 +101,9 @@ module tdma #(
             cnt_tdma_slot_len <= 0;
         end
         else if (flag_frame_sync) begin
-            cnt_tdma_slot_len <= tdma_tic_frame_sync_vio;
+            cnt_tdma_slot_len <= tdma_frame_sync_tic;
         end
         else begin
-            // if (cnt_tdma_slot_len < tdma_slot_len - 1) begin
-            //     cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
-            // end
-            // else begin
-            //     cnt_tdma_slot_len <= 0;
-            // end
             if (flag_end_of_one_slot) begin
                 cnt_tdma_slot_len <= 0;
             end
@@ -172,12 +165,12 @@ module tdma #(
     // ********    Debug    ********
 
     vio_tdma u_vio_tdma (
-        .clk       (clk),
-        .probe_in0 (tdma_slot_len),
-        .probe_in1 (tdma_tic_2_ps),
-        .probe_in2 (tdma_slot_num),
-        .probe_in3 (local_id),
-        .probe_out0(tdma_tic_frame_sync_vio)
+        .clk      (clk),
+        .probe_in0(tdma_slot_len),
+        .probe_in1(tdma_tic_2_ps),
+        .probe_in2(tdma_slot_num),
+        .probe_in3(local_id),
+        .probe_in4(tdma_frame_sync_tic)
     );
 
     ila_mac_layer u_ila_mac_layer (