From 3bdfbd31dca70a41aadd465403403af28115ee80 Mon Sep 17 00:00:00 2001
From: ZoroGH <zoro.ghc@gmail.com>
Date: Fri, 18 Oct 2024 19:14:09 +0800
Subject: [PATCH] feat(top): adjust rf control logic, ila for 3rd test

---
 contraint/mm7020_timing.xdc |  1 +
 hdl/RecvTop.v               | 21 ++++++++++++---------
 hdl/system_top.v            | 28 ++++++++++++++++++++++++++++
 3 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/contraint/mm7020_timing.xdc b/contraint/mm7020_timing.xdc
index aca3c7d..1553a19 100644
--- a/contraint/mm7020_timing.xdc
+++ b/contraint/mm7020_timing.xdc
@@ -13,6 +13,7 @@ set_false_path -through [get_nets u_tdma/tdma_tic_frame_sync_vio*]
 set_false_path -through [get_nets rx_rst]
 set_false_path -through [get_nets rst_sys]
 set_false_path -through [get_nets rst20]
+set_false_path -through [get_nets u_tdma/rx_rst]
 
 set_false_path -through [get_nets u_RecvTop/flag_mgc_done]
 set_false_path -through [get_nets u_RecvTop/flag_frame_sync]
diff --git a/hdl/RecvTop.v b/hdl/RecvTop.v
index 1c0aa78..a2c188c 100644
--- a/hdl/RecvTop.v
+++ b/hdl/RecvTop.v
@@ -662,15 +662,18 @@ module RecvTop (
     );
 
     ila_recv_top u_ila_recv_top (
-        .clk   (clk_quarter),
-        .probe0(dagc_data_in_i),      // width: 12
-        .probe1(dagc_data_in_q),      // width: 12
-        .probe2(flag_frame_sync),     // width: 1
-        .probe3(phase_adjust_rdy),    // width: 1
-        .probe4(phase_adjust_douti),  // width: 10
-        .probe5(phase_adjust_doutq),  // width: 10
-        .probe6(good_frames),         // width: 9
-        .probe7(bad_frames)           // width: 9
+        .clk    (clk_quarter),
+        .probe0 (dagc_data_in_i),      // width: 12
+        .probe1 (dagc_data_in_q),      // width: 12
+        .probe2 (flag_frame_sync),     // width: 1
+        .probe3 (phase_adjust_rdy),    // width: 1
+        .probe4 (phase_adjust_douti),  // width: 10
+        .probe5 (phase_adjust_doutq),  // width: 10
+        .probe6 (IntpARdy),            // width: 1
+        .probe7 (IntpOuti),            // width: 10
+        .probe8 (IntpOutq),            // width: 10
+        .probe9 (good_frames),         // width: 9
+        .probe10(bad_frames)           // width: 9
     );
 
 
diff --git a/hdl/system_top.v b/hdl/system_top.v
index cc8e575..4fb2885 100644
--- a/hdl/system_top.v
+++ b/hdl/system_top.v
@@ -144,6 +144,12 @@ module system_top (
     // rx
     wire        rx_err_flag_pos;
 
+    wire        rf_io3_d1_12db;
+    wire        rf_io4_d2_6db;
+    wire        rf_io0_d3_18db;
+    wire        rf_io1_d4_12db;
+    wire        rf_io2_trx;  // 1 for tx on, 0 for rx
+
     // vio
     wire        rst_manual;
     wire        rx_rst_vio;
@@ -166,6 +172,19 @@ module system_top (
     assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
     assign bb_rx_i          = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
     assign bb_rx_q          = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
+    // gpio  rf control
+    assign rf_gpio[0]       = rf_io0_d3_18db;
+    assign rf_gpio[1]       = rf_io1_d4_12db;
+    assign rf_gpio[2]       = rf_io2_trx;
+    assign rf_gpio[3]       = rf_io3_d1_12db;
+    assign rf_gpio[4]       = rf_io4_d2_6db;
+    assign rf_gpio[5]       = 0;
+    // at send slot, rx rst is on, and trx is 1 for tx
+    assign rf_io2_trx       = rx_rst;
+    assign rf_io0_d3_18db   = 0;
+    assign rf_io1_d4_12db   = 0;
+    assign rf_io3_d1_12db   = 0;
+    assign rf_io4_d2_6db    = 0;
 
     // ******** Logic Block ********
 
@@ -383,4 +402,13 @@ module system_top (
     //     .probe1(ad9361_tx_data_q)   // input wire [11:0]  probe1
     // );
 
+    // vio_rf u_vio_rf (
+    //     .clk       (clk_poweron),
+    //     .probe_out0(),
+    //     .probe_out1(rf_io3_d1_12db),
+    //     .probe_out2(rf_io4_d2_6db),
+    //     .probe_out3(rf_io0_d3_18db),
+    //     .probe_out4(rf_io1_d4_12db)
+    // );
+
 endmodule