diff --git a/coe/bram_scramble.coe b/coe/bram_scramble.coe new file mode 100644 index 0000000..df08f76 --- /dev/null +++ b/coe/bram_scramble.coe @@ -0,0 +1,11 @@ +memory_initialization_radix=2; +memory_initialization_vector= +01010101111100101000010011111111 +11111010011001101010001100000111 +00101001010100111011101100111101 +01100011110011100110001011010010 +01111101101111010111010001000011 +10010000010101101101011001011000 +00010010111000000110010010011011 +00000101111000110100000001000111 +; \ No newline at end of file diff --git a/hdl/RecvTop.v b/hdl/RecvTop.v index f6ac6c2..086541e 100644 --- a/hdl/RecvTop.v +++ b/hdl/RecvTop.v @@ -20,28 +20,33 @@ ////////////////////////////////////////////////////////////////////////////////// module RecvTop ( input clk, - input clk_2x, // clk_2x + input clk_2x, // clk_2x input clk_4x, input rst, - input rst2, // TODO： delete the signal + input rst2, // TODO： delete the signal // phy wave input [11:0] dini, input [11:0] dinq, // mgc control output [ 3:0] ad9361_ctrl_in, - output wire flag_mgc_done_pulse, // active high pulse signal - output wire frame_sync_pulse, // in domain clk + output wire flag_mgc_done_pulse, // active high pulse signal + output wire frame_sync_pulse, // in domain clk //vio - input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路 - input EQUenable_vio, //为1时启用均衡 - input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29 - input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60 + input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路 + input EQUenable_vio, //为1时启用均衡 + input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29 + input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60 // stop signal - output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 - output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 + output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 + output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 // mac frame header output [63:0] recvNetData, - output recvNetDataNd + output recvNetDataNd, + // rx data src + output wire [31:0] rx_data_src_fifo_tdata, + output wire rx_data_src_fifo_tlast, + input wire rx_data_src_fifo_tready, + output wire rx_data_src_fifo_tvalid ); wire rst_TimeSync; @@ -495,6 +500,17 @@ module RecvTop ( .total_frames(total_frames) ); + extract_mac_frame u_extract_mac_frame ( + .clk (clk_2x), + .rst (rst2 || rst_frame_sync || ~flag_frame_sync), + .ldpc_dec_out_start (LDPC_SyncOut), + .ldpc_dec_out_valid (LDPC_Rdy), + .ldpc_dec_out_data (LDPC_Dout), + .m_axis_mac_frame_tvalid(rx_data_src_fifo_tvalid), + .m_axis_mac_frame_tdata (rx_data_src_fifo_tdata), + .m_axis_mac_frame_tready(rx_data_src_fifo_tready), + .m_axis_mac_frame_tlast (rx_data_src_fifo_tlast) + ); diff --git a/hdl/descrambler.v b/hdl/descrambler.v new file mode 100644 index 0000000..8b4f982 --- /dev/null +++ b/hdl/descrambler.v @@ -0,0 +1,161 @@ +// * Engineer: +// * *************************************************** * +// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ * +// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ * +// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ * +// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ * +// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ * +// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ * +// * *************************************************** * +// * Update Date: +// * NOTE : +module scrambler #( + parameter ILA_ON = 0 +) ( + input clk, + input rst_n, + // s_axis_stream + input [31:0] s_axis_tdata, + input s_axis_tvalid, + output reg s_axis_tready, + input s_axis_tlast, + input [31:0] s_axis_rd_data_count, + // m_axis_stream + output reg [31:0] m_axis_tdata, + output reg m_axis_tvalid, + input m_axis_tready, + output reg m_axis_tlast +); + + + // ******** Wire & Reg ******** + + wire rst; + + reg [ 2:0] addr_scramble = 0; + reg [ 2:0] addr_scramble_d1 = 0; + reg [ 2:0] addr_scramble_d2 = 0; + wire [31:0] data_scramble_mask; + reg [ 3:0] cnt_in; + + reg [31:0] s_axis_tdata_d1; + reg [31:0] s_axis_tdata_d2; + + reg s_axis_tready_d1; + reg s_axis_tlast_d1; + // fsm + reg [ 1:0] cs = 0; + reg [ 1:0] ns = 0; + localparam S_IDLE = 0; + localparam S_WORKING = 1; + + + // ******** Assingment ******** + + assign rst = ~rst_n; + + // ******** Logic Block ******** + + always @(posedge clk) begin + cs <= ns; + end + + always @(*) begin + ns = cs; + case (cs) + S_IDLE: begin + if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 16) begin + ns = S_WORKING; + end + end + S_WORKING: begin + if (addr_scramble_d2 == 3'h7) begin + ns = S_IDLE; + end + end + default: begin + ns = S_IDLE; + end + endcase + end + + always @(posedge clk) begin + if (cs == S_IDLE) begin + addr_scramble <= 0; + end + else begin + addr_scramble <= addr_scramble + 1; + end + addr_scramble_d1 <= addr_scramble; + addr_scramble_d2 <= addr_scramble_d1; + end + + always @(posedge clk) begin + if (cs == S_WORKING) begin + m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask; + end + else begin + m_axis_tdata <= 0; + end + end + + always @(posedge clk) begin + if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin + s_axis_tready <= 1; + end + else begin + s_axis_tready <= 0; + end + end + + + always @(posedge clk) begin + s_axis_tdata_d1 <= s_axis_tdata; + + s_axis_tready_d1 <= s_axis_tready; + m_axis_tvalid <= s_axis_tready_d1; + + s_axis_tlast_d1 <= s_axis_tlast; + m_axis_tlast <= s_axis_tlast_d1; + + end + + always @(posedge clk) begin + if (cs == S_IDLE) begin + cnt_in <= 0; + end + else if (cs == S_WORKING && cnt_in < 4'd8) begin + cnt_in <= cnt_in + 1; + end + end + + + // ******** Inst ******** + + bram_scramble u_bram_scramble ( + .clka (clk), // input wire clka + .addra(addr_scramble), // input wire [2 : 0] addra + .douta(data_scramble_mask) // output wire [31 : 0] douta + ); + + // ******** Debug ******** + + generate + if (ILA_ON) + ila_scrambler u_ila_scrambler ( + .clk (clk), // input wire clk + .probe0(s_axis_tvalid), // input wire [0:0] probe0 + .probe1(s_axis_tready), // input wire [0:0] probe1 + .probe2(s_axis_tdata), // input wire [31:0] probe2 + .probe3(s_axis_tlast), // input wire [0:0] probe3 + .probe4(m_axis_tvalid), // input wire [0:0] probe4 + .probe5(m_axis_tready), // input wire [0:0] probe5 + .probe6(m_axis_tdata), // input wire [31:0] probe6 + .probe7(m_axis_tlast), // input wire [0:0] probe7 + .probe8(data_scramble_mask) // input wire [31:0] probe8 + ); + + endgenerate + + +endmodule diff --git a/hdl/enc_control.v b/hdl/enc_control.v index 7abcc9e..6c0f598 100644 --- a/hdl/enc_control.v +++ b/hdl/enc_control.v @@ -338,4 +338,18 @@ module enc_control #( // ******** Debug ******** + // ila_enc_control u_ila_enc_control ( + // .clk (clk), + // .probe0(s_axis_fifo_tvalid), // width: 1 + // .probe1(s_axis_fifo_tready), // width: 1 + // .probe2(s_axis_fifo_tdata), // width: 32 + // .probe3(data_src_count), // width: 32 + // .probe4(cs), // width: 4 + // .probe5(wc_data_in_ready), // width: 1 + // .probe6(wc_data_in_valid), // width: 1 + // .probe7(wc_data_out_valid), // width: 1 + // .probe8(data_add_prefix_in_ready), // width: 1 + // .probe9(data_add_prefix_out_valid) // width: 1 + // ); + endmodule diff --git a/hdl/extract_mac_frame.v b/hdl/extract_mac_frame.v new file mode 100644 index 0000000..1d87f18 --- /dev/null +++ b/hdl/extract_mac_frame.v @@ -0,0 +1,82 @@ +module extract_mac_frame ( + input clk, + input rst, + // ldpc out + input ldpc_dec_out_start, + input ldpc_dec_out_valid, + input ldpc_dec_out_data, + // axis + output wire m_axis_mac_frame_tvalid, + output wire [31:0] m_axis_mac_frame_tdata, + input m_axis_mac_frame_tready, + output reg m_axis_mac_frame_tlast + +); + // NOTE: module 1bit --> 32bit + // transfer 1bit serial to 32bit and sent to axis fifo + // + + localparam MAC_FRAME_LEN_BIT = 107520; + localparam MAC_FRAME_LEN_BYTE = 13440; + localparam MAC_FRAME_LEN_QUAD_BYTE = 3360; + + + // ******** Wire & Reg ******** + + reg [15:0] cnt_axis_out; + wire flag_handshake; + // serial input + wire ser; + wire ser_valid; + wire [31:0] par; + wire par_valid; + + + // ******** Assingment ******** + + assign ser = ldpc_dec_out_data; + assign ser_valid = ldpc_dec_out_valid; + assign m_axis_mac_frame_tvalid = par_valid; + assign m_axis_mac_frame_tdata = par; + + assign flag_handshake = m_axis_mac_frame_tvalid & m_axis_mac_frame_tready; + + // ******** Logic Block ******** + + always @(posedge clk) begin + if (rst) begin + cnt_axis_out <= 0; + end + else if (flag_handshake) begin + cnt_axis_out <= cnt_axis_out + 1; + end + end + + always @(*) begin + if (cnt_axis_out == MAC_FRAME_LEN_QUAD_BYTE - 1 && flag_handshake) begin + m_axis_mac_frame_tlast = 1; + end + else begin + m_axis_mac_frame_tlast = 0; + end + end + + // ******** Inst ******** + + // serial 1bit --> 32bit + ser2par u_ser2par ( + .clk (clk), + .rst (rst), + .ser (ser), + .ser_valid(ser_valid), + .par (par), + .par_valid(par_valid) + ); + + + + // ******** Debug ******** + + + +endmodule diff --git a/hdl/phy_control.v b/hdl/phy_control.v index 70620b1..4172ab4 100644 --- a/hdl/phy_control.v +++ b/hdl/phy_control.v @@ -389,6 +389,11 @@ module phy_control #( assign tdma_tic_2_ps = tdma_tic_2_ps_reg; + vio_phy_param u_vio_phy_param ( + .clk (local_clk), + .probe_in0(phy_cr_reg) + ); + //--- ADD YOUR OWN LOGIC END diff --git a/hdl/scrambler.v b/hdl/scrambler.v new file mode 100644 index 0000000..84adfaf --- /dev/null +++ b/hdl/scrambler.v @@ -0,0 +1,161 @@ +// * Engineer: +// * *************************************************** * +// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ * +// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ * +// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ * +// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ * +// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ * +// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ * +// * *************************************************** * +// * Update Date: +// * NOTE : +module scrambler #( + parameter ILA_ON = 0 +) ( + input clk, + input rst_n, + // s_axis_stream + input [31:0] s_axis_tdata, + input s_axis_tvalid, + output reg s_axis_tready, + input s_axis_tlast, + input [31:0] s_axis_rd_data_count, + // m_axis_stream + output reg [31:0] m_axis_tdata, + output reg m_axis_tvalid, + input m_axis_tready, + output reg m_axis_tlast +); + + + // ******** Wire & Reg ******** + + wire rst; + + reg [ 2:0] addr_scramble = 0; + reg [ 2:0] addr_scramble_d1 = 0; + reg [ 2:0] addr_scramble_d2 = 0; + wire [31:0] data_scramble_mask; + reg [ 3:0] cnt_in; + + reg [31:0] s_axis_tdata_d1; + reg [31:0] s_axis_tdata_d2; + + reg s_axis_tready_d1; + reg s_axis_tlast_d1; + // fsm + reg [ 1:0] cs = 0; + reg [ 1:0] ns = 0; + localparam S_IDLE = 0; + localparam S_WORKING = 1; + + + // ******** Assingment ******** + + assign rst = ~rst_n; + + // ******** Logic Block ******** + + always @(posedge clk) begin + cs <= ns; + end + + always @(*) begin + ns = cs; + case (cs) + S_IDLE: begin + if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 8) begin + ns = S_WORKING; + end + end + S_WORKING: begin + if (addr_scramble_d2 == 3'h7) begin + ns = S_IDLE; + end + end + default: begin + ns = S_IDLE; + end + endcase + end + + always @(posedge clk) begin + if (cs == S_IDLE) begin + addr_scramble <= 0; + end + else begin + addr_scramble <= addr_scramble + 1; + end + addr_scramble_d1 <= addr_scramble; + addr_scramble_d2 <= addr_scramble_d1; + end + + always @(posedge clk) begin + if (cs == S_WORKING) begin + m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask; + end + else begin + m_axis_tdata <= 0; + end + end + + always @(posedge clk) begin + if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin + s_axis_tready <= 1; + end + else begin + s_axis_tready <= 0; + end + end + + + always @(posedge clk) begin + s_axis_tdata_d1 <= s_axis_tdata; + + s_axis_tready_d1 <= s_axis_tready; + m_axis_tvalid <= s_axis_tready_d1; + + s_axis_tlast_d1 <= s_axis_tlast; + m_axis_tlast <= s_axis_tlast_d1; + + end + + always @(posedge clk) begin + if (cs == S_IDLE) begin + cnt_in <= 0; + end + else if (cs == S_WORKING && cnt_in < 4'd8) begin + cnt_in <= cnt_in + 1; + end + end + + + // ******** Inst ******** + + bram_scramble u_bram_scramble ( + .clka (clk), // input wire clka + .addra(addr_scramble), // input wire [2 : 0] addra + .douta(data_scramble_mask) // output wire [31 : 0] douta + ); + + // ******** Debug ******** + + generate + if (ILA_ON) + ila_scrambler u_ila_scrambler ( + .clk (clk), // input wire clk + .probe0(s_axis_tvalid), // input wire [0:0] probe0 + .probe1(s_axis_tready), // input wire [0:0] probe1 + .probe2(s_axis_tdata), // input wire [31:0] probe2 + .probe3(s_axis_tlast), // input wire [0:0] probe3 + .probe4(m_axis_tvalid), // input wire [0:0] probe4 + .probe5(m_axis_tready), // input wire [0:0] probe5 + .probe6(m_axis_tdata), // input wire [31:0] probe6 + .probe7(m_axis_tlast), // input wire [0:0] probe7 + .probe8(data_scramble_mask) // input wire [31:0] probe8 + ); + + endgenerate + + +endmodule diff --git a/hdl/ser2par.v b/hdl/ser2par.v new file mode 100644 index 0000000..b795241 --- /dev/null +++ b/hdl/ser2par.v @@ -0,0 +1,61 @@ +module ser2par #( + parameter PAR_WIDTH = 32 +) ( + input clk, + input rst, + input wire ser, + input wire ser_valid, + output reg [PAR_WIDTH -1:0] par, + output reg par_valid +); + + // ******** Wire & Reg ******** + reg [$clog2(PAR_WIDTH):0] cnt_idx; + + // ******** Assingment ******** + + // ******** Logic Block ******** + + always @(posedge clk) begin + if (rst) begin + cnt_idx <= 0; + end + else if (ser_valid) begin + if (cnt_idx == PAR_WIDTH - 1) begin // force it return to 0 + cnt_idx <= 0; + end + else begin + cnt_idx <= cnt_idx + 1; + end + end + end + + always @(posedge clk) begin + if (rst) begin + par <= 0; + end + else if (ser_valid) begin + par[cnt_idx] <= ser; + end + end + + always @(posedge clk) begin + if (cnt_idx == PAR_WIDTH - 1) begin + par_valid <= 1; + end + else begin + par_valid <= 0; + end + end + + + // ******** Inst ******** + + // ******** Debug ******** + + + + + + +endmodule diff --git a/hdl/system_top.v b/hdl/system_top.v index 8e46440..7a89649 100644 --- a/hdl/system_top.v +++ b/hdl/system_top.v @@ -90,6 +90,11 @@ module system_top ( // tx signal wire tx_test_flag; wire flag_mgc_done_pulse; + // rx bus + wire [31:0] rx_data_src_fifo_tdata; + wire rx_data_src_fifo_tlast; + wire rx_data_src_fifo_tready; + wire rx_data_src_fifo_tvalid; // baseband signal wire [11:0] ad9361_rx_data_i; @@ -132,6 +137,7 @@ module system_top ( // vio wire rst_manual; + wire rx_rst_vio; wire [ 7:0] node_id; wire intr_2ps; wire [ 7:0] max_slot_num; @@ -178,71 +184,78 @@ module system_top ( ); MM7020_BD_wrapper u_MM7020_BD_wrapper ( - .ad9361_spi_clk (ad9361_spi_clk), - .ad9361_spi_csn (ad9361_spi_csn), - .ad9361_spi_miso (ad9361_spi_miso), - .ad9361_spi_mosi (ad9361_spi_mosi), - .clk_ps (clk_poweron), - .rst_ps (rst_sys), + .ad9361_spi_clk (ad9361_spi_clk), + .ad9361_spi_csn (ad9361_spi_csn), + .ad9361_spi_miso (ad9361_spi_miso), + .ad9361_spi_mosi (ad9361_spi_mosi), + .clk_ps (clk_poweron), + .rst_ps (rst_sys), // ddr - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), // fixed io - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), // gpio ps - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), // intr pl to ps - .pl2ps_intr2 (intr_2ps), - .pl2ps_intr3 (flag_mgc_done_pulse), + .pl_tx_intr (intr_2ps | intr_2ps_vio_pos), + .pl_rx_intr (rx_data_src_fifo_tlast), // tx fifo - .tx_data_src_count (tx_data_src_count), - .tx_data_src_tdata (tx_data_src_tdata), - .tx_data_src_tready (tx_data_src_tready), - .tx_data_src_tvalid (tx_data_src_tvalid), - //phy control signal - .phy_rst (phy_rst), - .phy_tx_test_flag (phy_tx_test_flag), - .phy_tx_iq_reverse (phy_tx_iq_reverse), - .phy_rx_iq_reverse (phy_rx_iq_reverse), - .tdma_flag_is_master(tdma_flag_is_master), - .tdma_slot_len (tdma_slot_len), - .tdma_tic_2_ps (tdma_tic_2_ps), + .tx_data_src_count (tx_data_src_count), + .tx_data_src_tdata (tx_data_src_tdata), + .tx_data_src_tready (tx_data_src_tready), + .tx_data_src_tvalid (tx_data_src_tvalid), + // rx fifo + .clk_rx_data_src_fifo (clk_2x), + .rst_rx_data_src_fifo (rx_rst), + .rx_data_src_fifo_tdata (rx_data_src_fifo_tdata), + .rx_data_src_fifo_tlast (rx_data_src_fifo_tlast), + .rx_data_src_fifo_tready(rx_data_src_fifo_tready), + .rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid), + // phy control signal + .phy_rst (phy_rst), + .phy_tx_test_flag (phy_tx_test_flag), + .phy_tx_iq_reverse (phy_tx_iq_reverse), + .phy_rx_iq_reverse (phy_rx_iq_reverse), + .tdma_flag_is_master (tdma_flag_is_master), + .tdma_slot_len (tdma_slot_len), + .tdma_tic_2_ps (tdma_tic_2_ps), // uart - .uart_rx (uart_rx), - .uart_tx (uart_tx) + .uart_rx (uart_rx), + .uart_tx (uart_tx) ); - tdma u_tdma ( - .clk (clk_1x), - .rst (rst_sys), - .flag_is_master (tdma_flag_is_master), - .flag_frame_sync(frame_sync_pulse), - .tdma_slot_len (tdma_slot_len[23:0]), - .tdma_tic_2_ps (tdma_tic_2_ps[23:0]), - .intr_2ps (intr_2ps), - .tx_start (tx_start), - .rx_rst (rx_rst) - ); + // tdma u_tdma ( + // .clk (clk_1x), + // .rst (rst_sys), + // .flag_is_master (tdma_flag_is_master), + // .flag_frame_sync(frame_sync_pulse), + // .tdma_slot_len (tdma_slot_len[23:0]), + // .tdma_tic_2_ps (tdma_tic_2_ps[23:0]), + // .intr_2ps (intr_2ps), + // .tx_start (tx_start), + // .rx_rst (rx_rst) + // ); @@ -292,7 +305,7 @@ module system_top ( .rst (rst_sys | phy_rst), .speed_mode (2), .send_data_ready (send_data_ready), - .send_start (tx_start), + .send_start (tx_start | tx_start_vio_pos), .send_over (tx_done), .clk_data_src (clk_data_src), .tx_data_src_tdata (enc_fifo_dout_map), @@ -306,24 +319,28 @@ module system_top ( ); RecvTop u_RecvTop ( - .clk (clk_1x), - .clk_2x (clk_2x), - .clk_4x (clk_4x), - .rst (rst_sys | rx_rst | phy_rst), - .rst2 (rst_sys | phy_rst), - .dini (bb_rx_i), - .dinq (bb_rx_q), - .ad9361_ctrl_in (ad9361_ctrl_in), - .flag_mgc_done_pulse(flag_mgc_done_pulse), - .frame_sync_pulse (frame_sync_pulse), - .vio_tsync_inter16 (1), - .EQUenable_vio (1), - .Zerozone_vio (8'd29), - .vio_stopbit (7'd60), - .flag_stop (flag_stop), - .addr_stop (addr_stop), - .recvNetData (recvNetData), - .recvNetDataNd (recvNetDataNd) + .clk (clk_1x), + .clk_2x (clk_2x), + .clk_4x (clk_4x), + .rst (rst_sys | rx_rst | phy_rst | rx_rst_vio), + .rst2 (rst_sys | phy_rst), + .dini (bb_rx_i), + .dinq (bb_rx_q), + .ad9361_ctrl_in (ad9361_ctrl_in), + .flag_mgc_done_pulse (flag_mgc_done_pulse), + .frame_sync_pulse (frame_sync_pulse), + .vio_tsync_inter16 (1), + .EQUenable_vio (1), + .Zerozone_vio (8'd29), + .vio_stopbit (7'd60), + .flag_stop (flag_stop), + .addr_stop (addr_stop), + .recvNetData (recvNetData), + .recvNetDataNd (recvNetDataNd), + .rx_data_src_fifo_tdata (rx_data_src_fifo_tdata), + .rx_data_src_fifo_tlast (rx_data_src_fifo_tlast), + .rx_data_src_fifo_tready(rx_data_src_fifo_tready), + .rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid) ); @@ -382,4 +399,11 @@ module system_top ( end + vio_system_top u_vio_system_top ( + .clk (clk_1x), + .probe_out0(rx_rst_vio), + .probe_out1(tx_start_vio), + .probe_out2(intr_2ps_vio) + ); + endmodule diff --git a/hdl/tdma.v b/hdl/tdma.v index 4470f23..362ab04 100644 --- a/hdl/tdma.v +++ b/hdl/tdma.v @@ -79,6 +79,12 @@ module tdma #( // ******** Debug ******** + vio_tdma u_vio_tdma ( + .clk (clk), + .probe_in0(tdma_slot_len), + .probe_in1(tdma_tic_2_ps), + .probe_in2(flag_is_master) + ); ila_mac_layer u_ila_mac_layer ( .clk (clk), diff --git a/hdl/width_convert.v b/hdl/width_convert.v index 028b33d..c1f886d 100644 --- a/hdl/width_convert.v +++ b/hdl/width_convert.v @@ -12,13 +12,13 @@ // * NOTE : this is the first version convert from wider bitwidth to narrower bitwidth module width_convert #( - parameter INPUT_WIDTH = 16, - parameter OUTPUT_WIDTH = 2 + parameter INPUT_WIDTH = 32, + parameter OUTPUT_WIDTH = 1 ) ( input clk, input rst, input data_in_valid, - input wire data_in_ready, + output wire data_in_ready, input wire [INPUT_WIDTH - 1 : 0] data_in, output reg data_out_valid, output reg [OUTPUT_WIDTH -1 : 0] data_out diff --git a/sim/tb_extract_mac_frame.v b/sim/tb_extract_mac_frame.v new file mode 100644 index 0000000..d7b17df --- /dev/null +++ b/sim/tb_extract_mac_frame.v @@ -0,0 +1,82 @@ +`timescale 1ns / 1ns + +module tb_extract_mac_frame (); + + reg clk = 0; + always #1 clk <= ~clk; + + reg [ 3:0] cnt_startup = 0; + reg rst; + + reg ldpc_in; + reg [31:0] cnt_in = 0; + reg [ 4:0] cnt_sleep = 0; + reg sleep = 0; + reg cnt_in_valid = 0; + + + wire m_axis_mac_frame_tvalid; + wire [31:0] m_axis_mac_frame_tdata; + wire m_axis_mac_frame_tlast; + + always @(posedge clk) begin + + if (m_axis_mac_frame_tlast == 1) begin + cnt_startup <= 0; + end + else if (cnt_startup < 4'hF) begin + cnt_startup <= cnt_startup + 1; + end + rst <= cnt_startup <= 4'hC; + + end + + always @(posedge clk) begin + if (rst) begin + cnt_in <= 0; + end + + ldpc_in <= $random(); + + if (cnt_startup == 4'hF) begin + if (sleep) begin + cnt_in <= 0; + cnt_in_valid <= 0; + cnt_sleep <= cnt_sleep + 1; + if (cnt_sleep == 5'b11111) begin + sleep <= 0; + end + end + else begin + cnt_sleep <= 0; + if (cnt_in < 1024) begin + cnt_in <= cnt_in + 1; + end + + if (cnt_in == 1023) begin + sleep <= 1; + end + + cnt_in_valid <= 1; + end + end + end + + extract_mac_frame u_extract_mac_frame ( + .clk (clk), + .rst (rst), + .ldpc_dec_out_start (cnt_startup == 4'hD), + .ldpc_dec_out_valid (cnt_in_valid), + .ldpc_dec_out_data (ldpc_in), + .m_axis_mac_frame_tvalid(m_axis_mac_frame_tvalid), + .m_axis_mac_frame_tdata (m_axis_mac_frame_tdata), + .m_axis_mac_frame_tready(1), + .m_axis_mac_frame_tlast (m_axis_mac_frame_tlast) + ); + + + + + + +endmodule diff --git a/sim/tb_scrambler.v b/sim/tb_scrambler.v new file mode 100644 index 0000000..788e06c --- /dev/null +++ b/sim/tb_scrambler.v @@ -0,0 +1,53 @@ +`timescale 1ns / 1ns +module tb_scrambler (); + + + reg clk = 0; + always #1 clk <= ~clk; + reg [3:0] cnt_startup = 0; + reg rst; + + always @(posedge clk) begin + if (cnt_startup < 4'hF) begin + cnt_startup <= cnt_startup + 1; + end + rst <= cnt_startup <= 4'hC; + end + + + reg [31:0] s_axis_tdata; + reg s_axis_tvalid; + wire s_axis_tready; + reg s_axis_tlast; + wire [31:0] m_axis_tdata; + wire m_axis_tvalid; + // wire m_axis_tvalid; + wire m_axis_tlast; + reg [31:0] cnt = 0; + + always @(posedge clk) begin + s_axis_tvalid <= (cnt_startup == 4'hF && cnt < 32); + if (rst) begin + s_axis_tdata <= 0; + end + else if (s_axis_tready && cnt < 32) begin + s_axis_tdata <= cnt; + cnt <= cnt + 1; + end + end + + scrambler u_scrambler ( + .clk (clk), + .rst (rst), + .s_axis_tdata (s_axis_tdata), + .s_axis_tvalid(s_axis_tvalid), + .s_axis_tready(s_axis_tready), + .s_axis_tlast (s_axis_tlast), + .m_axis_tdata (m_axis_tdata), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(1), + .m_axis_tlast (m_axis_tlast) + ); + + +endmodule