diff --git a/hdl/PAPR.v b/hdl/PAPR.v index b97727c..0d668af 100644 --- a/hdl/PAPR.v +++ b/hdl/PAPR.v @@ -182,13 +182,12 @@ module PAPR #( end ila_frame_sync u_ila_frame_sync ( - .clk (clk), // input wire clk - .probe0(vec_mag), // input wire [21:0] probe0 - .probe1(data_avg), // input wire [21:0] probe0 - .probe2(cs), // input wire [2:0] probe2 - .probe3(cnt), // input wire [7:0] probe2 - .probe4(frame_sync), // input wire [0:0] probe2 - .probe5(vec_mag_reserved) // input wire [21:0] probe2 + .clk (clk), // input wire clk + .probe0(vec_mag), // input wire [21:0] probe0 + .probe1(data_avg), // input wire [21:0] probe0 + .probe2(cs), // input wire [2:0] probe2 + .probe3(cnt), // input wire [7:0] probe2 + .probe4(frame_sync) // input wire [0:0] probe2 ); diff --git a/hdl/RecvTop.v b/hdl/RecvTop.v index 723dc1a..1c0aa78 100644 --- a/hdl/RecvTop.v +++ b/hdl/RecvTop.v @@ -140,7 +140,7 @@ module RecvTop ( end end - assign mgc_start = (cnt_mgc_delay == 8'hFE); + assign mgc_start = (cnt_mgc_delay == 8'hFE); assign mgc_start_quarter = (cnt_mgc_delay >= 8'hF0) && (cnt_mgc_delay <= 8'hFE); // * MGC module @@ -662,25 +662,15 @@ module RecvTop ( ); ila_recv_top u_ila_recv_top ( - .clk (clk_quarter), - .probe0 (dagc_data_in_i), // width: 12 - .probe1 (dagc_data_in_q), // width: 12 - .probe2 (flag_mgc_done), // width: 1 - .probe3 (flag_frame_sync), // width: 1 - .probe4 (flag_cfo_done), // width: 1 - .probe5 (freqdataout_i), // width: 10 - .probe6 (freqdataout_q), // width: 10 - .probe7 (IntpARdy), // width: 1 - .probe8 (IntpOuti), // width: 10 - .probe9 (IntpOutq), // width: 10 - .probe10(nd_SC_FDE_dout), // width: 1 - .probe11(SC_FDE_douti), // width: 10 - .probe12(SC_FDE_doutq), // width: 10 - .probe13(phase_adjust_rdy), // width: 1 - .probe14(phase_adjust_douti), // width: 10 - .probe15(phase_adjust_doutq), // width: 10 - .probe16(good_frames), // width: 9 - .probe17(bad_frames) // width: 9 + .clk (clk_quarter), + .probe0(dagc_data_in_i), // width: 12 + .probe1(dagc_data_in_q), // width: 12 + .probe2(flag_frame_sync), // width: 1 + .probe3(phase_adjust_rdy), // width: 1 + .probe4(phase_adjust_douti), // width: 10 + .probe5(phase_adjust_doutq), // width: 10 + .probe6(good_frames), // width: 9 + .probe7(bad_frames) // width: 9 ); diff --git a/hdl/SC_FDE_TOP.v b/hdl/SC_FDE_TOP.v index 09470e6..56ca6a9 100644 --- a/hdl/SC_FDE_TOP.v +++ b/hdl/SC_FDE_TOP.v @@ -556,4 +556,13 @@ module SC_FDE_TOP ( .flagoverflow_FDE_dataout_29to10q(flagoverflow_FDE_dataout_29to10q) //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 ); + // ila_scfde u_ila_scfde ( + // .clk (clk), // input wire clk + // .probe0(flag_ow_left), // 1 + // .probe1(ifft_out_nd), // 1 + // .probe2(ifft_index), // 8 + // .probe3(ifft_out_tdata) //64 + // ); + + endmodule diff --git a/hdl/Transmitter.v b/hdl/Transmitter.v index f01cfdb..a49cbb7 100644 --- a/hdl/Transmitter.v +++ b/hdl/Transmitter.v @@ -561,15 +561,15 @@ module Transmitter #( // ******** Debug ******** - ila_transmitter u_ila_transmitter ( - .clk (clk), // input wire clk - .probe0(cnt_sym_send), // input wire [15:0] probe0 - .probe1(cs), // input wire [3:0] probe1 - .probe2(ns), // input wire [3:0] probe2 - .probe3(send_data_ready), // input wire [0:0] probe3 - .probe4(send_start), // input wire [0:0] probe4 - .probe5(tx_data_src_tvalid) // input wire [0:0] probe5 - ); + // ila_transmitter u_ila_transmitter ( + // .clk (clk), // input wire clk + // .probe0(cnt_sym_send), // input wire [15:0] probe0 + // .probe1(cs), // input wire [3:0] probe1 + // .probe2(ns), // input wire [3:0] probe2 + // .probe3(send_data_ready), // input wire [0:0] probe3 + // .probe4(send_start), // input wire [0:0] probe4 + // .probe5(tx_data_src_tvalid) // input wire [0:0] probe5 + // ); endmodule diff --git a/hdl/ad9361_mgc_pin_ctrl.v b/hdl/ad9361_mgc_pin_ctrl.v index 4bb9832..5eee16a 100644 --- a/hdl/ad9361_mgc_pin_ctrl.v +++ b/hdl/ad9361_mgc_pin_ctrl.v @@ -162,18 +162,18 @@ module ad9361_mgc_pin_ctrl ( // .probe_out0(start) // output wire [0 : 0] probe_out0 // ); - ila_ad9361_mgc u_ila_ad9361_mgc ( - .clk (clk), // input wire clk - .probe0(start_posedge), // input wire [0:0] probe0 - .probe1(rx_data_i), // input wire [11:0] probe1 - .probe2(u_power_measure.cs), // input wire [2:0] probe2 - .probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3 - .probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4 - .probe5(flag_too_high), // input wire [0:0] probe5 - .probe6(flag_too_low), // input wire [0:0] probe6 - .probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6 - .probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6 - ); + // ila_ad9361_mgc u_ila_ad9361_mgc ( + // .clk (clk), // input wire clk + // .probe0(start_posedge), // input wire [0:0] probe0 + // .probe1(rx_data_i), // input wire [11:0] probe1 + // .probe2(u_power_measure.cs), // input wire [2:0] probe2 + // .probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3 + // .probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4 + // .probe5(flag_too_high), // input wire [0:0] probe5 + // .probe6(flag_too_low), // input wire [0:0] probe6 + // .probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6 + // .probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6 + // ); endmodule diff --git a/hdl/phy_control.v b/hdl/phy_control.v index a5a8b89..20f3571 100644 --- a/hdl/phy_control.v +++ b/hdl/phy_control.v @@ -410,10 +410,10 @@ module phy_control #( // frame sync tic assign tdma_frame_sync_tic = tdma_frame_sync_tic_reg; - vio_phy_param u_vio_phy_param ( - .clk (local_clk), - .probe_in0(phy_cr_reg) - ); + // vio_phy_param u_vio_phy_param ( + // .clk (local_clk), + // .probe_in0(phy_cr_reg) + // ); //--- ADD YOUR OWN LOGIC END