From 92583b785cf6c1851d8f9dee1d77483472969e98 Mon Sep 17 00:00:00 2001 From: ZoroGH Date: Mon, 29 Jul 2024 19:04:48 +0800 Subject: [PATCH] feat(top): add mac layer control, half tested --- contraint/mm7020_timing.xdc | 5 +- hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v | 220 +++++++-------- hdl/RecvTop.v | 64 +++-- hdl/net_city.v | 419 ++++++++++++++++++++++++++++ hdl/system_top.v | 222 +++++++++------ hdl/tdma.v | 114 +++----- 6 files changed, 738 insertions(+), 306 deletions(-) create mode 100644 hdl/net_city.v diff --git a/contraint/mm7020_timing.xdc b/contraint/mm7020_timing.xdc index ed3106c..a5bd3d5 100644 --- a/contraint/mm7020_timing.xdc +++ b/contraint/mm7020_timing.xdc @@ -1,3 +1,4 @@ -set_property MAX_FANOUT 512 [get_nets *u_Receiver/mag*] +set_property MAX_FANOUT 512 [get_nets *u_RecvTop/mag*] # set_property MAX_FANOUT 512 [get_nets u_Receiver/mag_valid] -set_false_path -through [get_nets u_Receiver/rst] \ No newline at end of file +# set_false_path -through [get_nets u_Receiver/rst] +set_false_path -through [get_nets u_RecvTop/SR[0]] \ No newline at end of file diff --git a/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v b/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v index 4b491f2..a8b5bf1 100644 --- a/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v +++ b/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v @@ -20,130 +20,122 @@ ////////////////////////////////////////////////////////////////////////////////// -module CCSDS_LDPC_DEC_K1024_R12_TOPP - #( - parameter MAX_ITER_NUM = 6'd14, //最大迭代次数常量 - parameter WIDTH = 4'd8, //量化比特 - parameter OUT_ONLY_INFORMATION = 1'b0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字 - ) - ( - input clk, //工作时钟,100MHz - input Rst, //同步复位信号,高有效 - input FrameSync, //帧同步标志,高脉冲 - input Nd, //译码输入数据有效标志,高有效 - input [WIDTH-1:0] Din, //译码输入数据,软信息 - - - output LDPC_SyncOut, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点 - output Rdy, //译码输出信号有效标志,高有效 - output [0:0] LDPC_Dout, //译码输出信号,MSB输出 - - output [8:0] good_frames, //译码好帧计数 - output [8:0] bad_frames, //译码坏帧计数 - output [8:0] total_frames //译码总帧数计数 - ); - - wire FrameSync_A_TM; - wire Nd_A_TM; - wire [WIDTH-1:0] Din_A_TM; - - wire FrameSync_B_TM; - wire Nd_B_TM; - wire [WIDTH-1:0] Din_B_TM; - - wire LDPC_SyncOut_A; - wire Rdy_A; - wire [0:0] LDPC_Dout_A; - wire [8:0] good_frames_A; - wire [8:0] bad_frames_A; - wire [8:0] total_frames_A; +module CCSDS_LDPC_DEC_K1024_R12_TOPP #( + parameter MAX_ITER_NUM = 6'd14, //最大迭代次数常量 + parameter WIDTH = 4'd8, //量化比特 + parameter OUT_ONLY_INFORMATION = 1'b1 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字 +) ( + input clk, //工作时钟,100MHz + input Rst, //同步复位信号,高有效 + input FrameSync, //帧同步标志,高脉冲 + input Nd, //译码输入数据有效标志,高有效 + input [WIDTH-1:0] Din, //译码输入数据,软信息 - wire LDPC_SyncOut_B; - wire Rdy_B; - wire [0:0] LDPC_Dout_B; - wire [8:0] good_frames_B; - wire [8:0] bad_frames_B; - wire [8:0] total_frames_B; - - LDPC_TopManage_2 - #( + output LDPC_SyncOut, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点 + output Rdy, //译码输出信号有效标志,高有效 + output [0:0] LDPC_Dout, //译码输出信号,MSB输出 + + output [8:0] good_frames, //译码好帧计数 + output [8:0] bad_frames, //译码坏帧计数 + output [8:0] total_frames //译码总帧数计数 +); + + wire FrameSync_A_TM; + wire Nd_A_TM; + wire [WIDTH-1:0] Din_A_TM; + + wire FrameSync_B_TM; + wire Nd_B_TM; + wire [WIDTH-1:0] Din_B_TM; + + wire LDPC_SyncOut_A; + wire Rdy_A; + wire [ 0:0] LDPC_Dout_A; + wire [ 8:0] good_frames_A; + wire [ 8:0] bad_frames_A; + wire [ 8:0] total_frames_A; + + wire LDPC_SyncOut_B; + wire Rdy_B; + wire [ 0:0] LDPC_Dout_B; + wire [ 8:0] good_frames_B; + wire [ 8:0] bad_frames_B; + wire [ 8:0] total_frames_B; + + + LDPC_TopManage_2 #( .WIDTH(WIDTH) - ) - TM ( - .clk(clk), - .Rst(Rst), - .FrameSync_TM(FrameSync), - .Nd_TM(Nd), - .Din_TM(Din), - .FrameSync_A_TM(FrameSync_A_TM), - .Nd_A_TM(Nd_A_TM), - .Din_A_TM(Din_A_TM), - .FrameSync_B_TM(FrameSync_B_TM), - .Nd_B_TM(Nd_B_TM), - .Din_B_TM(Din_B_TM), - .LDPC_SyncOut_A_TM(LDPC_SyncOut_A), - .Rdy_A_TM(Rdy_A), - .LDPC_Dout_A_TM(LDPC_Dout_A), - .good_frames_A_TM(good_frames_A), - .bad_frames_A_TM(bad_frames_A), - .total_frames_A_TM(total_frames_A), - .LDPC_SyncOut_B_TM(LDPC_SyncOut_B), - .Rdy_B_TM(Rdy_B), - .LDPC_Dout_B_TM(LDPC_Dout_B), - .good_frames_B_TM(good_frames_B), - .bad_frames_B_TM(bad_frames_B), - .total_frames_B_TM(total_frames_B), - .LDPC_SyncOut_TM(LDPC_SyncOut), - .Rdy_TM(Rdy), - .LDPC_Dout_TM(LDPC_Dout), - .good_frames_TM(good_frames), - .bad_frames_TM(bad_frames), - .total_frames_TM(total_frames) + ) TM ( + .clk (clk), + .Rst (Rst), + .FrameSync_TM (FrameSync), + .Nd_TM (Nd), + .Din_TM (Din), + .FrameSync_A_TM (FrameSync_A_TM), + .Nd_A_TM (Nd_A_TM), + .Din_A_TM (Din_A_TM), + .FrameSync_B_TM (FrameSync_B_TM), + .Nd_B_TM (Nd_B_TM), + .Din_B_TM (Din_B_TM), + .LDPC_SyncOut_A_TM(LDPC_SyncOut_A), + .Rdy_A_TM (Rdy_A), + .LDPC_Dout_A_TM (LDPC_Dout_A), + .good_frames_A_TM (good_frames_A), + .bad_frames_A_TM (bad_frames_A), + .total_frames_A_TM(total_frames_A), + .LDPC_SyncOut_B_TM(LDPC_SyncOut_B), + .Rdy_B_TM (Rdy_B), + .LDPC_Dout_B_TM (LDPC_Dout_B), + .good_frames_B_TM (good_frames_B), + .bad_frames_B_TM (bad_frames_B), + .total_frames_B_TM(total_frames_B), + .LDPC_SyncOut_TM (LDPC_SyncOut), + .Rdy_TM (Rdy), + .LDPC_Dout_TM (LDPC_Dout), + .good_frames_TM (good_frames), + .bad_frames_TM (bad_frames), + .total_frames_TM (total_frames) ); - - CCSDS_LDPC_DEC_K1024_R12 - #( - .MAX_ITER_NUM(MAX_ITER_NUM), + + CCSDS_LDPC_DEC_K1024_R12 #( + .MAX_ITER_NUM(MAX_ITER_NUM), .WIDTH(WIDTH), - .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION) - ) - inst_DEC_A ( - .clk(clk), - .Rst(Rst), - .FrameSync(FrameSync_A_TM), - .Nd(Nd_A_TM), - .Din(Din_A_TM), - .LDPC_SyncOut(LDPC_SyncOut_A), - .Rdy(Rdy_A), - .LDPC_Dout(LDPC_Dout_A), - .good_frames(good_frames_A), - .bad_frames(bad_frames_A), - .total_frames(total_frames_A) + .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION) + ) inst_DEC_A ( + .clk (clk), + .Rst (Rst), + .FrameSync (FrameSync_A_TM), + .Nd (Nd_A_TM), + .Din (Din_A_TM), + .LDPC_SyncOut(LDPC_SyncOut_A), + .Rdy (Rdy_A), + .LDPC_Dout (LDPC_Dout_A), + .good_frames (good_frames_A), + .bad_frames (bad_frames_A), + .total_frames(total_frames_A) ); - - CCSDS_LDPC_DEC_K1024_R12 - #( - .MAX_ITER_NUM(MAX_ITER_NUM), + + CCSDS_LDPC_DEC_K1024_R12 #( + .MAX_ITER_NUM(MAX_ITER_NUM), .WIDTH(WIDTH), - .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION) - ) - inst_DEC_B ( - .clk(clk), - .Rst(Rst), - .FrameSync(FrameSync_B_TM), - .Nd(Nd_B_TM), - .Din(Din_B_TM), - .LDPC_SyncOut(LDPC_SyncOut_B), - .Rdy(Rdy_B), - .LDPC_Dout(LDPC_Dout_B), - .good_frames(good_frames_B), - .bad_frames(bad_frames_B), - .total_frames(total_frames_B) + .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION) + ) inst_DEC_B ( + .clk (clk), + .Rst (Rst), + .FrameSync (FrameSync_B_TM), + .Nd (Nd_B_TM), + .Din (Din_B_TM), + .LDPC_SyncOut(LDPC_SyncOut_B), + .Rdy (Rdy_B), + .LDPC_Dout (LDPC_Dout_B), + .good_frames (good_frames_B), + .bad_frames (bad_frames_B), + .total_frames(total_frames_B) ); - + endmodule diff --git a/hdl/RecvTop.v b/hdl/RecvTop.v index 3f8940c..f85a607 100644 --- a/hdl/RecvTop.v +++ b/hdl/RecvTop.v @@ -19,27 +19,28 @@ // ////////////////////////////////////////////////////////////////////////////////// module RecvTop ( - input clk, - input clk_2x, // clk_2x - input clk_4x, - input rst, - input rst2, // TODO： delete the signal + input clk, + input clk_2x, // clk_2x + input clk_4x, + input rst, + input rst2, // TODO： delete the signal // phy wave - input [11:0] dini, - input [11:0] dinq, + input [11:0] dini, + input [11:0] dinq, // mgc control - output [ 3:0] ad9361_ctrl_in, + output [ 3:0] ad9361_ctrl_in, + output wire frame_sync_pulse, // in domain clk //vio - input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路 - input EQUenable_vio, //为1时启用均衡 - input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29 - input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60 + input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路 + input EQUenable_vio, //为1时启用均衡 + input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29 + input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60 // stop signal - output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 - output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 + output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 + output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 // mac frame header - output [63:0] recvNetData, - output recvNetDataNd + output [63:0] recvNetData, + output recvNetDataNd ); wire rst_TimeSync; @@ -255,12 +256,12 @@ module RecvTop ( .m_axis_data_tdata (dmf_tdata_interp4_q) ); - localparam CNT_CHU_SEQ_SYNC_MAX = 40;//! should not less than 3 due to the minimum rst of aresetn + localparam CNT_CHU_SEQ_SYNC_MAX = 40; //! should not less than 3 due to the minimum rst of aresetn wire [21:0] mag; wire mag_valid; wire frame_sync_4x; - wire frame_sync_pulse; // in domain clk + // wire frame_sync_pulse; reg flag_frame_sync; // active high level wire rst_frame_sync; // derive from frame sync pulse reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos @@ -411,9 +412,9 @@ module RecvTop ( .clk (clk), .rst (rst_frame_sync), // param - .EQUenable_vio (EQUenable_vio), //为1时启用均衡 - .Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29 - .flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐 + .EQUenable_vio (EQUenable_vio), //为1时启用均衡 + .Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29 + .flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐 .nd (IntpARdy), .dini (IntpOuti), .dinq (IntpOutq), @@ -533,6 +534,27 @@ module RecvTop ( .src_rst () // 1-bit input: optional; required when RST_USED = 1 ); + // ***** debug ***** + + ila_recv_top u_ila_recv_top ( + .clk (clk), + .probe0 (flag_mgc_done), // width: 1 + .probe1 (flag_frame_sync), // width: 1 + .probe2 (mf_data_interp4_q), // width: 32 + .probe3 (mf_data_interp4_i), // width: 32 + .probe4 (freqestm.freq_out), // width: 14 + .probe5 (freqdataout_i), // width: 10 + .probe6 (freqdataout_q), // width: 10 + .probe7 (nd_SC_FDE_dout), // width: 1 + .probe8 (SC_FDE_douti), // width: 10 + .probe9 (SC_FDE_doutq), // width: 10 + .probe10(LDPC_SyncOut), // width: 1 + .probe11(LDPC_Rdy), // width: 1 + .probe12(LDPC_Dout), // width: 1 + .probe13(bad_frames), // width: 9 + .probe14(total_frames), // width: 9 + .probe15(mgc_start) // width: 1 + ); endmodule diff --git a/hdl/net_city.v b/hdl/net_city.v new file mode 100644 index 0000000..84ab267 --- /dev/null +++ b/hdl/net_city.v @@ -0,0 +1,419 @@ +`timescale 1ns / 1ps + +module net_city ( + // basic + input clk, + input rst_initial, + input rst_manual, //manual + // tx signal + output reg tx_start = 1'b0, // pulse + output reg [63:0] trans_net_data = 64'd0, + output reg flag_video_send = 1'b0, + output reg [07:0] recv_id = 8'd0, + // rx signal + input frame_sync, + input recv_net_data_nd, + input [63:0] recv_net_data, + // net parameter + input [31:0] frame_sync_time, + input [07:0] id_num, + input [07:0] max_slot_num, + input [07:0] video_id01, + input [07:0] video_id02, + input [07:0] video_id03, + // net state + output reg is_net = 1'b0, + output reg flag_to_uc = 1'b0, + // intr 2 ps + output wire intr_ps, + output reg rx_rst, + input wire tx_done +); + //----------parameter---------- + localparam SLOT_TIME = 750000; // 15ms + + //----------rst---------- + wire rst; + assign rst = rst_initial || rst_manual; + + //----------counter_1s---------- + reg [31:0] cnt_1s = 32'd0; + always @(posedge clk) begin + if (rst) begin + cnt_1s <= 32'd0; + end + else begin + if (cnt_1s == 32'd49999999) begin + cnt_1s <= 32'd0; + end + else begin + cnt_1s <= cnt_1s + 32'd1; + end + end + end + + //----------flag_tx---------- + + + //----------state_net---------- + reg [07:0] state_net = 8'd0; + reg [31:0] cnt_trans_slot = 32'd0; + reg [31:0] cnt_inter_slot = 32'd0; + reg [07:0] cur_slot = 8'd0; + reg [07:0] cnt_video_slot = 8'd0; + reg [31:0] cnt_other = 32'd0; + + reg [07:0] connect_node = 8'd0; + reg [63:0] trans_net_data_reg = 64'd0; + reg [07:0] recv_connect_node = 8'd0; + reg [07:0] recv_video_id01 = 8'd0; + reg [07:0] recv_video_id02 = 8'd0; + reg [07:0] recv_video_id03 = 8'd0; + + // if u dont understand this code blew, plz contact NanzZ 😊 + assign intr_ps = (cnt_trans_slot == SLOT_TIME - 50000) && ((id_num == 1 && (cur_slot == max_slot_num - 1)) || (id_num != 1 && (cur_slot == id_num - 8'd2))); + + always @(posedge clk) begin + if (rst) begin + rx_rst <= 1; + end + else if (tx_start) begin + rx_rst <= 1; + end + else if (tx_done) begin + rx_rst <= 0; + end + end + + + + always @(posedge clk) begin + if (rst) begin + state_net <= 8'd0; + cnt_trans_slot <= 32'd0; + cnt_inter_slot <= 32'd0; + cnt_other <= 32'd0; + recv_id <= 8'd0; + recv_connect_node <= 8'd0; + recv_video_id01 <= 8'd0; + recv_video_id02 <= 8'd0; + recv_video_id03 <= 8'd0; + tx_start <= 1'b0; + trans_net_data <= 64'd0; + is_net <= 1'b0; + flag_video_send <= 1'b0; + end + else begin + case (state_net) + 8'd0: begin + state_net <= 8'd1; + cnt_trans_slot <= 32'd0; + cnt_inter_slot <= 32'd0; + cnt_other <= 32'd0; + recv_id <= recv_id; + recv_connect_node <= 8'd0; + recv_video_id01 <= recv_video_id01; + recv_video_id02 <= recv_video_id02; + recv_video_id03 <= recv_video_id03; + tx_start <= 1'b0; + trans_net_data <= 64'd0; + is_net <= 1'b0; + flag_video_send <= 1'b0; + end + 8'd1: begin + state_net <= 8'd2; + end + 8'd2: begin + if (frame_sync) begin + state_net <= 8'd50; + cnt_other <= 32'd0; + cnt_trans_slot <= frame_sync_time; + cnt_inter_slot <= cnt_trans_slot + 32'd1; + end + else if (cnt_other == 32'd49999999) begin + cnt_other <= 32'd0; + state_net <= 8'd100; + is_net <= 1'b1; + end + else begin + cnt_other <= cnt_other + 32'd1; + end + end + + 8'd100: begin // _tx + state_net <= 8'd101; + tx_start <= 1'b1; + trans_net_data <= trans_net_data_reg; + cnt_trans_slot <= 32'd0; + cnt_inter_slot <= 32'd0; + end + 8'd101: begin + state_net <= 8'd200; + tx_start <= 1'b0; + cnt_trans_slot <= cnt_trans_slot + 32'd1; + end + + 8'd200: begin // wait + if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num == 1 && (cur_slot == max_slot_num - 1))) begin + state_net <= 8'd100; + cnt_trans_slot <= cnt_trans_slot + 32'd1; + cnt_inter_slot <= 32'd0; + end + else if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num != 1 && (cur_slot == id_num - 8'd2))) begin + state_net <= 8'd100; + cnt_trans_slot <= cnt_trans_slot + 32'd1; + cnt_inter_slot <= 32'd0; + end + else if (frame_sync) begin + state_net <= 8'd50; + cnt_trans_slot <= frame_sync_time; + cnt_inter_slot <= cnt_trans_slot + 32'd1; + end + else begin + if (cnt_trans_slot == SLOT_TIME - 1) begin + cnt_trans_slot <= 32'd0; + end + else begin + cnt_trans_slot <= cnt_trans_slot + 32'd1; + end + cnt_inter_slot <= 32'd0; + end + + case (id_num) + recv_video_id01: begin + if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd0) begin + flag_video_send <= 1'b1; + end + else begin + flag_video_send <= 1'b0; + end + end + recv_video_id02: begin + if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd1) begin + flag_video_send <= 1'b1; + end + else begin + flag_video_send <= 1'b0; + end + end + recv_video_id03: begin + if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd2) begin + flag_video_send <= 1'b1; + end + else begin + flag_video_send <= 1'b0; + end + end + default: begin + flag_video_send <= 1'b0; + end + endcase + end + + 8'd50: begin + if (recv_net_data_nd) begin + if (recv_net_data[23:00] == 24'h7e5a33) begin + state_net <= 8'd51; + is_net <= 1'b1; + + cnt_trans_slot <= cnt_trans_slot + 32'd1; + cnt_inter_slot <= cnt_inter_slot + 32'd1; + + recv_id <= recv_net_data[63:56]; + recv_video_id01 <= recv_net_data[55:48]; + recv_video_id02 <= recv_net_data[47:40]; + recv_video_id03 <= recv_net_data[39:32]; + recv_connect_node <= recv_net_data[31:24]; + end + else begin + state_net <= 8'd200; + is_net <= 1'b0; + + cnt_trans_slot <= cnt_inter_slot + 32'd1; + end + end + else begin + cnt_trans_slot <= cnt_trans_slot + 32'd1; + cnt_inter_slot <= cnt_inter_slot + 32'd1; + end + end + 8'd51: begin + state_net <= 8'd200; + cnt_trans_slot <= cnt_trans_slot + 32'd1; + end + + default: begin + state_net <= 8'd0; + cnt_trans_slot <= 32'd0; + cnt_inter_slot <= 32'd0; + cnt_other <= 32'd0; + recv_id <= recv_id; + recv_connect_node <= 8'd0; + recv_video_id01 <= recv_video_id01; + recv_video_id02 <= recv_video_id02; + recv_video_id03 <= recv_video_id03; + tx_start <= 1'b0; + trans_net_data <= 64'd0; + is_net <= 1'b0; + flag_video_send <= 1'b0; + end + endcase + end + end + + //----------connect_node---------- + // always @(posedge clk) begin + // if (rst) begin + // connect_node <= 8'd0; + // end else begin + // if (state_net == 8'd51) begin + // case (recv_id) + // 8'd1: begin + // connect_node[07:06] <= 2'b11; + // end + // 8'd2: begin + // connect_node[05:04] <= 2'b11; + // end + // 8'd3: begin + // connect_node[03:02] <= 2'b11; + // end + // 8'd4: begin + // connect_node[01:00] <= 2'b11; + // end + // default: begin + // connect_node <= 8'd0; + // end + // endcase + // end else if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num) begin + // connect_node <= 8'd0; + // end else begin + // connect_node <= connect_node; + // end + // end + // end + + //----------trans_net_data_reg---------- + reg [07:0] trans_video_id01; + reg [07:0] trans_video_id02; + reg [07:0] trans_video_id03; + always @(posedge clk) begin + if (rst) begin + trans_video_id01 <= 8'd0; + trans_video_id02 <= 8'd0; + trans_video_id03 <= 8'd0; + end + else begin + if (id_num == 8'd1) begin //主节点 + trans_video_id01 <= video_id01; + trans_video_id02 <= video_id02; + trans_video_id03 <= video_id03; + end + else if (recv_id == 8'd1) begin //从节点只听从主节点命令 + trans_video_id01 <= recv_video_id01; + trans_video_id02 <= recv_video_id02; + trans_video_id03 <= recv_video_id03; + end + else begin + trans_video_id01 <= trans_video_id01; + trans_video_id02 <= trans_video_id02; + trans_video_id03 <= trans_video_id03; + end + end + end + always @(posedge clk) begin + if (rst) begin + trans_net_data_reg <= 64'd0; + end + else begin + if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num - 8'd1) begin + trans_net_data_reg[63:56] <= id_num; + trans_net_data_reg[55:48] <= trans_video_id01; + trans_net_data_reg[47:40] <= trans_video_id02; + trans_net_data_reg[39:32] <= trans_video_id03; + trans_net_data_reg[31:24] <= connect_node; + trans_net_data_reg[23:00] <= 24'h7e5a33; + end + else begin + trans_net_data_reg <= trans_net_data_reg; + end + end + end + + //----------cur_slot---------- + always @(posedge clk) begin + if (rst) begin + cur_slot <= 8'd0; + end + else begin + if (state_net == 8'd51) begin + if (recv_id <= max_slot_num) begin + cur_slot <= recv_id - 8'd1; + end + else begin + cur_slot <= cur_slot; + end + end + else if (cnt_trans_slot == SLOT_TIME - 1) begin + if (cur_slot == max_slot_num - 8'd1) begin + cur_slot <= 8'd0; + end + else begin + cur_slot <= cur_slot + 8'd1; + end + end + else begin + cur_slot <= cur_slot; + end + end + end + + //----------cnt_video_slot---------- + always @(posedge clk) begin + if (rst) begin + cnt_video_slot <= 8'd0; + end + else begin + if (cnt_trans_slot == SLOT_TIME - 1) begin + if (cnt_video_slot == 8'd2) begin + cnt_video_slot <= 8'd0; + end + else begin + cnt_video_slot <= cnt_video_slot + 8'd1; + end + end + else begin + cnt_video_slot <= cnt_video_slot; + end + end + end + + always @(posedge clk) begin + if (rst) begin + flag_to_uc <= 1'b0; + end + else begin + if (cnt_trans_slot == SLOT_TIME / 2 - 1) begin + flag_to_uc <= 1'b1; + end + else begin + flag_to_uc <= 1'b0; + end + end + end + + ila_MAC ila_MAC ( + .clk (clk), + .probe0 (tx_start), + .probe1 (connect_node), + .probe2 (cnt_trans_slot), + .probe3 (recv_net_data), + .probe4 (state_net), + .probe5 (recv_id), + .probe6 (cur_slot), + .probe7 (id_num), + .probe8 (frame_sync), + .probe9 (max_slot_num), + .probe10(recv_net_data_nd), + .probe11(trans_net_data) + ); +endmodule diff --git a/hdl/system_top.v b/hdl/system_top.v index 39433ca..d2e86f6 100644 --- a/hdl/system_top.v +++ b/hdl/system_top.v @@ -108,7 +108,21 @@ module system_top ( // tx signal wire frame_sync_pulse; + wire rx_rst; + wire tx_done; + wire intr_2ps_vio; + reg intr_2ps_vio_d1; + wire intr_2ps_vio_pos; + wire tx_start_vio; + reg tx_start_vio_d1; + wire tx_start_vio_pos; + + // vio + wire rst_manual; + wire [ 7:0] node_id; + wire intr_2ps; + wire [ 7:0] max_slot_num; // ******** Assingment ******** @@ -197,76 +211,101 @@ module system_top ( ); + // tdma #( + // .SLOT_LEN (750000), // 50MHz--> 15ms + // .TIC_TO_PS_LEN (700000), + // .TIC_FRAME_SYNC(42344) + // ) u_tdma ( + // .clk (clk_1x), + // .rst (rst_sys), + // .flag_is_master (0), + // .flag_frame_sync(frame_sync_pulse), + // .intr_2ps (intr_2ps), + // .tx_start (tx_start), + // .rx_rst (rx_rst) + // ); + + net_city u_net_city ( + .clk (clk_1x), + .rst_initial (rst_sys), + .rst_manual (rst_manual), + .tx_start (tx_start), + .trans_net_data (), + .flag_video_send (), + .recv_id (), + .frame_sync (frame_sync_pulse), + .recv_net_data_nd(1), + .recv_net_data (0), + .frame_sync_time (42344), + .id_num (node_id), + .max_slot_num (max_slot_num), + .video_id01 (0), + .video_id02 (0), + .video_id03 (0), + .is_net (), + .flag_to_uc (), + .intr_ps (intr_2ps), + .rx_rst (rx_rst), + .tx_done (tx_done) + ); // ---- PHY layer logic start - // enc_control u_enc_control ( - // .clk (clk_poweron), - // .rst (rst_sys | phy_rst_ps), - // .s_axis_fifo_tvalid (tx_data_src_tvalid), - // .s_axis_fifo_tready (tx_data_src_tready), - // .s_axis_fifo_tdata (tx_data_src_tdata), - // .data_src_count (tx_data_src_count), - // .fifo_enc_out_rd_clk (clk_1x), - // .fifo_enc_out_rd_en (enc_fifo_rd_en), - // .fifo_enc_out_dout_map(enc_fifo_dout_map), - // .fifo_enc_out_empty (enc_fifo_empty) - // ); - - - // tdma #( - // .SLOT_LEN (1250000), // 50MHz--> 25ms - // .TIC_TO_PS_LEN (1200000), - // .TIC_FRAME_SYNC(42272) - // ) u_tdma ( - // .clk (clk_1x), - // .rst (rst_sys), - // .flag_is_master (1'b0), - // .flag_frame_sync(frame_sync_pulse), - // .intr_2ps (intr_2ps), - // .tx_start (tx_start) - // ); - - - // Transmitter u_Transmitter ( - // .clk (clk_1x), - // .rst (rst_sys | phy_rst | phy_rst_vio), - // .speed_mode (speed_mode), - // .send_data_ready (send_data_ready), - // .send_start (send_start), - // .send_over (send_over), - // .clk_data_src (clk_data_src), - // .tx_data_src_tdata (enc_fifo_dout_map), - // .tx_data_src_tready(enc_fifo_rd_en), - // .tx_data_src_tvalid(~enc_fifo_empty), - // .hopping_freq (), - // .ad9361_tx_data_i (ad9361_tx_data_i), - // .ad9361_tx_data_q (ad9361_tx_data_q), - // .test (tx_test_flag | phy_tx_test_flag_vio), - // .hop_wait (100) - // ); - - // Receiver u_Receiver ( - // .clk (clk_1x), - // .clk_2x (clk_2x), - // .clk_4x (clk_4x), - // .rst (rst_sys | phy_rst | phy_rst_vio), - // .speed_mode (speed_mode), - // .ad9361_rx_data_i(ad9361_rx_data_i), - // .ad9361_rx_data_q(ad9361_rx_data_q), - // .frame_sync_pulse(frame_sync_pulse) - // ); - - ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ( - .clk (clk_1x), - .rst (rst_sys | phy_rst), - .rx_data_i (ad9361_rx_data_i), - .rx_data_q (ad9361_rx_data_q), - .ad9361_ctrl_in(ad9361_ctrl_in) + enc_control u_enc_control ( + .clk (clk_poweron), + .rst (rst_sys | phy_rst_ps), + .s_axis_fifo_tvalid (tx_data_src_tvalid), + .s_axis_fifo_tready (tx_data_src_tready), + .s_axis_fifo_tdata (tx_data_src_tdata), + .data_src_count (tx_data_src_count), + .fifo_enc_out_rd_clk (clk_1x), + .fifo_enc_out_rd_en (enc_fifo_rd_en), + .fifo_enc_out_dout_map(enc_fifo_dout_map), + .fifo_enc_out_empty (enc_fifo_empty) ); + Transmitter u_Transmitter ( + .clk (clk_1x), + .rst (rst_sys | phy_rst), + .speed_mode (2), + .send_data_ready (send_data_ready), + .send_start (tx_start), + .send_over (tx_done), + .clk_data_src (clk_data_src), + .tx_data_src_tdata (enc_fifo_dout_map), + .tx_data_src_tready(enc_fifo_rd_en), + .tx_data_src_tvalid(~enc_fifo_empty), + .hopping_freq (), + .ad9361_tx_data_i (ad9361_tx_data_i), + .ad9361_tx_data_q (ad9361_tx_data_q), + .test (tx_test_flag | phy_tx_test_flag_vio), + .hop_wait (100) + ); + + RecvTop u_RecvTop ( + .clk (clk_1x), + .clk_2x (clk_2x), + .clk_4x (clk_4x), + .rst (rst_sys | rx_rst | phy_rst), + .rst2 (rst_sys | phy_rst), + .dini (ad9361_rx_data_i), + .dinq (ad9361_rx_data_q), + .ad9361_ctrl_in (ad9361_ctrl_in), + .frame_sync_pulse (frame_sync_pulse), + .vio_tsync_inter16(1), + .EQUenable_vio (1), + .Zerozone_vio (8'd29), + .vio_stopbit (7'd60), + .flag_stop (flag_stop), + .addr_stop (addr_stop), + .recvNetData (recvNetData), + .recvNetDataNd (recvNetDataNd) + ); + + + @@ -318,41 +357,38 @@ module system_top ( // ******** Debug ******** - ila_ad9361_rx u_ila_ad9361_rx ( - .clk (ad9361_rx_clk), - .probe0(ad9361_rx_data_i), - .probe1(ad9361_rx_data_q), - .probe2(u_ad9361_mgc_pin_ctrl.flag_adjust) - ); + // ila_ad9361_rx u_ila_ad9361_rx ( + // .clk (ad9361_rx_clk), + // .probe0(ad9361_rx_data_i), + // .probe1(ad9361_rx_data_q), + // .probe2(u_ad9361_mgc_pin_ctrl.flag_adjust) + // ); - ila_ad9361_tx u_ila_ad9361_tx ( - .clk (ad9361_tx_clk), // input wire clk - .probe0(ad9361_tx_data_i), // input wire [11:0] probe0 - .probe1(ad9361_tx_data_q) // input wire [11:0] probe1 - ); + // ila_ad9361_tx u_ila_ad9361_tx ( + // .clk (ad9361_tx_clk), // input wire clk + // .probe0(ad9361_tx_data_i), // input wire [11:0] probe0 + // .probe1(ad9361_tx_data_q) // input wire [11:0] probe1 + // ); + assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1; + always @(posedge clk_1x) begin + tx_start_vio_d1 <= tx_start_vio; + end + + assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1; + always @(posedge clk_1x) begin + intr_2ps_vio_d1 <= intr_2ps_vio; + end + vio_phy_control u_vio_phy_control ( - .clk (clk_1x), // input wire clk - .probe_out0(phy_rst_vio), // output wire [0 : 0] probe_out0 - .probe_out1(phy_tx_test_flag_vio), // output wire [0 : 0] probe_out1 - .probe_out2(send_start) // output wire [0 : 0] probe_out2 + .clk (clk_1x), // input wire clk + .probe_out0(rst_manual), // output wire [0 : 0] + .probe_out1(node_id), // output wire [7 : 0] + .probe_out2(max_slot_num), // output wire [7 : 0] + .probe_out3(intr_2ps_vio), // output wire [0 : 0] + .probe_out4(tx_start_vio) // output wire [0 : 0] ); - vio_gpio u_vio_gpio ( - .clk (clk_poweron), - .probe_out0(rf_gpio), - .probe_out1(led_red), - .probe_out2(led_yellow), - .probe_out3(led_blue) - ); - - vio_tx_speed_mode u_vio_tx_speed_mode ( - .clk (clk_1x), - .probe_out0(speed_mode) - ); - - - endmodule diff --git a/hdl/tdma.v b/hdl/tdma.v index 5a4eed4..d283d72 100644 --- a/hdl/tdma.v +++ b/hdl/tdma.v @@ -18,99 +18,61 @@ module tdma #( parameter TIC_TO_PS_LEN = 1200000, parameter TIC_FRAME_SYNC = 42272 ) ( - input clk, - input rst, - input flag_is_master, - input flag_frame_sync, - output intr_2ps, - // output tic_hop, - output tx_start + input clk, + input rst, + input flag_is_master, // TODO: refactor it to parameters + input flag_frame_sync, + output intr_2ps, + (* KEEP = "TRUE" *) output tx_start, + (* KEEP = "TRUE" *) output rx_rst ); // TODO: 需要检查综合后电路是否会被优化 // BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化 // ******** Wire & Reg ******** - reg flag_is_tx_slot; + reg flag_is_tx_slot; // ******** Assingment ******** // ******** Logic Block ******** - generate - if (SLOT_LEN <= 65535) begin // slot len is small - reg [15:0] cnt; - always @(posedge clk) begin - if (rst) begin - cnt <= 16'd0; - end - else begin - if (!flag_is_master && flag_frame_sync) begin - // slave update cnt - cnt <= TIC_FRAME_SYNC; - end - else if (cnt >= SLOT_LEN - 1) begin - cnt <= 16'd0; - end - else begin - cnt <= cnt + 16'd1; - end - end - end - assign tx_start = flag_is_tx_slot & (cnt == 16'd10); // just a num for avoiding the zero,(cnt is also 0 in rst state) - assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN); - always @(posedge clk) begin - if (rst) begin - flag_is_tx_slot <= 0; - end - else if (!flag_is_master && flag_frame_sync) begin - flag_is_tx_slot <= 0; - end - else if (cnt == 16'd1) begin - flag_is_tx_slot <= ~flag_is_tx_slot; - end - end + reg [23:0] cnt; + always @(posedge clk) begin + if (rst) begin + cnt <= 0; end else begin - reg [15:0] cnt_l; - reg [ 7:0] cnt_h; - always @(posedge clk) begin - if (rst) begin - cnt_l <= 16'd0; - cnt_h <= 8'd0; + if (!flag_is_master && flag_frame_sync) begin + // slave update cnt + cnt <= TIC_FRAME_SYNC; + end + else begin + // master + if (cnt < SLOT_LEN) begin + cnt <= cnt + 1; end else begin - if (!flag_is_master && flag_frame_sync) begin - // slave update cnt - {cnt_h, cnt_l} <= TIC_FRAME_SYNC; - end - else begin - // master - if ({cnt_h, cnt_l} >= SLOT_LEN) begin - cnt_h <= 8'd0; - cnt_l <= 16'd0; - end - else begin - {cnt_h, cnt_l} <= {cnt_h, cnt_l} + 24'd1; - end - end - end - end - assign tx_start = flag_is_tx_slot & ({cnt_h, cnt_l} == 16'd10); - assign intr_2ps = ~flag_is_tx_slot & ({cnt_h, cnt_l} == TIC_TO_PS_LEN); - - always @(posedge clk) begin - if (rst) begin - flag_is_tx_slot <= 0; - end - else if (!flag_is_master && flag_frame_sync) begin - flag_is_tx_slot <= 0; - end - else if ({cnt_h, cnt_l} == 16'd1) begin - flag_is_tx_slot <= ~flag_is_tx_slot; + cnt <= 0; end end end - endgenerate + end + assign tx_start = flag_is_tx_slot & (cnt == 16'd10); + assign rx_rst = flag_is_tx_slot | (~flag_is_tx_slot & (cnt <= 16'd10)); + assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN); + + always @(posedge clk) begin + if (rst) begin + flag_is_tx_slot <= 0; + end + else if (!flag_is_master && flag_frame_sync) begin + flag_is_tx_slot <= 0; + end + else if (cnt == 16'd1) begin + flag_is_tx_slot <= ~flag_is_tx_slot; + end + end + // ******** Inst ********