diff --git a/hdl/system_top.v b/hdl/system_top.v
index 1b1928a..34a013c 100644
--- a/hdl/system_top.v
+++ b/hdl/system_top.v
@@ -156,6 +156,9 @@ module system_top (
     wire        intr_2ps;
     wire [ 7:0] max_slot_num;
 
+    reg  [15:0] cnt_pulse_wider_tx_start = 0;
+    reg  [15:0] cnt_pulse_wider_frame_sync = 0;
+
     // ******** Assingment  ********
 
     assign ad9361_tx_clk    = clk_1x;
@@ -174,14 +177,40 @@ module system_top (
     // gpio  rf control
     assign rf_gpio[0]       = rf_io0_d3_18db;
     assign rf_gpio[1]       = rf_io1_d4_12db;
-    assign rf_gpio[2]       = rf_io2_trx;
-    assign rf_gpio[3]       = rf_io3_d1_12db;
+    // assign rf_gpio[2]       = rf_io2_trx;
+    // assign rf_gpio[3]       = rf_io3_d1_12db;
     assign rf_gpio[4]       = rf_io4_d2_6db;
     assign rf_gpio[5]       = 0;
+    // temporary for test gpio
+    assign rf_gpio[2]       = (cnt_pulse_wider_tx_start != 0);
+    assign rf_gpio[3]       = (cnt_pulse_wider_frame_sync != 0);
 
 
     // ******** Logic Block ********
 
+    always @(posedge clk_1x) begin
+        if (tx_start) begin
+            cnt_pulse_wider_tx_start <= 1;
+        end
+        else if (cnt_pulse_wider_tx_start > 0) begin
+            cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start + 1;
+        end
+        else begin
+            cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start;
+        end
+    end
+    always @(posedge clk_2x) begin
+        if (rx_data_src_fifo_tlast) begin
+            cnt_pulse_wider_frame_sync <= 1;
+        end
+        else if (cnt_pulse_wider_frame_sync > 0) begin
+            cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync + 1;
+        end
+        else begin
+            cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync;
+        end
+    end
+
     // ********    Inst     ********
 
     clk_wiz_poweron u_clk_wiz_poweron (
@@ -392,13 +421,13 @@ module system_top (
     //     .probe1(ad9361_tx_data_q)   // input wire [11:0]  probe1
     // );
 
-    vio_rf u_vio_rf (
-        .clk       (clk_poweron),
-        .probe_out0(rf_io2_trx),
-        .probe_out1(rf_io3_d1_12db),
-        .probe_out2(rf_io4_d2_6db),
-        .probe_out3(rf_io0_d3_18db),
-        .probe_out4(rf_io1_d4_12db)
-    );
+    // vio_rf u_vio_rf (
+    //     .clk       (clk_poweron),
+    //     .probe_out0(rf_io2_trx),
+    //     .probe_out1(rf_io3_d1_12db),
+    //     .probe_out2(rf_io4_d2_6db),
+    //     .probe_out3(rf_io0_d3_18db),
+    //     .probe_out4(rf_io1_d4_12db)
+    // );
 
 endmodule