diff --git a/contraint/mm7020_timing.xdc b/contraint/mm7020_timing.xdc index 892e7bc..0fb4931 100644 --- a/contraint/mm7020_timing.xdc +++ b/contraint/mm7020_timing.xdc @@ -1,4 +1,11 @@ set_property MAX_FANOUT 512 [get_nets *u_RecvTop/mag*] # set_property MAX_FANOUT 512 [get_nets u_Receiver/mag_valid] # set_false_path -through [get_nets u_Receiver/rst] -# set_false_path -through [get_nets u_RecvTop/SR[0]] \ No newline at end of file +# set_false_path -through [get_nets u_RecvTop/SR[0]] +set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_rst] +set_false_path -through [get_nets phy_tx_test_flag] +set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_tx_iq_reverse] +set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_rx_iq_reverse] +set_false_path -through [get_nets tdma_flag_is_master] +set_false_path -through [get_nets tdma_slot_len*] +set_false_path -through [get_nets tdma_tic_2_ps*] diff --git a/hdl/phy_control.v b/hdl/phy_control.v index 54780fe..70620b1 100644 --- a/hdl/phy_control.v +++ b/hdl/phy_control.v @@ -63,8 +63,16 @@ module phy_control #( // resetn (should synchronised with "clk") input rstn, // can be floating if ASYNC_CLK == 0 - output wire phy_rst, - output wire phy_tx_test_flag + // control sigal + output wire phy_rst, + output wire phy_tx_test_flag, + output wire phy_tx_iq_reverse, + output wire phy_rx_iq_reverse, + // tdma parameters + output wire tdma_flag_is_master, + output wire [31:0] tdma_slot_len, + output wire [31:0] tdma_tic_2_ps + //--- ADD YOUR OWN PORTS END ); @@ -329,10 +337,14 @@ module phy_control #( localparam integer PHY_CR = 'h00000000 >> 2; // RW localparam integer PHY_SR = 'h00000004 >> 2; // RW + localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2; + localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2; // Register definitions reg [31:0] phy_cr_reg = 32'h0; reg [31:0] phy_sr_reg = 32'h0; + reg [31:0] tdma_slot_len_reg = 32'h0; + reg [31:0] tdma_tic_2_ps_reg = 32'h0; // Register Reading always @(posedge local_clk) begin @@ -355,20 +367,26 @@ module phy_control #( case (up_waddr_s) PHY_CR: phy_cr_reg <= up_wdata_s; PHY_SR: phy_sr_reg <= up_wdata_s; + TDMA_SLOT_LEN: tdma_slot_len_reg <= up_wdata_s; + TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s; endcase end else begin - // self logic + // self logic end end end // control reg definition - assign phy_rst = ~phy_cr_reg[0]; - assign phy_tx_test_flag = phy_cr_reg[1]; - - + assign phy_rst = ~phy_cr_reg[0]; + assign phy_tx_test_flag = phy_cr_reg[1]; + assign phy_tx_iq_reverse = phy_cr_reg[2]; + assign phy_rx_iq_reverse = phy_cr_reg[3]; + assign tdma_flag_is_master = phy_cr_reg[4]; + // tdma + assign tdma_slot_len = tdma_slot_len_reg; + assign tdma_tic_2_ps = tdma_tic_2_ps_reg; //--- ADD YOUR OWN LOGIC END diff --git a/hdl/system_top.v b/hdl/system_top.v index df66262..8e46440 100644 --- a/hdl/system_top.v +++ b/hdl/system_top.v @@ -109,10 +109,14 @@ module system_top ( // phy control signal wire phy_rst_vio; - wire phy_rst_ps; wire phy_rst; wire phy_tx_test_flag_vio; wire phy_tx_test_flag; + wire phy_tx_iq_reverse; + wire phy_rx_iq_reverse; + wire tdma_flag_is_master; + wire [31:0] tdma_slot_len; + wire [31:0] tdma_tic_2_ps; // tx signal wire frame_sync_pulse; @@ -143,10 +147,10 @@ module system_top ( assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx - assign ad9361_tx_data_i = bb_tx_iq_reverse ? bb_tx_q : bb_tx_i; - assign ad9361_tx_data_q = bb_tx_iq_reverse ? bb_tx_i : bb_tx_q; - assign bb_rx_i = bb_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i; - assign bb_rx_q = bb_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q; + assign ad9361_tx_data_i = phy_tx_iq_reverse ? bb_tx_q : bb_tx_i; + assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q; + assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i; + assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q; // ******** Logic Block ******** @@ -174,73 +178,74 @@ module system_top ( ); MM7020_BD_wrapper u_MM7020_BD_wrapper ( - .ad9361_spi_clk (ad9361_spi_clk), - .ad9361_spi_csn (ad9361_spi_csn), - .ad9361_spi_miso (ad9361_spi_miso), - .ad9361_spi_mosi (ad9361_spi_mosi), - .clk_ps (clk_poweron), - .rst_ps (rst_sys), + .ad9361_spi_clk (ad9361_spi_clk), + .ad9361_spi_csn (ad9361_spi_csn), + .ad9361_spi_miso (ad9361_spi_miso), + .ad9361_spi_mosi (ad9361_spi_mosi), + .clk_ps (clk_poweron), + .rst_ps (rst_sys), // ddr - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), // fixed io - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), // gpio ps - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), // intr pl to ps - .pl2ps_intr2 (intr_2ps), - .pl2ps_intr3 (flag_mgc_done_pulse), + .pl2ps_intr2 (intr_2ps), + .pl2ps_intr3 (flag_mgc_done_pulse), // tx fifo - .tx_data_src_count (tx_data_src_count), - .tx_data_src_tdata (tx_data_src_tdata), - .tx_data_src_tready(tx_data_src_tready), - .tx_data_src_tvalid(tx_data_src_tvalid), + .tx_data_src_count (tx_data_src_count), + .tx_data_src_tdata (tx_data_src_tdata), + .tx_data_src_tready (tx_data_src_tready), + .tx_data_src_tvalid (tx_data_src_tvalid), //phy control signal - .phy_rst (phy_rst_ps), - .phy_tx_test_flag (phy_tx_test_flag), + .phy_rst (phy_rst), + .phy_tx_test_flag (phy_tx_test_flag), + .phy_tx_iq_reverse (phy_tx_iq_reverse), + .phy_rx_iq_reverse (phy_rx_iq_reverse), + .tdma_flag_is_master(tdma_flag_is_master), + .tdma_slot_len (tdma_slot_len), + .tdma_tic_2_ps (tdma_tic_2_ps), // uart - .uart_rx (uart_rx), - .uart_tx (uart_tx) + .uart_rx (uart_rx), + .uart_tx (uart_tx) ); - - tdma #( - .SLOT_LEN (750000), // 50MHz--> 15ms - .TIC_TO_PS_LEN (700000), - .TIC_FRAME_SYNC(42344) - // .SLOT_LEN (625001), // 50MHz--> 15ms - // .TIC_TO_PS_LEN (575000), - // .TIC_FRAME_SYNC(42344) - ) u_tdma ( + tdma u_tdma ( .clk (clk_1x), .rst (rst_sys), - .flag_is_master (flag_is_master), + .flag_is_master (tdma_flag_is_master), .flag_frame_sync(frame_sync_pulse), + .tdma_slot_len (tdma_slot_len[23:0]), + .tdma_tic_2_ps (tdma_tic_2_ps[23:0]), .intr_2ps (intr_2ps), .tx_start (tx_start), .rx_rst (rx_rst) ); + + // net_city u_net_city ( // .clk (clk_1x), // .rst_initial (rst_sys), @@ -270,7 +275,7 @@ module system_top ( enc_control u_enc_control ( .clk (clk_poweron), - .rst (rst_sys | phy_rst_ps), + .rst (rst_sys | phy_rst), .s_axis_fifo_tvalid (tx_data_src_tvalid), .s_axis_fifo_tready (tx_data_src_tready), .s_axis_fifo_tdata (tx_data_src_tdata), @@ -296,7 +301,7 @@ module system_top ( .hopping_freq (), .ad9361_tx_data_i (bb_tx_i), .ad9361_tx_data_q (bb_tx_q), - .test (tx_test_flag | phy_tx_test_flag_vio), + .test (phy_tx_test_flag), .hop_wait (100) ); @@ -349,28 +354,6 @@ module system_top ( // ******** CDC ******** - xpm_cdc_single #( - .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 - .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values - .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages - .SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input - ) xpm_cdc_single_tx_test_flag_ps_inst ( - .dest_out(tx_test_flag), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered. - .dest_clk(clk_1x), // 1-bit input: Clock signal for the destination clock domain. - .src_clk (clk_poweron), // 1-bit input: optional; required when SRC_INPUT_REG = 1 - .src_in (phy_tx_test_flag) // 1-bit input: Input signal to be synchronized to dest_clk domain. - ); - - xpm_cdc_sync_rst #( - .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 - .INIT (1), // DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization registers to 1 - .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values - .SIM_ASSERT_CHK(0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages - ) xpm_cdc_sync_rst_phy_rst_inst ( - .dest_rst(phy_rst), // 1-bit output: src_rst synchronized to the destination clock domain. This output is registered. - .dest_clk(clk_1x), // 1-bit input: Destination clock. - .src_rst (phy_rst_ps) // 1-bit input: Source reset signal. - ); // ******** Debug ******** @@ -399,13 +382,4 @@ module system_top ( end - - vio_phy_control u_vio_phy_control ( - .clk (clk_1x), // input wire clk - .probe_out0(flag_is_master), // output wire [0 : 0] - .probe_out1(bb_tx_iq_reverse), // output wire [0 : 0] - .probe_out2(bb_rx_iq_reverse) // output wire [0 : 0] - ); - - endmodule diff --git a/hdl/tdma.v b/hdl/tdma.v index 28d03e5..4470f23 100644 --- a/hdl/tdma.v +++ b/hdl/tdma.v @@ -14,17 +14,17 @@ // ! PLEASE MAKE SURE THE PARAMETER ARE VALID // ! WHEN U INSTANTIATE THIS MODULE module tdma #( - parameter SLOT_LEN = 750000, - parameter TIC_TO_PS_LEN = 700000, parameter TIC_FRAME_SYNC = 42344 ) ( - input clk, - input rst, - input flag_is_master, // TODO: refactor it to parameters - input flag_frame_sync, - output intr_2ps, - output tx_start, - output reg rx_rst + input clk, + input rst, + input flag_is_master, + input flag_frame_sync, + input wire [23:0] tdma_slot_len, + input wire [23:0] tdma_tic_2_ps, + output intr_2ps, + output tx_start, + output reg rx_rst ); // TODO: 需要检查综合后电路是否会被优化 @@ -38,7 +38,7 @@ module tdma #( // ******** Assingment ******** assign tx_start = flag_is_master & (cnt == 16'd10); - assign intr_2ps = flag_is_master & (cnt == TIC_TO_PS_LEN - 1); + assign intr_2ps = flag_is_master & (cnt == tdma_tic_2_ps - 1); // ******** Logic Block ******** @@ -55,7 +55,7 @@ module tdma #( end else begin // master - if (cnt < SLOT_LEN - 1) begin + if (cnt < tdma_slot_len - 1) begin cnt <= cnt + 1; end else begin @@ -75,22 +75,6 @@ module tdma #( end end - // always @(posedge clk) begin - // if (rst) begin - // flag_is_tx_slot <= 0; - // end - // else if (!flag_is_master && flag_frame_sync) begin - // flag_is_tx_slot <= 0; - // end - // else if (cnt == 16'd1) begin - // flag_is_tx_slot <= ~flag_is_tx_slot; - // end - // end - - - - - // ******** Inst ******** // ******** Debug ********