From d210233e74bd3614cc28ec2dd5f9ec456515c72e Mon Sep 17 00:00:00 2001 From: ZoroGH Date: Mon, 22 Jul 2024 15:01:48 +0800 Subject: [PATCH] reivew --- .tags | 10567 ++++++++++++++++++++++++++++++++++++++++++++++++ hdl/RecvTop.v | 8 +- 2 files changed, 10571 insertions(+), 4 deletions(-) create mode 100644 .tags diff --git a/.tags b/.tags new file mode 100644 index 0000000..aaefb5b --- /dev/null +++ b/.tags @@ -0,0 +1,10567 @@ +!_TAG_EXTRA_DESCRIPTION anonymous /Include tags for non-named objects like lambda/ +!_TAG_EXTRA_DESCRIPTION fileScope /Include tags of file scope/ +!_TAG_EXTRA_DESCRIPTION pseudo /Include pseudo tags/ +!_TAG_EXTRA_DESCRIPTION subparser /Include tags generated by subparsers/ +!_TAG_FIELD_DESCRIPTION epoch /the last modified time of the input file (only for F\/file kind tag)/ +!_TAG_FIELD_DESCRIPTION file /File-restricted scoping/ +!_TAG_FIELD_DESCRIPTION input /input file/ +!_TAG_FIELD_DESCRIPTION name /tag name/ +!_TAG_FIELD_DESCRIPTION pattern /pattern/ +!_TAG_FIELD_DESCRIPTION typeref /Type and name of a variable or typedef/ +!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ +!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ +!_TAG_KIND_DESCRIPTION!Verilog b,block /blocks (begin, fork)/ +!_TAG_KIND_DESCRIPTION!Verilog c,constant /constants (parameter, specparam)/ +!_TAG_KIND_DESCRIPTION!Verilog d,define /text macros/ +!_TAG_KIND_DESCRIPTION!Verilog e,event /events/ +!_TAG_KIND_DESCRIPTION!Verilog f,function /functions/ +!_TAG_KIND_DESCRIPTION!Verilog i,instance /instances of module/ +!_TAG_KIND_DESCRIPTION!Verilog m,module /modules/ +!_TAG_KIND_DESCRIPTION!Verilog n,net /net data types/ +!_TAG_KIND_DESCRIPTION!Verilog p,port /ports/ +!_TAG_KIND_DESCRIPTION!Verilog r,register /variable data types/ +!_TAG_KIND_DESCRIPTION!Verilog t,task /tasks/ +!_TAG_OUTPUT_EXCMD mixed /number, pattern, mixed, or combineV2/ +!_TAG_OUTPUT_FILESEP slash /slash or backslash/ +!_TAG_OUTPUT_MODE u-ctags /u-ctags or e-ctags/ +!_TAG_OUTPUT_VERSION 0.0 /current.age/ +!_TAG_PARSER_VERSION!Verilog 1.1 /current.age/ +!_TAG_PATTERN_LENGTH_LIMIT 96 /0 for no limit/ +!_TAG_PROC_CWD C:/Users/ZoroGH/dev/vivadoPrj/MM7020/source/ // +!_TAG_PROGRAM_AUTHOR Universal Ctags Team // +!_TAG_PROGRAM_NAME Universal Ctags /Derived from Exuberant Ctags/ +!_TAG_PROGRAM_URL https://ctags.io/ /official site/ +!_TAG_PROGRAM_VERSION 6.1.0 /v6.1.0/ +!_TAG_ROLE_DESCRIPTION!Verilog!module decl /declaring instances/ +A adi_library/common/ad_addsub.v /^ input [(A_DATA_WIDTH-1):0] A,$/;" p module:ad_addsub +ACCEPTANCE adi_library/axi_dmac/tb/axi_slave.v /^ parameter ACCEPTANCE = 3,$/;" c module:axi_slave +ACQUIRE adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ localparam ACQUIRE = 2'b10;$/;" c module:mdc_mdio +ADC_ADDRESS_WIDTH adi_library/util_adcfifo/util_adcfifo.v /^ localparam ADC_ADDRESS_WIDTH = DMA_ADDRESS_WIDTH - ADDRESS_PADDING_WIDTH;$/;" c module:util_adcfifo +ADC_ADDR_LIMIT adi_library/util_adcfifo/util_adcfifo.v /^ localparam ADC_ADDR_LIMIT = (2**ADC_ADDRESS_WIDTH)-1;$/;" c module:util_adcfifo +ADC_DATA_WIDTH adi_library/util_adcfifo/util_adcfifo.v /^ parameter ADC_DATA_WIDTH = 256,$/;" c module:util_adcfifo +ADC_DATA_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ parameter ADC_DATA_WIDTH = 128,$/;" c module:axi_adcfifo +ADC_DATA_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ parameter ADC_DATA_WIDTH = 128,$/;" c module:axi_adcfifo_adc +ADC_MEM_RATIO adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ localparam ADC_MEM_RATIO = AXI_DATA_WIDTH\/ADC_DATA_WIDTH;$/;" c module:axi_adcfifo_adc +ADDER adi_library/common/ad_addsub.v /^ localparam ADDER = 1;$/;" c module:ad_addsub +ADDRESS_PADDING_WIDTH adi_library/util_adcfifo/util_adcfifo.v /^ localparam ADDRESS_PADDING_WIDTH = (DMA_MEM_RATIO == 1) ? 0 :$/;" c module:util_adcfifo +ADDRESS_WIDTH adi_library/common/ad_mem.v /^ parameter ADDRESS_WIDTH = 5) ($/;" c module:ad_mem +ADDRESS_WIDTH adi_library/util_axis_fifo/address_gray.v /^ parameter ADDRESS_WIDTH = 4$/;" c module:fifo_address_gray +ADDRESS_WIDTH adi_library/util_axis_fifo/address_gray_pipelined.v /^ parameter ADDRESS_WIDTH = 4$/;" c module:fifo_address_gray_pipelined +ADDRESS_WIDTH adi_library/util_axis_fifo/address_sync.v /^ parameter ADDRESS_WIDTH = 4$/;" c module:fifo_address_sync +ADDRESS_WIDTH adi_library/util_axis_fifo/util_axis_fifo.v /^ parameter ADDRESS_WIDTH = 4,$/;" c module:util_axis_fifo +ADDRESS_WIDTH adi_library/util_dacfifo/util_dacfifo.v /^ parameter ADDRESS_WIDTH = 6,$/;" c module:util_dacfifo +ADDRESS_WIDTH adi_library/util_mfifo/util_mfifo.v /^ parameter ADDRESS_WIDTH = 8) ($/;" c module:util_mfifo +ADDRESS_WIDTH adi_library/util_rfifo/util_rfifo.v /^ localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 5) ? DIN_ADDRESS_WIDTH : 5;$/;" c module:util_rfifo +ADDRESS_WIDTH adi_library/util_var_fifo/util_var_fifo.v /^ parameter ADDRESS_WIDTH = 13) ($/;" c module:util_var_fifo +ADDRESS_WIDTH adi_library/util_wfifo/util_wfifo.v /^ localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 4) ? DIN_ADDRESS_WIDTH : 4;$/;" c module:util_wfifo +ADDRESS_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ parameter ADDRESS_WIDTH = 4,$/;" c module:axi_dacfifo_address_buffer +ADDRESS_WIDTH_DEST adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam ADDRESS_WIDTH_DEST = BURST_LEN_WIDTH_DEST + ID_WIDTH - 1;$/;" c module:axi_dmac_burst_memory +ADDRESS_WIDTH_SRC adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam ADDRESS_WIDTH_SRC = BURST_LEN_WIDTH_SRC + ID_WIDTH - 1;$/;" c module:axi_dmac_burst_memory +ADDR_MASK adi_library/axi_dmac/tb/regmap_tb.v /^ localparam ADDR_MASK = {{DMA_AXI_ADDR_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};$/;" c module:dmac_regmap_tb +ADD_OR_SUB_N adi_library/common/ad_addsub.v /^ parameter ADD_OR_SUB_N = 0) ($/;" c module:ad_addsub +AGC_HEADER_LEN hdl/Transmitter.v /^ parameter AGC_HEADER_LEN = 2130,$/;" c module:Transmitter +ALLOW_ABORT adi_library/axi_dmac/data_mover.v /^ parameter ALLOW_ABORT = 0) ($/;" c module:dmac_data_mover +ALLOW_ASYM_MEM adi_library/axi_dmac/axi_dmac.v /^ parameter ALLOW_ASYM_MEM = 0$/;" c module:axi_dmac +ALLOW_ASYM_MEM adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter ALLOW_ASYM_MEM = 0$/;" c module:axi_dmac_burst_memory +ALLOW_ASYM_MEM adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter ALLOW_ASYM_MEM = 0$/;" c module:axi_dmac_transfer +ALLOW_ASYM_MEM adi_library/axi_dmac/request_arb.v /^ parameter ALLOW_ASYM_MEM = 0$/;" c module:dmac_request_arb +ALLOW_ZERO_MASKING adi_library/common/ad_pnmon.v /^ parameter ALLOW_ZERO_MASKING = 0) ($/;" c module:ad_pnmon +ANY_EDGE adi_library/common/ad_edge_detect.v /^ localparam ANY_EDGE = 2;$/;" c module:ad_edge_detect +APROX_DW_GAIN_ERR adi_library/common/ad_dds_sine_cordic.v /^ localparam APROX_DW_GAIN_ERR = (CORDIC_DW < 21) ? 4 :$/;" c module:ad_dds_sine_cordic +ASYNC_CLK adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter ASYNC_CLK = 1,$/;" c module:axi_dmac_burst_memory +ASYNC_CLK adi_library/util_axis_fifo/util_axis_fifo.v /^ parameter ASYNC_CLK = 1,$/;" c module:util_axis_fifo +ASYNC_CLK adi_library/util_cdc/sync_bits.v /^ parameter ASYNC_CLK = 1)($/;" c module:sync_bits +ASYNC_CLK adi_library/util_cdc/sync_data.v /^ parameter ASYNC_CLK = 1$/;" c module:sync_data +ASYNC_CLK adi_library/util_cdc/sync_event.v /^ parameter ASYNC_CLK = 1$/;" c module:sync_event +ASYNC_CLK adi_library/util_cdc/sync_gray.v /^ parameter ASYNC_CLK = 1)($/;" c module:sync_gray +ASYNC_CLK hdl/phy_control.v /^ parameter ASYNC_CLK = 1,$/;" c module:phy_control +ASYNC_CLK_DEST_REQ adi_library/axi_dmac/axi_dmac.v /^ parameter ASYNC_CLK_DEST_REQ = 1,$/;" c module:axi_dmac +ASYNC_CLK_DEST_REQ adi_library/axi_dmac/axi_dmac_reset_manager.v /^ parameter ASYNC_CLK_DEST_REQ = 1$/;" c module:axi_dmac_reset_manager +ASYNC_CLK_DEST_REQ adi_library/axi_dmac/axi_dmac_response_manager.v /^ parameter ASYNC_CLK_DEST_REQ = 1$/;" c module:axi_dmac_response_manager +ASYNC_CLK_DEST_REQ adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter ASYNC_CLK_DEST_REQ = 1,$/;" c module:axi_dmac_transfer +ASYNC_CLK_DEST_REQ adi_library/axi_dmac/request_arb.v /^ parameter ASYNC_CLK_DEST_REQ = 1,$/;" c module:dmac_request_arb +ASYNC_CLK_REQ_SRC adi_library/axi_dmac/axi_dmac.v /^ parameter ASYNC_CLK_REQ_SRC = 1,$/;" c module:axi_dmac +ASYNC_CLK_REQ_SRC adi_library/axi_dmac/axi_dmac_reset_manager.v /^ parameter ASYNC_CLK_REQ_SRC = 1,$/;" c module:axi_dmac_reset_manager +ASYNC_CLK_REQ_SRC adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter ASYNC_CLK_REQ_SRC = 1,$/;" c module:axi_dmac_transfer +ASYNC_CLK_REQ_SRC adi_library/axi_dmac/request_arb.v /^ parameter ASYNC_CLK_REQ_SRC = 1,$/;" c module:dmac_request_arb +ASYNC_CLK_SRC_DEST adi_library/axi_dmac/axi_dmac.v /^ parameter ASYNC_CLK_SRC_DEST = 1,$/;" c module:axi_dmac +ASYNC_CLK_SRC_DEST adi_library/axi_dmac/axi_dmac_reset_manager.v /^ parameter ASYNC_CLK_SRC_DEST = 1,$/;" c module:axi_dmac_reset_manager +ASYNC_CLK_SRC_DEST adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter ASYNC_CLK_SRC_DEST = 1,$/;" c module:axi_dmac_transfer +ASYNC_CLK_SRC_DEST adi_library/axi_dmac/request_arb.v /^ parameter ASYNC_CLK_SRC_DEST = 1,$/;" c module:dmac_request_arb +ASYNC_SPI_CLK adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter ASYNC_SPI_CLK = 0,$/;" c module:axi_spi_engine +ASYNC_SPI_CLK adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ parameter ASYNC_SPI_CLK = 0,$/;" c module:spi_engine_offload +ASYNC_TRIG adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ parameter ASYNC_TRIG = 0,$/;" c module:spi_engine_offload +AUX_FIFO_SIZE adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam AUX_FIFO_SIZE = 2**(ID_WIDTH-1);$/;" c module:axi_dmac_burst_memory +AW adi_library/axi_dmac/tb/regmap_tb.v /^ localparam AW = 12;$/;" c module:dmac_regmap_tb +AXI_ADDRESS adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ parameter AXI_ADDRESS = 32'h00000000,$/;" c module:axi_adcfifo +AXI_ADDRESS adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ parameter AXI_ADDRESS = 32'h00000000,$/;" c module:axi_adcfifo_rd +AXI_ADDRESS adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ parameter AXI_ADDRESS = 32'h00000000,$/;" c module:axi_adcfifo_wr +AXI_ADDRESS adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ parameter AXI_ADDRESS = 32'h00000000,$/;" c module:axi_dacfifo +AXI_ADDRESS adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ parameter AXI_ADDRESS = 32'h00000000,$/;" c module:axi_dacfifo_rd +AXI_ADDRESS adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ parameter AXI_ADDRESS = 32'h00000000,$/;" c module:axi_dacfifo_wr +AXI_ADDRESS_LIMIT adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ parameter AXI_ADDRESS_LIMIT = 32'hffffffff) ($/;" c module:axi_adcfifo +AXI_ADDRESS_LIMIT adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ parameter AXI_ADDRESS_LIMIT = 32'h00000000) ($/;" c module:axi_adcfifo_rd +AXI_ADDRESS_LIMIT adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ parameter AXI_ADDRESS_LIMIT = 32'h00000000) ($/;" c module:axi_adcfifo_wr +AXI_ADDRESS_LIMIT adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ parameter AXI_ADDRESS_LIMIT = 32'hffffffff) ($/;" c module:axi_dacfifo +AXI_ADDRESS_LIMIT adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ parameter AXI_ADDRESS_LIMIT = 32'h00000000,$/;" c module:axi_dacfifo_wr +AXI_ADDRESS_WIDTH adi_library/common/up_axi.v /^ parameter AXI_ADDRESS_WIDTH = 16) ($/;" c module:up_axi +AXI_ADDRESS_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ localparam AXI_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) :$/;" c module:axi_adcfifo_dma +AXI_ADDRESS_WIDTH hdl/phy_control.v /^ parameter AXI_ADDRESS_WIDTH = 5$/;" c module:phy_control +AXI_ADDRESS_WIDTH hdl/up_axi.v /^ parameter AXI_ADDRESS_WIDTH = 16$/;" c module:up_axi +AXI_ARINCR adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam AXI_ARINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH;$/;" c module:axi_dacfifo_rd +AXI_AWINCR adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;$/;" c module:axi_adcfifo_rd +AXI_AWINCR adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;$/;" c module:axi_adcfifo_wr +AXI_AWINCR adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH;$/;" c module:axi_dacfifo_wr +AXI_BIGGER adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam AXI_BIGGER = (MAX_WIDTH == AXI_DATA_WIDTH) ? 1 : 0;$/;" c module:axi_dacfifo_rd +AXI_BIGGER adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam AXI_BIGGER = (MAX_WIDTH == AXI_DATA_WIDTH) ? 1 : 0;$/;" c module:axi_dacfifo_wr +AXI_BUF_THRESHOLD_HI adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam AXI_BUF_THRESHOLD_HI = (AXI_BIGGER) ? (2 * (AXI_LENGTH+1)) : (2 * (AXI_LENGTH+1) */;" c module:axi_dacfifo_rd +AXI_BYTE_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH\/8;$/;" c module:axi_adcfifo_rd +AXI_BYTE_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH\/8;$/;" c module:axi_adcfifo_wr +AXI_BYTE_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH\/8;$/;" c module:axi_dacfifo_rd +AXI_BYTE_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH\/8;$/;" c module:axi_dacfifo_wr +AXI_DATA_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ parameter AXI_DATA_WIDTH = 512,$/;" c module:axi_adcfifo +AXI_DATA_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ parameter AXI_DATA_WIDTH = 512) ($/;" c module:axi_adcfifo_adc +AXI_DATA_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ parameter AXI_DATA_WIDTH = 512,$/;" c module:axi_adcfifo_dma +AXI_DATA_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ parameter AXI_DATA_WIDTH = 512,$/;" c module:axi_adcfifo_rd +AXI_DATA_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ parameter AXI_DATA_WIDTH = 512,$/;" c module:axi_adcfifo_wr +AXI_DATA_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ parameter AXI_DATA_WIDTH = 512,$/;" c module:axi_dacfifo +AXI_DATA_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ parameter AXI_DATA_WIDTH = 512,$/;" c module:axi_dacfifo_rd +AXI_DATA_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ parameter AXI_DATA_WIDTH = 512,$/;" c module:axi_dacfifo_wr +AXI_ID_WIDTH_DEST adi_library/axi_dmac/axi_dmac.v /^ parameter AXI_ID_WIDTH_DEST = 1,$/;" c module:axi_dmac +AXI_ID_WIDTH_SRC adi_library/axi_dmac/axi_dmac.v /^ parameter AXI_ID_WIDTH_SRC = 1,$/;" c module:axi_dmac +AXI_LENGTH adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ parameter AXI_LENGTH = 16,$/;" c module:axi_adcfifo +AXI_LENGTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ parameter AXI_LENGTH = 16,$/;" c module:axi_adcfifo_rd +AXI_LENGTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ parameter AXI_LENGTH = 16,$/;" c module:axi_adcfifo_wr +AXI_LENGTH adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ parameter AXI_LENGTH = 15,$/;" c module:axi_dacfifo +AXI_LENGTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ parameter AXI_LENGTH = 15,$/;" c module:axi_dacfifo_rd +AXI_LENGTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ parameter AXI_LENGTH = 15,$/;" c module:axi_dacfifo_wr +AXI_LENGTH_WIDTH adi_library/axi_dmac/dest_axi_mm.v /^ parameter AXI_LENGTH_WIDTH = 8)($/;" c module:dmac_dest_mm_axi +AXI_LENGTH_WIDTH adi_library/axi_dmac/src_axi_mm.v /^ parameter AXI_LENGTH_WIDTH = 8)($/;" c module:dmac_src_mm_axi +AXI_LENGTH_WIDTH_DEST adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter AXI_LENGTH_WIDTH_DEST = 8,$/;" c module:axi_dmac_transfer +AXI_LENGTH_WIDTH_DEST adi_library/axi_dmac/request_arb.v /^ parameter AXI_LENGTH_WIDTH_DEST = 8,$/;" c module:dmac_request_arb +AXI_LENGTH_WIDTH_SRC adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter AXI_LENGTH_WIDTH_SRC = 8,$/;" c module:axi_dmac_transfer +AXI_LENGTH_WIDTH_SRC adi_library/axi_dmac/request_arb.v /^ parameter AXI_LENGTH_WIDTH_SRC = 8,$/;" c module:dmac_request_arb +AXI_MEM_ADDRESS_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH :$/;" c module:axi_dacfifo_rd +AXI_MEM_ADDRESS_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH :$/;" c module:axi_dacfifo_wr +AXI_SIZE adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ parameter AXI_SIZE = 2,$/;" c module:axi_adcfifo +AXI_SIZE adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ parameter AXI_SIZE = 2,$/;" c module:axi_adcfifo_rd +AXI_SIZE adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ parameter AXI_SIZE = 2,$/;" c module:axi_adcfifo_wr +AXI_SIZE adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ parameter AXI_SIZE = 2,$/;" c module:axi_dacfifo +AXI_SIZE adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ parameter AXI_SIZE = 2,$/;" c module:axi_dacfifo_rd +AXI_SIZE adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ parameter AXI_SIZE = 6,$/;" c module:axi_dacfifo_wr +AXI_SLICE_DEST adi_library/axi_dmac/axi_dmac.v /^ parameter AXI_SLICE_DEST = 0,$/;" c module:axi_dmac +AXI_SLICE_DEST adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter AXI_SLICE_DEST = 0,$/;" c module:axi_dmac_transfer +AXI_SLICE_DEST adi_library/axi_dmac/request_arb.v /^ parameter AXI_SLICE_DEST = 0,$/;" c module:dmac_request_arb +AXI_SLICE_SRC adi_library/axi_dmac/axi_dmac.v /^ parameter AXI_SLICE_SRC = 0,$/;" c module:axi_dmac +AXI_SLICE_SRC adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter AXI_SLICE_SRC = 0,$/;" c module:axi_dmac_transfer +AXI_SLICE_SRC adi_library/axi_dmac/request_arb.v /^ parameter AXI_SLICE_SRC = 0,$/;" c module:dmac_request_arb +A_ADDRESS_WIDTH adi_library/common/ad_mem_asym.v /^ parameter A_ADDRESS_WIDTH = 8,$/;" c module:ad_mem_asym +A_DATA_WIDTH adi_library/common/ad_addsub.v /^ parameter A_DATA_WIDTH = 32,$/;" c module:ad_addsub +A_DATA_WIDTH adi_library/common/ad_mem_asym.v /^ parameter A_DATA_WIDTH = 256,$/;" c module:ad_mem_asym +A_DATA_WIDTH adi_library/xilinx/common/ad_mul.v /^ parameter A_DATA_WIDTH = 17,$/;" c module:ad_mul +A_TXDIFFCTRL adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] A_TXDIFFCTRL = 5'b10110,$/;" c module:util_adxcvr +A_TXDIFFCTRL adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] A_TXDIFFCTRL = 5'b10110,$/;" c module:util_adxcvr_xch +A_d adi_library/common/ad_addsub.v /^ reg [(A_DATA_WIDTH-1):0] A_d = 'b0;$/;" r module:ad_addsub +AbsIQ_max hdl/ApproxAbs_18bit.v /^ reg [17:0] AbsIQ_max;$/;" r module:ApproxAbs_18bit +AbsIQ_max hdl/ApproxAbs_v2.v /^ reg [9:0] AbsIQ_max;$/;" r module:ApproxAbs_v2 +AbsIQ_max_7by8 hdl/ApproxAbs_18bit.v /^ reg [17:0] AbsIQ_max_7by8;$/;" r module:ApproxAbs_18bit +AbsIQ_max_7by8 hdl/ApproxAbs_v2.v /^ reg [9:0] AbsIQ_max_7by8;$/;" r module:ApproxAbs_v2 +AbsIQ_min hdl/ApproxAbs_18bit.v /^ reg [17:0] AbsIQ_min;$/;" r module:ApproxAbs_18bit +AbsIQ_min hdl/ApproxAbs_v2.v /^ reg [9:0] AbsIQ_min;$/;" r module:ApproxAbs_v2 +AbsIQ_min_1by2 hdl/ApproxAbs_18bit.v /^ reg [17:0] AbsIQ_min_1by2;$/;" r module:ApproxAbs_18bit +AbsIQ_min_1by2 hdl/ApproxAbs_v2.v /^ reg [9:0] AbsIQ_min_1by2;$/;" r module:ApproxAbs_v2 +Abs_Din_I hdl/ApproxAbs_18bit.v /^ reg [17:0] Abs_Din_I;$/;" r module:ApproxAbs_18bit +Abs_Din_I hdl/ApproxAbs_v2.v /^ reg [9:0] Abs_Din_I;$/;" r module:ApproxAbs_v2 +Abs_Din_Q hdl/ApproxAbs_18bit.v /^ reg [17:0] Abs_Din_Q; $/;" r module:ApproxAbs_18bit +Abs_Din_Q hdl/ApproxAbs_v2.v /^ reg [9:0] Abs_Din_Q;$/;" r module:ApproxAbs_v2 +Amax adi_library/common/ad_addsub.v /^ input [(A_DATA_WIDTH-1):0] Amax,$/;" p module:ad_addsub +Amax_d adi_library/common/ad_addsub.v /^ reg [(A_DATA_WIDTH-1):0] Amax_d = 'b0;$/;" r module:ad_addsub +Amax_d2 adi_library/common/ad_addsub.v /^ reg [(A_DATA_WIDTH-1):0] Amax_d2 = 'b0;$/;" r module:ad_addsub +ApproxAbs_18bit hdl/ApproxAbs_18bit.v /^module ApproxAbs_18bit($/;" m +ApproxAbs_18bit hdl/Chn_Estimate.v /^ApproxAbs_18bit ApproxAbs_18bit ($/;" i module:Chn_Estimate typeref:module:ApproxAbs_18bit +ApproxAbs_rdy hdl/SCFDE_recv_FrameSync.v /^ wire ApproxAbs_rdy;$/;" n module:SCFDE_recv_FrameSync +ApproxAbs_v2 hdl/ApproxAbs_v2.v /^module ApproxAbs_v2 ($/;" m +ApproxAbs_v2_djy hdl/DAGC_v2.v /^ ApproxAbs_v2 ApproxAbs_v2_djy ($/;" i module:DAGC_v2 typeref:module:ApproxAbs_v2 +ApproxAbs_v2_tsync hdl/TSync_Abs_new4.v /^ ApproxAbs_v2 ApproxAbs_v2_tsync ($/;" i module:TSync_Abs_new4 typeref:module:ApproxAbs_v2 +ApproxAbs_v2_tsync1 hdl/TSync_Abs_new16.v /^ ApproxAbs_v2 ApproxAbs_v2_tsync1 ($/;" i module:TSync_Abs_new16 typeref:module:ApproxAbs_v2 +ApproxAbs_v2_tsync2 hdl/TSync_Abs_new16.v /^ ApproxAbs_v2 ApproxAbs_v2_tsync2 ($/;" i module:TSync_Abs_new16 typeref:module:ApproxAbs_v2 +ApproxAbs_v2_tsync3 hdl/TSync_Abs_new16.v /^ ApproxAbs_v2 ApproxAbs_v2_tsync3 ($/;" i module:TSync_Abs_new16 typeref:module:ApproxAbs_v2 +ApproxAbs_v2_tsync4 hdl/SCFDE_recv_FrameSync.v /^ ApproxAbs_v2_20bit ApproxAbs_v2_tsync4 ($/;" i module:SCFDE_recv_FrameSync typeref:module:ApproxAbs_v2_20bit +ApproxAbs_v2_tsync4 hdl/TSync_Abs_new16.v /^ ApproxAbs_v2 ApproxAbs_v2_tsync4 ($/;" i module:TSync_Abs_new16 typeref:module:ApproxAbs_v2 +BACKWARD_REGISTERED adi_library/axi_dmac/axi_register_slice.v /^ parameter BACKWARD_REGISTERED = 0)($/;" c module:axi_register_slice +BASE_ADDRESS adi_library/common/up_delay_cntrl.v /^ parameter BASE_ADDRESS = 6'h02) ($/;" c module:up_delay_cntrl +BASE_ADDRESS adi_library/common/up_tdd_cntrl.v /^ parameter BASE_ADDRESS = 6'h20$/;" c module:up_tdd_cntrl +BEATS_PER_BURST_LIMIT_DEST adi_library/axi_dmac/axi_dmac.v /^localparam BEATS_PER_BURST_LIMIT_DEST =$/;" c module:axi_dmac +BEATS_PER_BURST_LIMIT_SRC adi_library/axi_dmac/axi_dmac.v /^localparam BEATS_PER_BURST_LIMIT_SRC =$/;" c module:axi_dmac +BEATS_PER_BURST_WIDTH adi_library/axi_dmac/address_generator.v /^ parameter BEATS_PER_BURST_WIDTH = 4,$/;" c module:dmac_address_generator +BEATS_PER_BURST_WIDTH adi_library/axi_dmac/data_mover.v /^ parameter BEATS_PER_BURST_WIDTH = 4,$/;" c module:dmac_data_mover +BEATS_PER_BURST_WIDTH adi_library/axi_dmac/dest_axi_mm.v /^ parameter BEATS_PER_BURST_WIDTH = 4,$/;" c module:dmac_dest_mm_axi +BEATS_PER_BURST_WIDTH adi_library/axi_dmac/dest_axi_stream.v /^ parameter BEATS_PER_BURST_WIDTH = 4)($/;" c module:dmac_dest_axi_stream +BEATS_PER_BURST_WIDTH adi_library/axi_dmac/dest_fifo_inf.v /^ parameter BEATS_PER_BURST_WIDTH = 4)($/;" c module:dmac_dest_fifo_inf +BEATS_PER_BURST_WIDTH adi_library/axi_dmac/src_axi_mm.v /^ parameter BEATS_PER_BURST_WIDTH = 4,$/;" c module:dmac_src_mm_axi +BEATS_PER_BURST_WIDTH adi_library/axi_dmac/src_axi_stream.v /^ parameter BEATS_PER_BURST_WIDTH = 4)($/;" c module:dmac_src_axi_stream +BEATS_PER_BURST_WIDTH adi_library/axi_dmac/src_fifo_inf.v /^ parameter BEATS_PER_BURST_WIDTH = 4)($/;" c module:dmac_src_fifo_inf +BEATS_PER_BURST_WIDTH_DEST adi_library/axi_dmac/request_arb.v /^localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;$/;" c module:dmac_request_arb +BEATS_PER_BURST_WIDTH_SRC adi_library/axi_dmac/request_arb.v /^localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;$/;" c module:dmac_request_arb +BEAT_COUNTER_MAX adi_library/axi_dmac/data_mover.v /^localparam BEAT_COUNTER_MAX = {BEATS_PER_BURST_WIDTH{1'b1}};$/;" c module:dmac_data_mover +BIG_ENDIAN adi_library/util_axis_resize/util_axis_resize.v /^ parameter BIG_ENDIAN = 0)($/;" c module:util_axis_resize +BIT_COUNTER_CARRY adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1);$/;" c module:spi_engine_execution +BIT_COUNTER_CLEAR adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};$/;" c module:spi_engine_execution +BIT_COUNTER_WIDTH adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :$/;" c module:spi_engine_execution +BLOCK_NUM hdl/Transmitter.v /^ parameter BLOCK_NUM = 28,$/;" c module:Transmitter +BUFR_DIVIDE adi_library/xilinx/common/ad_serdes_clk.v /^ localparam BUFR_DIVIDE = (DDR_OR_SDR_N == 1'b1) ? SERDES_FACTOR \/ 2 : SERDES_FACTOR;$/;" c module:ad_serdes_clk +BUF_THRESHOLD_HI adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ localparam BUF_THRESHOLD_HI = 6'd60;$/;" c module:axi_adcfifo_rd +BUF_THRESHOLD_HI adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ localparam BUF_THRESHOLD_HI = 8'd250;$/;" c module:axi_adcfifo_wr +BUF_THRESHOLD_LO adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ localparam BUF_THRESHOLD_LO = 6'd3;$/;" c module:axi_adcfifo_rd +BUF_THRESHOLD_LO adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ localparam BUF_THRESHOLD_LO = 8'd6;$/;" c module:axi_adcfifo_wr +BURSTS_PER_TRANSFER_WIDTH adi_library/axi_dmac/request_arb.v /^localparam BURSTS_PER_TRANSFER_WIDTH = DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH;$/;" c module:dmac_request_arb +BURSTS_PER_TRANSFER_WIDTH adi_library/axi_dmac/request_generator.v /^ parameter BURSTS_PER_TRANSFER_WIDTH = 17)($/;" c module:dmac_request_generator +BURST_LEN adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam BURST_LEN = MAX_BYTES_PER_BURST \/ (DATA_WIDTH_MEM \/ 8);$/;" c module:axi_dmac_burst_memory +BURST_LEN_WIDTH adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam BURST_LEN_WIDTH = BURST_LEN > 128 ? 8 :$/;" c module:axi_dmac_burst_memory +BURST_LEN_WIDTH adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam BURST_LEN_WIDTH = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH;$/;" c module:axi_dmac_response_manager +BURST_LEN_WIDTH_DEST adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam BURST_LEN_WIDTH_DEST = BURST_LEN_WIDTH +$/;" c module:axi_dmac_burst_memory +BURST_LEN_WIDTH_SRC adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam BURST_LEN_WIDTH_SRC = BURST_LEN_WIDTH +$/;" c module:axi_dmac_burst_memory +BYTES_PER_BEAT adi_library/axi_dmac/tb/regmap_tb.v /^ localparam BYTES_PER_BEAT = 1;$/;" c module:dmac_regmap_tb +BYTES_PER_BEAT_WIDTH adi_library/axi_dmac/address_generator.v /^ parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH\/8),$/;" c module:dmac_address_generator +BYTES_PER_BEAT_WIDTH adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam BYTES_PER_BEAT_WIDTH = DEST_SRC_RATIO_WIDTH + BYTES_PER_BEAT_WIDTH_SRC;$/;" c module:axi_dmac_response_manager +BYTES_PER_BEAT_WIDTH adi_library/axi_dmac/dest_axi_mm.v /^ parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH\/8),$/;" c module:dmac_dest_mm_axi +BYTES_PER_BEAT_WIDTH adi_library/axi_dmac/src_axi_mm.v /^ parameter BYTES_PER_BEAT_WIDTH = 3,$/;" c module:dmac_src_mm_axi +BYTES_PER_BEAT_WIDTH_DEST adi_library/axi_dmac/2d_transfer.v /^ parameter BYTES_PER_BEAT_WIDTH_DEST = 3)($/;" c module:dmac_2d_transfer +BYTES_PER_BEAT_WIDTH_DEST adi_library/axi_dmac/axi_dmac.v /^localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 :$/;" c module:axi_dmac +BYTES_PER_BEAT_WIDTH_DEST adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam BYTES_PER_BEAT_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BURST_LEN_WIDTH_DEST;$/;" c module:axi_dmac_burst_memory +BYTES_PER_BEAT_WIDTH_DEST adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter BYTES_PER_BEAT_WIDTH_DEST = 1,$/;" c module:axi_dmac_regmap +BYTES_PER_BEAT_WIDTH_DEST adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter BYTES_PER_BEAT_WIDTH_DEST = 1,$/;" c module:axi_dmac_regmap_request +BYTES_PER_BEAT_WIDTH_DEST adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST\/8),$/;" c module:axi_dmac_transfer +BYTES_PER_BEAT_WIDTH_DEST adi_library/axi_dmac/request_arb.v /^ parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST\/8),$/;" c module:dmac_request_arb +BYTES_PER_BEAT_WIDTH_MEM adi_library/axi_dmac/axi_dmac_resize_src.v /^ parameter BYTES_PER_BEAT_WIDTH_MEM = 3$/;" c module:axi_dmac_resize_src +BYTES_PER_BEAT_WIDTH_MEM_SRC adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam BYTES_PER_BEAT_WIDTH_MEM_SRC = BYTES_PER_BURST_WIDTH - BURST_LEN_WIDTH_SRC;$/;" c module:axi_dmac_burst_memory +BYTES_PER_BEAT_WIDTH_SRC adi_library/axi_dmac/2d_transfer.v /^ parameter BYTES_PER_BEAT_WIDTH_SRC = 3,$/;" c module:dmac_2d_transfer +BYTES_PER_BEAT_WIDTH_SRC adi_library/axi_dmac/axi_dmac.v /^localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :$/;" c module:axi_dmac +BYTES_PER_BEAT_WIDTH_SRC adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DATA_WIDTH_SRC\/8),$/;" c module:axi_dmac_burst_memory +BYTES_PER_BEAT_WIDTH_SRC adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter BYTES_PER_BEAT_WIDTH_SRC = 1,$/;" c module:axi_dmac_regmap +BYTES_PER_BEAT_WIDTH_SRC adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter BYTES_PER_BEAT_WIDTH_SRC = 1,$/;" c module:axi_dmac_regmap_request +BYTES_PER_BEAT_WIDTH_SRC adi_library/axi_dmac/axi_dmac_resize_src.v /^ parameter BYTES_PER_BEAT_WIDTH_SRC = 3,$/;" c module:axi_dmac_resize_src +BYTES_PER_BEAT_WIDTH_SRC adi_library/axi_dmac/axi_dmac_response_manager.v /^ parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC\/8),$/;" c module:axi_dmac_response_manager +BYTES_PER_BEAT_WIDTH_SRC adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC\/8),$/;" c module:axi_dmac_transfer +BYTES_PER_BEAT_WIDTH_SRC adi_library/axi_dmac/request_arb.v /^ parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC\/8),$/;" c module:dmac_request_arb +BYTES_PER_BURST_LIMIT adi_library/axi_dmac/axi_dmac.v /^localparam BYTES_PER_BURST_LIMIT =$/;" c module:axi_dmac +BYTES_PER_BURST_LIMIT_DEST adi_library/axi_dmac/axi_dmac.v /^localparam BYTES_PER_BURST_LIMIT_DEST =$/;" c module:axi_dmac +BYTES_PER_BURST_LIMIT_SRC adi_library/axi_dmac/axi_dmac.v /^localparam BYTES_PER_BURST_LIMIT_SRC =$/;" c module:axi_dmac +BYTES_PER_BURST_WIDTH adi_library/axi_dmac/2d_transfer.v /^ parameter BYTES_PER_BURST_WIDTH = 7,$/;" c module:dmac_2d_transfer +BYTES_PER_BURST_WIDTH adi_library/axi_dmac/axi_dmac.v /^localparam BYTES_PER_BURST_WIDTH =$/;" c module:axi_dmac +BYTES_PER_BURST_WIDTH adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST),$/;" c module:axi_dmac_burst_memory +BYTES_PER_BURST_WIDTH adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter BYTES_PER_BURST_WIDTH = 7,$/;" c module:axi_dmac_regmap +BYTES_PER_BURST_WIDTH adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter BYTES_PER_BURST_WIDTH = 7,$/;" c module:axi_dmac_regmap_request +BYTES_PER_BURST_WIDTH adi_library/axi_dmac/axi_dmac_response_manager.v /^ parameter BYTES_PER_BURST_WIDTH = 7,$/;" c module:axi_dmac_response_manager +BYTES_PER_BURST_WIDTH adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter BYTES_PER_BURST_WIDTH = 7,$/;" c module:axi_dmac_transfer +BYTES_PER_BURST_WIDTH adi_library/axi_dmac/dest_axi_mm.v /^ parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST),$/;" c module:dmac_dest_mm_axi +BYTES_PER_BURST_WIDTH adi_library/axi_dmac/request_arb.v /^ parameter BYTES_PER_BURST_WIDTH = 7,$/;" c module:dmac_request_arb +B_ADDRESS_WIDTH adi_library/common/ad_mem_asym.v /^ parameter B_ADDRESS_WIDTH = 10,$/;" c module:ad_mem_asym +B_DATA_VALUE adi_library/common/ad_addsub.v /^ parameter B_DATA_VALUE = 32'h1,$/;" c module:ad_addsub +B_DATA_WIDTH adi_library/common/ad_mem_asym.v /^ parameter B_DATA_WIDTH = 64) ($/;" c module:ad_mem_asym +B_DATA_WIDTH adi_library/xilinx/common/ad_mul.v /^ parameter B_DATA_WIDTH = 17,$/;" c module:ad_mul +B_reg adi_library/common/ad_addsub.v /^ reg [(A_DATA_WIDTH-1):0] B_reg = B_DATA_VALUE;$/;" r module:ad_addsub +C1 adi_library/common/ad_csc.v /^ input signed [MUL_COEF_DW-1:0] C1,$/;" p module:ad_csc +C2 adi_library/common/ad_csc.v /^ input signed [MUL_COEF_DW-1:0] C2,$/;" p module:ad_csc +C3 adi_library/common/ad_csc.v /^ input signed [MUL_COEF_DW-1:0] C3,$/;" p module:ad_csc +C4 adi_library/common/ad_csc.v /^ input signed [SUM_COEF_DW-1:0] C4,$/;" p module:ad_csc +CCSDS_LDPC_DEC_K1024_R12_TOPP hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^module CCSDS_LDPC_DEC_K1024_R12_TOPP$/;" m +CCSDS_LDPC_ENC_R12 hdl/CCSDS_LDPC_ENC_R12.v /^module CCSDS_LDPC_ENC_R12($/;" m +CE adi_library/common/ad_addsub.v /^ input CE);$/;" p module:ad_addsub +CHANNEL_DATA_WIDTH adi_library/util_bsplit/util_bsplit.v /^ parameter CHANNEL_DATA_WIDTH = 1,$/;" c module:util_bsplit +CHANNEL_DATA_WIDTH adi_library/util_pack/util_cpack2/util_cpack2.v /^localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;$/;" c module:util_cpack2 +CHANNEL_DATA_WIDTH adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam CHANNEL_DATA_WIDTH = SAMPLES_PER_CHANNEL * SAMPLE_DATA_WIDTH;$/;" c module:pack_shell +CHANNEL_DATA_WIDTH adi_library/util_pack/util_upack2/util_upack2.v /^localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;$/;" c module:util_upack2 +CHANNEL_ID adi_library/common/up_adc_channel.v /^ parameter CHANNEL_ID = 4'h0,$/;" c module:up_adc_channel +CHANNEL_ID adi_library/common/up_dac_channel.v /^ parameter CHANNEL_ID = 4'h0,$/;" c module:up_dac_channel +CHU_SEQ_LEN hdl/Transmitter.v /^ parameter CHU_SEQ_LEN = 128,$/;" c module:Transmitter +CH_HSPMUX adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] CH_HSPMUX = 16'b0010010000100100,$/;" c module:util_adxcvr +CH_HSPMUX adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] CH_HSPMUX = 16'b0010010000100100,$/;" c module:util_adxcvr_xch +CLKIN_DS_OR_SE_N adi_library/xilinx/common/ad_serdes_clk.v /^ parameter CLKIN_DS_OR_SE_N = 1,$/;" c module:ad_serdes_clk +CLK_EDGE_SEL adi_library/common/up_dac_common.v /^ parameter [ 0:0] CLK_EDGE_SEL = 1'b0,$/;" c module:up_dac_common +CLK_PERIOD sim/tb_Receiver.v /^ localparam CLK_PERIOD = 20_0;$/;" c module:tb_Receiver +CLK_RATIO adi_library/common/ad_dds.v /^ parameter CLK_RATIO = 1) ($/;" c module:ad_dds +CMD_CHIPSELECT adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam CMD_CHIPSELECT = 2'b01;$/;" c module:spi_engine_execution +CMD_FIFO_ADDRESS_WIDTH adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter CMD_FIFO_ADDRESS_WIDTH = 4,$/;" c module:axi_spi_engine +CMD_MEM_ADDRESS_WIDTH adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ parameter CMD_MEM_ADDRESS_WIDTH = 4,$/;" c module:spi_engine_offload +CMD_MISC adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam CMD_MISC = 2'b11;$/;" c module:spi_engine_execution +CMD_TRANSFER adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam CMD_TRANSFER = 2'b00;$/;" c module:spi_engine_execution +CMD_WRITE adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam CMD_WRITE = 2'b10;$/;" c module:spi_engine_execution +CMOS_LVDS_N adi_library/xilinx/common/ad_serdes_in.v /^ parameter CMOS_LVDS_N = 0,$/;" c module:ad_serdes_in +CMOS_LVDS_N adi_library/xilinx/common/ad_serdes_out.v /^ parameter CMOS_LVDS_N = 0,$/;" c module:ad_serdes_out +CN1_half hdl/Interp_half.v /^ CN1_half CN1_half (.CLK(clk), .A(din_n1), .P(multquartern1)); $/;" i module:Interp_half typeref:module:CN1_half +CN1_quarter hdl/Interp_quarter.v /^ CN1 CN1_quarter (.CLK(clk), .A(din_t0), .P(multquartern1)); $/;" i module:Interp_quarter typeref:module:CN1 +CN2_quarter hdl/Interp_quarter.v /^ CN2 CN2_quarter (.CLK(clk), .A(din_p1), .P(multquartern2)); $/;" i module:Interp_quarter typeref:module:CN2 +CNT_ADJUST_TIMES_MAX hdl/power_measure.v /^ localparam CNT_ADJUST_TIMES_MAX = 25;$/;" c module:power_measure +CNT_AMP_TOO_HIGH_THRESHOLD hdl/power_measure.v /^ localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;$/;" c module:power_measure +CNT_IN_MAX hdl/enc_control.v /^ localparam CNT_IN_MAX = ENC_IN_LEN \/ INPUT_DATA_WIDTH;$/;" c module:enc_control +CNT_IN_MAX sim/tb_width_convert.v /^ localparam CNT_IN_MAX = 32;$/;" c module:tb_width_convert +CNT_IN_WIDTH hdl/enc_control.v /^ localparam CNT_IN_WIDTH = $clog2(CNT_IN_MAX);$/;" c module:enc_control +CNT_MAX hdl/width_convert.v /^ localparam CNT_MAX = INPUT_WIDTH \/ OUTPUT_WIDTH;$/;" c module:width_convert +CNT_MEASURING_MAX hdl/power_measure.v /^ localparam CNT_MEASURING_MAX = 512; \/\/ * 观察64个周期$/;" c module:power_measure +CNT_OUT_MAX hdl/enc_control.v /^ localparam CNT_OUT_MAX = ENC_OUT_LEN;$/;" c module:enc_control +CNT_OUT_WIDTH hdl/enc_control.v /^ localparam CNT_OUT_WIDTH = $clog2(CNT_OUT_MAX); \/\/ 多留1bit$/;" c module:enc_control +CNT_W adi_library/common/ad_pnmon.v /^ localparam CNT_W = $clog2(OOS_THRESHOLD);$/;" c module:ad_pnmon +CNT_WAIT_9361_MAX hdl/power_measure.v /^ localparam CNT_WAIT_9361_MAX = 80; \/\/* 等待周期数$/;" c module:power_measure +CNT_WIDTH hdl/add_prefix.v /^ localparam CNT_WIDTH = $clog2(DATA_LEN);$/;" c module:add_prefix +COMMON_ID adi_library/common/up_adc_channel.v /^ parameter COMMON_ID = 6'h01,$/;" c module:up_adc_channel +COMMON_ID adi_library/common/up_adc_common.v /^ parameter COMMON_ID = 6'h00,$/;" c module:up_adc_common +COMMON_ID adi_library/common/up_dac_channel.v /^ parameter COMMON_ID = 6'h11,$/;" c module:up_dac_channel +COMMON_ID adi_library/common/up_dac_common.v /^ parameter COMMON_ID = 6'h10,$/;" c module:up_dac_common +CONFIG adi_library/common/up_adc_common.v /^ parameter CONFIG = 0,$/;" c module:up_adc_common +CONFIG adi_library/common/up_dac_common.v /^ parameter CONFIG = 0,$/;" c module:up_dac_common +CONTROL_PATH_DELAY adi_library/common/ad_tdd_control.v /^ parameter integer CONTROL_PATH_DELAY = 0) ($/;" c module:ad_tdd_control +CORDIC adi_library/common/ad_dds_2.v /^ localparam CORDIC = 1;$/;" c module:ad_dds_2 +CORDIC_DW adi_library/common/ad_dds.v /^ parameter CORDIC_DW = 16,$/;" c module:ad_dds +CORDIC_DW adi_library/common/ad_dds_2.v /^ parameter CORDIC_DW = 16,$/;" c module:ad_dds_2 +CORDIC_DW adi_library/common/ad_dds_sine_cordic.v /^ parameter CORDIC_DW = 16,$/;" c module:ad_dds_sine_cordic +CORDIC_PHASE_DW adi_library/common/ad_dds.v /^ parameter CORDIC_PHASE_DW = 16,$/;" c module:ad_dds +CORDIC_PHASE_DW adi_library/common/ad_dds_2.v /^ parameter CORDIC_PHASE_DW = 16) ($/;" c module:ad_dds_2 +CP1_quarter hdl/Interp_quarter.v /^ CP1 CP1_quarter (.CLK(clk), .A(din_n2), .P(multquarterp1)); $/;" i module:Interp_quarter typeref:module:CP1 +CPLL_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] CPLL_CFG0 = 16'b0000000111111010,$/;" c module:util_adxcvr +CPLL_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] CPLL_CFG0 = 16'b0000000111111010,$/;" c module:util_adxcvr_xch +CPLL_CFG1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] CPLL_CFG1 = 16'b0000000000100011,$/;" c module:util_adxcvr +CPLL_CFG1 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] CPLL_CFG1 = 16'b0000000000100011,$/;" c module:util_adxcvr_xch +CPLL_CFG2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] CPLL_CFG2 = 16'b0000000000000010,$/;" c module:util_adxcvr +CPLL_CFG2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] CPLL_CFG2 = 16'b0000000000000010,$/;" c module:util_adxcvr_xch +CPLL_CFG3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] CPLL_CFG3 = 16'b0000000000000000,$/;" c module:util_adxcvr +CPLL_CFG3 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] CPLL_CFG3 = 16'b0000000000000000,$/;" c module:util_adxcvr_xch +CPLL_FBDIV adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ parameter CPLL_FBDIV = 1,$/;" c module:axi_xcvrlb +CPLL_FBDIV adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ parameter CPLL_FBDIV = 1,$/;" c module:axi_xcvrlb_1 +CPLL_FBDIV adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer CPLL_FBDIV = 2,$/;" c module:util_adxcvr +CPLL_FBDIV adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer CPLL_FBDIV = 2,$/;" c module:util_adxcvr_xch +CPLL_FBDIV_4_5 adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ parameter CPLL_FBDIV_4_5 = 5,$/;" c module:axi_xcvrlb +CPLL_FBDIV_4_5 adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ parameter CPLL_FBDIV_4_5 = 5,$/;" c module:axi_xcvrlb_1 +CPLL_FBDIV_4_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer CPLL_FBDIV_4_5 = 5,$/;" c module:util_adxcvr +CPLL_FBDIV_4_5 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer CPLL_FBDIV_4_5 = 5,$/;" c module:util_adxcvr_xch +CR adi_library/common/ad_iqcor.v /^ parameter CR = 16, \/\/ Converter Resolution$/;" c module:ad_iqcor +CR_CB_N adi_library/common/ad_ss_422to444.v /^ parameter CR_CB_N = 0,$/;" c module:ad_ss_422to444 +CR_CB_N adi_library/common/ad_ss_444to422.v /^ parameter CR_CB_N = 0,$/;" c module:ad_ss_444to422 +CS_PIN adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ parameter CS_PIN = 0,$/;" c module:util_sigma_delta_spi +CT0_half hdl/Interp_half.v /^ CN1_half CT0_half (.CLK(clk), .A(din_t0), .P(multquartert0)); $/;" i module:Interp_half typeref:module:CN1_half +CT0_quarter hdl/Interp_quarter.v /^ CT0 CT0_quarter (.CLK(clk), .A(din_n1), .P(multquartert0)); $/;" i module:Interp_quarter typeref:module:CT0 +CTRL_WIDTH adi_library/util_pack/util_pack_common/pack_network.v /^ localparam CTRL_WIDTH = 2**PORT_ADDRESS_WIDTH * NUM_STAGES * MUX_ORDER;$/;" c module:pack_network +CYCLIC adi_library/axi_dmac/axi_dmac.v /^ parameter CYCLIC = 1,$/;" c module:axi_dmac +C_T_WIDTH adi_library/common/ad_dds_2.v /^ localparam C_T_WIDTH = (DDS_D_DW > DDS_DW) ? (DDS_D_DW - DDS_DW) : (DDS_DW - DDS_D_DW);$/;" c module:ad_dds_2 +ChnEst_ZF_i hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_i_d1 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i_d1 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_i_d2 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i_d2 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_i_d3 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i_d3 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_i_d4 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i_d4 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_i_d5 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i_d5 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_i_d6 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i_d6 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_i_d7 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i_d7 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_i_d8 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i_d8 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_i_d9 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_i_d9 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_nd hdl/Chn_Estimate.v /^reg [0:0] ChnEst_ZF_nd = 1'd0; \/\/ZF信道估计结果$/;" r module:Chn_Estimate +ChnEst_ZF_nd_d1 hdl/Chn_Estimate.v /^reg [0:0] ChnEst_ZF_nd_d1 = 1'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_nd_d2 hdl/Chn_Estimate.v /^reg [0:0] ChnEst_ZF_nd_d2 = 1'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_nd_d3 hdl/Chn_Estimate.v /^reg [0:0] ChnEst_ZF_nd_d3 = 1'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_nd_d4 hdl/Chn_Estimate.v /^reg [0:0] ChnEst_ZF_nd_d4 = 1'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_nd_d5 hdl/Chn_Estimate.v /^reg [0:0] ChnEst_ZF_nd_d5 = 1'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_nd_d6 hdl/Chn_Estimate.v /^reg [0:0] ChnEst_ZF_nd_d6 = 1'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_nd_d7 hdl/Chn_Estimate.v /^reg [0:0] ChnEst_ZF_nd_d7 = 1'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_nd_d8 hdl/Chn_Estimate.v /^reg [0:0] ChnEst_ZF_nd_d8 = 1'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_nd_d9 hdl/Chn_Estimate.v /^reg [0:0] ChnEst_ZF_nd_d9 = 1'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_q hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_q = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_q_d1 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_q_d1 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_q_d2 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_q_d2 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_q_d3 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_q_d3 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_q_d4 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_q_d4 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_q_d5 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_q_d5 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_q_d6 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_q_d6 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_q_d7 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_q_d7 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_q_d8 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_q_d8 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_ZF_q_d9 hdl/Chn_Estimate.v /^reg [17:0] ChnEst_ZF_q_d9 = 18'd0;$/;" r module:Chn_Estimate +ChnEst_comdiv_ac hdl/Chn_Estimate.v /^MUL_FDE ChnEst_comdiv_ac ($/;" i module:Chn_Estimate typeref:module:MUL_FDE +ChnEst_comdiv_ad hdl/Chn_Estimate.v /^MUL_FDE ChnEst_comdiv_ad ($/;" i module:Chn_Estimate typeref:module:MUL_FDE +ChnEst_comdiv_bc hdl/Chn_Estimate.v /^MUL_FDE ChnEst_comdiv_bc ($/;" i module:Chn_Estimate typeref:module:MUL_FDE +ChnEst_comdiv_bd hdl/Chn_Estimate.v /^MUL_FDE ChnEst_comdiv_bd ($/;" i module:Chn_Estimate typeref:module:MUL_FDE +Chn_Estimate hdl/Chn_Estimate.v /^module Chn_Estimate($/;" m +Chn_Estimate_djy hdl/SC_FDE_TOP.v /^ Chn_Estimate Chn_Estimate_djy ($/;" i module:SC_FDE_TOP typeref:module:Chn_Estimate +ComMul_EstNoise hdl/Noise_Estimate.v /^ ComMul_EstNoise ComMul_EstNoise ($/;" i module:Noise_Estimate typeref:module:ComMul_EstNoise +ComMul_Noisei hdl/Noise_Estimate.v /^ wire [19:0] ComMul_Noisei;$/;" n module:Noise_Estimate +ComMul_Noiseq hdl/Noise_Estimate.v /^ wire [19:0] ComMul_Noiseq;$/;" n module:Noise_Estimate +CompMultIP1 hdl/phase_adjust.v /^ CompMultIP CompMultIP1 ($/;" i module:phase_adjust typeref:module:CompMultIP +CompMultIP2 hdl/phase_adjust.v /^ CompMultIP2 CompMultIP2 ($/;" i module:phase_adjust typeref:module:CompMultIP2 +CrYCb_data adi_library/common/ad_csc_CrYCb2RGB.v /^ input [23:0] CrYCb_data,$/;" p module:ad_csc_CrYCb2RGB +CrYCb_data adi_library/common/ad_csc_RGB2CrYCb.v /^ output [23:0] CrYCb_data);$/;" p module:ad_csc_RGB2CrYCb +CrYCb_sync adi_library/common/ad_csc_CrYCb2RGB.v /^ input [DELAY_DATA_WIDTH-1:0] CrYCb_sync,$/;" p module:ad_csc_CrYCb2RGB +CrYCb_sync adi_library/common/ad_csc_RGB2CrYCb.v /^ output [DELAY_DATA_WIDTH-1:0] CrYCb_sync,$/;" p module:ad_csc_RGB2CrYCb +DAC_ADDRESS_WIDTH adi_library/util_dacfifo/util_dacfifo_bypass.v /^ localparam DAC_ADDRESS_WIDTH = 4;$/;" c module:util_dacfifo_bypass +DAC_BUF_THRESHOLD_HI adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam DAC_BUF_THRESHOLD_HI = (AXI_BIGGER) ? (2 * (AXI_LENGTH+1) * MEM_RATIO) : (2 * (AXI/;" c module:axi_dacfifo_rd +DAC_BUF_THRESHOLD_LO adi_library/util_dacfifo/util_dacfifo_bypass.v /^ localparam DAC_BUF_THRESHOLD_LO = 4;$/;" c module:util_dacfifo_bypass +DAC_DATA_WIDTH adi_library/util_dacfifo/util_dacfifo_bypass.v /^ parameter DAC_DATA_WIDTH = 64,$/;" c module:util_dacfifo_bypass +DAC_DATA_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ parameter DAC_DATA_WIDTH = 64,$/;" c module:axi_dacfifo +DAC_DATA_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ parameter DAC_DATA_WIDTH = 64,$/;" c module:axi_dacfifo_rd +DAC_MEM_ADDRESS_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ parameter DAC_MEM_ADDRESS_WIDTH = 8) ($/;" c module:axi_dacfifo_rd +DAGC_LUT_rom hdl/DAGC_v2.v /^ DAGC_LUT_rom DAGC_LUT_rom ($/;" i module:DAGC_v2 typeref:module:DAGC_LUT_rom +DAGC_mul_10bit12_i hdl/DAGC_v2.v /^ DAGC_mul_10bit12 DAGC_mul_10bit12_i ($/;" i module:DAGC_v2 typeref:module:DAGC_mul_10bit12 +DAGC_mul_10bit12_q hdl/DAGC_v2.v /^ DAGC_mul_10bit12 DAGC_mul_10bit12_q ($/;" i module:DAGC_v2 typeref:module:DAGC_mul_10bit12 +DAGC_out_i hdl/DAGC_v2.v /^ output reg [9:0] DAGC_out_i = 10'd0,$/;" p module:DAGC_v2 +DAGC_out_i hdl/RecvTop.v /^ output [ 9:0] DAGC_out_i, \/\/DAGC输出$/;" p module:RecvTop +DAGC_out_q hdl/DAGC_v2.v /^ output reg [9:0] DAGC_out_q = 10'd0,$/;" p module:DAGC_v2 +DAGC_out_q hdl/RecvTop.v /^ output [ 9:0] DAGC_out_q,$/;" p module:RecvTop +DAGC_rdy hdl/RecvTop.v /^ output DAGC_rdy,$/;" p module:RecvTop +DAGC_v2 hdl/DAGC_v2.v /^module DAGC_v2 ($/;" m +DAGC_v2 hdl/RecvTop.v /^ DAGC_v2 DAGC_v2 ($/;" i module:RecvTop typeref:module:DAGC_v2 +DATAFORMAT_DISABLE adi_library/common/up_adc_channel.v /^ parameter DATAFORMAT_DISABLE = 0,$/;" c module:up_adc_channel +DATA_LEN hdl/add_prefix.v /^ parameter DATA_LEN = 256,$/;" c module:add_prefix +DATA_RATE adi_library/xilinx/common/ad_serdes_in.v /^ localparam DATA_RATE = (DDR_OR_SDR_N) ? "DDR" : "SDR";$/;" c module:ad_serdes_in +DATA_WIDTH adi_library/axi_dmac/axi_register_slice.v /^ parameter DATA_WIDTH = 32,$/;" c module:axi_register_slice +DATA_WIDTH adi_library/axi_dmac/data_mover.v /^ parameter DATA_WIDTH = 64,$/;" c module:dmac_data_mover +DATA_WIDTH adi_library/axi_dmac/dest_fifo_inf.v /^ parameter DATA_WIDTH = 64,$/;" c module:dmac_dest_fifo_inf +DATA_WIDTH adi_library/axi_dmac/src_fifo_inf.v /^ parameter DATA_WIDTH = 64,$/;" c module:dmac_src_fifo_inf +DATA_WIDTH adi_library/axi_dmac/tb/axi_read_slave.v /^ parameter DATA_WIDTH = 32,$/;" c module:axi_read_slave +DATA_WIDTH adi_library/axi_dmac/tb/axi_slave.v /^ parameter DATA_WIDTH = 32,$/;" c module:axi_slave +DATA_WIDTH adi_library/axi_dmac/tb/axi_write_slave.v /^ parameter DATA_WIDTH = 32,$/;" c module:axi_write_slave +DATA_WIDTH adi_library/common/ad_axis_inf_rx.v /^ parameter DATA_WIDTH = 16) ($/;" c module:ad_axis_inf_rx +DATA_WIDTH adi_library/common/ad_b2g.v /^ parameter DATA_WIDTH = 8) ($/;" c module:ad_b2g +DATA_WIDTH adi_library/common/ad_bus_mux.v /^ parameter DATA_WIDTH = 16) ($/;" c module:ad_bus_mux +DATA_WIDTH adi_library/common/ad_datafmt.v /^ parameter DATA_WIDTH = 16,$/;" c module:ad_datafmt +DATA_WIDTH adi_library/common/ad_g2b.v /^ parameter DATA_WIDTH = 8) ($/;" c module:ad_g2b +DATA_WIDTH adi_library/common/ad_iobuf.v /^ parameter DATA_WIDTH = 1) ($/;" c module:ad_iobuf +DATA_WIDTH adi_library/common/ad_mem.v /^ parameter DATA_WIDTH = 16,$/;" c module:ad_mem +DATA_WIDTH adi_library/common/ad_pnmon.v /^ parameter DATA_WIDTH = 16,$/;" c module:ad_pnmon +DATA_WIDTH adi_library/common/up_delay_cntrl.v /^ parameter DATA_WIDTH = 8,$/;" c module:up_delay_cntrl +DATA_WIDTH adi_library/common/up_xfer_cntrl.v /^ parameter DATA_WIDTH = 8) ($/;" c module:up_xfer_cntrl +DATA_WIDTH adi_library/common/up_xfer_status.v /^ parameter DATA_WIDTH = 8) ($/;" c module:up_xfer_status +DATA_WIDTH adi_library/common/util_axis_upscale.v /^ parameter DATA_WIDTH = 24,$/;" c module:util_axis_upscale +DATA_WIDTH adi_library/common/util_delay.v /^ parameter DATA_WIDTH = 1,$/;" c module:util_delay +DATA_WIDTH adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter [15:0] DATA_WIDTH = 8,$/;" c module:axi_spi_engine +DATA_WIDTH adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ parameter DATA_WIDTH = 8, \/\/ Valid data widths values are 8\/16\/24\/32$/;" c module:spi_engine_execution +DATA_WIDTH adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ parameter DATA_WIDTH = 8, \/\/ Valid data widths values are 8\/16\/24\/32$/;" c module:spi_engine_interconnect +DATA_WIDTH adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ parameter DATA_WIDTH = 8, \/\/ Valid data widths values are 8\/16\/24\/32$/;" c module:spi_engine_offload +DATA_WIDTH adi_library/util_axis_fifo/util_axis_fifo.v /^ parameter DATA_WIDTH = 64,$/;" c module:util_axis_fifo +DATA_WIDTH adi_library/util_cdc/sync_gray.v /^ parameter DATA_WIDTH = 1,$/;" c module:sync_gray +DATA_WIDTH adi_library/util_cic/cic_comb.v /^ parameter DATA_WIDTH = 32,$/;" c module:cic_comb +DATA_WIDTH adi_library/util_cic/cic_int.v /^ parameter DATA_WIDTH = 12,$/;" c module:cic_int +DATA_WIDTH adi_library/util_dacfifo/util_dacfifo.v /^ parameter DATA_WIDTH = 128) ($/;" c module:util_dacfifo +DATA_WIDTH adi_library/util_extract/util_extract.v /^ parameter DATA_WIDTH = NUM_OF_CHANNELS * 16) ($/;" c module:util_extract +DATA_WIDTH adi_library/util_rfifo/util_rfifo.v /^ localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS;$/;" c module:util_rfifo +DATA_WIDTH adi_library/util_var_fifo/util_var_fifo.v /^ parameter DATA_WIDTH = 32,$/;" c module:util_var_fifo +DATA_WIDTH adi_library/util_wfifo/util_wfifo.v /^ localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS;$/;" c module:util_wfifo +DATA_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ parameter DATA_WIDTH = 16)($/;" c module:axi_dacfifo_address_buffer +DATA_WIDTH adi_library/xilinx/common/ad_serdes_in.v /^ parameter DATA_WIDTH = 16,$/;" c module:ad_serdes_in +DATA_WIDTH adi_library/xilinx/common/ad_serdes_out.v /^ parameter DATA_WIDTH = 16) ($/;" c module:ad_serdes_out +DATA_WIDTH hdl/shift_reg.v /^ parameter DATA_WIDTH = 8,$/;" c module:shift_reg +DATA_WIDTH_DEST adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter DATA_WIDTH_DEST = 64,$/;" c module:axi_dmac_burst_memory +DATA_WIDTH_DEST adi_library/axi_dmac/axi_dmac_resize_dest.v /^ parameter DATA_WIDTH_DEST = 64,$/;" c module:axi_dmac_resize_dest +DATA_WIDTH_MEM adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam DATA_WIDTH_MEM = DATA_WIDTH_SRC > DATA_WIDTH_DEST ?$/;" c module:axi_dmac_burst_memory +DATA_WIDTH_MEM adi_library/axi_dmac/axi_dmac_resize_dest.v /^ parameter DATA_WIDTH_MEM = 64$/;" c module:axi_dmac_resize_dest +DATA_WIDTH_MEM adi_library/axi_dmac/axi_dmac_resize_src.v /^ parameter DATA_WIDTH_MEM = 64,$/;" c module:axi_dmac_resize_src +DATA_WIDTH_MEM_DEST adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam DATA_WIDTH_MEM_DEST = DATA_WIDTH_MEM >>$/;" c module:axi_dmac_burst_memory +DATA_WIDTH_MEM_SRC adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam DATA_WIDTH_MEM_SRC = DATA_WIDTH_MEM >>$/;" c module:axi_dmac_burst_memory +DATA_WIDTH_SRC adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter DATA_WIDTH_SRC = 64,$/;" c module:axi_dmac_burst_memory +DATA_WIDTH_SRC adi_library/axi_dmac/axi_dmac_resize_src.v /^ parameter DATA_WIDTH_SRC = 64,$/;" c module:axi_dmac_resize_src +DBG_ID_PADDING adi_library/axi_dmac/axi_dmac.v /^localparam DBG_ID_PADDING = ID_WIDTH > 8 ? 0 : 8 - ID_WIDTH;$/;" c module:axi_dmac +DCFILTER_DISABLE adi_library/common/up_adc_channel.v /^ parameter DCFILTER_DISABLE = 0,$/;" c module:up_adc_channel +DDR_OR_SDR_N adi_library/xilinx/common/ad_serdes_clk.v /^ parameter DDR_OR_SDR_N = 1,$/;" c module:ad_serdes_clk +DDR_OR_SDR_N adi_library/xilinx/common/ad_serdes_in.v /^ parameter DDR_OR_SDR_N = 0,$/;" c module:ad_serdes_in +DDR_OR_SDR_N adi_library/xilinx/common/ad_serdes_out.v /^ parameter DDR_OR_SDR_N = 1,$/;" c module:ad_serdes_out +DDS_12bit_8192 hdl/DDS_compensate.v /^COSLUT_8192 DDS_12bit_8192 ($/;" i module:DDS_compensate typeref:module:COSLUT_8192 +DDS_CORDIC_TYPE adi_library/common/ad_dds_1.v /^ localparam DDS_CORDIC_TYPE = 1;$/;" c module:ad_dds_1 +DDS_DFreq_Update1 hdl/DDS_compensate.v /^AdderSigned_25_25_2dly DDS_DFreq_Update1 ($/;" i module:DDS_compensate typeref:module:AdderSigned_25_25_2dly +DDS_DISABLE adi_library/common/up_dac_channel.v /^ parameter DDS_DISABLE = 0,$/;" c module:up_dac_channel +DDS_DW adi_library/common/ad_dds.v /^ parameter DDS_DW = 16,$/;" c module:ad_dds +DDS_DW adi_library/common/ad_dds_2.v /^ parameter DDS_DW = 16,$/;" c module:ad_dds_2 +DDS_D_DW adi_library/common/ad_dds_1.v /^ parameter DDS_D_DW = 16,$/;" c module:ad_dds_1 +DDS_D_DW adi_library/common/ad_dds_2.v /^ localparam DDS_D_DW = (DDS_TYPE == CORDIC) ? CORDIC_DW : 16;$/;" c module:ad_dds_2 +DDS_POLINOMIAL_TYPE adi_library/common/ad_dds_1.v /^ localparam DDS_POLINOMIAL_TYPE = 2;$/;" c module:ad_dds_1 +DDS_P_DW adi_library/common/ad_dds_1.v /^ parameter DDS_P_DW = 16) ($/;" c module:ad_dds_1 +DDS_P_DW adi_library/common/ad_dds_2.v /^ localparam DDS_P_DW = (DDS_TYPE == CORDIC) ? CORDIC_PHASE_DW : 16;$/;" c module:ad_dds_2 +DDS_TYPE adi_library/common/ad_dds.v /^ parameter DDS_TYPE = 1,$/;" c module:ad_dds +DDS_TYPE adi_library/common/ad_dds_1.v /^ parameter DDS_TYPE = 1,$/;" c module:ad_dds_1 +DDS_TYPE adi_library/common/ad_dds_2.v /^ parameter DDS_TYPE = 1,$/;" c module:ad_dds_2 +DDS_compensate hdl/DDS_compensate.v /^module DDS_compensate($/;" m +DDS_compensate_mx hdl/freqestm.v /^ DDS_compensate DDS_compensate_mx ($/;" i module:freqestm typeref:module:DDS_compensate +DDS_trunc_i hdl/freqestm.v /^ wire [11:0] DDS_trunc_i;$/;" n module:freqestm +DDS_trunc_nd hdl/freqestm.v /^ wire DDS_trunc_nd;$/;" n module:freqestm +DDS_trunc_q hdl/freqestm.v /^ wire [11:0] DDS_trunc_q;$/;" n module:freqestm +DDS_width hdl/DDS_compensate.v /^ localparam DDS_width = 24; \/\/25bits in fact$/;" c module:DDS_compensate +DDSin_i hdl/freqestm.v /^ reg [11:0] DDSin_i;$/;" r module:freqestm +DDSin_q hdl/freqestm.v /^ reg [11:0] DDSin_q;$/;" r module:freqestm +DEFAULT_CLK_DIV adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ parameter DEFAULT_CLK_DIV = 0,$/;" c module:spi_engine_execution +DEFAULT_SPI_CFG adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ parameter DEFAULT_SPI_CFG = 0,$/;" c module:spi_engine_execution +DELAYED_DATA_WIDTH adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam DELAYED_DATA_WIDTH = TOTAL_DATA_WIDTH - 2 * CHANNEL_DATA_WIDTH;$/;" c block:pack_shell.gen_pack.gen_output_buffer +DELAY_CYCLES adi_library/common/util_delay.v /^ parameter DELAY_CYCLES = 1) ($/;" c module:util_delay +DELAY_DATA_WIDTH adi_library/common/ad_csc_CrYCb2RGB.v /^ parameter DELAY_DATA_WIDTH = 16) ($/;" c module:ad_csc_CrYCb2RGB +DELAY_DATA_WIDTH adi_library/common/ad_csc_RGB2CrYCb.v /^ parameter DELAY_DATA_WIDTH = 16) ($/;" c module:ad_csc_RGB2CrYCb +DELAY_DATA_WIDTH adi_library/common/ad_dds_sine.v /^ parameter DELAY_DATA_WIDTH = 16) ($/;" c module:ad_dds_sine +DELAY_DATA_WIDTH adi_library/common/ad_ss_422to444.v /^ parameter DELAY_DATA_WIDTH = 16) ($/;" c module:ad_ss_422to444 +DELAY_DATA_WIDTH adi_library/common/ad_ss_444to422.v /^ parameter DELAY_DATA_WIDTH = 16) ($/;" c module:ad_ss_444to422 +DELAY_DATA_WIDTH adi_library/xilinx/common/ad_mul.v /^ parameter DELAY_DATA_WIDTH = 16) ($/;" c module:ad_mul +DELAY_DW adi_library/common/ad_csc.v /^ parameter DELAY_DW = 16,$/;" c module:ad_csc +DELAY_DW adi_library/common/ad_dds_cordic_pipe.v /^ parameter DELAY_DW = 1,$/;" c module:ad_dds_cordic_pipe +DELAY_DW adi_library/common/ad_dds_sine_cordic.v /^ parameter DELAY_DW = 1) ($/;" c module:ad_dds_sine_cordic +DEPTH hdl/shift_reg.v /^ parameter DEPTH = 4$/;" c module:shift_reg +DEST_SRC_RATIO adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam DEST_SRC_RATIO = DMA_DATA_WIDTH_DEST\/DMA_DATA_WIDTH_SRC;$/;" c module:axi_dmac_response_manager +DEST_SRC_RATIO_WIDTH adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam DEST_SRC_RATIO_WIDTH = DEST_SRC_RATIO > 64 ? 7 :$/;" c module:axi_dmac_response_manager +DEV_PACKAGE adi_library/common/up_adc_common.v /^ parameter [ 7:0] DEV_PACKAGE = 0,$/;" c module:up_adc_common +DEV_PACKAGE adi_library/common/up_clkgen.v /^ parameter [ 7:0] DEV_PACKAGE = 0,$/;" c module:up_clkgen +DEV_PACKAGE adi_library/common/up_dac_common.v /^ parameter [ 7:0] DEV_PACKAGE = 0,$/;" c module:up_dac_common +DEV_PACKAGE adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter DEV_PACKAGE = 0,$/;" c module:axi_adxcvr +DEV_PACKAGE adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 7:0] DEV_PACKAGE = 0,$/;" c module:axi_adxcvr_up +DIN_ADDRESS_WIDTH adi_library/util_rfifo/util_rfifo.v /^ parameter DIN_ADDRESS_WIDTH = 8) ($/;" c module:util_rfifo +DIN_ADDRESS_WIDTH adi_library/util_wfifo/util_wfifo.v /^ parameter DIN_ADDRESS_WIDTH = 8) ($/;" c module:util_wfifo +DIN_DATA_WIDTH adi_library/util_mfifo/util_mfifo.v /^ parameter DIN_DATA_WIDTH = 32,$/;" c module:util_mfifo +DIN_DATA_WIDTH adi_library/util_rfifo/util_rfifo.v /^ parameter DIN_DATA_WIDTH = 32,$/;" c module:util_rfifo +DIN_DATA_WIDTH adi_library/util_wfifo/util_wfifo.v /^ parameter DIN_DATA_WIDTH = 32,$/;" c module:util_wfifo +DISABLE adi_library/common/ad_datafmt.v /^ parameter DISABLE = 0) ($/;" c module:ad_datafmt +DISABLE adi_library/common/ad_dds.v /^ parameter DISABLE = 0,$/;" c module:ad_dds +DISABLE adi_library/common/ad_iqcor.v /^ parameter DISABLE = 0,$/;" c module:ad_iqcor +DISABLE adi_library/common/up_delay_cntrl.v /^ parameter DISABLE = 0,$/;" c module:up_delay_cntrl +DISABLE adi_library/xilinx/common/ad_dcfilter.v /^ parameter DISABLE = 0) ($/;" c module:ad_dcfilter +DISABLE_DEBUG_REGISTERS adi_library/axi_dmac/axi_dmac.v /^ parameter DISABLE_DEBUG_REGISTERS = 0,$/;" c module:axi_dmac +DISABLE_DEBUG_REGISTERS adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter DISABLE_DEBUG_REGISTERS = 0,$/;" c module:axi_dmac_regmap +DISABLE_DEBUG_REGISTERS adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter DISABLE_DEBUG_REGISTERS = 0,$/;" c module:axi_dmac_regmap_request +DMA_2D_TRANSFER adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_2D_TRANSFER = 0,$/;" c module:axi_dmac +DMA_2D_TRANSFER adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter DMA_2D_TRANSFER = 0,$/;" c module:axi_dmac_regmap +DMA_2D_TRANSFER adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter DMA_2D_TRANSFER = 0,$/;" c module:axi_dmac_regmap_request +DMA_2D_TRANSFER adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter DMA_2D_TRANSFER = 1,$/;" c module:axi_dmac_transfer +DMA_ADDRESS_WIDTH adi_library/util_adcfifo/util_adcfifo.v /^ parameter DMA_ADDRESS_WIDTH = 10) ($/;" c module:util_adcfifo +DMA_ADDRESS_WIDTH adi_library/util_dacfifo/util_dacfifo_bypass.v /^ localparam DMA_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH :$/;" c module:util_dacfifo_bypass +DMA_ADDRESS_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ localparam DMA_ADDRESS_WIDTH = 8;$/;" c module:axi_adcfifo_dma +DMA_ADDRESS_WIDTH_DEST adi_library/axi_dmac/request_arb.v /^localparam DMA_ADDRESS_WIDTH_DEST = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;$/;" c module:dmac_request_arb +DMA_ADDRESS_WIDTH_SRC adi_library/axi_dmac/request_arb.v /^localparam DMA_ADDRESS_WIDTH_SRC = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;$/;" c module:dmac_request_arb +DMA_ADDR_LIMIT adi_library/util_adcfifo/util_adcfifo.v /^ localparam DMA_ADDR_LIMIT = (2**DMA_ADDRESS_WIDTH)-1;$/;" c module:util_adcfifo +DMA_ADDR_WIDTH adi_library/axi_dmac/address_generator.v /^ parameter DMA_ADDR_WIDTH = 32,$/;" c module:dmac_address_generator +DMA_ADDR_WIDTH adi_library/axi_dmac/dest_axi_mm.v /^ parameter DMA_ADDR_WIDTH = 32,$/;" c module:dmac_dest_mm_axi +DMA_ADDR_WIDTH adi_library/axi_dmac/src_axi_mm.v /^ parameter DMA_ADDR_WIDTH = 32,$/;" c module:dmac_src_mm_axi +DMA_AXIS_DEST_W adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_AXIS_DEST_W = 4,$/;" c module:axi_dmac +DMA_AXIS_ID_W adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_AXIS_ID_W = 8,$/;" c module:axi_dmac +DMA_AXI_ADDR_WIDTH adi_library/axi_dmac/2d_transfer.v /^ parameter DMA_AXI_ADDR_WIDTH = 32,$/;" c module:dmac_2d_transfer +DMA_AXI_ADDR_WIDTH adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_AXI_ADDR_WIDTH = 32,$/;" c module:axi_dmac +DMA_AXI_ADDR_WIDTH adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter DMA_AXI_ADDR_WIDTH = 32,$/;" c module:axi_dmac_regmap +DMA_AXI_ADDR_WIDTH adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter DMA_AXI_ADDR_WIDTH = 32,$/;" c module:axi_dmac_regmap_request +DMA_AXI_ADDR_WIDTH adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter DMA_AXI_ADDR_WIDTH = 32,$/;" c module:axi_dmac_transfer +DMA_AXI_ADDR_WIDTH adi_library/axi_dmac/request_arb.v /^ parameter DMA_AXI_ADDR_WIDTH = 32,$/;" c module:dmac_request_arb +DMA_AXI_ADDR_WIDTH adi_library/axi_dmac/tb/regmap_tb.v /^ localparam DMA_AXI_ADDR_WIDTH = 32;$/;" c module:dmac_regmap_tb +DMA_AXI_PROTOCOL_DEST adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_AXI_PROTOCOL_DEST = 0,$/;" c module:axi_dmac +DMA_AXI_PROTOCOL_SRC adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_AXI_PROTOCOL_SRC = 0,$/;" c module:axi_dmac +DMA_BUF_THRESHOLD_HI adi_library/util_dacfifo/util_dacfifo_bypass.v /^ localparam DMA_BUF_THRESHOLD_HI = {(DMA_ADDRESS_WIDTH){1'b1}} - 4;$/;" c module:util_dacfifo_bypass +DMA_BUF_THRESHOLD_HI adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - 4;$/;" c module:axi_dacfifo_wr +DMA_CYCLIC adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter DMA_CYCLIC = 0,$/;" c module:axi_dmac_regmap +DMA_CYCLIC adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter DMA_CYCLIC = 0,$/;" c module:axi_dmac_regmap_request +DMA_DATA_WIDTH adi_library/axi_dmac/address_generator.v /^ parameter DMA_DATA_WIDTH = 64,$/;" c module:dmac_address_generator +DMA_DATA_WIDTH adi_library/axi_dmac/dest_axi_mm.v /^ parameter DMA_DATA_WIDTH = 64,$/;" c module:dmac_dest_mm_axi +DMA_DATA_WIDTH adi_library/axi_dmac/src_axi_mm.v /^ parameter DMA_DATA_WIDTH = 64,$/;" c module:dmac_src_mm_axi +DMA_DATA_WIDTH adi_library/util_adcfifo/util_adcfifo.v /^ parameter DMA_DATA_WIDTH = 64,$/;" c module:util_adcfifo +DMA_DATA_WIDTH adi_library/util_dacfifo/util_dacfifo_bypass.v /^ parameter DMA_DATA_WIDTH = 64) ($/;" c module:util_dacfifo_bypass +DMA_DATA_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ parameter DMA_DATA_WIDTH = 64,$/;" c module:axi_adcfifo +DMA_DATA_WIDTH adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ parameter DMA_DATA_WIDTH = 64,$/;" c module:axi_adcfifo_dma +DMA_DATA_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ parameter DMA_DATA_WIDTH = 64,$/;" c module:axi_dacfifo +DMA_DATA_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ parameter DMA_DATA_WIDTH = 64,$/;" c module:axi_dacfifo_wr +DMA_DATA_WIDTH_DEST adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_DATA_WIDTH_DEST = 64,$/;" c module:axi_dmac +DMA_DATA_WIDTH_DEST adi_library/axi_dmac/axi_dmac_response_manager.v /^ parameter DMA_DATA_WIDTH_DEST = 64,$/;" c module:axi_dmac_response_manager +DMA_DATA_WIDTH_DEST adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter DMA_DATA_WIDTH_DEST = 64,$/;" c module:axi_dmac_transfer +DMA_DATA_WIDTH_DEST adi_library/axi_dmac/request_arb.v /^ parameter DMA_DATA_WIDTH_DEST = 64,$/;" c module:dmac_request_arb +DMA_DATA_WIDTH_SRC adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_DATA_WIDTH_SRC = 64,$/;" c module:axi_dmac +DMA_DATA_WIDTH_SRC adi_library/axi_dmac/axi_dmac_response_manager.v /^ parameter DMA_DATA_WIDTH_SRC = 64,$/;" c module:axi_dmac_response_manager +DMA_DATA_WIDTH_SRC adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter DMA_DATA_WIDTH_SRC = 64,$/;" c module:axi_dmac_transfer +DMA_DATA_WIDTH_SRC adi_library/axi_dmac/request_arb.v /^ parameter DMA_DATA_WIDTH_SRC = 64,$/;" c module:dmac_request_arb +DMA_LENGTH_ALIGN adi_library/axi_dmac/axi_dmac.v /^ localparam DMA_LENGTH_ALIGN =$/;" c module:axi_dmac +DMA_LENGTH_ALIGN adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter DMA_LENGTH_ALIGN = 3,$/;" c module:axi_dmac_burst_memory +DMA_LENGTH_ALIGN adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter DMA_LENGTH_ALIGN = 3,$/;" c module:axi_dmac_regmap +DMA_LENGTH_ALIGN adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter DMA_LENGTH_ALIGN = 3,$/;" c module:axi_dmac_regmap_request +DMA_LENGTH_ALIGN adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter DMA_LENGTH_ALIGN = 3,$/;" c module:axi_dmac_transfer +DMA_LENGTH_ALIGN adi_library/axi_dmac/request_arb.v /^ parameter DMA_LENGTH_ALIGN = 3,$/;" c module:dmac_request_arb +DMA_LENGTH_ALIGN adi_library/axi_dmac/tb/regmap_tb.v /^ localparam DMA_LENGTH_ALIGN = 3;$/;" c module:dmac_regmap_tb +DMA_LENGTH_ALIGN_DEST adi_library/axi_dmac/axi_dmac.v /^localparam DMA_LENGTH_ALIGN_DEST =$/;" c module:axi_dmac +DMA_LENGTH_ALIGN_SRC adi_library/axi_dmac/axi_dmac.v /^localparam DMA_LENGTH_ALIGN_SRC =$/;" c module:axi_dmac +DMA_LENGTH_WIDTH adi_library/axi_dmac/2d_transfer.v /^ parameter DMA_LENGTH_WIDTH = 24,$/;" c module:dmac_2d_transfer +DMA_LENGTH_WIDTH adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_LENGTH_WIDTH = 24,$/;" c module:axi_dmac +DMA_LENGTH_WIDTH adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter DMA_LENGTH_WIDTH = 24,$/;" c module:axi_dmac_regmap +DMA_LENGTH_WIDTH adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter DMA_LENGTH_WIDTH = 24,$/;" c module:axi_dmac_regmap_request +DMA_LENGTH_WIDTH adi_library/axi_dmac/axi_dmac_response_manager.v /^ parameter DMA_LENGTH_WIDTH = 24,$/;" c module:axi_dmac_response_manager +DMA_LENGTH_WIDTH adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter DMA_LENGTH_WIDTH = 24,$/;" c module:axi_dmac_transfer +DMA_LENGTH_WIDTH adi_library/axi_dmac/request_arb.v /^ parameter DMA_LENGTH_WIDTH = 24,$/;" c module:dmac_request_arb +DMA_LENGTH_WIDTH adi_library/axi_dmac/tb/regmap_tb.v /^ localparam DMA_LENGTH_WIDTH = 24;$/;" c module:dmac_regmap_tb +DMA_MEM_ADDRESS_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ parameter DMA_MEM_ADDRESS_WIDTH = 8) ($/;" c module:axi_dacfifo_wr +DMA_MEM_RATIO adi_library/util_adcfifo/util_adcfifo.v /^ localparam DMA_MEM_RATIO = ADC_DATA_WIDTH\/DMA_DATA_WIDTH;$/;" c module:util_adcfifo +DMA_MEM_RATIO adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ localparam DMA_MEM_RATIO = AXI_DATA_WIDTH\/DMA_DATA_WIDTH;$/;" c module:axi_adcfifo_dma +DMA_READY_ENABLE adi_library/util_adcfifo/util_adcfifo.v /^ parameter DMA_READY_ENABLE = 1,$/;" c module:util_adcfifo +DMA_READY_ENABLE adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ parameter DMA_READY_ENABLE = 1,$/;" c module:axi_adcfifo +DMA_READY_ENABLE adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ parameter DMA_READY_ENABLE = 1) ($/;" c module:axi_adcfifo_dma +DMA_TYPE_AXI_MM adi_library/axi_dmac/axi_dmac.v /^localparam DMA_TYPE_AXI_MM = 0;$/;" c module:axi_dmac +DMA_TYPE_AXI_STREAM adi_library/axi_dmac/axi_dmac.v /^localparam DMA_TYPE_AXI_STREAM = 1;$/;" c module:axi_dmac +DMA_TYPE_DEST adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_TYPE_DEST = 0,$/;" c module:axi_dmac +DMA_TYPE_DEST adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter DMA_TYPE_DEST = 0,$/;" c module:axi_dmac_regmap +DMA_TYPE_DEST adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter DMA_TYPE_DEST = 0,$/;" c module:axi_dmac_transfer +DMA_TYPE_DEST adi_library/axi_dmac/request_arb.v /^ parameter DMA_TYPE_DEST = 0,$/;" c module:dmac_request_arb +DMA_TYPE_FIFO adi_library/axi_dmac/axi_dmac.v /^localparam DMA_TYPE_FIFO = 2;$/;" c module:axi_dmac +DMA_TYPE_FIFO adi_library/axi_dmac/request_arb.v /^localparam DMA_TYPE_FIFO = 2;$/;" c module:dmac_request_arb +DMA_TYPE_MM_AXI adi_library/axi_dmac/request_arb.v /^localparam DMA_TYPE_MM_AXI = 0;$/;" c module:dmac_request_arb +DMA_TYPE_SRC adi_library/axi_dmac/axi_dmac.v /^ parameter DMA_TYPE_SRC = 2,$/;" c module:axi_dmac +DMA_TYPE_SRC adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter DMA_TYPE_SRC = 2,$/;" c module:axi_dmac_regmap +DMA_TYPE_SRC adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter DMA_TYPE_SRC = 2,$/;" c module:axi_dmac_transfer +DMA_TYPE_SRC adi_library/axi_dmac/request_arb.v /^ parameter DMA_TYPE_SRC = 2,$/;" c module:dmac_request_arb +DMA_TYPE_STREAM_AXI adi_library/axi_dmac/request_arb.v /^localparam DMA_TYPE_STREAM_AXI = 1;$/;" c module:dmac_request_arb +DMF_i hdl/SCFDE_recv_FrameSync.v /^ DMF DMF_i ($/;" i module:SCFDE_recv_FrameSync typeref:module:DMF +DMF_q hdl/SCFDE_recv_FrameSync.v /^ DMF DMF_q ($/;" i module:SCFDE_recv_FrameSync typeref:module:DMF +DOUT_DATA_WIDTH adi_library/util_rfifo/util_rfifo.v /^ parameter DOUT_DATA_WIDTH = 64,$/;" c module:util_rfifo +DOUT_DATA_WIDTH adi_library/util_wfifo/util_wfifo.v /^ parameter DOUT_DATA_WIDTH = 64,$/;" c module:util_wfifo +DPW adi_library/common/ad_iqcor.v /^ parameter DPW = 1 \/\/ Data Path Width$/;" c module:ad_iqcor +DRP_DISABLE adi_library/common/up_adc_common.v /^ parameter DRP_DISABLE = 0,$/;" c module:up_adc_common +DRP_DISABLE adi_library/common/up_dac_common.v /^ parameter DRP_DISABLE = 0,$/;" c module:up_dac_common +DRP_WIDTH adi_library/common/up_delay_cntrl.v /^ parameter DRP_WIDTH = 5,$/;" c module:up_delay_cntrl +DRP_WIDTH adi_library/xilinx/common/ad_serdes_in.v /^ parameter DRP_WIDTH = 5,$/;" c module:ad_serdes_in +DR_OQ_DDR adi_library/xilinx/common/ad_serdes_out.v /^ localparam DR_OQ_DDR = DDR_OR_SDR_N == 1'b1 ? "DDR": "SDR";$/;" c module:ad_serdes_out +DW adi_library/common/ad_csc_CrYCb2RGB.v /^ localparam DW = DELAY_DATA_WIDTH - 1;$/;" c module:ad_csc_CrYCb2RGB +DW adi_library/common/ad_csc_RGB2CrYCb.v /^ localparam DW = DELAY_DATA_WIDTH - 1;$/;" c module:ad_csc_RGB2CrYCb +DW adi_library/common/ad_pngen.v /^ parameter DW = 16$/;" c module:ad_pngen +DW adi_library/common/ad_ss_422to444.v /^ localparam DW = DELAY_DATA_WIDTH - 1;$/;" c module:ad_ss_422to444 +DW adi_library/common/ad_ss_444to422.v /^ localparam DW = DELAY_DATA_WIDTH - 1;$/;" c module:ad_ss_444to422 +DW adi_library/common/ad_xcvr_rx_if.v /^ parameter DW = OCTETS_PER_BEAT * 8$/;" c module:ad_xcvr_rx_if +D_DW adi_library/common/ad_dds_cordic_pipe.v /^ parameter D_DW = 16,$/;" c module:ad_dds_cordic_pipe +DemodMult_pad hdl/DDS_compensate.v /^ wire [13:0] DemodMult_pad;$/;" n module:DDS_compensate +Demod_ovrflw hdl/DDS_compensate.v /^ output Demod_ovrflw;$/;" p module:DDS_compensate +Demod_ovrflw hdl/freqestm.v /^ wire Demod_ovrflw;$/;" n module:freqestm +Demod_ovrflw_i hdl/DDS_compensate.v /^ wire Demod_ovrflw_i,Demod_ovrflw_q;$/;" n module:DDS_compensate +Demod_ovrflw_q hdl/DDS_compensate.v /^ wire Demod_ovrflw_i,Demod_ovrflw_q;$/;" n module:DDS_compensate +Din hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input [WIDTH-1:0] Din, \/\/译码输入数据,软信息$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Din_A_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [WIDTH-1:0] Din_A_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Din_B_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [WIDTH-1:0] Din_B_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Din_I hdl/ApproxAbs_18bit.v /^ input [17:0] Din_I,$/;" p module:ApproxAbs_18bit +Din_I hdl/ApproxAbs_v2.v /^ input [9:0] Din_I,$/;" p module:ApproxAbs_v2 +Din_I hdl/DAGC_v2.v /^ reg [ 9:0] Din_I = 10'd0;$/;" r module:DAGC_v2 +Din_I_D1 hdl/ApproxAbs_18bit.v /^ reg [17:0] Din_I_D1;$/;" r module:ApproxAbs_18bit +Din_I_D1 hdl/ApproxAbs_v2.v /^ reg [9:0] Din_I_D1;$/;" r module:ApproxAbs_v2 +Din_I_neg hdl/ApproxAbs_18bit.v /^ reg [17:0] Din_I_neg;$/;" r module:ApproxAbs_18bit +Din_I_neg hdl/ApproxAbs_v2.v /^ reg [9:0] Din_I_neg;$/;" r module:ApproxAbs_v2 +Din_Q hdl/ApproxAbs_18bit.v /^ input [17:0] Din_Q,$/;" p module:ApproxAbs_18bit +Din_Q hdl/ApproxAbs_v2.v /^ input [9:0] Din_Q,$/;" p module:ApproxAbs_v2 +Din_Q hdl/DAGC_v2.v /^ reg [ 9:0] Din_Q = 10'd0;$/;" r module:DAGC_v2 +Din_Q_D1 hdl/ApproxAbs_18bit.v /^ reg [17:0] Din_Q_D1; $/;" r module:ApproxAbs_18bit +Din_Q_D1 hdl/ApproxAbs_v2.v /^ reg [9:0] Din_Q_D1;$/;" r module:ApproxAbs_v2 +Din_Q_neg hdl/ApproxAbs_18bit.v /^ reg [17:0] Din_Q_neg;$/;" r module:ApproxAbs_18bit +Din_Q_neg hdl/ApproxAbs_v2.v /^ reg [9:0] Din_Q_neg;$/;" r module:ApproxAbs_v2 +Dout hdl/ApproxAbs_18bit.v /^ output reg [18:0] Dout,$/;" p module:ApproxAbs_18bit +Dout hdl/ApproxAbs_v2.v /^ output reg [10:0] Dout = 11'd0,$/;" p module:ApproxAbs_v2 +Dout hdl/DAGC_v2.v /^ wire [10:0] Dout;$/;" n module:DAGC_v2 +Dout_Temp hdl/ApproxAbs_18bit.v /^ reg [18:0] Dout_Temp;$/;" r module:ApproxAbs_18bit +Dout_Temp hdl/ApproxAbs_v2.v /^ reg [10:0] Dout_Temp;$/;" r module:ApproxAbs_v2 +Dout_Temp1 hdl/ApproxAbs_18bit.v /^ reg [18:0] Dout_Temp1;$/;" r module:ApproxAbs_18bit +Dout_Temp1 hdl/ApproxAbs_v2.v /^ reg [10:0] Dout_Temp1;$/;" r module:ApproxAbs_v2 +Dout_Temp2 hdl/ApproxAbs_18bit.v /^ reg [18:0] Dout_Temp2;$/;" r module:ApproxAbs_18bit +Dout_Temp2 hdl/ApproxAbs_v2.v /^ reg [10:0] Dout_Temp2;$/;" r module:ApproxAbs_v2 +EDGE adi_library/common/ad_edge_detect.v /^ parameter EDGE = 0) ($/;" c module:ad_edge_detect +ENABLE_DIAGNOSTICS_IF adi_library/axi_dmac/axi_dmac.v /^ parameter ENABLE_DIAGNOSTICS_IF = 0,$/;" c module:axi_dmac +ENABLE_DIAGNOSTICS_IF adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter ENABLE_DIAGNOSTICS_IF = 0,$/;" c module:axi_dmac_burst_memory +ENABLE_DIAGNOSTICS_IF adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter ENABLE_DIAGNOSTICS_IF = 0,$/;" c module:axi_dmac_transfer +ENABLE_DIAGNOSTICS_IF adi_library/axi_dmac/request_arb.v /^ parameter ENABLE_DIAGNOSTICS_IF = 0,$/;" c module:dmac_request_arb +ENABLE_RANDOM adi_library/util_pack/tb/cpack_tb.v /^ parameter ENABLE_RANDOM = 0;$/;" c module:cpack_tb +ENABLE_RANDOM adi_library/util_pack/tb/upack_tb.v /^ parameter ENABLE_RANDOM = 0;$/;" c module:upack_tb +ENC_IN_LEN hdl/enc_control.v /^ parameter ENC_IN_LEN = 1024,$/;" c module:enc_control +ENC_OUT_LEN hdl/enc_control.v /^ parameter ENC_OUT_LEN = 2048,$/;" c module:enc_control +EQUenable_vio hdl/SC_FDE_TOP.v /^ input EQUenable_vio, \/\/为1时启用均衡$/;" p module:SC_FDE_TOP +EQUenable_vio hdl/data_equalizer.v /^ input EQUenable_vio,$/;" p module:data_equalizer +ES_DRP_CTRL_ADDR adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [11:0] ES_DRP_CTRL_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03d : (XCVR_TYPE == GTHE3/;" c module:axi_adxcvr_es +ES_DRP_ECNT_ADDR adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [11:0] ES_DRP_ECNT_ADDR = (XCVR_TYPE == GTXE2) ? 12'h14f : (XCVR_TYPE == GTHE3/;" c module:axi_adxcvr_es +ES_DRP_HOFFSET_ADDR adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [11:0] ES_DRP_HOFFSET_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03c : (XCVR_TYPE == GTHE3/;" c module:axi_adxcvr_es +ES_DRP_SCNT_ADDR adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [11:0] ES_DRP_SCNT_ADDR = (XCVR_TYPE == GTXE2) ? 12'h150 : (XCVR_TYPE == GTHE3/;" c module:axi_adxcvr_es +ES_DRP_STATUS_ADDR adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [11:0] ES_DRP_STATUS_ADDR = (XCVR_TYPE == GTXE2) ? 12'h151 : (XCVR_TYPE == GTHE3/;" c module:axi_adxcvr_es +ES_DRP_VOFFSET_ADDR adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [11:0] ES_DRP_VOFFSET_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03b : (XCVR_TYPE == GTHE3/;" c module:axi_adxcvr_es +ES_FSM_AXI_READY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_AXI_READY = 6'h16;$/;" c module:axi_adxcvr_es +ES_FSM_AXI_WRITE adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_AXI_WRITE = 6'h15;$/;" c module:axi_adxcvr_es +ES_FSM_CTRL_READ adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_CTRL_READ = 6'h09;$/;" c module:axi_adxcvr_es +ES_FSM_CTRL_RRDY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_CTRL_RRDY = 6'h0a;$/;" c module:axi_adxcvr_es +ES_FSM_ECNT_READ adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_ECNT_READ = 6'h13;$/;" c module:axi_adxcvr_es +ES_FSM_ECNT_RRDY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_ECNT_RRDY = 6'h14;$/;" c module:axi_adxcvr_es +ES_FSM_HOFFSET_READ adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_HOFFSET_READ = 6'h01;$/;" c module:axi_adxcvr_es +ES_FSM_HOFFSET_RRDY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_HOFFSET_RRDY = 6'h02;$/;" c module:axi_adxcvr_es +ES_FSM_HOFFSET_WRDY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_HOFFSET_WRDY = 6'h04;$/;" c module:axi_adxcvr_es +ES_FSM_HOFFSET_WRITE adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_HOFFSET_WRITE = 6'h03;$/;" c module:axi_adxcvr_es +ES_FSM_IDLE adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_IDLE = 6'h00;$/;" c module:axi_adxcvr_es +ES_FSM_SCNT_READ adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_SCNT_READ = 6'h11;$/;" c module:axi_adxcvr_es +ES_FSM_SCNT_RRDY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_SCNT_RRDY = 6'h12;$/;" c module:axi_adxcvr_es +ES_FSM_START_WRDY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_START_WRDY = 6'h0c;$/;" c module:axi_adxcvr_es +ES_FSM_START_WRITE adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_START_WRITE = 6'h0b;$/;" c module:axi_adxcvr_es +ES_FSM_STATUS_READ adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_STATUS_READ = 6'h0d;$/;" c module:axi_adxcvr_es +ES_FSM_STATUS_RRDY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_STATUS_RRDY = 6'h0e;$/;" c module:axi_adxcvr_es +ES_FSM_STOP_WRDY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_STOP_WRDY = 6'h10;$/;" c module:axi_adxcvr_es +ES_FSM_STOP_WRITE adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_STOP_WRITE = 6'h0f;$/;" c module:axi_adxcvr_es +ES_FSM_UPDATE adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_UPDATE = 6'h17;$/;" c module:axi_adxcvr_es +ES_FSM_VOFFSET_READ adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_VOFFSET_READ = 6'h05;$/;" c module:axi_adxcvr_es +ES_FSM_VOFFSET_RRDY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_VOFFSET_RRDY = 6'h06;$/;" c module:axi_adxcvr_es +ES_FSM_VOFFSET_WRDY adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_VOFFSET_WRDY = 6'h08;$/;" c module:axi_adxcvr_es +ES_FSM_VOFFSET_WRITE adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam [ 4:0] ES_FSM_VOFFSET_WRITE = 6'h07;$/;" c module:axi_adxcvr_es +Encode_Dout hdl/CCSDS_LDPC_ENC_R12.v /^ output reg Encode_Dout = 1'd0,$/;" p module:CCSDS_LDPC_ENC_R12 +Encode_Rdy hdl/CCSDS_LDPC_ENC_R12.v /^ output reg Encode_Rdy = 1'd0$/;" p module:CCSDS_LDPC_ENC_R12 +Encode_Sync_Dout hdl/CCSDS_LDPC_ENC_R12.v /^ output reg Encode_Sync_Dout = 1'd0,$/;" p module:CCSDS_LDPC_ENC_R12 +Encoder_Din hdl/CCSDS_LDPC_ENC_R12.v /^ input Encoder_Din,$/;" p module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d01 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d01 = 1'd0; reg Encoder_Din_d02 = 1'd0; reg Encoder_Din_d03 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d02 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d01 = 1'd0; reg Encoder_Din_d02 = 1'd0; reg Encoder_Din_d03 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d03 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d01 = 1'd0; reg Encoder_Din_d02 = 1'd0; reg Encoder_Din_d03 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d04 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d01 = 1'd0; reg Encoder_Din_d02 = 1'd0; reg Encoder_Din_d03 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d05 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d01 = 1'd0; reg Encoder_Din_d02 = 1'd0; reg Encoder_Din_d03 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d06 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d06 = 1'd0; reg Encoder_Din_d07 = 1'd0; reg Encoder_Din_d08 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d07 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d06 = 1'd0; reg Encoder_Din_d07 = 1'd0; reg Encoder_Din_d08 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d08 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d06 = 1'd0; reg Encoder_Din_d07 = 1'd0; reg Encoder_Din_d08 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d09 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d06 = 1'd0; reg Encoder_Din_d07 = 1'd0; reg Encoder_Din_d08 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d10 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d06 = 1'd0; reg Encoder_Din_d07 = 1'd0; reg Encoder_Din_d08 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d11 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d11 = 1'd0; reg Encoder_Din_d12 = 1'd0; reg Encoder_Din_d13 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d12 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d11 = 1'd0; reg Encoder_Din_d12 = 1'd0; reg Encoder_Din_d13 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d13 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d11 = 1'd0; reg Encoder_Din_d12 = 1'd0; reg Encoder_Din_d13 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d14 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d11 = 1'd0; reg Encoder_Din_d12 = 1'd0; reg Encoder_Din_d13 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d15 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d11 = 1'd0; reg Encoder_Din_d12 = 1'd0; reg Encoder_Din_d13 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d16 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d16 = 1'd0; reg Encoder_Din_d17 = 1'd0; reg Encoder_Din_d18 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d17 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d16 = 1'd0; reg Encoder_Din_d17 = 1'd0; reg Encoder_Din_d18 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d18 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d16 = 1'd0; reg Encoder_Din_d17 = 1'd0; reg Encoder_Din_d18 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d19 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d16 = 1'd0; reg Encoder_Din_d17 = 1'd0; reg Encoder_Din_d18 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Din_d20 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Din_d16 = 1'd0; reg Encoder_Din_d17 = 1'd0; reg Encoder_Din_d18 = 1'd0; reg Encoder/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Nd hdl/CCSDS_LDPC_ENC_R12.v /^ input Encoder_Nd,$/;" p module:CCSDS_LDPC_ENC_R12 +Encoder_Nd_d1 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Nd_d1 = 1'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_Nd_d2 hdl/CCSDS_LDPC_ENC_R12.v /^ reg Encoder_Nd_d2 = 1'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +Encoder_SyncIn hdl/CCSDS_LDPC_ENC_R12.v /^ input Encoder_SyncIn,$/;" p module:CCSDS_LDPC_ENC_R12 +EstNoise_i hdl/Chn_Estimate.v /^ input [27:0] EstNoise_i,$/;" p module:Chn_Estimate +EstNoise_i hdl/Noise_Estimate.v /^ output reg [27:0] EstNoise_i = 28'd0,$/;" p module:Noise_Estimate +EstNoise_i hdl/SC_FDE_TOP.v /^ wire [27:0] EstNoise_i;$/;" n module:SC_FDE_TOP +EstNoise_q hdl/Chn_Estimate.v /^ input [27:0] EstNoise_q,$/;" p module:Chn_Estimate +EstNoise_q hdl/Noise_Estimate.v /^ output reg [27:0] EstNoise_q = 28'd0 \/\/应当为0$/;" p module:Noise_Estimate +EstNoise_q hdl/SC_FDE_TOP.v /^ wire [27:0] EstNoise_q;$/;" n module:SC_FDE_TOP +FIFO_BYPASS adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0;$/;" c module:axi_dacfifo +FIFO_SIZE adi_library/axi_dmac/axi_dmac.v /^ parameter FIFO_SIZE = 8, \/\/ In bursts$/;" c module:axi_dmac +FIFO_SIZE adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter FIFO_SIZE = 8,$/;" c module:axi_dmac_transfer +FIFO_SIZE adi_library/axi_dmac/request_arb.v /^ parameter FIFO_SIZE = 8,$/;" c module:dmac_request_arb +FIFO_THRESHOLD_HI adi_library/util_dacfifo/util_dacfifo.v /^ localparam FIFO_THRESHOLD_HI = {(ADDRESS_WIDTH){1'b1}} - 4;$/;" c module:util_dacfifo +FORWARD_REGISTERED adi_library/axi_dmac/axi_register_slice.v /^ parameter FORWARD_REGISTERED = 0,$/;" c module:axi_register_slice +FPGA_FAMILY adi_library/common/up_adc_common.v /^ parameter [ 7:0] FPGA_FAMILY = 0,$/;" c module:up_adc_common +FPGA_FAMILY adi_library/common/up_clkgen.v /^ parameter [ 7:0] FPGA_FAMILY = 0,$/;" c module:up_clkgen +FPGA_FAMILY adi_library/common/up_dac_common.v /^ parameter [ 7:0] FPGA_FAMILY = 0,$/;" c module:up_dac_common +FPGA_FAMILY adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter FPGA_FAMILY = 0,$/;" c module:axi_adxcvr +FPGA_FAMILY adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 7:0] FPGA_FAMILY = 0,$/;" c module:axi_adxcvr_up +FPGA_TECHNOLOGY adi_library/common/up_adc_common.v /^ parameter [ 7:0] FPGA_TECHNOLOGY = 0,$/;" c module:up_adc_common +FPGA_TECHNOLOGY adi_library/common/up_clkgen.v /^ parameter [ 7:0] FPGA_TECHNOLOGY = 0,$/;" c module:up_clkgen +FPGA_TECHNOLOGY adi_library/common/up_dac_common.v /^ parameter [ 7:0] FPGA_TECHNOLOGY = 0,$/;" c module:up_dac_common +FPGA_TECHNOLOGY adi_library/util_adcfifo/util_adcfifo.v /^ parameter FPGA_TECHNOLOGY = 0,$/;" c module:util_adcfifo +FPGA_TECHNOLOGY adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter FPGA_TECHNOLOGY = 0,$/;" c module:axi_adxcvr +FPGA_TECHNOLOGY adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 7:0] FPGA_TECHNOLOGY = 0,$/;" c module:axi_adxcvr_up +FPGA_TECHNOLOGY adi_library/xilinx/common/ad_data_in.v /^ parameter FPGA_TECHNOLOGY = 0,$/;" c module:ad_data_in +FPGA_TECHNOLOGY adi_library/xilinx/common/ad_data_out.v /^ parameter FPGA_TECHNOLOGY = 0,$/;" c module:ad_data_out +FPGA_TECHNOLOGY adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter FPGA_TECHNOLOGY = 0,$/;" c module:ad_mmcm_drp +FPGA_TECHNOLOGY adi_library/xilinx/common/ad_serdes_clk.v /^ parameter FPGA_TECHNOLOGY = 0,$/;" c module:ad_serdes_clk +FPGA_TECHNOLOGY adi_library/xilinx/common/ad_serdes_in.v /^ parameter FPGA_TECHNOLOGY = 0,$/;" c module:ad_serdes_in +FPGA_TECHNOLOGY adi_library/xilinx/common/ad_serdes_out.v /^ parameter FPGA_TECHNOLOGY = 0,$/;" c module:ad_serdes_out +FPGA_VOLTAGE adi_library/common/up_clkgen.v /^ parameter [15:0] FPGA_VOLTAGE = 0) ($/;" c module:up_clkgen +FPGA_VOLTAGE adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [15:0] FPGA_VOLTAGE = 0,$/;" c module:axi_adxcvr +FPGA_VOLTAGE adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [15:0] FPGA_VOLTAGE = 0,$/;" c module:axi_adxcvr_up +FRAME_HEADER_LEN hdl/Transmitter.v /^ parameter FRAME_HEADER_LEN = 512,$/;" c module:Transmitter +FrameMerge hdl/FrameMerge.v /^module FrameMerge($/;" m +FrameMerge hdl/RecvTop.v /^ FrameMerge FrameMerge ($/;" i module:RecvTop typeref:module:FrameMerge +FrameSync hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input FrameSync, \/\/帧同步标志,高脉冲$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +FrameSync_A_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire FrameSync_A_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +FrameSync_B_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire FrameSync_B_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +FrameSync_douti hdl/RecvTop.v /^ wire [9:0] FrameSync_douti;$/;" n module:RecvTop +FrameSync_doutq hdl/RecvTop.v /^ wire [9:0] FrameSync_doutq;$/;" n module:RecvTop +GAP_LEN hdl/Transmitter.v /^ parameter GAP_LEN = 160$/;" c module:Transmitter +GEN_ASYNC_RESET adi_library/axi_dmac/axi_dmac_reset_manager.v /^localparam GEN_ASYNC_RESET = {$/;" c module:axi_dmac_reset_manager +GPIO_DISABLE adi_library/common/up_adc_common.v /^ parameter GPIO_DISABLE = 0,$/;" c module:up_adc_common +GPIO_DISABLE adi_library/common/up_dac_common.v /^ parameter GPIO_DISABLE = 0) ($/;" c module:up_dac_common +GTHE3 adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam GTHE3 = 5;$/;" c module:axi_adxcvr_es +GTHE3_TRANSCEIVERS adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ localparam GTHE3_TRANSCEIVERS = 5;$/;" c module:util_adxcvr_xch +GTHE3_TRANSCEIVERS adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ localparam GTHE3_TRANSCEIVERS = 5;$/;" c module:util_adxcvr_xcm +GTHE4 adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam GTHE4 = 8;$/;" c module:axi_adxcvr_es +GTHE4_TRANSCEIVERS adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ localparam GTHE4_TRANSCEIVERS = 8;$/;" c module:util_adxcvr_xch +GTHE4_TRANSCEIVERS adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ localparam GTHE4_TRANSCEIVERS = 8;$/;" c module:util_adxcvr_xcm +GTXE2 adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam GTXE2 = 2;$/;" c module:axi_adxcvr_es +GTXE2_TRANSCEIVERS adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ localparam GTXE2_TRANSCEIVERS = 2;$/;" c module:util_adxcvr_xch +GTXE2_TRANSCEIVERS adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ localparam GTXE2_TRANSCEIVERS = 2;$/;" c module:util_adxcvr_xcm +GTYE4 adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ localparam GTYE4 = 9;$/;" c module:axi_adxcvr_es +GTYE4_TRANSCEIVERS adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ localparam GTYE4_TRANSCEIVERS = 9;$/;" c module:util_adxcvr_xch +GTYE4_TRANSCEIVERS adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ localparam GTYE4_TRANSCEIVERS = 9;$/;" c module:util_adxcvr_xcm +G_MATRIX_ROM_R12 hdl/CCSDS_LDPC_ENC_R12.v /^ G_MATRIX_ROM_R12 G_MATRIX_ROM_R12 ($/;" i module:CCSDS_LDPC_ENC_R12 typeref:module:G_MATRIX_ROM_R12 +G_matrix_addr hdl/CCSDS_LDPC_ENC_R12.v /^ reg [6:0] G_matrix_addr = 7'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d01 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d01 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d01_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d01_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d02 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d02 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d02_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d02_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d03 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d03 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d03_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d03_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d04 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d04 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d04_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d04_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d05 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d05 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d05_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d05_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d06 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d06 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d06_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d06_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d07 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d07 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d07_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d07_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d08 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d08 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d08_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d08_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d09 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d09 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d09_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d09_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d10 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d10 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d10_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d10_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d11 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d11 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d11_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d11_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d12 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d12 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d12_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d12_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d13 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d13 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d13_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d13_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d14 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d14 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d14_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d14_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d15 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d15 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d15_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d15_tem = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d16 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d16 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_d16_tem hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] G_matrix_d16_tem = 64'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_rom_out hdl/CCSDS_LDPC_ENC_R12.v /^ wire [63:0] G_matrix_rom_out;$/;" n module:CCSDS_LDPC_ENC_R12 +G_matrix_row_valid hdl/CCSDS_LDPC_ENC_R12.v /^ reg G_matrix_row_valid = 1'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +G_matrix_valid hdl/CCSDS_LDPC_ENC_R12.v /^ reg G_matrix_valid = 1'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +G_row_rd_clk_num hdl/CCSDS_LDPC_ENC_R12.v /^ reg [4:0] G_row_rd_clk_num = 5'd0; \/\/完整读取G矩阵的一行需要时钟数$/;" r module:CCSDS_LDPC_ENC_R12 +H adi_library/util_cic/cic_comb.v /^ localparam H = DATA_WIDTH - STAGE_WIDTH * j - 1;$/;" c module:cic_comb +H adi_library/util_cic/cic_int.v /^ localparam H = DATA_WIDTH - STAGE_WIDTH * i - 1;$/;" c module:cic_int +HAS_DEST_ADDR adi_library/axi_dmac/axi_dmac.v /^localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM;$/;" c module:axi_dmac +HAS_DEST_ADDR adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter HAS_DEST_ADDR = 1,$/;" c module:axi_dmac_regmap +HAS_DEST_ADDR adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter HAS_DEST_ADDR = 1,$/;" c module:axi_dmac_regmap_request +HAS_SRC_ADDR adi_library/axi_dmac/axi_dmac.v /^localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM;$/;" c module:axi_dmac +HAS_SRC_ADDR adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter HAS_SRC_ADDR = 1,$/;" c module:axi_dmac_regmap +HAS_SRC_ADDR adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter HAS_SRC_ADDR = 1,$/;" c module:axi_dmac_regmap_request +I hdl/MagnitudeEstimator.v /^ input [VEC_WIDTH-1:0] I,$/;" p module:MagnitudeEstimator +IBUF_inst adi_library/xilinx/common/ad_serdes_clk.v /^ IBUF IBUF_inst ($/;" i module:ad_serdes_clk typeref:module:IBUF +ID adi_library/axi_dmac/axi_dmac.v /^ parameter ID = 0,$/;" c module:axi_dmac +ID adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter ID = 0,$/;" c module:axi_dmac_regmap +ID adi_library/common/up_adc_common.v /^ parameter ID = 0,$/;" c module:up_adc_common +ID adi_library/common/up_clkgen.v /^ parameter ID = 0,$/;" c module:up_clkgen +ID adi_library/common/up_dac_common.v /^ parameter ID = 0,$/;" c module:up_dac_common +ID adi_library/common/up_hdmi_rx.v /^ parameter ID = 0) ($/;" c module:up_hdmi_rx +ID adi_library/common/up_hdmi_tx.v /^ parameter ID = 0) ($/;" c module:up_hdmi_tx +ID adi_library/common/up_pmod.v /^ parameter ID = 0) ($/;" c module:up_pmod +ID adi_library/common/up_tdd_cntrl.v /^ parameter ID = 0,$/;" c module:up_tdd_cntrl +ID adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter ID = 0,$/;" c module:axi_spi_engine +ID adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter integer ID = 0,$/;" c module:axi_adxcvr +ID adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter integer ID = 0,$/;" c module:axi_adxcvr_up +IDELAY_VALUE adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ parameter IDELAY_VALUE = 18,$/;" c module:util_gmii_to_rgmii +IDLE adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ localparam IDLE = 2'b01;$/;" c module:mdc_mdio +IDLE adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam IDLE = 5'b00001;$/;" c module:axi_dacfifo_rd +IDLE adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam IDLE = 9'b000000001;$/;" c module:axi_dacfifo_wr +IDLE_TIMEOUT adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ parameter IDLE_TIMEOUT = 63 ) ($/;" c module:util_sigma_delta_spi +ID_WIDTH adi_library/axi_dmac/address_generator.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_address_generator +ID_WIDTH adi_library/axi_dmac/axi_dmac.v /^localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 :$/;" c module:axi_dmac +ID_WIDTH adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter ID_WIDTH = 3,$/;" c module:axi_dmac_burst_memory +ID_WIDTH adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter ID_WIDTH = $clog2(FIFO_SIZE*2),$/;" c module:axi_dmac_transfer +ID_WIDTH adi_library/axi_dmac/data_mover.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_data_mover +ID_WIDTH adi_library/axi_dmac/dest_axi_mm.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_dest_mm_axi +ID_WIDTH adi_library/axi_dmac/dest_axi_stream.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_dest_axi_stream +ID_WIDTH adi_library/axi_dmac/dest_fifo_inf.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_dest_fifo_inf +ID_WIDTH adi_library/axi_dmac/request_arb.v /^ parameter ID_WIDTH = $clog2(FIFO_SIZE*2),$/;" c module:dmac_request_arb +ID_WIDTH adi_library/axi_dmac/request_generator.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_request_generator +ID_WIDTH adi_library/axi_dmac/response_generator.v /^ parameter ID_WIDTH = 3)($/;" c module:dmac_response_generator +ID_WIDTH adi_library/axi_dmac/response_handler.v /^ parameter ID_WIDTH = 3)($/;" c module:dmac_response_handler +ID_WIDTH adi_library/axi_dmac/src_axi_mm.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_src_mm_axi +ID_WIDTH adi_library/axi_dmac/src_axi_stream.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_src_axi_stream +ID_WIDTH adi_library/axi_dmac/src_fifo_inf.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_src_fifo_inf +INIT_DELAY adi_library/common/up_delay_cntrl.v /^ parameter INIT_DELAY = 0,$/;" c module:up_delay_cntrl +INPUT_DATA_WIDTH hdl/enc_control.v /^ parameter INPUT_DATA_WIDTH = 32$/;" c module:enc_control +INPUT_WIDTH hdl/width_convert.v /^ parameter INPUT_WIDTH = 16,$/;" c module:width_convert +IODELAY_CTRL adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ parameter IODELAY_CTRL = 1'b0,$/;" c module:util_gmii_to_rgmii +IODELAY_CTRL adi_library/xilinx/common/ad_data_in.v /^ parameter IODELAY_CTRL = 0,$/;" c module:ad_data_in +IODELAY_CTRL adi_library/xilinx/common/ad_data_out.v /^ parameter IODELAY_CTRL = 0,$/;" c module:ad_data_out +IODELAY_CTRL adi_library/xilinx/common/ad_serdes_in.v /^ parameter IODELAY_CTRL = 0,$/;" c module:ad_serdes_in +IODELAY_CTRL_ENABLED adi_library/xilinx/common/ad_data_in.v /^ localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;$/;" c module:ad_data_in +IODELAY_CTRL_ENABLED adi_library/xilinx/common/ad_data_out.v /^ localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;$/;" c module:ad_data_out +IODELAY_CTRL_SIM_DEVICE adi_library/xilinx/common/ad_data_in.v /^ localparam IODELAY_CTRL_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE" :$/;" c module:ad_data_in +IODELAY_CTRL_SIM_DEVICE adi_library/xilinx/common/ad_data_out.v /^ localparam IODELAY_CTRL_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE" :$/;" c module:ad_data_out +IODELAY_ENABLE adi_library/xilinx/common/ad_data_in.v /^ parameter IODELAY_ENABLE = 1,$/;" c module:ad_data_in +IODELAY_ENABLE adi_library/xilinx/common/ad_data_out.v /^ parameter IODELAY_ENABLE = 0,$/;" c module:ad_data_out +IODELAY_FPGA_TECHNOLOGY adi_library/xilinx/common/ad_data_in.v /^ localparam IODELAY_FPGA_TECHNOLOGY = (IODELAY_ENABLE == 1) ? FPGA_TECHNOLOGY : NONE;$/;" c module:ad_data_in +IODELAY_FPGA_TECHNOLOGY adi_library/xilinx/common/ad_data_out.v /^ localparam IODELAY_FPGA_TECHNOLOGY = (IODELAY_ENABLE == 1) ? FPGA_TECHNOLOGY : NONE;$/;" c module:ad_data_out +IODELAY_GROUP adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ parameter IODELAY_GROUP = "if_delay_group",$/;" c module:util_gmii_to_rgmii +IODELAY_GROUP adi_library/xilinx/common/ad_data_in.v /^ parameter IODELAY_GROUP = "dev_if_delay_group",$/;" c module:ad_data_in +IODELAY_GROUP adi_library/xilinx/common/ad_data_out.v /^ parameter IODELAY_GROUP = "dev_if_delay_group",$/;" c module:ad_data_out +IODELAY_GROUP adi_library/xilinx/common/ad_serdes_in.v /^ parameter IODELAY_GROUP = "dev_if_delay_group",$/;" c module:ad_serdes_in +IODELAY_SIM_DEVICE adi_library/xilinx/common/ad_data_in.v /^ localparam IODELAY_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" :$/;" c module:ad_data_in +IODELAY_SIM_DEVICE adi_library/xilinx/common/ad_data_out.v /^ localparam IODELAY_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS_ES1" /;" c module:ad_data_out +IQCORRECTION_DISABLE adi_library/common/up_adc_channel.v /^ parameter IQCORRECTION_DISABLE = 0) ($/;" c module:up_adc_channel +IQCORRECTION_DISABLE adi_library/common/up_dac_channel.v /^ parameter IQCORRECTION_DISABLE = 0) ($/;" c module:up_dac_channel +IQmerge hdl/IQmerge.v /^module IQmerge($/;" m +IQmerge hdl/RecvTop.v /^ IQmerge IQmerge ($/;" i module:RecvTop typeref:module:IQmerge +IQmergedout hdl/RecvTop.v /^ wire [7:0] IQmergedout;$/;" n module:RecvTop +IQmergerdy hdl/RecvTop.v /^ wire IQmergerdy;$/;" n module:RecvTop +Interp_half hdl/Interp_half.v /^module Interp_half($/;" m +Interp_halfi hdl/Interpolation.v /^ Interp_half Interp_halfi (.clk(clk), .din_p1(dini_p1), .din_t0(dini_t0), .din_n1(dini_n1), .din/;" i module:Interpolation typeref:module:Interp_half +Interp_halfq hdl/Interpolation.v /^ Interp_half Interp_halfq (.clk(clk), .din_p1(dinq_p1), .din_t0(dinq_t0), .din_n1(dinq_n1), .din/;" i module:Interpolation typeref:module:Interp_half +Interp_quarter hdl/Interp_quarter.v /^module Interp_quarter($/;" m +Interp_quarteri hdl/Interpolation.v /^ Interp_quarter Interp_quarteri (.clk(clk), .din_p1(dini_p1), .din_t0(dini_t0), .din_n1(dini_n1)/;" i module:Interpolation typeref:module:Interp_quarter +Interp_quarteri3 hdl/Interpolation.v /^ Interp_quarter Interp_quarteri3 (.clk(clk), .din_p1(dini_n2), .din_t0(dini_n1), .din_n1(dini_t0/;" i module:Interpolation typeref:module:Interp_quarter +Interp_quarterq hdl/Interpolation.v /^ Interp_quarter Interp_quarterq (.clk(clk), .din_p1(dinq_p1), .din_t0(dinq_t0), .din_n1(dinq_n1)/;" i module:Interpolation typeref:module:Interp_quarter +Interp_quarterq3 hdl/Interpolation.v /^ Interp_quarter Interp_quarterq3 (.clk(clk), .din_p1(dinq_n2), .din_t0(dinq_n1), .din_n1(dinq_t0/;" i module:Interpolation typeref:module:Interp_quarter +InterpdoutiA hdl/TimeSync_top.v /^ wire [9:0] InterpdoutiA;$/;" n module:TimeSync_top +InterpdoutiB hdl/TimeSync_top.v /^ wire [9:0] InterpdoutiB;$/;" n module:TimeSync_top +InterpdoutiC hdl/TimeSync_top.v /^ wire [9:0] InterpdoutiC;$/;" n module:TimeSync_top +InterpdoutiD hdl/TimeSync_top.v /^ wire [9:0] InterpdoutiD;$/;" n module:TimeSync_top +InterpdoutqA hdl/TimeSync_top.v /^ wire [9:0] InterpdoutqA;$/;" n module:TimeSync_top +InterpdoutqB hdl/TimeSync_top.v /^ wire [9:0] InterpdoutqB;$/;" n module:TimeSync_top +InterpdoutqC hdl/TimeSync_top.v /^ wire [9:0] InterpdoutqC;$/;" n module:TimeSync_top +InterpdoutqD hdl/TimeSync_top.v /^ wire [9:0] InterpdoutqD;$/;" n module:TimeSync_top +Interpolation hdl/Interpolation.v /^module Interpolation($/;" m +Interpolation hdl/TimeSync_top.v /^ Interpolation Interpolation ($/;" i module:TimeSync_top typeref:module:Interpolation +IntpARdy hdl/RecvTop.v /^ output IntpARdy, \/\/TSync输出nd$/;" p module:RecvTop +IntpOuti hdl/RecvTop.v /^ output [ 9:0] IntpOuti, \/\/TSync输出$/;" p module:RecvTop +IntpOutq hdl/RecvTop.v /^ output [ 9:0] IntpOutq,$/;" p module:RecvTop +L adi_library/util_cic/cic_comb.v /^ localparam L = k == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (j+1);$/;" c module:cic_comb +L adi_library/util_cic/cic_int.v /^ localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1);$/;" c module:cic_int +LDPC_Dout hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output [0:0] LDPC_Dout, \/\/译码输出信号,MSB输出$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_Dout hdl/RecvTop.v /^ wire LDPC_Dout;$/;" n module:RecvTop +LDPC_Dout_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [0:0] LDPC_Dout_A;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_Dout_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [0:0] LDPC_Dout_B;$/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_Rdy hdl/RecvTop.v /^ wire LDPC_Rdy;$/;" n module:RecvTop +LDPC_SyncOut hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output LDPC_SyncOut, \/\/LDPC 模块帧同步输出信号,高脉冲,指示帧起点$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_SyncOut hdl/RecvTop.v /^ wire LDPC_SyncOut;$/;" n module:RecvTop +LDPC_SyncOut_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire LDPC_SyncOut_A; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_SyncOut_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire LDPC_SyncOut_B; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LDPC_decode hdl/RecvTop.v /^ CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode ($/;" i module:RecvTop typeref:module:CCSDS_LDPC_DEC_K1024_R12_TOPP +LENGTH_ALIGN adi_library/axi_dmac/tb/regmap_tb.v /^ localparam LENGTH_ALIGN = 2;$/;" c module:dmac_regmap_tb +LENGTH_ALIGN_MASK adi_library/axi_dmac/tb/regmap_tb.v /^ localparam LENGTH_ALIGN_MASK = {LENGTH_ALIGN{1'b1}};$/;" c module:dmac_regmap_tb +LENGTH_MASK adi_library/axi_dmac/tb/regmap_tb.v /^ localparam LENGTH_MASK = {DMA_LENGTH_WIDTH{1'b1}};$/;" c module:dmac_regmap_tb +LENGTH_WIDTH adi_library/axi_dmac/address_generator.v /^ parameter LENGTH_WIDTH = 8)($/;" c module:dmac_address_generator +LENGTH_WIDTH adi_library/axi_dmac/src_axi_stream.v /^ parameter LENGTH_WIDTH = 24,$/;" c module:dmac_src_axi_stream +LPM_OR_DFE_N adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter LPM_OR_DFE_N = 1,$/;" c module:axi_adxcvr +LPM_OR_DFE_N adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter LPM_OR_DFE_N = 1,$/;" c module:axi_adxcvr_up +LUT_FSCALE adi_library/common/ad_dds_sine_cordic.v /^ localparam LUT_FSCALE = 1 << (PHASE_DW);$/;" c module:ad_dds_sine_cordic +MAG_WIDTH hdl/PAPR.v /^ parameter MAG_WIDTH = 22,$/;" c module:PAPR +MASTER_DATA_WIDTH adi_library/util_axis_resize/util_axis_resize.v /^ parameter MASTER_DATA_WIDTH = 64,$/;" c module:util_axis_resize +MAX_BEATS_PER_BURST adi_library/axi_dmac/address_generator.v /^localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}};$/;" c module:dmac_address_generator +MAX_BYTES_PER_BURST adi_library/axi_dmac/axi_dmac.v /^ parameter MAX_BYTES_PER_BURST = 128,$/;" c module:axi_dmac +MAX_BYTES_PER_BURST adi_library/axi_dmac/axi_dmac_burst_memory.v /^ parameter MAX_BYTES_PER_BURST = 128,$/;" c module:axi_dmac_burst_memory +MAX_BYTES_PER_BURST adi_library/axi_dmac/axi_dmac_transfer.v /^ parameter MAX_BYTES_PER_BURST = 128,$/;" c module:axi_dmac_transfer +MAX_BYTES_PER_BURST adi_library/axi_dmac/dest_axi_mm.v /^ parameter MAX_BYTES_PER_BURST = 128,$/;" c module:dmac_dest_mm_axi +MAX_BYTES_PER_BURST adi_library/axi_dmac/request_arb.v /^ parameter MAX_BYTES_PER_BURST = 128,$/;" c module:dmac_request_arb +MAX_DEPTH adi_library/util_var_fifo/util_var_fifo.v /^ localparam MAX_DEPTH = (2 ** ADDRESS_WIDTH) - 1;$/;" c module:util_var_fifo +MAX_ITER_NUM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ parameter MAX_ITER_NUM = 6'd14, \/\/最大迭代次数常量 /;" c module:CCSDS_LDPC_DEC_K1024_R12_TOPP +MAX_LATENCY adi_library/axi_dmac/tb/axi_read_slave.v /^ parameter MAX_LATENCY = 48$/;" c module:axi_read_slave +MAX_LATENCY adi_library/axi_dmac/tb/axi_slave.v /^ parameter MAX_LATENCY = 32$/;" c module:axi_slave +MAX_LENGTH adi_library/axi_dmac/address_generator.v /^localparam MAX_LENGTH = {BEATS_PER_BURST_WIDTH{1'b1}};$/;" c module:dmac_address_generator +MAX_ROOM adi_library/util_axis_fifo/address_gray_pipelined.v /^localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};$/;" c module:fifo_address_gray_pipelined +MAX_ROOM adi_library/util_axis_fifo/address_sync.v /^localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};$/;" c module:fifo_address_sync +MAX_WIDTH adi_library/common/ad_mem_asym.v /^ localparam MAX_WIDTH = `max(A_DATA_WIDTH, B_DATA_WIDTH);$/;" c module:ad_mem_asym +MAX_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam MAX_WIDTH = `max(AXI_DATA_WIDTH, DAC_DATA_WIDTH);$/;" c module:axi_dacfifo_rd +MAX_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam MAX_WIDTH = `max(AXI_DATA_WIDTH, DMA_DATA_WIDTH);$/;" c module:axi_dacfifo_wr +MEASURED_LENGTH_WIDTH adi_library/axi_dmac/axi_dmac_regmap_request.v /^localparam MEASURED_LENGTH_WIDTH = (DMA_2D_TRANSFER == 1) ? 32 : DMA_LENGTH_WIDTH;$/;" c module:axi_dmac_regmap_request +MEM_ADDRESS_WIDTH adi_library/common/ad_mem_asym.v /^ localparam MEM_ADDRESS_WIDTH = `max(A_ADDRESS_WIDTH, B_ADDRESS_WIDTH);$/;" c module:ad_mem_asym +MEM_DATA_WIDTH adi_library/common/ad_mem_asym.v /^ localparam MEM_DATA_WIDTH = MIN_WIDTH;$/;" c module:ad_mem_asym +MEM_RATIO adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam MEM_RATIO = DATA_WIDTH_SRC > DATA_WIDTH_DEST ?$/;" c module:axi_dmac_burst_memory +MEM_RATIO adi_library/common/ad_mem_asym.v /^ localparam MEM_RATIO = MAX_WIDTH \/ MIN_WIDTH;$/;" c module:ad_mem_asym +MEM_RATIO adi_library/util_dacfifo/util_dacfifo_bypass.v /^ localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH\/DAC_DATA_WIDTH :$/;" c module:util_dacfifo_bypass +MEM_RATIO adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam MEM_RATIO = MAX_WIDTH\/MIN_WIDTH;$/;" c module:axi_dacfifo_rd +MEM_RATIO adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam MEM_RATIO = MAX_WIDTH\/MIN_WIDTH;$/;" c module:axi_dacfifo_wr +MEM_RATIO_LOG2 adi_library/common/ad_mem_asym.v /^ localparam MEM_RATIO_LOG2 = clog2(MEM_RATIO);$/;" c module:ad_mem_asym +MEM_RATIO_WIDTH adi_library/axi_dmac/axi_dmac_burst_memory.v /^localparam MEM_RATIO_WIDTH =$/;" c module:axi_dmac_burst_memory +MEM_SIZE adi_library/common/ad_mem_asym.v /^ localparam MEM_SIZE = 2 ** MEM_ADDRESS_WIDTH;$/;" c module:ad_mem_asym +MF12p5_12bit_i hdl/MF_Top.v /^ MF12p5_12bit MF12p5_12bit_i ($/;" i module:MF_Top typeref:module:MF12p5_12bit +MF12p5_12bit_q hdl/MF_Top.v /^ MF12p5_12bit MF12p5_12bit_q ($/;" i module:MF_Top typeref:module:MF12p5_12bit +MF_Top hdl/MF_Top.v /^module MF_Top ($/;" m +MF_Top hdl/RecvTop.v /^ MF_Top MF_Top ($/;" i module:RecvTop typeref:module:MF_Top +MF_m_axis_data_tdata_i hdl/MF_Top.v /^ wire [31:0] MF_m_axis_data_tdata_i;$/;" n module:MF_Top +MF_m_axis_data_tdata_q hdl/MF_Top.v /^ wire [31:0] MF_m_axis_data_tdata_q;$/;" n module:MF_Top +MF_rdy hdl/MF_Top.v /^ output reg MF_rdy,$/;" p module:MF_Top +MF_rdy hdl/RecvTop.v /^ wire MF_rdy;$/;" n module:RecvTop +MF_rdy_d1 hdl/MF_Top.v /^ reg MF_rdy_d1;$/;" r module:MF_Top +MF_rst hdl/MF_Top.v /^ output reg MF_rst$/;" p module:MF_Top +MF_rst hdl/RecvTop.v /^ wire MF_rst;$/;" n module:RecvTop +MIN_LATENCY adi_library/axi_dmac/tb/axi_read_slave.v /^ parameter MIN_LATENCY = 48,$/;" c module:axi_read_slave +MIN_LATENCY adi_library/axi_dmac/tb/axi_slave.v /^ parameter MIN_LATENCY = 16,$/;" c module:axi_slave +MIN_STAGE adi_library/util_pack/util_pack_common/pack_ctrl.v /^ parameter MIN_STAGE = 0,$/;" c module:pack_ctrl +MIN_STAGE adi_library/util_pack/util_pack_common/pack_network.v /^ parameter MIN_STAGE = 1,$/;" c module:pack_network +MIN_STAGE adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam MIN_STAGE = PACK ? (i == 0 ? SAMPLE_ADDRESS_WIDTH % 2 : 0) :$/;" c block:pack_shell.gen_network +MIN_WIDTH adi_library/common/ad_mem_asym.v /^ localparam MIN_WIDTH = `min(A_DATA_WIDTH, B_DATA_WIDTH);$/;" c module:ad_mem_asym +MIN_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam MIN_WIDTH = `min(AXI_DATA_WIDTH, DAC_DATA_WIDTH);$/;" c module:axi_dacfifo_rd +MIN_WIDTH adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam MIN_WIDTH = `min(AXI_DATA_WIDTH, DMA_DATA_WIDTH);$/;" c module:axi_dacfifo_wr +MISC_SLEEP adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam MISC_SLEEP = 1'b1;$/;" c module:spi_engine_execution +MISC_SYNC adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam MISC_SYNC = 1'b0;$/;" c module:spi_engine_execution +MMCM_CLK0_DIV adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_CLK0_DIV = 2.000,$/;" c module:ad_mmcm_drp +MMCM_CLK0_DIV adi_library/xilinx/common/ad_serdes_clk.v /^ parameter MMCM_CLK0_DIV = 2.000,$/;" c module:ad_serdes_clk +MMCM_CLK0_PHASE adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_CLK0_PHASE = 0.000,$/;" c module:ad_mmcm_drp +MMCM_CLK1_DIV adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_CLK1_DIV = 6,$/;" c module:ad_mmcm_drp +MMCM_CLK1_DIV adi_library/xilinx/common/ad_serdes_clk.v /^ parameter MMCM_CLK1_DIV = 6) ($/;" c module:ad_serdes_clk +MMCM_CLK1_PHASE adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_CLK1_PHASE = 0.000,$/;" c module:ad_mmcm_drp +MMCM_CLK2_DIV adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_CLK2_DIV = 2.000,$/;" c module:ad_mmcm_drp +MMCM_CLK2_PHASE adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_CLK2_PHASE = 0.000) ($/;" c module:ad_mmcm_drp +MMCM_CLKIN2_PERIOD adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_CLKIN2_PERIOD = 1.667,$/;" c module:ad_mmcm_drp +MMCM_CLKIN_PERIOD adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_CLKIN_PERIOD = 1.667,$/;" c module:ad_mmcm_drp +MMCM_CLKIN_PERIOD adi_library/xilinx/common/ad_serdes_clk.v /^ parameter MMCM_CLKIN_PERIOD = 1.667,$/;" c module:ad_serdes_clk +MMCM_OR_BUFR_N adi_library/xilinx/common/ad_serdes_clk.v /^ parameter MMCM_OR_BUFR_N = 1,$/;" c module:ad_serdes_clk +MMCM_VCO_DIV adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_VCO_DIV = 6,$/;" c module:ad_mmcm_drp +MMCM_VCO_DIV adi_library/xilinx/common/ad_serdes_clk.v /^ parameter MMCM_VCO_DIV = 6,$/;" c module:ad_serdes_clk +MMCM_VCO_MUL adi_library/xilinx/common/ad_mmcm_drp.v /^ parameter MMCM_VCO_MUL = 12.000,$/;" c module:ad_mmcm_drp +MMCM_VCO_MUL adi_library/xilinx/common/ad_serdes_clk.v /^ parameter MMCM_VCO_MUL = 12.000,$/;" c module:ad_serdes_clk +MM_IF_TYPE adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter MM_IF_TYPE = 0,$/;" c module:axi_spi_engine +MODULE_VERSION hdl/phy_control.v /^ localparam MODULE_VERSION = 'h000001;$/;" c module:phy_control +MSB_WIDTH adi_library/common/util_axis_upscale.v /^ localparam MSB_WIDTH = UDATA_WIDTH - DATA_WIDTH;$/;" c module:util_axis_upscale +MUL_COEF_DW adi_library/common/ad_csc.v /^ parameter MUL_COEF_DW = 17,$/;" c module:ad_csc +MUL_DW adi_library/common/ad_csc.v /^ localparam MUL_DW = MUL_COEF_DW + PIXEL_WD -1;$/;" c module:ad_csc +MUX_ORDER adi_library/util_pack/util_pack_common/pack_ctrl.v /^ parameter MUX_ORDER = 1,$/;" c module:pack_ctrl +MUX_ORDER adi_library/util_pack/util_pack_common/pack_interconnect.v /^ parameter MUX_ORDER = 2,$/;" c module:pack_interconnect +MUX_ORDER adi_library/util_pack/util_pack_common/pack_network.v /^ parameter MUX_ORDER = 1,$/;" c module:pack_network +MUX_ORDER adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam MUX_ORDER = i == 0 ? 2 : 1;$/;" c block:pack_shell.gen_network +M_MEM_RATIO adi_library/util_rfifo/util_rfifo.v /^ localparam M_MEM_RATIO = DOUT_DATA_WIDTH\/DIN_DATA_WIDTH;$/;" c module:util_rfifo +M_MEM_RATIO adi_library/util_wfifo/util_wfifo.v /^ localparam M_MEM_RATIO = DOUT_DATA_WIDTH\/DIN_DATA_WIDTH;$/;" c module:util_wfifo +M_SEQ hdl/frame_sync.v /^ parameter [511:0] M_SEQ =512'b11111111100001111011100001011001101101111010000111001100001001/;" c module:frame_sync +M_SEQ_REVERSE hdl/frame_sync.v /^ parameter [511:0] M_SEQ_REVERSE =512'b000000111101111100010111001100100000100101001110110100/;" c module:frame_sync +MagnitudeEstimator hdl/MagnitudeEstimator.v /^module MagnitudeEstimator #($/;" m +MultFreq hdl/DDS_compensate.v /^ComplexMult12x12_4dly MultFreq ($/;" i module:DDS_compensate typeref:module:ComplexMult12x12_4dly +Multouti01 hdl/freqestm.v /^ wire [20:0] Multouti01;$/;" n module:freqestm +Multouti01_head hdl/freqestm.v /^ wire [ 2:0] Multouti01_head;$/;" n module:freqestm +Multoutq01 hdl/freqestm.v /^ wire [20:0] Multoutq01;$/;" n module:freqestm +Multoutq01_head hdl/freqestm.v /^ wire [ 2:0] Multoutq01_head;$/;" n module:freqestm +ND hdl/ApproxAbs_18bit.v /^ input ND,$/;" p module:ApproxAbs_18bit +ND hdl/ApproxAbs_v2.v /^ input ND,$/;" p module:ApproxAbs_v2 +ND hdl/DAGC_v2.v /^ reg ND = 1'd0;$/;" r module:DAGC_v2 +NEG_EDGE adi_library/common/ad_edge_detect.v /^ localparam NEG_EDGE = 1;$/;" c module:ad_edge_detect +NONE adi_library/xilinx/common/ad_data_in.v /^ localparam NONE = -1;$/;" c module:ad_data_in +NONE adi_library/xilinx/common/ad_data_out.v /^ localparam NONE = -1;$/;" c module:ad_data_out +NON_POWER_OF_TWO adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam NON_POWER_OF_TWO = NUM_OF_CHANNELS > 2;$/;" c module:pack_shell +NUM_GROUPS adi_library/common/ad_perfect_shuffle.v /^ parameter NUM_GROUPS = 2,$/;" c module:ad_perfect_shuffle +NUM_M adi_library/axi_dmac/splitter.v /^ parameter NUM_M = 2)($/;" c module:splitter +NUM_OFFLOAD adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter NUM_OFFLOAD = 0,$/;" c module:axi_spi_engine +NUM_OF_BITS adi_library/util_cdc/sync_bits.v /^ parameter NUM_OF_BITS = 1,$/;" c module:sync_bits +NUM_OF_BITS adi_library/util_cdc/sync_data.v /^ parameter NUM_OF_BITS = 1,$/;" c module:sync_data +NUM_OF_CHANNELS adi_library/common/util_axis_upscale.v /^ parameter NUM_OF_CHANNELS = 4,$/;" c module:util_axis_upscale +NUM_OF_CHANNELS adi_library/util_bsplit/util_bsplit.v /^ parameter NUM_OF_CHANNELS = 8) ($/;" c module:util_bsplit +NUM_OF_CHANNELS adi_library/util_extract/util_extract.v /^ parameter NUM_OF_CHANNELS = 2,$/;" c module:util_extract +NUM_OF_CHANNELS adi_library/util_mfifo/util_mfifo.v /^ parameter NUM_OF_CHANNELS = 4,$/;" c module:util_mfifo +NUM_OF_CHANNELS adi_library/util_pack/tb/cpack_tb.v /^ parameter NUM_OF_CHANNELS = 4;$/;" c module:cpack_tb +NUM_OF_CHANNELS adi_library/util_pack/tb/underflow_tb.v /^ parameter NUM_OF_CHANNELS = 8;$/;" c module:upack2_underflow_tb +NUM_OF_CHANNELS adi_library/util_pack/tb/upack_tb.v /^ parameter NUM_OF_CHANNELS = 8;$/;" c module:upack_tb +NUM_OF_CHANNELS adi_library/util_pack/util_cpack2/util_cpack2.v /^ parameter NUM_OF_CHANNELS = 4,$/;" c module:util_cpack2 +NUM_OF_CHANNELS adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ parameter NUM_OF_CHANNELS = 4,$/;" c module:util_cpack2_impl +NUM_OF_CHANNELS adi_library/util_pack/util_pack_common/pack_shell.v /^ parameter NUM_OF_CHANNELS = 4,$/;" c module:pack_shell +NUM_OF_CHANNELS adi_library/util_pack/util_upack2/util_upack2.v /^ parameter NUM_OF_CHANNELS = 4,$/;" c module:util_upack2 +NUM_OF_CHANNELS adi_library/util_pack/util_upack2/util_upack2_impl.v /^ parameter NUM_OF_CHANNELS = 4,$/;" c module:util_upack2_impl +NUM_OF_CHANNELS adi_library/util_rfifo/util_rfifo.v /^ parameter NUM_OF_CHANNELS = 4,$/;" c module:util_rfifo +NUM_OF_CHANNELS adi_library/util_wfifo/util_wfifo.v /^ parameter NUM_OF_CHANNELS = 4,$/;" c module:util_wfifo +NUM_OF_CHANNELS_M adi_library/util_bsplit/util_bsplit.v /^ localparam NUM_OF_CHANNELS_M = 9;$/;" c module:util_bsplit +NUM_OF_CS adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ parameter NUM_OF_CS = 1,$/;" c module:spi_engine_execution +NUM_OF_CS adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ parameter NUM_OF_CS = 1,$/;" c module:util_sigma_delta_spi +NUM_OF_EVENTS adi_library/util_cdc/sync_event.v /^ parameter NUM_OF_EVENTS = 1,$/;" c module:sync_event +NUM_OF_LANES adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter integer NUM_OF_LANES = 8,$/;" c module:axi_adxcvr +NUM_OF_LANES adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ parameter integer NUM_OF_LANES = 8;$/;" c module:axi_adxcvr_mdrp +NUM_OF_LANES adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ parameter integer NUM_OF_LANES = 8;$/;" c module:axi_adxcvr_mstatus +NUM_OF_LANES adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter integer NUM_OF_LANES = 8,$/;" c module:axi_adxcvr_up +NUM_OF_LANES adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ parameter NUM_OF_LANES = 1,$/;" c module:axi_xcvrlb +NUM_OF_LANES adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ localparam integer NUM_OF_LANES = (TX_NUM_OF_LANES > RX_NUM_OF_LANES) ?$/;" c module:util_adxcvr +NUM_OF_PORTS adi_library/util_pack/tb/cpack_tb.v /^ localparam NUM_OF_PORTS = SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;$/;" c module:cpack_tb +NUM_OF_PORTS adi_library/util_pack/tb/underflow_tb.v /^ localparam NUM_OF_PORTS = SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;$/;" c module:upack2_underflow_tb +NUM_OF_PORTS adi_library/util_pack/tb/upack_tb.v /^ localparam NUM_OF_PORTS = SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;$/;" c module:upack_tb +NUM_OF_PORTS adi_library/util_pack/util_pack_common/pack_ctrl.v /^ localparam NUM_OF_PORTS = 2**PORT_ADDRESS_WIDTH;$/;" c module:pack_ctrl +NUM_OF_SAMPLES adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam NUM_OF_SAMPLES = NUM_OF_CHANNELS * SAMPLES_PER_CHANNEL;$/;" c module:pack_shell +NUM_OF_SDI adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter [ 7:0] NUM_OF_SDI = 1 ) ($/;" c module:axi_spi_engine +NUM_OF_SDI adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ parameter NUM_OF_SDI = 1,$/;" c module:spi_engine_execution +NUM_OF_SDI adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ parameter NUM_OF_SDI = 1 ) ($/;" c module:spi_engine_interconnect +NUM_OF_SDI adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ parameter NUM_OF_SDI = 1 ) ($/;" c module:spi_engine_offload +NUM_OF_SLAVES adi_library/common/ad_3w_spi.v /^ parameter NUM_OF_SLAVES=8) ($/;" c module:ad_3w_spi +NUM_PORTS adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam NUM_PORTS = 2**PORT_ADDRESS_WIDTH;$/;" c module:pack_interconnect +NUM_REGS adi_library/axi_dmac/tb/regmap_tb.v /^ localparam NUM_REGS = 'h200;$/;" c module:dmac_regmap_tb +NUM_STAGES adi_library/util_cic/cic_comb.v /^ parameter NUM_STAGES = 1$/;" c module:cic_comb +NUM_STAGES adi_library/util_cic/cic_int.v /^ parameter NUM_STAGES = 1$/;" c module:cic_int +NUM_STAGES adi_library/util_pack/util_pack_common/pack_ctrl.v /^ parameter NUM_STAGES = 2,$/;" c module:pack_ctrl +NUM_STAGES adi_library/util_pack/util_pack_common/pack_interconnect.v /^ parameter NUM_STAGES = 2,$/;" c module:pack_interconnect +NUM_STAGES adi_library/util_pack/util_pack_common/pack_network.v /^ parameter NUM_STAGES = 1,$/;" c module:pack_network +NUM_STAGES adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam NUM_STAGES = PACK ? (i == 0 ? SAMPLE_ADDRESS_WIDTH \/ 2 : SAMPLE_ADDRESS_WIDT/;" c block:pack_shell.gen_network +NUM_SWITCHES adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam NUM_SWITCHES = NUM_PORTS \/ z;$/;" c module:pack_interconnect +Nd hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input Nd, \/\/译码输入数据有效标志,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Nd_A_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Nd_A_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Nd_B_TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Nd_B_TM; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Noise_Estimate hdl/Noise_Estimate.v /^module Noise_Estimate($/;" m +Noise_Estimate_djy hdl/SC_FDE_TOP.v /^ Noise_Estimate Noise_Estimate_djy ($/;" i module:SC_FDE_TOP typeref:module:Noise_Estimate +OCTETS_PER_BEAT adi_library/common/ad_xcvr_rx_if.v /^ parameter OCTETS_PER_BEAT = 4,$/;" c module:ad_xcvr_rx_if +OCTETS_PER_SAMPLE adi_library/common/ad_datafmt.v /^ parameter OCTETS_PER_SAMPLE = 2,$/;" c module:ad_datafmt +OFF adi_library/common/ad_tdd_control.v /^ localparam [ 0:0] OFF = 0;$/;" c module:ad_tdd_control +OFFLOAD0_CMD_MEM_ADDRESS_WIDTH adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4,$/;" c module:axi_spi_engine +OFFLOAD0_SDO_MEM_ADDRESS_WIDTH adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,$/;" c module:axi_spi_engine +ON adi_library/common/ad_tdd_control.v /^ localparam [ 0:0] ON = 1;$/;" c module:ad_tdd_control +OOS_THRESHOLD adi_library/common/ad_pnmon.v /^ parameter OOS_THRESHOLD = 16,$/;" c module:ad_pnmon +OUTPUT_WIDTH hdl/width_convert.v /^ parameter OUTPUT_WIDTH = 2$/;" c module:width_convert +OUT_CLK_SEL adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [ 2:0] OUT_CLK_SEL = 3'd4) ($/;" c module:axi_adxcvr +OUT_CLK_SEL adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 2:0] OUT_CLK_SEL = 3'd4) ($/;" c module:axi_adxcvr_up +OUT_ONLY_INFORMATION hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ parameter OUT_ONLY_INFORMATION = 1'b0 \/\/译码输出格式选择标志，1:只输出/;" c module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Out_Info_bit hdl/CCSDS_LDPC_ENC_R12.v /^ reg Out_Info_bit = 1'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +Out_Process_R12 hdl/CCSDS_LDPC_ENC_R12.v /^ Out_Process_R12 Out_Process_R12($/;" i module:CCSDS_LDPC_ENC_R12 typeref:module:Out_Process_R12 +Out_Process_R12 hdl/Out_Process_R12.v /^module Out_Process_R12($/;" m +PACK adi_library/util_pack/util_pack_common/pack_ctrl.v /^ parameter PACK = 0$/;" c module:pack_ctrl +PACK adi_library/util_pack/util_pack_common/pack_interconnect.v /^ parameter PACK = 0 \/\/ 0 = Unpack, 1 = Pack$/;" c module:pack_interconnect +PACK adi_library/util_pack/util_pack_common/pack_network.v /^ parameter PACK = 0,$/;" c module:pack_network +PACK adi_library/util_pack/util_pack_common/pack_shell.v /^ parameter PACK = 0$/;" c module:pack_shell +PAPR hdl/PAPR.v /^module PAPR #($/;" m +PCORE_VERSION adi_library/axi_dmac/axi_dmac_regmap.v /^localparam PCORE_VERSION = 'h00040361;$/;" c module:axi_dmac_regmap +PCORE_VERSION adi_library/common/up_clkgen.v /^ localparam PCORE_VERSION = 32'h00050063;$/;" c module:up_clkgen +PCORE_VERSION adi_library/common/up_hdmi_rx.v /^ localparam PCORE_VERSION = 32'h00040063;$/;" c module:up_hdmi_rx +PCORE_VERSION adi_library/common/up_hdmi_tx.v /^ localparam PCORE_VERSION = 32'h00040063;$/;" c module:up_hdmi_tx +PCORE_VERSION adi_library/common/up_pmod.v /^ localparam PCORE_VERSION = 32'h00010001;$/;" c module:up_pmod +PCORE_VERSION adi_library/common/up_tdd_cntrl.v /^ localparam PCORE_VERSION = 32'h00010061;$/;" c module:up_tdd_cntrl +PCORE_VERSION adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ localparam PCORE_VERSION = 'h010071;$/;" c module:axi_spi_engine +PHASE1_LEN hdl/Transmitter.v /^ parameter PHASE1_LEN = 2112, \/\/ (8 cp + 256 sym)* 8 ( total 2048 valid sym)$/;" c module:Transmitter +PHASE_DW adi_library/common/ad_dds.v /^ parameter PHASE_DW = 16,$/;" c module:ad_dds +PHASE_DW adi_library/common/ad_dds_2.v /^ parameter PHASE_DW = 16,$/;" c module:ad_dds_2 +PHASE_DW adi_library/common/ad_dds_sine_cordic.v /^ parameter PHASE_DW = 16,$/;" c module:ad_dds_sine_cordic +PHY_AD adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ parameter PHY_AD = 5'b10000) ($/;" c module:mdc_mdio +PHY_AD adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ parameter PHY_AD = 5'b10000,$/;" c module:util_gmii_to_rgmii +PHY_CR hdl/phy_control.v /^ localparam integer PHY_CR = 'h00000000 >> 2; \/\/ RW$/;" c module:phy_control +PHY_SR hdl/phy_control.v /^ localparam integer PHY_SR = 'h00000004 >> 2; \/\/ RW$/;" c module:phy_control +PIXEL_WD adi_library/common/ad_csc.v /^ localparam PIXEL_WD = 9; \/\/ sign extended$/;" c module:ad_csc +PN_W adi_library/common/ad_pngen.v /^ localparam PN_W = DW > POL_W ? DW : POL_W;$/;" c module:ad_pngen +POLYNOMIAL adi_library/common/ad_dds_2.v /^ localparam POLYNOMIAL = 2;$/;" c module:ad_dds_2 +POL_MASK adi_library/common/ad_pngen.v /^ parameter POL_MASK = 32'b0000_0000_0000_0000_0000_0000_1100_0000,$/;" c module:ad_pngen +POL_W adi_library/common/ad_pngen.v /^ parameter POL_W = 7,$/;" c module:ad_pngen +PORT_ADDRESS_WIDTH adi_library/util_pack/util_pack_common/pack_ctrl.v /^ parameter PORT_ADDRESS_WIDTH = 2,$/;" c module:pack_ctrl +PORT_ADDRESS_WIDTH adi_library/util_pack/util_pack_common/pack_interconnect.v /^ parameter PORT_ADDRESS_WIDTH = 3,$/;" c module:pack_interconnect +PORT_ADDRESS_WIDTH adi_library/util_pack/util_pack_common/pack_network.v /^ parameter PORT_ADDRESS_WIDTH = 1,$/;" c module:pack_network +PORT_DATA_WIDTH adi_library/util_pack/util_pack_common/pack_interconnect.v /^ parameter PORT_DATA_WIDTH = 16,$/;" c module:pack_interconnect +PORT_DATA_WIDTH adi_library/util_pack/util_pack_common/pack_network.v /^ parameter PORT_DATA_WIDTH = 16$/;" c module:pack_network +POR_CFG adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] POR_CFG = 16'b0000000000000110,$/;" c module:util_adxcvr +POR_CFG adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] POR_CFG = 16'b0000000000000110,$/;" c module:util_adxcvr_xcm +POS_EDGE adi_library/common/ad_edge_detect.v /^ localparam POS_EDGE = 0;$/;" c module:ad_edge_detect +PPF0_CFG adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] PPF0_CFG = 16'b0000011000000000,$/;" c module:util_adxcvr +PPF0_CFG adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] PPF0_CFG = 16'b0000011000000000,$/;" c module:util_adxcvr_xcm +PREFIX_LEN hdl/Transmitter.v /^ parameter PREFIX_LEN = 8,$/;" c module:Transmitter +PREFIX_LEN hdl/add_prefix.v /^ parameter PREFIX_LEN = 8$/;" c module:add_prefix +PREIQ_FREQ_BST adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer PREIQ_FREQ_BST = 0,$/;" c module:util_adxcvr +PREIQ_FREQ_BST adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer PREIQ_FREQ_BST = 0,$/;" c module:util_adxcvr_xch +PULSE_PERIOD adi_library/common/util_pulse_gen.v /^ parameter PULSE_PERIOD = 100000000)( \/\/ t_period * clk_freq$/;" c module:util_pulse_gen +PULSE_PERIOD hdl/ad9361_mgc_pin_ctrl.v /^ localparam PULSE_PERIOD = 5;$/;" c module:ad9361_mgc_pin_ctrl +PULSE_WIDTH adi_library/common/util_pulse_gen.v /^ parameter PULSE_WIDTH = 7,$/;" c module:util_pulse_gen +P_DW adi_library/common/ad_dds_cordic_pipe.v /^ parameter P_DW = 16,$/;" c module:ad_dds_cordic_pipe +Pilot_rdy hdl/RecvTop.v /^ wire Pilot_rdy;$/;" n module:RecvTop +Pilot_rdy hdl/SCFDE_recv_FrameSync.v /^ output reg Pilot_rdy = 1'b0, \/\/出峰后88个clk后拉高1clk，对齐导频/;" p module:SCFDE_recv_FrameSync +Pilot_rdy_hide1_d1 hdl/RecvTop.v /^ output Pilot_rdy_hide1_d1,$/;" p module:RecvTop +Pilot_rdy_hide1_d1 hdl/SCFDE_recv_FrameSync.v /^ output reg Pilot_rdy_hide1_d1 = 1'b0$/;" p module:SCFDE_recv_FrameSync +Q hdl/MagnitudeEstimator.v /^ input [VEC_WIDTH-1:0] Q,$/;" p module:MagnitudeEstimator +QPLL_CFG adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [26:0] QPLL_CFG = 27'h0680181,$/;" c module:util_adxcvr +QPLL_CFG adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [26:0] QPLL_CFG = 27'h0680181,$/;" c module:util_adxcvr_xcm +QPLL_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] QPLL_CFG0 = 16'b0011001100011100,$/;" c module:util_adxcvr +QPLL_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_CFG0 = 16'b0011001100011100,$/;" c module:util_adxcvr_xcm +QPLL_CFG1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] QPLL_CFG1 = 16'b1101000000111000,$/;" c module:util_adxcvr +QPLL_CFG1 adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_CFG1 = 16'b1101000000111000,$/;" c module:util_adxcvr_xcm +QPLL_CFG1_G3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] QPLL_CFG1_G3 = 16'b1101000000111000,$/;" c module:util_adxcvr +QPLL_CFG1_G3 adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_CFG1_G3 = 16'b1101000000111000,$/;" c module:util_adxcvr_xcm +QPLL_CFG2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] QPLL_CFG2 = 16'b0000111111000000,$/;" c module:util_adxcvr +QPLL_CFG2 adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_CFG2 = 16'b0000111111000000,$/;" c module:util_adxcvr_xcm +QPLL_CFG2_G3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000,$/;" c module:util_adxcvr +QPLL_CFG2_G3 adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000,$/;" c module:util_adxcvr_xcm +QPLL_CFG3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] QPLL_CFG3 = 16'b0000000100100000,$/;" c module:util_adxcvr +QPLL_CFG3 adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_CFG3 = 16'b0000000100100000,$/;" c module:util_adxcvr_xcm +QPLL_CFG4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] QPLL_CFG4 = 16'b0000000000000011,$/;" c module:util_adxcvr +QPLL_CFG4 adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_CFG4 = 16'b0000000000000011,$/;" c module:util_adxcvr_xcm +QPLL_CP adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] QPLL_CP = 10'b0001111111,$/;" c module:util_adxcvr +QPLL_CP adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_CP = 10'b0001111111$/;" c module:util_adxcvr_xcm +QPLL_CP_G3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] QPLL_CP_G3 = 10'b0000011111,$/;" c module:util_adxcvr +QPLL_CP_G3 adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_CP_G3 = 10'b0000011111,$/;" c module:util_adxcvr_xcm +QPLL_ENABLE adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter integer QPLL_ENABLE = 1,$/;" c module:axi_adxcvr +QPLL_ENABLE adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter integer QPLL_ENABLE = 1,$/;" c module:axi_adxcvr_up +QPLL_FBDIV adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [ 9:0] QPLL_FBDIV = 10'b0000110000,$/;" c module:util_adxcvr +QPLL_FBDIV adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [ 9:0] QPLL_FBDIV = 10'b0000110000,$/;" c module:util_adxcvr_xcm +QPLL_FBDIV_RATIO adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer QPLL_FBDIV_RATIO = 1,$/;" c module:util_adxcvr +QPLL_FBDIV_RATIO adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter integer QPLL_FBDIV_RATIO = 1,$/;" c module:util_adxcvr_xcm +QPLL_LPF adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] QPLL_LPF = 10'b0100110111,$/;" c module:util_adxcvr +QPLL_LPF adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter [15:0] QPLL_LPF = 10'b0100110111,$/;" c module:util_adxcvr_xcm +QPLL_REFCLK_DIV adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer QPLL_REFCLK_DIV = 1,$/;" c module:util_adxcvr +QPLL_REFCLK_DIV adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter integer QPLL_REFCLK_DIV = 1,$/;" c module:util_adxcvr_xcm +Q_OR_I_N adi_library/common/ad_iqcor.v /^ parameter Q_OR_I_N = 0,$/;" c module:ad_iqcor +RAM_ChnEst_MMSE hdl/SC_FDE_TOP.v /^ RAM_ChnEst_MMSE RAM_ChnEst_MMSE ($/;" i module:SC_FDE_TOP typeref:module:RAM_ChnEst_MMSE +RAM_IQmerge hdl/IQmerge.v /^ RAM_IQmerge RAM_IQmerge ($/;" i module:IQmerge typeref:module:RAM_IQmerge +RAM_merge_0 hdl/FrameMerge.v /^ RAM_merge RAM_merge_0 ($/;" i module:FrameMerge typeref:module:RAM_merge +RAM_phase hdl/phase_adjust.v /^ RAM_phase RAM_phase ($/;" i module:phase_adjust typeref:module:RAM_phase +RAM_recvnew_0 hdl/FrameMerge.v /^ RAM_recvnew RAM_recvnew_0 ($/;" i module:FrameMerge typeref:module:RAM_recvnew +RAM_recvnew_1 hdl/FrameMerge.v /^ RAM_recvnew RAM_recvnew_1 ($/;" i module:FrameMerge typeref:module:RAM_recvnew +RAM_recvnew_2 hdl/FrameMerge.v /^ RAM_recvnew RAM_recvnew_2 ($/;" i module:FrameMerge typeref:module:RAM_recvnew +RAMaddra hdl/FrameMerge.v /^ output reg [16:0] RAMaddra = 17'd0, \/\/比较误码率$/;" p module:FrameMerge +RAMaddra hdl/RecvTop.v /^ wire [16:0] RAMaddra; \/\/比较误码率$/;" n module:RecvTop +RAMaddra_new_0 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_new_0 = 17'd0,$/;" p module:FrameMerge +RAMaddra_new_0_d1 hdl/FrameMerge.v /^ reg [16:0] RAMaddra_new_0_d1 = 17'd0;$/;" r module:FrameMerge +RAMaddra_new_1 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_new_1 = 17'd0,$/;" p module:FrameMerge +RAMaddra_new_1_d1 hdl/FrameMerge.v /^ reg [16:0] RAMaddra_new_1_d1 = 17'd0;$/;" r module:FrameMerge +RAMaddra_new_2 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_new_2 = 17'd0,$/;" p module:FrameMerge +RAMaddra_new_2_d1 hdl/FrameMerge.v /^ reg [16:0] RAMaddra_new_2_d1 = 17'd0;$/;" r module:FrameMerge +RAMaddra_new_3 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_new_3 = 17'd0,$/;" p module:FrameMerge +RAMaddra_new_3_d1 hdl/FrameMerge.v /^ reg [16:0] RAMaddra_new_3_d1 = 17'd0;$/;" r module:FrameMerge +RAMaddra_new_temp hdl/FrameMerge.v /^ reg [16:0] RAMaddra_new_temp = 17'd0;$/;" r module:FrameMerge +RAMaddra_write_0 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_write_0 = 17'd0,$/;" p module:FrameMerge +RAMaddra_write_1 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_write_1 = 17'd0,$/;" p module:FrameMerge +RAMaddra_write_2 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_write_2 = 17'd0,$/;" p module:FrameMerge +RAMaddra_write_3 hdl/FrameMerge.v /^ output reg [16:0] RAMaddra_write_3 = 17'd0,$/;" p module:FrameMerge +RAMaddrb hdl/FrameMerge.v /^ reg [16:0] RAMaddrb = 17'd0;$/;" r module:FrameMerge +RAMdout hdl/FrameMerge.v /^ wire RAMdout;$/;" n module:FrameMerge +RAMdout_d1 hdl/FrameMerge.v /^ output reg RAMdout_d1 = 1'd0,$/;" p module:FrameMerge +RAMdout_d1 hdl/RecvTop.v /^ wire RAMdout_d1;$/;" n module:RecvTop +RATE adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [ 2:0] RATE = 3'd0,$/;" c module:axi_adxcvr +RATE adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 2:0] RATE = 3'd0,$/;" c module:axi_adxcvr_up +RATIO adi_library/axi_dmac/axi_dmac_resize_dest.v /^ localparam RATIO = DATA_WIDTH_MEM \/ DATA_WIDTH_DEST;$/;" c module:axi_dmac_resize_dest +RATIO adi_library/axi_dmac/axi_dmac_resize_src.v /^ localparam RATIO = DATA_WIDTH_MEM \/ DATA_WIDTH_SRC;$/;" c module:axi_dmac_resize_src +RATIO adi_library/util_axis_resize/util_axis_resize.v /^localparam RATIO = (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) ?$/;" c module:util_axis_resize +RATIO_WIDTH adi_library/axi_dmac/axi_dmac_resize_src.v /^ localparam RATIO_WIDTH = RATIO > 64 ? 7 :$/;" c module:axi_dmac_resize_src +READ_ACCEPTANCE adi_library/axi_dmac/tb/axi_read_slave.v /^ parameter READ_ACCEPTANCE = 4,$/;" c module:axi_read_slave +REAL_MAX_BYTES_PER_BURST adi_library/axi_dmac/axi_dmac.v /^localparam REAL_MAX_BYTES_PER_BURST =$/;" c module:axi_dmac +REAL_NUM_OF_CHANNELS adi_library/util_pack/util_cpack2/util_cpack2.v /^localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 :$/;" c module:util_cpack2 +REAL_NUM_OF_CHANNELS adi_library/util_pack/util_upack2/util_upack2.v /^localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 :$/;" c module:util_upack2 +REFCLK_FREQUENCY adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ parameter REFCLK_FREQUENCY = 200) ($/;" c module:util_gmii_to_rgmii +REFCLK_FREQUENCY adi_library/xilinx/common/ad_data_in.v /^ parameter REFCLK_FREQUENCY = 200) ($/;" c module:ad_data_in +REFCLK_FREQUENCY adi_library/xilinx/common/ad_data_out.v /^ parameter REFCLK_FREQUENCY = 200) ($/;" c module:ad_data_out +REFCLK_FREQUENCY adi_library/xilinx/common/ad_serdes_in.v /^ parameter REFCLK_FREQUENCY = 200) ($/;" c module:ad_serdes_in +REG_CLK_DIV adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam REG_CLK_DIV = 2'b00;$/;" c module:spi_engine_execution +REG_CONFIG adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam REG_CONFIG = 2'b01;$/;" c module:spi_engine_execution +REG_WORD_LENGTH adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^localparam REG_WORD_LENGTH = 2'b10;$/;" c module:spi_engine_execution +REQ_LEN_INC adi_library/axi_dmac/tb/dma_read_tb.v /^ parameter REQ_LEN_INC = 4;$/;" c module:dmac_dma_read_tb +REQ_LEN_INC adi_library/axi_dmac/tb/dma_write_tb.v /^ parameter REQ_LEN_INC = 4;$/;" c module:dmac_dma_write_tb +REQ_LEN_INIT adi_library/axi_dmac/tb/dma_read_tb.v /^ parameter REQ_LEN_INIT = 4;$/;" c module:dmac_dma_read_tb +REQ_LEN_INIT adi_library/axi_dmac/tb/dma_write_tb.v /^ parameter REQ_LEN_INIT = 4;$/;" c module:dmac_dma_write_tb +RGB_data adi_library/common/ad_csc_CrYCb2RGB.v /^ output [23:0] RGB_data);$/;" p module:ad_csc_CrYCb2RGB +RGB_data adi_library/common/ad_csc_RGB2CrYCb.v /^ input [23:0] RGB_data,$/;" p module:ad_csc_RGB2CrYCb +RGB_sync adi_library/common/ad_csc_CrYCb2RGB.v /^ output [DELAY_DATA_WIDTH-1:0] RGB_sync,$/;" p module:ad_csc_CrYCb2RGB +RGB_sync adi_library/common/ad_csc_RGB2CrYCb.v /^ input [DELAY_DATA_WIDTH-1:0] RGB_sync,$/;" p module:ad_csc_RGB2CrYCb +ROM_ber hdl/FrameMerge.v /^ ROM_ber ROM_ber ($/;" i module:FrameMerge typeref:module:ROM_ber +ROMaddra hdl/FrameMerge.v /^ output reg [16:0] ROMaddra = 17'd0, \/\/比较误码率$/;" p module:FrameMerge +ROMaddra hdl/RecvTop.v /^ wire [16:0] ROMaddra; \/\/比较误码率$/;" n module:RecvTop +ROMaddra_d1 hdl/FrameMerge.v /^ reg [16:0] ROMaddra_d1 = 17'd0;$/;" r module:FrameMerge +ROMaddra_d2 hdl/FrameMerge.v /^ output reg [16:0] ROMaddra_d2 = 17'd0,$/;" p module:FrameMerge +ROMaddra_d2 hdl/RecvTop.v /^ wire [16:0] ROMaddra_d2;$/;" n module:RecvTop +ROMdout hdl/FrameMerge.v /^ wire ROMdout;$/;" n module:FrameMerge +RTX_BUF_CML_CTRL adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [2:0] RTX_BUF_CML_CTRL = 3'b011,$/;" c module:util_adxcvr +RTX_BUF_CML_CTRL adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [2:0] RTX_BUF_CML_CTRL = 3'b011,$/;" c module:util_adxcvr_xch +RXCDR_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010,$/;" c module:util_adxcvr +RXCDR_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010,$/;" c module:util_adxcvr_xch +RXCDR_CFG2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RXCDR_CFG2 = 16'b0000001001101001,$/;" c module:util_adxcvr +RXCDR_CFG2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] RXCDR_CFG2 = 16'b0000001001101001,$/;" c module:util_adxcvr_xch +RXCDR_CFG2_GEN2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [ 9:0] RXCDR_CFG2_GEN2 = 10'b1001100101,$/;" c module:util_adxcvr +RXCDR_CFG2_GEN2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [ 9:0] RXCDR_CFG2_GEN2 = 10'b1001100101,$/;" c module:util_adxcvr_xch +RXCDR_CFG2_GEN4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RXCDR_CFG2_GEN4 = 16'b0000000010110100,$/;" c module:util_adxcvr +RXCDR_CFG2_GEN4 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] RXCDR_CFG2_GEN4 = 16'b0000000010110100,$/;" c module:util_adxcvr_xch +RXCDR_CFG3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RXCDR_CFG3 = 16'b0000000000010010,$/;" c module:util_adxcvr +RXCDR_CFG3 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] RXCDR_CFG3 = 16'b0000000000010010,$/;" c module:util_adxcvr_xch +RXCDR_CFG3_GEN2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010,$/;" c module:util_adxcvr +RXCDR_CFG3_GEN2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010,$/;" c module:util_adxcvr_xch +RXCDR_CFG3_GEN3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010,$/;" c module:util_adxcvr +RXCDR_CFG3_GEN3 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010,$/;" c module:util_adxcvr_xch +RXCDR_CFG3_GEN4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100,$/;" c module:util_adxcvr +RXCDR_CFG3_GEN4 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100,$/;" c module:util_adxcvr_xch +RXPI_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RXPI_CFG0 = 16'b0000000000000010,$/;" c module:util_adxcvr +RXPI_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] RXPI_CFG0 = 16'b0000000000000010,$/;" c module:util_adxcvr_xch +RXPI_CFG1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RXPI_CFG1 = 16'b0000000000010101,$/;" c module:util_adxcvr +RXPI_CFG1 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] RXPI_CFG1 = 16'b0000000000010101,$/;" c module:util_adxcvr_xch +RX_CDR_CFG adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020,$/;" c module:util_adxcvr +RX_CDR_CFG adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020,$/;" c module:util_adxcvr_xch +RX_CLK25_DIV adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer RX_CLK25_DIV = 20,$/;" c module:util_adxcvr +RX_CLK25_DIV adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer RX_CLK25_DIV = 20,$/;" c module:util_adxcvr_xch +RX_DFE_LPM_CFG adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] RX_DFE_LPM_CFG = 16'h0104,$/;" c module:util_adxcvr +RX_DFE_LPM_CFG adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] RX_DFE_LPM_CFG = 16'h0104,$/;" c module:util_adxcvr_xch +RX_LANE_INVERT adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer RX_LANE_INVERT = 0) ($/;" c module:util_adxcvr +RX_NUM_OF_LANES adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer RX_NUM_OF_LANES = 8,$/;" c module:util_adxcvr +RX_OUT_DIV adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer RX_OUT_DIV = 1,$/;" c module:util_adxcvr +RX_OUT_DIV adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer RX_OUT_DIV = 1,$/;" c module:util_adxcvr_xch +RX_PMA_CFG adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [31:0] RX_PMA_CFG = 32'h001e7080,$/;" c module:util_adxcvr +RX_PMA_CFG adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [31:0] RX_PMA_CFG = 32'h001e7080,$/;" c module:util_adxcvr_xch +RX_POLARITY adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer RX_POLARITY = 0) ($/;" c module:util_adxcvr_xch +RX_WIDEMODE_CDR adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [ 1:0] RX_WIDEMODE_CDR = 2'b00,$/;" c module:util_adxcvr +RX_WIDEMODE_CDR adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [ 1:0] RX_WIDEMODE_CDR = 2'b00,$/;" c module:util_adxcvr_xch +RX_XMODE_SEL adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [ 0:0] RX_XMODE_SEL = 1'b1,$/;" c module:util_adxcvr +RX_XMODE_SEL adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [ 0:0] RX_XMODE_SEL = 1'b1,$/;" c module:util_adxcvr_xch +Rdy hdl/ApproxAbs_18bit.v /^ output reg Rdy $/;" p module:ApproxAbs_18bit +Rdy hdl/ApproxAbs_v2.v /^ output reg Rdy = 1'b0$/;" p module:ApproxAbs_v2 +Rdy hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output Rdy, \/\/译码输出信号有效标志,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Rdy_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Rdy_A; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Rdy_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire Rdy_B; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +Rdy_abs hdl/DAGC_v2.v /^ wire [ 0:0] Rdy_abs;$/;" n module:DAGC_v2 +Rdy_b1 hdl/ApproxAbs_18bit.v /^ reg Rdy_b1 = 1'b0;$/;" r module:ApproxAbs_18bit +Rdy_b1 hdl/ApproxAbs_v2.v /^ reg Rdy_b1 = 1'b0;$/;" r module:ApproxAbs_v2 +Rdy_b2 hdl/ApproxAbs_18bit.v /^ reg Rdy_b2 = 1'b0;$/;" r module:ApproxAbs_18bit +Rdy_b2 hdl/ApproxAbs_v2.v /^ reg Rdy_b2 = 1'b0;$/;" r module:ApproxAbs_v2 +Rdy_b3 hdl/ApproxAbs_18bit.v /^ reg Rdy_b3 = 1'b0;$/;" r module:ApproxAbs_18bit +Rdy_b3 hdl/ApproxAbs_v2.v /^ reg Rdy_b3 = 1'b0;$/;" r module:ApproxAbs_v2 +Rdy_b4 hdl/ApproxAbs_18bit.v /^ reg Rdy_b4 = 1'b0;$/;" r module:ApproxAbs_18bit +Rdy_b4 hdl/ApproxAbs_v2.v /^ reg Rdy_b4 = 1'b0;$/;" r module:ApproxAbs_v2 +Rdy_b5 hdl/ApproxAbs_18bit.v /^ reg Rdy_b5 = 1'b0;$/;" r module:ApproxAbs_18bit +Rdy_b5 hdl/ApproxAbs_v2.v /^ reg Rdy_b5 = 1'b0;$/;" r module:ApproxAbs_v2 +Receiver hdl/Receiver.v /^module Receiver ($/;" m +RecvTop hdl/RecvTop.v /^module RecvTop ($/;" m +Rst hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input Rst, \/\/同步复位信号,高有效$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +SAMPLES_PER_CHANNEL adi_library/util_pack/tb/cpack_tb.v /^ parameter SAMPLES_PER_CHANNEL = 1;$/;" c module:cpack_tb +SAMPLES_PER_CHANNEL adi_library/util_pack/tb/underflow_tb.v /^ parameter SAMPLES_PER_CHANNEL = 4;$/;" c module:upack2_underflow_tb +SAMPLES_PER_CHANNEL adi_library/util_pack/tb/upack_tb.v /^ parameter SAMPLES_PER_CHANNEL = 1;$/;" c module:upack_tb +SAMPLES_PER_CHANNEL adi_library/util_pack/util_cpack2/util_cpack2.v /^ parameter SAMPLES_PER_CHANNEL = 1,$/;" c module:util_cpack2 +SAMPLES_PER_CHANNEL adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ parameter SAMPLES_PER_CHANNEL = 1,$/;" c module:util_cpack2_impl +SAMPLES_PER_CHANNEL adi_library/util_pack/util_pack_common/pack_shell.v /^ parameter SAMPLES_PER_CHANNEL = 1,$/;" c module:pack_shell +SAMPLES_PER_CHANNEL adi_library/util_pack/util_upack2/util_upack2.v /^ parameter SAMPLES_PER_CHANNEL = 1,$/;" c module:util_upack2 +SAMPLES_PER_CHANNEL adi_library/util_pack/util_upack2/util_upack2_impl.v /^ parameter SAMPLES_PER_CHANNEL = 1,$/;" c module:util_upack2_impl +SAMPLE_ADDRESS_WIDTH adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam SAMPLE_ADDRESS_WIDTH =$/;" c module:pack_shell +SAMPLE_DATA_WIDTH adi_library/util_pack/util_cpack2/util_cpack2.v /^ parameter SAMPLE_DATA_WIDTH = 16$/;" c module:util_cpack2 +SAMPLE_DATA_WIDTH adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ parameter SAMPLE_DATA_WIDTH = 16$/;" c module:util_cpack2_impl +SAMPLE_DATA_WIDTH adi_library/util_pack/util_pack_common/pack_shell.v /^ parameter SAMPLE_DATA_WIDTH = 16,$/;" c module:pack_shell +SAMPLE_DATA_WIDTH adi_library/util_pack/util_upack2/util_upack2.v /^ parameter SAMPLE_DATA_WIDTH = 16$/;" c module:util_upack2 +SAMPLE_DATA_WIDTH adi_library/util_pack/util_upack2/util_upack2_impl.v /^ parameter SAMPLE_DATA_WIDTH = 16$/;" c module:util_upack2_impl +SCALE_ONLY adi_library/common/ad_iqcor.v /^ parameter SCALE_ONLY = 0,$/;" c module:ad_iqcor +SCFDE_recv_FrameSync hdl/SCFDE_recv_FrameSync.v /^module SCFDE_recv_FrameSync ($/;" m +SCFDE_recv_FrameSync_inst hdl/RecvTop.v /^ SCFDE_recv_FrameSync SCFDE_recv_FrameSync_inst ($/;" i module:RecvTop typeref:module:SCFDE_recv_FrameSync +SC_FDE_TOP hdl/SC_FDE_TOP.v /^module SC_FDE_TOP($/;" m +SC_FDE_TOP_djy hdl/RecvTop.v /^ SC_FDE_TOP SC_FDE_TOP_djy ($/;" i module:RecvTop typeref:module:SC_FDE_TOP +SC_FDE_commul hdl/data_equalizer.v /^ SC_FDE_commul SC_FDE_commul ($/;" i module:data_equalizer typeref:module:SC_FDE_commul +SC_FDE_douti hdl/RecvTop.v /^ output [ 9:0] SC_FDE_douti, \/\/SC_FDE输出$/;" p module:RecvTop +SC_FDE_douti hdl/SC_FDE_TOP.v /^ output [9:0] SC_FDE_douti,$/;" p module:SC_FDE_TOP +SC_FDE_douti hdl/data_equalizer.v /^ output reg [9:0] SC_FDE_douti = 10'd0,$/;" p module:data_equalizer +SC_FDE_doutq hdl/RecvTop.v /^ output [ 9:0] SC_FDE_doutq,$/;" p module:RecvTop +SC_FDE_doutq hdl/SC_FDE_TOP.v /^ output [9:0] SC_FDE_doutq,$/;" p module:SC_FDE_TOP +SC_FDE_doutq hdl/data_equalizer.v /^ output reg [9:0] SC_FDE_doutq = 10'd0,$/;" p module:data_equalizer +SDI_DELAY adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ parameter [1:0] SDI_DELAY = 2'b00) ($/;" c module:spi_engine_execution +SDI_FIFO_ADDRESS_WIDTH adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter SDI_FIFO_ADDRESS_WIDTH = 5,$/;" c module:axi_spi_engine +SDO_DEFAULT adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ parameter [0:0] SDO_DEFAULT = 1'b0,$/;" c module:spi_engine_execution +SDO_FIFO_ADDRESS_WIDTH adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter SDO_FIFO_ADDRESS_WIDTH = 5,$/;" c module:axi_spi_engine +SDO_MEM_ADDRESS_WIDTH adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ parameter SDO_MEM_ADDRESS_WIDTH = 4,$/;" c module:spi_engine_offload +SEL_0_DIV adi_library/xilinx/util_clkdiv/util_clkdiv.v /^parameter SEL_0_DIV = "4";$/;" c module:util_clkdiv +SEL_1_DIV adi_library/xilinx/util_clkdiv/util_clkdiv.v /^parameter SEL_1_DIV = "2";$/;" c module:util_clkdiv +SEQ adi_library/util_cic/cic_comb.v /^ parameter SEQ = 1,$/;" c module:cic_comb +SERDES_FACTOR adi_library/xilinx/common/ad_serdes_clk.v /^ parameter SERDES_FACTOR = 8,$/;" c module:ad_serdes_clk +SERDES_FACTOR adi_library/xilinx/common/ad_serdes_in.v /^ parameter SERDES_FACTOR = 8,$/;" c module:ad_serdes_in +SERDES_FACTOR adi_library/xilinx/common/ad_serdes_out.v /^ parameter SERDES_FACTOR = 8,$/;" c module:ad_serdes_out +SEVEN_SERIES adi_library/xilinx/common/ad_data_in.v /^ localparam SEVEN_SERIES = 1;$/;" c module:ad_data_in +SEVEN_SERIES adi_library/xilinx/common/ad_data_out.v /^ localparam SEVEN_SERIES = 1;$/;" c module:ad_data_out +SEVEN_SERIES adi_library/xilinx/common/ad_mmcm_drp.v /^ localparam SEVEN_SERIES = 1;$/;" c module:ad_mmcm_drp +SEVEN_SERIES adi_library/xilinx/common/ad_serdes_in.v /^ localparam SEVEN_SERIES = 1;$/;" c module:ad_serdes_in +SEVEN_SERIES adi_library/xilinx/common/ad_serdes_out.v /^ localparam SEVEN_SERIES = 1;$/;" c module:ad_serdes_out +SHIFT adi_library/common/ad_dds_cordic_pipe.v /^ parameter SHIFT = 0) ($/;" c module:ad_dds_cordic_pipe +SIM_DEVICE adi_library/xilinx/common/ad_serdes_in.v /^ localparam SIM_DEVICE = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" :$/;" c module:ad_serdes_in +SIM_DEVICE adi_library/xilinx/common/ad_serdes_out.v /^ localparam SIM_DEVICE = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" :$/;" c module:ad_serdes_out +SIM_DEVICE adi_library/xilinx/util_clkdiv/util_clkdiv.v /^parameter SIM_DEVICE = "7SERIES";$/;" c module:util_clkdiv +SIM_DEVICE_IDELAYCTRL adi_library/xilinx/common/ad_serdes_in.v /^ localparam SIM_DEVICE_IDELAYCTRL = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" :$/;" c module:ad_serdes_in +SINGLE_ENDED adi_library/xilinx/common/ad_data_clk.v /^ parameter SINGLE_ENDED = 0) ($/;" c module:ad_data_clk +SINGLE_ENDED adi_library/xilinx/common/ad_data_in.v /^ parameter SINGLE_ENDED = 0,$/;" c module:ad_data_in +SINGLE_ENDED adi_library/xilinx/common/ad_data_out.v /^ parameter SINGLE_ENDED = 0,$/;" c module:ad_data_out +SLAVE_DATA_WIDTH adi_library/util_axis_resize/util_axis_resize.v /^ parameter SLAVE_DATA_WIDTH = 64,$/;" c module:util_axis_resize +SLOT_LEN hdl/tdma.v /^ parameter SLOT_LEN = 1250000,$/;" c module:tdma +SPEED_GRADE adi_library/common/up_adc_common.v /^ parameter [ 7:0] SPEED_GRADE = 0,$/;" c module:up_adc_common +SPEED_GRADE adi_library/common/up_clkgen.v /^ parameter [ 7:0] SPEED_GRADE = 0,$/;" c module:up_clkgen +SPEED_GRADE adi_library/common/up_dac_common.v /^ parameter [ 7:0] SPEED_GRADE = 0,$/;" c module:up_dac_common +SPEED_GRADE adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter SPEED_GRADE = 0,$/;" c module:axi_adxcvr +SPEED_GRADE adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 7:0] SPEED_GRADE = 0,$/;" c module:axi_adxcvr_up +STAGE_WIDTH adi_library/util_cic/cic_comb.v /^ parameter STAGE_WIDTH = 1,$/;" c module:cic_comb +STAGE_WIDTH adi_library/util_cic/cic_int.v /^ parameter STAGE_WIDTH = 1,$/;" c module:cic_int +START_CODE_DISABLE adi_library/common/up_adc_common.v /^ parameter START_CODE_DISABLE = 0) ($/;" c module:up_adc_common +STATE_ACC adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam STATE_ACC = 3'h1;$/;" c module:axi_dmac_response_manager +STATE_CONSUME adi_library/axi_dmac/request_generator.v /^localparam STATE_CONSUME = 3'h3;$/;" c module:dmac_request_generator +STATE_DISABLED adi_library/axi_dmac/axi_dmac_reset_manager.v /^localparam STATE_DISABLED = 3'h2;$/;" c module:axi_dmac_reset_manager +STATE_DO_RESET adi_library/axi_dmac/axi_dmac_reset_manager.v /^localparam STATE_DO_RESET = 3'h0;$/;" c module:axi_dmac_reset_manager +STATE_ENABLED adi_library/axi_dmac/axi_dmac_reset_manager.v /^localparam STATE_ENABLED = 3'h4;$/;" c module:axi_dmac_reset_manager +STATE_GEN_ID adi_library/axi_dmac/request_generator.v /^localparam STATE_GEN_ID = 3'h1;$/;" c module:dmac_request_generator +STATE_IDLE adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam STATE_IDLE = 3'h0;$/;" c module:axi_dmac_response_manager +STATE_IDLE adi_library/axi_dmac/request_generator.v /^localparam STATE_IDLE = 3'h0;$/;" c module:dmac_request_generator +STATE_RESET adi_library/axi_dmac/axi_dmac_reset_manager.v /^localparam STATE_RESET = 3'h1;$/;" c module:axi_dmac_reset_manager +STATE_REWIND_ID adi_library/axi_dmac/request_generator.v /^localparam STATE_REWIND_ID = 3'h2;$/;" c module:dmac_request_generator +STATE_SHUTDOWN adi_library/axi_dmac/axi_dmac_reset_manager.v /^localparam STATE_SHUTDOWN = 3'h5;$/;" c module:axi_dmac_reset_manager +STATE_STARTUP adi_library/axi_dmac/axi_dmac_reset_manager.v /^localparam STATE_STARTUP = 3'h3;$/;" c module:axi_dmac_reset_manager +STATE_WAIT_LAST adi_library/axi_dmac/request_generator.v /^localparam STATE_WAIT_LAST = 3'h4;$/;" c module:dmac_request_generator +STATE_WRITE_RESPR adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam STATE_WRITE_RESPR = 3'h2;$/;" c module:axi_dmac_response_manager +STATE_WRITE_ZRCMPL adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam STATE_WRITE_ZRCMPL = 3'h4;$/;" c module:axi_dmac_response_manager +STATE_ZERO_COMPL adi_library/axi_dmac/axi_dmac_response_manager.v /^localparam STATE_ZERO_COMPL = 3'h3;$/;" c module:axi_dmac_response_manager +STRIDE_MASK adi_library/axi_dmac/tb/regmap_tb.v /^ localparam STRIDE_MASK = {{DMA_LENGTH_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};$/;" c module:dmac_regmap_tb +SUBSTRACTER adi_library/common/ad_addsub.v /^ localparam SUBSTRACTER = 0;$/;" c module:ad_addsub +SUM_COEF_DW adi_library/common/ad_csc.v /^ parameter SUM_COEF_DW = 24,$/;" c module:ad_csc +SUM_WIDTH hdl/PAPR.v /^ localparam SUM_WIDTH = 32;$/;" c module:PAPR +SYNC_FIFO_ADDRESS_WIDTH adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter SYNC_FIFO_ADDRESS_WIDTH = 4,$/;" c module:axi_spi_engine +SYNC_TRANSFER_START adi_library/axi_dmac/axi_dmac.v /^ parameter SYNC_TRANSFER_START = 0,$/;" c module:axi_dmac +SYNC_TRANSFER_START adi_library/axi_dmac/axi_dmac_regmap.v /^ parameter SYNC_TRANSFER_START = 0$/;" c module:axi_dmac_regmap +SYNC_TRANSFER_START adi_library/axi_dmac/axi_dmac_regmap_request.v /^ parameter SYNC_TRANSFER_START = 0$/;" c module:axi_dmac_regmap_request +SYSREF_HALFPERIOD adi_library/common/ad_sysref_gen.v /^ localparam SYSREF_HALFPERIOD = SYSREF_PERIOD\/2 - 1;$/;" c module:ad_sysref_gen +SYSREF_PERIOD adi_library/common/ad_sysref_gen.v /^ parameter SYSREF_PERIOD = 128;$/;" c module:ad_sysref_gen +SYS_CLK_SEL adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [ 1:0] SYS_CLK_SEL = 2'd3,$/;" c module:axi_adxcvr +SYS_CLK_SEL adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 1:0] SYS_CLK_SEL = 2'd3,$/;" c module:axi_adxcvr_up +S_AXI adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ localparam S_AXI = 0;$/;" c module:axi_spi_engine +S_AXIS_DATA_WIDTH adi_library/axi_dmac/dest_axi_stream.v /^ parameter S_AXIS_DATA_WIDTH = 64,$/;" c module:dmac_dest_axi_stream +S_AXIS_DATA_WIDTH adi_library/axi_dmac/src_axi_stream.v /^ parameter S_AXIS_DATA_WIDTH = 64,$/;" c module:dmac_src_axi_stream +S_AXIS_REGISTERED adi_library/util_axis_fifo/util_axis_fifo.v /^ parameter S_AXIS_REGISTERED = 1$/;" c module:util_axis_fifo +S_DEC hdl/ad9361_mgc_pin_ctrl.v /^ localparam S_DEC = 2;$/;" c module:ad9361_mgc_pin_ctrl +S_DONE hdl/ad9361_mgc_pin_ctrl.v /^ localparam S_DONE = 3;$/;" c module:ad9361_mgc_pin_ctrl +S_IDLE hdl/Transmitter.v /^ localparam [3:0] S_IDLE = 4'd0;$/;" c module:Transmitter +S_IDLE hdl/ad9361_mgc_pin_ctrl.v /^ localparam S_IDLE = 0;$/;" c module:ad9361_mgc_pin_ctrl +S_IDLE hdl/add_prefix.v /^ localparam [2:0] S_IDLE = 0;$/;" c module:add_prefix +S_IDLE hdl/enc_control.v /^ localparam [3:0] S_IDLE = 4'd0;$/;" c module:enc_control +S_IN hdl/add_prefix.v /^ localparam [2:0] S_IN = 1;$/;" c module:add_prefix +S_INC hdl/ad9361_mgc_pin_ctrl.v /^ localparam S_INC = 1;$/;" c module:ad9361_mgc_pin_ctrl +S_MEASURE_ADJ hdl/power_measure.v /^ localparam S_MEASURE_ADJ = 3;$/;" c module:power_measure +S_MEASURE_DONE hdl/power_measure.v /^ localparam S_MEASURE_DONE = 2;$/;" c module:power_measure +S_MEASURE_IDLE hdl/power_measure.v /^ localparam S_MEASURE_IDLE = 0;$/;" c module:power_measure +S_MEASURE_ING hdl/power_measure.v /^ localparam S_MEASURE_ING = 1;$/;" c module:power_measure +S_MEASURE_STARTUP hdl/power_measure.v /^ localparam S_MEASURE_STARTUP = 4;$/;" c module:power_measure +S_OUT hdl/add_prefix.v /^ localparam [2:0] S_OUT = 2;$/;" c module:add_prefix +S_SEND_AGC hdl/Transmitter.v /^ localparam [3:0] S_SEND_AGC = 4'd1;$/;" c module:Transmitter +S_SEND_CHU_NEG hdl/Transmitter.v /^ localparam [3:0] S_SEND_CHU_NEG = 4'd9;$/;" c module:Transmitter +S_SEND_CHU_POS hdl/Transmitter.v /^ localparam [3:0] S_SEND_CHU_POS = 4'd8;$/;" c module:Transmitter +S_SEND_FRAME_HEADER hdl/Transmitter.v /^ localparam [3:0] S_SEND_FRAME_HEADER = 4'd2;$/;" c module:Transmitter +S_SEND_PHASE1 hdl/Transmitter.v /^ localparam [3:0] S_SEND_PHASE1 = 4'd3;$/;" c module:Transmitter +S_START hdl/enc_control.v /^ localparam [3:0] S_START = 4'd1;$/;" c module:enc_control +S_TEST hdl/Transmitter.v /^ localparam [3:0] S_TEST = 4'd7;$/;" c module:Transmitter +S_WAIT_ADD_PREFIX_DONE hdl/enc_control.v /^ localparam [3:0] S_WAIT_ADD_PREFIX_DONE = 4'd3;$/;" c module:enc_control +S_WAIT_GAP hdl/Transmitter.v /^ localparam [3:0] S_WAIT_GAP = 4'd6; \/\/ wait for freq switch$/;" c module:Transmitter +S_WAIT_HOP hdl/Transmitter.v /^ localparam [3:0] S_WAIT_HOP = 4'd5;$/;" c module:Transmitter +S_WAIT_LDPC_OUT hdl/enc_control.v /^ localparam [3:0] S_WAIT_LDPC_OUT = 4'd2;$/;" c module:enc_control +Scramble hdl/FrameMerge.v /^ Scramble Scramble ($/;" i module:FrameMerge typeref:module:Scramble +Sync_i hdl/SCFDE_recv_FrameSync.v /^ output reg [9:0] Sync_i = 10'd0,$/;" p module:SCFDE_recv_FrameSync +Sync_q hdl/SCFDE_recv_FrameSync.v /^ output reg [9:0] Sync_q = 10'd0,$/;" p module:SCFDE_recv_FrameSync +Sync_rdy hdl/RecvTop.v /^ wire Sync_rdy;$/;" n module:RecvTop +Sync_rdy hdl/SCFDE_recv_FrameSync.v /^ output reg Sync_rdy = 1'b0, \/\/判断出峰的标志位，出峰后拉高1c/;" p module:SCFDE_recv_FrameSync +TB_sys sim/TB_sys.v /^module TB_sys ();$/;" m +TDD_SYNC_PERIOD adi_library/util_tdd_sync/util_tdd_sync.v /^ parameter TDD_SYNC_PERIOD = 100000000) ($/;" c module:util_tdd_sync +TIC_FRAME_SYNC hdl/tdma.v /^ parameter TIC_FRAME_SYNC = 42272$/;" c module:tdma +TIC_TO_PS_LEN hdl/tdma.v /^ parameter TIC_TO_PS_LEN = 1200000,$/;" c module:tdma +TIMEOUT adi_library/axi_dmac/tb/regmap_tb.v /^ `define TIMEOUT 1000000$/;" d module:dmac_regmap_tb +TIMEOUT adi_library/axi_dmac/tb/reset_manager_tb.v /^ `define TIMEOUT 1000000$/;" d module:dmac_reset_manager_tb +TIMEOUT adi_library/util_pack/tb/cpack_tb.v /^ `define TIMEOUT 1500000$/;" d module:cpack_tb +TIMEOUT adi_library/util_pack/tb/upack_tb.v /^ `define TIMEOUT 1500000$/;" d module:upack_tb +TM hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ TM ($/;" i module:CCSDS_LDPC_DEC_K1024_R12_TOPP typeref:module:LDPC_TopManage_2 +TOTAL_DATA_WIDTH adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ localparam TOTAL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;$/;" c module:util_cpack2_impl +TOTAL_DATA_WIDTH adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam TOTAL_DATA_WIDTH = PORT_DATA_WIDTH * NUM_PORTS;$/;" c module:pack_interconnect +TOTAL_DATA_WIDTH adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam TOTAL_DATA_WIDTH = CHANNEL_DATA_WIDTH * NUM_OF_CHANNELS;$/;" c module:pack_shell +TOTAL_WIDTH adi_library/common/up_clock_mon.v /^ parameter TOTAL_WIDTH = 32$/;" c module:up_clock_mon +TRANSFER_ADDR adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ localparam TRANSFER_ADDR = 32'h80000000;$/;" c module:dmac_dma_read_shutdown_tb +TRANSFER_ADDR adi_library/axi_dmac/tb/dma_read_tb.v /^ localparam TRANSFER_ADDR = 32'h80000000;$/;" c module:dmac_dma_read_tb +TRANSFER_ADDR adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ localparam TRANSFER_ADDR = 32'h80000000;$/;" c module:dmac_dma_write_shutdown_tb +TRANSFER_ADDR adi_library/axi_dmac/tb/dma_write_tb.v /^ localparam TRANSFER_ADDR = 32'h80000000;$/;" c module:dmac_dma_write_tb +TRANSFER_LEN adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ localparam TRANSFER_LEN = 24'h2ff;$/;" c module:dmac_dma_read_shutdown_tb +TRANSFER_LEN adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ localparam TRANSFER_LEN = 24'h2ff;$/;" c module:dmac_dma_write_shutdown_tb +TSync_Abs_new16 hdl/TSync_Abs_new16.v /^module TSync_Abs_new16($/;" m +TSync_Abs_new16 hdl/TimeSync_top.v /^ TSync_Abs_new16 TSync_Abs_new16 ($/;" i module:TimeSync_top typeref:module:TSync_Abs_new16 +TSync_Abs_new4 hdl/TSync_Abs_new4.v /^module TSync_Abs_new4($/;" m +TSync_Abs_new4 hdl/TimeSync_top.v /^ TSync_Abs_new4 TSync_Abs_new4 ($/;" i module:TimeSync_top typeref:module:TSync_Abs_new4 +TSyncout_i hdl/TSync_Abs_new16.v /^ output reg [9:0] TSyncout_i = 10'd0,$/;" p module:TSync_Abs_new16 +TSyncout_i hdl/TSync_Abs_new4.v /^ output reg [9:0] TSyncout_i = 10'd0,$/;" p module:TSync_Abs_new4 +TSyncout_nd hdl/TSync_Abs_new16.v /^ output reg TSyncout_nd = 1'd0,$/;" p module:TSync_Abs_new16 +TSyncout_nd hdl/TSync_Abs_new4.v /^ output reg TSyncout_nd = 1'd0,$/;" p module:TSync_Abs_new4 +TSyncout_q hdl/TSync_Abs_new16.v /^ output reg [9:0] TSyncout_q = 10'd0,$/;" p module:TSync_Abs_new16 +TSyncout_q hdl/TSync_Abs_new4.v /^ output reg [9:0] TSyncout_q = 10'd0,$/;" p module:TSync_Abs_new4 +TXDRV_FREQBAND adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer TXDRV_FREQBAND = 0,$/;" c module:util_adxcvr +TXDRV_FREQBAND adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer TXDRV_FREQBAND = 0,$/;" c module:util_adxcvr_xch +TXFE_CFG1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] TXFE_CFG1 = 16'b0110110000000000,$/;" c module:util_adxcvr +TXFE_CFG1 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] TXFE_CFG1 = 16'b0110110000000000,$/;" c module:util_adxcvr_xch +TXFE_CFG2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] TXFE_CFG2 = 16'b0110110000000000,$/;" c module:util_adxcvr +TXFE_CFG2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] TXFE_CFG2 = 16'b0110110000000000,$/;" c module:util_adxcvr_xch +TXFE_CFG3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] TXFE_CFG3 = 16'b0110110000000000,$/;" c module:util_adxcvr +TXFE_CFG3 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] TXFE_CFG3 = 16'b0110110000000000,$/;" c module:util_adxcvr_xch +TXPI_CFG adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] TXPI_CFG = 16'b0000000001010100,$/;" c module:util_adxcvr +TXPI_CFG adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] TXPI_CFG = 16'b0000000001010100,$/;" c module:util_adxcvr_xch +TXPI_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] TXPI_CFG0 = 16'b0000001100000000,$/;" c module:util_adxcvr +TXPI_CFG0 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] TXPI_CFG0 = 16'b0000001100000000,$/;" c module:util_adxcvr_xch +TXPI_CFG1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] TXPI_CFG1 = 16'b0001000000000000,$/;" c module:util_adxcvr +TXPI_CFG1 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] TXPI_CFG1 = 16'b0001000000000000,$/;" c module:util_adxcvr_xch +TX_CLK25_DIV adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer TX_CLK25_DIV = 20,$/;" c module:util_adxcvr +TX_CLK25_DIV adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer TX_CLK25_DIV = 20,$/;" c module:util_adxcvr_xch +TX_DATA_PATH_DELAY adi_library/common/ad_tdd_control.v /^ parameter integer TX_DATA_PATH_DELAY = 0,$/;" c module:ad_tdd_control +TX_DIFFCTRL adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [ 4:0] TX_DIFFCTRL = 5'd8,$/;" c module:axi_adxcvr +TX_DIFFCTRL adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 3:0] TX_DIFFCTRL = 4'd8,$/;" c module:axi_adxcvr_up +TX_LANE_INVERT adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer TX_LANE_INVERT = 0,$/;" c module:util_adxcvr +TX_NUM_OF_LANES adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer TX_NUM_OF_LANES = 8,$/;" c module:util_adxcvr +TX_OR_RX_N adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter integer TX_OR_RX_N = 0,$/;" c module:axi_adxcvr +TX_OR_RX_N adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ parameter integer TX_OR_RX_N = 0;$/;" c module:axi_adxcvr_es +TX_OR_RX_N adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter integer TX_OR_RX_N = 0,$/;" c module:axi_adxcvr_up +TX_OUT_DIV adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer TX_OUT_DIV = 1,$/;" c module:util_adxcvr +TX_OUT_DIV adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer TX_OUT_DIV = 1,$/;" c module:util_adxcvr_xch +TX_PI_BIASSET adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter [15:0] TX_PI_BIASSET = 1,$/;" c module:util_adxcvr +TX_PI_BIASSET adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter [15:0] TX_PI_BIASSET = 1,$/;" c module:util_adxcvr_xch +TX_POLARITY adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer TX_POLARITY = 0,$/;" c module:util_adxcvr_xch +TX_POSTCURSOR adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [ 4:0] TX_POSTCURSOR = 5'd0,$/;" c module:axi_adxcvr +TX_POSTCURSOR adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 4:0] TX_POSTCURSOR = 5'd0,$/;" c module:axi_adxcvr_up +TX_PRECURSOR adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [ 4:0] TX_PRECURSOR = 5'd0,$/;" c module:axi_adxcvr +TX_PRECURSOR adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 4:0] TX_PRECURSOR = 5'd0,$/;" c module:axi_adxcvr_up +T_DIN_DATA_WIDTH adi_library/util_rfifo/util_rfifo.v /^ localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8;$/;" c module:util_rfifo +T_DIN_DATA_WIDTH adi_library/util_wfifo/util_wfifo.v /^ localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8;$/;" c module:util_wfifo +T_DOUT_DATA_WIDTH adi_library/util_rfifo/util_rfifo.v /^ localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8;$/;" c module:util_rfifo +T_DOUT_DATA_WIDTH adi_library/util_wfifo/util_wfifo.v /^ localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8;$/;" c module:util_wfifo +Threshold hdl/SCFDE_recv_FrameSync.v /^ reg [19:0] Threshold;$/;" r module:SCFDE_recv_FrameSync +TimeSync_top hdl/RecvTop.v /^ TimeSync_top TimeSync_top ($/;" i module:RecvTop typeref:module:TimeSync_top +TimeSync_top hdl/TimeSync_top.v /^module TimeSync_top($/;" m +Transmitter hdl/Transmitter.v /^module Transmitter #($/;" m +Trunc_demod_i hdl/DDS_compensate.v /^trunc_25to12_2dly Trunc_demod_i ($/;" i module:DDS_compensate typeref:module:trunc_25to12_2dly +Trunc_demod_q hdl/DDS_compensate.v /^trunc_25to12_2dly Trunc_demod_q ($/;" i module:DDS_compensate typeref:module:trunc_25to12_2dly +UDATA_WIDTH adi_library/common/util_axis_upscale.v /^ parameter UDATA_WIDTH = 32)($/;" c module:util_axis_upscale +ULTRASCALE adi_library/xilinx/common/ad_data_in.v /^ localparam ULTRASCALE = 2;$/;" c module:ad_data_in +ULTRASCALE adi_library/xilinx/common/ad_data_out.v /^ localparam ULTRASCALE = 2;$/;" c module:ad_data_out +ULTRASCALE adi_library/xilinx/common/ad_mmcm_drp.v /^ localparam ULTRASCALE = 2;$/;" c module:ad_mmcm_drp +ULTRASCALE adi_library/xilinx/common/ad_serdes_in.v /^ localparam ULTRASCALE = 2;$/;" c module:ad_serdes_in +ULTRASCALE adi_library/xilinx/common/ad_serdes_out.v /^ localparam ULTRASCALE = 2;$/;" c module:ad_serdes_out +ULTRASCALE_PLUS adi_library/xilinx/common/ad_data_in.v /^ localparam ULTRASCALE_PLUS = 3;$/;" c module:ad_data_in +ULTRASCALE_PLUS adi_library/xilinx/common/ad_data_out.v /^ localparam ULTRASCALE_PLUS = 3;$/;" c module:ad_data_out +ULTRASCALE_PLUS adi_library/xilinx/common/ad_mmcm_drp.v /^ localparam ULTRASCALE_PLUS = 3;$/;" c module:ad_mmcm_drp +ULTRASCALE_PLUS adi_library/xilinx/common/ad_serdes_in.v /^ localparam ULTRASCALE_PLUS = 3;$/;" c module:ad_serdes_in +ULTRASCALE_PLUS adi_library/xilinx/common/ad_serdes_out.v /^ localparam ULTRASCALE_PLUS = 3;$/;" c module:ad_serdes_out +UP_FIFO adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ localparam UP_FIFO = 1;$/;" c module:axi_spi_engine +USERPORTS_DISABLE adi_library/common/up_adc_channel.v /^ parameter USERPORTS_DISABLE = 0,$/;" c module:up_adc_channel +USERPORTS_DISABLE adi_library/common/up_adc_common.v /^ parameter USERPORTS_DISABLE = 0,$/;" c module:up_adc_common +USERPORTS_DISABLE adi_library/common/up_dac_channel.v /^ parameter USERPORTS_DISABLE = 0,$/;" c module:up_dac_channel +USERPORTS_DISABLE adi_library/common/up_dac_common.v /^ parameter USERPORTS_DISABLE = 0,$/;" c module:up_dac_common +VAL_DBG_DEST_ADDR adi_library/axi_dmac/tb/regmap_tb.v /^ localparam VAL_DBG_DEST_ADDR = 32'hfedcba98;$/;" c module:dmac_regmap_tb +VAL_DBG_IDS0 adi_library/axi_dmac/tb/regmap_tb.v /^ localparam VAL_DBG_IDS0 = 32'h01234567;$/;" c module:dmac_regmap_tb +VAL_DBG_IDS1 adi_library/axi_dmac/tb/regmap_tb.v /^ localparam VAL_DBG_IDS1 = 32'h89abcdef;$/;" c module:dmac_regmap_tb +VAL_DBG_SRC_ADDR adi_library/axi_dmac/tb/regmap_tb.v /^ localparam VAL_DBG_SRC_ADDR = 32'h76543210;$/;" c module:dmac_regmap_tb +VAL_DBG_STATUS adi_library/axi_dmac/tb/regmap_tb.v /^ localparam VAL_DBG_STATUS = 8'ha5;$/;" c module:dmac_regmap_tb +VCD_FILE adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ parameter VCD_FILE = {`__FILE__,"cd"};$/;" c module:dmac_dma_read_shutdown_tb +VCD_FILE adi_library/axi_dmac/tb/dma_read_tb.v /^ parameter VCD_FILE = {`__FILE__,"cd"};$/;" c module:dmac_dma_read_tb +VCD_FILE adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ parameter VCD_FILE = {`__FILE__,"cd"};$/;" c module:dmac_dma_write_shutdown_tb +VCD_FILE adi_library/axi_dmac/tb/dma_write_tb.v /^ parameter VCD_FILE = {`__FILE__,"cd"};$/;" c module:dmac_dma_write_tb +VCD_FILE adi_library/axi_dmac/tb/regmap_tb.v /^ parameter VCD_FILE = {`__FILE__,"cd"};$/;" c module:dmac_regmap_tb +VCD_FILE adi_library/axi_dmac/tb/reset_manager_tb.v /^ parameter VCD_FILE = {`__FILE__,"cd"};$/;" c module:dmac_reset_manager_tb +VCD_FILE adi_library/util_pack/tb/cpack_tb.v /^ parameter VCD_FILE = {`__FILE__,"cd"};$/;" c module:cpack_tb +VCD_FILE adi_library/util_pack/tb/underflow_tb.v /^ parameter VCD_FILE = {`__FILE__,"cd"};$/;" c module:upack2_underflow_tb +VCD_FILE adi_library/util_pack/tb/upack_tb.v /^ parameter VCD_FILE = {`__FILE__,"cd"};$/;" c module:upack_tb +VEC_WIDTH hdl/MagnitudeEstimator.v /^ parameter VEC_WIDTH = 21$/;" c module:MagnitudeEstimator +VERSION adi_library/common/up_adc_common.v /^ localparam VERSION = 32'h000a0162;$/;" c module:up_adc_common +VERSION adi_library/common/up_dac_common.v /^ localparam VERSION = 32'h00090162;$/;" c module:up_dac_common +VERSION adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ localparam [31:0] VERSION = 32'h00110161;$/;" c module:axi_adxcvr_up +VERSION adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ localparam [31:0] VERSION = 32'h00100161;$/;" c module:axi_xcvrlb +WIDTH hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ parameter WIDTH = 4'd8, \/\/量化比特$/;" c module:CCSDS_LDPC_DEC_K1024_R12_TOPP +WIDTH hdl/add_prefix.v /^ parameter WIDTH = 2,$/;" c module:add_prefix +WIDTH_DEST adi_library/axi_dmac/tb/dma_read_tb.v /^ parameter WIDTH_DEST = 32;$/;" c module:dmac_dma_read_tb +WIDTH_DEST adi_library/axi_dmac/tb/dma_write_tb.v /^ parameter WIDTH_DEST = 32;$/;" c module:dmac_dma_write_tb +WIDTH_SRC adi_library/axi_dmac/tb/dma_read_tb.v /^ parameter WIDTH_SRC = 32;$/;" c module:dmac_dma_read_tb +WIDTH_SRC adi_library/axi_dmac/tb/dma_write_tb.v /^ parameter WIDTH_SRC = 32;$/;" c module:dmac_dma_write_tb +WINDOW_DEPTH hdl/PAPR.v /^ parameter WINDOW_DEPTH = 1023$/;" c module:PAPR +WORDS_PER_GROUP adi_library/common/ad_perfect_shuffle.v /^ parameter WORDS_PER_GROUP = 2,$/;" c module:ad_perfect_shuffle +WORD_WIDTH adi_library/common/ad_perfect_shuffle.v /^ parameter WORD_WIDTH = 8$/;" c module:ad_perfect_shuffle +WRITE_ACCEPTANCE adi_library/axi_dmac/tb/axi_write_slave.v /^ parameter WRITE_ACCEPTANCE = 3$/;" c module:axi_write_slave +XCVR_ID adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ parameter integer XCVR_ID = 0;$/;" c module:axi_adxcvr_mdrp +XCVR_ID adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ parameter integer XCVR_ID = 0;$/;" c module:axi_adxcvr_mstatus +XCVR_TYPE adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter integer XCVR_TYPE = 0,$/;" c module:axi_adxcvr +XCVR_TYPE adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ parameter integer XCVR_TYPE = 0;$/;" c module:axi_adxcvr_es +XCVR_TYPE adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter integer XCVR_TYPE = 0,$/;" c module:axi_adxcvr_up +XCVR_TYPE adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ parameter XCVR_TYPE = 2) ($/;" c module:axi_xcvrlb +XCVR_TYPE adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ parameter XCVR_TYPE = 2$/;" c module:axi_xcvrlb_1 +XCVR_TYPE adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer XCVR_TYPE = 0,$/;" c module:util_adxcvr +XCVR_TYPE adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer XCVR_TYPE = 0,$/;" c module:util_adxcvr_xch +XCVR_TYPE adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ parameter integer XCVR_TYPE = 0,$/;" c module:util_adxcvr_xcm +XFER_END adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam XFER_END = 5'b10000;$/;" c module:axi_dacfifo_rd +XFER_END adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam XFER_END = 9'b100000000;$/;" c module:axi_dacfifo_wr +XFER_FB_WLAST adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam XFER_FB_WLAST = 9'b000001000;$/;" c module:axi_dacfifo_wr +XFER_FULL_BURST adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam XFER_FULL_BURST = 5'b00100;$/;" c module:axi_dacfifo_rd +XFER_FULL_BURST adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam XFER_FULL_BURST = 9'b000000100;$/;" c module:axi_dacfifo_wr +XFER_LAST_BURST adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam XFER_LAST_BURST = 9'b001000000;$/;" c module:axi_dacfifo_wr +XFER_LB_WLAST adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam XFER_LB_WLAST = 9'b010000000;$/;" c module:axi_dacfifo_wr +XFER_PARTIAL_BURST adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam XFER_PARTIAL_BURST = 5'b01000;$/;" c module:axi_dacfifo_rd +XFER_PARTIAL_BURST adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam XFER_PARTIAL_BURST = 9'b000010000;$/;" c module:axi_dacfifo_wr +XFER_PB_WLAST adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam XFER_PB_WLAST = 9'b000100000;$/;" c module:axi_dacfifo_wr +XFER_STAGING adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ localparam XFER_STAGING = 5'b00010;$/;" c module:axi_dacfifo_rd +XFER_STAGING adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ localparam XFER_STAGING = 9'b000000010;$/;" c module:axi_dacfifo_wr +X_FSCALE adi_library/common/ad_dds_sine_cordic.v /^ localparam X_FSCALE = 1 << (CORDIC_DW);$/;" c module:ad_dds_sine_cordic +X_VALUE adi_library/common/ad_dds_sine_cordic.v /^ localparam [CORDIC_DW-1:0] X_VALUE = ((X_FSCALE\/2)\/(1.64676))-APROX_DW_GAIN_ERR;$/;" c module:ad_dds_sine_cordic +YCbCr_2_RGB adi_library/common/ad_csc.v /^ parameter YCbCr_2_RGB = 0) ($/;" c module:ad_csc +Zerozone_vio hdl/Chn_Estimate.v /^ input [7:0] Zerozone_vio,$/;" p module:Chn_Estimate +Zerozone_vio hdl/SC_FDE_TOP.v /^ input [7:0] Zerozone_vio, \/\/零域估计，默认值为8'd29$/;" p module:SC_FDE_TOP +_dest_diag_level_bursts adi_library/axi_dmac/axi_dmac_burst_memory.v /^ reg [ID_WIDTH-1:0] _dest_diag_level_bursts = 'h0;$/;" r module:axi_dmac_burst_memory +_m_axis_level adi_library/util_axis_fifo/util_axis_fifo.v /^ wire [ADDRESS_WIDTH:0] _m_axis_level;$/;" n module:util_axis_fifo +_m_axis_raddr adi_library/util_axis_fifo/address_gray.v /^reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;$/;" r module:fifo_address_gray +_m_axis_raddr adi_library/util_axis_fifo/address_gray_pipelined.v /^reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;$/;" r module:fifo_address_gray_pipelined +_m_axis_raddr_next adi_library/util_axis_fifo/address_gray.v /^reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;$/;" r module:fifo_address_gray +_m_axis_raddr_next adi_library/util_axis_fifo/address_gray_pipelined.v /^reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;$/;" r module:fifo_address_gray_pipelined +_m_axis_ready adi_library/util_axis_fifo/util_axis_fifo.v /^ wire _m_axis_ready;$/;" n module:util_axis_fifo +_m_axis_valid adi_library/util_axis_fifo/util_axis_fifo.v /^ wire _m_axis_valid;$/;" n module:util_axis_fifo +_m_axis_waddr adi_library/util_axis_fifo/address_gray_pipelined.v /^wire [ADDRESS_WIDTH:0] _m_axis_waddr;$/;" n module:fifo_address_gray_pipelined +_s_axis_raddr adi_library/util_axis_fifo/address_gray_pipelined.v /^wire [ADDRESS_WIDTH:0] _s_axis_raddr;$/;" n module:fifo_address_gray_pipelined +_s_axis_waddr adi_library/util_axis_fifo/address_gray.v /^reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;$/;" r module:fifo_address_gray +_s_axis_waddr adi_library/util_axis_fifo/address_gray_pipelined.v /^reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;$/;" r module:fifo_address_gray_pipelined +_s_axis_waddr_next adi_library/util_axis_fifo/address_gray.v /^reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;$/;" r module:fifo_address_gray +_s_axis_waddr_next adi_library/util_axis_fifo/address_gray_pipelined.v /^reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;$/;" r module:fifo_address_gray_pipelined +a adi_library/axi_dmac/request_arb.v /^ input [ID_WIDTH-1:0] a;$/;" p function:dmac_request_arb.compare_id +abort_req adi_library/axi_dmac/axi_dmac_transfer.v /^wire abort_req;$/;" n module:axi_dmac_transfer +abort_req adi_library/axi_dmac/request_arb.v /^ output abort_req,$/;" p module:dmac_request_arb +abort_req adi_library/axi_dmac/request_generator.v /^ output abort_req,$/;" p module:dmac_request_generator +abs_ZF hdl/Chn_Estimate.v /^wire [18:0] abs_ZF;$/;" n module:Chn_Estimate +abs_ZF_nd hdl/Chn_Estimate.v /^wire abs_ZF_nd;$/;" n module:Chn_Estimate +abs_check hdl/RecvTop.v /^ output [10:0] abs_check,$/;" p module:RecvTop +abs_i hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] abs_i;$/;" r module:MagnitudeEstimator +abs_pilot2 hdl/Chn_Estimate.v /^abs_pilot2 abs_pilot2 ($/;" i module:Chn_Estimate typeref:module:abs_pilot2 +abs_q hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] abs_q;$/;" r module:MagnitudeEstimator +abs_ref hdl/RecvTop.v /^ output [10:0] abs_ref,$/;" p module:RecvTop +acc1 adi_library/common/util_dec256sinc24b.v /^ reg [36:0] acc1 = 37'h0;$/;" r module:util_dec256sinc24b +acc1_s adi_library/common/util_dec256sinc24b.v /^ wire [36:0] acc1_s;$/;" n module:util_dec256sinc24b +acc2 adi_library/common/util_dec256sinc24b.v /^ reg [36:0] acc2 = 37'h0;$/;" r module:util_dec256sinc24b +acc2_s adi_library/common/util_dec256sinc24b.v /^ wire [36:0] acc2_s;$/;" n module:util_dec256sinc24b +acc3 adi_library/common/util_dec256sinc24b.v /^ reg [36:0] acc3 = 37'h0;$/;" r module:util_dec256sinc24b +acc3_d adi_library/common/util_dec256sinc24b.v /^ reg [36:0] acc3_d = 37'h0;$/;" r module:util_dec256sinc24b +acc3_s adi_library/common/util_dec256sinc24b.v /^ wire [36:0] acc3_s;$/;" n module:util_dec256sinc24b +acc_01 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_01 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_01 hdl/TSync_Abs_new4.v /^ reg [19:0] acc_01 = 20'd0;$/;" r module:TSync_Abs_new4 +acc_01_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_01_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_01_reg hdl/TSync_Abs_new4.v /^ reg [19:0] acc_01_reg = 20'd0;$/;" r module:TSync_Abs_new4 +acc_02 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_02 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_02 hdl/TSync_Abs_new4.v /^ reg [19:0] acc_02 = 20'd0;$/;" r module:TSync_Abs_new4 +acc_02_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_02_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_02_reg hdl/TSync_Abs_new4.v /^ reg [19:0] acc_02_reg = 20'd0;$/;" r module:TSync_Abs_new4 +acc_03 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_03 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_03 hdl/TSync_Abs_new4.v /^ reg [19:0] acc_03 = 20'd0;$/;" r module:TSync_Abs_new4 +acc_03_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_03_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_03_reg hdl/TSync_Abs_new4.v /^ reg [19:0] acc_03_reg = 20'd0;$/;" r module:TSync_Abs_new4 +acc_04 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_04 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_04 hdl/TSync_Abs_new4.v /^ reg [19:0] acc_04 = 20'd0;$/;" r module:TSync_Abs_new4 +acc_04_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_04_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_04_reg hdl/TSync_Abs_new4.v /^ reg [19:0] acc_04_reg = 20'd0;$/;" r module:TSync_Abs_new4 +acc_05 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_05 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_05_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_05_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_06 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_06 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_06_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_06_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_07 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_07 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_07_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_07_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_08 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_08 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_08_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_08_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_09 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_09 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_09_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_09_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_10 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_10 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_10_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_10_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_11 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_11 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_11_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_11_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_12 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_12 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_12_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_12_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_13 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_13 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_13_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_13_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_14 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_14 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_14_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_14_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_15 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_15 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_15_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_15_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_16 hdl/TSync_Abs_new16.v /^ reg [19:0] acc_16 = 20'd0;$/;" r module:TSync_Abs_new16 +acc_16_reg hdl/TSync_Abs_new16.v /^ reg [19:0] acc_16_reg = 20'd0;$/;" r module:TSync_Abs_new16 +acc_com_i hdl/freqestm.v /^ reg [31:0] acc_com_i;$/;" r module:freqestm +acc_com_q hdl/freqestm.v /^ reg [31:0] acc_com_q;$/;" r module:freqestm +acc_mean hdl/RecvTop.v /^ output [12:0] acc_mean,$/;" p module:RecvTop +acc_rdy hdl/freqestm.v /^ reg acc_rdy;$/;" r module:freqestm +acked adi_library/axi_dmac/splitter.v /^reg [NUM_M-1:0] acked;$/;" r module:splitter +aclk adi_library/util_fir_dec/util_fir_dec.v /^ input aclk,$/;" p module:util_fir_dec +aclk adi_library/util_fir_int/util_fir_int.v /^ input aclk,$/;" p module:util_fir_int +acq_freindex hdl/DDS_compensate.v /^ wire [4:0] acq_freindex; \/\/-- 捕获频偏$/;" n module:DDS_compensate +acq_nd hdl/DDS_compensate.v /^ input acq_nd;$/;" p module:DDS_compensate +active adi_library/axi_dmac/data_mover.v /^reg active = 1'b0;$/;" r module:dmac_data_mover +active adi_library/axi_dmac/dest_axi_stream.v /^reg active = 1'b0;$/;" r module:dmac_dest_axi_stream +active adi_library/axi_dmac/dest_fifo_inf.v /^reg active = 1'b0;$/;" r module:dmac_dest_fifo_inf +active adi_library/axi_dmac/response_handler.v /^wire active = id != request_id;$/;" n module:dmac_response_handler +active adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg active,$/;" p module:spi_engine_execution +active adi_library/util_cic/cic_comb.v /^reg active = 1'b0;$/;" r module:cic_comb +ad9361_ctrl_in hdl/RecvTop.v /^ output [3:0] ad9361_ctrl_in,$/;" p module:RecvTop +ad9361_ctrl_in hdl/ad9361_mgc_pin_ctrl.v /^ output wire [ 3:0] ad9361_ctrl_in,$/;" p module:ad9361_mgc_pin_ctrl +ad9361_ctrl_in hdl/system_top.v /^ output wire [ 3:0] ad9361_ctrl_in, \/\/ ad9361 control in pins, for fastlock control$/;" p module:system_top +ad9361_dp_fdd_1r1t hdl/ad9361_dp_fdd_1r1t.v /^module ad9361_dp_fdd_1r1t ($/;" m +ad9361_dp_fdd_1r1t_inst hdl/system_top.v /^ ad9361_dp_fdd_1r1t ad9361_dp_fdd_1r1t_inst ($/;" i module:system_top typeref:module:ad9361_dp_fdd_1r1t +ad9361_en_agc hdl/system_top.v /^ output ad9361_en_agc, \/\/ enable AGC, active high$/;" p module:system_top +ad9361_enable hdl/system_top.v /^ output ad9361_enable, \/\/ enable ad9361, active high$/;" p module:system_top +ad9361_mgc_pin_ctrl hdl/ad9361_mgc_pin_ctrl.v /^module ad9361_mgc_pin_ctrl ($/;" m +ad9361_reset_b hdl/system_top.v /^ output ad9361_reset_b, \/\/ asynchronous reset, active low$/;" p module:system_top +ad9361_rx_clk hdl/system_top.v /^ input ad9361_rx_clk, \/\/ ad9361 receive data clock output$/;" p module:system_top +ad9361_rx_clk sim/tb_tx_with_enc.v /^ reg ad9361_rx_clk = 0; \/\/ 50MHz$/;" r module:tb_tx_with_enc +ad9361_rx_data hdl/system_top.v /^ input [11:0] ad9361_rx_data, \/\/ ad9361 receive data $/;" p module:system_top +ad9361_rx_data_i hdl/Receiver.v /^ input [11:0] ad9361_rx_data_i,$/;" p module:Receiver +ad9361_rx_data_i hdl/system_top.v /^ wire [11:0] ad9361_rx_data_i;$/;" n module:system_top +ad9361_rx_data_i sim/TB_sys.v /^ wire [11:0] ad9361_rx_data_i;$/;" n module:TB_sys +ad9361_rx_data_i sim/tb_Receiver.v /^ reg [11:0] ad9361_rx_data_i;$/;" r module:tb_Receiver +ad9361_rx_data_i sim/tb_tx_with_enc.v /^ wire [11:0] ad9361_rx_data_i;$/;" n module:tb_tx_with_enc +ad9361_rx_data_q hdl/Receiver.v /^ input [11:0] ad9361_rx_data_q,$/;" p module:Receiver +ad9361_rx_data_q hdl/system_top.v /^ wire [11:0] ad9361_rx_data_q;$/;" n module:system_top +ad9361_rx_data_q sim/TB_sys.v /^ wire [11:0] ad9361_rx_data_q;$/;" n module:TB_sys +ad9361_rx_data_q sim/tb_Receiver.v /^ reg [11:0] ad9361_rx_data_q;$/;" r module:tb_Receiver +ad9361_rx_data_q sim/tb_tx_with_enc.v /^ wire [11:0] ad9361_rx_data_q;$/;" n module:tb_tx_with_enc +ad9361_rx_frame hdl/system_top.v /^ input ad9361_rx_frame, \/\/ ad9361 receive data frame output signal, indicat/;" p module:system_top +ad9361_rx_frame_i hdl/system_top.v /^ wire ad9361_rx_frame_i;$/;" n module:system_top +ad9361_rx_frame_i sim/TB_sys.v /^ wire ad9361_rx_frame_i;$/;" n module:TB_sys +ad9361_rx_frame_i sim/tb_tx_with_enc.v /^ wire ad9361_rx_frame_i;$/;" n module:tb_tx_with_enc +ad9361_rx_frame_q hdl/system_top.v /^ wire ad9361_rx_frame_q;$/;" n module:system_top +ad9361_rx_frame_q sim/TB_sys.v /^ wire ad9361_rx_frame_q;$/;" n module:TB_sys +ad9361_rx_frame_q sim/tb_tx_with_enc.v /^ wire ad9361_rx_frame_q;$/;" n module:tb_tx_with_enc +ad9361_spi_clk hdl/ad9361_spi_interface.v /^ output ad9361_spi_clk,$/;" p module:ad9361_spi_interface +ad9361_spi_clk hdl/system_top.v /^ output ad9361_spi_clk,$/;" p module:system_top +ad9361_spi_csn hdl/ad9361_spi_interface.v /^ output ad9361_spi_csn,$/;" p module:ad9361_spi_interface +ad9361_spi_csn hdl/system_top.v /^ output ad9361_spi_csn,$/;" p module:system_top +ad9361_spi_interface hdl/ad9361_spi_interface.v /^module ad9361_spi_interface ($/;" m +ad9361_spi_miso hdl/ad9361_spi_interface.v /^ input ad9361_spi_miso,$/;" p module:ad9361_spi_interface +ad9361_spi_miso hdl/system_top.v /^ input ad9361_spi_miso,$/;" p module:system_top +ad9361_spi_mosi hdl/ad9361_spi_interface.v /^ output ad9361_spi_mosi,$/;" p module:ad9361_spi_interface +ad9361_spi_mosi hdl/system_top.v /^ output ad9361_spi_mosi,$/;" p module:system_top +ad9361_tx_clk hdl/system_top.v /^ output ad9361_tx_clk, \/\/ ad9361 feedback clock$/;" p module:system_top +ad9361_tx_data hdl/system_top.v /^ output [11:0] ad9361_tx_data, \/\/ ad9361 transmit data$/;" p module:system_top +ad9361_tx_data_i hdl/Transmitter.v /^ output wire [11:0] ad9361_tx_data_i,$/;" p module:Transmitter +ad9361_tx_data_i hdl/system_top.v /^ wire [11:0] ad9361_tx_data_i;$/;" n module:system_top +ad9361_tx_data_i sim/TB_sys.v /^ wire [11:0] ad9361_tx_data_i;$/;" n module:TB_sys +ad9361_tx_data_i sim/tb_tx_with_enc.v /^ wire [11:0] ad9361_tx_data_i;$/;" n module:tb_tx_with_enc +ad9361_tx_data_q hdl/Transmitter.v /^ output wire [11:0] ad9361_tx_data_q,$/;" p module:Transmitter +ad9361_tx_data_q hdl/system_top.v /^ wire [11:0] ad9361_tx_data_q;$/;" n module:system_top +ad9361_tx_data_q sim/TB_sys.v /^ wire [11:0] ad9361_tx_data_q;$/;" n module:TB_sys +ad9361_tx_data_q sim/tb_tx_with_enc.v /^ wire [11:0] ad9361_tx_data_q;$/;" n module:tb_tx_with_enc +ad9361_tx_frame hdl/system_top.v /^ output ad9361_tx_frame, \/\/ ad9361 transmit data frame input signal, indicat/;" p module:system_top +ad9361_txnrx hdl/system_top.v /^ output ad9361_txnrx, \/\/ logic low selects the RX, logic high selects the/;" p module:system_top +ad_3w_spi adi_library/common/ad_3w_spi.v /^module ad_3w_spi #($/;" m +ad_addsub adi_library/common/ad_addsub.v /^module ad_addsub #($/;" m +ad_adl5904_rst adi_library/common/ad_adl5904_rst.v /^module ad_adl5904_rst ($/;" m +ad_axis_inf_rx adi_library/common/ad_axis_inf_rx.v /^module ad_axis_inf_rx #($/;" m +ad_b2g adi_library/common/ad_b2g.v /^module ad_b2g #($/;" m +ad_bus_mux adi_library/common/ad_bus_mux.v /^module ad_bus_mux #($/;" m +ad_csc adi_library/common/ad_csc.v /^module ad_csc #($/;" m +ad_csc_CrYCb2RGB adi_library/common/ad_csc_CrYCb2RGB.v /^module ad_csc_CrYCb2RGB #($/;" m +ad_csc_RGB2CrYCb adi_library/common/ad_csc_RGB2CrYCb.v /^module ad_csc_RGB2CrYCb #($/;" m +ad_data_clk adi_library/xilinx/common/ad_data_clk.v /^module ad_data_clk #($/;" m +ad_data_in adi_library/xilinx/common/ad_data_in.v /^module ad_data_in #($/;" m +ad_data_out adi_library/xilinx/common/ad_data_out.v /^module ad_data_out #($/;" m +ad_datafmt adi_library/common/ad_datafmt.v /^module ad_datafmt #($/;" m +ad_dcfilter adi_library/xilinx/common/ad_dcfilter.v /^module ad_dcfilter #($/;" m +ad_dds adi_library/common/ad_dds.v /^module ad_dds #($/;" m +ad_dds_1 adi_library/common/ad_dds_1.v /^module ad_dds_1 #($/;" m +ad_dds_2 adi_library/common/ad_dds_2.v /^module ad_dds_2 #($/;" m +ad_dds_cordic_pipe adi_library/common/ad_dds_cordic_pipe.v /^module ad_dds_cordic_pipe#($/;" m +ad_dds_sine adi_library/common/ad_dds_sine.v /^module ad_dds_sine #($/;" m +ad_dds_sine_cordic adi_library/common/ad_dds_sine_cordic.v /^module ad_dds_sine_cordic #($/;" m +ad_edge_detect adi_library/common/ad_edge_detect.v /^module ad_edge_detect #($/;" m +ad_g2b adi_library/common/ad_g2b.v /^module ad_g2b #($/;" m +ad_iobuf adi_library/common/ad_iobuf.v /^module ad_iobuf #($/;" m +ad_iqcor adi_library/common/ad_iqcor.v /^module ad_iqcor #($/;" m +ad_mem adi_library/common/ad_mem.v /^module ad_mem #($/;" m +ad_mem_asym adi_library/common/ad_mem_asym.v /^module ad_mem_asym #($/;" m +ad_mmcm_drp adi_library/xilinx/common/ad_mmcm_drp.v /^module ad_mmcm_drp #($/;" m +ad_mul adi_library/xilinx/common/ad_mul.v /^module ad_mul #($/;" m +ad_perfect_shuffle adi_library/common/ad_perfect_shuffle.v /^module ad_perfect_shuffle #($/;" m +ad_pngen adi_library/common/ad_pngen.v /^module ad_pngen #($/;" m +ad_pnmon adi_library/common/ad_pnmon.v /^module ad_pnmon #($/;" m +ad_pps_receiver adi_library/common/ad_pps_receiver.v /^module ad_pps_receiver ($/;" m +ad_rst adi_library/common/ad_rst.v /^module ad_rst ($/;" m +ad_serdes_clk adi_library/xilinx/common/ad_serdes_clk.v /^module ad_serdes_clk #($/;" m +ad_serdes_in adi_library/xilinx/common/ad_serdes_in.v /^module ad_serdes_in #($/;" m +ad_serdes_out adi_library/xilinx/common/ad_serdes_out.v /^module ad_serdes_out #($/;" m +ad_ss_422to444 adi_library/common/ad_ss_422to444.v /^module ad_ss_422to444 #($/;" m +ad_ss_444to422 adi_library/common/ad_ss_444to422.v /^module ad_ss_444to422 #($/;" m +ad_sysref_gen adi_library/common/ad_sysref_gen.v /^module ad_sysref_gen ($/;" m +ad_tdd_control adi_library/common/ad_tdd_control.v /^module ad_tdd_control#($/;" m +ad_xcvr_rx_if adi_library/common/ad_xcvr_rx_if.v /^module ad_xcvr_rx_if #($/;" m +adc_capture_arm adi_library/util_adcfifo/util_adcfifo.v /^ reg adc_capture_arm = 1'b0;$/;" r module:util_adcfifo +adc_clk adi_library/common/ad_pnmon.v /^ input adc_clk,$/;" p module:ad_pnmon +adc_clk adi_library/common/up_adc_channel.v /^ input adc_clk,$/;" p module:up_adc_channel +adc_clk adi_library/common/up_adc_common.v /^ input adc_clk,$/;" p module:up_adc_common +adc_clk adi_library/util_adcfifo/util_adcfifo.v /^ input adc_clk,$/;" p module:util_adcfifo +adc_clk adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input adc_clk,$/;" p module:axi_adcfifo +adc_clk adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ input adc_clk,$/;" p module:axi_adcfifo_adc +adc_clk adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input adc_clk,$/;" p module:axi_adcfifo_wr +adc_clk_ratio adi_library/common/up_adc_common.v /^ input [31:0] adc_clk_ratio,$/;" p module:up_adc_common +adc_data_in adi_library/common/ad_pnmon.v /^ input [(DATA_WIDTH-1):0] adc_data_in,$/;" p module:ad_pnmon +adc_data_pn adi_library/common/ad_pnmon.v /^ input [(DATA_WIDTH-1):0] adc_data_pn,$/;" p module:ad_pnmon +adc_data_sel adi_library/common/up_adc_channel.v /^ output [ 3:0] adc_data_sel,$/;" p module:up_adc_channel +adc_dcfilt_coeff adi_library/common/up_adc_channel.v /^ output [15:0] adc_dcfilt_coeff,$/;" p module:up_adc_channel +adc_dcfilt_enb adi_library/common/up_adc_channel.v /^ output adc_dcfilt_enb,$/;" p module:up_adc_channel +adc_dcfilt_offset adi_library/common/up_adc_channel.v /^ output [15:0] adc_dcfilt_offset,$/;" p module:up_adc_channel +adc_ddata adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ output reg [AXI_DATA_WIDTH-1:0] adc_ddata,$/;" p module:axi_adcfifo_adc +adc_ddata_s adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ wire [AXI_DATA_WIDTH-1:0] adc_ddata_s;$/;" n module:axi_adcfifo +adc_ddr_edgesel adi_library/common/up_adc_common.v /^ output adc_ddr_edgesel,$/;" p module:up_adc_common +adc_dfmt_enable adi_library/common/up_adc_channel.v /^ output adc_dfmt_enable,$/;" p module:up_adc_channel +adc_dfmt_se adi_library/common/up_adc_channel.v /^ output adc_dfmt_se,$/;" p module:up_adc_channel +adc_dfmt_type adi_library/common/up_adc_channel.v /^ output adc_dfmt_type,$/;" p module:up_adc_channel +adc_dwr adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ output reg adc_dwr,$/;" p module:axi_adcfifo_adc +adc_dwr_s adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ wire adc_dwr_s;$/;" n module:axi_adcfifo +adc_enable adi_library/common/up_adc_channel.v /^ output adc_enable,$/;" p module:up_adc_channel +adc_end_of_capture_s adi_library/util_adcfifo/util_adcfifo.v /^ wire adc_end_of_capture_s;$/;" n module:util_adcfifo +adc_iqcor_coeff_1 adi_library/common/up_adc_channel.v /^ output [15:0] adc_iqcor_coeff_1,$/;" p module:up_adc_channel +adc_iqcor_coeff_2 adi_library/common/up_adc_channel.v /^ output [15:0] adc_iqcor_coeff_2,$/;" p module:up_adc_channel +adc_iqcor_enb adi_library/common/up_adc_channel.v /^ output adc_iqcor_enb,$/;" p module:up_adc_channel +adc_num_lanes adi_library/common/up_adc_common.v /^ output [4:0] adc_num_lanes,$/;" p module:up_adc_common +adc_or adi_library/common/up_adc_channel.v /^ input adc_or,$/;" p module:up_adc_channel +adc_pattern_has_zero adi_library/common/ad_pnmon.v /^ input adc_pattern_has_zero,$/;" p module:ad_pnmon +adc_pin_mode adi_library/common/up_adc_common.v /^ output adc_pin_mode,$/;" p module:up_adc_common +adc_pn_err adi_library/common/ad_pnmon.v /^ output adc_pn_err$/;" p module:ad_pnmon +adc_pn_err adi_library/common/up_adc_channel.v /^ input adc_pn_err,$/;" p module:up_adc_channel +adc_pn_err_int adi_library/common/ad_pnmon.v /^ reg adc_pn_err_int = 'd0;$/;" r module:ad_pnmon +adc_pn_err_s adi_library/common/ad_pnmon.v /^ wire adc_pn_err_s;$/;" n module:ad_pnmon +adc_pn_match_d adi_library/common/ad_pnmon.v /^ reg adc_pn_match_d = 'd0;$/;" r module:ad_pnmon +adc_pn_match_d_s adi_library/common/ad_pnmon.v /^ wire adc_pn_match_d_s;$/;" n module:ad_pnmon +adc_pn_match_s adi_library/common/ad_pnmon.v /^ wire adc_pn_match_s;$/;" n module:ad_pnmon +adc_pn_match_z adi_library/common/ad_pnmon.v /^ reg adc_pn_match_z = 'd0;$/;" r module:ad_pnmon +adc_pn_match_z_s adi_library/common/ad_pnmon.v /^ wire adc_pn_match_z_s;$/;" n module:ad_pnmon +adc_pn_oos adi_library/common/ad_pnmon.v /^ output adc_pn_oos,$/;" p module:ad_pnmon +adc_pn_oos adi_library/common/up_adc_channel.v /^ input adc_pn_oos,$/;" p module:up_adc_channel +adc_pn_oos_count adi_library/common/ad_pnmon.v /^ reg [CNT_W-1:0] adc_pn_oos_count = 'd0;$/;" r module:ad_pnmon +adc_pn_oos_int adi_library/common/ad_pnmon.v /^ reg adc_pn_oos_int = 'd0;$/;" r module:ad_pnmon +adc_pn_update_s adi_library/common/ad_pnmon.v /^ wire adc_pn_update_s;$/;" n module:ad_pnmon +adc_pnseq_sel adi_library/common/up_adc_channel.v /^ output [ 3:0] adc_pnseq_sel,$/;" p module:up_adc_channel +adc_r1_mode adi_library/common/up_adc_common.v /^ output adc_r1_mode,$/;" p module:up_adc_common +adc_rel_enable adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg adc_rel_enable = 'd0;$/;" r module:axi_adcfifo_wr +adc_rel_toggle adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg adc_rel_toggle = 'd0;$/;" r module:axi_adcfifo_wr +adc_rel_waddr adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 7:0] adc_rel_waddr = 'd0;$/;" r module:axi_adcfifo_wr +adc_rst adi_library/common/up_adc_channel.v /^ input adc_rst,$/;" p module:up_adc_channel +adc_rst adi_library/common/up_adc_common.v /^ output adc_rst,$/;" p module:up_adc_common +adc_rst adi_library/util_adcfifo/util_adcfifo.v /^ input adc_rst,$/;" p module:util_adcfifo +adc_rst adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input adc_rst,$/;" p module:axi_adcfifo +adc_rst adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ input adc_rst,$/;" p module:axi_adcfifo_adc +adc_rst adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input adc_rst,$/;" p module:axi_adcfifo_wr +adc_rst_n adi_library/common/up_adc_common.v /^ wire adc_rst_n;$/;" n module:up_adc_common +adc_rst_s adi_library/common/up_adc_common.v /^ wire adc_rst_s;$/;" n module:up_adc_common +adc_rst_s adi_library/util_adcfifo/util_adcfifo.v /^ wire adc_rst_s;$/;" n module:util_adcfifo +adc_sdr_ddr_n adi_library/common/up_adc_common.v /^ output adc_sdr_ddr_n,$/;" p module:up_adc_common +adc_sref_sync adi_library/common/up_adc_common.v /^ output adc_sref_sync,$/;" p module:up_adc_common +adc_start_code adi_library/common/up_adc_common.v /^ output [31:0] adc_start_code,$/;" p module:up_adc_common +adc_status adi_library/common/up_adc_common.v /^ input adc_status,$/;" p module:up_adc_common +adc_status_ovf adi_library/common/up_adc_common.v /^ input adc_status_ovf,$/;" p module:up_adc_common +adc_sync adi_library/common/up_adc_common.v /^ output adc_sync,$/;" p module:up_adc_common +adc_sync_status adi_library/common/up_adc_common.v /^ input adc_sync_status,$/;" p module:up_adc_common +adc_usr_datatype_be adi_library/common/up_adc_channel.v /^ input adc_usr_datatype_be,$/;" p module:up_adc_channel +adc_usr_datatype_bits adi_library/common/up_adc_channel.v /^ input [ 7:0] adc_usr_datatype_bits,$/;" p module:up_adc_channel +adc_usr_datatype_shift adi_library/common/up_adc_channel.v /^ input [ 7:0] adc_usr_datatype_shift,$/;" p module:up_adc_channel +adc_usr_datatype_signed adi_library/common/up_adc_channel.v /^ input adc_usr_datatype_signed,$/;" p module:up_adc_channel +adc_usr_datatype_total_bits adi_library/common/up_adc_channel.v /^ input [ 7:0] adc_usr_datatype_total_bits,$/;" p module:up_adc_channel +adc_usr_decimation_m adi_library/common/up_adc_channel.v /^ input [15:0] adc_usr_decimation_m,$/;" p module:up_adc_channel +adc_usr_decimation_n adi_library/common/up_adc_channel.v /^ input [15:0] adc_usr_decimation_n,$/;" p module:up_adc_channel +adc_valid_d adi_library/common/ad_pnmon.v /^ reg adc_valid_d = 'd0;$/;" r module:ad_pnmon +adc_valid_in adi_library/common/ad_pnmon.v /^ input adc_valid_in,$/;" p module:ad_pnmon +adc_valid_zero adi_library/common/ad_pnmon.v /^ wire adc_valid_zero;$/;" n module:ad_pnmon +adc_valid_zero_d adi_library/common/ad_pnmon.v /^ reg adc_valid_zero_d = 'b0;$/;" r module:ad_pnmon +adc_waddr adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 7:0] adc_waddr = 'd0;$/;" r module:axi_adcfifo_wr +adc_waddr_g adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 7:0] adc_waddr_g = 'd0;$/;" r module:axi_adcfifo_wr +adc_waddr_int adi_library/util_adcfifo/util_adcfifo.v /^ reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int = 'd0;$/;" r module:util_adcfifo +adc_waddr_int_s adi_library/util_adcfifo/util_adcfifo.v /^ wire [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int_s;$/;" n module:util_adcfifo +adc_wcnt_int adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ reg [ 2:0] adc_wcnt_int = 'd0;$/;" r module:axi_adcfifo_adc +adc_wdata adi_library/util_adcfifo/util_adcfifo.v /^ input [ADC_DATA_WIDTH-1:0] adc_wdata,$/;" p module:util_adcfifo +adc_wdata adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input [ADC_DATA_WIDTH-1:0] adc_wdata,$/;" p module:axi_adcfifo +adc_wdata adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ input [ADC_DATA_WIDTH-1:0] adc_wdata,$/;" p module:axi_adcfifo_adc +adc_wdata adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input [AXI_DATA_WIDTH-1:0] adc_wdata,$/;" p module:axi_adcfifo_wr +adc_wdata_int adi_library/util_adcfifo/util_adcfifo.v /^ reg [ADC_DATA_WIDTH-1:0] adc_wdata_int = 'd0;$/;" r module:util_adcfifo +adc_wovf adi_library/util_adcfifo/util_adcfifo.v /^ output adc_wovf,$/;" p module:util_adcfifo +adc_wovf adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output adc_wovf,$/;" p module:axi_adcfifo +adc_wovf adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ output reg adc_wovf,$/;" p module:axi_adcfifo_adc +adc_wr adi_library/util_adcfifo/util_adcfifo.v /^ input adc_wr,$/;" p module:util_adcfifo +adc_wr adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input adc_wr,$/;" p module:axi_adcfifo +adc_wr adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ input adc_wr,$/;" p module:axi_adcfifo_adc +adc_wr adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input adc_wr,$/;" p module:axi_adcfifo_wr +adc_wr_int adi_library/util_adcfifo/util_adcfifo.v /^ reg adc_wr_int = 'd0;$/;" r module:util_adcfifo +adc_xfer_addr adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 31:0] adc_xfer_addr = 'd0;$/;" r module:axi_adcfifo_wr +adc_xfer_enable adi_library/util_adcfifo/util_adcfifo.v /^ reg adc_xfer_enable = 'd0;$/;" r module:util_adcfifo +adc_xfer_enable adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg adc_xfer_enable = 'd0;$/;" r module:axi_adcfifo_wr +adc_xfer_init adi_library/util_adcfifo/util_adcfifo.v /^ reg adc_xfer_init = 'd0;$/;" r module:util_adcfifo +adc_xfer_init adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg adc_xfer_init = 'd0;$/;" r module:axi_adcfifo_wr +adc_xfer_limit adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg adc_xfer_limit = 'd0;$/;" r module:axi_adcfifo_wr +adc_xfer_req_m adi_library/util_adcfifo/util_adcfifo.v /^ reg [ 2:0] adc_xfer_req_m = 'd0;$/;" r module:util_adcfifo +adc_xfer_req_m adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 2:0] adc_xfer_req_m = 'd0;$/;" r module:axi_adcfifo_wr +adc_xfer_status_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ wire [ 3:0] adc_xfer_status_s;$/;" n module:axi_adcfifo_adc +add_Noisei hdl/Noise_Estimate.v /^ reg [27:0] add_Noisei = 28'd0;$/;" r module:Noise_Estimate +add_Noiseq hdl/Noise_Estimate.v /^ reg [27:0] add_Noiseq = 28'd0;$/;" r module:Noise_Estimate +add_prefix hdl/add_prefix.v /^module add_prefix #($/;" m +add_prefix_in_ready hdl/enc_control.v /^ wire add_prefix_in_ready;$/;" n module:enc_control +add_prefix_start hdl/enc_control.v /^ reg add_prefix_start;$/;" r module:enc_control +add_regi hdl/SCFDE_recv_FrameSync.v /^ wire [18:0] add_regi;$/;" n module:SCFDE_recv_FrameSync +add_regi_19bit hdl/SCFDE_recv_FrameSync.v /^ wire [18:0] add_regi_19bit;$/;" n module:SCFDE_recv_FrameSync +add_regq hdl/SCFDE_recv_FrameSync.v /^ wire [18:0] add_regq;$/;" n module:SCFDE_recv_FrameSync +add_regq_19bit hdl/SCFDE_recv_FrameSync.v /^ wire [18:0] add_regq_19bit;$/;" n module:SCFDE_recv_FrameSync +adder_gen_block hdl/frame_sync.v /^ for (i = 0; i < 512; i = i + 1) begin : adder_gen_block$/;" b module:frame_sync +addr adi_library/axi_dmac/address_generator.v /^ output [DMA_ADDR_WIDTH-1:0] addr,$/;" p module:dmac_address_generator +addr adi_library/axi_dmac/tb/axi_slave.v /^ input [31:0] addr,$/;" p module:axi_slave +addr adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] addr;$/;" p task:dmac_regmap_tb.invert_register +addr adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] addr;$/;" p task:dmac_regmap_tb.read_reg +addr adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] addr;$/;" p task:dmac_regmap_tb.read_reg_check +addr adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] addr;$/;" p task:dmac_regmap_tb.set_reset_reg_value +addr adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] addr;$/;" p task:dmac_regmap_tb.write_reg +addr adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] addr;$/;" p task:dmac_regmap_tb.write_reg_and_update +addr_abs_pilot2 hdl/Chn_Estimate.v /^reg [7:0] addr_abs_pilot2 = 8'd0;$/;" r module:Chn_Estimate +addr_fft_piloti hdl/Chn_Estimate.v /^reg [7:0] addr_fft_piloti = 8'd0;$/;" r module:Chn_Estimate +addr_fft_pilotq hdl/Chn_Estimate.v /^reg [7:0] addr_fft_pilotq = 8'd0;$/;" r module:Chn_Estimate +addr_lut hdl/DAGC_v2.v /^ reg [10:0] addr_lut = 11'd0;$/;" r module:DAGC_v2 +addr_r adi_library/util_var_fifo/util_var_fifo.v /^ output [ADDRESS_WIDTH-1:0] addr_r,$/;" p module:util_var_fifo +addr_ready adi_library/axi_dmac/address_generator.v /^ input addr_ready,$/;" p module:dmac_address_generator +addr_stop hdl/FrameMerge.v /^ output reg [16:0] addr_stop = 17'd0, \/\/给shx，拉高一个clk,与flag_stop对齐，指示/;" p module:FrameMerge +addr_stop hdl/RecvTop.v /^ output [16:0] addr_stop, \/\/给shx，拉高8个clk,与flag_stop对齐，指示位置与最/;" p module:RecvTop +addr_stop_0 hdl/FrameMerge.v /^ output [16:0] addr_stop_0, $/;" p module:FrameMerge +addr_stop_0 hdl/RecvTop.v /^ wire [16:0] addr_stop_0;$/;" n module:RecvTop +addr_tx_test hdl/Transmitter.v /^ reg [12:0] addr_tx_test = 'd0;$/;" r module:Transmitter +addr_valid adi_library/axi_dmac/address_generator.v /^ output reg addr_valid,$/;" p module:dmac_address_generator +addr_valid_d1 adi_library/axi_dmac/address_generator.v /^reg addr_valid_d1;$/;" r module:dmac_address_generator +addr_w adi_library/util_var_fifo/util_var_fifo.v /^ output [ADDRESS_WIDTH-1:0] addr_w,$/;" p module:util_var_fifo +addra adi_library/common/ad_mem.v /^ input [(ADDRESS_WIDTH-1):0] addra,$/;" p module:ad_mem +addra adi_library/common/ad_mem_asym.v /^ input [A_ADDRESS_WIDTH-1:0] addra,$/;" p module:ad_mem_asym +addra adi_library/util_var_fifo/util_var_fifo.v /^ reg [ADDRESS_WIDTH-1:0] addra = 'd0;$/;" r module:util_var_fifo +addra hdl/IQmerge.v /^ reg [9:0] addra = 10'd0;$/;" r module:IQmerge +addra hdl/phase_adjust.v /^ reg [7:0] addra = 8'd0;$/;" r module:phase_adjust +addra_pilot01 hdl/freqestm.v /^ reg [11:0] addra_pilot01;$/;" r module:freqestm +addra_pilot02 hdl/freqestm.v /^ reg [11:0] addra_pilot02;$/;" r module:freqestm +addradelay hdl/IQmerge.v /^ reg [9:0] addradelay = 10'd0;$/;" r module:IQmerge +addradelay hdl/phase_adjust.v /^ reg [9:0] addradelay = 10'd0;$/;" r module:phase_adjust +addrb adi_library/common/ad_mem.v /^ input [(ADDRESS_WIDTH-1):0] addrb,$/;" p module:ad_mem +addrb adi_library/common/ad_mem_asym.v /^ input [B_ADDRESS_WIDTH-1:0] addrb,$/;" p module:ad_mem_asym +addrb adi_library/util_var_fifo/util_var_fifo.v /^ reg [ADDRESS_WIDTH-1:0] addrb = 'd0;$/;" r module:util_var_fifo +addrb hdl/IQmerge.v /^ reg [10:0] addrb = 11'd0;$/;" r module:IQmerge +addrb hdl/phase_adjust.v /^ reg [7:0] addrb = 8'd0;$/;" r module:phase_adjust +addrb_pilot01 hdl/freqestm.v /^ reg [11:0] addrb_pilot01;$/;" r module:freqestm +addrb_pilot02 hdl/freqestm.v /^ reg [11:0] addrb_pilot02;$/;" r module:freqestm +address adi_library/axi_dmac/address_generator.v /^reg [DMA_ADDR_WIDTH-BYTES_PER_BEAT_WIDTH-1:0] address = 'h00;$/;" r module:dmac_address_generator +address_enabled adi_library/axi_dmac/dest_axi_mm.v /^wire address_enabled;$/;" n module:dmac_dest_mm_axi +address_enabled adi_library/axi_dmac/src_axi_mm.v /^wire address_enabled;$/;" n module:dmac_src_mm_axi +address_eot adi_library/axi_dmac/dest_axi_mm.v /^ input address_eot,$/;" p module:dmac_dest_mm_axi +address_eot adi_library/axi_dmac/src_axi_mm.v /^ input address_eot,$/;" p module:dmac_src_mm_axi +address_id adi_library/axi_dmac/dest_axi_mm.v /^ output [ID_WIDTH-1:0] address_id,$/;" p module:dmac_dest_mm_axi +address_id adi_library/axi_dmac/src_axi_mm.v /^ output [ID_WIDTH-1:0] address_id,$/;" p module:dmac_src_mm_axi +addrin_1 hdl/DAGC_v2.v /^ reg [11:0] addrin_1 = 12'd0;$/;" r module:DAGC_v2 +addrin_MMSE hdl/Chn_Estimate.v /^ output reg [7:0] addrin_MMSE = 8'd0,$/;" p module:Chn_Estimate +addrin_MMSE hdl/SC_FDE_TOP.v /^ wire [7:0] addrin_MMSE;$/;" n module:SC_FDE_TOP +addrout_1 hdl/DAGC_v2.v /^ reg [11:0] addrout_1 = 12'd0;$/;" r module:DAGC_v2 +addrout_MMSE hdl/SC_FDE_TOP.v /^ wire [7:0] addrout_MMSE;$/;" n module:SC_FDE_TOP +addrout_MMSE hdl/data_equalizer.v /^ output reg [7:0] addrout_MMSE = 8'd0,$/;" p module:data_equalizer +agc_check hdl/DAGC_v2.v /^ output reg [12:0] agc_check = 13'd0,$/;" p module:DAGC_v2 +agc_check hdl/RecvTop.v /^ output [12:0] agc_check,$/;" p module:RecvTop +agc_ref hdl/DAGC_v2.v /^ output reg [12:0] agc_ref = 13'd0,$/;" p module:DAGC_v2 +agc_ref hdl/RecvTop.v /^ output [12:0] agc_ref,$/;" p module:RecvTop +agc_ref_h hdl/DAGC_v2.v /^ reg [14:0] agc_ref_h = 15'd0;$/;" r module:DAGC_v2 +agc_ref_l hdl/DAGC_v2.v /^ reg [12:0] agc_ref_l = 13'd0;$/;" r module:DAGC_v2 +agc_ref_temp hdl/DAGC_v2.v /^ reg [22:0] agc_ref_temp = 23'd0;$/;" r module:DAGC_v2 +agcdata0 hdl/DAGC_v2.v /^ reg [13:0] agcdata0 = 14'd0;$/;" r module:DAGC_v2 +agcdata1 hdl/DAGC_v2.v /^ reg [13:0] agcdata1 = 14'd0;$/;" r module:DAGC_v2 +angle adi_library/common/ad_dds_1.v /^ input [DDS_P_DW-1:0] angle,$/;" p module:ad_dds_1 +angle adi_library/common/ad_dds_sine.v /^ input [15:0] angle,$/;" p module:ad_dds_sine +angle adi_library/common/ad_dds_sine_cordic.v /^ input [ PHASE_DW-1:0] angle,$/;" p module:ad_dds_sine_cordic +angle_s adi_library/common/ad_dds_sine.v /^ wire [15:0] angle_s;$/;" n module:ad_dds_sine +araddr adi_library/axi_dmac/tb/axi_read_slave.v /^ input [31:0] araddr,$/;" p module:axi_read_slave +araddr adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [31:0] araddr;$/;" n module:dmac_dma_read_shutdown_tb +araddr adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [31:0] araddr;$/;" n module:dmac_dma_read_tb +arburst adi_library/axi_dmac/tb/axi_read_slave.v /^ input [1:0] arburst,$/;" p module:axi_read_slave +arburst adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [1:0] arburst;$/;" n module:dmac_dma_read_shutdown_tb +arburst adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [1:0] arburst;$/;" n module:dmac_dma_read_tb +arcache adi_library/axi_dmac/tb/axi_read_slave.v /^ input [3:0] arcache,$/;" p module:axi_read_slave +arcache adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [3:0] arcache;$/;" n module:dmac_dma_read_shutdown_tb +arcache adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [3:0] arcache;$/;" n module:dmac_dma_read_tb +aread adi_library/common/ad_mem_asym.v /^ for (i = 0; i < MEM_RATIO; i = i + 1) begin : aread$/;" b block:ad_mem_asym.memread +arlen adi_library/axi_dmac/tb/axi_read_slave.v /^ input [7:0] arlen,$/;" p module:axi_read_slave +arlen adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [7:0] arlen;$/;" n module:dmac_dma_read_shutdown_tb +arlen adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [7:0] arlen;$/;" n module:dmac_dma_read_tb +arprot adi_library/axi_dmac/tb/axi_read_slave.v /^ input [2:0] arprot,$/;" p module:axi_read_slave +arprot adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [2:0] arprot;$/;" n module:dmac_dma_read_shutdown_tb +arprot adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [2:0] arprot;$/;" n module:dmac_dma_read_tb +arready adi_library/axi_dmac/tb/axi_read_slave.v /^ output arready,$/;" p module:axi_read_slave +arsize adi_library/axi_dmac/tb/axi_read_slave.v /^ input [2:0] arsize,$/;" p module:axi_read_slave +arsize adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [2:0] arsize;$/;" n module:dmac_dma_read_shutdown_tb +arsize adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [2:0] arsize;$/;" n module:dmac_dma_read_tb +arvalid adi_library/axi_dmac/tb/axi_read_slave.v /^ input arvalid,$/;" p module:axi_read_slave +atan2_freq hdl/freqestm.v /^ atan2_freq atan2_freq ($/;" i module:freqestm typeref:module:atan2_freq +atan2_phase hdl/phase_adjust.v /^ atan2_phase atan2_phase ($/;" i module:phase_adjust typeref:module:atan2_phase +atan2_rotate hdl/phase_adjust.v /^ atan2_rotate atan2_rotate ($/;" i module:phase_adjust typeref:module:atan2_rotate +atan_table adi_library/common/ad_dds_sine_cordic.v /^ wire [ PHASE_DW-1:0] atan_table[0:CORDIC_DW-2];$/;" n module:ad_dds_sine_cordic +average_1024 hdl/SCFDE_recv_FrameSync.v /^ average_1024 average_1024 ($/;" i module:SCFDE_recv_FrameSync typeref:module:average_1024 +average_add10 hdl/SCFDE_recv_FrameSync.v /^ wire [19:0] average_add10;$/;" n module:SCFDE_recv_FrameSync +awaddr adi_library/axi_dmac/tb/axi_write_slave.v /^ input [31:0] awaddr,$/;" p module:axi_write_slave +awaddr adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire [31:0] awaddr;$/;" n module:dmac_dma_write_shutdown_tb +awaddr adi_library/axi_dmac/tb/dma_write_tb.v /^ wire [31:0] awaddr;$/;" n module:dmac_dma_write_tb +awburst adi_library/axi_dmac/tb/axi_write_slave.v /^ input [1:0] awburst,$/;" p module:axi_write_slave +awburst adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire [1:0] awburst;$/;" n module:dmac_dma_write_shutdown_tb +awburst adi_library/axi_dmac/tb/dma_write_tb.v /^ wire [1:0] awburst;$/;" n module:dmac_dma_write_tb +awcache adi_library/axi_dmac/tb/axi_write_slave.v /^ input [3:0] awcache,$/;" p module:axi_write_slave +awcache adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire [3:0] awcache;$/;" n module:dmac_dma_write_shutdown_tb +awcache adi_library/axi_dmac/tb/dma_write_tb.v /^ wire [3:0] awcache;$/;" n module:dmac_dma_write_tb +awlen adi_library/axi_dmac/tb/axi_write_slave.v /^ input [7:0] awlen,$/;" p module:axi_write_slave +awlen adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire [7:0] awlen;$/;" n module:dmac_dma_write_shutdown_tb +awlen adi_library/axi_dmac/tb/dma_write_tb.v /^ wire [7:0] awlen;$/;" n module:dmac_dma_write_tb +awprot adi_library/axi_dmac/tb/axi_write_slave.v /^ input [2:0] awprot,$/;" p module:axi_write_slave +awprot adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire [2:0] awprot;$/;" n module:dmac_dma_write_shutdown_tb +awprot adi_library/axi_dmac/tb/dma_write_tb.v /^ wire [2:0] awprot;$/;" n module:dmac_dma_write_tb +awready adi_library/axi_dmac/tb/axi_write_slave.v /^ output awready,$/;" p module:axi_write_slave +awready adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire awready;$/;" n module:dmac_dma_read_shutdown_tb +awready adi_library/axi_dmac/tb/dma_read_tb.v /^ wire awready;$/;" n module:dmac_dma_read_tb +awready adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire awready;$/;" n module:dmac_dma_write_shutdown_tb +awready adi_library/axi_dmac/tb/dma_write_tb.v /^ wire awready;$/;" n module:dmac_dma_write_tb +awrite adi_library/common/ad_mem_asym.v /^ for (i = 0; i < MEM_RATIO; i = i + 1) begin : awrite$/;" b block:ad_mem_asym.memwrite +awsize adi_library/axi_dmac/tb/axi_write_slave.v /^ input [2:0] awsize,$/;" p module:axi_write_slave +awsize adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire [2:0] awsize;$/;" n module:dmac_dma_write_shutdown_tb +awsize adi_library/axi_dmac/tb/dma_write_tb.v /^ wire [2:0] awsize;$/;" n module:dmac_dma_write_tb +awvalid adi_library/axi_dmac/tb/axi_write_slave.v /^ input awvalid,$/;" p module:axi_write_slave +awvalid adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire awvalid;$/;" n module:dmac_dma_read_shutdown_tb +awvalid adi_library/axi_dmac/tb/dma_read_tb.v /^ wire awvalid;$/;" n module:dmac_dma_read_tb +awvalid adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire awvalid;$/;" n module:dmac_dma_write_shutdown_tb +awvalid adi_library/axi_dmac/tb/dma_write_tb.v /^ wire awvalid;$/;" n module:dmac_dma_write_tb +axi_adcfifo adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^module axi_adcfifo #($/;" m +axi_adcfifo_adc adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^module axi_adcfifo_adc #($/;" m +axi_adcfifo_dma adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^module axi_adcfifo_dma #($/;" m +axi_adcfifo_rd adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^module axi_adcfifo_rd #($/;" m +axi_adcfifo_wr adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^module axi_adcfifo_wr #($/;" m +axi_addr_diff adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [DMA_ADDRESS_WIDTH-1:0] axi_addr_diff = 'd0;$/;" r module:axi_adcfifo_dma +axi_addr_diff adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 7:0] axi_addr_diff = 'd0;$/;" r module:axi_adcfifo_wr +axi_addr_diff_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ wire [DMA_ADDRESS_WIDTH:0] axi_addr_diff_s;$/;" n module:axi_adcfifo_dma +axi_addr_diff_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ wire [ 8:0] axi_addr_diff_s;$/;" n module:axi_adcfifo_wr +axi_adxcvr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^module axi_adxcvr #($/;" m +axi_adxcvr_es adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^module axi_adxcvr_es ($/;" m +axi_adxcvr_mdrp adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^module axi_adxcvr_mdrp ($/;" m +axi_adxcvr_mstatus adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^module axi_adxcvr_mstatus ($/;" m +axi_adxcvr_up adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^module axi_adxcvr_up #($/;" m +axi_almost_empty adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg axi_almost_empty = 'd0;$/;" r module:axi_adcfifo_wr +axi_almost_full adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg axi_almost_full = 'd0;$/;" r module:axi_adcfifo_wr +axi_araddr adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 31:0] axi_araddr,$/;" p module:axi_adcfifo +axi_araddr adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output reg [ 31:0] axi_araddr,$/;" p module:axi_adcfifo_rd +axi_araddr adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 31:0] axi_araddr,$/;" p module:axi_dacfifo +axi_araddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output reg [31:0] axi_araddr,$/;" p module:axi_dacfifo_rd +axi_araddr_prev adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [31:0] axi_araddr_prev = 'd0;$/;" r module:axi_dacfifo_rd +axi_arburst adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 1:0] axi_arburst,$/;" p module:axi_adcfifo +axi_arburst adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output [ 1:0] axi_arburst,$/;" p module:axi_adcfifo_rd +axi_arburst adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 1:0] axi_arburst,$/;" p module:axi_dacfifo +axi_arburst adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output [ 1:0] axi_arburst,$/;" p module:axi_dacfifo_rd +axi_arcache adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 3:0] axi_arcache,$/;" p module:axi_adcfifo +axi_arcache adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output [ 3:0] axi_arcache,$/;" p module:axi_adcfifo_rd +axi_arcache adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 3:0] axi_arcache,$/;" p module:axi_dacfifo +axi_arcache adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output [ 3:0] axi_arcache,$/;" p module:axi_dacfifo_rd +axi_arid adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 3:0] axi_arid,$/;" p module:axi_adcfifo +axi_arid adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output [ 3:0] axi_arid,$/;" p module:axi_adcfifo_rd +axi_arid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 3:0] axi_arid,$/;" p module:axi_dacfifo +axi_arid adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output [ 3:0] axi_arid,$/;" p module:axi_dacfifo_rd +axi_arlen adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 7:0] axi_arlen,$/;" p module:axi_adcfifo +axi_arlen adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output [ 7:0] axi_arlen,$/;" p module:axi_adcfifo_rd +axi_arlen adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 7:0] axi_arlen,$/;" p module:axi_dacfifo +axi_arlen adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output [ 7:0] axi_arlen,$/;" p module:axi_dacfifo_rd +axi_arlock adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output axi_arlock,$/;" p module:axi_adcfifo +axi_arlock adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output axi_arlock,$/;" p module:axi_adcfifo_rd +axi_arlock adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output axi_arlock,$/;" p module:axi_dacfifo +axi_arlock adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output axi_arlock,$/;" p module:axi_dacfifo_rd +axi_arprot adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 2:0] axi_arprot,$/;" p module:axi_adcfifo +axi_arprot adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output [ 2:0] axi_arprot,$/;" p module:axi_adcfifo_rd +axi_arprot adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 2:0] axi_arprot,$/;" p module:axi_dacfifo +axi_arprot adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output [ 2:0] axi_arprot,$/;" p module:axi_dacfifo_rd +axi_arqos adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 3:0] axi_arqos,$/;" p module:axi_adcfifo +axi_arqos adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output [ 3:0] axi_arqos,$/;" p module:axi_adcfifo_rd +axi_arqos adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 3:0] axi_arqos,$/;" p module:axi_dacfifo +axi_arqos adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output [ 3:0] axi_arqos,$/;" p module:axi_dacfifo_rd +axi_arready adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input axi_arready,$/;" p module:axi_adcfifo +axi_arready adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input axi_arready,$/;" p module:axi_adcfifo_rd +axi_arready adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input axi_arready,$/;" p module:axi_dacfifo +axi_arready adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input axi_arready,$/;" p module:axi_dacfifo_rd +axi_arsize adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 2:0] axi_arsize,$/;" p module:axi_adcfifo +axi_arsize adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output [ 2:0] axi_arsize,$/;" p module:axi_adcfifo_rd +axi_arsize adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 2:0] axi_arsize,$/;" p module:axi_dacfifo +axi_arsize adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output [ 2:0] axi_arsize,$/;" p module:axi_dacfifo_rd +axi_aruser adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 3:0] axi_aruser,$/;" p module:axi_adcfifo +axi_aruser adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output [ 3:0] axi_aruser,$/;" p module:axi_adcfifo_rd +axi_arvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output axi_arvalid,$/;" p module:axi_adcfifo +axi_arvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output reg axi_arvalid,$/;" p module:axi_adcfifo_rd +axi_arvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output axi_arvalid,$/;" p module:axi_dacfifo +axi_arvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output reg axi_arvalid,$/;" p module:axi_dacfifo_rd +axi_awaddr adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 31:0] axi_awaddr,$/;" p module:axi_adcfifo +axi_awaddr adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output reg [ 31:0] axi_awaddr,$/;" p module:axi_adcfifo_wr +axi_awaddr adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 31:0] axi_awaddr,$/;" p module:axi_dacfifo +axi_awaddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output reg [31:0] axi_awaddr,$/;" p module:axi_dacfifo_wr +axi_awburst adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 1:0] axi_awburst,$/;" p module:axi_adcfifo +axi_awburst adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [ 1:0] axi_awburst,$/;" p module:axi_adcfifo_wr +axi_awburst adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 1:0] axi_awburst,$/;" p module:axi_dacfifo +axi_awburst adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output [ 1:0] axi_awburst,$/;" p module:axi_dacfifo_wr +axi_awcache adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 3:0] axi_awcache,$/;" p module:axi_adcfifo +axi_awcache adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [ 3:0] axi_awcache,$/;" p module:axi_adcfifo_wr +axi_awcache adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 3:0] axi_awcache,$/;" p module:axi_dacfifo +axi_awcache adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output [ 3:0] axi_awcache,$/;" p module:axi_dacfifo_wr +axi_awid adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 3:0] axi_awid,$/;" p module:axi_adcfifo +axi_awid adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [ 3:0] axi_awid,$/;" p module:axi_adcfifo_wr +axi_awid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 3:0] axi_awid,$/;" p module:axi_dacfifo +axi_awid adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output [ 3:0] axi_awid,$/;" p module:axi_dacfifo_wr +axi_awlen adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 7:0] axi_awlen,$/;" p module:axi_adcfifo +axi_awlen adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [ 7:0] axi_awlen,$/;" p module:axi_adcfifo_wr +axi_awlen adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 7:0] axi_awlen,$/;" p module:axi_dacfifo +axi_awlen adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output [ 7:0] axi_awlen,$/;" p module:axi_dacfifo_wr +axi_awlock adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output axi_awlock,$/;" p module:axi_adcfifo +axi_awlock adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output axi_awlock,$/;" p module:axi_adcfifo_wr +axi_awlock adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output axi_awlock,$/;" p module:axi_dacfifo +axi_awlock adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output axi_awlock,$/;" p module:axi_dacfifo_wr +axi_awprot adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 2:0] axi_awprot,$/;" p module:axi_adcfifo +axi_awprot adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [ 2:0] axi_awprot,$/;" p module:axi_adcfifo_wr +axi_awprot adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 2:0] axi_awprot,$/;" p module:axi_dacfifo +axi_awprot adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output [ 2:0] axi_awprot,$/;" p module:axi_dacfifo_wr +axi_awqos adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 3:0] axi_awqos,$/;" p module:axi_adcfifo +axi_awqos adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [ 3:0] axi_awqos,$/;" p module:axi_adcfifo_wr +axi_awqos adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 3:0] axi_awqos,$/;" p module:axi_dacfifo +axi_awqos adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output [ 3:0] axi_awqos,$/;" p module:axi_dacfifo_wr +axi_awready adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input axi_awready,$/;" p module:axi_adcfifo +axi_awready adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input axi_awready,$/;" p module:axi_adcfifo_wr +axi_awready adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input axi_awready,$/;" p module:axi_dacfifo +axi_awready adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input axi_awready,$/;" p module:axi_dacfifo_wr +axi_awsize adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 2:0] axi_awsize,$/;" p module:axi_adcfifo +axi_awsize adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [ 2:0] axi_awsize,$/;" p module:axi_adcfifo_wr +axi_awsize adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [ 2:0] axi_awsize,$/;" p module:axi_dacfifo +axi_awsize adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output [ 2:0] axi_awsize,$/;" p module:axi_dacfifo_wr +axi_awuser adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 3:0] axi_awuser,$/;" p module:axi_adcfifo +axi_awuser adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [ 3:0] axi_awuser,$/;" p module:axi_adcfifo_wr +axi_awvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output axi_awvalid,$/;" p module:axi_adcfifo +axi_awvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output reg axi_awvalid,$/;" p module:axi_adcfifo_wr +axi_awvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output axi_awvalid,$/;" p module:axi_dacfifo +axi_awvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output reg axi_awvalid,$/;" p module:axi_dacfifo_wr +axi_bid adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input [ 3:0] axi_bid,$/;" p module:axi_adcfifo +axi_bid adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input [ 3:0] axi_bid,$/;" p module:axi_adcfifo_wr +axi_bid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input [ 3:0] axi_bid,$/;" p module:axi_dacfifo +axi_bid adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input [ 3:0] axi_bid,$/;" p module:axi_dacfifo_wr +axi_bready adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output axi_bready,$/;" p module:axi_adcfifo +axi_bready adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output axi_bready,$/;" p module:axi_adcfifo_wr +axi_bready adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output axi_bready,$/;" p module:axi_dacfifo +axi_bready adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output axi_bready,$/;" p module:axi_dacfifo_wr +axi_bresp adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input [ 1:0] axi_bresp,$/;" p module:axi_adcfifo +axi_bresp adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input [ 1:0] axi_bresp,$/;" p module:axi_adcfifo_wr +axi_bresp adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input [ 1:0] axi_bresp,$/;" p module:axi_dacfifo +axi_bresp adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input [ 1:0] axi_bresp,$/;" p module:axi_dacfifo_wr +axi_buser adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input [ 3:0] axi_buser,$/;" p module:axi_adcfifo +axi_buser adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input [ 3:0] axi_buser,$/;" p module:axi_adcfifo_wr +axi_bvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input axi_bvalid,$/;" p module:axi_adcfifo +axi_bvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input axi_bvalid,$/;" p module:axi_adcfifo_wr +axi_bvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input axi_bvalid,$/;" p module:axi_dacfifo +axi_bvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input axi_bvalid,$/;" p module:axi_dacfifo_wr +axi_clk adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input axi_clk,$/;" p module:axi_adcfifo +axi_clk adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ input axi_clk,$/;" p module:axi_adcfifo_adc +axi_clk adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ input axi_clk,$/;" p module:axi_adcfifo_dma +axi_clk adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input axi_clk,$/;" p module:axi_adcfifo_rd +axi_clk adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input axi_clk,$/;" p module:axi_adcfifo_wr +axi_clk adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input axi_clk,$/;" p module:axi_dacfifo +axi_clk adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input axi_clk,$/;" p module:axi_dacfifo_rd +axi_clk adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input axi_clk,$/;" p module:axi_dacfifo_wr +axi_dacfifo adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^module axi_dacfifo #($/;" m +axi_dacfifo_address_buffer adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^module axi_dacfifo_address_buffer #($/;" m +axi_dacfifo_rd adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^module axi_dacfifo_rd #($/;" m +axi_dacfifo_wr adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^module axi_dacfifo_wr #($/;" m +axi_data_req adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg axi_data_req = 1'b0;$/;" r module:axi_dacfifo_rd +axi_ddata adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ input [AXI_DATA_WIDTH-1:0] axi_ddata,$/;" p module:axi_adcfifo_dma +axi_ddata adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output reg [AXI_DATA_WIDTH-1:0] axi_ddata,$/;" p module:axi_adcfifo_rd +axi_ddata_s adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ wire [AXI_DATA_WIDTH-1:0] axi_ddata_s;$/;" n module:axi_adcfifo +axi_dlast_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire axi_dlast_s;$/;" n module:axi_dacfifo_rd +axi_dma_last_beats_m1 adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [ 3:0] axi_dma_last_beats_m1 = 4'b0;$/;" r module:axi_dacfifo_wr +axi_dma_last_beats_m2 adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [ 3:0] axi_dma_last_beats_m2 = 4'b0;$/;" r module:axi_dacfifo_wr +axi_dmac adi_library/axi_dmac/axi_dmac.v /^module axi_dmac #($/;" m +axi_dmac_burst_memory adi_library/axi_dmac/axi_dmac_burst_memory.v /^module axi_dmac_burst_memory #($/;" m +axi_dmac_regmap adi_library/axi_dmac/axi_dmac_regmap.v /^module axi_dmac_regmap #($/;" m +axi_dmac_regmap_request adi_library/axi_dmac/axi_dmac_regmap_request.v /^module axi_dmac_regmap_request #($/;" m +axi_dmac_reset_manager adi_library/axi_dmac/axi_dmac_reset_manager.v /^module axi_dmac_reset_manager #($/;" m +axi_dmac_resize_dest adi_library/axi_dmac/axi_dmac_resize_dest.v /^module axi_dmac_resize_dest #($/;" m +axi_dmac_resize_src adi_library/axi_dmac/axi_dmac_resize_src.v /^module axi_dmac_resize_src #($/;" m +axi_dmac_response_manager adi_library/axi_dmac/axi_dmac_response_manager.v /^module axi_dmac_response_manager #($/;" m +axi_dmac_transfer adi_library/axi_dmac/axi_dmac_transfer.v /^module axi_dmac_transfer #($/;" m +axi_dready adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ output reg axi_dready,$/;" p module:axi_adcfifo_dma +axi_dready adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input axi_dready);$/;" p module:axi_adcfifo_rd +axi_dready_s adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ wire axi_dready_s;$/;" n module:axi_adcfifo +axi_drst adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ input axi_drst,$/;" p module:axi_adcfifo_adc +axi_drst adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ input axi_drst,$/;" p module:axi_adcfifo_dma +axi_drst adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output reg axi_drst,$/;" p module:axi_adcfifo_rd +axi_drst_s adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ wire axi_drst_s;$/;" n module:axi_adcfifo +axi_dvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ input axi_dvalid,$/;" p module:axi_adcfifo_dma +axi_dvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output reg axi_dvalid,$/;" p module:axi_adcfifo_rd +axi_dvalid_s adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ wire axi_dvalid_s;$/;" n module:axi_adcfifo +axi_dvalid_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire axi_dvalid_s;$/;" n module:axi_dacfifo_rd +axi_dwovf adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output reg axi_dwovf,$/;" p module:axi_adcfifo_wr +axi_dwunf adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output reg axi_dwunf,$/;" p module:axi_adcfifo_wr +axi_fifo_reset_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire axi_fifo_reset_s;$/;" n module:axi_dacfifo_rd +axi_fifo_reset_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire axi_fifo_reset_s;$/;" n module:axi_dacfifo_wr +axi_last_addr adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output reg [31:0] axi_last_addr,$/;" p module:axi_dacfifo_wr +axi_last_addr_s adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ (* dont_touch = "true" *) wire [31:0] axi_last_addr_s;$/;" n module:axi_dacfifo +axi_last_beats adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input [ 7:0] axi_last_beats,$/;" p module:axi_dacfifo_rd +axi_last_beats adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output reg [ 7:0] axi_last_beats,$/;" p module:axi_dacfifo_wr +axi_last_beats_s adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ (* dont_touch = "true" *) wire [ 7:0] axi_last_beats_s;$/;" n module:axi_dacfifo +axi_last_burst_length adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [ 7:0] axi_last_burst_length = 8'b0;$/;" r module:axi_dacfifo_wr +axi_last_raddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input [31:0] axi_last_raddr,$/;" p module:axi_dacfifo_rd +axi_mem_addr_diff adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'd0;$/;" r module:axi_dacfifo_rd +axi_mem_addr_diff adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'd0;$/;" r module:axi_dacfifo_wr +axi_mem_addr_diff_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire [ AXI_MEM_ADDRESS_WIDTH:0] axi_mem_addr_diff_s;$/;" n module:axi_dacfifo_rd +axi_mem_addr_diff_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire [AXI_MEM_ADDRESS_WIDTH:0] axi_mem_addr_diff_s;$/;" n module:axi_dacfifo_wr +axi_mem_laddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ (* dont_touch = "true" *) reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0;$/;" r module:axi_dacfifo_rd +axi_mem_laddr_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr_s;$/;" n module:axi_dacfifo_rd +axi_mem_laddr_toggle adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ (* dont_touch = "true" *) reg axi_mem_laddr_toggle = 1'b0;$/;" r module:axi_dacfifo_rd +axi_mem_last adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg axi_mem_last = 1'b0;$/;" r module:axi_dacfifo_wr +axi_mem_last_d adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg axi_mem_last_d = 1'b0;$/;" r module:axi_dacfifo_wr +axi_mem_last_read_toggle adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg axi_mem_last_read_toggle = 1'b0;$/;" r module:axi_dacfifo_wr +axi_mem_last_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire axi_mem_last_s;$/;" n module:axi_dacfifo_wr +axi_mem_raddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0;$/;" r module:axi_dacfifo_rd +axi_mem_raddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0;$/;" r module:axi_dacfifo_wr +axi_mem_raddr_b2g_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_b2g_s;$/;" n module:axi_dacfifo_wr +axi_mem_raddr_g adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_g = 'd0;$/;" r module:axi_dacfifo_wr +axi_mem_raddr_m1 adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m1 = 'd0;$/;" r module:axi_dacfifo_rd +axi_mem_raddr_m2 adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2 = 'd0;$/;" r module:axi_dacfifo_rd +axi_mem_raddr_m2_g2b_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2_g2b_s;$/;" n module:axi_dacfifo_rd +axi_mem_raddr_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_s;$/;" n module:axi_dacfifo_rd +axi_mem_rdata adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(AXI_DATA_WIDTH-1):0] axi_mem_rdata = 'd0;$/;" r module:axi_dacfifo_wr +axi_mem_rdata_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire [(AXI_DATA_WIDTH-1):0] axi_mem_rdata_s;$/;" n module:axi_dacfifo_wr +axi_mem_read_en_d adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg axi_mem_read_en_d = 1'b0;$/;" r module:axi_dacfifo_wr +axi_mem_read_en_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire axi_mem_read_en_s;$/;" n module:axi_dacfifo_wr +axi_mem_rvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg axi_mem_rvalid = 1'b0;$/;" r module:axi_dacfifo_wr +axi_mem_rvalid_d adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg axi_mem_rvalid_d = 1'b0;$/;" r module:axi_dacfifo_wr +axi_mem_rvalid_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire axi_mem_rvalid_s;$/;" n module:axi_dacfifo_wr +axi_mem_waddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0;$/;" r module:axi_dacfifo_rd +axi_mem_waddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0;$/;" r module:axi_dacfifo_wr +axi_mem_waddr_b2g_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_b2g_s;$/;" n module:axi_dacfifo_rd +axi_mem_waddr_g adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_g = 'd0;$/;" r module:axi_dacfifo_rd +axi_mem_waddr_m1 adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m1 = 'd0;$/;" r module:axi_dacfifo_wr +axi_mem_waddr_m2 adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m2 = 'd0;$/;" r module:axi_dacfifo_wr +axi_mem_waddr_m2_g2b_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m2_g2b_s;$/;" n module:axi_dacfifo_wr +axi_mem_waddr_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s;$/;" n module:axi_dacfifo_rd +axi_mem_waddr_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s;$/;" n module:axi_dacfifo_wr +axi_partial_burst_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire axi_partial_burst_s;$/;" n module:axi_dacfifo_wr +axi_raddr adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 7:0] axi_raddr = 'd0;$/;" r module:axi_adcfifo_wr +axi_raddr_rel adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [DMA_ADDRESS_WIDTH-1:0] axi_raddr_rel = 'd0;$/;" r module:axi_adcfifo_dma +axi_raddr_rel_t_m adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [ 2:0] axi_raddr_rel_t_m = 'd0;$/;" r module:axi_adcfifo_dma +axi_raddr_rel_t_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ wire axi_raddr_rel_t_s;$/;" n module:axi_adcfifo_dma +axi_rd adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ reg axi_rd = 'd0;$/;" r module:axi_adcfifo_rd +axi_rd adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg axi_rd = 'd0;$/;" r module:axi_adcfifo_wr +axi_rd_active adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ reg axi_rd_active = 'd0;$/;" r module:axi_adcfifo_rd +axi_rd_addr adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input [ 31:0] axi_rd_addr,$/;" p module:axi_adcfifo_rd +axi_rd_addr adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output reg [ 31:0] axi_rd_addr,$/;" p module:axi_adcfifo_wr +axi_rd_addr_h adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ reg [ 31:0] axi_rd_addr_h = 'd0;$/;" r module:axi_adcfifo_rd +axi_rd_addr_s adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ wire [ 31:0] axi_rd_addr_s;$/;" n module:axi_adcfifo +axi_rd_d adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg axi_rd_d = 'd0;$/;" r module:axi_adcfifo_wr +axi_rd_req adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input axi_rd_req,$/;" p module:axi_adcfifo_rd +axi_rd_req adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output reg axi_rd_req,$/;" p module:axi_adcfifo_wr +axi_rd_req_s adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ wire axi_rd_req_s;$/;" n module:axi_adcfifo +axi_rd_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ wire axi_rd_s;$/;" n module:axi_adcfifo_wr +axi_rdata adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input [AXI_DATA_WIDTH-1:0] axi_rdata,$/;" p module:axi_adcfifo +axi_rdata adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input [AXI_DATA_WIDTH-1:0] axi_rdata,$/;" p module:axi_adcfifo_rd +axi_rdata adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input [(AXI_DATA_WIDTH-1):0] axi_rdata,$/;" p module:axi_dacfifo +axi_rdata adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input [(AXI_DATA_WIDTH-1):0] axi_rdata,$/;" p module:axi_dacfifo_rd +axi_rdata_d adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [AXI_DATA_WIDTH-1:0] axi_rdata_d = 'd0;$/;" r module:axi_adcfifo_wr +axi_rdata_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ wire [AXI_DATA_WIDTH-1:0] axi_rdata_s;$/;" n module:axi_adcfifo_wr +axi_read_slave adi_library/axi_dmac/tb/axi_read_slave.v /^module axi_read_slave #($/;" m +axi_read_state adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [ 4:0] axi_read_state = 5'b0;$/;" r module:axi_dacfifo_rd +axi_ready_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ wire axi_ready_s;$/;" n module:axi_adcfifo_rd +axi_register_slice adi_library/axi_dmac/axi_register_slice.v /^module axi_register_slice #($/;" m +axi_rel_toggle_m adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 2:0] axi_rel_toggle_m = 'd0;$/;" r module:axi_adcfifo_wr +axi_rel_toggle_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ wire axi_rel_toggle_s;$/;" n module:axi_adcfifo_wr +axi_rel_waddr adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 7:0] axi_rel_waddr = 'd0;$/;" r module:axi_adcfifo_wr +axi_req_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ wire axi_req_s;$/;" n module:axi_adcfifo_wr +axi_rerror adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output reg axi_rerror,$/;" p module:axi_adcfifo_rd +axi_rerror adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output reg axi_rerror,$/;" p module:axi_dacfifo_rd +axi_reset adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg axi_reset = 'd0;$/;" r module:axi_adcfifo_wr +axi_reset_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire axi_reset_s;$/;" n module:axi_dacfifo_wr +axi_resetn adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input axi_resetn,$/;" p module:axi_adcfifo +axi_resetn adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input axi_resetn,$/;" p module:axi_adcfifo_rd +axi_resetn adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input axi_resetn,$/;" p module:axi_adcfifo_wr +axi_resetn adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input axi_resetn,$/;" p module:axi_dacfifo +axi_resetn adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input axi_resetn,$/;" p module:axi_dacfifo_rd +axi_resetn adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input axi_resetn,$/;" p module:axi_dacfifo_wr +axi_rid adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input [ 3:0] axi_rid,$/;" p module:axi_adcfifo +axi_rid adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input [ 3:0] axi_rid,$/;" p module:axi_adcfifo_rd +axi_rid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input [ 3:0] axi_rid,$/;" p module:axi_dacfifo +axi_rid adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input [ 3:0] axi_rid,$/;" p module:axi_dacfifo_rd +axi_rlast adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input axi_rlast,$/;" p module:axi_adcfifo +axi_rlast adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input axi_rlast,$/;" p module:axi_adcfifo_rd +axi_rlast adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg axi_rlast = 'd0;$/;" r module:axi_adcfifo_wr +axi_rlast adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input axi_rlast,$/;" p module:axi_dacfifo +axi_rlast adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input axi_rlast,$/;" p module:axi_dacfifo_rd +axi_rlast_d adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg axi_rlast_d = 'd0;$/;" r module:axi_adcfifo_wr +axi_rlast_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ wire axi_rlast_s;$/;" n module:axi_adcfifo_wr +axi_rready adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output axi_rready);$/;" p module:axi_adcfifo +axi_rready adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ output reg axi_rready,$/;" p module:axi_adcfifo_rd +axi_rready adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output axi_rready);$/;" p module:axi_dacfifo +axi_rready adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output reg axi_rready,$/;" p module:axi_dacfifo_rd +axi_rresp adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input [ 1:0] axi_rresp,$/;" p module:axi_adcfifo +axi_rresp adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input [ 1:0] axi_rresp,$/;" p module:axi_adcfifo_rd +axi_rresp adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input [ 1:0] axi_rresp,$/;" p module:axi_dacfifo +axi_rresp adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input [ 1:0] axi_rresp,$/;" p module:axi_dacfifo_rd +axi_ruser adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input [ 3:0] axi_ruser,$/;" p module:axi_adcfifo +axi_ruser adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input [ 3:0] axi_ruser,$/;" p module:axi_adcfifo_rd +axi_rvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input axi_rvalid,$/;" p module:axi_adcfifo +axi_rvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input axi_rvalid,$/;" p module:axi_adcfifo_rd +axi_rvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input axi_rvalid,$/;" p module:axi_dacfifo +axi_rvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input axi_rvalid,$/;" p module:axi_dacfifo_rd +axi_slave adi_library/axi_dmac/tb/axi_slave.v /^module axi_slave #($/;" m +axi_spi_engine adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^module axi_spi_engine #($/;" m +axi_spi_engine_check_watermark adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ `define axi_spi_engine_check_watermark(x, n) \\$/;" d module:axi_spi_engine +axi_waddr adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr = 'd0;$/;" r module:axi_adcfifo_dma +axi_waddr adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 7:0] axi_waddr = 'd0;$/;" r module:axi_adcfifo_wr +axi_waddr_m1 adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 7:0] axi_waddr_m1 = 'd0;$/;" r module:axi_adcfifo_wr +axi_waddr_m2 adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 7:0] axi_waddr_m2 = 'd0;$/;" r module:axi_adcfifo_wr +axi_waddr_ready_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire axi_waddr_ready_s;$/;" n module:axi_dacfifo_wr +axi_waddr_rel adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr_rel = 'd0;$/;" r module:axi_adcfifo_dma +axi_waddr_rel_count adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [ 2:0] axi_waddr_rel_count = 'd0;$/;" r module:axi_adcfifo_dma +axi_waddr_rel_t adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg axi_waddr_rel_t = 'd0;$/;" r module:axi_adcfifo_dma +axi_waddr_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ wire [DMA_ADDRESS_WIDTH-1:0] axi_waddr_s;$/;" n module:axi_adcfifo_dma +axi_wdata adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [AXI_DATA_WIDTH-1:0] axi_wdata,$/;" p module:axi_adcfifo +axi_wdata adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [AXI_DATA_WIDTH-1:0] axi_wdata,$/;" p module:axi_adcfifo_wr +axi_wdata adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [(AXI_DATA_WIDTH-1):0] axi_wdata,$/;" p module:axi_dacfifo +axi_wdata adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output [(AXI_DATA_WIDTH-1):0] axi_wdata,$/;" p module:axi_dacfifo_wr +axi_werror adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output reg axi_werror);$/;" p module:axi_adcfifo_wr +axi_werror adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output reg axi_werror);$/;" p module:axi_dacfifo_wr +axi_wlast adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output axi_wlast,$/;" p module:axi_adcfifo +axi_wlast adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output axi_wlast,$/;" p module:axi_adcfifo_wr +axi_wlast adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output axi_wlast,$/;" p module:axi_dacfifo +axi_wlast adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output axi_wlast,$/;" p module:axi_dacfifo_wr +axi_wready adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input axi_wready,$/;" p module:axi_adcfifo +axi_wready adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input axi_wready,$/;" p module:axi_adcfifo_wr +axi_wready adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input axi_wready,$/;" p module:axi_dacfifo +axi_wready adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input axi_wready,$/;" p module:axi_dacfifo_wr +axi_wready_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ wire axi_wready_s;$/;" n module:axi_adcfifo_wr +axi_wready_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire axi_wready_s;$/;" n module:axi_dacfifo_wr +axi_write_slave adi_library/axi_dmac/tb/axi_write_slave.v /^module axi_write_slave #($/;" m +axi_writer_state adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ (* dont_touch = "true" *)reg [ 8:0] axi_writer_state = 9'b0;$/;" r module:axi_dacfifo_wr +axi_wstrb adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [(AXI_DATA_WIDTH\/8)-1:0] axi_wstrb,$/;" p module:axi_adcfifo +axi_wstrb adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [AXI_BYTE_WIDTH-1:0] axi_wstrb,$/;" p module:axi_adcfifo_wr +axi_wstrb adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output [(AXI_DATA_WIDTH\/8-1):0] axi_wstrb,$/;" p module:axi_dacfifo +axi_wstrb adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output [((AXI_DATA_WIDTH\/8)-1):0] axi_wstrb,$/;" p module:axi_dacfifo_wr +axi_wuser adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 3:0] axi_wuser,$/;" p module:axi_adcfifo +axi_wuser adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output [ 3:0] axi_wuser,$/;" p module:axi_adcfifo_wr +axi_wvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output axi_wvalid,$/;" p module:axi_adcfifo +axi_wvalid adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ output axi_wvalid,$/;" p module:axi_adcfifo_wr +axi_wvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output axi_wvalid,$/;" p module:axi_dacfifo +axi_wvalid adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output axi_wvalid,$/;" p module:axi_dacfifo_wr +axi_wvalid_counter adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [ 7:0] axi_wvalid_counter = 8'b0;$/;" r module:axi_dacfifo_wr +axi_xcvrlb adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^module axi_xcvrlb #($/;" m +axi_xcvrlb_1 adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^module axi_xcvrlb_1 #($/;" m +axi_xfer_enable adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ reg axi_xfer_enable = 'd0;$/;" r module:axi_adcfifo_rd +axi_xfer_init adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ reg axi_xfer_init = 'd0;$/;" r module:axi_adcfifo_rd +axi_xfer_init adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg axi_xfer_init = 'd0;$/;" r module:axi_adcfifo_wr +axi_xfer_out adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output reg axi_xfer_out,$/;" p module:axi_dacfifo_wr +axi_xfer_pburst_offset adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [ 3:0] axi_xfer_pburst_offset = 4'b1111;$/;" r module:axi_dacfifo_wr +axi_xfer_posedge adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg axi_xfer_posedge = 1'b0;$/;" r module:axi_dacfifo_wr +axi_xfer_req adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input axi_xfer_req,$/;" p module:axi_dacfifo_rd +axi_xfer_req_m adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ reg [ 2:0] axi_xfer_req_m = 'd0;$/;" r module:axi_adcfifo_rd +axi_xfer_req_m adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [ 2:0] axi_xfer_req_m = 'd0;$/;" r module:axi_adcfifo_wr +axi_xfer_req_m adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [ 2:0] axi_xfer_req_m = 3'b0;$/;" r module:axi_dacfifo_wr +axi_xfer_req_s adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ wire axi_xfer_req_s;$/;" n module:axi_dacfifo +axi_xfer_status adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v /^ input [ 3:0] axi_xfer_status);$/;" p module:axi_adcfifo_adc +axi_xfer_status adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ input [ 3:0] axi_xfer_status,$/;" p module:axi_adcfifo_dma +axi_xfer_status_s adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ wire [ 3:0] axi_xfer_status_s;$/;" n module:axi_adcfifo +axi_xlast adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg axi_xlast;$/;" r module:axi_dacfifo_wr +axi_xlast_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire axi_xlast_s;$/;" n module:axi_dacfifo_wr +b adi_library/axi_dmac/request_arb.v /^ input [ID_WIDTH-1:0] b;$/;" p function:dmac_request_arb.compare_id +b adi_library/common/ad_b2g.v /^ input [DATA_WIDTH-1:0] b;$/;" p function:ad_b2g.b2g +b adi_library/util_cdc/sync_gray.v /^ input [DATA_WIDTH-1:0] b;$/;" p function:sync_gray.b2g +b adi_library/util_cdc/sync_gray.v /^ reg [DATA_WIDTH-1:0] b;$/;" r function:sync_gray.g2b +b adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input [7:0] b;$/;" p function:axi_adcfifo_wr.b2g +b adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [7:0] b;$/;" r function:axi_adcfifo_wr.g2b +b2g adi_library/common/ad_b2g.v /^ function [DATA_WIDTH-1:0] b2g;$/;" f module:ad_b2g +b2g adi_library/util_cdc/sync_gray.v /^ function [DATA_WIDTH-1:0] b2g;$/;" f module:sync_gray +b2g adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ function [7:0] b2g;$/;" f module:axi_adcfifo_wr +bad_frames hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output [8:0] bad_frames, \/\/译码坏帧计数$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +bad_frames hdl/RecvTop.v /^ wire [8:0] bad_frames;$/;" n module:RecvTop +bad_frames_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [8:0] bad_frames_A; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +bad_frames_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [8:0] bad_frames_B; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +bagcnt hdl/FrameMerge.v /^ reg [8:0] bagcnt = 9'd0;$/;" r module:FrameMerge +bagcount hdl/IQmerge.v /^ reg [8:0] bagcount = 9'd0;$/;" r module:IQmerge +base adi_library/util_pack/util_pack_common/pack_ctrl.v /^ localparam base = i*MUX_ORDER;$/;" c block:pack_ctrl.demux_gen_outer +base adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam base = i * w;$/;" c block:pack_shell.gen_pack.gen_output_buffer.gen_out_data +bb_wave_out_i hdl/Transmitter.v /^ reg [31:0] bb_wave_out_i; \/\/ shape filter result$/;" r module:Transmitter +bb_wave_out_i_interp16 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_i_interp16;$/;" n module:Transmitter +bb_wave_out_i_interp4 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_i_interp4;$/;" n module:Transmitter +bb_wave_out_i_interp8 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_i_interp8;$/;" n module:Transmitter +bb_wave_out_q hdl/Transmitter.v /^ reg [31:0] bb_wave_out_q; \/\/ shape filter result$/;" r module:Transmitter +bb_wave_out_q_interp16 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_q_interp16;$/;" n module:Transmitter +bb_wave_out_q_interp4 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_q_interp4;$/;" n module:Transmitter +bb_wave_out_q_interp8 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_q_interp8;$/;" n module:Transmitter +beat_ack adi_library/axi_dmac/tb/axi_slave.v /^ input beat_ack,$/;" p module:axi_slave +beat_addr adi_library/axi_dmac/tb/axi_read_slave.v /^wire [31:0] beat_addr;$/;" n module:axi_read_slave +beat_addr adi_library/axi_dmac/tb/axi_slave.v /^ output [31:0] beat_addr,$/;" p module:axi_slave +beat_counter adi_library/axi_dmac/data_mover.v /^reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00;$/;" r module:dmac_data_mover +beat_counter adi_library/axi_dmac/tb/axi_slave.v /^reg [7:0] beat_counter = 'h00;$/;" r module:axi_slave +beat_counter_minus_one adi_library/axi_dmac/data_mover.v /^reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter_minus_one = 'h0;$/;" r module:dmac_data_mover +beat_last adi_library/axi_dmac/tb/axi_slave.v /^ output beat_last$/;" p module:axi_slave +beat_last adi_library/axi_dmac/tb/axi_write_slave.v /^wire beat_last;$/;" n module:axi_write_slave +beat_stb adi_library/axi_dmac/tb/axi_slave.v /^ output beat_stb,$/;" p module:axi_slave +bercompare hdl/FrameMerge.v /^ output reg bercompare = 1'b0,$/;" p module:FrameMerge +bercompare hdl/RecvTop.v /^ wire bercompare;$/;" n module:RecvTop +bercount hdl/FrameMerge.v /^ output reg [16:0] bercount = 17'd0,$/;" p module:FrameMerge +bercount hdl/RecvTop.v /^ wire [16:0] bercount;$/;" n module:RecvTop +bercount_max hdl/FrameMerge.v /^ output reg [16:0] bercount_max = 17'd0,$/;" p module:FrameMerge +bercount_max hdl/RecvTop.v /^ wire [16:0] bercount_max;$/;" n module:RecvTop +berstart hdl/FrameMerge.v /^ reg berstart = 1'b0;$/;" r module:FrameMerge +berstart_1d hdl/FrameMerge.v /^ output reg berstart_1d = 1'b0,$/;" p module:FrameMerge +berstart_1d hdl/RecvTop.v /^ wire berstart_1d;$/;" n module:RecvTop +bit_counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];$/;" n module:spi_engine_execution +bl_mem adi_library/axi_dmac/dest_axi_mm.v /^reg [BYTES_PER_BURST_WIDTH+1-1:0] bl_mem [0:2**(ID_WIDTH)-1];$/;" r module:dmac_dest_mm_axi +bl_ready adi_library/axi_dmac/address_generator.v /^ output reg bl_ready,$/;" p module:dmac_address_generator +bl_ready adi_library/axi_dmac/data_mover.v /^ input bl_ready,$/;" p module:dmac_data_mover +bl_ready adi_library/axi_dmac/dest_axi_mm.v /^ output bl_ready,$/;" p module:dmac_dest_mm_axi +bl_ready adi_library/axi_dmac/src_axi_mm.v /^ input bl_ready,$/;" p module:dmac_src_mm_axi +bl_ready adi_library/axi_dmac/src_axi_stream.v /^ input bl_ready,$/;" p module:dmac_src_axi_stream +bl_ready adi_library/axi_dmac/src_fifo_inf.v /^ input bl_ready,$/;" p module:dmac_src_fifo_inf +bl_ready_ag adi_library/axi_dmac/src_axi_mm.v /^wire bl_ready_ag;$/;" n module:dmac_src_mm_axi +bl_valid adi_library/axi_dmac/address_generator.v /^ input bl_valid,$/;" p module:dmac_address_generator +bl_valid adi_library/axi_dmac/data_mover.v /^ output reg bl_valid = 'b0,$/;" p module:dmac_data_mover +bl_valid adi_library/axi_dmac/dest_axi_mm.v /^ input bl_valid,$/;" p module:dmac_dest_mm_axi +bl_valid adi_library/axi_dmac/src_axi_mm.v /^ output bl_valid,$/;" p module:dmac_src_mm_axi +bl_valid adi_library/axi_dmac/src_axi_stream.v /^ output bl_valid,$/;" p module:dmac_src_axi_stream +bl_valid adi_library/axi_dmac/src_fifo_inf.v /^ output bl_valid,$/;" p module:dmac_src_fifo_inf +bl_valid_ag adi_library/axi_dmac/src_axi_mm.v /^wire bl_valid_ag;$/;" n module:dmac_src_mm_axi +block_descr_to_dst adi_library/axi_dmac/data_mover.v /^ output block_descr_to_dst,$/;" p module:dmac_data_mover +block_descr_to_dst adi_library/axi_dmac/request_arb.v /^wire block_descr_to_dst;$/;" n module:dmac_request_arb +block_descr_to_dst adi_library/axi_dmac/src_axi_stream.v /^ output block_descr_to_dst,$/;" p module:dmac_src_axi_stream +bready adi_library/axi_dmac/response_handler.v /^ output bready,$/;" p module:dmac_response_handler +bready adi_library/axi_dmac/tb/axi_write_slave.v /^ input bready,$/;" p module:axi_write_slave +bready adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire bready;$/;" n module:dmac_dma_write_shutdown_tb +bready adi_library/axi_dmac/tb/dma_write_tb.v /^ wire bready;$/;" n module:dmac_dma_write_tb +bresp adi_library/axi_dmac/response_handler.v /^ input [1:0] bresp,$/;" p module:dmac_response_handler +bresp adi_library/axi_dmac/tb/axi_write_slave.v /^ output [1:0] bresp$/;" p module:axi_write_slave +bresp adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire [1:0] bresp;$/;" n module:dmac_dma_write_shutdown_tb +bresp adi_library/axi_dmac/tb/dma_write_tb.v /^ wire [1:0] bresp;$/;" n module:dmac_dma_write_tb +buffer_disable adi_library/xilinx/common/ad_serdes_out.v /^ wire buffer_disable;$/;" n module:ad_serdes_out +bufg_fb_clk_s adi_library/xilinx/common/ad_mmcm_drp.v /^ wire bufg_fb_clk_s;$/;" n module:ad_mmcm_drp +bufmr_rgmii_rxc adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ BUFG bufmr_rgmii_rxc($/;" i module:util_gmii_to_rgmii typeref:module:BUFG +burst adi_library/axi_dmac/address_generator.v /^ output [ 1:0] burst,$/;" p module:dmac_address_generator +burst adi_library/axi_dmac/tb/axi_slave.v /^ input [1:0] burst,$/;" p module:axi_slave +burst_count adi_library/axi_dmac/request_generator.v /^reg [BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00;$/;" r module:dmac_request_generator +burst_len_mem adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg [BYTES_PER_BURST_WIDTH+1-1-DMA_LENGTH_ALIGN:0] burst_len_mem[0:AUX_FIFO_SIZE-1];$/;" r module:axi_dmac_burst_memory +bvalid adi_library/axi_dmac/response_handler.v /^ input bvalid,$/;" p module:dmac_response_handler +bvalid adi_library/axi_dmac/tb/axi_write_slave.v /^ output reg bvalid,$/;" p module:axi_write_slave +bvalid adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire bvalid;$/;" n module:dmac_dma_write_shutdown_tb +bvalid adi_library/axi_dmac/tb/dma_write_tb.v /^ wire bvalid;$/;" n module:dmac_dma_write_tb +bwd_data adi_library/axi_dmac/axi_register_slice.v /^reg [DATA_WIDTH-1:0] bwd_data = 'h00;$/;" r module:axi_register_slice +bwd_data_s adi_library/axi_dmac/axi_register_slice.v /^wire [DATA_WIDTH-1:0] bwd_data_s;$/;" n module:axi_register_slice +bwd_ready adi_library/axi_dmac/axi_register_slice.v /^reg bwd_ready = 1'b1;$/;" r module:axi_register_slice +bwd_ready_s adi_library/axi_dmac/axi_register_slice.v /^wire bwd_ready_s;$/;" n module:axi_register_slice +bwd_valid_s adi_library/axi_dmac/axi_register_slice.v /^wire bwd_valid_s;$/;" n module:axi_register_slice +bypass adi_library/util_dacfifo/util_dacfifo.v /^ input bypass);$/;" p module:util_dacfifo +bypass adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input bypass,$/;" p module:axi_dacfifo +byte_count adi_library/axi_dmac/tb/axi_write_slave.v /^integer byte_count;$/;" r module:axi_write_slave +cache adi_library/axi_dmac/address_generator.v /^ output [ 3:0] cache$/;" p module:dmac_address_generator +cache adi_library/axi_dmac/tb/axi_slave.v /^ input [3:0] cache,$/;" p module:axi_slave +cb adi_library/common/ad_ss_444to422.v /^ reg [ 7:0] cb = 'd0;$/;" r module:ad_ss_444to422 +cb_s adi_library/common/ad_ss_444to422.v /^ wire [ 9:0] cb_s;$/;" n module:ad_ss_444to422 +cdc_hold adi_library/util_cdc/sync_data.v /^reg [NUM_OF_BITS-1:0] cdc_hold;$/;" r module:sync_data +cdc_hold adi_library/util_cdc/sync_event.v /^ reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00;$/;" r module:sync_event +cdc_sync_fifo_ram adi_library/util_axis_fifo/util_axis_fifo.v /^ reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;$/;" r module:util_axis_fifo +cdc_sync_stage0 adi_library/util_cdc/sync_gray.v /^ reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;$/;" r module:sync_gray +cdc_sync_stage1 adi_library/util_cdc/sync_bits.v /^ reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;$/;" r module:sync_bits +cdc_sync_stage1 adi_library/util_cdc/sync_gray.v /^ reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;$/;" r module:sync_gray +cdc_sync_stage2 adi_library/util_cdc/sync_bits.v /^ reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;$/;" r module:sync_bits +cdc_sync_stage2 adi_library/util_cdc/sync_gray.v /^ reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;$/;" r module:sync_gray +ce adi_library/util_cic/cic_comb.v /^ input ce,$/;" p module:cic_comb +ce adi_library/util_cic/cic_int.v /^ input [NUM_STAGES-1:0] ce,$/;" p module:cic_int +ce adi_library/util_pack/util_pack_common/pack_shell.v /^ input ce,$/;" p module:pack_shell +ce adi_library/util_pack/util_upack2/util_upack2_impl.v /^ wire ce;$/;" n module:util_upack2_impl +ce_ctrl adi_library/util_pack/util_pack_common/pack_network.v /^ input ce_ctrl,$/;" p module:pack_network +ce_ctrl adi_library/util_pack/util_pack_common/pack_shell.v /^ wire ce_ctrl;$/;" n module:pack_shell +channel_0 adi_library/util_fir_dec/util_fir_dec.v /^ input [15:0] channel_0,$/;" p module:util_fir_dec +channel_0 adi_library/util_fir_int/util_fir_int.v /^ output [15:0] channel_0,$/;" p module:util_fir_int +channel_1 adi_library/util_fir_dec/util_fir_dec.v /^ input [15:0] channel_1,$/;" p module:util_fir_dec +channel_1 adi_library/util_fir_int/util_fir_int.v /^ output [15:0] channel_1,$/;" p module:util_fir_int +check_all_registers adi_library/axi_dmac/tb/regmap_tb.v /^ task check_all_registers;$/;" t module:dmac_regmap_tb +check_clk_num hdl/CCSDS_LDPC_ENC_R12.v /^ reg [10:0] check_clk_num = 11'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +check_clk_num hdl/Out_Process_R12.v /^ input [10:0] check_clk_num, \/\/校验比特个数$/;" p module:Out_Process_R12 +chu_seq hdl/Transmitter.v /^ wire [31:0] chu_seq;$/;" n module:Transmitter +chu_seq_addr hdl/Transmitter.v /^ reg [ 6:0] chu_seq_addr;$/;" r module:Transmitter +cic_comb adi_library/util_cic/cic_comb.v /^module cic_comb #($/;" m +cic_int adi_library/util_cic/cic_int.v /^module cic_int #($/;" m +clk adi_library/axi_dmac/address_generator.v /^ input clk,$/;" p module:dmac_address_generator +clk adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input clk,$/;" p module:axi_dmac_regmap_request +clk adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input clk,$/;" p module:axi_dmac_reset_manager +clk adi_library/axi_dmac/axi_dmac_resize_dest.v /^ input clk,$/;" p module:axi_dmac_resize_dest +clk adi_library/axi_dmac/axi_dmac_resize_src.v /^ input clk,$/;" p module:axi_dmac_resize_src +clk adi_library/axi_dmac/axi_register_slice.v /^ input clk,$/;" p module:axi_register_slice +clk adi_library/axi_dmac/data_mover.v /^ input clk,$/;" p module:dmac_data_mover +clk adi_library/axi_dmac/dest_fifo_inf.v /^ input clk,$/;" p module:dmac_dest_fifo_inf +clk adi_library/axi_dmac/request_generator.v /^ input clk,$/;" p module:dmac_request_generator +clk adi_library/axi_dmac/response_generator.v /^ input clk,$/;" p module:dmac_response_generator +clk adi_library/axi_dmac/response_handler.v /^ input clk,$/;" p module:dmac_response_handler +clk adi_library/axi_dmac/splitter.v /^ input clk,$/;" p module:splitter +clk adi_library/axi_dmac/src_fifo_inf.v /^ input clk,$/;" p module:dmac_src_fifo_inf +clk adi_library/axi_dmac/tb/axi_read_slave.v /^ input clk,$/;" p module:axi_read_slave +clk adi_library/axi_dmac/tb/axi_slave.v /^ input clk,$/;" p module:axi_slave +clk adi_library/axi_dmac/tb/axi_write_slave.v /^ input clk,$/;" p module:axi_write_slave +clk adi_library/axi_dmac/tb/tb_base.v /^ reg clk = 1'b0;$/;" r +clk adi_library/common/ad_addsub.v /^ input clk,$/;" p module:ad_addsub +clk adi_library/common/ad_axis_inf_rx.v /^ input clk,$/;" p module:ad_axis_inf_rx +clk adi_library/common/ad_csc.v /^ input clk,$/;" p module:ad_csc +clk adi_library/common/ad_csc_CrYCb2RGB.v /^ input clk,$/;" p module:ad_csc_CrYCb2RGB +clk adi_library/common/ad_csc_RGB2CrYCb.v /^ input clk,$/;" p module:ad_csc_RGB2CrYCb +clk adi_library/common/ad_datafmt.v /^ input clk,$/;" p module:ad_datafmt +clk adi_library/common/ad_dds.v /^ input clk,$/;" p module:ad_dds +clk adi_library/common/ad_dds_1.v /^ input clk,$/;" p module:ad_dds_1 +clk adi_library/common/ad_dds_2.v /^ input clk,$/;" p module:ad_dds_2 +clk adi_library/common/ad_dds_cordic_pipe.v /^ input clk,$/;" p module:ad_dds_cordic_pipe +clk adi_library/common/ad_dds_sine.v /^ input clk,$/;" p module:ad_dds_sine +clk adi_library/common/ad_dds_sine_cordic.v /^ input clk,$/;" p module:ad_dds_sine_cordic +clk adi_library/common/ad_edge_detect.v /^ input clk,$/;" p module:ad_edge_detect +clk adi_library/common/ad_iqcor.v /^ input clk,$/;" p module:ad_iqcor +clk adi_library/common/ad_pngen.v /^ input clk,$/;" p module:ad_pngen +clk adi_library/common/ad_pps_receiver.v /^ input clk,$/;" p module:ad_pps_receiver +clk adi_library/common/ad_rst.v /^ input clk,$/;" p module:ad_rst +clk adi_library/common/ad_ss_422to444.v /^ input clk,$/;" p module:ad_ss_422to444 +clk adi_library/common/ad_ss_444to422.v /^ input clk,$/;" p module:ad_ss_444to422 +clk adi_library/common/ad_tdd_control.v /^ input clk,$/;" p module:ad_tdd_control +clk adi_library/common/up_tdd_cntrl.v /^ input clk,$/;" p module:up_tdd_cntrl +clk adi_library/common/util_axis_upscale.v /^ input clk,$/;" p module:util_axis_upscale +clk adi_library/common/util_dec256sinc24b.v /^ input clk, \/* used to clk filter *\/$/;" p module:util_dec256sinc24b +clk adi_library/common/util_delay.v /^ input clk,$/;" p module:util_delay +clk adi_library/common/util_pulse_gen.v /^ input clk,$/;" p module:util_pulse_gen +clk adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire clk;$/;" n module:axi_spi_engine +clk adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input clk,$/;" p module:spi_engine_execution +clk adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input clk,$/;" p module:spi_engine_interconnect +clk adi_library/util_axis_fifo/address_sync.v /^ input clk,$/;" p module:fifo_address_sync +clk adi_library/util_axis_resize/util_axis_resize.v /^ input clk,$/;" p module:util_axis_resize +clk adi_library/util_cic/cic_comb.v /^ input clk,$/;" p module:cic_comb +clk adi_library/util_cic/cic_int.v /^ input clk,$/;" p module:cic_int +clk adi_library/util_extract/util_extract.v /^ input clk,$/;" p module:util_extract +clk adi_library/util_pack/tb/tb_base.v /^ reg clk = 1'b1;$/;" r +clk adi_library/util_pack/util_cpack2/util_cpack2.v /^ input clk,$/;" p module:util_cpack2 +clk adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ input clk,$/;" p module:util_cpack2_impl +clk adi_library/util_pack/util_pack_common/pack_network.v /^ input clk,$/;" p module:pack_network +clk adi_library/util_pack/util_pack_common/pack_shell.v /^ input clk,$/;" p module:pack_shell +clk adi_library/util_pack/util_upack2/util_upack2.v /^ input clk,$/;" p module:util_upack2 +clk adi_library/util_pack/util_upack2/util_upack2_impl.v /^ input clk,$/;" p module:util_upack2_impl +clk adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ input clk,$/;" p module:util_sigma_delta_spi +clk adi_library/util_tdd_sync/util_tdd_sync.v /^ input clk,$/;" p module:util_tdd_sync +clk adi_library/util_var_fifo/util_var_fifo.v /^ input clk,$/;" p module:util_var_fifo +clk adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ input clk,$/;" p module:axi_dacfifo_address_buffer +clk adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire clk;$/;" n module:axi_xcvrlb_1 +clk adi_library/xilinx/common/ad_data_clk.v /^ output clk);$/;" p module:ad_data_clk +clk adi_library/xilinx/common/ad_dcfilter.v /^ input clk,$/;" p module:ad_dcfilter +clk adi_library/xilinx/common/ad_mmcm_drp.v /^ input clk,$/;" p module:ad_mmcm_drp +clk adi_library/xilinx/common/ad_mul.v /^ input clk,$/;" p module:ad_mul +clk adi_library/xilinx/common/ad_serdes_clk.v /^ output clk,$/;" p module:ad_serdes_clk +clk adi_library/xilinx/common/ad_serdes_in.v /^ input clk,$/;" p module:ad_serdes_in +clk adi_library/xilinx/common/ad_serdes_out.v /^ input clk,$/;" p module:ad_serdes_out +clk adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ input clk,$/;" p module:util_clkdiv +clk hdl/ApproxAbs_18bit.v /^ input clk,$/;" p module:ApproxAbs_18bit +clk hdl/ApproxAbs_v2.v /^ input clk,$/;" p module:ApproxAbs_v2 +clk hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ input clk, \/\/工作时钟,100MHz$/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +clk hdl/CCSDS_LDPC_ENC_R12.v /^ input clk,$/;" p module:CCSDS_LDPC_ENC_R12 +clk hdl/Chn_Estimate.v /^ input clk,$/;" p module:Chn_Estimate +clk hdl/DAGC_v2.v /^ input clk,$/;" p module:DAGC_v2 +clk hdl/DDS_compensate.v /^ input clk;$/;" p module:DDS_compensate +clk hdl/FrameMerge.v /^ input clk,$/;" p module:FrameMerge +clk hdl/IQmerge.v /^ input clk,$/;" p module:IQmerge +clk hdl/Interp_half.v /^ input clk,$/;" p module:Interp_half +clk hdl/Interp_quarter.v /^ input clk,$/;" p module:Interp_quarter +clk hdl/Interpolation.v /^ input clk,$/;" p module:Interpolation +clk hdl/MF_Top.v /^ input clk,$/;" p module:MF_Top +clk hdl/MagnitudeEstimator.v /^ input clk,$/;" p module:MagnitudeEstimator +clk hdl/Noise_Estimate.v /^ input clk,$/;" p module:Noise_Estimate +clk hdl/Out_Process_R12.v /^ input clk,$/;" p module:Out_Process_R12 +clk hdl/PAPR.v /^ input clk, $/;" p module:PAPR +clk hdl/Receiver.v /^ input clk,$/;" p module:Receiver +clk hdl/RecvTop.v /^ input clk,$/;" p module:RecvTop +clk hdl/SCFDE_recv_FrameSync.v /^ input clk,$/;" p module:SCFDE_recv_FrameSync +clk hdl/SC_FDE_TOP.v /^ input clk,$/;" p module:SC_FDE_TOP +clk hdl/TSync_Abs_new16.v /^ input clk,$/;" p module:TSync_Abs_new16 +clk hdl/TSync_Abs_new4.v /^ input clk,$/;" p module:TSync_Abs_new4 +clk hdl/TimeSync_top.v /^ input clk,$/;" p module:TimeSync_top +clk hdl/Transmitter.v /^ input wire clk,$/;" p module:Transmitter +clk hdl/ad9361_mgc_pin_ctrl.v /^ input clk,$/;" p module:ad9361_mgc_pin_ctrl +clk hdl/add_prefix.v /^ input clk,$/;" p module:add_prefix +clk hdl/data_equalizer.v /^ input clk,$/;" p module:data_equalizer +clk hdl/data_ow.v /^ input clk,$/;" p module:data_ow +clk hdl/enc_control.v /^ input clk,$/;" p module:enc_control +clk hdl/frame_sync.v /^ input clk,$/;" p module:frame_sync +clk hdl/freqestm.v /^ input clk,$/;" p module:freqestm +clk hdl/phase_adjust.v /^ input clk,$/;" p module:phase_adjust +clk hdl/phy_control.v /^ input clk, \/\/ can be floating if ASYNC_CLK == 0$/;" p module:phy_control +clk hdl/power_measure.v /^ input clk,$/;" p module:power_measure +clk hdl/shift_reg.v /^ input clk,$/;" p module:shift_reg +clk hdl/tdma.v /^ input clk,$/;" p module:tdma +clk hdl/trunc_25to12_2dly.v /^ input clk;$/;" p module:trunc_25to12_2dly +clk hdl/width_convert.v /^ input clk,$/;" p module:width_convert +clk sim/TB_sys.v /^ reg clk;$/;" r module:TB_sys +clk sim/tb_Receiver.v /^ reg clk;$/;" r module:tb_Receiver +clk sim/tb_Transmitter.v /^ reg clk = 1;$/;" r module:tb_Transmitter +clk sim/tb_add_prefix.v /^ reg clk = 0;$/;" r module:tb_add_prefix +clk sim/tb_enc_control.v /^ reg clk = 1;$/;" r module:tb_enc_control +clk sim/tb_tdma.v /^ reg clk = 1;$/;" r module:tb_tdma +clk sim/tb_width_convert.v /^ reg clk = 1;$/;" r module:tb_width_convert +clk2 adi_library/xilinx/common/ad_mmcm_drp.v /^ input clk2,$/;" p module:ad_mmcm_drp +clk2 hdl/FrameMerge.v /^ input clk2,$/;" p module:FrameMerge +clk2 hdl/IQmerge.v /^ input clk2,$/;" p module:IQmerge +clk2 hdl/RecvTop.v /^ input clk2,$/;" p module:RecvTop +clk_100msps adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ wire clk_100msps;$/;" n module:util_gmii_to_rgmii +clk_125m adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input clk_125m,$/;" p module:util_gmii_to_rgmii +clk_1x hdl/system_top.v /^ wire clk_1x;$/;" n module:system_top +clk_1x sim/TB_sys.v /^ wire clk_1x;$/;" n module:TB_sys +clk_1x sim/tb_tx_with_enc.v /^ wire clk_1x;$/;" n module:tb_tx_with_enc +clk_20m adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input clk_20m,$/;" p module:util_gmii_to_rgmii +clk_25m adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input clk_25m,$/;" p module:util_gmii_to_rgmii +clk_2_5_divide adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) clk_2_5_divide ($/;" i module:util_gmii_to_rgmii typeref:module:BUFR +clk_2_5m adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ wire clk_2_5m;$/;" n module:util_gmii_to_rgmii +clk_2x hdl/Receiver.v /^ input clk_2x,$/;" p module:Receiver +clk_2x hdl/system_top.v /^ wire clk_2x;$/;" n module:system_top +clk_2x sim/TB_sys.v /^ wire clk_2x;$/;" n module:TB_sys +clk_2x sim/tb_Receiver.v /^ reg clk_2x;$/;" r module:tb_Receiver +clk_2x sim/tb_tx_with_enc.v /^ wire clk_2x;$/;" n module:tb_tx_with_enc +clk_4x hdl/Receiver.v /^ input clk_4x,$/;" p module:Receiver +clk_4x hdl/system_top.v /^ wire clk_4x;$/;" n module:system_top +clk_4x sim/TB_sys.v /^ wire clk_4x;$/;" n module:TB_sys +clk_4x sim/tb_Receiver.v /^ reg clk_4x;$/;" r module:tb_Receiver +clk_4x sim/tb_tx_with_enc.v /^ wire clk_4x;$/;" n module:tb_tx_with_enc +clk_60M_mac hdl/RecvTop.v /^ input clk_60M_mac,$/;" p module:RecvTop +clk_a adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg clk_a = 1'b0;$/;" r module:dmac_reset_manager_tb +clk_b adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg clk_b = 1'b0;$/;" r module:dmac_reset_manager_tb +clk_c adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg clk_c = 1'b0;$/;" r module:dmac_reset_manager_tb +clk_crystal hdl/system_top.v /^ input clk_crystal,$/;" p module:system_top +clk_crystal sim/tb_tx_with_enc.v /^ reg clk_crystal = 0; \/\/ 25MHz$/;" r module:tb_tx_with_enc +clk_data_src hdl/Transmitter.v /^ output wire clk_data_src,$/;" p module:Transmitter +clk_div adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [7:0] clk_div = DEFAULT_CLK_DIV;$/;" r module:spi_engine_execution +clk_div sim/tb_enc_control.v /^ wire clk_div;$/;" n module:tb_enc_control +clk_div_counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [7:0] clk_div_counter = 'h00;$/;" r module:spi_engine_execution +clk_div_counter_next adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [7:0] clk_div_counter_next = 'h00;$/;" r module:spi_engine_execution +clk_div_last adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg clk_div_last;$/;" r module:spi_engine_execution +clk_div_sel_0_s adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ wire clk_div_sel_0_s;$/;" n module:util_clkdiv +clk_div_sel_1_s adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ wire clk_div_sel_1_s;$/;" n module:util_clkdiv +clk_divide_sel_0 adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ ) clk_divide_sel_0 ($/;" i module:util_clkdiv typeref:module:BUFGCE_DIV +clk_divide_sel_0 adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ ) clk_divide_sel_0 ($/;" i module:util_clkdiv typeref:module:BUFR +clk_divide_sel_1 adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ ) clk_divide_sel_1 ($/;" i module:util_clkdiv typeref:module:BUFGCE_DIV +clk_divide_sel_1 adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ ) clk_divide_sel_1 ($/;" i module:util_clkdiv typeref:module:BUFR +clk_en adi_library/common/ad_pngen.v /^ input clk_en,$/;" p module:ad_pngen +clk_ibuf_s adi_library/xilinx/common/ad_data_clk.v /^ wire clk_ibuf_s;$/;" n module:ad_data_clk +clk_in_n adi_library/xilinx/common/ad_data_clk.v /^ input clk_in_n,$/;" p module:ad_data_clk +clk_in_n adi_library/xilinx/common/ad_serdes_clk.v /^ input clk_in_n,$/;" p module:ad_serdes_clk +clk_in_p adi_library/xilinx/common/ad_data_clk.v /^ input clk_in_p,$/;" p module:ad_data_clk +clk_in_p adi_library/xilinx/common/ad_serdes_clk.v /^ input clk_in_p,$/;" p module:ad_serdes_clk +clk_in_s adi_library/xilinx/common/ad_serdes_clk.v /^ wire clk_in_s;$/;" n module:ad_serdes_clk +clk_net_bit hdl/FrameMerge.v /^ reg [9:0] clk_net_bit;$/;" r module:FrameMerge +clk_net_byte hdl/FrameMerge.v /^ reg [7:0] clk_net_byte;$/;" r module:FrameMerge +clk_out adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ output clk_out$/;" p module:util_clkdiv +clk_poweron hdl/system_top.v /^ wire clk_poweron;$/;" n module:system_top +clk_poweron sim/TB_sys.v /^ wire clk_poweron;$/;" n module:TB_sys +clk_poweron sim/tb_tx_with_enc.v /^ wire clk_poweron;$/;" n module:tb_tx_with_enc +clk_sel adi_library/common/up_clkgen.v /^ output clk_sel,$/;" p module:up_clkgen +clk_sel adi_library/xilinx/common/ad_mmcm_drp.v /^ input clk_sel,$/;" p module:ad_mmcm_drp +clk_sel adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ input clk_sel,$/;" p module:util_clkdiv +clk_tx sim/tb_Transmitter.v /^ reg clk_tx = 1;$/;" r module:tb_Transmitter +clk_tx sim/tb_tdma.v /^ reg clk_tx = 1;$/;" r module:tb_tdma +clk_tx_data_src hdl/system_top.v /^ wire clk_tx_data_src;$/;" n module:system_top +clk_tx_data_src sim/TB_sys.v /^ wire clk_tx_data_src;$/;" n module:TB_sys +clk_tx_data_src sim/tb_tx_with_enc.v /^ wire clk_tx_data_src;$/;" n module:tb_tx_with_enc +clk_tx_mux0 adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) clk_tx_mux0 ($/;" i module:util_gmii_to_rgmii typeref:module:BUFGMUX +clk_tx_mux1 adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) clk_tx_mux1 ($/;" i module:util_gmii_to_rgmii typeref:module:BUFGMUX +clka adi_library/common/ad_mem.v /^ input clka,$/;" p module:ad_mem +clka adi_library/common/ad_mem_asym.v /^ input clka,$/;" p module:ad_mem_asym +clkb adi_library/common/ad_mem.v /^ input clkb,$/;" p module:ad_mem +clkb adi_library/common/ad_mem_asym.v /^ input clkb,$/;" p module:ad_mem_asym +clog2 adi_library/common/ad_mem_asym.v /^ function integer clog2;$/;" f module:ad_mem_asym +clog2 adi_library/util_axis_resize/util_axis_resize.v /^function integer clog2;$/;" f module:util_axis_resize +cmd adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input [15:0] cmd,$/;" p module:spi_engine_execution +cmd adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output [15:0] cmd,$/;" p module:spi_engine_offload +cmd_d1 adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [15:0] cmd_d1;$/;" r module:spi_engine_execution +cmd_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output [15:0] cmd_data,$/;" p module:axi_spi_engine +cmd_fifo_almost_empty adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire cmd_fifo_almost_empty;$/;" n module:axi_spi_engine +cmd_fifo_in_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [15:0] cmd_fifo_in_data;$/;" n module:axi_spi_engine +cmd_fifo_in_ready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire cmd_fifo_in_ready;$/;" n module:axi_spi_engine +cmd_fifo_in_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire cmd_fifo_in_valid;$/;" n module:axi_spi_engine +cmd_fifo_room adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;$/;" n module:axi_spi_engine +cmd_int_s adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^wire [15:0] cmd_int_s;$/;" n module:spi_engine_offload +cmd_mem adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];$/;" r module:spi_engine_offload +cmd_ready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input cmd_ready,$/;" p module:axi_spi_engine +cmd_ready adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output cmd_ready,$/;" p module:spi_engine_execution +cmd_ready adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input cmd_ready,$/;" p module:spi_engine_offload +cmd_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output cmd_valid,$/;" p module:axi_spi_engine +cmd_valid adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input cmd_valid,$/;" p module:spi_engine_execution +cmd_valid adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output cmd_valid,$/;" p module:spi_engine_offload +cnt hdl/PAPR.v /^ reg [ 5:0] cnt;$/;" r module:PAPR +cnt hdl/TSync_Abs_new16.v /^ output reg [1:0] cnt = 2'd0, \/\/12.5$/;" p module:TSync_Abs_new16 +cnt hdl/TSync_Abs_new4.v /^ output reg [1:0] cnt = 2'd0, \/\/12.5$/;" p module:TSync_Abs_new4 +cnt hdl/tdma.v /^ reg [15:0] cnt;$/;" r module:tdma +cnt hdl/width_convert.v /^ reg [$clog2(CNT_MAX) - 1 : 0] cnt;$/;" r module:width_convert +cnt sim/TB_sys.v /^ reg [31:0] cnt;$/;" r module:TB_sys +cnt_1024 hdl/TSync_Abs_new16.v /^ reg [9:0] cnt_1024 = 10'd0;$/;" r module:TSync_Abs_new16 +cnt_1024 hdl/TSync_Abs_new4.v /^ reg [9:0] cnt_1024 = 10'd0;$/;" r module:TSync_Abs_new4 +cnt_10data hdl/data_ow.v /^ reg [3:0] cnt_10data = 1'd0;$/;" r module:data_ow +cnt_128 hdl/TSync_Abs_new16.v /^ reg [6:0] cnt_128 = 7'd0;$/;" r module:TSync_Abs_new16 +cnt_128 hdl/TSync_Abs_new4.v /^ reg [6:0] cnt_128 = 7'd0;$/;" r module:TSync_Abs_new4 +cnt_16 hdl/TimeSync_top.v /^ wire [1:0] cnt_16;$/;" n module:TimeSync_top +cnt_256 hdl/TSync_Abs_new16.v /^ reg [7:0] cnt_256 = 8'd0;$/;" r module:TSync_Abs_new16 +cnt_256 hdl/TSync_Abs_new4.v /^ reg [7:0] cnt_256 = 8'd0;$/;" r module:TSync_Abs_new4 +cnt_256 hdl/data_equalizer.v /^ reg [7:0] cnt_256 = 8'd0;$/;" r module:data_equalizer +cnt_256 hdl/data_ow.v /^ reg [7:0] cnt_256 = 8'd0;$/;" r module:data_ow +cnt_256pilot hdl/data_ow.v /^ reg [7:0] cnt_256pilot = 8'd0;$/;" r module:data_ow +cnt_4 hdl/TSync_Abs_new16.v /^ reg [1:0] cnt_4 =2'd0;$/;" r module:TSync_Abs_new16 +cnt_4 hdl/TSync_Abs_new4.v /^ reg [1:0] cnt_4 =2'd0;$/;" r module:TSync_Abs_new4 +cnt_4 hdl/TimeSync_top.v /^ wire [1:0] cnt_4;$/;" n module:TimeSync_top +cnt_4096_3 hdl/DAGC_v2.v /^ reg [11:0] cnt_4096_3 = 12'd0;$/;" r module:DAGC_v2 +cnt_422_net hdl/FrameMerge.v /^ reg [7:0] cnt_422_net;$/;" r module:FrameMerge +cnt_422_wait hdl/FrameMerge.v /^ reg [4:0] cnt_422_wait;$/;" r module:FrameMerge +cnt_42block hdl/data_ow.v /^ reg [5:0] cnt_42block = 6'd0;$/;" r module:data_ow +cnt_50 hdl/DAGC_v2.v /^ reg [ 5:0] cnt_50 = 6'd0;$/;" r module:DAGC_v2 +cnt_512 hdl/TSync_Abs_new16.v /^ reg [8:0] cnt_512 = 9'd0;$/;" r module:TSync_Abs_new16 +cnt_512 hdl/TSync_Abs_new4.v /^ reg [8:0] cnt_512 = 9'd0;$/;" r module:TSync_Abs_new4 +cnt_6 hdl/freqestm.v /^ reg [ 3:0] cnt_6;$/;" r module:freqestm +cnt_64 hdl/TSync_Abs_new16.v /^ reg [5:0] cnt_64 = 6'd0;$/;" r module:TSync_Abs_new16 +cnt_64 hdl/TSync_Abs_new4.v /^ reg [5:0] cnt_64 = 6'd0;$/;" r module:TSync_Abs_new4 +cnt_8 hdl/FrameMerge.v /^ output reg [2:0] cnt_8 = 3'b0,$/;" p module:FrameMerge +cnt_8 hdl/RecvTop.v /^ wire [ 2:0] cnt_8;$/;" n module:RecvTop +cnt_add_prefix_in hdl/enc_control.v /^ reg [ 2:0] cnt_add_prefix_in;$/;" r module:enc_control +cnt_adjust_times hdl/power_measure.v /^ reg [ 7:0] cnt_adjust_times;$/;" r module:power_measure +cnt_agc_send hdl/Transmitter.v /^ reg [15:0] cnt_agc_send; \/\/ agc symbols have been sent$/;" r module:Transmitter +cnt_amp_too_high hdl/power_measure.v /^ reg [ 3:0] cnt_amp_too_high; \/\/ for short cuirt $/;" r module:power_measure +cnt_bag hdl/freqestm.v /^ reg [ 7:0] cnt_bag;$/;" r module:freqestm +cnt_blocks_send hdl/Transmitter.v /^ reg [15:0] cnt_blocks_send; \/\/ blocks have been sent$/;" r module:Transmitter +cnt_chu_send hdl/Transmitter.v /^ reg [15:0] cnt_chu_send;$/;" r module:Transmitter +cnt_cp hdl/freqestm.v /^ reg [11:0] cnt_cp;$/;" r module:freqestm +cnt_data_in sim/tb_width_convert.v /^ reg [3:0] cnt_data_in;$/;" r module:tb_width_convert +cnt_databag hdl/DAGC_v2.v /^ reg [14:0] cnt_databag = 15'd0;$/;" r module:DAGC_v2 +cnt_din hdl/CCSDS_LDPC_ENC_R12.v /^ reg [10:0] cnt_din = 11'd0; \/\/输入1024个时钟$/;" r module:CCSDS_LDPC_ENC_R12 +cnt_din_d1 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [10:0] cnt_din_d1 = 11'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +cnt_din_d2 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [10:0] cnt_din_d2 = 11'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +cnt_div sim/tb_enc_control.v /^ reg [ 1:0] cnt_div = 0;$/;" r module:tb_enc_control +cnt_encode_valid hdl/CCSDS_LDPC_ENC_R12.v /^ reg [9:0] cnt_encode_valid = 10'd0;$/;" r module:CCSDS_LDPC_ENC_R12 +cnt_fifo hdl/freqestm.v /^ reg [15:0] cnt_fifo;$/;" r module:freqestm +cnt_fifo_out_valid hdl/Receiver.v /^ reg [ 2:0] cnt_fifo_out_valid;$/;" r module:Receiver +cnt_fifo_out_valid_sel hdl/Receiver.v /^ reg [ 2:0] cnt_fifo_out_valid_sel; \/\/ 根据speed mode对应的计数器边界值$/;" r module:Receiver +cnt_frame hdl/freqestm.v /^ reg [14:0] cnt_frame;$/;" r module:freqestm +cnt_h hdl/tdma.v /^ reg [ 7:0] cnt_h;$/;" r module:tdma +cnt_in hdl/add_prefix.v /^ reg [CNT_WIDTH : 0] cnt_in;$/;" r module:add_prefix +cnt_in hdl/enc_control.v /^ reg [ CNT_IN_WIDTH : 0] cnt_in; \/\/ 多留1bit$/;" r module:enc_control +cnt_in sim/tb_width_convert.v /^ reg [5:0] cnt_in;$/;" r module:tb_width_convert +cnt_interp hdl/Transmitter.v /^ reg [ 3:0] cnt_interp;$/;" r module:Transmitter +cnt_l hdl/tdma.v /^ reg [15:0] cnt_l;$/;" r module:tdma +cnt_lost hdl/RecvTop.v /^ reg [20:0] cnt_lost;$/;" r module:RecvTop +cnt_measuring hdl/power_measure.v /^ reg [15:0] cnt_measuring;$/;" r module:power_measure +cnt_mgc_delay hdl/RecvTop.v /^ reg [7:0] cnt_mgc_delay;$/;" r module:RecvTop +cnt_net hdl/FrameMerge.v /^ reg [6:0] cnt_net;$/;" r module:FrameMerge +cnt_out hdl/add_prefix.v /^ reg [ CNT_WIDTH:0] cnt_out;$/;" r module:add_prefix +cnt_out hdl/enc_control.v /^ reg [CNT_OUT_WIDTH : 0] cnt_out; \/\/ 多留1bit$/;" r module:enc_control +cnt_phase hdl/phase_adjust.v /^ reg [9:0] cnt_phase;$/;" r module:phase_adjust +cnt_pilot hdl/freqestm.v /^ reg [11:0] cnt_pilot;$/;" r module:freqestm +cnt_process hdl/freqestm.v /^ reg [11:0] cnt_process;$/;" r module:freqestm +cnt_pulse_width hdl/ad9361_mgc_pin_ctrl.v /^ reg [3:0] cnt_pulse_width;$/;" r module:ad9361_mgc_pin_ctrl +cnt_rd sim/tb_enc_control.v /^ reg [1:0] cnt_rd;$/;" r module:tb_enc_control +cnt_rst hdl/DAGC_v2.v /^ reg [19:0] cnt_rst = 20'd0;$/;" r module:DAGC_v2 +cnt_rst hdl/freqestm.v /^ reg [19:0] cnt_rst = 20'd0;$/;" r module:freqestm +cnt_start sim/tb_enc_control.v /^ reg [31:0] cnt_start;$/;" r module:tb_enc_control +cnt_startup hdl/Receiver.v /^ reg [ 8:0] cnt_startup;$/;" r module:Receiver +cnt_startup hdl/power_measure.v /^ reg [ 7:0] cnt_startup; \/\/ set rx gain to max each time start posedge comes$/;" r module:power_measure +cnt_startup sim/tb_width_convert.v /^ reg [5:0] cnt_startup;$/;" r module:tb_width_convert +cnt_sym_send hdl/Transmitter.v /^ reg [15:0] cnt_sym_send; \/\/ symbols have been sent$/;" r module:Transmitter +cnt_tsync hdl/RecvTop.v /^ wire [1:0] cnt_tsync;$/;" n module:RecvTop +cnt_tsync hdl/TimeSync_top.v /^ output reg [1:0] cnt_tsync = 2'd0,\/\/12.5$/;" p module:TimeSync_top +cnt_wait hdl/Transmitter.v /^ reg [15:0] cnt_wait; \/\/ wait cnt max 65535 period, 50M -> 1.3ms$/;" r module:Transmitter +cnt_wait_9361 hdl/power_measure.v /^ reg [15:0] cnt_wait_9361;$/;" r module:power_measure +color1 adi_library/common/ad_csc.v /^ wire signed [8:0] color1;$/;" n module:ad_csc +color2 adi_library/common/ad_csc.v /^ wire signed [8:0] color2;$/;" n module:ad_csc +color3 adi_library/common/ad_csc.v /^ wire signed [8:0] color3;$/;" n module:ad_csc +com_freq hdl/freqestm.v /^ com_freq com_freq ($/;" i module:freqestm typeref:module:com_freq +comdiv_ac_a hdl/Chn_Estimate.v /^reg [13:0] comdiv_ac_a = 14'd0;$/;" r module:Chn_Estimate +comdiv_ac_c hdl/Chn_Estimate.v /^reg [7:0] comdiv_ac_c = 8'd0;$/;" r module:Chn_Estimate +comdiv_ac_out hdl/Chn_Estimate.v /^wire[21:0] comdiv_ac_out;$/;" n module:Chn_Estimate +comdiv_ad_a hdl/Chn_Estimate.v /^reg [13:0] comdiv_ad_a = 14'd0;$/;" r module:Chn_Estimate +comdiv_ad_d hdl/Chn_Estimate.v /^reg [7:0] comdiv_ad_d = 8'd0;$/;" r module:Chn_Estimate +comdiv_ad_out hdl/Chn_Estimate.v /^wire[21:0] comdiv_ad_out;$/;" n module:Chn_Estimate +comdiv_bc_b hdl/Chn_Estimate.v /^reg [13:0] comdiv_bc_b = 14'd0;$/;" r module:Chn_Estimate +comdiv_bc_c hdl/Chn_Estimate.v /^reg [7:0] comdiv_bc_c = 8'd0;$/;" r module:Chn_Estimate +comdiv_bc_out hdl/Chn_Estimate.v /^wire[21:0] comdiv_bc_out;$/;" n module:Chn_Estimate +comdiv_bd_b hdl/Chn_Estimate.v /^reg [13:0] comdiv_bd_b = 14'd0;$/;" r module:Chn_Estimate +comdiv_bd_d hdl/Chn_Estimate.v /^reg [7:0] comdiv_bd_d = 8'd0;$/;" r module:Chn_Estimate +comdiv_bd_out hdl/Chn_Estimate.v /^wire[21:0] comdiv_bd_out;$/;" n module:Chn_Estimate +comdiv_temp_ac_bd hdl/Chn_Estimate.v /^reg [22:0] comdiv_temp_ac_bd = 23'd0;$/;" r module:Chn_Estimate +comdiv_temp_ac_bd2 hdl/Chn_Estimate.v /^reg [25:0] comdiv_temp_ac_bd2 = 26'd0;$/;" r module:Chn_Estimate +comdiv_temp_bc_ad hdl/Chn_Estimate.v /^reg [22:0] comdiv_temp_bc_ad = 23'd0;$/;" r module:Chn_Estimate +comdiv_temp_bc_ad2 hdl/Chn_Estimate.v /^reg [25:0] comdiv_temp_bc_ad2 = 26'd0;$/;" r module:Chn_Estimate +compare_id adi_library/axi_dmac/request_arb.v /^function compare_id;$/;" f module:dmac_request_arb +completion_req adi_library/axi_dmac/axi_dmac_response_manager.v /^wire completion_req;$/;" n module:axi_dmac_response_manager +completion_req_last adi_library/axi_dmac/axi_dmac_response_manager.v /^ input completion_req_last,$/;" p module:axi_dmac_response_manager +completion_req_last adi_library/axi_dmac/request_arb.v /^wire completion_req_last;$/;" n module:dmac_request_arb +completion_req_last adi_library/axi_dmac/request_generator.v /^ output completion_req_last,$/;" p module:dmac_request_generator +completion_req_last_found adi_library/axi_dmac/axi_dmac_response_manager.v /^reg completion_req_last_found = 1'b0;$/;" r module:axi_dmac_response_manager +completion_req_ready adi_library/axi_dmac/axi_dmac_response_manager.v /^ output reg completion_req_ready = 1'b1,$/;" p module:axi_dmac_response_manager +completion_req_ready adi_library/axi_dmac/request_arb.v /^wire completion_req_ready;$/;" n module:dmac_request_arb +completion_req_ready adi_library/axi_dmac/request_generator.v /^ input completion_req_ready,$/;" p module:dmac_request_generator +completion_req_valid adi_library/axi_dmac/axi_dmac_response_manager.v /^ input completion_req_valid,$/;" p module:axi_dmac_response_manager +completion_req_valid adi_library/axi_dmac/request_arb.v /^wire completion_req_valid;$/;" n module:dmac_request_arb +completion_req_valid adi_library/axi_dmac/request_generator.v /^ output reg completion_req_valid = 1'b0,$/;" p module:dmac_request_generator +completion_transfer_id adi_library/axi_dmac/axi_dmac_response_manager.v /^ input [1:0] completion_transfer_id$/;" p module:axi_dmac_response_manager +completion_transfer_id adi_library/axi_dmac/request_arb.v /^wire [1:0] completion_transfer_id;$/;" n module:dmac_request_arb +completion_transfer_id adi_library/axi_dmac/request_generator.v /^ output [1:0] completion_transfer_id,$/;" p module:dmac_request_generator +core_clk adi_library/common/ad_sysref_gen.v /^ input core_clk,$/;" p module:ad_sysref_gen +cos_addr hdl/DDS_compensate.v /^ reg [12:0] cos_addr = 0,sin_addr = -13'd2048;$/;" r module:DDS_compensate +cos_dout hdl/DDS_compensate.v /^ wire [11:0] cos_dout,sin_dout;$/;" n module:DDS_compensate +cosine adi_library/common/ad_dds_sine_cordic.v /^ output reg [CORDIC_DW-1:0] cosine,$/;" p module:ad_dds_sine_cordic +count adi_library/axi_dmac/axi_dmac_resize_dest.v /^ reg [$clog2(RATIO)-1:0] count = 'h0;$/;" r module:axi_dmac_resize_dest +count adi_library/axi_dmac/tb/axi_write_slave.v /^always @(*) begin: count$/;" b module:axi_write_slave +count adi_library/util_axis_resize/util_axis_resize.v /^reg [clog2(RATIO)-1:0] count;$/;" r module:util_axis_resize +count_rst500 hdl/SCFDE_recv_FrameSync.v /^ reg [11:0] count_rst500 = 12'd0;$/;" r module:SCFDE_recv_FrameSync +counter adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg [10:0] counter = 'h00;$/;" r module:dmac_reset_manager_tb +counter adi_library/common/ad_sysref_gen.v /^ reg [ 7:0] counter;$/;" r module:ad_sysref_gen +counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;$/;" r module:spi_engine_execution +counter adi_library/util_cic/cic_comb.v /^reg [2:0] counter = 'h00;$/;" r module:cic_comb +counter adi_library/util_pack/tb/cpack_tb.v /^ integer counter;$/;" r module:cpack_tb +counter adi_library/util_pack/tb/underflow_tb.v /^ integer counter = 0;$/;" r module:upack2_underflow_tb +counter adi_library/util_pack/tb/upack_tb.v /^ integer counter;$/;" r module:upack_tb +counter adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT;$/;" r module:util_sigma_delta_spi +counter88 hdl/SCFDE_recv_FrameSync.v /^ reg [ 6:0] counter88 = 7'd0;$/;" r module:SCFDE_recv_FrameSync +counter_at_tdd_rx_dp_off_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_rx_dp_off_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_rx_dp_off_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_rx_dp_off_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_rx_dp_on_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_rx_dp_on_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_rx_dp_on_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_rx_dp_on_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_rx_off_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_rx_off_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_rx_off_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_rx_off_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_rx_on_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_rx_on_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_rx_on_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_rx_on_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_tx_dp_off_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_tx_dp_off_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_tx_dp_off_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_tx_dp_off_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_tx_dp_on_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_tx_dp_on_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_tx_dp_on_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_tx_dp_on_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_tx_off_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_tx_off_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_tx_off_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_tx_off_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_tx_on_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_tx_on_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_tx_on_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_tx_on_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_vco_rx_off_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_vco_rx_off_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_vco_rx_off_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_vco_rx_off_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_vco_rx_on_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_vco_rx_on_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_vco_rx_on_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_vco_rx_on_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_vco_tx_off_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_vco_tx_off_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_vco_tx_off_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_vco_tx_off_2 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_vco_tx_on_1 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_vco_tx_on_1 = 1'b0;$/;" r module:ad_tdd_control +counter_at_tdd_vco_tx_on_2 adi_library/common/ad_tdd_control.v /^ reg counter_at_tdd_vco_tx_on_2 = 1'b0;$/;" r module:ad_tdd_control +cpack_tb adi_library/util_pack/tb/cpack_tb.v /^module cpack_tb;$/;" m +cpha adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg cpha = DEFAULT_SPI_CFG[0];$/;" r module:spi_engine_execution +cpll_locked_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire cpll_locked_s;$/;" n module:util_adxcvr_xch +cpll_ref_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input cpll_ref_clk,$/;" p module:util_adxcvr_xch +cpll_ref_clk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_0,$/;" p module:util_adxcvr +cpll_ref_clk_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_1,$/;" p module:util_adxcvr +cpll_ref_clk_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_10,$/;" p module:util_adxcvr +cpll_ref_clk_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_11,$/;" p module:util_adxcvr +cpll_ref_clk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_12,$/;" p module:util_adxcvr +cpll_ref_clk_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_13,$/;" p module:util_adxcvr +cpll_ref_clk_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_14,$/;" p module:util_adxcvr +cpll_ref_clk_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_15,$/;" p module:util_adxcvr +cpll_ref_clk_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_2,$/;" p module:util_adxcvr +cpll_ref_clk_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_3,$/;" p module:util_adxcvr +cpll_ref_clk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_4,$/;" p module:util_adxcvr +cpll_ref_clk_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_5,$/;" p module:util_adxcvr +cpll_ref_clk_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_6,$/;" p module:util_adxcvr +cpll_ref_clk_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_7,$/;" p module:util_adxcvr +cpll_ref_clk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_8,$/;" p module:util_adxcvr +cpll_ref_clk_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input cpll_ref_clk_9,$/;" p module:util_adxcvr +cpol adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg cpol = DEFAULT_SPI_CFG[1];$/;" r module:spi_engine_execution +cr adi_library/common/ad_ss_444to422.v /^ reg [ 7:0] cr = 'd0;$/;" r module:ad_ss_444to422 +cr_cb_sel adi_library/common/ad_ss_422to444.v /^ reg cr_cb_sel = 'd0;$/;" r module:ad_ss_422to444 +cr_cb_sel adi_library/common/ad_ss_444to422.v /^ reg cr_cb_sel = 'd0;$/;" r module:ad_ss_444to422 +cr_s adi_library/common/ad_ss_444to422.v /^ wire [ 9:0] cr_s;$/;" n module:ad_ss_444to422 +cs adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg [NUM_OF_CS-1:0] cs,$/;" p module:spi_engine_execution +cs hdl/Transmitter.v /^ reg [ 3:0] cs;$/;" r module:Transmitter +cs hdl/ad9361_mgc_pin_ctrl.v /^ reg [2:0] cs;$/;" r module:ad9361_mgc_pin_ctrl +cs hdl/add_prefix.v /^ reg [ 2:0] cs = 0;$/;" r module:add_prefix +cs hdl/enc_control.v /^ reg [ 3:0] cs;$/;" r module:enc_control +cs hdl/power_measure.v /^ reg [2:0] cs = S_MEASURE_IDLE;$/;" r module:power_measure +cs_active_s adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);$/;" n module:spi_engine_execution +cs_sleep_counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];$/;" n module:spi_engine_execution +cs_sleep_counter2 adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)];$/;" n module:spi_engine_execution +cs_sleep_counter_compare adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire cs_sleep_counter_compare;$/;" n module:spi_engine_execution +cs_sleep_counter_compare2 adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire cs_sleep_counter_compare2;$/;" n module:spi_engine_execution +csc_data adi_library/common/ad_csc.v /^ output [ 7:0] csc_data);$/;" p module:ad_csc +csc_data_d adi_library/common/ad_csc.v /^ reg [ 7:0] csc_data_d;$/;" r module:ad_csc +csc_sync adi_library/common/ad_csc.v /^ output [ DELAY_DW-1:0] csc_sync,$/;" p module:ad_csc +ctrl adi_library/util_pack/util_pack_common/pack_ctrl.v /^ output [2**PORT_ADDRESS_WIDTH*MUX_ORDER*NUM_STAGES-1:0] ctrl$/;" p module:pack_ctrl +ctrl adi_library/util_pack/util_pack_common/pack_interconnect.v /^ input [2**PORT_ADDRESS_WIDTH*MUX_ORDER*NUM_STAGES-1:0] ctrl,$/;" p module:pack_interconnect +ctrl adi_library/util_pack/util_pack_common/pack_network.v /^ reg [CTRL_WIDTH-1:0] ctrl = 'h00;$/;" r module:pack_network +ctrl hdl/trunc_25to12_2dly.v /^ input ctrl;$/;" p module:trunc_25to12_2dly +ctrl1 adi_library/util_pack/util_pack_common/pack_ctrl.v /^ wire [NUM_OF_PORTS*MUX_ORDER*NUM_STAGES-1:0] ctrl1;$/;" n module:pack_ctrl +ctrl2 adi_library/util_pack/util_pack_common/pack_ctrl.v /^ reg [NUM_OF_PORTS*MUX_ORDER*NUM_STAGES-1:0] ctrl2;$/;" r module:pack_ctrl +ctrl_ adi_library/util_pack/util_pack_common/pack_network.v /^ wire [CTRL_WIDTH-1:0] ctrl_;$/;" n module:pack_network +ctrl_base adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam ctrl_base = (ctrl_stage * NUM_PORTS + j) * MUX_ORDER;$/;" c block:pack_interconnect.gen_stages.gen_ports +ctrl_clk adi_library/axi_dmac/axi_dmac_transfer.v /^ input ctrl_clk,$/;" p module:axi_dmac_transfer +ctrl_clk adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input ctrl_clk,$/;" p module:spi_engine_offload +ctrl_cmd_wr_addr adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00;$/;" r module:spi_engine_offload +ctrl_cmd_wr_data adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input [15:0] ctrl_cmd_wr_data,$/;" p module:spi_engine_offload +ctrl_cmd_wr_en adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input ctrl_cmd_wr_en,$/;" p module:spi_engine_offload +ctrl_do_enable adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg ctrl_do_enable = 1'b0;$/;" r module:spi_engine_offload +ctrl_enable adi_library/axi_dmac/axi_dmac.v /^wire ctrl_enable;$/;" n module:axi_dmac +ctrl_enable adi_library/axi_dmac/axi_dmac_regmap.v /^ output reg ctrl_enable = 1'b0,$/;" p module:axi_dmac_regmap +ctrl_enable adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input ctrl_enable,$/;" p module:axi_dmac_regmap_request +ctrl_enable adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input ctrl_enable,$/;" p module:axi_dmac_reset_manager +ctrl_enable adi_library/axi_dmac/axi_dmac_transfer.v /^ input ctrl_enable,$/;" p module:axi_dmac_transfer +ctrl_enable adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ reg ctrl_enable = 1'b0;$/;" r module:dmac_dma_read_shutdown_tb +ctrl_enable adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ reg ctrl_enable = 1'b0;$/;" r module:dmac_dma_write_shutdown_tb +ctrl_enable adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg ctrl_enable = 1'b0;$/;" r module:dmac_reset_manager_tb +ctrl_enable adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input ctrl_enable,$/;" p module:spi_engine_offload +ctrl_enabled adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output ctrl_enabled,$/;" p module:spi_engine_offload +ctrl_gen_inner adi_library/util_pack/util_pack_common/pack_ctrl.v /^ for (j = 0; j < NUM_OF_PORTS; j = j + 1) begin: ctrl_gen_inner$/;" b block:pack_ctrl.ctrl_gen_outer +ctrl_gen_outer adi_library/util_pack/util_pack_common/pack_ctrl.v /^ for (i = 0; i < NUM_STAGES; i = i + 1) begin: ctrl_gen_outer$/;" b module:pack_ctrl +ctrl_is_enabled adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^wire ctrl_is_enabled;$/;" n module:spi_engine_offload +ctrl_mem_reset adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input ctrl_mem_reset,$/;" p module:spi_engine_offload +ctrl_pause adi_library/axi_dmac/axi_dmac.v /^wire ctrl_pause;$/;" n module:axi_dmac +ctrl_pause adi_library/axi_dmac/axi_dmac_regmap.v /^ output reg ctrl_pause = 1'b0,$/;" p module:axi_dmac_regmap +ctrl_pause adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input ctrl_pause,$/;" p module:axi_dmac_reset_manager +ctrl_pause adi_library/axi_dmac/axi_dmac_transfer.v /^ input ctrl_pause,$/;" p module:axi_dmac_transfer +ctrl_pause adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg ctrl_pause = 1'b0;$/;" r module:dmac_reset_manager_tb +ctrl_resetn adi_library/axi_dmac/axi_dmac_transfer.v /^ input ctrl_resetn,$/;" p module:axi_dmac_transfer +ctrl_s adi_library/util_pack/util_pack_common/pack_network.v /^ wire [CTRL_WIDTH-1:0] ctrl_s;$/;" n module:pack_network +ctrl_sdo_wr_addr adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;$/;" r module:spi_engine_offload +ctrl_sdo_wr_data adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,$/;" p module:spi_engine_offload +ctrl_sdo_wr_en adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input ctrl_sdo_wr_en,$/;" p module:spi_engine_offload +ctrl_stage adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam ctrl_stage = PACK ? NUM_STAGES - i - 1 : i;$/;" c block:pack_interconnect.gen_stages +ctrl_sync_id_init adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg [ 7:0] ctrl_sync_id_init = 8'b0;$/;" r module:spi_engine_offload +ctrl_sync_id_load adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg ctrl_sync_id_load = 1'b0;$/;" r module:spi_engine_offload +cur_burst_length adi_library/axi_dmac/request_generator.v /^reg [BURSTS_PER_TRANSFER_WIDTH-1:0] cur_burst_length = 'h00;$/;" r module:dmac_request_generator +cur_req_xlast adi_library/axi_dmac/request_generator.v /^reg cur_req_xlast;$/;" r module:dmac_request_generator +cur_transfer_id adi_library/axi_dmac/request_generator.v /^reg cur_transfer_id = 1'b0;$/;" r module:dmac_request_generator +current_state adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ reg [ 1:0] current_state = IDLE;$/;" r module:mdc_mdio +cycle_out_cnt hdl/Out_Process_R12.v /^ reg [10:0] cycle_out_cnt = 11'd0;$/;" r module:Out_Process_R12 +cycle_out_en hdl/Out_Process_R12.v /^ reg cycle_out_en = 1'd0;$/;" r module:Out_Process_R12 +d_acc_data adi_library/common/up_xfer_status.v /^ reg [(DATA_WIDTH-1):0] d_acc_data = 'd0;$/;" r module:up_xfer_status +d_clk adi_library/common/up_clock_mon.v /^ input d_clk);$/;" p module:up_clock_mon +d_clk adi_library/common/up_xfer_cntrl.v /^ input d_clk,$/;" p module:up_xfer_cntrl +d_clk adi_library/common/up_xfer_status.v /^ input d_clk,$/;" p module:up_xfer_status +d_count adi_library/common/up_clock_mon.v /^ reg [TOTAL_WIDTH:0] d_count = 'd0;$/;" r module:up_clock_mon +d_count_reset_s adi_library/common/up_clock_mon.v /^ wire d_count_reset_s;$/;" n module:up_clock_mon +d_count_run_m1 adi_library/common/up_clock_mon.v /^ reg d_count_run_m1 = 'd0;$/;" r module:up_clock_mon +d_count_run_m2 adi_library/common/up_clock_mon.v /^ reg d_count_run_m2 = 'd0;$/;" r module:up_clock_mon +d_count_run_m3 adi_library/common/up_clock_mon.v /^ reg d_count_run_m3 = 'd0;$/;" r module:up_clock_mon +d_data_cntrl adi_library/common/up_xfer_cntrl.v /^ output [(DATA_WIDTH-1):0] d_data_cntrl);$/;" p module:up_xfer_cntrl +d_data_cntrl_int adi_library/common/up_xfer_cntrl.v /^ reg [(DATA_WIDTH-1):0] d_data_cntrl_int = 'd0;$/;" r module:up_xfer_cntrl +d_data_status adi_library/common/up_xfer_status.v /^ input [(DATA_WIDTH-1):0] d_data_status);$/;" p module:up_xfer_status +d_rst adi_library/common/up_clock_mon.v /^ input d_rst,$/;" p module:up_clock_mon +d_rst adi_library/common/up_xfer_cntrl.v /^ input d_rst,$/;" p module:up_xfer_cntrl +d_rst adi_library/common/up_xfer_status.v /^ input d_rst,$/;" p module:up_xfer_status +d_xfer_count adi_library/common/up_xfer_status.v /^ reg [ 5:0] d_xfer_count = 'd0;$/;" r module:up_xfer_status +d_xfer_data adi_library/common/up_xfer_status.v /^ reg [(DATA_WIDTH-1):0] d_xfer_data = 'd0;$/;" r module:up_xfer_status +d_xfer_enable_s adi_library/common/up_xfer_status.v /^ wire d_xfer_enable_s;$/;" n module:up_xfer_status +d_xfer_state adi_library/common/up_xfer_status.v /^ reg d_xfer_state = 'd0;$/;" r module:up_xfer_status +d_xfer_state_m1 adi_library/common/up_xfer_status.v /^ reg d_xfer_state_m1 = 'd0;$/;" r module:up_xfer_status +d_xfer_state_m2 adi_library/common/up_xfer_status.v /^ reg d_xfer_state_m2 = 'd0;$/;" r module:up_xfer_status +d_xfer_toggle adi_library/common/up_xfer_cntrl.v /^ reg d_xfer_toggle = 'd0;$/;" r module:up_xfer_cntrl +d_xfer_toggle adi_library/common/up_xfer_status.v /^ reg d_xfer_toggle = 'd0;$/;" r module:up_xfer_status +d_xfer_toggle_m1 adi_library/common/up_xfer_cntrl.v /^ reg d_xfer_toggle_m1 = 'd0;$/;" r module:up_xfer_cntrl +d_xfer_toggle_m2 adi_library/common/up_xfer_cntrl.v /^ reg d_xfer_toggle_m2 = 'd0;$/;" r module:up_xfer_cntrl +d_xfer_toggle_m3 adi_library/common/up_xfer_cntrl.v /^ reg d_xfer_toggle_m3 = 'd0;$/;" r module:up_xfer_cntrl +d_xfer_toggle_s adi_library/common/up_xfer_cntrl.v /^ wire d_xfer_toggle_s;$/;" n module:up_xfer_cntrl +dac_addr_diff adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dac_addr_diff = 'b0;$/;" r module:util_dacfifo +dac_addr_diff_s adi_library/util_dacfifo/util_dacfifo.v /^ wire [ADDRESS_WIDTH:0] dac_addr_diff_s;$/;" n module:util_dacfifo +dac_bypass adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_bypass = 1'b0;$/;" r module:util_dacfifo +dac_bypass adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ reg dac_bypass = 1'b0;$/;" r module:axi_dacfifo +dac_bypass_m1 adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_bypass_m1 = 1'b0;$/;" r module:util_dacfifo +dac_bypass_m1 adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ reg dac_bypass_m1 = 1'b0;$/;" r module:axi_dacfifo +dac_clk adi_library/common/up_dac_channel.v /^ input dac_clk,$/;" p module:up_dac_channel +dac_clk adi_library/common/up_dac_common.v /^ input dac_clk,$/;" p module:up_dac_common +dac_clk adi_library/util_dacfifo/util_dacfifo.v /^ input dac_clk,$/;" p module:util_dacfifo +dac_clk adi_library/util_dacfifo/util_dacfifo_bypass.v /^ input dac_clk,$/;" p module:util_dacfifo_bypass +dac_clk adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input dac_clk,$/;" p module:axi_dacfifo +dac_clk adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input dac_clk,$/;" p module:axi_dacfifo_rd +dac_clk_ratio adi_library/common/up_dac_common.v /^ input [31:0] dac_clk_ratio,$/;" p module:up_dac_common +dac_clksel adi_library/common/up_dac_common.v /^ output dac_clksel,$/;" p module:up_dac_common +dac_data adi_library/util_dacfifo/util_dacfifo.v /^ output reg [(DATA_WIDTH-1):0] dac_data,$/;" p module:util_dacfifo +dac_data adi_library/util_dacfifo/util_dacfifo_bypass.v /^ output reg [(DAC_DATA_WIDTH-1):0] dac_data,$/;" p module:util_dacfifo_bypass +dac_data adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output reg [(DAC_DATA_WIDTH-1):0] dac_data,$/;" p module:axi_dacfifo +dac_data adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output [(DAC_DATA_WIDTH-1):0] dac_data,$/;" p module:axi_dacfifo_rd +dac_data_bypass_s adi_library/util_dacfifo/util_dacfifo.v /^ wire [(DATA_WIDTH-1):0] dac_data_bypass_s;$/;" n module:util_dacfifo +dac_data_bypass_s adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s;$/;" n module:axi_dacfifo +dac_data_fifo_s adi_library/util_dacfifo/util_dacfifo.v /^ wire [(DATA_WIDTH-1):0] dac_data_fifo_s;$/;" n module:util_dacfifo +dac_data_fifo_s adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s;$/;" n module:axi_dacfifo +dac_data_sel adi_library/common/up_dac_channel.v /^ output [ 3:0] dac_data_sel,$/;" p module:up_dac_channel +dac_data_sync adi_library/common/ad_dds.v /^ input dac_data_sync,$/;" p module:ad_dds +dac_data_sync_m adi_library/common/ad_dds.v /^ reg dac_data_sync_m = 1'd0;$/;" r module:ad_dds +dac_datafmt adi_library/common/up_dac_common.v /^ output dac_datafmt,$/;" p module:up_dac_common +dac_datarate adi_library/common/up_dac_common.v /^ output [15:0] dac_datarate,$/;" p module:up_dac_common +dac_dds_data adi_library/common/ad_dds.v /^ output reg [DDS_DW*CLK_RATIO-1:0] dac_dds_data$/;" p module:ad_dds +dac_dds_data_s adi_library/common/ad_dds.v /^ wire [DDS_DW*CLK_RATIO-1:0] dac_dds_data_s;$/;" n module:ad_dds +dac_dds_format adi_library/common/ad_dds.v /^ input dac_dds_format,$/;" p module:ad_dds +dac_dds_incr_0 adi_library/common/ad_dds.v /^ reg [PHASE_DW-1:0] dac_dds_incr_0 = 'd0;$/;" r module:ad_dds +dac_dds_incr_1 adi_library/common/ad_dds.v /^ reg [PHASE_DW-1:0] dac_dds_incr_1 = 'd0;$/;" r module:ad_dds +dac_dds_incr_1 adi_library/common/up_dac_channel.v /^ output [15:0] dac_dds_incr_1,$/;" p module:up_dac_channel +dac_dds_incr_2 adi_library/common/up_dac_channel.v /^ output [15:0] dac_dds_incr_2,$/;" p module:up_dac_channel +dac_dds_init_1 adi_library/common/up_dac_channel.v /^ output [15:0] dac_dds_init_1,$/;" p module:up_dac_channel +dac_dds_init_2 adi_library/common/up_dac_channel.v /^ output [15:0] dac_dds_init_2,$/;" p module:up_dac_channel +dac_dds_phase_0 adi_library/common/ad_dds.v /^ reg [PHASE_DW-1:0] dac_dds_phase_0[1:CLK_RATIO];$/;" r module:ad_dds +dac_dds_phase_1 adi_library/common/ad_dds.v /^ reg [PHASE_DW-1:0] dac_dds_phase_1[1:CLK_RATIO];$/;" r module:ad_dds +dac_dds_scale_1 adi_library/common/up_dac_channel.v /^ output [15:0] dac_dds_scale_1,$/;" p module:up_dac_channel +dac_dds_scale_2 adi_library/common/up_dac_channel.v /^ output [15:0] dac_dds_scale_2,$/;" p module:up_dac_channel +dac_dunf adi_library/util_dacfifo/util_dacfifo.v /^ output reg dac_dunf,$/;" p module:util_dacfifo +dac_dunf adi_library/util_dacfifo/util_dacfifo_bypass.v /^ output reg dac_dunf$/;" p module:util_dacfifo_bypass +dac_dunf adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output reg dac_dunf,$/;" p module:axi_dacfifo +dac_dunf adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output reg dac_dunf);$/;" p module:axi_dacfifo_rd +dac_dunf_bypass_s adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ wire dac_dunf_bypass_s;$/;" n module:axi_dacfifo +dac_dunf_fifo_s adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ wire dac_dunf_fifo_s;$/;" n module:axi_dacfifo +dac_frame adi_library/common/up_dac_common.v /^ output dac_frame,$/;" p module:up_dac_common +dac_frame_2d adi_library/common/up_dac_common.v /^ reg dac_frame_2d = 'd0;$/;" r module:up_dac_common +dac_frame_d adi_library/common/up_dac_common.v /^ reg dac_frame_d = 'd0;$/;" r module:up_dac_common +dac_frame_int adi_library/common/up_dac_common.v /^ reg dac_frame_int = 'd0;$/;" r module:up_dac_common +dac_frame_s adi_library/common/up_dac_common.v /^ wire dac_frame_s;$/;" n module:up_dac_common +dac_iq_mode adi_library/common/up_dac_channel.v /^ output [ 1:0] dac_iq_mode,$/;" p module:up_dac_channel +dac_iqcor_coeff_1 adi_library/common/up_dac_channel.v /^ output [15:0] dac_iqcor_coeff_1,$/;" p module:up_dac_channel +dac_iqcor_coeff_2 adi_library/common/up_dac_channel.v /^ output [15:0] dac_iqcor_coeff_2,$/;" p module:up_dac_channel +dac_iqcor_enb adi_library/common/up_dac_channel.v /^ output dac_iqcor_enb,$/;" p module:up_dac_channel +dac_last_beats adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [ 3:0] dac_last_beats = 4'b0;$/;" r module:axi_dacfifo_rd +dac_last_beats_m adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [ 3:0] dac_last_beats_m = 4'b0;$/;" r module:axi_dacfifo_rd +dac_lastaddr adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dac_lastaddr = 'b0;$/;" r module:util_dacfifo +dac_lastaddr_g2b_s adi_library/util_dacfifo/util_dacfifo.v /^ wire [(ADDRESS_WIDTH-1):0] dac_lastaddr_g2b_s;$/;" n module:util_dacfifo +dac_lastaddr_m1 adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m1 = 'b0;$/;" r module:util_dacfifo +dac_lastaddr_m2 adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m2 = 'b0;$/;" r module:util_dacfifo +dac_mem_addr_diff_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire [ DAC_MEM_ADDRESS_WIDTH:0] dac_mem_addr_diff_s;$/;" n module:axi_dacfifo_rd +dac_mem_empty_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire dac_mem_empty_s;$/;" n module:util_dacfifo_bypass +dac_mem_enable adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg dac_mem_enable = 1'b0;$/;" r module:axi_dacfifo_rd +dac_mem_laddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr = 'd0;$/;" r module:axi_dacfifo_rd +dac_mem_laddr_b adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_b = 'd0;$/;" r module:axi_dacfifo_rd +dac_mem_laddr_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_s;$/;" n module:axi_dacfifo_rd +dac_mem_laddr_toggle_m adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [ 3:0] dac_mem_laddr_toggle_m = 4'd0;$/;" r module:axi_dacfifo_rd +dac_mem_raddr adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0;$/;" r module:util_dacfifo_bypass +dac_mem_raddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0;$/;" r module:axi_dacfifo_rd +dac_mem_raddr_b2g_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s;$/;" n module:util_dacfifo_bypass +dac_mem_raddr_b2g_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s;$/;" n module:axi_dacfifo_rd +dac_mem_raddr_g adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0;$/;" r module:util_dacfifo_bypass +dac_mem_raddr_g adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0;$/;" r module:axi_dacfifo_rd +dac_mem_rdata_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire [(DAC_DATA_WIDTH-1):0] dac_mem_rdata_s;$/;" n module:util_dacfifo_bypass +dac_mem_rea adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg dac_mem_rea = 1'b0;$/;" r module:util_dacfifo_bypass +dac_mem_rea_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire dac_mem_rea_s;$/;" n module:util_dacfifo_bypass +dac_mem_ready adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_mem_ready = 1'b0;$/;" r module:util_dacfifo +dac_mem_ren_s adi_library/util_dacfifo/util_dacfifo.v /^ wire dac_mem_ren_s;$/;" n module:util_dacfifo +dac_mem_valid adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg dac_mem_valid = 1'b0;$/;" r module:axi_dacfifo_rd +dac_mem_waddr adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr = 'd0;$/;" r module:util_dacfifo_bypass +dac_mem_waddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr = 'd0;$/;" r module:axi_dacfifo_rd +dac_mem_waddr_m1 adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 'd0;$/;" r module:util_dacfifo_bypass +dac_mem_waddr_m1 adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 'd0;$/;" r module:axi_dacfifo_rd +dac_mem_waddr_m2 adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 'd0;$/;" r module:util_dacfifo_bypass +dac_mem_waddr_m2 adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 'd0;$/;" r module:axi_dacfifo_rd +dac_mem_waddr_m2_g2b_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;$/;" n module:util_dacfifo_bypass +dac_mem_waddr_m2_g2b_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;$/;" n module:axi_dacfifo_rd +dac_mem_waddr_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_s;$/;" n module:util_dacfifo_bypass +dac_num_lanes adi_library/common/up_dac_common.v /^ output [4:0] dac_num_lanes,$/;" p module:up_dac_common +dac_par_enb adi_library/common/up_dac_common.v /^ output dac_par_enb,$/;" p module:up_dac_common +dac_par_type adi_library/common/up_dac_common.v /^ output dac_par_type,$/;" p module:up_dac_common +dac_pat_data_1 adi_library/common/up_dac_channel.v /^ output [15:0] dac_pat_data_1,$/;" p module:up_dac_channel +dac_pat_data_2 adi_library/common/up_dac_channel.v /^ output [15:0] dac_pat_data_2,$/;" p module:up_dac_channel +dac_r1_mode adi_library/common/up_dac_common.v /^ output dac_r1_mode,$/;" p module:up_dac_common +dac_raddr adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0;$/;" r module:util_dacfifo +dac_read adi_library/util_fir_int/util_fir_int.v /^ input dac_read);$/;" p module:util_fir_int +dac_rst adi_library/common/up_dac_channel.v /^ input dac_rst,$/;" p module:up_dac_channel +dac_rst adi_library/common/up_dac_common.v /^ output dac_rst,$/;" p module:up_dac_common +dac_rst adi_library/util_dacfifo/util_dacfifo.v /^ input dac_rst,$/;" p module:util_dacfifo +dac_rst adi_library/util_dacfifo/util_dacfifo_bypass.v /^ input dac_rst,$/;" p module:util_dacfifo_bypass +dac_rst adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input dac_rst,$/;" p module:axi_dacfifo +dac_rst adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input dac_rst,$/;" p module:axi_dacfifo_rd +dac_rst_int_s adi_library/util_dacfifo/util_dacfifo.v /^ wire dac_rst_int_s;$/;" n module:util_dacfifo +dac_rst_n adi_library/common/up_dac_common.v /^ wire dac_rst_n;$/;" n module:up_dac_common +dac_rst_s adi_library/common/up_dac_common.v /^ wire dac_rst_s;$/;" n module:up_dac_common +dac_sdr_ddr_n adi_library/common/up_dac_common.v /^ output dac_sdr_ddr_n,$/;" p module:up_dac_common +dac_status adi_library/common/up_dac_common.v /^ input dac_status,$/;" p module:up_dac_common +dac_status_unf adi_library/common/up_dac_common.v /^ input dac_status_unf,$/;" p module:up_dac_common +dac_sync adi_library/common/up_dac_common.v /^ output dac_sync,$/;" p module:up_dac_common +dac_sync_2d adi_library/common/up_dac_common.v /^ reg dac_sync_2d = 'd0;$/;" r module:up_dac_common +dac_sync_count adi_library/common/up_dac_common.v /^ reg [ 5:0] dac_sync_count = 'd0;$/;" r module:up_dac_common +dac_sync_d adi_library/common/up_dac_common.v /^ reg dac_sync_d = 'd0;$/;" r module:up_dac_common +dac_sync_in_status adi_library/common/up_dac_common.v /^ input dac_sync_in_status,$/;" p module:up_dac_common +dac_sync_int adi_library/common/up_dac_common.v /^ reg dac_sync_int = 'd0;$/;" r module:up_dac_common +dac_sync_s adi_library/common/up_dac_common.v /^ wire dac_sync_s;$/;" n module:up_dac_common +dac_usr_chanmax adi_library/common/up_dac_common.v /^ input [ 7:0] dac_usr_chanmax,$/;" p module:up_dac_common +dac_usr_datatype_be adi_library/common/up_dac_channel.v /^ input dac_usr_datatype_be,$/;" p module:up_dac_channel +dac_usr_datatype_bits adi_library/common/up_dac_channel.v /^ input [ 7:0] dac_usr_datatype_bits,$/;" p module:up_dac_channel +dac_usr_datatype_shift adi_library/common/up_dac_channel.v /^ input [ 7:0] dac_usr_datatype_shift,$/;" p module:up_dac_channel +dac_usr_datatype_signed adi_library/common/up_dac_channel.v /^ input dac_usr_datatype_signed,$/;" p module:up_dac_channel +dac_usr_datatype_total_bits adi_library/common/up_dac_channel.v /^ input [ 7:0] dac_usr_datatype_total_bits,$/;" p module:up_dac_channel +dac_usr_interpolation_m adi_library/common/up_dac_channel.v /^ input [15:0] dac_usr_interpolation_m,$/;" p module:up_dac_channel +dac_usr_interpolation_n adi_library/common/up_dac_channel.v /^ input [15:0] dac_usr_interpolation_n,$/;" p module:up_dac_channel +dac_valid adi_library/common/ad_dds.v /^ input dac_valid,$/;" p module:ad_dds +dac_valid adi_library/util_dacfifo/util_dacfifo.v /^ input dac_valid,$/;" p module:util_dacfifo +dac_valid adi_library/util_dacfifo/util_dacfifo_bypass.v /^ input dac_valid,$/;" p module:util_dacfifo_bypass +dac_valid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input dac_valid,$/;" p module:axi_dacfifo +dac_valid adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input dac_valid,$/;" p module:axi_dacfifo_rd +dac_waddr adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dac_waddr = 'b0;$/;" r module:util_dacfifo +dac_waddr_g2b_s adi_library/util_dacfifo/util_dacfifo.v /^ wire [(ADDRESS_WIDTH-1):0] dac_waddr_g2b_s;$/;" n module:util_dacfifo +dac_waddr_m1 adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dac_waddr_m1 = 'b0;$/;" r module:util_dacfifo +dac_waddr_m2 adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dac_waddr_m2 = 'b0;$/;" r module:util_dacfifo +dac_xfer_fifo_out_s adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ wire dac_xfer_fifo_out_s;$/;" n module:axi_dacfifo +dac_xfer_out adi_library/util_dacfifo/util_dacfifo.v /^ output reg dac_xfer_out,$/;" p module:util_dacfifo +dac_xfer_out adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output reg dac_xfer_out,$/;" p module:axi_dacfifo +dac_xfer_out adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ output dac_xfer_out,$/;" p module:axi_dacfifo_rd +dac_xfer_out_bypass adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ reg dac_xfer_out_bypass = 1'b0;$/;" r module:axi_dacfifo +dac_xfer_out_fifo adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_xfer_out_fifo = 1'b0;$/;" r module:util_dacfifo +dac_xfer_out_fifo_d adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_xfer_out_fifo_d = 1'b0;$/;" r module:util_dacfifo +dac_xfer_out_fifo_m1 adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_xfer_out_fifo_m1 = 1'b0;$/;" r module:util_dacfifo +dac_xfer_out_m1 adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ reg dac_xfer_out_m1 = 1'b0;$/;" r module:axi_dacfifo +dac_xfer_posedge_s adi_library/util_dacfifo/util_dacfifo.v /^ wire dac_xfer_posedge_s;$/;" n module:util_dacfifo +dac_xfer_req adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_xfer_req = 1'b0;$/;" r module:util_dacfifo +dac_xfer_req_d adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_xfer_req_d = 1'b0;$/;" r module:util_dacfifo +dac_xfer_req_m adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [ 2:0] dac_xfer_req_m = 3'b0;$/;" r module:axi_dacfifo_rd +dac_xfer_req_m1 adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_xfer_req_m1 = 1'b0;$/;" r module:util_dacfifo +dagc_rdy hdl/DAGC_v2.v /^ output reg dagc_rdy,$/;" p module:DAGC_v2 +dagc_rdy hdl/RecvTop.v /^ wire dagc_rdy;$/;" n module:RecvTop +dagc_rdy_d0 hdl/DAGC_v2.v /^ reg dagc_rdy_d0;$/;" r module:DAGC_v2 +dagc_rdy_d1 hdl/DAGC_v2.v /^ reg dagc_rdy_d1;$/;" r module:DAGC_v2 +dagc_rdy_d2 hdl/DAGC_v2.v /^ reg dagc_rdy_d2;$/;" r module:DAGC_v2 +dagc_rdy_d3 hdl/DAGC_v2.v /^ reg dagc_rdy_d3;$/;" r module:DAGC_v2 +dagc_rdy_d4 hdl/DAGC_v2.v /^ reg dagc_rdy_d4;$/;" r module:DAGC_v2 +data adi_library/axi_dmac/axi_dmac_resize_dest.v /^ reg [DATA_WIDTH_MEM-1:0] data = 'h0;$/;" r module:axi_dmac_resize_dest +data adi_library/axi_dmac/axi_dmac_resize_src.v /^ reg [DATA_WIDTH_MEM-1:0] data = 'h0;$/;" r module:axi_dmac_resize_src +data adi_library/axi_dmac/tb/axi_read_slave.v /^reg [DATA_WIDTH-1:0] data = 'h00;$/;" r module:axi_read_slave +data adi_library/common/ad_axis_inf_rx.v /^ input [(DATA_WIDTH-1):0] data,$/;" p module:ad_axis_inf_rx +data adi_library/common/ad_csc.v /^ input [ 23:0] data,$/;" p module:ad_csc +data adi_library/common/ad_datafmt.v /^ input [(DATA_WIDTH-1):0] data,$/;" p module:ad_datafmt +data adi_library/util_axis_fifo/util_axis_fifo.v /^ reg [DATA_WIDTH-1:0] data;$/;" r module:util_axis_fifo +data adi_library/util_axis_resize/util_axis_resize.v /^reg [MASTER_DATA_WIDTH-1:0] data;$/;" r module:util_axis_resize +data adi_library/util_axis_resize/util_axis_resize.v /^reg [SLAVE_DATA_WIDTH-1:0] data;$/;" r module:util_axis_resize +data adi_library/util_bsplit/util_bsplit.v /^ input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] data,$/;" p module:util_bsplit +data adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [TOTAL_DATA_WIDTH-1:0] data[0:2];$/;" n module:pack_shell +data adi_library/xilinx/common/ad_dcfilter.v /^ input [15:0] data,$/;" p module:ad_dcfilter +data_1 adi_library/common/ad_csc.v /^ reg signed [ MUL_DW:0] data_1;$/;" r module:ad_csc +data_1 hdl/TSync_Abs_new16.v /^ wire [10:0] data_1;$/;" n module:TSync_Abs_new16 +data_2 adi_library/common/ad_csc.v /^ reg signed [ MUL_DW:0] data_2;$/;" r module:ad_csc +data_2 hdl/TSync_Abs_new16.v /^ wire [10:0] data_2;$/;" n module:TSync_Abs_new16 +data_2d adi_library/xilinx/common/ad_dcfilter.v /^ reg [15:0] data_2d = 'd0;$/;" r module:ad_dcfilter +data_3 adi_library/common/ad_csc.v /^ reg signed [ MUL_DW:0] data_3;$/;" r module:ad_csc +data_3 hdl/TSync_Abs_new16.v /^ wire [10:0] data_3;$/;" n module:TSync_Abs_new16 +data_4 hdl/TSync_Abs_new16.v /^ wire [10:0] data_4;$/;" n module:TSync_Abs_new16 +data_Abs hdl/TSync_Abs_new4.v /^ wire [10:0] data_Abs;$/;" n module:TSync_Abs_new4 +data_a adi_library/xilinx/common/ad_mul.v /^ input [ A_DATA_WIDTH-1:0] data_a,$/;" p module:ad_mul +data_active adi_library/util_var_fifo/util_var_fifo.v /^ reg data_active = 'd0;$/;" r module:util_var_fifo +data_add_prefix_in hdl/enc_control.v /^ wire [ 1:0] data_add_prefix_in;$/;" n module:enc_control +data_add_prefix_in_ready hdl/enc_control.v /^ wire data_add_prefix_in_ready;$/;" n module:enc_control +data_add_prefix_out hdl/enc_control.v /^ wire [ 1:0] data_add_prefix_out;$/;" n module:enc_control +data_add_prefix_out_valid hdl/enc_control.v /^ wire data_add_prefix_out_valid;$/;" n module:enc_control +data_avg hdl/PAPR.v /^ wire [MAG_WIDTH-1:0] data_avg;$/;" n module:PAPR +data_b adi_library/xilinx/common/ad_mul.v /^ input [ B_DATA_WIDTH-1:0] data_b,$/;" p module:ad_mul +data_cmp adi_library/axi_dmac/tb/axi_write_slave.v /^reg [DATA_WIDTH-1:0] data_cmp = 'h00;$/;" r module:axi_write_slave +data_count hdl/DAGC_v2.v /^ wire [13:0] data_count;$/;" n module:DAGC_v2 +data_counter adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ reg [ 5:0] data_counter = 6'h0;$/;" r module:mdc_mdio +data_d adi_library/xilinx/common/ad_dcfilter.v /^ reg [15:0] data_d = 'd0;$/;" r module:ad_dcfilter +data_d1 adi_library/common/ad_csc.v /^ reg signed [ 23:0] data_d1;$/;" r module:ad_csc +data_d1 adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [DELAYED_DATA_WIDTH-1:0] data_d1 = 'h00;$/;" r block:pack_shell.gen_pack.gen_output_buffer +data_d1 adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [TOTAL_DATA_WIDTH-2*CHANNEL_DATA_WIDTH-1:0] data_d1 = 'h00;$/;" r block:pack_shell.gen_input_buffer +data_d2 adi_library/common/ad_csc.v /^ reg signed [ 23:0] data_d2;$/;" r module:ad_csc +data_dcfilt adi_library/xilinx/common/ad_dcfilter.v /^ reg [15:0] data_dcfilt = 'd0;$/;" r module:ad_dcfilter +data_delay adi_library/common/ad_dds_cordic_pipe.v /^ reg [DELAY_DW:1] data_delay = 'd0;$/;" r module:ad_dds_cordic_pipe +data_delay_in adi_library/common/ad_dds_cordic_pipe.v /^ input [DELAY_DW:1] data_delay_in,$/;" p module:ad_dds_cordic_pipe +data_delay_out adi_library/common/ad_dds_cordic_pipe.v /^ output [DELAY_DW:1] data_delay_out);$/;" p module:ad_dds_cordic_pipe +data_en adi_library/common/util_dec256sinc24b.v /^ output reg data_en,$/;" p module:util_dec256sinc24b +data_enabled adi_library/axi_dmac/dest_axi_stream.v /^reg data_enabled = 1'b0;$/;" r module:dmac_dest_axi_stream +data_eot adi_library/axi_dmac/dest_axi_stream.v /^ input data_eot,$/;" p module:dmac_dest_axi_stream +data_eot adi_library/axi_dmac/dest_fifo_inf.v /^ input data_eot,$/;" p module:dmac_dest_fifo_inf +data_eot adi_library/axi_dmac/request_arb.v /^wire data_eot = eot_mem_dest[data_id];$/;" n module:dmac_request_arb +data_equalizer hdl/data_equalizer.v /^module data_equalizer($/;" m +data_equalizer_djy hdl/SC_FDE_TOP.v /^ data_equalizer data_equalizer_djy ($/;" i module:SC_FDE_TOP typeref:module:data_equalizer +data_i hdl/frame_sync.v /^ input [11:0] data_i,$/;" p module:frame_sync +data_i hdl/power_measure.v /^ input wire [11:0] data_i,$/;" p module:power_measure +data_i_abs hdl/power_measure.v /^ reg [11:0] data_i_abs;$/;" r module:power_measure +data_i_reg hdl/frame_sync.v /^ reg [ 9:0] data_i_reg[511:0];$/;" r module:frame_sync +data_i_s adi_library/common/ad_iqcor.v /^ wire [CR-1:0] data_i_s;$/;" n block:ad_iqcor.g_loop +data_id adi_library/axi_dmac/dest_axi_stream.v /^ output [ID_WIDTH-1:0] data_id,$/;" p module:dmac_dest_axi_stream +data_id adi_library/axi_dmac/dest_fifo_inf.v /^ output reg [ID_WIDTH-1:0] data_id = 'h0,$/;" p module:dmac_dest_fifo_inf +data_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] data_id;$/;" n module:dmac_request_arb +data_id adi_library/axi_dmac/src_axi_mm.v /^ output [ID_WIDTH-1:0] data_id,$/;" p module:dmac_src_mm_axi +data_in adi_library/common/ad_iqcor.v /^ input [DPW*CR-1:0] data_in,$/;" p module:ad_iqcor +data_in adi_library/common/ad_perfect_shuffle.v /^ input [NUM_GROUPS*WORDS_PER_GROUP*WORD_WIDTH-1:0] data_in,$/;" p module:ad_perfect_shuffle +data_in adi_library/common/util_dec256sinc24b.v /^ input data_in, \/* input data to be filtered *\/$/;" p module:util_dec256sinc24b +data_in adi_library/util_cic/cic_comb.v /^ input [DATA_WIDTH-1:0] data_in,$/;" p module:cic_comb +data_in adi_library/util_cic/cic_int.v /^ input [DATA_WIDTH-1:0] data_in,$/;" p module:cic_int +data_in adi_library/util_extract/util_extract.v /^ input [DATA_WIDTH-1:0] data_in,$/;" p module:util_extract +data_in adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ reg [31:0] data_in = 32'h0;$/;" r module:mdc_mdio +data_in adi_library/util_pack/util_pack_common/pack_interconnect.v /^ input [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_in,$/;" p module:pack_interconnect +data_in adi_library/util_pack/util_pack_common/pack_network.v /^ input [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_in,$/;" p module:pack_network +data_in adi_library/util_var_fifo/util_var_fifo.v /^ input [DATA_WIDTH -1:0] data_in,$/;" p module:util_var_fifo +data_in hdl/add_prefix.v /^ input [WIDTH-1:0] data_in,$/;" p module:add_prefix +data_in hdl/width_convert.v /^ input wire [INPUT_WIDTH - 1 : 0] data_in,$/;" p module:width_convert +data_in sim/tb_add_prefix.v /^ reg [31:0] data_in = 0;$/;" r module:tb_add_prefix +data_in sim/tb_width_convert.v /^ reg [31:0] data_in;$/;" r module:tb_width_convert +data_in_0 adi_library/common/ad_bus_mux.v /^ input [DATA_WIDTH-1:0] data_in_0,$/;" p module:ad_bus_mux +data_in_1 adi_library/common/ad_bus_mux.v /^ input [DATA_WIDTH-1:0] data_in_1,$/;" p module:ad_bus_mux +data_in_d adi_library/common/ad_dds_sine_cordic.v /^ wire [ DELAY_DW-1:0] data_in_d [0:CORDIC_DW-1];$/;" n module:ad_dds_sine_cordic +data_in_d1 adi_library/util_var_fifo/util_var_fifo.v /^ reg [DATA_WIDTH-1:0] data_in_d1 = 'd0;$/;" r module:util_var_fifo +data_in_d2 adi_library/util_var_fifo/util_var_fifo.v /^ reg [DATA_WIDTH-1:0] data_in_d2 = 'd0;$/;" r module:util_var_fifo +data_in_d3 adi_library/util_var_fifo/util_var_fifo.v /^ reg [DATA_WIDTH-1:0] data_in_d3 = 'd0;$/;" r module:util_var_fifo +data_in_d4 adi_library/util_var_fifo/util_var_fifo.v /^ reg [DATA_WIDTH-1:0] data_in_d4 = 'd0;$/;" r module:util_var_fifo +data_in_ibuf_s adi_library/xilinx/common/ad_serdes_in.v /^ wire [(DATA_WIDTH-1):0] data_in_ibuf_s;$/;" n module:ad_serdes_in +data_in_idelay_s adi_library/xilinx/common/ad_serdes_in.v /^ wire [(DATA_WIDTH-1):0] data_in_idelay_s;$/;" n module:ad_serdes_in +data_in_latch hdl/width_convert.v /^ reg [ INPUT_WIDTH-1:0] data_in_latch;$/;" r module:width_convert +data_in_n adi_library/xilinx/common/ad_serdes_in.v /^ input [(DATA_WIDTH-1):0] data_in_n,$/;" p module:ad_serdes_in +data_in_p adi_library/xilinx/common/ad_serdes_in.v /^ input [(DATA_WIDTH-1):0] data_in_p,$/;" p module:ad_serdes_in +data_in_r adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ reg [31:0] data_in_r = 32'h0;$/;" r module:mdc_mdio +data_in_ready hdl/add_prefix.v /^ output reg data_in_ready,$/;" p module:add_prefix +data_in_ready hdl/width_convert.v /^ input wire data_in_ready,$/;" p module:width_convert +data_in_ready sim/tb_width_convert.v /^ wire data_in_ready;$/;" n module:tb_width_convert +data_in_seq adi_library/util_cic/cic_comb.v /^reg [DATA_WIDTH-1:0] data_in_seq;$/;" r module:cic_comb +data_in_trigger adi_library/util_extract/util_extract.v /^ input [DATA_WIDTH-1:0] data_in_trigger,$/;" p module:util_extract +data_in_valid adi_library/util_var_fifo/util_var_fifo.v /^ input data_in_valid,$/;" p module:util_var_fifo +data_in_valid hdl/width_convert.v /^ input data_in_valid,$/;" p module:width_convert +data_in_valid sim/tb_width_convert.v /^ reg data_in_valid;$/;" r module:tb_width_convert +data_in_valid_d1 adi_library/util_var_fifo/util_var_fifo.v /^ reg data_in_valid_d1 = 'd0;$/;" r module:util_var_fifo +data_in_valid_d2 adi_library/util_var_fifo/util_var_fifo.v /^ reg data_in_valid_d2 = 'd0;$/;" r module:util_var_fifo +data_int adi_library/common/ad_datafmt.v /^ reg [(8*OCTETS_PER_SAMPLE-1):0] data_int = 'd0;$/;" r module:ad_datafmt +data_int adi_library/common/ad_iqcor.v /^ reg [CR-1:0] data_int = 'd0;$/;" r block:ad_iqcor.g_loop +data_int adi_library/common/util_dec256sinc24b.v /^ reg [36:0] data_int = 37'h0;$/;" r module:util_dec256sinc24b +data_int adi_library/xilinx/common/ad_dcfilter.v /^ reg [15:0] data_int = 'd0;$/;" r module:ad_dcfilter +data_int_loc adi_library/common/ad_iqcor.v /^ wire [DPW*CR-1:0] data_int_loc;$/;" n module:ad_iqcor +data_iq adi_library/common/ad_iqcor.v /^ input [DPW*CR-1:0] data_iq,$/;" p module:ad_iqcor +data_net_byte hdl/FrameMerge.v /^ reg [7:0] data_net_byte [87:0];$/;" r module:FrameMerge +data_oe adi_library/xilinx/common/ad_serdes_out.v /^ input data_oe,$/;" p module:ad_serdes_out +data_out adi_library/common/ad_bus_mux.v /^ output [DATA_WIDTH-1:0] data_out);$/;" p module:ad_bus_mux +data_out adi_library/common/ad_datafmt.v /^ output [(8*OCTETS_PER_SAMPLE-1):0] data_out,$/;" p module:ad_datafmt +data_out adi_library/common/ad_iqcor.v /^ output [DPW*CR-1:0] data_out,$/;" p module:ad_iqcor +data_out adi_library/common/ad_perfect_shuffle.v /^ output [NUM_GROUPS*WORDS_PER_GROUP*WORD_WIDTH-1:0] data_out$/;" p module:ad_perfect_shuffle +data_out adi_library/common/util_dec256sinc24b.v /^ output reg [15:0] data_out, \/* filtered output *\/$/;" p module:util_dec256sinc24b +data_out adi_library/util_cic/cic_comb.v /^ output [DATA_WIDTH-1:0] data_out$/;" p module:cic_comb +data_out adi_library/util_cic/cic_int.v /^ output [DATA_WIDTH-1:0] data_out$/;" p module:cic_int +data_out adi_library/util_extract/util_extract.v /^ output [DATA_WIDTH-1:0] data_out,$/;" p module:util_extract +data_out adi_library/util_pack/util_pack_common/pack_interconnect.v /^ output [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_out$/;" p module:pack_interconnect +data_out adi_library/util_pack/util_pack_common/pack_network.v /^ output [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_out$/;" p module:pack_network +data_out adi_library/util_var_fifo/util_var_fifo.v /^ output [DATA_WIDTH-1:0] data_out,$/;" p module:util_var_fifo +data_out adi_library/xilinx/common/ad_dcfilter.v /^ output [15:0] data_out,$/;" p module:ad_dcfilter +data_out hdl/add_prefix.v /^ output reg [WIDTH-1:0] data_out,$/;" p module:add_prefix +data_out hdl/width_convert.v /^ output reg [OUTPUT_WIDTH -1 : 0] data_out$/;" p module:width_convert +data_out sim/tb_add_prefix.v /^ wire [31:0] data_out;$/;" n module:tb_add_prefix +data_out sim/tb_width_convert.v /^ wire [ 0:0] data_out;$/;" n module:tb_width_convert +data_out_d1 adi_library/util_var_fifo/util_var_fifo.v /^ reg [DATA_WIDTH-1:0] data_out_d1 = 'd0;$/;" r module:util_var_fifo +data_out_d2 adi_library/util_var_fifo/util_var_fifo.v /^ reg [DATA_WIDTH-1:0] data_out_d2 = 'd0;$/;" r module:util_var_fifo +data_out_d3 adi_library/util_var_fifo/util_var_fifo.v /^ reg [DATA_WIDTH-1:0] data_out_d3 = 'd0;$/;" r module:util_var_fifo +data_out_n adi_library/xilinx/common/ad_serdes_out.v /^ output [(DATA_WIDTH-1):0] data_out_n);$/;" p module:ad_serdes_out +data_out_p adi_library/xilinx/common/ad_serdes_out.v /^ output [(DATA_WIDTH-1):0] data_out_p,$/;" p module:ad_serdes_out +data_out_s adi_library/common/ad_datafmt.v /^ wire [(8*OCTETS_PER_SAMPLE-1):0] data_out_s;$/;" n module:ad_datafmt +data_out_s adi_library/common/util_axis_upscale.v /^ wire [(NUM_OF_CHANNELS*UDATA_WIDTH)-1:0] data_out_s;$/;" n module:util_axis_upscale +data_out_s adi_library/util_var_fifo/util_var_fifo.v /^ wire [DATA_WIDTH-1:0] data_out_s;$/;" n module:util_var_fifo +data_out_s adi_library/xilinx/common/ad_serdes_out.v /^ wire [(DATA_WIDTH-1):0] data_out_s;$/;" n module:ad_serdes_out +data_out_se adi_library/xilinx/common/ad_serdes_out.v /^ output [(DATA_WIDTH-1):0] data_out_se,$/;" p module:ad_serdes_out +data_out_valid adi_library/util_var_fifo/util_var_fifo.v /^ output data_out_valid,$/;" p module:util_var_fifo +data_out_valid hdl/add_prefix.v /^ output reg data_out_valid$/;" p module:add_prefix +data_out_valid hdl/width_convert.v /^ output reg data_out_valid,$/;" p module:width_convert +data_out_valid sim/tb_add_prefix.v /^ wire data_out_valid;$/;" n module:tb_add_prefix +data_out_valid sim/tb_width_convert.v /^ wire data_out_valid;$/;" n module:tb_width_convert +data_out_valid_s adi_library/util_var_fifo/util_var_fifo.v /^ wire data_out_valid_s;$/;" n module:util_var_fifo +data_ow hdl/data_ow.v /^module data_ow($/;" m +data_ow_djy hdl/SC_FDE_TOP.v /^ data_ow data_ow_djy ($/;" i module:SC_FDE_TOP typeref:module:data_ow +data_p adi_library/xilinx/common/ad_mul.v /^ output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p,$/;" p module:ad_mul +data_q hdl/frame_sync.v /^ input [11:0] data_q,$/;" p module:frame_sync +data_q hdl/power_measure.v /^ input wire [11:0] data_q,$/;" p module:power_measure +data_q_abs hdl/power_measure.v /^ reg [11:0] data_q_abs;$/;" r module:power_measure +data_q_s adi_library/common/ad_iqcor.v /^ wire [CR-1:0] data_q_s;$/;" n block:ad_iqcor.g_loop +data_rd_en adi_library/util_pack/util_upack2/util_upack2_impl.v /^ wire data_rd_en;$/;" n module:util_upack2_impl +data_ready adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ output reg data_ready);$/;" p module:util_sigma_delta_spi +data_s adi_library/util_bsplit/util_bsplit.v /^ wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] data_s;$/;" n module:util_bsplit +data_s0 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s0, \/\/ last bit received$/;" p module:ad_serdes_in +data_s0 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s0, \/\/ 1st bit to be transmitted$/;" p module:ad_serdes_out +data_s1 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s1,$/;" p module:ad_serdes_in +data_s1 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s1,$/;" p module:ad_serdes_out +data_s2 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s2,$/;" p module:ad_serdes_in +data_s2 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s2,$/;" p module:ad_serdes_out +data_s3 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s3,$/;" p module:ad_serdes_in +data_s3 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s3,$/;" p module:ad_serdes_out +data_s4 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s4,$/;" p module:ad_serdes_in +data_s4 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s4,$/;" p module:ad_serdes_out +data_s5 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s5,$/;" p module:ad_serdes_in +data_s5 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s5,$/;" p module:ad_serdes_out +data_s6 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s6,$/;" p module:ad_serdes_in +data_s6 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s6,$/;" p module:ad_serdes_out +data_s7 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s7, \/\/ 1st bit received$/;" p module:ad_serdes_in +data_s7 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s7, \/\/ last bit to be transmitted$/;" p module:ad_serdes_out +data_save hdl/RecvTop.v /^ wire data_save; \/\/debug用，暂不需使用$/;" n module:RecvTop +data_save hdl/freqestm.v /^ output reg data_save,$/;" p module:freqestm +data_sdi_shift adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ reg [DATA_WIDTH-1:0] data_sdi_shift;$/;" r block:spi_engine_execution.g_sdi_shift_reg +data_sdo_shift adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;$/;" r module:spi_engine_execution +data_shift1_s adi_library/xilinx/common/ad_serdes_in.v /^ wire [(DATA_WIDTH-1):0] data_shift1_s;$/;" n module:ad_serdes_in +data_shift2_s adi_library/xilinx/common/ad_serdes_in.v /^ wire [(DATA_WIDTH-1):0] data_shift2_s;$/;" n module:ad_serdes_in +data_src_count hdl/enc_control.v /^ input [ 31:0] data_src_count,$/;" p module:enc_control +data_src_count sim/tb_enc_control.v /^ reg [31:0] data_src_count;$/;" r module:tb_enc_control +data_sum hdl/PAPR.v /^ reg [SUM_WIDTH-1:0] data_sum;$/;" r module:PAPR +data_t adi_library/xilinx/common/ad_serdes_out.v /^ wire [(DATA_WIDTH-1):0] data_t;$/;" n module:ad_serdes_out +data_tx_test hdl/Transmitter.v /^ wire [7:0] data_tx_test;$/;" n module:Transmitter +data_valid adi_library/util_extract/util_extract.v /^ input data_valid,$/;" p module:util_extract +data_wr_en adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ wire data_wr_en = fifo_wr_en[0];$/;" n module:util_cpack2_impl +dataa_x adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) input [ D_DW-1:0] dataa_x,$/;" p module:ad_dds_cordic_pipe +dataa_y adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) input [ D_DW-1:0] dataa_y,$/;" p module:ad_dds_cordic_pipe +dataa_z adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) input [ P_DW-1:0] dataa_z,$/;" p module:ad_dds_cordic_pipe +datab_z adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) input [ P_DW-1:0] datab_z,$/;" p module:ad_dds_cordic_pipe +datain1_i hdl/TSync_Abs_new16.v /^ input [9:0] datain1_i,$/;" p module:TSync_Abs_new16 +datain1_q hdl/TSync_Abs_new16.v /^ input [9:0] datain1_q,$/;" p module:TSync_Abs_new16 +datain2_i hdl/TSync_Abs_new16.v /^ input [9:0] datain2_i,$/;" p module:TSync_Abs_new16 +datain2_q hdl/TSync_Abs_new16.v /^ input [9:0] datain2_q,$/;" p module:TSync_Abs_new16 +datain3_i hdl/TSync_Abs_new16.v /^ input [9:0] datain3_i,$/;" p module:TSync_Abs_new16 +datain3_q hdl/TSync_Abs_new16.v /^ input [9:0] datain3_q,$/;" p module:TSync_Abs_new16 +datain4_i hdl/TSync_Abs_new16.v /^ input [9:0] datain4_i,$/;" p module:TSync_Abs_new16 +datain4_q hdl/TSync_Abs_new16.v /^ input [9:0] datain4_q,$/;" p module:TSync_Abs_new16 +datain_01 hdl/freqestm.v /^ wire [19:0] datain_01;$/;" n module:freqestm +datain_02 hdl/freqestm.v /^ wire [19:0] datain_02;$/;" n module:freqestm +datain_03 hdl/freqestm.v /^ wire [19:0] datain_03;$/;" n module:freqestm +datain_i hdl/SCFDE_recv_FrameSync.v /^ input [9:0] datain_i,$/;" p module:SCFDE_recv_FrameSync +datain_i hdl/freqestm.v /^ input [9:0] datain_i,$/;" p module:freqestm +datain_i_d1 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_i_d1;$/;" r module:SCFDE_recv_FrameSync +datain_i_d2 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_i_d2;$/;" r module:SCFDE_recv_FrameSync +datain_i_d3 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_i_d3;$/;" r module:SCFDE_recv_FrameSync +datain_i_d4 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_i_d4;$/;" r module:SCFDE_recv_FrameSync +datain_i_d5 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_i_d5;$/;" r module:SCFDE_recv_FrameSync +datain_i_d6 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_i_d6;$/;" r module:SCFDE_recv_FrameSync +datain_i_d7 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_i_d7;$/;" r module:SCFDE_recv_FrameSync +datain_i_d8 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_i_d8;$/;" r module:SCFDE_recv_FrameSync +datain_i_d9 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_i_d9;$/;" r module:SCFDE_recv_FrameSync +datain_q hdl/SCFDE_recv_FrameSync.v /^ input [9:0] datain_q,$/;" p module:SCFDE_recv_FrameSync +datain_q hdl/freqestm.v /^ input [9:0] datain_q,$/;" p module:freqestm +datain_q_d1 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_q_d1;$/;" r module:SCFDE_recv_FrameSync +datain_q_d2 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_q_d2;$/;" r module:SCFDE_recv_FrameSync +datain_q_d3 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_q_d3;$/;" r module:SCFDE_recv_FrameSync +datain_q_d4 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_q_d4;$/;" r module:SCFDE_recv_FrameSync +datain_q_d5 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_q_d5;$/;" r module:SCFDE_recv_FrameSync +datain_q_d6 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_q_d6;$/;" r module:SCFDE_recv_FrameSync +datain_q_d7 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_q_d7;$/;" r module:SCFDE_recv_FrameSync +datain_q_d8 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_q_d8;$/;" r module:SCFDE_recv_FrameSync +datain_q_d9 hdl/SCFDE_recv_FrameSync.v /^ reg [9:0] datain_q_d9;$/;" r module:SCFDE_recv_FrameSync +dataini hdl/TSync_Abs_new4.v /^ input [9:0] dataini,$/;" p module:TSync_Abs_new4 +datainq hdl/TSync_Abs_new4.v /^ input [9:0] datainq,$/;" p module:TSync_Abs_new4 +dataout_16 hdl/freqestm.v /^ wire [19:0] dataout_16;$/;" n module:freqestm +dataout_i hdl/SCFDE_recv_FrameSync.v /^ wire [ 9:0] dataout_i;$/;" n module:SCFDE_recv_FrameSync +dataout_i hdl/freqestm.v /^ output reg [9:0] dataout_i,$/;" p module:freqestm +dataout_q hdl/SCFDE_recv_FrameSync.v /^ wire [9:0] dataout_q;$/;" n module:SCFDE_recv_FrameSync +dataout_q hdl/freqestm.v /^ output reg [9:0] dataout_q,$/;" p module:freqestm +dbg_dest_addr adi_library/axi_dmac/axi_dmac_regmap.v /^ input [DMA_AXI_ADDR_WIDTH-1:0] dbg_dest_addr,$/;" p module:axi_dmac_regmap +dbg_dest_address_id adi_library/axi_dmac/axi_dmac_transfer.v /^ output [ID_WIDTH-1:0] dbg_dest_address_id,$/;" p module:axi_dmac_transfer +dbg_dest_address_id adi_library/axi_dmac/request_arb.v /^ output [ID_WIDTH-1:0] dbg_dest_address_id,$/;" p module:dmac_request_arb +dbg_dest_data_id adi_library/axi_dmac/axi_dmac_transfer.v /^ output [ID_WIDTH-1:0] dbg_dest_data_id,$/;" p module:axi_dmac_transfer +dbg_dest_data_id adi_library/axi_dmac/request_arb.v /^ output [ID_WIDTH-1:0] dbg_dest_data_id,$/;" p module:dmac_request_arb +dbg_dest_request_id adi_library/axi_dmac/axi_dmac_transfer.v /^ output [ID_WIDTH-1:0] dbg_dest_request_id,$/;" p module:axi_dmac_transfer +dbg_dest_request_id adi_library/axi_dmac/request_arb.v /^ output [ID_WIDTH-1:0] dbg_dest_request_id,$/;" p module:dmac_request_arb +dbg_dest_response_id adi_library/axi_dmac/axi_dmac_transfer.v /^ output [ID_WIDTH-1:0] dbg_dest_response_id,$/;" p module:axi_dmac_transfer +dbg_dest_response_id adi_library/axi_dmac/request_arb.v /^ output [ID_WIDTH-1:0] dbg_dest_response_id,$/;" p module:dmac_request_arb +dbg_ids0 adi_library/axi_dmac/axi_dmac.v /^wire [31:0] dbg_ids0;$/;" n module:axi_dmac +dbg_ids0 adi_library/axi_dmac/axi_dmac_regmap.v /^ input [31:0] dbg_ids0,$/;" p module:axi_dmac_regmap +dbg_ids1 adi_library/axi_dmac/axi_dmac.v /^wire [31:0] dbg_ids1;$/;" n module:axi_dmac +dbg_ids1 adi_library/axi_dmac/axi_dmac_regmap.v /^ input [31:0] dbg_ids1$/;" p module:axi_dmac_regmap +dbg_src_addr adi_library/axi_dmac/axi_dmac_regmap.v /^ input [DMA_AXI_ADDR_WIDTH-1:0] dbg_src_addr,$/;" p module:axi_dmac_regmap +dbg_src_address_id adi_library/axi_dmac/axi_dmac_transfer.v /^ output [ID_WIDTH-1:0] dbg_src_address_id,$/;" p module:axi_dmac_transfer +dbg_src_address_id adi_library/axi_dmac/request_arb.v /^ output [ID_WIDTH-1:0] dbg_src_address_id,$/;" p module:dmac_request_arb +dbg_src_data_id adi_library/axi_dmac/axi_dmac_transfer.v /^ output [ID_WIDTH-1:0] dbg_src_data_id,$/;" p module:axi_dmac_transfer +dbg_src_data_id adi_library/axi_dmac/request_arb.v /^ output [ID_WIDTH-1:0] dbg_src_data_id,$/;" p module:dmac_request_arb +dbg_src_request_id adi_library/axi_dmac/axi_dmac_transfer.v /^ output [ID_WIDTH-1:0] dbg_src_request_id,$/;" p module:axi_dmac_transfer +dbg_src_request_id adi_library/axi_dmac/request_arb.v /^ output [ID_WIDTH-1:0] dbg_src_request_id,$/;" p module:dmac_request_arb +dbg_src_response_id adi_library/axi_dmac/axi_dmac_transfer.v /^ output [ID_WIDTH-1:0] dbg_src_response_id,$/;" p module:axi_dmac_transfer +dbg_src_response_id adi_library/axi_dmac/request_arb.v /^ output [ID_WIDTH-1:0] dbg_src_response_id,$/;" p module:dmac_request_arb +dbg_status adi_library/axi_dmac/axi_dmac.v /^wire [11:0] dbg_status;$/;" n module:axi_dmac +dbg_status adi_library/axi_dmac/axi_dmac_regmap.v /^ input [11:0] dbg_status,$/;" p module:axi_dmac_regmap +dbg_status adi_library/axi_dmac/axi_dmac_reset_manager.v /^ output [11:0] dbg_status$/;" p module:axi_dmac_reset_manager +dbg_status adi_library/axi_dmac/axi_dmac_transfer.v /^ output [11:0] dbg_status,$/;" p module:axi_dmac_transfer +dbg_status adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [11:0] dbg_status;$/;" n module:dmac_dma_read_shutdown_tb +dbg_status adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire [11:0] dbg_status;$/;" n module:dmac_dma_write_shutdown_tb +dbuf adi_library/common/util_delay.v /^ reg [DATA_WIDTH-1:0] dbuf[0:(DELAY_CYCLES-1)];$/;" r module:util_delay +dc_offset adi_library/xilinx/common/ad_dcfilter.v /^ reg [47:0] dc_offset = 'd0;$/;" r module:ad_dcfilter +dc_offset_d adi_library/xilinx/common/ad_dcfilter.v /^ reg [47:0] dc_offset_d = 'd0;$/;" r module:ad_dcfilter +dc_offset_s adi_library/xilinx/common/ad_dcfilter.v /^ wire [47:0] dc_offset_s;$/;" n module:ad_dcfilter +dc_removal_dout_i hdl/RecvTop.v /^ output [11:0] dc_removal_dout_i, \/\/MGC_adaptation、去直流输出$/;" p module:RecvTop +dc_removal_dout_q hdl/RecvTop.v /^ output [11:0] dc_removal_dout_q,$/;" p module:RecvTop +dc_value_i hdl/RecvTop.v /^ output [11:0] dc_value_i,$/;" p module:RecvTop +dc_value_q hdl/RecvTop.v /^ output [11:0] dc_value_q,$/;" p module:RecvTop +dcfilt_coeff adi_library/xilinx/common/ad_dcfilter.v /^ input [15:0] dcfilt_coeff,$/;" p module:ad_dcfilter +dcfilt_coeff_d adi_library/xilinx/common/ad_dcfilter.v /^ reg [15:0] dcfilt_coeff_d = 'd0;$/;" r module:ad_dcfilter +dcfilt_enb adi_library/xilinx/common/ad_dcfilter.v /^ input dcfilt_enb,$/;" p module:ad_dcfilter +dcfilt_offset adi_library/xilinx/common/ad_dcfilter.v /^ input [15:0] dcfilt_offset);$/;" p module:ad_dcfilter +ddata_in adi_library/common/ad_dds_sine.v /^ input [(DELAY_DATA_WIDTH-1):0] ddata_in,$/;" p module:ad_dds_sine +ddata_in adi_library/common/ad_dds_sine_cordic.v /^ input [ DELAY_DW-1:0] ddata_in,$/;" p module:ad_dds_sine_cordic +ddata_in adi_library/xilinx/common/ad_mul.v /^ input [(DELAY_DATA_WIDTH-1):0] ddata_in,$/;" p module:ad_mul +ddata_out adi_library/common/ad_dds_sine.v /^ output [(DELAY_DATA_WIDTH-1):0] ddata_out);$/;" p module:ad_dds_sine +ddata_out adi_library/common/ad_dds_sine_cordic.v /^ output reg [ DELAY_DW-1:0] ddata_out);$/;" p module:ad_dds_sine_cordic +ddata_out adi_library/xilinx/common/ad_mul.v /^ output reg [(DELAY_DATA_WIDTH-1):0] ddata_out);$/;" p module:ad_mul +ddata_out_int adi_library/common/ad_dds_sine.v /^ reg [(DELAY_DATA_WIDTH-1):0] ddata_out_int = 'd0;$/;" r module:ad_dds_sine +ddr_addr hdl/system_top.v /^ inout [14:0] ddr_addr,$/;" p module:system_top +ddr_ba hdl/system_top.v /^ inout [ 2:0] ddr_ba,$/;" p module:system_top +ddr_cas_n hdl/system_top.v /^ inout ddr_cas_n,$/;" p module:system_top +ddr_ck_n hdl/system_top.v /^ inout ddr_ck_n,$/;" p module:system_top +ddr_ck_p hdl/system_top.v /^ inout ddr_ck_p,$/;" p module:system_top +ddr_cke hdl/system_top.v /^ inout ddr_cke,$/;" p module:system_top +ddr_cs_n hdl/system_top.v /^ inout ddr_cs_n,$/;" p module:system_top +ddr_dm hdl/system_top.v /^ inout [ 3:0] ddr_dm,$/;" p module:system_top +ddr_dq hdl/system_top.v /^ inout [31:0] ddr_dq,$/;" p module:system_top +ddr_dqs_n hdl/system_top.v /^ inout [ 3:0] ddr_dqs_n,$/;" p module:system_top +ddr_dqs_p hdl/system_top.v /^ inout [ 3:0] ddr_dqs_p,$/;" p module:system_top +ddr_odt hdl/system_top.v /^ inout ddr_odt,$/;" p module:system_top +ddr_ras_n hdl/system_top.v /^ inout ddr_ras_n,$/;" p module:system_top +ddr_reset_n hdl/system_top.v /^ inout ddr_reset_n,$/;" p module:system_top +ddr_we_n hdl/system_top.v /^ inout ddr_we_n,$/;" p module:system_top +dds_data adi_library/common/ad_dds_1.v /^ output reg [DDS_D_DW-1:0] dds_data);$/;" p module:ad_dds_1 +dds_data adi_library/common/ad_dds_2.v /^ output [ DDS_DW-1:0] dds_data);$/;" p module:ad_dds_2 +dds_data_0_s adi_library/common/ad_dds_2.v /^ wire [DDS_D_DW-1:0] dds_data_0_s;$/;" n module:ad_dds_2 +dds_data_1_s adi_library/common/ad_dds_2.v /^ wire [DDS_D_DW-1:0] dds_data_1_s;$/;" n module:ad_dds_2 +dds_data_int adi_library/common/ad_dds_2.v /^ reg [DDS_D_DW-1:0] dds_data_int = 0;$/;" r module:ad_dds_2 +dds_data_out adi_library/common/ad_dds_2.v /^ reg [ DDS_DW-1:0] dds_data_out = 0;$/;" r module:ad_dds_2 +dds_data_rownd adi_library/common/ad_dds_2.v /^ reg [DDS_D_DW-1:0] dds_data_rownd = 0;$/;" r module:ad_dds_2 +dds_data_width adi_library/common/ad_dds_2.v /^ reg [ DDS_DW-1:0] dds_data_width = 0;$/;" r module:ad_dds_2 +dds_format adi_library/common/ad_dds_2.v /^ input dds_format,$/;" p module:ad_dds_2 +dds_freq hdl/DDS_compensate.v /^ reg [DDS_width:0] dds_freq = 0; \/\/ 相位累积量，残余频偏和变化率控制$/;" r module:DDS_compensate +dds_phase adi_library/common/ad_dds.v /^ for (i=1; i <= CLK_RATIO; i=i+1) begin: dds_phase$/;" b module:ad_dds +dds_phase hdl/DDS_compensate.v /^ reg [DDS_width:0] dds_phase = 0;$/;" r module:DDS_compensate +dds_phase_0 adi_library/common/ad_dds_2.v /^ input [PHASE_DW-1:0] dds_phase_0,$/;" p module:ad_dds_2 +dds_phase_0_s adi_library/common/ad_dds_2.v /^ wire [DDS_P_DW-1:0] dds_phase_0_s;$/;" n module:ad_dds_2 +dds_phase_1 adi_library/common/ad_dds_2.v /^ input [PHASE_DW-1:0] dds_phase_1,$/;" p module:ad_dds_2 +dds_phase_1_s adi_library/common/ad_dds_2.v /^ wire [DDS_P_DW-1:0] dds_phase_1_s;$/;" n module:ad_dds_2 +dds_rst hdl/DDS_compensate.v /^ reg dds_rst = 0; \/\/ DDS starts after acquisition$/;" r module:DDS_compensate +dds_scale_0 adi_library/common/ad_dds_2.v /^ input [ 15:0] dds_scale_0,$/;" p module:ad_dds_2 +dds_scale_0_d adi_library/common/ad_dds_2.v /^ reg [ 15:0] dds_scale_0_d = 0;$/;" r module:ad_dds_2 +dds_scale_1 adi_library/common/ad_dds_2.v /^ input [ 15:0] dds_scale_1,$/;" p module:ad_dds_2 +dds_scale_1_d adi_library/common/ad_dds_2.v /^ reg [ 15:0] dds_scale_1_d = 0;$/;" r module:ad_dds_2 +dds_start_freq hdl/DDS_compensate.v /^ reg [DDS_width:0] dds_start_freq = 0;$/;" r module:DDS_compensate +dds_update hdl/DDS_compensate.v /^ reg dds_update = 0; \/\/ identifier of updated deltafrequency & its rate$/;" r module:DDS_compensate +dds_update_d1 hdl/DDS_compensate.v /^ reg dds_update_d1 = 0,dds_update_d2 = 0;$/;" r module:DDS_compensate +dds_update_d2 hdl/DDS_compensate.v /^ reg dds_update_d1 = 0,dds_update_d2 = 0;$/;" r module:DDS_compensate +dds_update_df hdl/DDS_compensate.v /^ reg [DDS_width:0] dds_update_df = 0;$/;" r module:DDS_compensate +debug_loss hdl/RecvTop.v /^ input debug_loss$/;" p module:RecvTop +debug_loss hdl/SCFDE_recv_FrameSync.v /^ input debug_loss,$/;" p module:SCFDE_recv_FrameSync +dec_pulse hdl/ad9361_mgc_pin_ctrl.v /^ wire dec_pulse;$/;" n module:ad9361_mgc_pin_ctrl +dec_rate adi_library/common/util_dec256sinc24b.v /^ input [15:0] dec_rate);$/;" p module:util_dec256sinc24b +decimate adi_library/util_fir_dec/util_fir_dec.v /^ input decimate,$/;" p module:util_fir_dec +decimator adi_library/util_fir_dec/util_fir_dec.v /^ fir_decim decimator ($/;" i module:util_fir_dec typeref:module:fir_decim +deinterleaved_data adi_library/util_pack/util_upack2/util_upack2_impl.v /^ wire [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] deinterleaved_data;$/;" n module:util_upack2_impl +delay_clk adi_library/common/up_delay_cntrl.v /^ input delay_clk,$/;" p module:up_delay_cntrl +delay_clk adi_library/xilinx/common/ad_data_in.v /^ input delay_clk,$/;" p module:ad_data_in +delay_clk adi_library/xilinx/common/ad_data_out.v /^ input delay_clk,$/;" p module:ad_data_out +delay_clk adi_library/xilinx/common/ad_serdes_in.v /^ input delay_clk,$/;" p module:ad_serdes_in +delay_locked adi_library/common/up_delay_cntrl.v /^ input delay_locked,$/;" p module:up_delay_cntrl +delay_locked adi_library/xilinx/common/ad_data_in.v /^ output delay_locked);$/;" p module:ad_data_in +delay_locked adi_library/xilinx/common/ad_data_out.v /^ output delay_locked);$/;" p module:ad_data_out +delay_locked adi_library/xilinx/common/ad_serdes_in.v /^ output delay_locked);$/;" p module:ad_serdes_in +delay_rgmii_rd adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) delay_rgmii_rd ($/;" i module:util_gmii_to_rgmii typeref:module:IDELAYE2 +delay_rgmii_rx_ctl adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) delay_rgmii_rx_ctl ($/;" i module:util_gmii_to_rgmii typeref:module:IDELAYE2 +delay_rst adi_library/common/up_delay_cntrl.v /^ output delay_rst,$/;" p module:up_delay_cntrl +delay_rst adi_library/xilinx/common/ad_data_in.v /^ input delay_rst,$/;" p module:ad_data_in +delay_rst adi_library/xilinx/common/ad_data_out.v /^ input delay_rst,$/;" p module:ad_data_out +delay_rst adi_library/xilinx/common/ad_serdes_in.v /^ input delay_rst,$/;" p module:ad_serdes_in +delay_rst_s adi_library/common/up_delay_cntrl.v /^ wire delay_rst_s;$/;" n module:up_delay_cntrl +demod_i hdl/DDS_compensate.v /^ wire [24:0] demod_i,demod_q;$/;" n module:DDS_compensate +demod_nd hdl/DDS_compensate.v /^ wire demod_nd; \/\/排除第一个，这两个信号和din_nd是同步的$/;" n module:DDS_compensate +demod_q hdl/DDS_compensate.v /^ wire [24:0] demod_i,demod_q;$/;" n module:DDS_compensate +demod_trunc_i hdl/DDS_compensate.v /^ output [11:0] demod_trunc_i,demod_trunc_q;$/;" p module:DDS_compensate +demod_trunc_nd hdl/DDS_compensate.v /^ output demod_trunc_nd ;$/;" p module:DDS_compensate +demod_trunc_q hdl/DDS_compensate.v /^ output [11:0] demod_trunc_i,demod_trunc_q;$/;" p module:DDS_compensate +demux_gen_inner adi_library/util_pack/util_pack_common/pack_ctrl.v /^ for (k = 0; k < z; k = k + 1) begin: demux_gen_inner$/;" b block:pack_ctrl.demux_gen_outer +demux_gen_outer adi_library/util_pack/util_pack_common/pack_ctrl.v /^ for (i = 0; i < NUM_STAGES*NUM_OF_PORTS; i = i + z) begin: demux_gen_outer$/;" b module:pack_ctrl +depth adi_library/util_var_fifo/util_var_fifo.v /^ input [31:0] depth,$/;" p module:util_var_fifo +depth_d1 adi_library/util_var_fifo/util_var_fifo.v /^ reg [31:0] depth_d1 = 'd0;$/;" r module:util_var_fifo +dest_address adi_library/axi_dmac/2d_transfer.v /^reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dest_address = 'h00;$/;" r module:dmac_2d_transfer +dest_address_eot adi_library/axi_dmac/request_arb.v /^wire dest_address_eot = eot_mem_dest[dest_address_id];$/;" n module:dmac_request_arb +dest_address_id adi_library/axi_dmac/axi_dmac.v /^wire [ID_WIDTH-1:0] dest_address_id;$/;" n module:axi_dmac +dest_address_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] dest_address_id;$/;" n module:dmac_request_arb +dest_beat adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire dest_beat;$/;" n module:axi_dmac_burst_memory +dest_beat_counter adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg [BURST_LEN_WIDTH_DEST-1:0] dest_beat_counter = 'h00;$/;" r module:axi_dmac_burst_memory +dest_bl_ready adi_library/axi_dmac/request_arb.v /^wire dest_bl_ready;$/;" n module:dmac_request_arb +dest_bl_valid adi_library/axi_dmac/request_arb.v /^wire dest_bl_valid;$/;" n module:dmac_request_arb +dest_burst_info_id adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output [ID_WIDTH-1:0] dest_burst_info_id,$/;" p module:axi_dmac_burst_memory +dest_burst_info_id adi_library/axi_dmac/dest_axi_mm.v /^ input [ID_WIDTH-1:0] dest_burst_info_id,$/;" p module:dmac_dest_mm_axi +dest_burst_info_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] dest_burst_info_id;$/;" n module:dmac_request_arb +dest_burst_info_length adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length,$/;" p module:axi_dmac_burst_memory +dest_burst_info_length adi_library/axi_dmac/dest_axi_mm.v /^ input [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length,$/;" p module:dmac_dest_mm_axi +dest_burst_info_length adi_library/axi_dmac/request_arb.v /^wire [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length;$/;" n module:dmac_request_arb +dest_burst_info_partial adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output dest_burst_info_partial,$/;" p module:axi_dmac_burst_memory +dest_burst_info_partial adi_library/axi_dmac/dest_axi_mm.v /^ input dest_burst_info_partial,$/;" p module:dmac_dest_mm_axi +dest_burst_info_partial adi_library/axi_dmac/request_arb.v /^wire dest_burst_info_partial;$/;" n module:dmac_request_arb +dest_burst_info_write adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output reg dest_burst_info_write = 1'b0,$/;" p module:axi_dmac_burst_memory +dest_burst_info_write adi_library/axi_dmac/dest_axi_mm.v /^ input dest_burst_info_write,$/;" p module:dmac_dest_mm_axi +dest_burst_info_write adi_library/axi_dmac/request_arb.v /^wire dest_burst_info_write;$/;" n module:dmac_request_arb +dest_burst_len adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [BURST_LEN_WIDTH_DEST-1:0] dest_burst_len;$/;" n module:axi_dmac_burst_memory +dest_burst_len_data adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg [BYTES_PER_BURST_WIDTH+1-1:0] dest_burst_len_data = {DMA_LENGTH_ALIGN{1'b1}};$/;" r module:axi_dmac_burst_memory +dest_burst_length adi_library/axi_dmac/request_arb.v /^wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_burst_length;$/;" n module:dmac_request_arb +dest_burst_ready adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire dest_burst_ready;$/;" n module:axi_dmac_burst_memory +dest_burst_valid adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire dest_burst_valid;$/;" n module:axi_dmac_burst_memory +dest_clk adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input dest_clk,$/;" p module:axi_dmac_burst_memory +dest_clk adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input dest_clk,$/;" p module:axi_dmac_reset_manager +dest_clk adi_library/axi_dmac/axi_dmac_response_manager.v /^ input dest_clk,$/;" p module:axi_dmac_response_manager +dest_clk adi_library/axi_dmac/axi_dmac_transfer.v /^wire dest_clk;$/;" n module:axi_dmac_transfer +dest_clk adi_library/axi_dmac/request_arb.v /^ output dest_clk,$/;" p module:dmac_request_arb +dest_data adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output [DATA_WIDTH_DEST-1:0] dest_data,$/;" p module:axi_dmac_burst_memory +dest_data adi_library/axi_dmac/axi_dmac_resize_dest.v /^ output [DATA_WIDTH_DEST-1:0] dest_data,$/;" p module:axi_dmac_resize_dest +dest_data adi_library/axi_dmac/request_arb.v /^wire [DMA_DATA_WIDTH_DEST-1:0] dest_data;$/;" n module:dmac_request_arb +dest_data_id adi_library/axi_dmac/axi_dmac.v /^wire [ID_WIDTH-1:0] dest_data_id;$/;" n module:axi_dmac +dest_data_last adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output dest_data_last,$/;" p module:axi_dmac_burst_memory +dest_data_last adi_library/axi_dmac/axi_dmac_resize_dest.v /^ output dest_data_last,$/;" p module:axi_dmac_resize_dest +dest_data_ready adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input dest_data_ready,$/;" p module:axi_dmac_burst_memory +dest_data_ready adi_library/axi_dmac/axi_dmac_resize_dest.v /^ input dest_data_ready,$/;" p module:axi_dmac_resize_dest +dest_data_request_id adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input [ID_WIDTH-1:0] dest_data_request_id,$/;" p module:axi_dmac_burst_memory +dest_data_request_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] dest_data_request_id;$/;" n module:dmac_request_arb +dest_data_response_id adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output [ID_WIDTH-1:0] dest_data_response_id,$/;" p module:axi_dmac_burst_memory +dest_data_response_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] dest_data_response_id;$/;" n module:dmac_request_arb +dest_data_strb adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output [DATA_WIDTH_DEST\/8-1:0] dest_data_strb,$/;" p module:axi_dmac_burst_memory +dest_data_strb adi_library/axi_dmac/axi_dmac_resize_dest.v /^ output [DATA_WIDTH_DEST\/8-1:0] dest_data_strb$/;" p module:axi_dmac_resize_dest +dest_data_valid adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output dest_data_valid,$/;" p module:axi_dmac_burst_memory +dest_data_valid adi_library/axi_dmac/axi_dmac_resize_dest.v /^ output dest_data_valid,$/;" p module:axi_dmac_resize_dest +dest_diag_level_bursts adi_library/axi_dmac/axi_dmac.v /^ output [7:0] dest_diag_level_bursts$/;" p module:axi_dmac +dest_diag_level_bursts adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output [7:0] dest_diag_level_bursts$/;" p module:axi_dmac_burst_memory +dest_diag_level_bursts adi_library/axi_dmac/axi_dmac_transfer.v /^ output [7:0] dest_diag_level_bursts$/;" p module:axi_dmac_transfer +dest_diag_level_bursts adi_library/axi_dmac/request_arb.v /^ output [7:0] dest_diag_level_bursts$/;" p module:dmac_request_arb +dest_enable adi_library/axi_dmac/axi_dmac_reset_manager.v /^ output dest_enable,$/;" p module:axi_dmac_reset_manager +dest_enable adi_library/axi_dmac/axi_dmac_transfer.v /^wire dest_enable;$/;" n module:axi_dmac_transfer +dest_enable adi_library/axi_dmac/request_arb.v /^ input dest_enable,$/;" p module:dmac_request_arb +dest_enable adi_library/axi_dmac/tb/reset_manager_tb.v /^ wire dest_enable;$/;" n module:dmac_reset_manager_tb +dest_enabled adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input dest_enabled,$/;" p module:axi_dmac_reset_manager +dest_enabled adi_library/axi_dmac/axi_dmac_transfer.v /^wire dest_enabled;$/;" n module:axi_dmac_transfer +dest_enabled adi_library/axi_dmac/request_arb.v /^ output dest_enabled,$/;" p module:dmac_request_arb +dest_enabled adi_library/axi_dmac/tb/reset_manager_tb.v /^ wire dest_enabled = dest_enabled_shift[15];$/;" n module:dmac_reset_manager_tb +dest_enabled_shift adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg [15:0] dest_enabled_shift;$/;" r module:dmac_reset_manager_tb +dest_ext_resetn adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input dest_ext_resetn,$/;" p module:axi_dmac_reset_manager +dest_ext_resetn adi_library/axi_dmac/axi_dmac_transfer.v /^wire dest_ext_resetn;$/;" n module:axi_dmac_transfer +dest_ext_resetn adi_library/axi_dmac/request_arb.v /^ output dest_ext_resetn,$/;" p module:dmac_request_arb +dest_fifo_data adi_library/axi_dmac/request_arb.v /^wire [DMA_DATA_WIDTH_DEST-1:0] dest_fifo_data;$/;" n module:dmac_request_arb +dest_fifo_last adi_library/axi_dmac/request_arb.v /^wire dest_fifo_last;$/;" n module:dmac_request_arb +dest_fifo_ready adi_library/axi_dmac/request_arb.v /^wire dest_fifo_ready;$/;" n module:dmac_request_arb +dest_fifo_strb adi_library/axi_dmac/request_arb.v /^wire [DMA_DATA_WIDTH_DEST\/8-1:0] dest_fifo_strb;$/;" n module:dmac_request_arb +dest_fifo_valid adi_library/axi_dmac/request_arb.v /^wire dest_fifo_valid;$/;" n module:dmac_request_arb +dest_id adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg [ID_WIDTH-1:0] dest_id = 'h0;$/;" r module:axi_dmac_burst_memory +dest_id_next adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg [ID_WIDTH-1:0] dest_id_next = 'h0;$/;" r module:axi_dmac_burst_memory +dest_id_next_inc adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [ID_WIDTH-1:0] dest_id_next_inc;$/;" n module:axi_dmac_burst_memory +dest_id_reduced adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [ID_WIDTH-2:0] dest_id_reduced;$/;" n module:axi_dmac_burst_memory +dest_id_reduced_msb adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg dest_id_reduced_msb = 1'b0;$/;" r module:axi_dmac_burst_memory +dest_id_reduced_msb_next adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg dest_id_reduced_msb_next = 1'b0;$/;" r module:axi_dmac_burst_memory +dest_id_reduced_next adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [ID_WIDTH-2:0] dest_id_reduced_next;$/;" n module:axi_dmac_burst_memory +dest_last adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire dest_last;$/;" n module:axi_dmac_burst_memory +dest_last adi_library/axi_dmac/request_arb.v /^wire dest_last;$/;" n module:dmac_request_arb +dest_last_beat adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire dest_last_beat;$/;" n module:axi_dmac_burst_memory +dest_mem_data adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [DATA_WIDTH_MEM_DEST-1:0] dest_mem_data;$/;" n module:axi_dmac_burst_memory +dest_mem_data_last adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg dest_mem_data_last = 1'b0;$/;" r module:axi_dmac_burst_memory +dest_mem_data_ready adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire dest_mem_data_ready;$/;" n module:axi_dmac_burst_memory +dest_mem_data_strb adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg [DATA_WIDTH_MEM_DEST\/8-1:0] dest_mem_data_strb = {DATA_WIDTH_MEM_DEST\/8{1'b1}};$/;" r module:axi_dmac_burst_memory +dest_mem_data_valid adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg dest_mem_data_valid = 1'b0;$/;" r module:axi_dmac_burst_memory +dest_raddr adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [ADDRESS_WIDTH_DEST-1:0] dest_raddr;$/;" n module:axi_dmac_burst_memory +dest_ready adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire dest_ready;$/;" n module:axi_dmac_burst_memory +dest_ready adi_library/axi_dmac/request_arb.v /^wire dest_ready;$/;" n module:dmac_request_arb +dest_req_dest_address adi_library/axi_dmac/request_arb.v /^wire [DMA_ADDRESS_WIDTH_DEST-1:0] dest_req_dest_address;$/;" n module:dmac_request_arb +dest_req_ready adi_library/axi_dmac/request_arb.v /^wire dest_req_ready;$/;" n module:dmac_request_arb +dest_req_valid adi_library/axi_dmac/request_arb.v /^wire dest_req_valid;$/;" n module:dmac_request_arb +dest_req_xlast adi_library/axi_dmac/request_arb.v /^wire dest_req_xlast;$/;" n module:dmac_request_arb +dest_request_id adi_library/axi_dmac/axi_dmac.v /^wire [ID_WIDTH-1:0] dest_request_id;$/;" n module:axi_dmac +dest_request_id adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output [ID_WIDTH-1:0] dest_request_id,$/;" p module:axi_dmac_burst_memory +dest_request_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] dest_request_id;$/;" n module:dmac_request_arb +dest_reset adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input dest_reset,$/;" p module:axi_dmac_burst_memory +dest_resetn adi_library/axi_dmac/axi_dmac_reset_manager.v /^ output dest_resetn,$/;" p module:axi_dmac_reset_manager +dest_resetn adi_library/axi_dmac/axi_dmac_response_manager.v /^ input dest_resetn,$/;" p module:axi_dmac_response_manager +dest_resetn adi_library/axi_dmac/axi_dmac_transfer.v /^wire dest_resetn;$/;" n module:axi_dmac_transfer +dest_resetn adi_library/axi_dmac/request_arb.v /^ input dest_resetn,$/;" p module:dmac_request_arb +dest_response_data_burst_length adi_library/axi_dmac/axi_dmac_response_manager.v /^ input [BYTES_PER_BURST_WIDTH-1:0] dest_response_data_burst_length,$/;" p module:axi_dmac_response_manager +dest_response_data_burst_length adi_library/axi_dmac/request_arb.v /^wire [BYTES_PER_BURST_WIDTH-1:0] dest_response_data_burst_length;$/;" n module:dmac_request_arb +dest_response_eot adi_library/axi_dmac/request_arb.v /^wire dest_response_eot = eot_mem_dest[dest_response_id];$/;" n module:dmac_request_arb +dest_response_id adi_library/axi_dmac/axi_dmac.v /^wire [ID_WIDTH-1:0] dest_response_id;$/;" n module:axi_dmac +dest_response_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] dest_response_id;$/;" n module:dmac_request_arb +dest_response_partial adi_library/axi_dmac/axi_dmac_response_manager.v /^ input dest_response_partial,$/;" p module:axi_dmac_response_manager +dest_response_partial adi_library/axi_dmac/request_arb.v /^wire dest_response_partial;$/;" n module:dmac_request_arb +dest_response_ready adi_library/axi_dmac/axi_dmac_response_manager.v /^ output dest_response_ready,$/;" p module:axi_dmac_response_manager +dest_response_ready adi_library/axi_dmac/request_arb.v /^wire dest_response_ready;$/;" n module:dmac_request_arb +dest_response_resp adi_library/axi_dmac/axi_dmac_response_manager.v /^ input [1:0] dest_response_resp,$/;" p module:axi_dmac_response_manager +dest_response_resp adi_library/axi_dmac/request_arb.v /^wire [1:0] dest_response_resp;$/;" n module:dmac_request_arb +dest_response_resp_eot adi_library/axi_dmac/axi_dmac_response_manager.v /^ input dest_response_resp_eot,$/;" p module:axi_dmac_response_manager +dest_response_resp_eot adi_library/axi_dmac/request_arb.v /^wire dest_response_resp_eot;$/;" n module:dmac_request_arb +dest_response_valid adi_library/axi_dmac/axi_dmac_response_manager.v /^ input dest_response_valid,$/;" p module:axi_dmac_response_manager +dest_response_valid adi_library/axi_dmac/request_arb.v /^wire dest_response_valid;$/;" n module:dmac_request_arb +dest_src_burst_length adi_library/axi_dmac/request_arb.v /^wire [BEATS_PER_BURST_WIDTH_SRC-1:0] dest_src_burst_length;$/;" n module:dmac_request_arb +dest_src_id adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [ID_WIDTH-1:0] dest_src_id;$/;" n module:axi_dmac_burst_memory +dest_strb adi_library/axi_dmac/request_arb.v /^wire [DMA_DATA_WIDTH_DEST\/8-1:0] dest_strb;$/;" n module:dmac_request_arb +dest_stride adi_library/axi_dmac/2d_transfer.v /^reg [DMA_LENGTH_WIDTH-1:0] dest_stride = 'h0;$/;" r module:dmac_2d_transfer +dest_valid adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg dest_valid = 1'b0;$/;" r module:axi_dmac_burst_memory +dest_valid adi_library/axi_dmac/request_arb.v /^wire dest_valid;$/;" n module:dmac_request_arb +dfmt_enable adi_library/common/ad_datafmt.v /^ input dfmt_enable,$/;" p module:ad_datafmt +dfmt_enable adi_library/common/util_axis_upscale.v /^ input dfmt_enable,$/;" p module:util_axis_upscale +dfmt_se adi_library/common/ad_datafmt.v /^ input dfmt_se);$/;" p module:ad_datafmt +dfmt_se adi_library/common/util_axis_upscale.v /^ input dfmt_se);$/;" p module:util_axis_upscale +dfmt_type adi_library/common/ad_datafmt.v /^ input dfmt_type,$/;" p module:ad_datafmt +dfmt_type adi_library/common/util_axis_upscale.v /^ input dfmt_type,$/;" p module:util_axis_upscale +dfreq_word hdl/DDS_compensate.v /^ input [13:0] dfreq_word; \/\/-- 解调频偏$/;" p module:DDS_compensate +dfreq_word_nd hdl/DDS_compensate.v /^ input dfreq_word_nd;$/;" p module:DDS_compensate +dfreq_word_nd_DDS hdl/freqestm.v /^ reg dfreq_word_nd_DDS;$/;" r module:freqestm +diff adi_library/util_cic/cic_comb.v /^wire [DATA_WIDTH-1:0] diff = (data_in_seq | ~mask) - (storage_out & mask);$/;" n module:cic_comb +diff1_d adi_library/common/util_dec256sinc24b.v /^ reg [36:0] diff1_d = 37'h0;$/;" r module:util_dec256sinc24b +diff1_s adi_library/common/util_dec256sinc24b.v /^ wire [36:0] diff1_s;$/;" n module:util_dec256sinc24b +diff2_d adi_library/common/util_dec256sinc24b.v /^ reg [36:0] diff2_d = 37'h0;$/;" r module:util_dec256sinc24b +diff2_s adi_library/common/util_dec256sinc24b.v /^ wire [36:0] diff2_s;$/;" n module:util_dec256sinc24b +diff3_s adi_library/common/util_dec256sinc24b.v /^ wire [36:0] diff3_s;$/;" n module:util_dec256sinc24b +din adi_library/axi_dmac/src_fifo_inf.v /^ input [DATA_WIDTH-1:0] din,$/;" p module:dmac_src_fifo_inf +din adi_library/common/ad_b2g.v /^ input [DATA_WIDTH-1:0] din,$/;" p module:ad_b2g +din adi_library/common/ad_g2b.v /^ input [DATA_WIDTH-1:0] din,$/;" p module:ad_g2b +din adi_library/common/up_adc_channel.v /^ input [15:0] din;$/;" p function:up_adc_channel.sm2tc +din adi_library/common/up_dac_channel.v /^ input [15:0] din;$/;" p function:up_dac_channel.sm2tc +din adi_library/common/util_delay.v /^ input din,$/;" p module:util_delay +din adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ input [DATA_WIDTH-1:0] din,$/;" p module:axi_dacfifo_address_buffer +din adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ input [31:0] din;$/;" p function:axi_xcvrlb_1.pn31 +din hdl/FrameMerge.v /^ input din,$/;" p module:FrameMerge +din hdl/shift_reg.v /^ input [DATA_WIDTH-1:0] din,$/;" p module:shift_reg +din hdl/trunc_25to12_2dly.v /^ input [24:0] din;$/;" p module:trunc_25to12_2dly +din_1i hdl/DAGC_v2.v /^ reg [ 9:0] din_1i = 10'd0;$/;" r module:DAGC_v2 +din_MMSE hdl/Chn_Estimate.v /^ output reg [21:0] din_MMSE = 22'd0,$/;" p module:Chn_Estimate +din_MMSE hdl/SC_FDE_TOP.v /^ wire [21:0] din_MMSE;$/;" n module:SC_FDE_TOP +din_clk adi_library/util_mfifo/util_mfifo.v /^ input din_clk,$/;" p module:util_mfifo +din_clk adi_library/util_rfifo/util_rfifo.v /^ input din_clk,$/;" p module:util_rfifo +din_clk adi_library/util_wfifo/util_wfifo.v /^ input din_clk,$/;" p module:util_wfifo +din_data1i hdl/SC_FDE_TOP.v /^ wire [9:0] din_data1i;$/;" n module:SC_FDE_TOP +din_data1i hdl/data_ow.v /^ output reg [9:0] din_data1i = 10'd0,$/;" p module:data_ow +din_data1q hdl/SC_FDE_TOP.v /^ wire [9:0] din_data1q;$/;" n module:SC_FDE_TOP +din_data1q hdl/data_ow.v /^ output reg [9:0] din_data1q = 10'd0,$/;" p module:data_ow +din_data2i hdl/SC_FDE_TOP.v /^ wire [9:0] din_data2i;$/;" n module:SC_FDE_TOP +din_data2i hdl/data_ow.v /^ output reg [9:0] din_data2i = 10'd0,$/;" p module:data_ow +din_data2q hdl/SC_FDE_TOP.v /^ wire [9:0] din_data2q;$/;" n module:SC_FDE_TOP +din_data2q hdl/data_ow.v /^ output reg [9:0] din_data2q = 10'd0,$/;" p module:data_ow +din_data_0 adi_library/util_mfifo/util_mfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_0,$/;" p module:util_mfifo +din_data_0 adi_library/util_rfifo/util_rfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_0,$/;" p module:util_rfifo +din_data_0 adi_library/util_wfifo/util_wfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_0,$/;" p module:util_wfifo +din_data_1 adi_library/util_mfifo/util_mfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_1,$/;" p module:util_mfifo +din_data_1 adi_library/util_rfifo/util_rfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_1,$/;" p module:util_rfifo +din_data_1 adi_library/util_wfifo/util_wfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_1,$/;" p module:util_wfifo +din_data_2 adi_library/util_mfifo/util_mfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_2,$/;" p module:util_mfifo +din_data_2 adi_library/util_rfifo/util_rfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_2,$/;" p module:util_rfifo +din_data_2 adi_library/util_wfifo/util_wfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_2,$/;" p module:util_wfifo +din_data_3 adi_library/util_mfifo/util_mfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_3,$/;" p module:util_mfifo +din_data_3 adi_library/util_rfifo/util_rfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_3,$/;" p module:util_rfifo +din_data_3 adi_library/util_wfifo/util_wfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_3,$/;" p module:util_wfifo +din_data_4 adi_library/util_mfifo/util_mfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_4,$/;" p module:util_mfifo +din_data_4 adi_library/util_rfifo/util_rfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_4,$/;" p module:util_rfifo +din_data_4 adi_library/util_wfifo/util_wfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_4,$/;" p module:util_wfifo +din_data_5 adi_library/util_mfifo/util_mfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_5,$/;" p module:util_mfifo +din_data_5 adi_library/util_rfifo/util_rfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_5,$/;" p module:util_rfifo +din_data_5 adi_library/util_wfifo/util_wfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_5,$/;" p module:util_wfifo +din_data_6 adi_library/util_mfifo/util_mfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_6,$/;" p module:util_mfifo +din_data_6 adi_library/util_rfifo/util_rfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_6,$/;" p module:util_rfifo +din_data_6 adi_library/util_wfifo/util_wfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_6,$/;" p module:util_wfifo +din_data_7 adi_library/util_mfifo/util_mfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_7,$/;" p module:util_mfifo +din_data_7 adi_library/util_rfifo/util_rfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_7,$/;" p module:util_rfifo +din_data_7 adi_library/util_wfifo/util_wfifo.v /^ input [DIN_DATA_WIDTH-1:0] din_data_7,$/;" p module:util_wfifo +din_data_s adi_library/util_rfifo/util_rfifo.v /^ wire [(T_DIN_DATA_WIDTH-1):0] din_data_s;$/;" n module:util_rfifo +din_data_s adi_library/util_wfifo/util_wfifo.v /^ wire [(T_DIN_DATA_WIDTH-1):0] din_data_s;$/;" n module:util_wfifo +din_dcnt adi_library/util_wfifo/util_wfifo.v /^ reg [ 2:0] din_dcnt = 'd0;$/;" r module:util_wfifo +din_dcnt_s adi_library/util_wfifo/util_wfifo.v /^ wire [ 2:0] din_dcnt_s;$/;" n module:util_wfifo +din_dly hdl/trunc_25to12_2dly.v /^ reg [24:0] din_dly = 0;$/;" r module:trunc_25to12_2dly +din_dout_toggle_m1 adi_library/util_mfifo/util_mfifo.v /^ reg din_dout_toggle_m1 = 'd0;$/;" r module:util_mfifo +din_dout_toggle_m2 adi_library/util_mfifo/util_mfifo.v /^ reg din_dout_toggle_m2 = 'd0;$/;" r module:util_mfifo +din_dout_toggle_m3 adi_library/util_mfifo/util_mfifo.v /^ reg din_dout_toggle_m3 = 'd0;$/;" r module:util_mfifo +din_dout_toggle_s adi_library/util_mfifo/util_mfifo.v /^ wire din_dout_toggle_s;$/;" n module:util_mfifo +din_enable adi_library/util_mfifo/util_mfifo.v /^ reg din_enable = 'd0;$/;" r module:util_mfifo +din_enable adi_library/util_rfifo/util_rfifo.v /^ reg [ 7:0] din_enable = 'd0;$/;" r module:util_rfifo +din_enable adi_library/util_wfifo/util_wfifo.v /^ reg [ 7:0] din_enable = 'd0;$/;" r module:util_wfifo +din_enable_0 adi_library/util_rfifo/util_rfifo.v /^ output din_enable_0,$/;" p module:util_rfifo +din_enable_0 adi_library/util_wfifo/util_wfifo.v /^ input din_enable_0,$/;" p module:util_wfifo +din_enable_1 adi_library/util_rfifo/util_rfifo.v /^ output din_enable_1,$/;" p module:util_rfifo +din_enable_1 adi_library/util_wfifo/util_wfifo.v /^ input din_enable_1,$/;" p module:util_wfifo +din_enable_2 adi_library/util_rfifo/util_rfifo.v /^ output din_enable_2,$/;" p module:util_rfifo +din_enable_2 adi_library/util_wfifo/util_wfifo.v /^ input din_enable_2,$/;" p module:util_wfifo +din_enable_3 adi_library/util_rfifo/util_rfifo.v /^ output din_enable_3,$/;" p module:util_rfifo +din_enable_3 adi_library/util_wfifo/util_wfifo.v /^ input din_enable_3,$/;" p module:util_wfifo +din_enable_4 adi_library/util_rfifo/util_rfifo.v /^ output din_enable_4,$/;" p module:util_rfifo +din_enable_4 adi_library/util_wfifo/util_wfifo.v /^ input din_enable_4,$/;" p module:util_wfifo +din_enable_5 adi_library/util_rfifo/util_rfifo.v /^ output din_enable_5,$/;" p module:util_rfifo +din_enable_5 adi_library/util_wfifo/util_wfifo.v /^ input din_enable_5,$/;" p module:util_wfifo +din_enable_6 adi_library/util_rfifo/util_rfifo.v /^ output din_enable_6,$/;" p module:util_rfifo +din_enable_6 adi_library/util_wfifo/util_wfifo.v /^ input din_enable_6,$/;" p module:util_wfifo +din_enable_7 adi_library/util_rfifo/util_rfifo.v /^ output din_enable_7,$/;" p module:util_rfifo +din_enable_7 adi_library/util_wfifo/util_wfifo.v /^ input din_enable_7,$/;" p module:util_wfifo +din_enable_m1 adi_library/util_rfifo/util_rfifo.v /^ reg [ 7:0] din_enable_m1 = 'd0;$/;" r module:util_rfifo +din_enable_s adi_library/util_wfifo/util_wfifo.v /^ wire [ 7:0] din_enable_s;$/;" n module:util_wfifo +din_i hdl/DDS_compensate.v /^ input [11:0] din_i,din_q;$/;" p module:DDS_compensate +din_i hdl/phase_adjust.v /^ input [9:0] din_i,$/;" p module:phase_adjust +din_init adi_library/util_rfifo/util_rfifo.v /^ reg din_init = 'd0;$/;" r module:util_rfifo +din_n1 hdl/Interp_half.v /^ input [9:0] din_n1,$/;" p module:Interp_half +din_n1 hdl/Interp_quarter.v /^ input [9:0] din_n1,$/;" p module:Interp_quarter +din_n2 hdl/Interp_half.v /^ input [9:0] din_n2,$/;" p module:Interp_half +din_n2 hdl/Interp_quarter.v /^ input [9:0] din_n2,$/;" p module:Interp_quarter +din_nd hdl/DDS_compensate.v /^ input din_nd;$/;" p module:DDS_compensate +din_nd hdl/trunc_25to12_2dly.v /^ input din_nd;$/;" p module:trunc_25to12_2dly +din_nd_d1 hdl/DDS_compensate.v /^ reg din_nd_d1 = 0,din_nd_d2 = 0;$/;" r module:DDS_compensate +din_nd_d1 hdl/trunc_25to12_2dly.v /^ reg din_nd_d1 = 0;$/;" r module:trunc_25to12_2dly +din_nd_d2 hdl/DDS_compensate.v /^ reg din_nd_d1 = 0,din_nd_d2 = 0;$/;" r module:DDS_compensate +din_ovf adi_library/util_wfifo/util_wfifo.v /^ output reg din_ovf,$/;" p module:util_wfifo +din_ovf_m1 adi_library/util_wfifo/util_wfifo.v /^ reg din_ovf_m1 = 'd0;$/;" r module:util_wfifo +din_p1 hdl/Interp_half.v /^ input [9:0] din_p1,$/;" p module:Interp_half +din_p1 hdl/Interp_quarter.v /^ input [9:0] din_p1,$/;" p module:Interp_quarter +din_pilot01 hdl/freqestm.v /^ reg [19:0] din_pilot01;$/;" r module:freqestm +din_pilot02 hdl/freqestm.v /^ reg [19:0] din_pilot02;$/;" r module:freqestm +din_pilot1i hdl/data_ow.v /^ reg [9:0] din_pilot1i = 10'd0;$/;" r module:data_ow +din_pilot1q hdl/data_ow.v /^ reg [9:0] din_pilot1q = 10'd0;$/;" r module:data_ow +din_pilot2i hdl/data_ow.v /^ reg [9:0] din_pilot2i = 10'd0;$/;" r module:data_ow +din_pilot2q hdl/data_ow.v /^ reg [9:0] din_pilot2q = 10'd0;$/;" r module:data_ow +din_q hdl/DDS_compensate.v /^ input [11:0] din_i,din_q;$/;" p module:DDS_compensate +din_q hdl/phase_adjust.v /^ input [9:0] din_q,$/;" p module:phase_adjust +din_req adi_library/util_rfifo/util_rfifo.v /^ reg din_req = 'd0;$/;" r module:util_rfifo +din_req_cnt adi_library/util_rfifo/util_rfifo.v /^ reg [ 6:0] din_req_cnt = 'd0;$/;" r module:util_rfifo +din_req_s adi_library/util_rfifo/util_rfifo.v /^ wire din_req_s;$/;" n module:util_rfifo +din_req_t adi_library/util_wfifo/util_wfifo.v /^ reg din_req_t = 'd0;$/;" r module:util_wfifo +din_req_t_m1 adi_library/util_rfifo/util_rfifo.v /^ reg din_req_t_m1 = 'd0;$/;" r module:util_rfifo +din_req_t_m2 adi_library/util_rfifo/util_rfifo.v /^ reg din_req_t_m2 = 'd0;$/;" r module:util_rfifo +din_req_t_m3 adi_library/util_rfifo/util_rfifo.v /^ reg din_req_t_m3 = 'd0;$/;" r module:util_rfifo +din_rinit adi_library/util_wfifo/util_wfifo.v /^ reg [(ADDRESS_WIDTH-4):0] din_rinit = 'd0;$/;" r module:util_wfifo +din_rst adi_library/util_mfifo/util_mfifo.v /^ input din_rst,$/;" p module:util_mfifo +din_rst adi_library/util_wfifo/util_wfifo.v /^ input din_rst,$/;" p module:util_wfifo +din_rstn adi_library/util_rfifo/util_rfifo.v /^ input din_rstn,$/;" p module:util_rfifo +din_t0 hdl/Interp_half.v /^ input [9:0] din_t0,$/;" p module:Interp_half +din_t0 hdl/Interp_quarter.v /^ input [9:0] din_t0,$/;" p module:Interp_quarter +din_toggle adi_library/util_mfifo/util_mfifo.v /^ reg din_toggle = 'd0;$/;" r module:util_mfifo +din_unf adi_library/util_rfifo/util_rfifo.v /^ input din_unf,$/;" p module:util_rfifo +din_unf_d adi_library/util_rfifo/util_rfifo.v /^ reg din_unf_d = 'd0;$/;" r module:util_rfifo +din_valid adi_library/util_mfifo/util_mfifo.v /^ input din_valid,$/;" p module:util_mfifo +din_valid adi_library/util_rfifo/util_rfifo.v /^ reg din_valid = 'd0;$/;" r module:util_rfifo +din_valid_0 adi_library/util_rfifo/util_rfifo.v /^ output din_valid_0,$/;" p module:util_rfifo +din_valid_0 adi_library/util_wfifo/util_wfifo.v /^ input din_valid_0,$/;" p module:util_wfifo +din_valid_1 adi_library/util_rfifo/util_rfifo.v /^ output din_valid_1,$/;" p module:util_rfifo +din_valid_1 adi_library/util_wfifo/util_wfifo.v /^ input din_valid_1,$/;" p module:util_wfifo +din_valid_2 adi_library/util_rfifo/util_rfifo.v /^ output din_valid_2,$/;" p module:util_rfifo +din_valid_2 adi_library/util_wfifo/util_wfifo.v /^ input din_valid_2,$/;" p module:util_wfifo +din_valid_3 adi_library/util_rfifo/util_rfifo.v /^ output din_valid_3,$/;" p module:util_rfifo +din_valid_3 adi_library/util_wfifo/util_wfifo.v /^ input din_valid_3,$/;" p module:util_wfifo +din_valid_4 adi_library/util_rfifo/util_rfifo.v /^ output din_valid_4,$/;" p module:util_rfifo +din_valid_4 adi_library/util_wfifo/util_wfifo.v /^ input din_valid_4,$/;" p module:util_wfifo +din_valid_5 adi_library/util_rfifo/util_rfifo.v /^ output din_valid_5,$/;" p module:util_rfifo +din_valid_5 adi_library/util_wfifo/util_wfifo.v /^ input din_valid_5,$/;" p module:util_wfifo +din_valid_6 adi_library/util_rfifo/util_rfifo.v /^ output din_valid_6,$/;" p module:util_rfifo +din_valid_6 adi_library/util_wfifo/util_wfifo.v /^ input din_valid_6,$/;" p module:util_wfifo +din_valid_7 adi_library/util_rfifo/util_rfifo.v /^ output din_valid_7,$/;" p module:util_rfifo +din_valid_7 adi_library/util_wfifo/util_wfifo.v /^ input din_valid_7,$/;" p module:util_wfifo +din_valid_in_0 adi_library/util_rfifo/util_rfifo.v /^ input din_valid_in_0,$/;" p module:util_rfifo +din_valid_in_1 adi_library/util_rfifo/util_rfifo.v /^ input din_valid_in_1,$/;" p module:util_rfifo +din_valid_in_2 adi_library/util_rfifo/util_rfifo.v /^ input din_valid_in_2,$/;" p module:util_rfifo +din_valid_in_3 adi_library/util_rfifo/util_rfifo.v /^ input din_valid_in_3,$/;" p module:util_rfifo +din_valid_in_4 adi_library/util_rfifo/util_rfifo.v /^ input din_valid_in_4,$/;" p module:util_rfifo +din_valid_in_5 adi_library/util_rfifo/util_rfifo.v /^ input din_valid_in_5,$/;" p module:util_rfifo +din_valid_in_6 adi_library/util_rfifo/util_rfifo.v /^ input din_valid_in_6,$/;" p module:util_rfifo +din_valid_in_7 adi_library/util_rfifo/util_rfifo.v /^ input din_valid_in_7,$/;" p module:util_rfifo +din_valid_s adi_library/util_wfifo/util_wfifo.v /^ wire [ 7:0] din_valid_s;$/;" n module:util_wfifo +din_w adi_library/util_var_fifo/util_var_fifo.v /^ output [DATA_WIDTH-1:0] din_w,$/;" p module:util_var_fifo +din_waddr adi_library/util_mfifo/util_mfifo.v /^ reg [(ADDRESS_WIDTH-1):0] din_waddr = 'd0;$/;" r module:util_mfifo +din_waddr adi_library/util_rfifo/util_rfifo.v /^ reg [(ADDRESS_WIDTH-1):0] din_waddr = 'hc;$/;" r module:util_rfifo +din_waddr adi_library/util_wfifo/util_wfifo.v /^ reg [(ADDRESS_WIDTH-1):0] din_waddr = 'd0;$/;" r module:util_wfifo +din_waddr_max_s adi_library/util_mfifo/util_mfifo.v /^ wire din_waddr_max_s;$/;" n module:util_mfifo +din_wcnt adi_library/util_rfifo/util_rfifo.v /^ reg [ 2:0] din_wcnt = 'd0;$/;" r module:util_rfifo +din_wcnt_s adi_library/util_rfifo/util_rfifo.v /^ wire [ 2:0] din_wcnt_s;$/;" n module:util_rfifo +din_wdata adi_library/util_rfifo/util_rfifo.v /^ reg [(DATA_WIDTH-1):0] din_wdata = 'd0;$/;" r module:util_rfifo +din_wdata adi_library/util_wfifo/util_wfifo.v /^ reg [(DATA_WIDTH-1):0] din_wdata = 'd0;$/;" r module:util_wfifo +din_wdata_s adi_library/util_mfifo/util_mfifo.v /^ wire [(DIN_DATA_WIDTH-1):0] din_wdata_s[0:7];$/;" n module:util_mfifo +din_wr adi_library/util_mfifo/util_mfifo.v /^ reg din_wr = 'd0;$/;" r module:util_mfifo +din_wr adi_library/util_rfifo/util_rfifo.v /^ reg din_wr = 'd0;$/;" r module:util_rfifo +din_wr adi_library/util_wfifo/util_wfifo.v /^ reg din_wr = 'd0;$/;" r module:util_wfifo +dina adi_library/common/ad_mem.v /^ input [(DATA_WIDTH-1):0] dina,$/;" p module:ad_mem +dina adi_library/common/ad_mem_asym.v /^ input [A_DATA_WIDTH-1:0] dina,$/;" p module:ad_mem_asym +dina hdl/IQmerge.v /^ reg [15:0] dina = 16'd0;$/;" r module:IQmerge +dina hdl/phase_adjust.v /^ reg [19:0] dina = 20'd0;$/;" r module:phase_adjust +dini hdl/IQmerge.v /^ input [9:0] dini,$/;" p module:IQmerge +dini hdl/Interpolation.v /^ input [9:0] dini,$/;" p module:Interpolation +dini hdl/MF_Top.v /^ input [11:0] dini,$/;" p module:MF_Top +dini hdl/RecvTop.v /^ input [11:0] dini,$/;" p module:RecvTop +dini hdl/SC_FDE_TOP.v /^ input [9:0] dini,$/;" p module:SC_FDE_TOP +dini hdl/TimeSync_top.v /^ input [9:0] dini,$/;" p module:TimeSync_top +dini hdl/data_ow.v /^ input [9:0] dini,$/;" p module:data_ow +dini_n1 hdl/Interpolation.v /^ reg [9:0] dini_n1 = 10'd0;$/;" r module:Interpolation +dini_n2 hdl/Interpolation.v /^ reg [9:0] dini_n2 = 10'd0;$/;" r module:Interpolation +dini_n3 hdl/Interpolation.v /^ reg [9:0] dini_n3 = 10'd0;$/;" r module:Interpolation +dini_n4 hdl/Interpolation.v /^ reg [9:0] dini_n4 = 10'd0;$/;" r module:Interpolation +dini_p1 hdl/Interpolation.v /^ reg [9:0] dini_p1 = 10'd0;$/;" r module:Interpolation +dini_t0 hdl/Interpolation.v /^ reg [9:0] dini_t0 = 10'd0;$/;" r module:Interpolation +dinq hdl/IQmerge.v /^ input [9:0] dinq,$/;" p module:IQmerge +dinq hdl/Interpolation.v /^ input [9:0] dinq,$/;" p module:Interpolation +dinq hdl/MF_Top.v /^ input [11:0] dinq,$/;" p module:MF_Top +dinq hdl/RecvTop.v /^ input [11:0] dinq,$/;" p module:RecvTop +dinq hdl/SC_FDE_TOP.v /^ input [9:0] dinq,$/;" p module:SC_FDE_TOP +dinq hdl/TimeSync_top.v /^ input [9:0] dinq,$/;" p module:TimeSync_top +dinq hdl/data_ow.v /^ input [9:0] dinq,$/;" p module:data_ow +dinq_n1 hdl/Interpolation.v /^ reg [9:0] dinq_n1 = 10'd0;$/;" r module:Interpolation +dinq_n2 hdl/Interpolation.v /^ reg [9:0] dinq_n2 = 10'd0;$/;" r module:Interpolation +dinq_n3 hdl/Interpolation.v /^ reg [9:0] dinq_n3 = 10'd0;$/;" r module:Interpolation +dinq_n4 hdl/Interpolation.v /^ reg [9:0] dinq_n4 = 10'd0;$/;" r module:Interpolation +dinq_p1 hdl/Interpolation.v /^ reg [9:0] dinq_p1 = 10'd0;$/;" r module:Interpolation +dinq_t0 hdl/Interpolation.v /^ reg [9:0] dinq_t0 = 10'd0;$/;" r module:Interpolation +dio_i adi_library/common/ad_iobuf.v /^ input [(DATA_WIDTH-1):0] dio_i,$/;" p module:ad_iobuf +dio_o adi_library/common/ad_iobuf.v /^ output [(DATA_WIDTH-1):0] dio_o,$/;" p module:ad_iobuf +dio_p adi_library/common/ad_iobuf.v /^ inout [(DATA_WIDTH-1):0] dio_p);$/;" p module:ad_iobuf +dio_t adi_library/common/ad_iobuf.v /^ input [(DATA_WIDTH-1):0] dio_t,$/;" p module:ad_iobuf +dir adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) input dir,$/;" p module:ad_dds_cordic_pipe +dir_inv adi_library/common/ad_dds_cordic_pipe.v /^ wire dir_inv = ~dir;$/;" n module:ad_dds_cordic_pipe +disabled_all adi_library/axi_dmac/axi_dmac_reset_manager.v /^wire disabled_all;$/;" n module:axi_dmac_reset_manager +div2_MMSE hdl/Chn_Estimate.v /^reg [27:0] div2_MMSE = 28'd0;$/;" r module:Chn_Estimate +div2_MMSE_nd hdl/Chn_Estimate.v /^reg div2_MMSE_nd = 1'd0;$/;" r module:Chn_Estimate +div2_out_ce hdl/Chn_Estimate.v /^reg div2_out_ce = 1'd0;$/;" r module:Chn_Estimate +div_MMSE hdl/Chn_Estimate.v /^reg [30:0] div_MMSE = 31'd0;$/;" r module:Chn_Estimate +div_MMSE_nd hdl/Chn_Estimate.v /^reg div_MMSE_nd = 1'd0;$/;" r module:Chn_Estimate +div_axis_dout_tdata_i hdl/Chn_Estimate.v /^wire[71:0] div_axis_dout_tdata_i;$/;" n module:Chn_Estimate +div_axis_dout_tdata_q hdl/Chn_Estimate.v /^wire[71:0] div_axis_dout_tdata_q;$/;" n module:Chn_Estimate +div_clk adi_library/xilinx/common/ad_serdes_clk.v /^ output div_clk,$/;" p module:ad_serdes_clk +div_clk adi_library/xilinx/common/ad_serdes_in.v /^ input div_clk,$/;" p module:ad_serdes_in +div_clk adi_library/xilinx/common/ad_serdes_out.v /^ input div_clk,$/;" p module:ad_serdes_out +div_dld adi_library/xilinx/common/ad_serdes_in.v /^ wire div_dld;$/;" n block:ad_serdes_in.g_data +divider_ChnEst_i hdl/Chn_Estimate.v /^divider_ChnEst divider_ChnEst_i ($/;" i module:Chn_Estimate typeref:module:divider_ChnEst +divider_ChnEst_q hdl/Chn_Estimate.v /^divider_ChnEst divider_ChnEst_q ($/;" i module:Chn_Estimate typeref:module:divider_ChnEst +dividerin_dividend_i hdl/Chn_Estimate.v /^reg [33:0] dividerin_dividend_i = 34'd0;$/;" r module:Chn_Estimate +dividerin_dividend_q hdl/Chn_Estimate.v /^reg [33:0] dividerin_dividend_q = 34'd0;$/;" r module:Chn_Estimate +dividerin_divisor hdl/Chn_Estimate.v /^reg [27:0] dividerin_divisor = 28'd0;$/;" r module:Chn_Estimate +dividerin_valid hdl/Chn_Estimate.v /^reg dividerin_valid = 1'd0;$/;" r module:Chn_Estimate +dividerout_data_i hdl/Chn_Estimate.v /^wire[33:0] dividerout_data_i;$/;" n module:Chn_Estimate +dividerout_data_q hdl/Chn_Estimate.v /^wire[33:0] dividerout_data_q;$/;" n module:Chn_Estimate +dividerout_valid_i hdl/Chn_Estimate.v /^wire dividerout_valid_i;$/;" n module:Chn_Estimate +dividerout_valid_q hdl/Chn_Estimate.v /^wire dividerout_valid_q;$/;" n module:Chn_Estimate +dlyctrl adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ IDELAYCTRL dlyctrl ($/;" i module:util_gmii_to_rgmii typeref:module:IDELAYCTRL +dma_address_diff_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire [DMA_ADDRESS_WIDTH:0] dma_address_diff_s;$/;" n module:util_dacfifo_bypass +dma_bypass adi_library/util_dacfifo/util_dacfifo.v /^ reg dma_bypass = 1'b0;$/;" r module:util_dacfifo +dma_bypass adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ reg dma_bypass = 1'b0;$/;" r module:axi_dacfifo +dma_bypass_m1 adi_library/util_dacfifo/util_dacfifo.v /^ reg dma_bypass_m1 = 1'b0;$/;" r module:util_dacfifo +dma_bypass_m1 adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ reg dma_bypass_m1 = 1'b0;$/;" r module:axi_dacfifo +dma_clk adi_library/util_adcfifo/util_adcfifo.v /^ input dma_clk,$/;" p module:util_adcfifo +dma_clk adi_library/util_dacfifo/util_dacfifo.v /^ input dma_clk,$/;" p module:util_dacfifo +dma_clk adi_library/util_dacfifo/util_dacfifo_bypass.v /^ input dma_clk,$/;" p module:util_dacfifo_bypass +dma_clk adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input dma_clk,$/;" p module:axi_adcfifo +dma_clk adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ input dma_clk,$/;" p module:axi_adcfifo_dma +dma_clk adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input dma_clk,$/;" p module:axi_dacfifo +dma_clk adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input dma_clk,$/;" p module:axi_dacfifo_wr +dma_data adi_library/util_dacfifo/util_dacfifo.v /^ input [(DATA_WIDTH-1):0] dma_data,$/;" p module:util_dacfifo +dma_data adi_library/util_dacfifo/util_dacfifo_bypass.v /^ input [(DMA_DATA_WIDTH-1):0] dma_data,$/;" p module:util_dacfifo_bypass +dma_data adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input [(DMA_DATA_WIDTH-1):0] dma_data,$/;" p module:axi_dacfifo +dma_data adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input [(DMA_DATA_WIDTH-1):0] dma_data,$/;" p module:axi_dacfifo_wr +dma_endof_read adi_library/util_adcfifo/util_adcfifo.v /^ reg dma_endof_read = 'd0;$/;" r module:util_adcfifo +dma_fifo_reset_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire dma_fifo_reset_s;$/;" n module:axi_dacfifo_wr +dma_init adi_library/util_dacfifo/util_dacfifo.v /^ reg dma_init = 1'b0;$/;" r module:util_dacfifo +dma_last_beats adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ input [ 3:0] dma_last_beats,$/;" p module:axi_dacfifo_rd +dma_last_beats adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ (* dont_touch = "true" *) output reg [ 3:0] dma_last_beats,$/;" p module:axi_dacfifo_wr +dma_last_beats_s adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ wire [ 3:0] dma_last_beats_s;$/;" n module:axi_dacfifo +dma_lastaddr_g adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_g = 'b0;$/;" r module:util_dacfifo +dma_mem_addr_diff adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [DMA_ADDRESS_WIDTH-1:0] dma_mem_addr_diff = 'd0;$/;" r module:util_dacfifo_bypass +dma_mem_addr_diff adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_addr_diff = 'd0;$/;" r module:axi_dacfifo_wr +dma_mem_addr_diff_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire [(DMA_MEM_ADDRESS_WIDTH):0] dma_mem_addr_diff_s;$/;" n module:axi_dacfifo_wr +dma_mem_last_read_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire dma_mem_last_read_s;$/;" n module:axi_dacfifo_wr +dma_mem_last_read_toggle_m adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [ 2:0] dma_mem_last_read_toggle_m = 3'b0;$/;" r module:axi_dacfifo_wr +dma_mem_raddr adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0;$/;" r module:util_dacfifo_bypass +dma_mem_raddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0;$/;" r module:axi_dacfifo_wr +dma_mem_raddr_m1 adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 'd0;$/;" r module:util_dacfifo_bypass +dma_mem_raddr_m1 adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 'd0;$/;" r module:axi_dacfifo_wr +dma_mem_raddr_m2 adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0;$/;" r module:util_dacfifo_bypass +dma_mem_raddr_m2 adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0;$/;" r module:axi_dacfifo_wr +dma_mem_raddr_m2_g2b_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s;$/;" n module:util_dacfifo_bypass +dma_mem_raddr_m2_g2b_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s;$/;" n module:axi_dacfifo_wr +dma_mem_raddr_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_raddr_s;$/;" n module:util_dacfifo_bypass +dma_mem_raddr_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_s;$/;" n module:axi_dacfifo_wr +dma_mem_waddr adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0;$/;" r module:util_dacfifo_bypass +dma_mem_waddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0;$/;" r module:axi_dacfifo_wr +dma_mem_waddr_b2g_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_b2g_s;$/;" n module:util_dacfifo_bypass +dma_mem_waddr_b2g_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr_b2g_s;$/;" n module:axi_dacfifo_wr +dma_mem_waddr_g adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0;$/;" r module:util_dacfifo_bypass +dma_mem_waddr_g adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0;$/;" r module:axi_dacfifo_wr +dma_mem_wea_s adi_library/util_dacfifo/util_dacfifo_bypass.v /^ wire dma_mem_wea_s;$/;" n module:util_dacfifo_bypass +dma_mem_wea_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire dma_mem_wea_s;$/;" n module:axi_dacfifo_wr +dma_raddr adi_library/util_adcfifo/util_adcfifo.v /^ reg [DMA_ADDRESS_WIDTH:0] dma_raddr = 'd0;$/;" r module:util_adcfifo +dma_raddr adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0;$/;" r module:axi_adcfifo_dma +dma_raddr_rel adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr_rel = 'd0;$/;" r module:axi_adcfifo_dma +dma_raddr_rel_count adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [ 2:0] dma_raddr_rel_count = 'd0;$/;" r module:axi_adcfifo_dma +dma_raddr_rel_t adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg dma_raddr_rel_t = 'd0;$/;" r module:axi_adcfifo_dma +dma_rd adi_library/util_adcfifo/util_adcfifo.v /^ reg dma_rd = 'd0;$/;" r module:util_adcfifo +dma_rd adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg dma_rd = 'd0;$/;" r module:axi_adcfifo_dma +dma_rd_d adi_library/util_adcfifo/util_adcfifo.v /^ reg dma_rd_d = 'd0;$/;" r module:util_adcfifo +dma_rd_d adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg dma_rd_d = 'd0;$/;" r module:axi_adcfifo_dma +dma_rd_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ wire dma_rd_s;$/;" n module:axi_adcfifo_dma +dma_rdata_d adi_library/util_adcfifo/util_adcfifo.v /^ reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;$/;" r module:util_adcfifo +dma_rdata_d adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;$/;" r module:axi_adcfifo_dma +dma_rdata_s adi_library/util_adcfifo/util_adcfifo.v /^ wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;$/;" n module:util_adcfifo +dma_rdata_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;$/;" n module:axi_adcfifo_dma +dma_read_rst_s adi_library/util_adcfifo/util_adcfifo.v /^ wire dma_read_rst_s;$/;" n module:util_adcfifo +dma_ready adi_library/util_dacfifo/util_dacfifo.v /^ output reg dma_ready,$/;" p module:util_dacfifo +dma_ready adi_library/util_dacfifo/util_dacfifo_bypass.v /^ input dma_ready,$/;" p module:util_dacfifo_bypass +dma_ready adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ output reg dma_ready,$/;" p module:axi_dacfifo +dma_ready adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input dma_ready,$/;" p module:axi_dacfifo_wr +dma_ready_bypass_s adi_library/util_dacfifo/util_dacfifo.v /^ wire dma_ready_bypass_s;$/;" n module:util_dacfifo +dma_ready_out adi_library/util_dacfifo/util_dacfifo_bypass.v /^ output reg dma_ready_out,$/;" p module:util_dacfifo_bypass +dma_ready_out adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ output reg dma_ready_out,$/;" p module:axi_dacfifo_wr +dma_ready_wr_s adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ wire dma_ready_wr_s;$/;" n module:axi_dacfifo +dma_req_dest_address adi_library/axi_dmac/axi_dmac_transfer.v /^wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;$/;" n module:axi_dmac_transfer +dma_req_eot adi_library/axi_dmac/axi_dmac_transfer.v /^wire dma_req_eot;$/;" n module:axi_dmac_transfer +dma_req_last adi_library/axi_dmac/axi_dmac_transfer.v /^wire dma_req_last;$/;" n module:axi_dmac_transfer +dma_req_length adi_library/axi_dmac/axi_dmac_transfer.v /^wire [DMA_LENGTH_WIDTH-1:0] dma_req_length;$/;" n module:axi_dmac_transfer +dma_req_measured_burst_length adi_library/axi_dmac/axi_dmac_transfer.v /^wire [BYTES_PER_BURST_WIDTH-1:0] dma_req_measured_burst_length;$/;" n module:axi_dmac_transfer +dma_req_ready adi_library/axi_dmac/axi_dmac_transfer.v /^wire dma_req_ready;$/;" n module:axi_dmac_transfer +dma_req_src_address adi_library/axi_dmac/axi_dmac_transfer.v /^wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address;$/;" n module:axi_dmac_transfer +dma_req_sync_transfer_start adi_library/axi_dmac/axi_dmac_transfer.v /^wire dma_req_sync_transfer_start;$/;" n module:axi_dmac_transfer +dma_req_valid adi_library/axi_dmac/axi_dmac_transfer.v /^wire dma_req_valid;$/;" n module:axi_dmac_transfer +dma_response_partial adi_library/axi_dmac/axi_dmac_transfer.v /^wire dma_response_partial;$/;" n module:axi_dmac_transfer +dma_response_ready adi_library/axi_dmac/axi_dmac_transfer.v /^wire dma_response_ready;$/;" n module:axi_dmac_transfer +dma_response_valid adi_library/axi_dmac/axi_dmac_transfer.v /^wire dma_response_valid;$/;" n module:axi_dmac_transfer +dma_rst adi_library/util_dacfifo/util_dacfifo.v /^ input dma_rst,$/;" p module:util_dacfifo +dma_rst adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg dma_rst = 1'b0;$/;" r module:util_dacfifo_bypass +dma_rst adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg dma_rst = 'd0;$/;" r module:axi_adcfifo_dma +dma_rst adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input dma_rst,$/;" p module:axi_dacfifo +dma_rst adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input dma_rst,$/;" p module:axi_dacfifo_wr +dma_rst_int_s adi_library/util_dacfifo/util_dacfifo.v /^ wire dma_rst_int_s;$/;" n module:util_dacfifo +dma_rst_m1 adi_library/util_dacfifo/util_dacfifo_bypass.v /^ reg dma_rst_m1 = 1'b0;$/;" r module:util_dacfifo_bypass +dma_valid adi_library/util_dacfifo/util_dacfifo.v /^ input dma_valid,$/;" p module:util_dacfifo +dma_valid adi_library/util_dacfifo/util_dacfifo_bypass.v /^ input dma_valid,$/;" p module:util_dacfifo_bypass +dma_valid adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input dma_valid,$/;" p module:axi_dacfifo +dma_valid adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input dma_valid,$/;" p module:axi_dacfifo_wr +dma_waddr adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0;$/;" r module:util_dacfifo +dma_waddr_b2g_s adi_library/util_dacfifo/util_dacfifo.v /^ wire [(ADDRESS_WIDTH-1):0] dma_waddr_b2g_s;$/;" n module:util_dacfifo +dma_waddr_g adi_library/util_dacfifo/util_dacfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dma_waddr_g = 'b0;$/;" r module:util_dacfifo +dma_waddr_int adi_library/util_adcfifo/util_adcfifo.v /^ reg [DMA_ADDRESS_WIDTH-1:0] dma_waddr_int = 'd0;$/;" r module:util_adcfifo +dma_waddr_int_s adi_library/util_adcfifo/util_adcfifo.v /^ wire [ADC_ADDRESS_WIDTH-1:0] dma_waddr_int_s;$/;" n module:util_adcfifo +dma_waddr_rel adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [AXI_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0;$/;" r module:axi_adcfifo_dma +dma_waddr_rel_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s;$/;" n module:axi_adcfifo_dma +dma_waddr_rel_t_m adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ reg [ 2:0] dma_waddr_rel_t_m = 'd0;$/;" r module:axi_adcfifo_dma +dma_waddr_rel_t_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ wire dma_waddr_rel_t_s;$/;" n module:axi_adcfifo_dma +dma_wdata adi_library/util_adcfifo/util_adcfifo.v /^ output [DMA_DATA_WIDTH-1:0] dma_wdata,$/;" p module:util_adcfifo +dma_wdata adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [DMA_DATA_WIDTH-1:0] dma_wdata,$/;" p module:axi_adcfifo +dma_wdata adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ output [DMA_DATA_WIDTH-1:0] dma_wdata,$/;" p module:axi_adcfifo_dma +dma_wr adi_library/util_adcfifo/util_adcfifo.v /^ output dma_wr,$/;" p module:util_adcfifo +dma_wr adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output dma_wr,$/;" p module:axi_adcfifo +dma_wr adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ output dma_wr,$/;" p module:axi_adcfifo_dma +dma_wr_int_s adi_library/util_adcfifo/util_adcfifo.v /^ wire dma_wr_int_s;$/;" n module:util_adcfifo +dma_wready adi_library/util_adcfifo/util_adcfifo.v /^ input dma_wready,$/;" p module:util_adcfifo +dma_wready adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input dma_wready,$/;" p module:axi_adcfifo +dma_wready adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ input dma_wready,$/;" p module:axi_adcfifo_dma +dma_wready_s adi_library/util_adcfifo/util_adcfifo.v /^ wire dma_wready_s;$/;" n module:util_adcfifo +dma_wready_s adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ wire dma_wready_s;$/;" n module:axi_adcfifo_dma +dma_wren_s adi_library/util_dacfifo/util_dacfifo.v /^ wire dma_wren_s;$/;" n module:util_dacfifo +dma_xfer_last adi_library/util_dacfifo/util_dacfifo.v /^ input dma_xfer_last,$/;" p module:util_dacfifo +dma_xfer_last adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input dma_xfer_last,$/;" p module:axi_dacfifo +dma_xfer_last adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input dma_xfer_last,$/;" p module:axi_dacfifo_wr +dma_xfer_out_fifo adi_library/util_dacfifo/util_dacfifo.v /^ reg dma_xfer_out_fifo = 1'b0;$/;" r module:util_dacfifo +dma_xfer_posedge_s adi_library/util_dacfifo/util_dacfifo.v /^ wire dma_xfer_posedge_s;$/;" n module:util_dacfifo +dma_xfer_posedge_s adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ wire dma_xfer_posedge_s;$/;" n module:axi_dacfifo_wr +dma_xfer_req adi_library/util_adcfifo/util_adcfifo.v /^ input dma_xfer_req,$/;" p module:util_adcfifo +dma_xfer_req adi_library/util_dacfifo/util_dacfifo.v /^ input dma_xfer_req,$/;" p module:util_dacfifo +dma_xfer_req adi_library/util_dacfifo/util_dacfifo_bypass.v /^ input dma_xfer_req,$/;" p module:util_dacfifo_bypass +dma_xfer_req adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ input dma_xfer_req,$/;" p module:axi_adcfifo +dma_xfer_req adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ input dma_xfer_req,$/;" p module:axi_adcfifo_dma +dma_xfer_req adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v /^ input dma_xfer_req,$/;" p module:axi_adcfifo_rd +dma_xfer_req adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input dma_xfer_req,$/;" p module:axi_adcfifo_wr +dma_xfer_req adi_library/xilinx/axi_dacfifo/axi_dacfifo.v /^ input dma_xfer_req,$/;" p module:axi_dacfifo +dma_xfer_req adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ input dma_xfer_req,$/;" p module:axi_dacfifo_wr +dma_xfer_req_d adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ reg [ 1:0] dma_xfer_req_d = 2'b0;$/;" r module:axi_dacfifo_wr +dma_xfer_req_d1 adi_library/util_dacfifo/util_dacfifo.v /^ reg dma_xfer_req_d1 = 1'b0;$/;" r module:util_dacfifo +dma_xfer_req_d2 adi_library/util_dacfifo/util_dacfifo.v /^ reg dma_xfer_req_d2 = 1'b0;$/;" r module:util_dacfifo +dma_xfer_status adi_library/util_adcfifo/util_adcfifo.v /^ output [ 3:0] dma_xfer_status);$/;" p module:util_adcfifo +dma_xfer_status adi_library/xilinx/axi_adcfifo/axi_adcfifo.v /^ output [ 3:0] dma_xfer_status,$/;" p module:axi_adcfifo +dma_xfer_status adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v /^ output [ 3:0] dma_xfer_status);$/;" p module:axi_adcfifo_dma +dmac_2d_transfer adi_library/axi_dmac/2d_transfer.v /^module dmac_2d_transfer #($/;" m +dmac_address_generator adi_library/axi_dmac/address_generator.v /^module dmac_address_generator #($/;" m +dmac_data_mover adi_library/axi_dmac/data_mover.v /^module dmac_data_mover #($/;" m +dmac_dest_axi_stream adi_library/axi_dmac/dest_axi_stream.v /^module dmac_dest_axi_stream #($/;" m +dmac_dest_fifo_inf adi_library/axi_dmac/dest_fifo_inf.v /^module dmac_dest_fifo_inf #($/;" m +dmac_dest_mm_axi adi_library/axi_dmac/dest_axi_mm.v /^module dmac_dest_mm_axi #($/;" m +dmac_dma_read_shutdown_tb adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^module dmac_dma_read_shutdown_tb;$/;" m +dmac_dma_read_tb adi_library/axi_dmac/tb/dma_read_tb.v /^module dmac_dma_read_tb;$/;" m +dmac_dma_write_shutdown_tb adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^module dmac_dma_write_shutdown_tb;$/;" m +dmac_dma_write_tb adi_library/axi_dmac/tb/dma_write_tb.v /^module dmac_dma_write_tb;$/;" m +dmac_regmap_tb adi_library/axi_dmac/tb/regmap_tb.v /^module dmac_regmap_tb;$/;" m +dmac_request_arb adi_library/axi_dmac/request_arb.v /^module dmac_request_arb #($/;" m +dmac_request_generator adi_library/axi_dmac/request_generator.v /^module dmac_request_generator #($/;" m +dmac_reset_manager_tb adi_library/axi_dmac/tb/reset_manager_tb.v /^module dmac_reset_manager_tb;$/;" m +dmac_response_generator adi_library/axi_dmac/response_generator.v /^module dmac_response_generator #($/;" m +dmac_response_handler adi_library/axi_dmac/response_handler.v /^module dmac_response_handler #($/;" m +dmac_src_axi_stream adi_library/axi_dmac/src_axi_stream.v /^module dmac_src_axi_stream #($/;" m +dmac_src_fifo_inf adi_library/axi_dmac/src_fifo_inf.v /^module dmac_src_fifo_inf #($/;" m +dmac_src_mm_axi adi_library/axi_dmac/src_axi_mm.v /^module dmac_src_mm_axi #($/;" m +dmf_data_i hdl/Receiver.v /^ reg [20:0] dmf_data_i;$/;" r module:Receiver +dmf_data_q hdl/Receiver.v /^ reg [20:0] dmf_data_q;$/;" r module:Receiver +dmf_i hdl/frame_sync.v /^ output [17:0] dmf_i,$/;" p module:frame_sync +dmf_q hdl/frame_sync.v /^ output [17:0] dmf_q$/;" p module:frame_sync +dmf_ready hdl/Receiver.v /^ wire dmf_ready;$/;" n module:Receiver +dmf_s_valid hdl/Receiver.v /^ reg dmf_s_valid;$/;" r module:Receiver +dmf_tdata_interp16_i hdl/Receiver.v /^ wire [23:0] dmf_tdata_interp16_i;$/;" n module:Receiver +dmf_tdata_interp16_q hdl/Receiver.v /^ wire [23:0] dmf_tdata_interp16_q;$/;" n module:Receiver +dmf_tdata_interp4_i hdl/Receiver.v /^ wire [23:0] dmf_tdata_interp4_i;$/;" n module:Receiver +dmf_tdata_interp4_q hdl/Receiver.v /^ wire [23:0] dmf_tdata_interp4_q;$/;" n module:Receiver +dmf_tvalid hdl/Receiver.v /^ reg dmf_tvalid;$/;" r module:Receiver +dmf_tvalid_interp16_i hdl/Receiver.v /^ wire dmf_tvalid_interp16_i;$/;" n module:Receiver +dmf_tvalid_interp16_q hdl/Receiver.v /^ wire dmf_tvalid_interp16_q;$/;" n module:Receiver +dmf_tvalid_interp4_i hdl/Receiver.v /^ wire dmf_tvalid_interp4_i;$/;" n module:Receiver +dmf_tvalid_interp4_q hdl/Receiver.v /^ wire dmf_tvalid_interp4_q;$/;" n module:Receiver +dn adi_library/common/up_adc_channel.v /^ reg [15:0] dn;$/;" r function:up_adc_channel.sm2tc +dn adi_library/common/up_dac_channel.v /^ reg [15:0] dn;$/;" r function:up_dac_channel.sm2tc +do_acc_st adi_library/axi_dmac/axi_dmac_response_manager.v /^wire do_acc_st;$/;" n module:axi_dmac_response_manager +do_compl adi_library/axi_dmac/axi_dmac_response_manager.v /^wire do_compl;$/;" n module:axi_dmac_response_manager +do_enable adi_library/axi_dmac/axi_dmac_reset_manager.v /^reg do_enable = 1'b0;$/;" r module:axi_dmac_reset_manager +do_reset adi_library/axi_dmac/axi_dmac_reset_manager.v /^reg do_reset = 1'b0;$/;" r module:axi_dmac_reset_manager +do_trigger_reset adi_library/axi_dmac/tb/tb_base.v /^ task do_trigger_reset;$/;" t +do_trigger_reset adi_library/util_pack/tb/tb_base.v /^ task do_trigger_reset;$/;" t +dout adi_library/axi_dmac/dest_fifo_inf.v /^ output reg [DATA_WIDTH-1:0] dout,$/;" p module:dmac_dest_fifo_inf +dout adi_library/axi_dmac/tb/dma_read_tb.v /^ always @(posedge clk) begin: dout$/;" b module:dmac_dma_read_tb +dout adi_library/common/ad_b2g.v /^ output [DATA_WIDTH-1:0] dout);$/;" p module:ad_b2g +dout adi_library/common/ad_g2b.v /^ output [DATA_WIDTH-1:0] dout);$/;" p module:ad_g2b +dout adi_library/common/up_adc_channel.v /^ reg [15:0] dout;$/;" r function:up_adc_channel.sm2tc +dout adi_library/common/up_dac_channel.v /^ reg [15:0] dout;$/;" r function:up_dac_channel.sm2tc +dout adi_library/common/util_delay.v /^ output [DATA_WIDTH-1:0] dout);$/;" p module:util_delay +dout adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ output [DATA_WIDTH-1:0] dout);$/;" p module:axi_dacfifo_address_buffer +dout adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg [31:0] dout;$/;" r function:axi_xcvrlb_1.pn31 +dout hdl/IQmerge.v /^ output [7:0] dout$/;" p module:IQmerge +dout hdl/Interp_half.v /^ output reg [9:0] dout$/;" p module:Interp_half +dout hdl/Interp_quarter.v /^ output reg [9:0] dout$/;" p module:Interp_quarter +dout hdl/shift_reg.v /^ output [DATA_WIDTH-1:0] dout$/;" p module:shift_reg +dout hdl/trunc_25to12_2dly.v /^ output reg [11:0] dout = 0;$/;" p module:trunc_25to12_2dly +dout_1i hdl/DAGC_v2.v /^ wire [ 9:0] dout_1i;$/;" n module:DAGC_v2 +dout_MMSE hdl/SC_FDE_TOP.v /^ wire [21:0] dout_MMSE;$/;" n module:SC_FDE_TOP +dout_MMSE hdl/data_equalizer.v /^ input [21:0] dout_MMSE,$/;" p module:data_equalizer +dout_abs_pilot2 hdl/Chn_Estimate.v /^wire[14:0] dout_abs_pilot2;$/;" n module:Chn_Estimate +dout_clk adi_library/util_mfifo/util_mfifo.v /^ input dout_clk,$/;" p module:util_mfifo +dout_clk adi_library/util_rfifo/util_rfifo.v /^ input dout_clk,$/;" p module:util_rfifo +dout_clk adi_library/util_wfifo/util_wfifo.v /^ input dout_clk,$/;" p module:util_wfifo +dout_cnt adi_library/util_mfifo/util_mfifo.v /^ reg [ 4:0] dout_cnt = 'd0;$/;" r module:util_mfifo +dout_data adi_library/util_rfifo/util_rfifo.v /^ reg [(T_DOUT_DATA_WIDTH+1):0] dout_data = 'd0;$/;" r module:util_rfifo +dout_data1i hdl/SC_FDE_TOP.v /^ wire [9:0] dout_data1i;$/;" n module:SC_FDE_TOP +dout_data1i hdl/data_equalizer.v /^ input [9:0] dout_data1i,$/;" p module:data_equalizer +dout_data1q hdl/SC_FDE_TOP.v /^ wire [9:0] dout_data1q;$/;" n module:SC_FDE_TOP +dout_data1q hdl/data_equalizer.v /^ input [9:0] dout_data1q,$/;" p module:data_equalizer +dout_data2i hdl/SC_FDE_TOP.v /^ wire [9:0] dout_data2i;$/;" n module:SC_FDE_TOP +dout_data2i hdl/data_equalizer.v /^ input [9:0] dout_data2i,$/;" p module:data_equalizer +dout_data2q hdl/SC_FDE_TOP.v /^ wire [9:0] dout_data2q;$/;" n module:SC_FDE_TOP +dout_data2q hdl/data_equalizer.v /^ input [9:0] dout_data2q,$/;" p module:data_equalizer +dout_data_0 adi_library/util_mfifo/util_mfifo.v /^ output [15:0] dout_data_0,$/;" p module:util_mfifo +dout_data_0 adi_library/util_rfifo/util_rfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_0,$/;" p module:util_rfifo +dout_data_0 adi_library/util_wfifo/util_wfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_0,$/;" p module:util_wfifo +dout_data_1 adi_library/util_mfifo/util_mfifo.v /^ output [15:0] dout_data_1,$/;" p module:util_mfifo +dout_data_1 adi_library/util_rfifo/util_rfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_1,$/;" p module:util_rfifo +dout_data_1 adi_library/util_wfifo/util_wfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_1,$/;" p module:util_wfifo +dout_data_2 adi_library/util_mfifo/util_mfifo.v /^ output [15:0] dout_data_2,$/;" p module:util_mfifo +dout_data_2 adi_library/util_rfifo/util_rfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_2,$/;" p module:util_rfifo +dout_data_2 adi_library/util_wfifo/util_wfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_2,$/;" p module:util_wfifo +dout_data_3 adi_library/util_mfifo/util_mfifo.v /^ output [15:0] dout_data_3,$/;" p module:util_mfifo +dout_data_3 adi_library/util_rfifo/util_rfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_3,$/;" p module:util_rfifo +dout_data_3 adi_library/util_wfifo/util_wfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_3,$/;" p module:util_wfifo +dout_data_4 adi_library/util_mfifo/util_mfifo.v /^ output [15:0] dout_data_4,$/;" p module:util_mfifo +dout_data_4 adi_library/util_rfifo/util_rfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_4,$/;" p module:util_rfifo +dout_data_4 adi_library/util_wfifo/util_wfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_4,$/;" p module:util_wfifo +dout_data_5 adi_library/util_mfifo/util_mfifo.v /^ output [15:0] dout_data_5,$/;" p module:util_mfifo +dout_data_5 adi_library/util_rfifo/util_rfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_5,$/;" p module:util_rfifo +dout_data_5 adi_library/util_wfifo/util_wfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_5,$/;" p module:util_wfifo +dout_data_6 adi_library/util_mfifo/util_mfifo.v /^ output [15:0] dout_data_6,$/;" p module:util_mfifo +dout_data_6 adi_library/util_rfifo/util_rfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_6,$/;" p module:util_rfifo +dout_data_6 adi_library/util_wfifo/util_wfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_6,$/;" p module:util_wfifo +dout_data_7 adi_library/util_mfifo/util_mfifo.v /^ output [15:0] dout_data_7);$/;" p module:util_mfifo +dout_data_7 adi_library/util_rfifo/util_rfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_7,$/;" p module:util_rfifo +dout_data_7 adi_library/util_wfifo/util_wfifo.v /^ output [DOUT_DATA_WIDTH-1:0] dout_data_7,$/;" p module:util_wfifo +dout_data_s adi_library/util_rfifo/util_rfifo.v /^ wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s;$/;" n module:util_rfifo +dout_data_s adi_library/util_wfifo/util_wfifo.v /^ wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s;$/;" n module:util_wfifo +dout_din_toggle_m1 adi_library/util_mfifo/util_mfifo.v /^ reg dout_din_toggle_m1 = 'd0;$/;" r module:util_mfifo +dout_din_toggle_m2 adi_library/util_mfifo/util_mfifo.v /^ reg dout_din_toggle_m2 = 'd0;$/;" r module:util_mfifo +dout_din_toggle_m3 adi_library/util_mfifo/util_mfifo.v /^ reg dout_din_toggle_m3 = 'd0;$/;" r module:util_mfifo +dout_din_toggle_s adi_library/util_mfifo/util_mfifo.v /^ wire dout_din_toggle_s;$/;" n module:util_mfifo +dout_enable adi_library/util_mfifo/util_mfifo.v /^ reg dout_enable = 'd0;$/;" r module:util_mfifo +dout_enable adi_library/util_rfifo/util_rfifo.v /^ reg [ 7:0] dout_enable = 'd0;$/;" r module:util_rfifo +dout_enable adi_library/util_wfifo/util_wfifo.v /^ reg [ 7:0] dout_enable = 'd0;$/;" r module:util_wfifo +dout_enable_0 adi_library/util_rfifo/util_rfifo.v /^ input dout_enable_0,$/;" p module:util_rfifo +dout_enable_0 adi_library/util_wfifo/util_wfifo.v /^ output dout_enable_0,$/;" p module:util_wfifo +dout_enable_1 adi_library/util_rfifo/util_rfifo.v /^ input dout_enable_1,$/;" p module:util_rfifo +dout_enable_1 adi_library/util_wfifo/util_wfifo.v /^ output dout_enable_1,$/;" p module:util_wfifo +dout_enable_2 adi_library/util_rfifo/util_rfifo.v /^ input dout_enable_2,$/;" p module:util_rfifo +dout_enable_2 adi_library/util_wfifo/util_wfifo.v /^ output dout_enable_2,$/;" p module:util_wfifo +dout_enable_3 adi_library/util_rfifo/util_rfifo.v /^ input dout_enable_3,$/;" p module:util_rfifo +dout_enable_3 adi_library/util_wfifo/util_wfifo.v /^ output dout_enable_3,$/;" p module:util_wfifo +dout_enable_4 adi_library/util_rfifo/util_rfifo.v /^ input dout_enable_4,$/;" p module:util_rfifo +dout_enable_4 adi_library/util_wfifo/util_wfifo.v /^ output dout_enable_4,$/;" p module:util_wfifo +dout_enable_5 adi_library/util_rfifo/util_rfifo.v /^ input dout_enable_5,$/;" p module:util_rfifo +dout_enable_5 adi_library/util_wfifo/util_wfifo.v /^ output dout_enable_5,$/;" p module:util_wfifo +dout_enable_6 adi_library/util_rfifo/util_rfifo.v /^ input dout_enable_6,$/;" p module:util_rfifo +dout_enable_6 adi_library/util_wfifo/util_wfifo.v /^ output dout_enable_6,$/;" p module:util_wfifo +dout_enable_7 adi_library/util_rfifo/util_rfifo.v /^ input dout_enable_7,$/;" p module:util_rfifo +dout_enable_7 adi_library/util_wfifo/util_wfifo.v /^ output dout_enable_7,$/;" p module:util_wfifo +dout_enable_m1 adi_library/util_wfifo/util_wfifo.v /^ reg [ 7:0] dout_enable_m1 = 'd0;$/;" r module:util_wfifo +dout_enable_s adi_library/util_rfifo/util_rfifo.v /^ wire [ 7:0] dout_enable_s;$/;" n module:util_rfifo +dout_fft_piloti hdl/Chn_Estimate.v /^wire[7:0] dout_fft_piloti;$/;" n module:Chn_Estimate +dout_fft_pilotq hdl/Chn_Estimate.v /^wire[7:0] dout_fft_pilotq;$/;" n module:Chn_Estimate +dout_i hdl/phase_adjust.v /^ output [9:0] dout_i,$/;" p module:phase_adjust +dout_init adi_library/util_rfifo/util_rfifo.v /^ reg dout_init = 'd0;$/;" r module:util_rfifo +dout_init_s adi_library/util_rfifo/util_rfifo.v /^ wire dout_init_s;$/;" n module:util_rfifo +dout_ld adi_library/util_mfifo/util_mfifo.v /^ reg dout_ld = 'd0;$/;" r module:util_mfifo +dout_ld_d adi_library/util_mfifo/util_mfifo.v /^ reg dout_ld_d = 'd0;$/;" r module:util_mfifo +dout_lut hdl/DAGC_v2.v /^ wire [13:0] dout_lut;$/;" n module:DAGC_v2 +dout_nd hdl/trunc_25to12_2dly.v /^ output reg dout_nd = 0;$/;" p module:trunc_25to12_2dly +dout_ovf adi_library/util_wfifo/util_wfifo.v /^ input dout_ovf);$/;" p module:util_wfifo +dout_ovf_d adi_library/util_wfifo/util_wfifo.v /^ reg dout_ovf_d = 'd0;$/;" r module:util_wfifo +dout_pilot01 hdl/freqestm.v /^ wire [19:0] dout_pilot01;$/;" n module:freqestm +dout_pilot02 hdl/freqestm.v /^ wire [19:0] dout_pilot02;$/;" n module:freqestm +dout_pilot1i hdl/data_ow.v /^ wire [9:0] dout_pilot1i;$/;" n module:data_ow +dout_pilot1q hdl/data_ow.v /^ wire [9:0] dout_pilot1q;$/;" n module:data_ow +dout_pilot2i hdl/data_ow.v /^ wire [9:0] dout_pilot2i;$/;" n module:data_ow +dout_pilot2q hdl/data_ow.v /^ wire [9:0] dout_pilot2q;$/;" n module:data_ow +dout_q hdl/phase_adjust.v /^ output [9:0] dout_q$/;" p module:phase_adjust +dout_r adi_library/util_var_fifo/util_var_fifo.v /^ input [DATA_WIDTH-1:0] dout_r);$/;" p module:util_var_fifo +dout_raddr adi_library/util_mfifo/util_mfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0;$/;" r module:util_mfifo +dout_raddr adi_library/util_rfifo/util_rfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0;$/;" r module:util_rfifo +dout_raddr adi_library/util_wfifo/util_wfifo.v /^ reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd8;$/;" r module:util_wfifo +dout_raddr_max_s adi_library/util_mfifo/util_mfifo.v /^ wire dout_raddr_max_s;$/;" n module:util_mfifo +dout_rd_d adi_library/util_wfifo/util_wfifo.v /^ reg dout_rd_d = 'd0;$/;" r module:util_wfifo +dout_rd_s adi_library/util_mfifo/util_mfifo.v /^ wire dout_rd_s;$/;" n module:util_mfifo +dout_rdata adi_library/util_rfifo/util_rfifo.v /^ reg [(DATA_WIDTH-1):0] dout_rdata = 'd0;$/;" r module:util_rfifo +dout_rdata adi_library/util_wfifo/util_wfifo.v /^ reg [(DATA_WIDTH-1):0] dout_rdata = 'd0;$/;" r module:util_wfifo +dout_rdata_0 adi_library/util_mfifo/util_mfifo.v /^ reg [(DIN_DATA_WIDTH-1):0] dout_rdata_0 = 'd0;$/;" r module:util_mfifo +dout_rdata_1 adi_library/util_mfifo/util_mfifo.v /^ reg [(DIN_DATA_WIDTH-1):0] dout_rdata_1 = 'd0;$/;" r module:util_mfifo +dout_rdata_2 adi_library/util_mfifo/util_mfifo.v /^ reg [(DIN_DATA_WIDTH-1):0] dout_rdata_2 = 'd0;$/;" r module:util_mfifo +dout_rdata_3 adi_library/util_mfifo/util_mfifo.v /^ reg [(DIN_DATA_WIDTH-1):0] dout_rdata_3 = 'd0;$/;" r module:util_mfifo +dout_rdata_4 adi_library/util_mfifo/util_mfifo.v /^ reg [(DIN_DATA_WIDTH-1):0] dout_rdata_4 = 'd0;$/;" r module:util_mfifo +dout_rdata_5 adi_library/util_mfifo/util_mfifo.v /^ reg [(DIN_DATA_WIDTH-1):0] dout_rdata_5 = 'd0;$/;" r module:util_mfifo +dout_rdata_6 adi_library/util_mfifo/util_mfifo.v /^ reg [(DIN_DATA_WIDTH-1):0] dout_rdata_6 = 'd0;$/;" r module:util_mfifo +dout_rdata_7 adi_library/util_mfifo/util_mfifo.v /^ reg [(DIN_DATA_WIDTH-1):0] dout_rdata_7 = 'd0;$/;" r module:util_mfifo +dout_rdata_s adi_library/util_mfifo/util_mfifo.v /^ wire [(DIN_DATA_WIDTH-1):0] dout_rdata_s[0:7];$/;" n module:util_mfifo +dout_rdata_s adi_library/util_rfifo/util_rfifo.v /^ wire [(DATA_WIDTH-1):0] dout_rdata_s;$/;" n module:util_rfifo +dout_rdata_s adi_library/util_wfifo/util_wfifo.v /^ wire [(DATA_WIDTH-1):0] dout_rdata_s;$/;" n module:util_wfifo +dout_req_cnt adi_library/util_wfifo/util_wfifo.v /^ reg [ 3:0] dout_req_cnt = 'd0;$/;" r module:util_wfifo +dout_req_t adi_library/util_rfifo/util_rfifo.v /^ reg dout_req_t = 'd0;$/;" r module:util_rfifo +dout_req_t adi_library/util_wfifo/util_wfifo.v /^ reg dout_req_t = 'd0;$/;" r module:util_wfifo +dout_req_t_m1 adi_library/util_wfifo/util_wfifo.v /^ reg dout_req_t_m1 = 'd0;$/;" r module:util_wfifo +dout_req_t_m2 adi_library/util_wfifo/util_wfifo.v /^ reg dout_req_t_m2 = 'd0;$/;" r module:util_wfifo +dout_req_t_m3 adi_library/util_wfifo/util_wfifo.v /^ reg dout_req_t_m3 = 'd0;$/;" r module:util_wfifo +dout_req_t_s adi_library/util_wfifo/util_wfifo.v /^ wire dout_req_t_s;$/;" n module:util_wfifo +dout_rinit adi_library/util_wfifo/util_wfifo.v /^ reg [(ADDRESS_WIDTH-4):0] dout_rinit = 'd0;$/;" r module:util_wfifo +dout_rst adi_library/util_mfifo/util_mfifo.v /^ input dout_rst,$/;" p module:util_mfifo +dout_rst adi_library/util_rfifo/util_rfifo.v /^ input dout_rst,$/;" p module:util_rfifo +dout_rstn adi_library/util_wfifo/util_wfifo.v /^ input dout_rstn,$/;" p module:util_wfifo +dout_scramble hdl/FrameMerge.v /^ output dout_scramble,$/;" p module:FrameMerge +dout_scramble hdl/RecvTop.v /^ wire dout_scramble;$/;" n module:RecvTop +dout_scramble_d1 hdl/FrameMerge.v /^ reg [0:0] dout_scramble_d1 = 1'd0; \/\/比较误码率$/;" r module:FrameMerge +dout_toggle adi_library/util_mfifo/util_mfifo.v /^ reg dout_toggle = 'd0;$/;" r module:util_mfifo +dout_unf adi_library/util_rfifo/util_rfifo.v /^ output reg dout_unf);$/;" p module:util_rfifo +dout_unf_m1 adi_library/util_rfifo/util_rfifo.v /^ reg dout_unf_m1 = 'd0;$/;" r module:util_rfifo +dout_valid adi_library/util_mfifo/util_mfifo.v /^ output reg dout_valid,$/;" p module:util_mfifo +dout_valid adi_library/util_rfifo/util_rfifo.v /^ reg [ 7:0] dout_valid = 'd0;$/;" r module:util_rfifo +dout_valid adi_library/util_wfifo/util_wfifo.v /^ reg dout_valid = 'd0;$/;" r module:util_wfifo +dout_valid_0 adi_library/util_rfifo/util_rfifo.v /^ input dout_valid_0,$/;" p module:util_rfifo +dout_valid_0 adi_library/util_wfifo/util_wfifo.v /^ output dout_valid_0,$/;" p module:util_wfifo +dout_valid_1 adi_library/util_rfifo/util_rfifo.v /^ input dout_valid_1,$/;" p module:util_rfifo +dout_valid_1 adi_library/util_wfifo/util_wfifo.v /^ output dout_valid_1,$/;" p module:util_wfifo +dout_valid_2 adi_library/util_rfifo/util_rfifo.v /^ input dout_valid_2,$/;" p module:util_rfifo +dout_valid_2 adi_library/util_wfifo/util_wfifo.v /^ output dout_valid_2,$/;" p module:util_wfifo +dout_valid_3 adi_library/util_rfifo/util_rfifo.v /^ input dout_valid_3,$/;" p module:util_rfifo +dout_valid_3 adi_library/util_wfifo/util_wfifo.v /^ output dout_valid_3,$/;" p module:util_wfifo +dout_valid_4 adi_library/util_rfifo/util_rfifo.v /^ input dout_valid_4,$/;" p module:util_rfifo +dout_valid_4 adi_library/util_wfifo/util_wfifo.v /^ output dout_valid_4,$/;" p module:util_wfifo +dout_valid_5 adi_library/util_rfifo/util_rfifo.v /^ input dout_valid_5,$/;" p module:util_rfifo +dout_valid_5 adi_library/util_wfifo/util_wfifo.v /^ output dout_valid_5,$/;" p module:util_wfifo +dout_valid_6 adi_library/util_rfifo/util_rfifo.v /^ input dout_valid_6,$/;" p module:util_rfifo +dout_valid_6 adi_library/util_wfifo/util_wfifo.v /^ output dout_valid_6,$/;" p module:util_wfifo +dout_valid_7 adi_library/util_rfifo/util_rfifo.v /^ input dout_valid_7,$/;" p module:util_rfifo +dout_valid_7 adi_library/util_wfifo/util_wfifo.v /^ output dout_valid_7,$/;" p module:util_wfifo +dout_valid_i hdl/SCFDE_recv_FrameSync.v /^ wire dout_valid_i;$/;" n module:SCFDE_recv_FrameSync +dout_valid_out_0 adi_library/util_rfifo/util_rfifo.v /^ output dout_valid_out_0,$/;" p module:util_rfifo +dout_valid_out_1 adi_library/util_rfifo/util_rfifo.v /^ output dout_valid_out_1,$/;" p module:util_rfifo +dout_valid_out_2 adi_library/util_rfifo/util_rfifo.v /^ output dout_valid_out_2,$/;" p module:util_rfifo +dout_valid_out_3 adi_library/util_rfifo/util_rfifo.v /^ output dout_valid_out_3,$/;" p module:util_rfifo +dout_valid_out_4 adi_library/util_rfifo/util_rfifo.v /^ output dout_valid_out_4,$/;" p module:util_rfifo +dout_valid_out_5 adi_library/util_rfifo/util_rfifo.v /^ output dout_valid_out_5,$/;" p module:util_rfifo +dout_valid_out_6 adi_library/util_rfifo/util_rfifo.v /^ output dout_valid_out_6,$/;" p module:util_rfifo +dout_valid_out_7 adi_library/util_rfifo/util_rfifo.v /^ output dout_valid_out_7,$/;" p module:util_rfifo +dout_valid_q hdl/SCFDE_recv_FrameSync.v /^ wire dout_valid_q;$/;" n module:SCFDE_recv_FrameSync +dout_valid_s adi_library/util_rfifo/util_rfifo.v /^ wire [ 7:0] dout_valid_s;$/;" n module:util_rfifo +doutb adi_library/common/ad_mem.v /^ output reg [(DATA_WIDTH-1):0] doutb);$/;" p module:ad_mem +doutb adi_library/common/ad_mem_asym.v /^ output reg [B_DATA_WIDTH-1:0] doutb);$/;" p module:ad_mem_asym +doutb hdl/phase_adjust.v /^ wire [19:0] doutb;$/;" n module:phase_adjust +douti hdl/TimeSync_top.v /^ output reg [9:0] douti = 10'd0,$/;" p module:TimeSync_top +doutiA hdl/Interpolation.v /^ output reg [9:0] doutiA = 10'd0,$/;" p module:Interpolation +doutiB hdl/Interpolation.v /^ output [9:0] doutiB,$/;" p module:Interpolation +doutiC hdl/Interpolation.v /^ output [9:0] doutiC,$/;" p module:Interpolation +doutiD hdl/Interpolation.v /^ output [9:0] doutiD,$/;" p module:Interpolation +douti_16 hdl/TimeSync_top.v /^ wire [9:0] douti_16;$/;" n module:TimeSync_top +douti_4 hdl/TimeSync_top.v /^ wire [9:0] douti_4;$/;" n module:TimeSync_top +doutq hdl/TimeSync_top.v /^ output reg [9:0] doutq = 10'd0,$/;" p module:TimeSync_top +doutqA hdl/Interpolation.v /^ output reg [9:0] doutqA = 10'd0,$/;" p module:Interpolation +doutqB hdl/Interpolation.v /^ output [9:0] doutqB,$/;" p module:Interpolation +doutqC hdl/Interpolation.v /^ output [9:0] doutqC,$/;" p module:Interpolation +doutqD hdl/Interpolation.v /^ output [9:0] doutqD$/;" p module:Interpolation +doutq_16 hdl/TimeSync_top.v /^ wire [9:0] doutq_16;$/;" n module:TimeSync_top +doutq_4 hdl/TimeSync_top.v /^ wire [9:0] doutq_4;$/;" n module:TimeSync_top +dp adi_library/common/up_adc_channel.v /^ reg [15:0] dp;$/;" r function:up_adc_channel.sm2tc +dp adi_library/common/up_dac_channel.v /^ reg [15:0] dp;$/;" r function:up_dac_channel.sm2tc +dst_lsb adi_library/common/ad_perfect_shuffle.v /^ localparam dst_lsb = (i + j * NUM_GROUPS) * WORD_WIDTH;$/;" c block:ad_perfect_shuffle.shuffle_outer.shuffle_inner +duplex_mode adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ output reg duplex_mode);$/;" p module:mdc_mdio +duplex_mode adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ wire duplex_mode; \/\/ 1 full, 0 half$/;" n module:util_gmii_to_rgmii +early_tlast adi_library/axi_dmac/data_mover.v /^wire early_tlast;$/;" n module:dmac_data_mover +empty hdl/DAGC_v2.v /^ wire empty;$/;" n module:DAGC_v2 +empty hdl/freqestm.v /^ wire empty;$/;" n module:freqestm +empty_data1i hdl/SC_FDE_TOP.v /^ wire empty_data1i;$/;" n module:SC_FDE_TOP +empty_data1q hdl/SC_FDE_TOP.v /^ wire empty_data1q;$/;" n module:SC_FDE_TOP +empty_data2i hdl/SC_FDE_TOP.v /^ wire empty_data2i;$/;" n module:SC_FDE_TOP +empty_data2q hdl/SC_FDE_TOP.v /^ wire empty_data2q;$/;" n module:SC_FDE_TOP +empty_pilot1i hdl/data_ow.v /^ wire empty_pilot1i;$/;" n module:data_ow +empty_pilot1q hdl/data_ow.v /^ wire empty_pilot1q;$/;" n module:data_ow +empty_pilot2i hdl/data_ow.v /^ wire empty_pilot2i;$/;" n module:data_ow +empty_pilot2q hdl/data_ow.v /^ wire empty_pilot2q;$/;" n module:data_ow +en adi_library/axi_dmac/dest_fifo_inf.v /^ input en,$/;" p module:dmac_dest_fifo_inf +en adi_library/axi_dmac/src_fifo_inf.v /^ input en,$/;" p module:dmac_src_fifo_inf +en_r adi_library/util_var_fifo/util_var_fifo.v /^ output en_r,$/;" p module:util_var_fifo +en_row_01 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_01 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_01 hdl/Out_Process_R12.v /^ input [63:0] en_row_01,$/;" p module:Out_Process_R12 +en_row_01_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_01_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_02 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_02 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_02 hdl/Out_Process_R12.v /^ input [63:0] en_row_02,$/;" p module:Out_Process_R12 +en_row_02_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_02_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_03 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_03 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_03 hdl/Out_Process_R12.v /^ input [63:0] en_row_03,$/;" p module:Out_Process_R12 +en_row_03_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_03_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_04 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_04 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_04 hdl/Out_Process_R12.v /^ input [63:0] en_row_04,$/;" p module:Out_Process_R12 +en_row_04_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_04_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_05 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_05 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_05 hdl/Out_Process_R12.v /^ input [63:0] en_row_05,$/;" p module:Out_Process_R12 +en_row_05_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_05_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_06 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_06 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_06 hdl/Out_Process_R12.v /^ input [63:0] en_row_06,$/;" p module:Out_Process_R12 +en_row_06_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_06_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_07 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_07 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_07 hdl/Out_Process_R12.v /^ input [63:0] en_row_07,$/;" p module:Out_Process_R12 +en_row_07_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_07_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_08 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_08 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_08 hdl/Out_Process_R12.v /^ input [63:0] en_row_08,$/;" p module:Out_Process_R12 +en_row_08_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_08_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_09 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_09 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_09 hdl/Out_Process_R12.v /^ input [63:0] en_row_09,$/;" p module:Out_Process_R12 +en_row_09_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_09_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_10 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_10 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_10 hdl/Out_Process_R12.v /^ input [63:0] en_row_10,$/;" p module:Out_Process_R12 +en_row_10_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_10_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_11 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_11 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_11 hdl/Out_Process_R12.v /^ input [63:0] en_row_11,$/;" p module:Out_Process_R12 +en_row_11_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_11_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_12 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_12 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_12 hdl/Out_Process_R12.v /^ input [63:0] en_row_12,$/;" p module:Out_Process_R12 +en_row_12_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_12_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_13 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_13 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_13 hdl/Out_Process_R12.v /^ input [63:0] en_row_13,$/;" p module:Out_Process_R12 +en_row_13_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_13_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_14 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_14 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_14 hdl/Out_Process_R12.v /^ input [63:0] en_row_14,$/;" p module:Out_Process_R12 +en_row_14_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_14_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_15 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_15 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_15 hdl/Out_Process_R12.v /^ input [63:0] en_row_15,$/;" p module:Out_Process_R12 +en_row_15_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_15_tem = 64'd0; $/;" r module:Out_Process_R12 +en_row_16 hdl/CCSDS_LDPC_ENC_R12.v /^ reg [63:0] en_row_16 = 64'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +en_row_16 hdl/Out_Process_R12.v /^ input [63:0] en_row_16,$/;" p module:Out_Process_R12 +en_row_16_tem hdl/Out_Process_R12.v /^ reg [63:0] en_row_16_tem = 64'd0; $/;" r module:Out_Process_R12 +en_w adi_library/util_var_fifo/util_var_fifo.v /^ output en_w,$/;" p module:util_var_fifo +enable adi_library/axi_dmac/address_generator.v /^ input enable,$/;" p module:dmac_address_generator +enable adi_library/axi_dmac/dest_axi_mm.v /^ input enable,$/;" p module:dmac_dest_mm_axi +enable adi_library/axi_dmac/dest_axi_stream.v /^ input enable,$/;" p module:dmac_dest_axi_stream +enable adi_library/axi_dmac/dest_fifo_inf.v /^ input enable,$/;" p module:dmac_dest_fifo_inf +enable adi_library/axi_dmac/request_generator.v /^ input enable,$/;" p module:dmac_request_generator +enable adi_library/axi_dmac/response_generator.v /^ input enable,$/;" p module:dmac_response_generator +enable adi_library/axi_dmac/response_handler.v /^ input enable,$/;" p module:dmac_response_handler +enable adi_library/axi_dmac/src_axi_mm.v /^ input enable,$/;" p module:dmac_src_mm_axi +enable adi_library/axi_dmac/src_axi_stream.v /^ input enable,$/;" p module:dmac_src_axi_stream +enable adi_library/axi_dmac/src_fifo_inf.v /^ input enable,$/;" p module:dmac_src_fifo_inf +enable adi_library/common/util_dec256sinc24b.v /^ reg enable = 1'b0;$/;" r module:util_dec256sinc24b +enable adi_library/util_cic/cic_comb.v /^ input [NUM_STAGES-1:0] enable,$/;" p module:cic_comb +enable adi_library/util_pack/tb/cpack_tb.v /^ reg [NUM_OF_CHANNELS-1:0] enable = 'h1;$/;" r module:cpack_tb +enable adi_library/util_pack/tb/underflow_tb.v /^ reg [NUM_OF_CHANNELS-1:0] enable = {NUM_OF_CHANNELS{1'b1}};$/;" r module:upack2_underflow_tb +enable adi_library/util_pack/tb/upack_tb.v /^ reg [NUM_OF_CHANNELS-1:0] enable = 'h1;$/;" r module:upack_tb +enable adi_library/util_pack/util_cpack2/util_cpack2.v /^wire [REAL_NUM_OF_CHANNELS-1:0] enable;$/;" n module:util_cpack2 +enable adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ input [NUM_OF_CHANNELS-1:0] enable,$/;" p module:util_cpack2_impl +enable adi_library/util_pack/util_pack_common/pack_shell.v /^ input [NUM_OF_CHANNELS-1:0] enable,$/;" p module:pack_shell +enable adi_library/util_pack/util_upack2/util_upack2_impl.v /^ input [NUM_OF_CHANNELS-1:0] enable,$/;" p module:util_upack2_impl +enable1 hdl/TSync_Abs_new16.v /^ reg enable1 = 0;$/;" r module:TSync_Abs_new16 +enable_0 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_0,$/;" p module:util_cpack2 +enable_0 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_0,$/;" p module:util_upack2 +enable_1 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_1,$/;" p module:util_cpack2 +enable_1 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_1,$/;" p module:util_upack2 +enable_10 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_10,$/;" p module:util_cpack2 +enable_10 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_10,$/;" p module:util_upack2 +enable_11 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_11,$/;" p module:util_cpack2 +enable_11 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_11,$/;" p module:util_upack2 +enable_12 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_12,$/;" p module:util_cpack2 +enable_12 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_12,$/;" p module:util_upack2 +enable_13 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_13,$/;" p module:util_cpack2 +enable_13 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_13,$/;" p module:util_upack2 +enable_14 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_14,$/;" p module:util_cpack2 +enable_14 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_14,$/;" p module:util_upack2 +enable_15 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_15,$/;" p module:util_cpack2 +enable_15 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_15,$/;" p module:util_upack2 +enable_16 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_16,$/;" p module:util_cpack2 +enable_16 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_16,$/;" p module:util_upack2 +enable_17 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_17,$/;" p module:util_cpack2 +enable_17 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_17,$/;" p module:util_upack2 +enable_18 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_18,$/;" p module:util_cpack2 +enable_18 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_18,$/;" p module:util_upack2 +enable_19 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_19,$/;" p module:util_cpack2 +enable_19 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_19,$/;" p module:util_upack2 +enable_2 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_2,$/;" p module:util_cpack2 +enable_2 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_2,$/;" p module:util_upack2 +enable_20 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_20,$/;" p module:util_cpack2 +enable_20 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_20,$/;" p module:util_upack2 +enable_21 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_21,$/;" p module:util_cpack2 +enable_21 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_21,$/;" p module:util_upack2 +enable_22 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_22,$/;" p module:util_cpack2 +enable_22 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_22,$/;" p module:util_upack2 +enable_23 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_23,$/;" p module:util_cpack2 +enable_23 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_23,$/;" p module:util_upack2 +enable_24 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_24,$/;" p module:util_cpack2 +enable_24 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_24,$/;" p module:util_upack2 +enable_25 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_25,$/;" p module:util_cpack2 +enable_25 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_25,$/;" p module:util_upack2 +enable_26 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_26,$/;" p module:util_cpack2 +enable_26 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_26,$/;" p module:util_upack2 +enable_27 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_27,$/;" p module:util_cpack2 +enable_27 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_27,$/;" p module:util_upack2 +enable_28 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_28,$/;" p module:util_cpack2 +enable_28 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_28,$/;" p module:util_upack2 +enable_29 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_29,$/;" p module:util_cpack2 +enable_29 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_29,$/;" p module:util_upack2 +enable_3 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_3,$/;" p module:util_cpack2 +enable_3 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_3,$/;" p module:util_upack2 +enable_30 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_30,$/;" p module:util_cpack2 +enable_30 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_30,$/;" p module:util_upack2 +enable_31 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_31,$/;" p module:util_cpack2 +enable_31 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_31,$/;" p module:util_upack2 +enable_32 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_32,$/;" p module:util_cpack2 +enable_32 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_32,$/;" p module:util_upack2 +enable_33 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_33,$/;" p module:util_cpack2 +enable_33 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_33,$/;" p module:util_upack2 +enable_34 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_34,$/;" p module:util_cpack2 +enable_34 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_34,$/;" p module:util_upack2 +enable_35 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_35,$/;" p module:util_cpack2 +enable_35 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_35,$/;" p module:util_upack2 +enable_36 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_36,$/;" p module:util_cpack2 +enable_36 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_36,$/;" p module:util_upack2 +enable_37 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_37,$/;" p module:util_cpack2 +enable_37 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_37,$/;" p module:util_upack2 +enable_38 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_38,$/;" p module:util_cpack2 +enable_38 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_38,$/;" p module:util_upack2 +enable_39 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_39,$/;" p module:util_cpack2 +enable_39 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_39,$/;" p module:util_upack2 +enable_4 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_4,$/;" p module:util_cpack2 +enable_4 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_4,$/;" p module:util_upack2 +enable_40 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_40,$/;" p module:util_cpack2 +enable_40 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_40,$/;" p module:util_upack2 +enable_41 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_41,$/;" p module:util_cpack2 +enable_41 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_41,$/;" p module:util_upack2 +enable_42 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_42,$/;" p module:util_cpack2 +enable_42 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_42,$/;" p module:util_upack2 +enable_43 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_43,$/;" p module:util_cpack2 +enable_43 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_43,$/;" p module:util_upack2 +enable_44 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_44,$/;" p module:util_cpack2 +enable_44 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_44,$/;" p module:util_upack2 +enable_45 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_45,$/;" p module:util_cpack2 +enable_45 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_45,$/;" p module:util_upack2 +enable_46 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_46,$/;" p module:util_cpack2 +enable_46 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_46,$/;" p module:util_upack2 +enable_47 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_47,$/;" p module:util_cpack2 +enable_47 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_47,$/;" p module:util_upack2 +enable_48 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_48,$/;" p module:util_cpack2 +enable_48 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_48,$/;" p module:util_upack2 +enable_49 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_49,$/;" p module:util_cpack2 +enable_49 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_49,$/;" p module:util_upack2 +enable_5 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_5,$/;" p module:util_cpack2 +enable_5 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_5,$/;" p module:util_upack2 +enable_50 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_50,$/;" p module:util_cpack2 +enable_50 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_50,$/;" p module:util_upack2 +enable_51 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_51,$/;" p module:util_cpack2 +enable_51 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_51,$/;" p module:util_upack2 +enable_52 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_52,$/;" p module:util_cpack2 +enable_52 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_52,$/;" p module:util_upack2 +enable_53 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_53,$/;" p module:util_cpack2 +enable_53 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_53,$/;" p module:util_upack2 +enable_54 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_54,$/;" p module:util_cpack2 +enable_54 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_54,$/;" p module:util_upack2 +enable_55 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_55,$/;" p module:util_cpack2 +enable_55 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_55,$/;" p module:util_upack2 +enable_56 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_56,$/;" p module:util_cpack2 +enable_56 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_56,$/;" p module:util_upack2 +enable_57 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_57,$/;" p module:util_cpack2 +enable_57 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_57,$/;" p module:util_upack2 +enable_58 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_58,$/;" p module:util_cpack2 +enable_58 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_58,$/;" p module:util_upack2 +enable_59 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_59,$/;" p module:util_cpack2 +enable_59 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_59,$/;" p module:util_upack2 +enable_6 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_6,$/;" p module:util_cpack2 +enable_6 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_6,$/;" p module:util_upack2 +enable_60 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_60,$/;" p module:util_cpack2 +enable_60 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_60,$/;" p module:util_upack2 +enable_61 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_61,$/;" p module:util_cpack2 +enable_61 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_61,$/;" p module:util_upack2 +enable_62 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_62,$/;" p module:util_cpack2 +enable_62 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_62,$/;" p module:util_upack2 +enable_63 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_63,$/;" p module:util_cpack2 +enable_63 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_63,$/;" p module:util_upack2 +enable_7 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_7,$/;" p module:util_cpack2 +enable_7 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_7,$/;" p module:util_upack2 +enable_8 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_8,$/;" p module:util_cpack2 +enable_8 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_8,$/;" p module:util_upack2 +enable_9 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input enable_9,$/;" p module:util_cpack2 +enable_9 adi_library/util_pack/util_upack2/util_upack2.v /^ input enable_9,$/;" p module:util_upack2 +enable_count adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [SAMPLE_ADDRESS_WIDTH-1:0] enable_count = 'h0;$/;" r module:pack_shell +enable_in_0 adi_library/common/ad_bus_mux.v /^ input enable_in_0,$/;" p module:ad_bus_mux +enable_in_1 adi_library/common/ad_bus_mux.v /^ input enable_in_1,$/;" p module:ad_bus_mux +enable_int adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [NUM_OF_CHANNELS-1:0] enable_int = 'h00;$/;" r module:pack_shell +enable_out adi_library/common/ad_bus_mux.v /^ output enable_out,$/;" p module:ad_bus_mux +enable_s adi_library/util_pack/util_cpack2/util_cpack2.v /^wire [63:0] enable_s;$/;" n module:util_cpack2 +enable_s adi_library/util_pack/util_upack2/util_upack2.v /^wire [63:0] enable_s;$/;" n module:util_upack2 +enabled adi_library/axi_dmac/address_generator.v /^ output reg enabled,$/;" p module:dmac_address_generator +enabled adi_library/axi_dmac/dest_axi_mm.v /^ output enabled,$/;" p module:dmac_dest_mm_axi +enabled adi_library/axi_dmac/dest_axi_stream.v /^ output enabled,$/;" p module:dmac_dest_axi_stream +enabled adi_library/axi_dmac/dest_fifo_inf.v /^ output enabled,$/;" p module:dmac_dest_fifo_inf +enabled adi_library/axi_dmac/response_generator.v /^ output reg enabled,$/;" p module:dmac_response_generator +enabled adi_library/axi_dmac/response_handler.v /^ output reg enabled,$/;" p module:dmac_response_handler +enabled adi_library/axi_dmac/src_axi_mm.v /^ output reg enabled = 1'b0,$/;" p module:dmac_src_mm_axi +enabled adi_library/axi_dmac/src_axi_stream.v /^ output enabled,$/;" p module:dmac_src_axi_stream +enabled adi_library/axi_dmac/src_fifo_inf.v /^ output enabled,$/;" p module:dmac_src_fifo_inf +enabled_all adi_library/axi_dmac/axi_dmac_reset_manager.v /^wire enabled_all;$/;" n module:axi_dmac_reset_manager +enabled_dest adi_library/axi_dmac/axi_dmac_reset_manager.v /^wire enabled_dest;$/;" n module:axi_dmac_reset_manager +enabled_dest adi_library/axi_dmac/request_arb.v /^wire enabled_dest;$/;" n module:dmac_request_arb +enabled_src adi_library/axi_dmac/axi_dmac_reset_manager.v /^wire enabled_src;$/;" n module:axi_dmac_reset_manager +enabled_src adi_library/axi_dmac/request_arb.v /^wire enabled_src;$/;" n module:dmac_request_arb +enc_control hdl/enc_control.v /^module enc_control #($/;" m +enc_dout sim/tb_enc_control.v /^ wire [15:0] enc_dout;$/;" n module:tb_enc_control +enc_dout_intr sim/tb_enc_control.v /^ wire enc_dout_intr;$/;" n module:tb_enc_control +enc_dout_valid sim/tb_enc_control.v /^ wire enc_dout_valid;$/;" n module:tb_enc_control +enc_fifo_dout_map hdl/system_top.v /^ wire [31:0] enc_fifo_dout_map;$/;" n module:system_top +enc_fifo_dout_map sim/TB_sys.v /^ wire [31:0] enc_fifo_dout_map;$/;" n module:TB_sys +enc_fifo_dout_map sim/tb_tx_with_enc.v /^ wire [31:0] enc_fifo_dout_map;$/;" n module:tb_tx_with_enc +enc_fifo_empty hdl/system_top.v /^ wire enc_fifo_empty;$/;" n module:system_top +enc_fifo_empty sim/TB_sys.v /^ wire enc_fifo_empty;$/;" n module:TB_sys +enc_fifo_empty sim/tb_tx_with_enc.v /^ wire enc_fifo_empty;$/;" n module:tb_tx_with_enc +enc_fifo_rd_en hdl/system_top.v /^ wire enc_fifo_rd_en;$/;" n module:system_top +enc_fifo_rd_en sim/TB_sys.v /^ wire enc_fifo_rd_en;$/;" n module:TB_sys +enc_fifo_rd_en sim/tb_tx_with_enc.v /^ wire enc_fifo_rd_en;$/;" n module:tb_tx_with_enc +encode_din hdl/Out_Process_R12.v /^ input encode_din, \/\/将输入信息比特输出$/;" p module:Out_Process_R12 +encode_out hdl/CCSDS_LDPC_ENC_R12.v /^ wire encode_out;$/;" n module:CCSDS_LDPC_ENC_R12 +encode_out hdl/Out_Process_R12.v /^ output reg encode_out = 1'd0,$/;" p module:Out_Process_R12 +encode_rdy hdl/CCSDS_LDPC_ENC_R12.v /^ wire encode_rdy;$/;" n module:CCSDS_LDPC_ENC_R12 +encode_rdy hdl/Out_Process_R12.v /^ output reg encode_rdy = 1'd0$/;" p module:Out_Process_R12 +encode_sync_out hdl/CCSDS_LDPC_ENC_R12.v /^ wire encode_sync_out;$/;" n module:CCSDS_LDPC_ENC_R12 +encode_sync_out hdl/Out_Process_R12.v /^ output reg encode_sync_out = 1'd0,$/;" p module:Out_Process_R12 +encode_valid hdl/CCSDS_LDPC_ENC_R12.v /^ reg encode_valid = 1'd0; $/;" r module:CCSDS_LDPC_ENC_R12 +encode_valid hdl/Out_Process_R12.v /^ input encode_valid, \/\/下降沿表示完成码字计算$/;" p module:Out_Process_R12 +encode_valid_d1 hdl/Out_Process_R12.v /^ reg encode_valid_d1 = 1'd0; reg encode_valid_d2 = 1'd0;$/;" r module:Out_Process_R12 +encode_valid_d2 hdl/Out_Process_R12.v /^ reg encode_valid_d1 = 1'd0; reg encode_valid_d2 = 1'd0;$/;" r module:Out_Process_R12 +end_of_period_s adi_library/common/util_pulse_gen.v /^ wire end_of_period_s;$/;" n module:util_pulse_gen +end_of_word adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire end_of_word;$/;" n module:spi_engine_execution +eot adi_library/axi_dmac/address_generator.v /^ input eot,$/;" p module:dmac_address_generator +eot adi_library/axi_dmac/data_mover.v /^ input eot,$/;" p module:dmac_data_mover +eot adi_library/axi_dmac/request_arb.v /^ output eot,$/;" p module:dmac_request_arb +eot adi_library/axi_dmac/request_generator.v /^ output eot$/;" p module:dmac_request_generator +eot adi_library/axi_dmac/response_generator.v /^ input eot,$/;" p module:dmac_response_generator +eot adi_library/axi_dmac/response_handler.v /^ input eot,$/;" p module:dmac_response_handler +eot adi_library/axi_dmac/src_axi_stream.v /^ input eot,$/;" p module:dmac_src_axi_stream +eot adi_library/axi_dmac/src_fifo_inf.v /^ input eot,$/;" p module:dmac_src_fifo_inf +eot_id adi_library/axi_dmac/2d_transfer.v /^reg [1:0] eot_id = 'h00;$/;" r module:dmac_2d_transfer +eot_mem_dest adi_library/axi_dmac/request_arb.v /^reg eot_mem_dest[0:2**ID_WIDTH-1];$/;" r module:dmac_request_arb +eot_mem_src adi_library/axi_dmac/request_arb.v /^reg eot_mem_src[0:2**ID_WIDTH-1];$/;" r module:dmac_request_arb +event_data_in_channel_halt hdl/SC_FDE_TOP.v /^ wire event_data_in_channel_halt;$/;" n module:SC_FDE_TOP +event_data_in_channel_halt_ifft hdl/SC_FDE_TOP.v /^ wire event_data_in_channel_halt_ifft;$/;" n module:SC_FDE_TOP +event_data_out_channel_halt hdl/SC_FDE_TOP.v /^ wire event_data_out_channel_halt;$/;" n module:SC_FDE_TOP +event_data_out_channel_halt_ifft hdl/SC_FDE_TOP.v /^ wire event_data_out_channel_halt_ifft;$/;" n module:SC_FDE_TOP +event_frame_started hdl/SC_FDE_TOP.v /^ wire event_frame_started;$/;" n module:SC_FDE_TOP +event_frame_started_ifft hdl/SC_FDE_TOP.v /^ wire event_frame_started_ifft;$/;" n module:SC_FDE_TOP +event_status_channel_halt hdl/SC_FDE_TOP.v /^ wire event_status_channel_halt;$/;" n module:SC_FDE_TOP +event_status_channel_halt_ifft hdl/SC_FDE_TOP.v /^ wire event_status_channel_halt_ifft;$/;" n module:SC_FDE_TOP +event_tlast_missing hdl/SC_FDE_TOP.v /^ wire event_tlast_missing;$/;" n module:SC_FDE_TOP +event_tlast_missing_ifft hdl/SC_FDE_TOP.v /^ wire event_tlast_missing_ifft;$/;" n module:SC_FDE_TOP +event_tlast_unexpected hdl/SC_FDE_TOP.v /^ wire event_tlast_unexpected;$/;" n module:SC_FDE_TOP +event_tlast_unexpected_ifft hdl/SC_FDE_TOP.v /^ wire event_tlast_unexpected_ifft;$/;" n module:SC_FDE_TOP +exec_chipselect_cmd adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;$/;" n module:spi_engine_execution +exec_cmd adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire exec_cmd = cmd_ready && cmd_valid;$/;" n module:spi_engine_execution +exec_misc_cmd adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;$/;" n module:spi_engine_execution +exec_sync_cmd adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;$/;" n module:spi_engine_execution +exec_transfer_cmd adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;$/;" n module:spi_engine_execution +exec_write_cmd adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;$/;" n module:spi_engine_execution +expected adi_library/axi_dmac/tb/regmap_tb.v /^ reg [31:0] expected;$/;" r task:dmac_regmap_tb.read_reg_check +expected_fifo_rd_data adi_library/util_pack/tb/upack_tb.v /^ reg [NUM_OF_PORTS*8-1:0] expected_fifo_rd_data = 'h00;$/;" r module:upack_tb +expected_packed_fifo_wr_data adi_library/util_pack/tb/cpack_tb.v /^ reg [NUM_OF_PORTS*8-1:0] expected_packed_fifo_wr_data;$/;" r module:cpack_tb +expected_reg_mem adi_library/axi_dmac/tb/regmap_tb.v /^ reg [31:0] expected_reg_mem[0:NUM_REGS-1];$/;" r module:dmac_regmap_tb +ext_data_in adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_in;$/;" n block:pack_shell.gen_input_buffer +ext_data_out adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_out;$/;" n block:pack_shell.gen_input_buffer +ext_data_shuffled adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_shuffled;$/;" n block:pack_shell.gen_input_buffer +ext_prefix_count adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [(SAMPLE_ADDRESS_WIDTH+1)*(2*NUM_OF_SAMPLES)-1:0] ext_prefix_count;$/;" n block:pack_shell.gen_input_buffer +failed adi_library/axi_dmac/tb/axi_write_slave.v /^reg failed = 'b0;$/;" r module:axi_write_slave +failed adi_library/axi_dmac/tb/tb_base.v /^ reg failed = 1'b0;$/;" r +failed adi_library/util_pack/tb/tb_base.v /^ reg failed = 1'b0;$/;" r +ff_m1 adi_library/common/ad_edge_detect.v /^ reg ff_m1 = 0;$/;" r module:ad_edge_detect +ff_m2 adi_library/common/ad_edge_detect.v /^ reg ff_m2 = 0;$/;" r module:ad_edge_detect +fft_256 hdl/SC_FDE_TOP.v /^ fft_256 fft_256 ($/;" i module:SC_FDE_TOP typeref:module:fft_256 +fft_config_tready hdl/SC_FDE_TOP.v /^ wire fft_config_tready;$/;" n module:SC_FDE_TOP +fft_config_tvalid hdl/SC_FDE_TOP.v /^ reg fft_config_tvalid = 1'd0;$/;" r module:SC_FDE_TOP +fft_in_i hdl/Chn_Estimate.v /^ output reg [16:0] fft_in_i = 17'd0,$/;" p module:Chn_Estimate +fft_in_i hdl/SC_FDE_TOP.v /^ reg [16:0] fft_in_i = 17'd0;$/;" r module:SC_FDE_TOP +fft_in_i hdl/data_equalizer.v /^ output reg [16:0] fft_in_i = 17'd0,$/;" p module:data_equalizer +fft_in_i_data hdl/SC_FDE_TOP.v /^ wire [16:0] fft_in_i_data;$/;" n module:SC_FDE_TOP +fft_in_i_pilot hdl/SC_FDE_TOP.v /^ wire [16:0] fft_in_i_pilot;$/;" n module:SC_FDE_TOP +fft_in_nd hdl/Chn_Estimate.v /^ output reg fft_in_nd = 1'd0,$/;" p module:Chn_Estimate +fft_in_nd hdl/SC_FDE_TOP.v /^ reg fft_in_nd = 1'd0;$/;" r module:SC_FDE_TOP +fft_in_nd hdl/data_equalizer.v /^ output reg fft_in_nd = 1'd0,$/;" p module:data_equalizer +fft_in_q hdl/Chn_Estimate.v /^ output reg [16:0] fft_in_q = 17'd0,$/;" p module:Chn_Estimate +fft_in_q hdl/SC_FDE_TOP.v /^ reg [16:0] fft_in_q = 17'd0;$/;" r module:SC_FDE_TOP +fft_in_q hdl/data_equalizer.v /^ output reg [16:0] fft_in_q = 17'd0,$/;" p module:data_equalizer +fft_in_q_data hdl/SC_FDE_TOP.v /^ wire [16:0] fft_in_q_data;$/;" n module:SC_FDE_TOP +fft_in_q_pilot hdl/SC_FDE_TOP.v /^ wire [16:0] fft_in_q_pilot;$/;" n module:SC_FDE_TOP +fft_in_tready hdl/SC_FDE_TOP.v /^ wire fft_in_tready;$/;" n module:SC_FDE_TOP +fft_index hdl/Chn_Estimate.v /^ input [7:0] fft_index,$/;" p module:Chn_Estimate +fft_index hdl/SC_FDE_TOP.v /^ wire[7:0] fft_index;$/;" n module:SC_FDE_TOP +fft_index hdl/data_equalizer.v /^ input [7:0] fft_index,$/;" p module:data_equalizer +fft_out_i hdl/Chn_Estimate.v /^ input [25:0] fft_out_i,$/;" p module:Chn_Estimate +fft_out_i hdl/SC_FDE_TOP.v /^ wire[25:0] fft_out_i;$/;" n module:SC_FDE_TOP +fft_out_i hdl/data_equalizer.v /^ input [25:0] fft_out_i,$/;" p module:data_equalizer +fft_out_i_d1 hdl/Chn_Estimate.v /^reg [25:0] fft_out_i_d1 = 26'd0;$/;" r module:Chn_Estimate +fft_out_i_d1 hdl/data_equalizer.v /^ reg [25:0] fft_out_i_d1 = 26'd0;$/;" r module:data_equalizer +fft_out_nd hdl/Chn_Estimate.v /^ input fft_out_nd,$/;" p module:Chn_Estimate +fft_out_nd hdl/SC_FDE_TOP.v /^ wire fft_out_nd;$/;" n module:SC_FDE_TOP +fft_out_nd hdl/data_equalizer.v /^ input fft_out_nd,$/;" p module:data_equalizer +fft_out_nd_d1 hdl/Chn_Estimate.v /^reg fft_out_nd_d1 = 1'd0;$/;" r module:Chn_Estimate +fft_out_nd_d1 hdl/data_equalizer.v /^ reg fft_out_nd_d1 = 1'd0;$/;" r module:data_equalizer +fft_out_q hdl/Chn_Estimate.v /^ input [25:0] fft_out_q,$/;" p module:Chn_Estimate +fft_out_q hdl/SC_FDE_TOP.v /^ wire[25:0] fft_out_q;$/;" n module:SC_FDE_TOP +fft_out_q hdl/data_equalizer.v /^ input [25:0] fft_out_q,$/;" p module:data_equalizer +fft_out_q_d1 hdl/Chn_Estimate.v /^reg [25:0] fft_out_q_d1 = 26'd0;$/;" r module:Chn_Estimate +fft_out_q_d1 hdl/data_equalizer.v /^ reg [25:0] fft_out_q_d1 = 26'd0;$/;" r module:data_equalizer +fft_out_tdata hdl/SC_FDE_TOP.v /^ wire[63:0] fft_out_tdata;$/;" n module:SC_FDE_TOP +fft_pilot_imag hdl/Chn_Estimate.v /^fft_pilot_imag fft_pilot_imag ($/;" i module:Chn_Estimate typeref:module:fft_pilot_imag +fft_pilot_real hdl/Chn_Estimate.v /^fft_pilot_real fft_pilot_real ($/;" i module:Chn_Estimate typeref:module:fft_pilot_real +fifo_active adi_library/util_var_fifo/util_var_fifo.v /^ reg fifo_active = 'd0;$/;" r module:util_var_fifo +fifo_address_gray adi_library/util_axis_fifo/address_gray.v /^module fifo_address_gray #($/;" m +fifo_address_gray_pipelined adi_library/util_axis_fifo/address_gray_pipelined.v /^module fifo_address_gray_pipelined #($/;" m +fifo_address_sync adi_library/util_axis_fifo/address_sync.v /^module fifo_address_sync #($/;" m +fifo_clk adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ reg fifo_clk = 1'b0;$/;" r module:dmac_dma_read_shutdown_tb +fifo_clk adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ reg fifo_clk = 1'b0;$/;" r module:dmac_dma_write_shutdown_tb +fifo_dagc hdl/DAGC_v2.v /^ fifo_dagc fifo_dagc ($/;" i module:DAGC_v2 typeref:module:fifo_dagc +fifo_data adi_library/axi_dmac/dest_axi_mm.v /^ input [DMA_DATA_WIDTH-1:0] fifo_data,$/;" p module:dmac_dest_mm_axi +fifo_data adi_library/axi_dmac/dest_axi_stream.v /^ input [S_AXIS_DATA_WIDTH-1:0] fifo_data,$/;" p module:dmac_dest_axi_stream +fifo_data adi_library/axi_dmac/dest_fifo_inf.v /^ input [DATA_WIDTH-1:0] fifo_data,$/;" p module:dmac_dest_fifo_inf +fifo_data adi_library/axi_dmac/src_axi_mm.v /^ output [DMA_DATA_WIDTH-1:0] fifo_data,$/;" p module:dmac_src_mm_axi +fifo_data adi_library/axi_dmac/src_axi_stream.v /^ output [S_AXIS_DATA_WIDTH-1:0] fifo_data,$/;" p module:dmac_src_axi_stream +fifo_data adi_library/axi_dmac/src_fifo_inf.v /^ output [DATA_WIDTH-1:0] fifo_data,$/;" p module:dmac_src_fifo_inf +fifo_data_ow1i hdl/SC_FDE_TOP.v /^ fifo_ow256 fifo_data_ow1i ($/;" i module:SC_FDE_TOP typeref:module:fifo_ow256 +fifo_data_ow1q hdl/SC_FDE_TOP.v /^ fifo_ow256 fifo_data_ow1q ($/;" i module:SC_FDE_TOP typeref:module:fifo_ow256 +fifo_data_ow2i hdl/SC_FDE_TOP.v /^ fifo_ow256 fifo_data_ow2i ($/;" i module:SC_FDE_TOP typeref:module:fifo_ow256 +fifo_data_ow2q hdl/SC_FDE_TOP.v /^ fifo_ow256 fifo_data_ow2q ($/;" i module:SC_FDE_TOP typeref:module:fifo_ow256 +fifo_enc_out_almost_empty hdl/enc_control.v /^ wire fifo_enc_out_almost_empty;$/;" n module:enc_control +fifo_enc_out_dout hdl/enc_control.v /^ wire [ 1:0] fifo_enc_out_dout;$/;" n module:enc_control +fifo_enc_out_dout_i hdl/enc_control.v /^ wire [ 15:0] fifo_enc_out_dout_i;$/;" n module:enc_control +fifo_enc_out_dout_map hdl/enc_control.v /^ output wire [ 31:0] fifo_enc_out_dout_map,$/;" p module:enc_control +fifo_enc_out_dout_map sim/tb_enc_control.v /^ wire [31:0] fifo_enc_out_dout_map;$/;" n module:tb_enc_control +fifo_enc_out_dout_q hdl/enc_control.v /^ wire [ 15:0] fifo_enc_out_dout_q;$/;" n module:enc_control +fifo_enc_out_empty hdl/enc_control.v /^ output wire fifo_enc_out_empty$/;" p module:enc_control +fifo_enc_out_empty sim/tb_enc_control.v /^ wire fifo_enc_out_empty;$/;" n module:tb_enc_control +fifo_enc_out_prog_empty hdl/enc_control.v /^ wire fifo_enc_out_prog_empty; \/\/ 20 sym$/;" n module:enc_control +fifo_enc_out_prog_empty_1x hdl/enc_control.v /^ wire fifo_enc_out_prog_empty_1x; \/\/ 20 sym$/;" n module:enc_control +fifo_enc_out_rd_clk hdl/enc_control.v /^ input wire fifo_enc_out_rd_clk,$/;" p module:enc_control +fifo_enc_out_rd_en hdl/enc_control.v /^ input wire fifo_enc_out_rd_en,$/;" p module:enc_control +fifo_enc_out_rd_en sim/tb_enc_control.v /^ reg fifo_enc_out_rd_en;$/;" r module:tb_enc_control +fifo_eot_beat adi_library/axi_dmac/dest_axi_stream.v /^wire fifo_eot_beat;$/;" n module:dmac_dest_axi_stream +fifo_eot_beat adi_library/axi_dmac/dest_fifo_inf.v /^wire fifo_eot_beat;$/;" n module:dmac_dest_fifo_inf +fifo_freq hdl/freqestm.v /^ fifo_freq fifo_freq ($/;" i module:freqestm typeref:module:fifo_freq +fifo_last adi_library/axi_dmac/dest_axi_mm.v /^ input fifo_last,$/;" p module:dmac_dest_mm_axi +fifo_last adi_library/axi_dmac/dest_axi_stream.v /^ input fifo_last,$/;" p module:dmac_dest_axi_stream +fifo_last adi_library/axi_dmac/dest_fifo_inf.v /^ input fifo_last,$/;" p module:dmac_dest_fifo_inf +fifo_last adi_library/axi_dmac/src_axi_mm.v /^ output fifo_last,$/;" p module:dmac_src_mm_axi +fifo_last adi_library/axi_dmac/src_axi_stream.v /^ output fifo_last,$/;" p module:dmac_src_axi_stream +fifo_last adi_library/axi_dmac/src_fifo_inf.v /^ output fifo_last,$/;" p module:dmac_src_fifo_inf +fifo_last_beat adi_library/axi_dmac/dest_axi_stream.v /^wire fifo_last_beat;$/;" n module:dmac_dest_axi_stream +fifo_last_beat adi_library/axi_dmac/dest_fifo_inf.v /^wire fifo_last_beat;$/;" n module:dmac_dest_fifo_inf +fifo_out hdl/Receiver.v /^ wire [31:0] fifo_out;$/;" n module:Receiver +fifo_out_valid hdl/Receiver.v /^ wire fifo_out_valid;$/;" n module:Receiver +fifo_partial_burst adi_library/axi_dmac/src_axi_stream.v /^ output fifo_partial_burst,$/;" p module:dmac_src_axi_stream +fifo_pilot_ow1i hdl/data_ow.v /^ fifo_ow256 fifo_pilot_ow1i ($/;" i module:data_ow typeref:module:fifo_ow256 +fifo_pilot_ow1q hdl/data_ow.v /^ fifo_ow256 fifo_pilot_ow1q ($/;" i module:data_ow typeref:module:fifo_ow256 +fifo_pilot_ow2i hdl/data_ow.v /^ fifo_ow256 fifo_pilot_ow2i ($/;" i module:data_ow typeref:module:fifo_ow256 +fifo_pilot_ow2q hdl/data_ow.v /^ fifo_ow256 fifo_pilot_ow2q ($/;" i module:data_ow typeref:module:fifo_ow256 +fifo_rd_beat_counter adi_library/axi_dmac/tb/dma_read_tb.v /^ reg [23:0] fifo_rd_beat_counter = 'h00;$/;" r module:dmac_dma_read_tb +fifo_rd_clk adi_library/axi_dmac/axi_dmac.v /^ input fifo_rd_clk,$/;" p module:axi_dmac +fifo_rd_clk adi_library/axi_dmac/axi_dmac_transfer.v /^ input fifo_rd_clk,$/;" p module:axi_dmac_transfer +fifo_rd_clk adi_library/axi_dmac/request_arb.v /^ input fifo_rd_clk,$/;" p module:dmac_request_arb +fifo_rd_data adi_library/util_pack/tb/underflow_tb.v /^ wire [NUM_OF_PORTS*8-1:0] fifo_rd_data;$/;" n module:upack2_underflow_tb +fifo_rd_data adi_library/util_pack/tb/upack_tb.v /^ wire [NUM_OF_PORTS*8-1:0] fifo_rd_data;$/;" n module:upack_tb +fifo_rd_data adi_library/util_pack/util_upack2/util_upack2.v /^wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_rd_data;$/;" n module:util_upack2 +fifo_rd_data adi_library/util_pack/util_upack2/util_upack2_impl.v /^ output reg [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data,$/;" p module:util_upack2_impl +fifo_rd_data_0 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_0,$/;" p module:util_upack2 +fifo_rd_data_1 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_1,$/;" p module:util_upack2 +fifo_rd_data_10 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_10,$/;" p module:util_upack2 +fifo_rd_data_11 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_11,$/;" p module:util_upack2 +fifo_rd_data_12 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_12,$/;" p module:util_upack2 +fifo_rd_data_13 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_13,$/;" p module:util_upack2 +fifo_rd_data_14 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_14,$/;" p module:util_upack2 +fifo_rd_data_15 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_15,$/;" p module:util_upack2 +fifo_rd_data_16 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_16,$/;" p module:util_upack2 +fifo_rd_data_17 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_17,$/;" p module:util_upack2 +fifo_rd_data_18 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_18,$/;" p module:util_upack2 +fifo_rd_data_19 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_19,$/;" p module:util_upack2 +fifo_rd_data_2 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_2,$/;" p module:util_upack2 +fifo_rd_data_20 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_20,$/;" p module:util_upack2 +fifo_rd_data_21 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_21,$/;" p module:util_upack2 +fifo_rd_data_22 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_22,$/;" p module:util_upack2 +fifo_rd_data_23 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_23,$/;" p module:util_upack2 +fifo_rd_data_24 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_24,$/;" p module:util_upack2 +fifo_rd_data_25 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_25,$/;" p module:util_upack2 +fifo_rd_data_26 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_26,$/;" p module:util_upack2 +fifo_rd_data_27 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_27,$/;" p module:util_upack2 +fifo_rd_data_28 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_28,$/;" p module:util_upack2 +fifo_rd_data_29 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_29,$/;" p module:util_upack2 +fifo_rd_data_3 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_3,$/;" p module:util_upack2 +fifo_rd_data_30 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_30,$/;" p module:util_upack2 +fifo_rd_data_31 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_31,$/;" p module:util_upack2 +fifo_rd_data_32 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_32,$/;" p module:util_upack2 +fifo_rd_data_33 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_33,$/;" p module:util_upack2 +fifo_rd_data_34 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_34,$/;" p module:util_upack2 +fifo_rd_data_35 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_35,$/;" p module:util_upack2 +fifo_rd_data_36 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_36,$/;" p module:util_upack2 +fifo_rd_data_37 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_37,$/;" p module:util_upack2 +fifo_rd_data_38 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_38,$/;" p module:util_upack2 +fifo_rd_data_39 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_39,$/;" p module:util_upack2 +fifo_rd_data_4 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_4,$/;" p module:util_upack2 +fifo_rd_data_40 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_40,$/;" p module:util_upack2 +fifo_rd_data_41 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_41,$/;" p module:util_upack2 +fifo_rd_data_42 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_42,$/;" p module:util_upack2 +fifo_rd_data_43 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_43,$/;" p module:util_upack2 +fifo_rd_data_44 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_44,$/;" p module:util_upack2 +fifo_rd_data_45 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_45,$/;" p module:util_upack2 +fifo_rd_data_46 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_46,$/;" p module:util_upack2 +fifo_rd_data_47 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_47,$/;" p module:util_upack2 +fifo_rd_data_48 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_48,$/;" p module:util_upack2 +fifo_rd_data_49 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_49,$/;" p module:util_upack2 +fifo_rd_data_5 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_5,$/;" p module:util_upack2 +fifo_rd_data_50 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_50,$/;" p module:util_upack2 +fifo_rd_data_51 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_51,$/;" p module:util_upack2 +fifo_rd_data_52 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_52,$/;" p module:util_upack2 +fifo_rd_data_53 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_53,$/;" p module:util_upack2 +fifo_rd_data_54 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_54,$/;" p module:util_upack2 +fifo_rd_data_55 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_55,$/;" p module:util_upack2 +fifo_rd_data_56 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_56,$/;" p module:util_upack2 +fifo_rd_data_57 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_57,$/;" p module:util_upack2 +fifo_rd_data_58 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_58,$/;" p module:util_upack2 +fifo_rd_data_59 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_59,$/;" p module:util_upack2 +fifo_rd_data_6 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_6,$/;" p module:util_upack2 +fifo_rd_data_60 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_60,$/;" p module:util_upack2 +fifo_rd_data_61 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_61,$/;" p module:util_upack2 +fifo_rd_data_62 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_62,$/;" p module:util_upack2 +fifo_rd_data_63 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_63,$/;" p module:util_upack2 +fifo_rd_data_7 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_7,$/;" p module:util_upack2 +fifo_rd_data_8 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_8,$/;" p module:util_upack2 +fifo_rd_data_9 adi_library/util_pack/util_upack2/util_upack2.v /^ output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_9,$/;" p module:util_upack2 +fifo_rd_data_s adi_library/util_pack/util_upack2/util_upack2.v /^wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_rd_data_s;$/;" n module:util_upack2 +fifo_rd_dout adi_library/axi_dmac/axi_dmac.v /^ output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,$/;" p module:axi_dmac +fifo_rd_dout adi_library/axi_dmac/axi_dmac_transfer.v /^ output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,$/;" p module:axi_dmac_transfer +fifo_rd_dout adi_library/axi_dmac/request_arb.v /^ output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,$/;" p module:dmac_request_arb +fifo_rd_dout adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [WIDTH_DEST-1:0] fifo_rd_dout;$/;" n module:dmac_dma_read_tb +fifo_rd_dout_cmp adi_library/axi_dmac/tb/dma_read_tb.v /^ reg [WIDTH_DEST-1:0] fifo_rd_dout_cmp = 'h00;$/;" r module:dmac_dma_read_tb +fifo_rd_dout_mismatch adi_library/axi_dmac/tb/dma_read_tb.v /^ reg fifo_rd_dout_mismatch = 1'b0;$/;" r module:dmac_dma_read_tb +fifo_rd_en adi_library/axi_dmac/axi_dmac.v /^ input fifo_rd_en,$/;" p module:axi_dmac +fifo_rd_en adi_library/axi_dmac/axi_dmac_transfer.v /^ input fifo_rd_en,$/;" p module:axi_dmac_transfer +fifo_rd_en adi_library/axi_dmac/request_arb.v /^ input fifo_rd_en,$/;" p module:dmac_request_arb +fifo_rd_en adi_library/axi_dmac/tb/dma_read_tb.v /^ wire fifo_rd_en = 1'b1;$/;" n module:dmac_dma_read_tb +fifo_rd_en adi_library/util_pack/tb/underflow_tb.v /^ reg fifo_rd_en = 1'b1;$/;" r module:upack2_underflow_tb +fifo_rd_en adi_library/util_pack/tb/upack_tb.v /^ reg fifo_rd_en = 1'b1;$/;" r module:upack_tb +fifo_rd_en adi_library/util_pack/util_upack2/util_upack2.v /^ input fifo_rd_en,$/;" p module:util_upack2 +fifo_rd_en adi_library/util_pack/util_upack2/util_upack2_impl.v /^ input [NUM_OF_CHANNELS-1:0] fifo_rd_en,$/;" p module:util_upack2_impl +fifo_rd_req_length adi_library/axi_dmac/tb/dma_read_tb.v /^ reg [23:0] fifo_rd_req_length = REQ_LEN_INIT;$/;" r module:dmac_dma_read_tb +fifo_rd_underflow adi_library/axi_dmac/axi_dmac.v /^ output fifo_rd_underflow,$/;" p module:axi_dmac +fifo_rd_underflow adi_library/axi_dmac/axi_dmac_transfer.v /^ output fifo_rd_underflow,$/;" p module:axi_dmac_transfer +fifo_rd_underflow adi_library/axi_dmac/request_arb.v /^ output fifo_rd_underflow,$/;" p module:dmac_request_arb +fifo_rd_underflow adi_library/axi_dmac/tb/dma_read_tb.v /^ wire fifo_rd_underflow;$/;" n module:dmac_dma_read_tb +fifo_rd_underflow adi_library/util_pack/tb/underflow_tb.v /^ wire fifo_rd_underflow;$/;" n module:upack2_underflow_tb +fifo_rd_underflow adi_library/util_pack/util_upack2/util_upack2.v /^ output fifo_rd_underflow,$/;" p module:util_upack2 +fifo_rd_underflow adi_library/util_pack/util_upack2/util_upack2_impl.v /^ output reg fifo_rd_underflow,$/;" p module:util_upack2_impl +fifo_rd_valid adi_library/axi_dmac/axi_dmac.v /^ output fifo_rd_valid,$/;" p module:axi_dmac +fifo_rd_valid adi_library/axi_dmac/axi_dmac_transfer.v /^ output fifo_rd_valid,$/;" p module:axi_dmac_transfer +fifo_rd_valid adi_library/axi_dmac/request_arb.v /^ output fifo_rd_valid,$/;" p module:dmac_request_arb +fifo_rd_valid adi_library/axi_dmac/tb/dma_read_tb.v /^ wire fifo_rd_valid;$/;" n module:dmac_dma_read_tb +fifo_rd_valid adi_library/util_pack/tb/underflow_tb.v /^ wire fifo_rd_valid;$/;" n module:upack2_underflow_tb +fifo_rd_valid adi_library/util_pack/tb/upack_tb.v /^ wire fifo_rd_valid;$/;" n module:upack_tb +fifo_rd_valid adi_library/util_pack/util_upack2/util_upack2.v /^ output fifo_rd_valid,$/;" p module:util_upack2 +fifo_rd_valid adi_library/util_pack/util_upack2/util_upack2_impl.v /^ output reg fifo_rd_valid,$/;" p module:util_upack2_impl +fifo_rd_xfer_req adi_library/axi_dmac/axi_dmac.v /^ output fifo_rd_xfer_req,$/;" p module:axi_dmac +fifo_rd_xfer_req adi_library/axi_dmac/axi_dmac_transfer.v /^ output fifo_rd_xfer_req,$/;" p module:axi_dmac_transfer +fifo_rd_xfer_req adi_library/axi_dmac/request_arb.v /^ output fifo_rd_xfer_req,$/;" p module:dmac_request_arb +fifo_ready adi_library/axi_dmac/dest_axi_mm.v /^ output fifo_ready,$/;" p module:dmac_dest_mm_axi +fifo_ready adi_library/axi_dmac/dest_axi_stream.v /^ output fifo_ready,$/;" p module:dmac_dest_axi_stream +fifo_ready adi_library/axi_dmac/dest_fifo_inf.v /^ output fifo_ready,$/;" p module:dmac_dest_fifo_inf +fifo_strb adi_library/axi_dmac/dest_axi_mm.v /^ input [DMA_DATA_WIDTH\/8-1:0] fifo_strb,$/;" p module:dmac_dest_mm_axi +fifo_valid adi_library/axi_dmac/dest_axi_mm.v /^ input fifo_valid,$/;" p module:dmac_dest_mm_axi +fifo_valid adi_library/axi_dmac/dest_axi_stream.v /^ input fifo_valid,$/;" p module:dmac_dest_axi_stream +fifo_valid adi_library/axi_dmac/dest_fifo_inf.v /^ input fifo_valid,$/;" p module:dmac_dest_fifo_inf +fifo_valid adi_library/axi_dmac/src_axi_mm.v /^ output fifo_valid,$/;" p module:dmac_src_mm_axi +fifo_valid adi_library/axi_dmac/src_axi_stream.v /^ output fifo_valid,$/;" p module:dmac_src_axi_stream +fifo_valid adi_library/axi_dmac/src_fifo_inf.v /^ output fifo_valid,$/;" p module:dmac_src_fifo_inf +fifo_valid_bytes adi_library/axi_dmac/src_axi_mm.v /^ output [BYTES_PER_BEAT_WIDTH-1:0] fifo_valid_bytes,$/;" p module:dmac_src_mm_axi +fifo_wc_empty hdl/enc_control.v /^ wire fifo_wc_empty;$/;" n module:enc_control +fifo_wc_prog_full hdl/enc_control.v /^ wire fifo_wc_prog_full;$/;" n module:enc_control +fifo_wc_prog_full_d1 hdl/enc_control.v /^ reg fifo_wc_prog_full_d1;$/;" r module:enc_control +fifo_wr adi_library/axi_dmac/tb/dma_write_tb.v /^ always @(posedge clk) begin: fifo_wr$/;" b module:dmac_dma_write_tb +fifo_wr_clk adi_library/axi_dmac/axi_dmac.v /^ input fifo_wr_clk,$/;" p module:axi_dmac +fifo_wr_clk adi_library/axi_dmac/axi_dmac_transfer.v /^ input fifo_wr_clk,$/;" p module:axi_dmac_transfer +fifo_wr_clk adi_library/axi_dmac/request_arb.v /^ input fifo_wr_clk,$/;" p module:dmac_request_arb +fifo_wr_data adi_library/util_pack/tb/cpack_tb.v /^ reg [NUM_OF_PORTS*8-1:0] fifo_wr_data = 'h00;$/;" r module:cpack_tb +fifo_wr_data adi_library/util_pack/util_cpack2/util_cpack2.v /^wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_wr_data;$/;" n module:util_cpack2 +fifo_wr_data adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data,$/;" p module:util_cpack2_impl +fifo_wr_data_0 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_0,$/;" p module:util_cpack2 +fifo_wr_data_1 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_1,$/;" p module:util_cpack2 +fifo_wr_data_10 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_10,$/;" p module:util_cpack2 +fifo_wr_data_11 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_11,$/;" p module:util_cpack2 +fifo_wr_data_12 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_12,$/;" p module:util_cpack2 +fifo_wr_data_13 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_13,$/;" p module:util_cpack2 +fifo_wr_data_14 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_14,$/;" p module:util_cpack2 +fifo_wr_data_15 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_15,$/;" p module:util_cpack2 +fifo_wr_data_16 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_16,$/;" p module:util_cpack2 +fifo_wr_data_17 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_17,$/;" p module:util_cpack2 +fifo_wr_data_18 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_18,$/;" p module:util_cpack2 +fifo_wr_data_19 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_19,$/;" p module:util_cpack2 +fifo_wr_data_2 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_2,$/;" p module:util_cpack2 +fifo_wr_data_20 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_20,$/;" p module:util_cpack2 +fifo_wr_data_21 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_21,$/;" p module:util_cpack2 +fifo_wr_data_22 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_22,$/;" p module:util_cpack2 +fifo_wr_data_23 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_23,$/;" p module:util_cpack2 +fifo_wr_data_24 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_24,$/;" p module:util_cpack2 +fifo_wr_data_25 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_25,$/;" p module:util_cpack2 +fifo_wr_data_26 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_26,$/;" p module:util_cpack2 +fifo_wr_data_27 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_27,$/;" p module:util_cpack2 +fifo_wr_data_28 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_28,$/;" p module:util_cpack2 +fifo_wr_data_29 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_29,$/;" p module:util_cpack2 +fifo_wr_data_3 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_3,$/;" p module:util_cpack2 +fifo_wr_data_30 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_30,$/;" p module:util_cpack2 +fifo_wr_data_31 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_31,$/;" p module:util_cpack2 +fifo_wr_data_32 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_32,$/;" p module:util_cpack2 +fifo_wr_data_33 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_33,$/;" p module:util_cpack2 +fifo_wr_data_34 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_34,$/;" p module:util_cpack2 +fifo_wr_data_35 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_35,$/;" p module:util_cpack2 +fifo_wr_data_36 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_36,$/;" p module:util_cpack2 +fifo_wr_data_37 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_37,$/;" p module:util_cpack2 +fifo_wr_data_38 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_38,$/;" p module:util_cpack2 +fifo_wr_data_39 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_39,$/;" p module:util_cpack2 +fifo_wr_data_4 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_4,$/;" p module:util_cpack2 +fifo_wr_data_40 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_40,$/;" p module:util_cpack2 +fifo_wr_data_41 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_41,$/;" p module:util_cpack2 +fifo_wr_data_42 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_42,$/;" p module:util_cpack2 +fifo_wr_data_43 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_43,$/;" p module:util_cpack2 +fifo_wr_data_44 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_44,$/;" p module:util_cpack2 +fifo_wr_data_45 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_45,$/;" p module:util_cpack2 +fifo_wr_data_46 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_46,$/;" p module:util_cpack2 +fifo_wr_data_47 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_47,$/;" p module:util_cpack2 +fifo_wr_data_48 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_48,$/;" p module:util_cpack2 +fifo_wr_data_49 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_49,$/;" p module:util_cpack2 +fifo_wr_data_5 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_5,$/;" p module:util_cpack2 +fifo_wr_data_50 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_50,$/;" p module:util_cpack2 +fifo_wr_data_51 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_51,$/;" p module:util_cpack2 +fifo_wr_data_52 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_52,$/;" p module:util_cpack2 +fifo_wr_data_53 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_53,$/;" p module:util_cpack2 +fifo_wr_data_54 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_54,$/;" p module:util_cpack2 +fifo_wr_data_55 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_55,$/;" p module:util_cpack2 +fifo_wr_data_56 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_56,$/;" p module:util_cpack2 +fifo_wr_data_57 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_57,$/;" p module:util_cpack2 +fifo_wr_data_58 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_58,$/;" p module:util_cpack2 +fifo_wr_data_59 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_59,$/;" p module:util_cpack2 +fifo_wr_data_6 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_6,$/;" p module:util_cpack2 +fifo_wr_data_60 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_60,$/;" p module:util_cpack2 +fifo_wr_data_61 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_61,$/;" p module:util_cpack2 +fifo_wr_data_62 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_62,$/;" p module:util_cpack2 +fifo_wr_data_63 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_63,$/;" p module:util_cpack2 +fifo_wr_data_7 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_7,$/;" p module:util_cpack2 +fifo_wr_data_8 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_8,$/;" p module:util_cpack2 +fifo_wr_data_9 adi_library/util_pack/util_cpack2/util_cpack2.v /^ input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_9,$/;" p module:util_cpack2 +fifo_wr_data_s adi_library/util_pack/util_cpack2/util_cpack2.v /^wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_wr_data_s;$/;" n module:util_cpack2 +fifo_wr_din adi_library/axi_dmac/axi_dmac.v /^ input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,$/;" p module:axi_dmac +fifo_wr_din adi_library/axi_dmac/axi_dmac_transfer.v /^ input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,$/;" p module:axi_dmac_transfer +fifo_wr_din adi_library/axi_dmac/request_arb.v /^ input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,$/;" p module:dmac_request_arb +fifo_wr_din adi_library/axi_dmac/tb/dma_write_tb.v /^ reg [WIDTH_SRC-1:0] fifo_wr_din = 'b0;$/;" r module:dmac_dma_write_tb +fifo_wr_en adi_library/axi_dmac/axi_dmac.v /^ input fifo_wr_en,$/;" p module:axi_dmac +fifo_wr_en adi_library/axi_dmac/axi_dmac_transfer.v /^ input fifo_wr_en,$/;" p module:axi_dmac_transfer +fifo_wr_en adi_library/axi_dmac/request_arb.v /^ input fifo_wr_en,$/;" p module:dmac_request_arb +fifo_wr_en adi_library/util_pack/tb/cpack_tb.v /^ reg fifo_wr_en = 1'b1;$/;" r module:cpack_tb +fifo_wr_en adi_library/util_pack/util_cpack2/util_cpack2.v /^ input fifo_wr_en,$/;" p module:util_cpack2 +fifo_wr_en adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ input [NUM_OF_CHANNELS-1:0] fifo_wr_en,$/;" p module:util_cpack2_impl +fifo_wr_overflow adi_library/axi_dmac/axi_dmac.v /^ output fifo_wr_overflow,$/;" p module:axi_dmac +fifo_wr_overflow adi_library/axi_dmac/axi_dmac_transfer.v /^ output fifo_wr_overflow,$/;" p module:axi_dmac_transfer +fifo_wr_overflow adi_library/axi_dmac/request_arb.v /^ output fifo_wr_overflow,$/;" p module:dmac_request_arb +fifo_wr_overflow adi_library/util_pack/util_cpack2/util_cpack2.v /^ output fifo_wr_overflow,$/;" p module:util_cpack2 +fifo_wr_overflow adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ output fifo_wr_overflow,$/;" p module:util_cpack2_impl +fifo_wr_rq adi_library/axi_dmac/tb/dma_write_tb.v /^ reg fifo_wr_rq = 'b0;$/;" r module:dmac_dma_write_tb +fifo_wr_sync adi_library/axi_dmac/axi_dmac.v /^ input fifo_wr_sync,$/;" p module:axi_dmac +fifo_wr_sync adi_library/axi_dmac/axi_dmac_transfer.v /^ input fifo_wr_sync,$/;" p module:axi_dmac_transfer +fifo_wr_sync adi_library/axi_dmac/request_arb.v /^ input fifo_wr_sync,$/;" p module:dmac_request_arb +fifo_wr_xfer_req adi_library/axi_dmac/axi_dmac.v /^ output fifo_wr_xfer_req,$/;" p module:axi_dmac +fifo_wr_xfer_req adi_library/axi_dmac/axi_dmac_transfer.v /^ output fifo_wr_xfer_req,$/;" p module:axi_dmac_transfer +fifo_wr_xfer_req adi_library/axi_dmac/request_arb.v /^ output fifo_wr_xfer_req,$/;" p module:dmac_request_arb +fifo_wr_xfer_req adi_library/axi_dmac/tb/dma_write_tb.v /^ wire fifo_wr_xfer_req;$/;" n module:dmac_dma_write_tb +find_stop hdl/FrameMerge.v /^ find_stop find_stop ($/;" i module:FrameMerge typeref:module:find_stop +fir_tvalid_in hdl/Transmitter.v /^ wire fir_tvalid_in; \/\/ shape filter input valid$/;" n module:Transmitter +first_bit adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire first_bit;$/;" n module:spi_engine_execution +fixed_io_ddr_vrn hdl/system_top.v /^ inout fixed_io_ddr_vrn,$/;" p module:system_top +fixed_io_ddr_vrp hdl/system_top.v /^ inout fixed_io_ddr_vrp,$/;" p module:system_top +fixed_io_mio hdl/system_top.v /^ inout [53:0] fixed_io_mio,$/;" p module:system_top +fixed_io_ps_clk hdl/system_top.v /^ inout fixed_io_ps_clk,$/;" p module:system_top +fixed_io_ps_porb hdl/system_top.v /^ inout fixed_io_ps_porb,$/;" p module:system_top +fixed_io_ps_srstb hdl/system_top.v /^ inout fixed_io_ps_srstb,$/;" p module:system_top +flag sim/tb_Receiver.v /^ reg flag;$/;" r module:tb_Receiver +flag_ChnEstFFT_done hdl/Chn_Estimate.v /^ output reg flag_ChnEstFFT_done = 1'd0,$/;" p module:Chn_Estimate +flag_ChnEstFFT_done hdl/SC_FDE_TOP.v /^ wire flag_ChnEstFFT_done; \/\/信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出/;" n module:SC_FDE_TOP +flag_ChnEstFFT_done hdl/data_equalizer.v /^ input flag_ChnEstFFT_done, \/\/信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给/;" p module:data_equalizer +flag_abs_power hdl/RecvTop.v /^ output flag_abs_power,$/;" p module:RecvTop +flag_adjust hdl/ad9361_mgc_pin_ctrl.v /^ wire flag_adjust;$/;" n module:ad9361_mgc_pin_ctrl +flag_agc_power hdl/DAGC_v2.v /^ output reg flag_agc_power = 1'd0,$/;" p module:DAGC_v2 +flag_agc_power hdl/RecvTop.v /^ output flag_agc_power,$/;" p module:RecvTop +flag_agch hdl/DAGC_v2.v /^ output reg flag_agch = 1'd0,$/;" p module:DAGC_v2 +flag_agch hdl/RecvTop.v /^ output flag_agch,$/;" p module:RecvTop +flag_agcl hdl/DAGC_v2.v /^ output reg flag_agcl = 1'd0,$/;" p module:DAGC_v2 +flag_agcl hdl/RecvTop.v /^ output flag_agcl,$/;" p module:RecvTop +flag_badframe hdl/RecvTop.v /^ output reg flag_badframe = 1'd0,$/;" p module:RecvTop +flag_ber hdl/RecvTop.v /^ output reg flag_ber = 1'd0,$/;" p module:RecvTop +flag_bercount hdl/RecvTop.v /^ output reg flag_bercount = 1'd0,$/;" p module:RecvTop +flag_clk16 hdl/TSync_Abs_new16.v /^ output reg [1:0] flag_clk16 = 2'd0, \/\/12.5$/;" p module:TSync_Abs_new16 +flag_clk16 hdl/TimeSync_top.v /^ wire [1:0] flag_clk16;$/;" n module:TimeSync_top +flag_clk4 hdl/TSync_Abs_new4.v /^ output reg [1:0] flag_clk4 = 2'd0 \/\/12.5$/;" p module:TSync_Abs_new4 +flag_clk4 hdl/TimeSync_top.v /^ wire [1:0] flag_clk4;$/;" n module:TimeSync_top +flag_clk_1_01 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_1_01 =2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_1_01 hdl/TSync_Abs_new4.v /^ reg [1:0] flag_clk_1_01 =2'd0;$/;" r module:TSync_Abs_new4 +flag_clk_1_02 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_1_02 =2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_1_02 hdl/TSync_Abs_new4.v /^ reg [1:0] flag_clk_1_02 =2'd0;$/;" r module:TSync_Abs_new4 +flag_clk_1_03 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_1_03 =2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_1_04 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_1_04 =2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_1_05 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_1_05 =2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_1_06 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_1_06 =2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_1_07 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_1_07 =2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_1_08 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_1_08 =2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_2_01 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_2_01 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_2_02 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_2_02 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_2_03 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_2_03 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_2_04 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_2_04 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_3_1 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_3_1 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_3_2 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_clk_3_2 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_clk_4bit hdl/RecvTop.v /^ output [ 3:0] flag_clk_4bit, \/\/位同步选取通道结果$/;" p module:RecvTop +flag_clk_4bit hdl/TimeSync_top.v /^ output reg [3:0] flag_clk_4bit = 4'd0\/\/12.5 $/;" p module:TimeSync_top +flag_cnt_0 hdl/TSync_Abs_new16.v /^ reg flag_cnt_0 = 1'd0;$/;" r module:TSync_Abs_new16 +flag_cnt_0 hdl/TSync_Abs_new4.v /^ reg flag_cnt_0 = 1'd0;$/;" r module:TSync_Abs_new4 +flag_dataow hdl/SC_FDE_TOP.v /^ wire flag_dataow; \/\/拉高1clk，说明一段数据ow存储完毕，后端可开始连续/;" n module:SC_FDE_TOP +flag_dataow hdl/data_equalizer.v /^ input flag_dataow, \/\/拉高1clk，说明一段数据ow存储完毕，后端可开始连续/;" p module:data_equalizer +flag_dataow hdl/data_ow.v /^ output reg flag_dataow = 1'd0, \/\/拉高1clk，说明一段数据ow存储完毕，后端可开/;" p module:data_ow +flag_dc hdl/RecvTop.v /^ output flag_dc,$/;" p module:RecvTop +flag_frame_sync hdl/tdma.v /^ input flag_frame_sync,$/;" p module:tdma +flag_frame_sync_m sim/tb_tdma.v /^ wire flag_frame_sync_m;$/;" n module:tb_tdma +flag_frame_sync_s sim/tb_tdma.v /^ reg flag_frame_sync_s = 0;$/;" r module:tb_tdma +flag_framesync hdl/TSync_Abs_new16.v /^ reg flag_framesync = 1'd0;$/;" r module:TSync_Abs_new16 +flag_framesync hdl/TSync_Abs_new4.v /^ reg flag_framesync = 1'd0;$/;" r module:TSync_Abs_new4 +flag_is_master hdl/tdma.v /^ input flag_is_master,$/;" p module:tdma +flag_is_tx_slot hdl/tdma.v /^ reg flag_is_tx_slot;$/;" r module:tdma +flag_mgc_done hdl/RecvTop.v /^ wire flag_mgc_done;$/;" n module:RecvTop +flag_mgc_done hdl/ad9361_mgc_pin_ctrl.v /^ output reg flag_mgc_done$/;" p module:ad9361_mgc_pin_ctrl +flag_notbyte hdl/FrameMerge.v /^ output reg flag_notbyte = 1'd0,$/;" p module:FrameMerge +flag_notbyte hdl/RecvTop.v /^ wire flag_notbyte; \/\/为1时说明得到的有效数据不以字节为单位$/;" n module:RecvTop +flag_num16 hdl/TSync_Abs_new16.v /^ output reg [1:0] flag_num16 = 2'd0$/;" p module:TSync_Abs_new16 +flag_num16 hdl/TimeSync_top.v /^ wire [1:0] flag_num16;$/;" n module:TimeSync_top +flag_num_1_01 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_1_01 =2'd0;$/;" r module:TSync_Abs_new16 +flag_num_1_02 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_1_02 =2'd0;$/;" r module:TSync_Abs_new16 +flag_num_1_03 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_1_03 =2'd0;$/;" r module:TSync_Abs_new16 +flag_num_1_04 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_1_04 =2'd0;$/;" r module:TSync_Abs_new16 +flag_num_1_05 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_1_05 =2'd0;$/;" r module:TSync_Abs_new16 +flag_num_1_06 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_1_06 =2'd0;$/;" r module:TSync_Abs_new16 +flag_num_1_07 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_1_07 =2'd0;$/;" r module:TSync_Abs_new16 +flag_num_1_08 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_1_08 =2'd0;$/;" r module:TSync_Abs_new16 +flag_num_2_01 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_2_01 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_num_2_02 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_2_02 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_num_2_03 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_2_03 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_num_2_04 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_2_04 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_num_3_1 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_3_1 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_num_3_2 hdl/TSync_Abs_new16.v /^ reg [1:0] flag_num_3_2 = 2'd0;$/;" r module:TSync_Abs_new16 +flag_overflow hdl/RecvTop.v /^ output flag_overflow,$/;" p module:RecvTop +flag_ow_left hdl/SC_FDE_TOP.v /^ input flag_ow_left, \/\/在一帧内，与第一个数据段的pilot的ow第一个nd对齐$/;" p module:SC_FDE_TOP +flag_ow_left hdl/data_ow.v /^ input flag_ow_left,$/;" p module:data_ow +flag_pilot hdl/data_ow.v /^ reg [0:0] flag_pilot = 1'd0;$/;" r module:data_ow +flag_powerabsh hdl/RecvTop.v /^ output flag_powerabsh,$/;" p module:RecvTop +flag_powerabsl hdl/RecvTop.v /^ output flag_powerabsl,$/;" p module:RecvTop +flag_ram_1 hdl/DAGC_v2.v /^ reg flag_ram_1 = 1'd0;$/;" r module:DAGC_v2 +flag_ram_2 hdl/DAGC_v2.v /^ reg flag_ram_2 = 1'd0;$/;" r module:DAGC_v2 +flag_save hdl/TSync_Abs_new16.v /^ reg flag_save = 0;$/;" r module:TSync_Abs_new16 +flag_small hdl/RecvTop.v /^ output flag_small,$/;" p module:RecvTop +flag_state_mgc hdl/RecvTop.v /^ output flag_state_mgc,$/;" p module:RecvTop +flag_stop hdl/FrameMerge.v /^ output reg flag_stop = 1'd0, \/\/给shx，拉高一个clk表示当前时帧有效数据接/;" p module:FrameMerge +flag_stop hdl/RecvTop.v /^ output flag_stop, \/\/给shx，拉高8个clk表示当前时帧有效数据接收完毕$/;" p module:RecvTop +flag_stop_0 hdl/FrameMerge.v /^ output flag_stop_0, \/\/给shx，拉高1个clk表示当前时帧有效数据接收完毕$/;" p module:FrameMerge +flag_stop_0 hdl/RecvTop.v /^ wire flag_stop_0; \/\/给shx，拉高1个clk表示当前时帧有效数据接收完毕$/;" n module:RecvTop +flag_sync hdl/SCFDE_recv_FrameSync.v /^ output reg flag_sync = 1'b0,$/;" p module:SCFDE_recv_FrameSync +flag_too_high hdl/ad9361_mgc_pin_ctrl.v /^ wire flag_too_high; \/\/ high amplitude$/;" n module:ad9361_mgc_pin_ctrl +flag_too_high hdl/power_measure.v /^ output reg flag_too_high,$/;" p module:power_measure +flag_too_low hdl/ad9361_mgc_pin_ctrl.v /^ wire flag_too_low; \/\/ low amplitude$/;" n module:ad9361_mgc_pin_ctrl +flag_too_low hdl/power_measure.v /^ output reg flag_too_low,$/;" p module:power_measure +flag_transmitter_test sim/TB_sys.v /^ wire flag_transmitter_test;$/;" n module:TB_sys +flag_working hdl/width_convert.v /^ reg flag_working;$/;" r module:width_convert +flagoverflow hdl/RecvTop.v /^ output reg flagoverflow = 1'd0, \/\/总溢出标志$/;" p module:RecvTop +flagoverflow_ChnZF_26to18 hdl/Chn_Estimate.v /^ output reg flagoverflow_ChnZF_26to18 = 1'd0, \/\/第2个fft结果截位，即ZF信道/;" p module:Chn_Estimate +flagoverflow_ChnZF_26to18 hdl/RecvTop.v /^ output flagoverflow_ChnZF_26to18, \/\/第2个fft结果截位，即ZF信/;" p module:RecvTop +flagoverflow_ChnZF_26to18 hdl/SC_FDE_TOP.v /^ output flagoverflow_ChnZF_26to18, \/\/第2个fft结果截位，即ZF信道估计结果的截/;" p module:SC_FDE_TOP +flagoverflow_FDE_dataout_29to10i hdl/RecvTop.v /^ output flagoverflow_FDE_dataout_29to10i, \/\/ifft结果截位，即均衡结果/;" p module:RecvTop +flagoverflow_FDE_dataout_29to10i hdl/SC_FDE_TOP.v /^ output flagoverflow_FDE_dataout_29to10i, \/\/ifft结果截位，即均衡结果处，结果先/;" p module:SC_FDE_TOP +flagoverflow_FDE_dataout_29to10i hdl/data_equalizer.v /^ output reg flagoverflow_FDE_dataout_29to10i = 1'd0, \/\/ifft结果截位，即均衡结果处/;" p module:data_equalizer +flagoverflow_FDE_dataout_29to10q hdl/RecvTop.v /^ output flagoverflow_FDE_dataout_29to10q, \/\/ifft结果截位，即均衡结果/;" p module:RecvTop +flagoverflow_FDE_dataout_29to10q hdl/SC_FDE_TOP.v /^ output flagoverflow_FDE_dataout_29to10q \/\/ifft结果截位，即均衡结果处，结果先/;" p module:SC_FDE_TOP +flagoverflow_FDE_dataout_29to10q hdl/data_equalizer.v /^ output reg flagoverflow_FDE_dataout_29to10q = 1'd0 \/\/ifft结果截位，即均衡结果处/;" p module:data_equalizer +flagoverflow_MMSEdiv_divisor_31to28 hdl/Chn_Estimate.v /^ output reg flagoverflow_MMSEdiv_divisor_31to28 = 1'd0, \/\/第2个除法器，即MMS/;" p module:Chn_Estimate +flagoverflow_MMSEdiv_divisor_31to28 hdl/RecvTop.v /^ output flagoverflow_MMSEdiv_divisor_31to28, \/\/第2个除法器，即MMSE除法/;" p module:RecvTop +flagoverflow_MMSEdiv_divisor_31to28 hdl/SC_FDE_TOP.v /^ output flagoverflow_MMSEdiv_divisor_31to28, \/\/第2个除法器，即MMSE除法的分母截位/;" p module:SC_FDE_TOP +flagoverflow_comdiv_34to20i hdl/Chn_Estimate.v /^ output reg flagoverflow_comdiv_34to20i = 1'd0, \/\/第1个除法器结果截位，即/;" p module:Chn_Estimate +flagoverflow_comdiv_34to20i hdl/RecvTop.v /^ output flagoverflow_comdiv_34to20i, \/\/第1个除法器结果截位，即/;" p module:RecvTop +flagoverflow_comdiv_34to20i hdl/SC_FDE_TOP.v /^ output flagoverflow_comdiv_34to20i, \/\/第1个除法器结果截位，即复数除法结果的/;" p module:SC_FDE_TOP +flagoverflow_comdiv_34to20q hdl/Chn_Estimate.v /^ output reg flagoverflow_comdiv_34to20q = 1'd0, \/\/第1个除法器结果截位，即/;" p module:Chn_Estimate +flagoverflow_comdiv_34to20q hdl/RecvTop.v /^ output flagoverflow_comdiv_34to20q, \/\/第1个除法器结果截位，即/;" p module:RecvTop +flagoverflow_comdiv_34to20q hdl/SC_FDE_TOP.v /^ output flagoverflow_comdiv_34to20q, \/\/第1个除法器结果截位，即复数除法结果的/;" p module:SC_FDE_TOP +flagoverflow_divmmse_34to11 hdl/Chn_Estimate.v /^ output reg flagoverflow_divmmse_34to11 = 1'd0 \/\/第2个除法器结果截位，即/;" p module:Chn_Estimate +flagoverflow_divmmse_34to11 hdl/RecvTop.v /^ output flagoverflow_divmmse_34to11, \/\/第2个除法器结果截位，即/;" p module:RecvTop +flagoverflow_divmmse_34to11 hdl/SC_FDE_TOP.v /^ output flagoverflow_divmmse_34to11, \/\/第2个除法器结果截位，即MMSE信道估计结/;" p module:SC_FDE_TOP +flagoverflow_fftdata_26to16i hdl/RecvTop.v /^ output flagoverflow_fftdata_26to16i, \/\/数据段ow的fft输出截位，/;" p module:RecvTop +flagoverflow_fftdata_26to16i hdl/SC_FDE_TOP.v /^ output flagoverflow_fftdata_26to16i, \/\/数据段ow的fft输出截位，26截到16$/;" p module:SC_FDE_TOP +flagoverflow_fftdata_26to16i hdl/data_equalizer.v /^ output reg flagoverflow_fftdata_26to16i = 1'd0, \/\/数据段ow的fft输出截位，26截到/;" p module:data_equalizer +flagoverflow_fftdata_26to16q hdl/RecvTop.v /^ output flagoverflow_fftdata_26to16q, \/\/数据段ow的fft输出截位，/;" p module:RecvTop +flagoverflow_fftdata_26to16q hdl/SC_FDE_TOP.v /^ output flagoverflow_fftdata_26to16q, \/\/数据段ow的fft输出截位，26截到16$/;" p module:SC_FDE_TOP +flagoverflow_fftdata_26to16q hdl/data_equalizer.v /^ output reg flagoverflow_fftdata_26to16q = 1'd0, \/\/数据段ow的fft输出截位，26截到/;" p module:data_equalizer +flagoverflow_fftpilot_26to14 hdl/Chn_Estimate.v /^ output reg flagoverflow_fftpilot_26to14 = 1'd0, \/\/第1个fft结果截位，即导频/;" p module:Chn_Estimate +flagoverflow_fftpilot_26to14 hdl/RecvTop.v /^ output flagoverflow_fftpilot_26to14, \/\/第1个fft结果截位，即导频/;" p module:RecvTop +flagoverflow_fftpilot_26to14 hdl/SC_FDE_TOP.v /^ output flagoverflow_fftpilot_26to14, \/\/第1个fft结果截位，即导频fft结果的截位/;" p module:SC_FDE_TOP +flagoverflow_ifftindata_28to20i hdl/RecvTop.v /^ output flagoverflow_ifftindata_28to20i, \/\/均衡完毕后（频域结果）/;" p module:RecvTop +flagoverflow_ifftindata_28to20i hdl/SC_FDE_TOP.v /^ output flagoverflow_ifftindata_28to20i, \/\/均衡完毕后（频域结果）的截位，即乘/;" p module:SC_FDE_TOP +flagoverflow_ifftindata_28to20i hdl/data_equalizer.v /^ output reg flagoverflow_ifftindata_28to20i = 1'd0, \/\/均衡完毕后（频域结果）的截/;" p module:data_equalizer +flagoverflow_ifftindata_28to20q hdl/RecvTop.v /^ output flagoverflow_ifftindata_28to20q, \/\/均衡完毕后（频域结果）/;" p module:RecvTop +flagoverflow_ifftindata_28to20q hdl/SC_FDE_TOP.v /^ output flagoverflow_ifftindata_28to20q, \/\/均衡完毕后（频域结果）的截位，即乘/;" p module:SC_FDE_TOP +flagoverflow_ifftindata_28to20q hdl/data_equalizer.v /^ output reg flagoverflow_ifftindata_28to20q = 1'd0, \/\/均衡完毕后（频域结果）的截/;" p module:data_equalizer +flagoverflow_ifftzero_29to17i hdl/Chn_Estimate.v /^ output reg flagoverflow_ifftzero_29to17i = 1'd0, \/\/第1个ifft结果截位，即ZF/;" p module:Chn_Estimate +flagoverflow_ifftzero_29to17i hdl/RecvTop.v /^ output flagoverflow_ifftzero_29to17i, \/\/第1个ifft结果截位，即ZF零/;" p module:RecvTop +flagoverflow_ifftzero_29to17i hdl/SC_FDE_TOP.v /^ output flagoverflow_ifftzero_29to17i, \/\/第1个ifft结果截位，即ZF零域估计处，结/;" p module:SC_FDE_TOP +flagoverflow_ifftzero_29to17q hdl/Chn_Estimate.v /^ output reg flagoverflow_ifftzero_29to17q = 1'd0, \/\/第1个ifft结果截位，即ZF/;" p module:Chn_Estimate +flagoverflow_ifftzero_29to17q hdl/RecvTop.v /^ output flagoverflow_ifftzero_29to17q, \/\/第1个ifft结果截位，即ZF零/;" p module:RecvTop +flagoverflow_ifftzero_29to17q hdl/SC_FDE_TOP.v /^ output flagoverflow_ifftzero_29to17q, \/\/第1个ifft结果截位，即ZF零域估计处，结/;" p module:SC_FDE_TOP +frameIDnd hdl/FrameMerge.v /^ input frameIDnd,$/;" p module:FrameMerge +frameIDnd_d1 hdl/FrameMerge.v /^ reg frameIDnd_d1 = 1'd0;$/;" r module:FrameMerge +frameIDnd_d2 hdl/FrameMerge.v /^ reg frameIDnd_d2 = 1'd0;$/;" r module:FrameMerge +frame_sync hdl/PAPR.v /^ output reg frame_sync,$/;" p module:PAPR +frame_sync hdl/Receiver.v /^ wire frame_sync;$/;" n module:Receiver +frame_sync hdl/frame_sync.v /^module frame_sync #($/;" m +frame_sync_4x hdl/Receiver.v /^ wire frame_sync_4x;$/;" n module:Receiver +frame_sync_d1 hdl/PAPR.v /^ reg frame_sync_d1;$/;" r module:PAPR +frame_sync_pulse hdl/PAPR.v /^ output reg frame_sync_pulse$/;" p module:PAPR +frame_sync_pulse hdl/Receiver.v /^ output frame_sync_pulse \/\/ in domain clk$/;" p module:Receiver +frame_sync_pulse hdl/system_top.v /^ wire frame_sync_pulse;$/;" n module:system_top +frame_sync_pulse sim/tb_tx_with_enc.v /^ wire frame_sync_pulse;$/;" n module:tb_tx_with_enc +framedata hdl/FrameMerge.v /^ wire framedata;$/;" n module:FrameMerge +framedata_d1 hdl/FrameMerge.v /^ reg framedata_d1;$/;" r module:FrameMerge +framelost hdl/RecvTop.v /^ reg framelost;$/;" r module:RecvTop +framerdy hdl/FrameMerge.v /^ output reg framerdy = 1'b0,$/;" p module:FrameMerge +framerdy hdl/RecvTop.v /^ output framerdy, \/\/一帧译码结果存储完毕标/;" p module:RecvTop +framesync hdl/DAGC_v2.v /^ reg framesync;$/;" r module:DAGC_v2 +framesync hdl/IQmerge.v /^ input framesync,$/;" p module:IQmerge +framesync hdl/Interpolation.v /^ input framesync,$/;" p module:Interpolation +framesync hdl/RecvTop.v /^ output framesync, \/\/帧同步峰$/;" p module:RecvTop +framesync hdl/TimeSync_top.v /^ input framesync, \/\/帧同步标志$/;" p module:TimeSync_top +framesync hdl/freqestm.v /^ input framesync,$/;" p module:freqestm +framesync hdl/phase_adjust.v /^ input framesync,$/;" p module:phase_adjust +framesync_Interpolation hdl/Interpolation.v /^ output reg framesync_Interpolation = 1'd0,$/;" p module:Interpolation +framesync_Interpolation hdl/TSync_Abs_new16.v /^ input framesync_Interpolation,$/;" p module:TSync_Abs_new16 +framesync_Interpolation hdl/TSync_Abs_new4.v /^ input framesync_Interpolation,$/;" p module:TSync_Abs_new4 +framesync_Interpolation hdl/TimeSync_top.v /^ wire framesync_Interpolation;$/;" n module:TimeSync_top +framesync_d0 hdl/DAGC_v2.v /^ input framesync_d0,$/;" p module:DAGC_v2 +framesync_d1 hdl/DAGC_v2.v /^ reg framesync_d1;$/;" r module:DAGC_v2 +framesync_d2 hdl/DAGC_v2.v /^ reg framesync_d2;$/;" r module:DAGC_v2 +framesync_d2 hdl/freqestm.v /^ wire framesync_d2;$/;" n module:freqestm +framesync_d3 hdl/DAGC_v2.v /^ reg framesync_d3;$/;" r module:DAGC_v2 +framesync_d3 hdl/freqestm.v /^ wire framesync_d3;$/;" n module:freqestm +framesync_d4 hdl/DAGC_v2.v /^ reg framesync_d4;$/;" r module:DAGC_v2 +framesync_d5 hdl/DAGC_v2.v /^ reg framesync_d5;$/;" r module:DAGC_v2 +framesync_delay hdl/RecvTop.v /^ output framesync_delay, \/\/帧同步峰，与频率补偿输/;" p module:RecvTop +framesync_delay hdl/freqestm.v /^ output reg framesync_delay,$/;" p module:freqestm +framesync_delay_d1 hdl/freqestm.v /^ reg framesync_delay_d1 = 1'b0;$/;" r module:freqestm +framesync_delay_d2 hdl/freqestm.v /^ reg framesync_delay_d2 = 1'b0;$/;" r module:freqestm +framesync_delay_d3 hdl/freqestm.v /^ reg framesync_delay_d3 = 1'b0;$/;" r module:freqestm +framesync_delay_d4 hdl/freqestm.v /^ reg framesync_delay_d4 = 1'b0;$/;" r module:freqestm +framesync_delay_d5 hdl/freqestm.v /^ reg framesync_delay_d5 = 1'b0;$/;" r module:freqestm +framesync_delay_d6 hdl/freqestm.v /^ reg framesync_delay_d6 = 1'b0;$/;" r module:freqestm +framesync_delay_d7 hdl/freqestm.v /^ reg framesync_delay_d7 = 1'b0;$/;" r module:freqestm +framesync_delay_d8 hdl/freqestm.v /^ reg framesync_delay_d8 = 1'b0;$/;" r module:freqestm +framesync_delay_d9 hdl/freqestm.v /^ reg framesync_delay_d9 = 1'b0;$/;" r module:freqestm +framesync_n1 hdl/Interpolation.v /^ reg [0:0] framesync_n1 = 1'd0;$/;" r module:Interpolation +framesync_n2 hdl/Interpolation.v /^ reg [0:0] framesync_n2 = 1'd0;$/;" r module:Interpolation +framesync_n3 hdl/Interpolation.v /^ reg [0:0] framesync_n3 = 1'd0;$/;" r module:Interpolation +framesync_n4 hdl/Interpolation.v /^ reg [0:0] framesync_n4 = 1'd0;$/;" r module:Interpolation +framesync_out16 hdl/TSync_Abs_new16.v /^ output reg framesync_out16 = 1'd0,$/;" p module:TSync_Abs_new16 +framesync_out16 hdl/TimeSync_top.v /^ wire framesync_out16;$/;" n module:TimeSync_top +framesync_out4 hdl/TSync_Abs_new4.v /^ output reg framesync_out4 = 1'd0,$/;" p module:TSync_Abs_new4 +framesync_out4 hdl/TimeSync_top.v /^ wire framesync_out4;$/;" n module:TimeSync_top +framesync_p1 hdl/Interpolation.v /^ reg [0:0] framesync_p1 = 1'd0;$/;" r module:Interpolation +framesync_success hdl/DDS_compensate.v /^ input framesync_success;$/;" p module:DDS_compensate +framesync_t0 hdl/Interpolation.v /^ reg [0:0] framesync_t0 = 1'd0;$/;" r module:Interpolation +framesync_tsync hdl/RecvTop.v /^ output framesync_tsync, \/\/帧同步标志，与TSync输出/;" p module:RecvTop +framesync_tsync hdl/TimeSync_top.v /^ output reg framesync_tsync = 1'd0, \/\/帧同步标志$/;" p module:TimeSync_top +free_rcounter adi_library/common/ad_pps_receiver.v /^ reg [31:0] free_rcounter = 32'b0;$/;" r module:ad_pps_receiver +freq_out hdl/freqestm.v /^ reg [13:0] freq_out;$/;" r module:freqestm +freqdataout_i hdl/RecvTop.v /^ output [ 9:0] freqdataout_i, \/\/频率补偿输出$/;" p module:RecvTop +freqdataout_q hdl/RecvTop.v /^ output [ 9:0] freqdataout_q,$/;" p module:RecvTop +freqestm hdl/RecvTop.v /^ freqestm freqestm ($/;" i module:RecvTop typeref:module:freqestm +freqestm hdl/freqestm.v /^module freqestm ($/;" m +full hdl/DAGC_v2.v /^ wire full;$/;" n module:DAGC_v2 +full hdl/freqestm.v /^ wire full;$/;" n module:freqestm +full_data1i hdl/SC_FDE_TOP.v /^ wire full_data1i;$/;" n module:SC_FDE_TOP +full_data1q hdl/SC_FDE_TOP.v /^ wire full_data1q;$/;" n module:SC_FDE_TOP +full_data2i hdl/SC_FDE_TOP.v /^ wire full_data2i;$/;" n module:SC_FDE_TOP +full_data2q hdl/SC_FDE_TOP.v /^ wire full_data2q;$/;" n module:SC_FDE_TOP +full_pilot1i hdl/data_ow.v /^ wire full_pilot1i;$/;" n module:data_ow +full_pilot1q hdl/data_ow.v /^ wire full_pilot1q;$/;" n module:data_ow +full_pilot2i hdl/data_ow.v /^ wire full_pilot2i;$/;" n module:data_ow +full_pilot2q hdl/data_ow.v /^ wire full_pilot2q;$/;" n module:data_ow +fwd_data adi_library/axi_dmac/axi_register_slice.v /^reg [DATA_WIDTH-1:0] fwd_data = 'h00;$/;" r module:axi_register_slice +fwd_data_s adi_library/axi_dmac/axi_register_slice.v /^wire [DATA_WIDTH-1:0] fwd_data_s;$/;" n module:axi_register_slice +fwd_ready_s adi_library/axi_dmac/axi_register_slice.v /^wire fwd_ready_s;$/;" n module:axi_register_slice +fwd_valid adi_library/axi_dmac/axi_register_slice.v /^reg fwd_valid = 1'b0;$/;" r module:axi_register_slice +fwd_valid_s adi_library/axi_dmac/axi_register_slice.v /^wire fwd_valid_s;$/;" n module:axi_register_slice +g adi_library/common/ad_g2b.v /^ input [DATA_WIDTH-1:0] g;$/;" p function:ad_g2b.g2b +g adi_library/util_cdc/sync_gray.v /^ input [DATA_WIDTH-1:0] g;$/;" p function:sync_gray.g2b +g adi_library/util_cdc/sync_gray.v /^ reg [DATA_WIDTH-1:0] g;$/;" r function:sync_gray.b2g +g adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ input [7:0] g;$/;" p function:axi_adcfifo_wr.g2b +g adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ reg [7:0] g;$/;" r function:axi_adcfifo_wr.b2g +g2b adi_library/common/ad_g2b.v /^ function [DATA_WIDTH-1:0] g2b;$/;" f module:ad_g2b +g2b adi_library/util_cdc/sync_gray.v /^ function [DATA_WIDTH-1:0] g2b;$/;" f module:sync_gray +g2b adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v /^ function [7:0] g2b;$/;" f module:axi_adcfifo_wr +g_channels adi_library/util_mfifo/util_mfifo.v /^ for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_channels$/;" b module:util_mfifo +g_channels_unused adi_library/util_mfifo/util_mfifo.v /^ for (n = NUM_OF_CHANNELS; n < 8; n = n + 1) begin: g_channels_unused$/;" b module:util_mfifo +g_data adi_library/xilinx/common/ad_serdes_in.v /^ for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data$/;" b module:ad_serdes_in +g_data adi_library/xilinx/common/ad_serdes_out.v /^ for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data$/;" b module:ad_serdes_out +g_data_out adi_library/util_extract/util_extract.v /^ for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_data_out$/;" b module:util_extract +g_dinit adi_library/common/up_delay_cntrl.v /^ for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dinit$/;" b module:up_delay_cntrl +g_dwr adi_library/common/up_delay_cntrl.v /^ for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr$/;" b module:up_delay_cntrl +g_in adi_library/util_rfifo/util_rfifo.v /^ for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in$/;" b module:util_rfifo +g_in adi_library/util_wfifo/util_wfifo.v /^ for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in$/;" b module:util_wfifo +g_io adi_library/xilinx/common/ad_serdes_in.v /^ for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_io$/;" b module:ad_serdes_in +g_iobuf adi_library/common/ad_iobuf.v /^ for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf$/;" b module:ad_iobuf +g_lanes adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lanes$/;" b module:axi_xcvrlb +g_loop adi_library/common/ad_iqcor.v /^ for (i=0; i (b) ? (a) : (b)}$/;" d module:ad_mem_asym +max adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ `define max(a,b) {(a) > (b) ? (a) : (b)}$/;" d module:axi_dacfifo_rd +max adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ `define max(a,b) {(a) > (b) ? (a) : (b)}$/;" d module:axi_dacfifo_wr +max hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] max;$/;" r module:MagnitudeEstimator +max_component1 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] max_component1;$/;" r module:MagnitudeEstimator +max_component2 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] max_component2;$/;" r module:MagnitudeEstimator +max_component3 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] max_component3;$/;" r module:MagnitudeEstimator +max_res hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] max_res;$/;" r module:MagnitudeEstimator +mdc_mdio adi_library/util_gmii_to_rgmii/mdc_mdio.v /^module mdc_mdio #($/;" m +mdc_mdio_in adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) mdc_mdio_in($/;" i module:util_gmii_to_rgmii typeref:module:mdc_mdio +mdio_in_r adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ input mdio_in_r,$/;" p module:mdc_mdio +mdio_in_r adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input mdio_in_r,$/;" p module:util_gmii_to_rgmii +mdio_in_w adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ input mdio_in_w,$/;" p module:mdc_mdio +mdio_in_w adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input mdio_in_w,$/;" p module:util_gmii_to_rgmii +mdio_mdc adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ input mdio_mdc,$/;" p module:mdc_mdio +mdio_mdc adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input mdio_mdc,$/;" p module:util_gmii_to_rgmii +mean_temp hdl/RecvTop.v /^ output [24:0] mean_temp,$/;" p module:RecvTop +measured_burst_length adi_library/axi_dmac/axi_dmac_response_manager.v /^ output reg [BYTES_PER_BURST_WIDTH-1:0] measured_burst_length = 'h0,$/;" p module:axi_dmac_response_manager +measured_burst_length adi_library/axi_dmac/request_arb.v /^ output [BYTES_PER_BURST_WIDTH-1:0] measured_burst_length,$/;" p module:dmac_request_arb +measured_last_burst_length adi_library/axi_dmac/address_generator.v /^ input [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,$/;" p module:dmac_address_generator +measured_last_burst_length adi_library/axi_dmac/data_mover.v /^ output reg [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,$/;" p module:dmac_data_mover +measured_last_burst_length adi_library/axi_dmac/dest_axi_mm.v /^ input [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,$/;" p module:dmac_dest_mm_axi +measured_last_burst_length adi_library/axi_dmac/src_axi_mm.v /^ output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,$/;" p module:dmac_src_mm_axi +measured_last_burst_length adi_library/axi_dmac/src_axi_stream.v /^ output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,$/;" p module:dmac_src_axi_stream +measured_last_burst_length adi_library/axi_dmac/src_fifo_inf.v /^ output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,$/;" p module:dmac_src_fifo_inf +mem_data adi_library/axi_dmac/axi_dmac_resize_dest.v /^ input [DATA_WIDTH_MEM-1:0] mem_data,$/;" p module:axi_dmac_resize_dest +mem_data adi_library/axi_dmac/axi_dmac_resize_src.v /^ output [DATA_WIDTH_MEM-1:0] mem_data,$/;" p module:axi_dmac_resize_src +mem_data_last adi_library/axi_dmac/axi_dmac_resize_dest.v /^ input mem_data_last,$/;" p module:axi_dmac_resize_dest +mem_data_last adi_library/axi_dmac/axi_dmac_resize_src.v /^ output mem_data_last,$/;" p module:axi_dmac_resize_src +mem_data_partial_burst adi_library/axi_dmac/axi_dmac_resize_src.v /^ output mem_data_partial_burst$/;" p module:axi_dmac_resize_src +mem_data_ready adi_library/axi_dmac/axi_dmac_resize_dest.v /^ output mem_data_ready,$/;" p module:axi_dmac_resize_dest +mem_data_strb adi_library/axi_dmac/axi_dmac_resize_dest.v /^ input [DATA_WIDTH_MEM\/8-1:0] mem_data_strb,$/;" p module:axi_dmac_resize_dest +mem_data_valid adi_library/axi_dmac/axi_dmac_resize_dest.v /^ input mem_data_valid,$/;" p module:axi_dmac_resize_dest +mem_data_valid adi_library/axi_dmac/axi_dmac_resize_src.v /^ output mem_data_valid,$/;" p module:axi_dmac_resize_src +mem_data_valid_bytes adi_library/axi_dmac/axi_dmac_resize_src.v /^ output [BYTES_PER_BEAT_WIDTH_MEM-1:0] mem_data_valid_bytes,$/;" p module:axi_dmac_resize_src +mem_i sim/tb_Receiver.v /^ reg [11:0] mem_i [10000:0];$/;" r module:tb_Receiver +mem_q sim/tb_Receiver.v /^ reg [11:0] mem_q [10000:0];$/;" r module:tb_Receiver +memread adi_library/common/ad_mem_asym.v /^ always @(posedge clkb) begin : memread$/;" b module:ad_mem_asym +memwrite adi_library/common/ad_mem_asym.v /^ always @(posedge clka) begin : memwrite$/;" b module:ad_mem_asym +message adi_library/axi_dmac/tb/regmap_tb.v /^ input [255:0] message;$/;" p task:dmac_regmap_tb.check_all_registers +message adi_library/axi_dmac/tb/regmap_tb.v /^ input [255:0] message;$/;" p task:dmac_regmap_tb.read_reg_check +mf_data_i hdl/Receiver.v /^ reg [11:0] mf_data_i;$/;" r module:Receiver +mf_data_interp16_i hdl/Receiver.v /^ wire [31:0] mf_data_interp16_i;$/;" n module:Receiver +mf_data_interp16_q hdl/Receiver.v /^ wire [31:0] mf_data_interp16_q;$/;" n module:Receiver +mf_data_interp4_i hdl/Receiver.v /^ wire [31:0] mf_data_interp4_i;$/;" n module:Receiver +mf_data_interp4_q hdl/Receiver.v /^ wire [31:0] mf_data_interp4_q;$/;" n module:Receiver +mf_data_q hdl/Receiver.v /^ reg [11:0] mf_data_q;$/;" r module:Receiver +mf_i hdl/DAGC_v2.v /^ wire [ 9:0] mf_i;$/;" n module:DAGC_v2 +mf_q hdl/DAGC_v2.v /^ wire [ 9:0] mf_q;$/;" n module:DAGC_v2 +mgc1_rdy hdl/DAGC_v2.v /^ input mgc1_rdy,$/;" p module:DAGC_v2 +mgc1_rdy hdl/RecvTop.v /^ output mgc1_rdy,$/;" p module:RecvTop +mgc_rdy hdl/DAGC_v2.v /^ output reg mgc_rdy,$/;" p module:DAGC_v2 +mgc_rdy hdl/RecvTop.v /^ wire mgc_rdy;$/;" n module:RecvTop +mgc_rdy hdl/freqestm.v /^ input mgc_rdy,$/;" p module:freqestm +mgc_rdy_d0 hdl/DAGC_v2.v /^ reg mgc_rdy_d0;$/;" r module:DAGC_v2 +mgc_rdy_d1 hdl/DAGC_v2.v /^ reg mgc_rdy_d1;$/;" r module:DAGC_v2 +mgc_rdy_d2 hdl/DAGC_v2.v /^ reg mgc_rdy_d2;$/;" r module:DAGC_v2 +mgc_rdy_d3 hdl/DAGC_v2.v /^ reg mgc_rdy_d3;$/;" r module:DAGC_v2 +mgc_rdy_d4 hdl/DAGC_v2.v /^ reg mgc_rdy_d4;$/;" r module:DAGC_v2 +mgc_start hdl/RecvTop.v /^ wire mgc_start;$/;" n module:RecvTop +min adi_library/common/ad_mem_asym.v /^ `define min(a,b) {(a) < (b) ? (a) : (b)}$/;" d module:ad_mem_asym +min adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ `define min(a,b) {(a) < (b) ? (a) : (b)}$/;" d module:axi_dacfifo_rd +min adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v /^ `define min(a,b) {(a) < (b) ? (a) : (b)}$/;" d module:axi_dacfifo_wr +min hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] min;$/;" r module:MagnitudeEstimator +min_component1 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] min_component1;$/;" r module:MagnitudeEstimator +min_component2 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] min_component2;$/;" r module:MagnitudeEstimator +min_component3 hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] min_component3;$/;" r module:MagnitudeEstimator +min_res hdl/MagnitudeEstimator.v /^ reg [VEC_WIDTH-1:0] min_res;$/;" r module:MagnitudeEstimator +mmcm_clk_0 adi_library/xilinx/common/ad_mmcm_drp.v /^ output mmcm_clk_0,$/;" p module:ad_mmcm_drp +mmcm_clk_0_s adi_library/xilinx/common/ad_mmcm_drp.v /^ wire mmcm_clk_0_s;$/;" n module:ad_mmcm_drp +mmcm_clk_1 adi_library/xilinx/common/ad_mmcm_drp.v /^ output mmcm_clk_1,$/;" p module:ad_mmcm_drp +mmcm_clk_1_s adi_library/xilinx/common/ad_mmcm_drp.v /^ wire mmcm_clk_1_s;$/;" n module:ad_mmcm_drp +mmcm_clk_2 adi_library/xilinx/common/ad_mmcm_drp.v /^ output mmcm_clk_2,$/;" p module:ad_mmcm_drp +mmcm_clk_2_s adi_library/xilinx/common/ad_mmcm_drp.v /^ wire mmcm_clk_2_s;$/;" n module:ad_mmcm_drp +mmcm_fb_clk_s adi_library/xilinx/common/ad_mmcm_drp.v /^ wire mmcm_fb_clk_s;$/;" n module:ad_mmcm_drp +mmcm_locked_s adi_library/xilinx/common/ad_mmcm_drp.v /^ wire mmcm_locked_s;$/;" n module:ad_mmcm_drp +mmcm_rst adi_library/common/up_adc_common.v /^ output mmcm_rst,$/;" p module:up_adc_common +mmcm_rst adi_library/common/up_clkgen.v /^ output mmcm_rst,$/;" p module:up_clkgen +mmcm_rst adi_library/common/up_dac_common.v /^ output mmcm_rst,$/;" p module:up_dac_common +mmcm_rst adi_library/xilinx/common/ad_mmcm_drp.v /^ input mmcm_rst,$/;" p module:ad_mmcm_drp +mseqs hdl/Transmitter.v /^ wire mseqs;$/;" n module:Transmitter +mseqs_addr hdl/Transmitter.v /^ reg [ 8:0] mseqs_addr;$/;" r module:Transmitter +mseqs_addr_d1 hdl/Transmitter.v /^ reg [ 8:0] mseqs_addr_d1;$/;" r module:Transmitter +mseqs_addr_d2 hdl/Transmitter.v /^ reg [ 8:0] mseqs_addr_d2;$/;" r module:Transmitter +mulifft_datai hdl/data_equalizer.v /^ reg [19:0] mulifft_datai = 20'd0;$/;" r module:data_equalizer +mulifft_dataq hdl/data_equalizer.v /^ reg [19:0] mulifft_dataq = 20'd0;$/;" r module:data_equalizer +mulifft_nd hdl/data_equalizer.v /^ reg mulifft_nd = 1'd0;$/;" r module:data_equalizer +mulin_ai hdl/data_equalizer.v /^ reg [15:0] mulin_ai = 16'd0;$/;" r module:data_equalizer +mulin_aq hdl/data_equalizer.v /^ reg [15:0] mulin_aq = 16'd0;$/;" r module:data_equalizer +mulin_bi hdl/data_equalizer.v /^ reg [10:0] mulin_bi = 11'd0;$/;" r module:data_equalizer +mulin_bq hdl/data_equalizer.v /^ reg [10:0] mulin_bq = 11'd0;$/;" r module:data_equalizer +mulin_i_d0 hdl/data_equalizer.v /^ reg [15:0] mulin_i_d0 = 16'd0;$/;" r module:data_equalizer +mulin_nd hdl/data_equalizer.v /^ reg mulin_nd = 1'd0;$/;" r module:data_equalizer +mulin_nd_d0 hdl/data_equalizer.v /^ reg mulin_nd_d0 = 1'd0;$/;" r module:data_equalizer +mulin_q_d0 hdl/data_equalizer.v /^ reg [15:0] mulin_q_d0 = 16'd0;$/;" r module:data_equalizer +mulout_data hdl/data_equalizer.v /^ wire[63:0] mulout_data;$/;" n module:data_equalizer +mulout_datai hdl/data_equalizer.v /^ wire [27:0] mulout_datai;$/;" n module:data_equalizer +mulout_dataq hdl/data_equalizer.v /^ wire [27:0] mulout_dataq;$/;" n module:data_equalizer +mulout_i hdl/DAGC_v2.v /^ wire [23:0] mulout_i;$/;" n module:DAGC_v2 +mulout_nd hdl/data_equalizer.v /^ wire mulout_nd;$/;" n module:data_equalizer +mulout_q hdl/DAGC_v2.v /^ wire [23:0] mulout_q;$/;" n module:DAGC_v2 +multquartern1 hdl/Interp_half.v /^ wire [13:0] multquartern1;$/;" n module:Interp_half +multquartern1 hdl/Interp_quarter.v /^ wire [15:0] multquartern1;$/;" n module:Interp_quarter +multquartern2 hdl/Interp_half.v /^ reg [9:0] multquartern2 = 10'd0;$/;" r module:Interp_half +multquartern2 hdl/Interp_quarter.v /^ wire [13:0] multquartern2;$/;" n module:Interp_quarter +multquarterp1 hdl/Interp_half.v /^ reg [9:0] multquarterp1 = 10'd0;$/;" r module:Interp_half +multquarterp1 hdl/Interp_quarter.v /^ wire [13:0] multquarterp1;$/;" n module:Interp_quarter +multquartert0 hdl/Interp_half.v /^ wire [13:0] multquartert0;$/;" n module:Interp_half +multquartert0 hdl/Interp_quarter.v /^ wire [16:0] multquartert0;$/;" n module:Interp_quarter +mux_in adi_library/util_pack/util_pack_common/pack_interconnect.v /^ wire [TOTAL_DATA_WIDTH-1:0] mux_in;$/;" n block:pack_interconnect.gen_stages +mux_out adi_library/util_pack/util_pack_common/pack_interconnect.v /^ wire [TOTAL_DATA_WIDTH-1:0] mux_out;$/;" n block:pack_interconnect.gen_stages +n adi_library/common/ad_iobuf.v /^ genvar n;$/;" r module:ad_iobuf +n adi_library/common/up_delay_cntrl.v /^ genvar n;$/;" r module:up_delay_cntrl +n adi_library/util_extract/util_extract.v /^ genvar n;$/;" r module:util_extract +n adi_library/util_mfifo/util_mfifo.v /^ genvar n;$/;" r module:util_mfifo +n adi_library/util_pack/util_pack_common/pack_ctrl.v /^ localparam n = j \/ k1;$/;" c block:pack_ctrl.ctrl_gen_outer.ctrl_gen_inner +n adi_library/util_pack/util_pack_common/pack_ctrl.v /^ integer n;$/;" r module:pack_ctrl +n adi_library/util_rfifo/util_rfifo.v /^ genvar n;$/;" r module:util_rfifo +n adi_library/util_wfifo/util_wfifo.v /^ genvar n;$/;" r module:util_wfifo +n adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ genvar n;$/;" r module:axi_xcvrlb +nd hdl/FrameMerge.v /^ input nd,$/;" p module:FrameMerge +nd hdl/IQmerge.v /^ input nd,$/;" p module:IQmerge +nd hdl/SC_FDE_TOP.v /^ input nd,$/;" p module:SC_FDE_TOP +nd hdl/data_ow.v /^ input nd,$/;" p module:data_ow +nd hdl/phase_adjust.v /^ input nd,$/;" p module:phase_adjust +nd_1 hdl/TSync_Abs_new16.v /^ reg nd_1 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_1 hdl/TSync_Abs_new4.v /^ reg nd_1 = 1'd0;$/;" r module:TSync_Abs_new4 +nd_2 hdl/TSync_Abs_new16.v /^ reg nd_2 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_2 hdl/TSync_Abs_new4.v /^ reg nd_2 = 1'd0;$/;" r module:TSync_Abs_new4 +nd_3 hdl/TSync_Abs_new16.v /^ reg nd_3 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_3 hdl/TSync_Abs_new4.v /^ reg nd_3 = 1'd0;$/;" r module:TSync_Abs_new4 +nd_4 hdl/TSync_Abs_new16.v /^ reg nd_4 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_4 hdl/TSync_Abs_new4.v /^ reg nd_4 = 1'd0;$/;" r module:TSync_Abs_new4 +nd_5 hdl/TSync_Abs_new16.v /^ reg nd_5 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_5 hdl/TSync_Abs_new4.v /^ reg nd_5 = 1'd0;$/;" r module:TSync_Abs_new4 +nd_6 hdl/TSync_Abs_new16.v /^ reg nd_6 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_6 hdl/TSync_Abs_new4.v /^ reg nd_6 = 1'd0;$/;" r module:TSync_Abs_new4 +nd_7 hdl/TSync_Abs_new16.v /^ reg nd_7 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_7 hdl/TSync_Abs_new4.v /^ reg nd_7 = 1'd0;$/;" r module:TSync_Abs_new4 +nd_EstNoise hdl/Chn_Estimate.v /^ input nd_EstNoise,$/;" p module:Chn_Estimate +nd_EstNoise hdl/Noise_Estimate.v /^ output reg nd_EstNoise = 1'd0,$/;" p module:Noise_Estimate +nd_EstNoise hdl/SC_FDE_TOP.v /^ wire nd_EstNoise;$/;" n module:SC_FDE_TOP +nd_SC_FDE_dout hdl/RecvTop.v /^ output nd_SC_FDE_dout, \/\/SC_FDE输出nd$/;" p module:RecvTop +nd_SC_FDE_dout hdl/SC_FDE_TOP.v /^ output nd_SC_FDE_dout,$/;" p module:SC_FDE_TOP +nd_SC_FDE_dout hdl/data_equalizer.v /^ output reg nd_SC_FDE_dout = 1'd0,$/;" p module:data_equalizer +nd_acc hdl/TSync_Abs_new16.v /^ reg nd_acc = 1'd0;$/;" r module:TSync_Abs_new16 +nd_acc hdl/TSync_Abs_new4.v /^ reg nd_acc = 1'd0;$/;" r module:TSync_Abs_new4 +nd_acc1 hdl/TSync_Abs_new16.v /^ reg nd_acc1 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_acc1 hdl/TSync_Abs_new4.v /^ reg nd_acc1 = 1'd0;$/;" r module:TSync_Abs_new4 +nd_acc2 hdl/TSync_Abs_new16.v /^ reg nd_acc2 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_acc2 hdl/TSync_Abs_new4.v /^ reg nd_acc2 = 1'd0;$/;" r module:TSync_Abs_new4 +nd_acc3 hdl/TSync_Abs_new16.v /^ reg nd_acc3 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_acc4 hdl/TSync_Abs_new16.v /^ reg nd_acc4 = 1'd0;$/;" r module:TSync_Abs_new16 +nd_ber hdl/FrameMerge.v /^ output reg [0:0] nd_ber = 1'd0, \/\/比较误码率$/;" p module:FrameMerge +nd_ber hdl/RecvTop.v /^ wire nd_ber;$/;" n module:RecvTop +nd_comdiv_mulin hdl/Chn_Estimate.v /^reg [0:0] nd_comdiv_mulin = 1'd0;$/;" r module:Chn_Estimate +nd_comdiv_mulout hdl/Chn_Estimate.v /^reg [0:0] nd_comdiv_mulout = 1'd0;$/;" r module:Chn_Estimate +nd_comdiv_mulout_d1 hdl/Chn_Estimate.v /^reg [0:0] nd_comdiv_mulout_d1 = 1'd0;$/;" r module:Chn_Estimate +nd_comdiv_mulout_d2 hdl/Chn_Estimate.v /^reg [0:0] nd_comdiv_mulout_d2 = 1'd0;$/;" r module:Chn_Estimate +nd_datafft hdl/SC_FDE_TOP.v /^ wire nd_datafft;$/;" n module:SC_FDE_TOP +nd_dataifft hdl/SC_FDE_TOP.v /^ wire nd_dataifft;$/;" n module:SC_FDE_TOP +nd_flag hdl/TSync_Abs_new16.v /^ reg nd_flag = 1'd0;$/;" r module:TSync_Abs_new16 +nd_flag hdl/TSync_Abs_new4.v /^ reg nd_flag = 1'd0;$/;" r module:TSync_Abs_new4 +nd_noise_d0 hdl/Noise_Estimate.v /^ reg nd_noise_d0 = 1'd0;$/;" r module:Noise_Estimate +nd_noise_d1 hdl/Noise_Estimate.v /^ reg nd_noise_d1 = 1'd0;$/;" r module:Noise_Estimate +nd_noise_d2 hdl/Noise_Estimate.v /^ reg nd_noise_d2 = 1'd0;$/;" r module:Noise_Estimate +nd_noise_d3 hdl/Noise_Estimate.v /^ reg nd_noise_d3 = 1'd0;$/;" r module:Noise_Estimate +nd_noise_d4 hdl/Noise_Estimate.v /^ reg nd_noise_d4 = 1'd0;$/;" r module:Noise_Estimate +nd_noise_d5 hdl/Noise_Estimate.v /^ reg nd_noise_d5 = 1'd0;$/;" r module:Noise_Estimate +nd_noise_d6 hdl/Noise_Estimate.v /^ reg nd_noise_d6 = 1'd0;$/;" r module:Noise_Estimate +nd_pilot hdl/data_ow.v /^ reg [0:0] nd_pilot = 1'd0;$/;" r module:data_ow +nd_pilot2 hdl/Chn_Estimate.v /^ input nd_pilot2,$/;" p module:Chn_Estimate +nd_pilot2 hdl/Noise_Estimate.v /^ input nd_pilot2,$/;" p module:Noise_Estimate +nd_pilot2 hdl/SC_FDE_TOP.v /^ wire nd_pilot2;$/;" n module:SC_FDE_TOP +nd_pilot2 hdl/data_equalizer.v /^ input nd_pilot2,$/;" p module:data_equalizer +nd_pilot2 hdl/data_ow.v /^ output reg nd_pilot2 = 1'd0,$/;" p module:data_ow +nd_pilotfft hdl/SC_FDE_TOP.v /^ wire nd_pilotfft;$/;" n module:SC_FDE_TOP +nd_pilotifft hdl/SC_FDE_TOP.v /^ wire nd_pilotifft;$/;" n module:SC_FDE_TOP +nd_recvnet_dout hdl/FrameMerge.v /^ reg nd_recvnet_dout; $/;" r module:FrameMerge +nd_recvnet_dout_d1 hdl/FrameMerge.v /^ reg nd_recvnet_dout_d1;$/;" r module:FrameMerge +nd_recvnet_dout_d2 hdl/FrameMerge.v /^ reg nd_recvnet_dout_d2;$/;" r module:FrameMerge +nd_recvnet_dout_d3 hdl/FrameMerge.v /^ reg nd_recvnet_dout_d3;$/;" r module:FrameMerge +nd_recvnet_dout_d4 hdl/FrameMerge.v /^ reg nd_recvnet_dout_d4;$/;" r module:FrameMerge +nd_stop_new hdl/FrameMerge.v /^ reg nd_stop_new = 1'd0;$/;" r module:FrameMerge +needs_reset adi_library/axi_dmac/axi_dmac_reset_manager.v /^reg needs_reset = 1'b0;$/;" r module:axi_dmac_reset_manager +needs_sync adi_library/axi_dmac/data_mover.v /^reg needs_sync = 1'b0;$/;" r module:dmac_data_mover +next_enable adi_library/util_pack/tb/cpack_tb.v /^ reg [NUM_OF_CHANNELS-1:0] next_enable = 'h1;$/;" r module:cpack_tb +next_enable adi_library/util_pack/tb/upack_tb.v /^ reg [NUM_OF_CHANNELS-1:0] next_enable = 'h1;$/;" r module:upack_tb +next_state adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ reg [ 1:0] next_state = IDLE;$/;" r module:mdc_mdio +noisei hdl/Noise_Estimate.v /^ reg [9:0] noisei = 10'd0;$/;" r module:Noise_Estimate +noiseq hdl/Noise_Estimate.v /^ reg [9:0] noiseq = 10'd0;$/;" r module:Noise_Estimate +noiseqh hdl/Noise_Estimate.v /^ reg [9:0] noiseqh = 10'd0;$/;" r module:Noise_Estimate +ns hdl/Transmitter.v /^ reg [ 3:0] ns;$/;" r module:Transmitter +ns hdl/ad9361_mgc_pin_ctrl.v /^ reg [2:0] ns;$/;" r module:ad9361_mgc_pin_ctrl +ns hdl/add_prefix.v /^ reg [ 2:0] ns = 0;$/;" r module:add_prefix +ns hdl/enc_control.v /^ reg [ 3:0] ns;$/;" r module:enc_control +ns hdl/power_measure.v /^ reg [2:0] ns = S_MEASURE_IDLE;$/;" r module:power_measure +ntx_rx adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire ntx_rx = counter[0];$/;" n module:spi_engine_execution +num_beats adi_library/axi_dmac/axi_dmac_resize_src.v /^ reg [RATIO_WIDTH-1:0] num_beats = {RATIO_WIDTH{1'b1}};$/;" r module:axi_dmac_resize_src +nx_completion_req_valid adi_library/axi_dmac/request_generator.v /^reg nx_completion_req_valid;$/;" r module:dmac_request_generator +nx_state adi_library/axi_dmac/axi_dmac_response_manager.v /^reg [2:0] nx_state;$/;" r module:axi_dmac_response_manager +nx_state adi_library/axi_dmac/request_generator.v /^reg [2:0] nx_state;$/;" r module:dmac_request_generator +offload0_cmd_wr_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output [15:0] offload0_cmd_wr_data,$/;" p module:axi_spi_engine +offload0_cmd_wr_en adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output offload0_cmd_wr_en,$/;" p module:axi_spi_engine +offload0_enable adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output offload0_enable,$/;" p module:axi_spi_engine +offload0_enable_reg adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg offload0_enable_reg;$/;" r module:axi_spi_engine +offload0_enabled adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input offload0_enabled,$/;" p module:axi_spi_engine +offload0_enabled_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire offload0_enabled_s;$/;" n module:axi_spi_engine +offload0_mem_reset adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output offload0_mem_reset,$/;" p module:axi_spi_engine +offload0_mem_reset_reg adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg offload0_mem_reset_reg;$/;" r module:axi_spi_engine +offload0_sdo_wr_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,$/;" p module:axi_spi_engine +offload0_sdo_wr_en adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output offload0_sdo_wr_en,$/;" p module:axi_spi_engine +offload_sdi_data adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data$/;" p module:spi_engine_offload +offload_sdi_ready adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input offload_sdi_ready,$/;" p module:spi_engine_offload +offload_sdi_valid adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output offload_sdi_valid,$/;" p module:spi_engine_offload +offload_sync_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [7:0] offload_sync_data);$/;" p module:axi_spi_engine +offload_sync_fifo_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [7:0] offload_sync_fifo_data;$/;" n module:axi_spi_engine +offload_sync_fifo_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire offload_sync_fifo_valid;$/;" n module:axi_spi_engine +offload_sync_id adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg [7:0] offload_sync_id = 'h00;$/;" r module:axi_spi_engine +offload_sync_id_pending adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg offload_sync_id_pending = 1'b0;$/;" r module:axi_spi_engine +offload_sync_ready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output offload_sync_ready,$/;" p module:axi_spi_engine +offload_sync_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input offload_sync_valid,$/;" p module:axi_spi_engine +out adi_library/common/ad_addsub.v /^ output reg [(A_DATA_WIDTH-1):0] out,$/;" p module:ad_addsub +out_abort_req adi_library/axi_dmac/2d_transfer.v /^ input out_abort_req,$/;" p module:dmac_2d_transfer +out_bits adi_library/util_cdc/sync_bits.v /^ output [NUM_OF_BITS-1:0] out_bits);$/;" p module:sync_bits +out_clk adi_library/util_cdc/sync_bits.v /^ input out_clk,$/;" p module:sync_bits +out_clk adi_library/util_cdc/sync_data.v /^ input out_clk,$/;" p module:sync_data +out_clk adi_library/util_cdc/sync_event.v /^ input out_clk,$/;" p module:sync_event +out_clk adi_library/util_cdc/sync_gray.v /^ input out_clk,$/;" p module:sync_gray +out_clk adi_library/xilinx/common/ad_serdes_clk.v /^ output out_clk,$/;" p module:ad_serdes_clk +out_count adi_library/util_cdc/sync_gray.v /^ output [DATA_WIDTH-1:0] out_count);$/;" p module:sync_gray +out_count_m adi_library/util_cdc/sync_gray.v /^ reg [DATA_WIDTH-1:0] out_count_m = 'h0;$/;" r module:sync_gray +out_d adi_library/common/ad_addsub.v /^ reg [A_DATA_WIDTH:0] out_d = 'b0;$/;" r module:ad_addsub +out_d2 adi_library/common/ad_addsub.v /^ reg [A_DATA_WIDTH:0] out_d2 = 'b0;$/;" r module:ad_addsub +out_data adi_library/util_cdc/sync_data.v /^ output reg [NUM_OF_BITS-1:0] out_data$/;" p module:sync_data +out_data adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ wire [TOTAL_DATA_WIDTH-1:0] out_data;$/;" n module:util_cpack2_impl +out_data adi_library/util_pack/util_pack_common/pack_shell.v /^ output [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] out_data,$/;" p module:pack_shell +out_data adi_library/util_pack/util_upack2/util_upack2_impl.v /^ wire [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] out_data;$/;" n module:util_upack2_impl +out_eot adi_library/axi_dmac/2d_transfer.v /^ input out_eot,$/;" p module:dmac_2d_transfer +out_event adi_library/util_cdc/sync_event.v /^ output reg [NUM_OF_EVENTS-1:0] out_event$/;" p module:sync_event +out_event_s adi_library/util_cdc/sync_event.v /^wire [NUM_OF_EVENTS-1:0] out_event_s;$/;" n module:sync_event +out_last adi_library/axi_dmac/2d_transfer.v /^wire out_last;$/;" n module:dmac_2d_transfer +out_load adi_library/util_cdc/sync_data.v /^wire out_load = out_toggle ^ out_toggle_d1;$/;" n module:sync_data +out_measured_burst_length adi_library/axi_dmac/2d_transfer.v /^ input [BYTES_PER_BURST_WIDTH-1:0] out_measured_burst_length,$/;" p module:dmac_2d_transfer +out_req_dest_address adi_library/axi_dmac/2d_transfer.v /^ output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,$/;" p module:dmac_2d_transfer +out_req_last adi_library/axi_dmac/2d_transfer.v /^ output out_req_last,$/;" p module:dmac_2d_transfer +out_req_length adi_library/axi_dmac/2d_transfer.v /^ output [DMA_LENGTH_WIDTH-1:0] out_req_length,$/;" p module:dmac_2d_transfer +out_req_ready adi_library/axi_dmac/2d_transfer.v /^ input out_req_ready,$/;" p module:dmac_2d_transfer +out_req_src_address adi_library/axi_dmac/2d_transfer.v /^ output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,$/;" p module:dmac_2d_transfer +out_req_sync_transfer_start adi_library/axi_dmac/2d_transfer.v /^ output reg out_req_sync_transfer_start,$/;" p module:dmac_2d_transfer +out_req_valid adi_library/axi_dmac/2d_transfer.v /^ output reg out_req_valid,$/;" p module:dmac_2d_transfer +out_resetn adi_library/util_cdc/sync_bits.v /^ input out_resetn,$/;" p module:sync_bits +out_resetn adi_library/util_cdc/sync_gray.v /^ input out_resetn,$/;" p module:sync_gray +out_response_partial adi_library/axi_dmac/2d_transfer.v /^ input out_response_partial,$/;" p module:dmac_2d_transfer +out_response_ready adi_library/axi_dmac/2d_transfer.v /^ output reg out_response_ready = 1'b1$/;" p module:dmac_2d_transfer +out_response_valid adi_library/axi_dmac/2d_transfer.v /^ input out_response_valid,$/;" p module:dmac_2d_transfer +out_sync adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ wire out_sync;$/;" n module:util_cpack2_impl +out_sync adi_library/util_pack/util_pack_common/pack_shell.v /^ output out_sync,$/;" p module:pack_shell +out_toggle adi_library/util_cdc/sync_data.v /^wire out_toggle;$/;" n module:sync_data +out_toggle adi_library/util_cdc/sync_event.v /^wire out_toggle;$/;" n module:sync_event +out_toggle_d1 adi_library/util_cdc/sync_data.v /^reg out_toggle_d1 = 1'b0;$/;" r module:sync_data +out_toggle_d1 adi_library/util_cdc/sync_event.v /^reg out_toggle_d1 = 1'b0;$/;" r module:sync_event +out_valid adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ wire [NUM_OF_CHANNELS*SAMPLES_PER_CHANNEL-1:0] out_valid;$/;" n module:util_cpack2_impl +out_valid adi_library/util_pack/util_pack_common/pack_shell.v /^ output [NUM_OF_CHANNELS*SAMPLES_PER_CHANNEL-1:0] out_valid$/;" p module:pack_shell +overflow adi_library/axi_dmac/src_fifo_inf.v /^ output reg overflow,$/;" p module:dmac_src_fifo_inf +ovrflw hdl/trunc_25to12_2dly.v /^ output reg ovrflw = 0;$/;" p module:trunc_25to12_2dly +p1_data_i adi_library/common/ad_iqcor.v /^ reg [CR-1:0] p1_data_i = 'd0;$/;" r block:ad_iqcor.g_loop +p1_data_i_int adi_library/common/ad_iqcor.v /^ wire [CR-1:0] p1_data_i_int;$/;" n block:ad_iqcor.g_loop +p1_data_i_s adi_library/common/ad_iqcor.v /^ wire [CR-1:0] p1_data_i_s;$/;" n block:ad_iqcor.g_loop +p1_data_p adi_library/common/ad_iqcor.v /^ reg [33:0] p1_data_p = 'd0;$/;" r block:ad_iqcor.g_loop +p1_data_p_i_s adi_library/common/ad_iqcor.v /^ wire [33:0] p1_data_p_i_s;$/;" n block:ad_iqcor.g_loop +p1_data_p_q_s adi_library/common/ad_iqcor.v /^ wire [33:0] p1_data_p_q_s;$/;" n block:ad_iqcor.g_loop +p1_data_q adi_library/common/ad_iqcor.v /^ reg [CR-1:0] p1_data_q = 'd0;$/;" r block:ad_iqcor.g_loop +p1_data_q_int adi_library/common/ad_iqcor.v /^ wire [CR-1:0] p1_data_q_int;$/;" n block:ad_iqcor.g_loop +p1_data_q_s adi_library/common/ad_iqcor.v /^ wire [CR-1:0] p1_data_q_s;$/;" n block:ad_iqcor.g_loop +p1_ddata adi_library/xilinx/common/ad_mul.v /^ reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;$/;" r module:ad_mul +p1_valid adi_library/common/ad_iqcor.v /^ reg p1_valid = 'd0;$/;" r block:ad_iqcor.g_loop +p1_valid_s adi_library/common/ad_iqcor.v /^ wire p1_valid_s;$/;" n block:ad_iqcor.g_loop +p2_ddata adi_library/xilinx/common/ad_mul.v /^ reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;$/;" r module:ad_mul +pack_ctrl adi_library/util_pack/util_pack_common/pack_ctrl.v /^module pack_ctrl #($/;" m +pack_interconnect adi_library/util_pack/util_pack_common/pack_interconnect.v /^module pack_interconnect #($/;" m +pack_network adi_library/util_pack/util_pack_common/pack_network.v /^module pack_network #($/;" m +pack_shell adi_library/util_pack/util_pack_common/pack_shell.v /^module pack_shell #($/;" m +packed_fifo_wr_data adi_library/util_pack/tb/cpack_tb.v /^ wire [NUM_OF_PORTS*8-1:0] packed_fifo_wr_data;$/;" n module:cpack_tb +packed_fifo_wr_data adi_library/util_pack/util_cpack2/util_cpack2.v /^ output [2**$clog2(NUM_OF_CHANNELS)*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] packed_fifo_wr_d/;" p module:util_cpack2 +packed_fifo_wr_data adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ output reg [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] packed_fifo_wr_data = '/;" p module:util_cpack2_impl +packed_fifo_wr_en adi_library/util_pack/tb/cpack_tb.v /^ wire packed_fifo_wr_en;$/;" n module:cpack_tb +packed_fifo_wr_en adi_library/util_pack/util_cpack2/util_cpack2.v /^ output packed_fifo_wr_en,$/;" p module:util_cpack2 +packed_fifo_wr_en adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ output reg packed_fifo_wr_en = 1'b0,$/;" p module:util_cpack2_impl +packed_fifo_wr_overflow adi_library/util_pack/util_cpack2/util_cpack2.v /^ input packed_fifo_wr_overflow,$/;" p module:util_cpack2 +packed_fifo_wr_overflow adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ input packed_fifo_wr_overflow,$/;" p module:util_cpack2_impl +packed_fifo_wr_sync adi_library/util_pack/util_cpack2/util_cpack2.v /^ output packed_fifo_wr_sync,$/;" p module:util_cpack2 +packed_fifo_wr_sync adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ output reg packed_fifo_wr_sync = 1'b1,$/;" p module:util_cpack2_impl +partial_burst adi_library/axi_dmac/axi_dmac_resize_src.v /^ reg partial_burst = 1'b0;$/;" r module:axi_dmac_resize_src +pending_burst adi_library/axi_dmac/data_mover.v /^reg pending_burst = 1'b0;$/;" r module:dmac_data_mover +pending_events adi_library/util_cdc/sync_event.v /^wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event;$/;" n module:sync_event +phase adi_library/xilinx/common/ad_serdes_clk.v /^ output [ 7:0] phase,$/;" p module:ad_serdes_clk +phase adi_library/xilinx/common/ad_serdes_in.v /^ input [ 7:0] phase,$/;" p module:ad_serdes_in +phase_adjust hdl/RecvTop.v /^ phase_adjust phase_adjust ($/;" i module:RecvTop typeref:module:phase_adjust +phase_adjust hdl/phase_adjust.v /^module phase_adjust($/;" m +phase_adjust_douti hdl/RecvTop.v /^ wire [9:0] phase_adjust_douti;$/;" n module:RecvTop +phase_adjust_doutq hdl/RecvTop.v /^ wire [9:0] phase_adjust_doutq;$/;" n module:RecvTop +phase_adjust_rdy hdl/RecvTop.v /^ wire phase_adjust_rdy;$/;" n module:RecvTop +phase_estm hdl/phase_adjust.v /^ reg [9:0] phase_estm;$/;" r module:phase_adjust +phase_final hdl/phase_adjust.v /^ reg [9:0] phase_final;$/;" r module:phase_adjust +phase_out hdl/freqestm.v /^ wire [ 9:0] phase_out;$/;" n module:freqestm +phase_out hdl/phase_adjust.v /^ wire [9:0] phase_out;$/;" n module:phase_adjust +phase_out_head hdl/freqestm.v /^ wire [ 5:0] phase_out_head;$/;" n module:freqestm +phase_out_head hdl/phase_adjust.v /^ wire [5:0] phase_out_head;$/;" n module:phase_adjust +phase_pi hdl/phase_adjust.v /^ reg [9:0] phase_pi = 10'b0110010010;$/;" r module:phase_adjust +phase_reg hdl/freqestm.v /^ reg [ 9:0] phase_reg;$/;" r module:freqestm +phase_shengyu hdl/phase_adjust.v /^ reg [9:0] phase_shengyu;$/;" r module:phase_adjust +phaserdy hdl/freqestm.v /^ wire phaserdy;$/;" n module:freqestm +phaserdy hdl/phase_adjust.v /^ wire phaserdy;$/;" n module:phase_adjust +phy_control hdl/phy_control.v /^module phy_control #($/;" m +phy_cr_reg hdl/phy_control.v /^ reg [31:0] phy_cr_reg = 32'h0;$/;" r module:phy_control +phy_rst hdl/phy_control.v /^ output wire phy_rst,$/;" p module:phy_control +phy_rst hdl/system_top.v /^ wire phy_rst;$/;" n module:system_top +phy_rst_ps hdl/system_top.v /^ wire phy_rst_ps;$/;" n module:system_top +phy_rst_vio hdl/system_top.v /^ wire phy_rst_vio;$/;" n module:system_top +phy_sr_reg hdl/phy_control.v /^ reg [31:0] phy_sr_reg = 32'h0;$/;" r module:phy_control +phy_tx_test_flag hdl/phy_control.v /^ output wire phy_tx_test_flag$/;" p module:phy_control +phy_tx_test_flag hdl/system_top.v /^ wire phy_tx_test_flag;$/;" n module:system_top +phy_tx_test_flag_vio hdl/system_top.v /^ wire phy_tx_test_flag_vio;$/;" n module:system_top +pilot_datai hdl/Chn_Estimate.v /^ input [9:0] pilot_datai,$/;" p module:Chn_Estimate +pilot_datai hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_datai;$/;" n module:SC_FDE_TOP +pilot_datai hdl/data_ow.v /^ output reg [9:0] pilot_datai = 10'd0,$/;" p module:data_ow +pilot_dataq hdl/Chn_Estimate.v /^ input [9:0] pilot_dataq,$/;" p module:Chn_Estimate +pilot_dataq hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_dataq;$/;" n module:SC_FDE_TOP +pilot_dataq hdl/data_ow.v /^ output reg [9:0] pilot_dataq = 10'd0,$/;" p module:data_ow +pilot_diffi hdl/data_ow.v /^ reg [10:0] pilot_diffi = 11'd0;$/;" r module:data_ow +pilot_diffq hdl/data_ow.v /^ reg [10:0] pilot_diffq = 11'd0;$/;" r module:data_ow +pilot_noisei hdl/Noise_Estimate.v /^ input [9:0] pilot_noisei,$/;" p module:Noise_Estimate +pilot_noisei hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_noisei;$/;" n module:SC_FDE_TOP +pilot_noisei hdl/data_ow.v /^ output reg [9:0] pilot_noisei = 10'd0,$/;" p module:data_ow +pilot_noiseq hdl/Noise_Estimate.v /^ input [9:0] pilot_noiseq,$/;" p module:Noise_Estimate +pilot_noiseq hdl/SC_FDE_TOP.v /^ wire [9:0] pilot_noiseq;$/;" n module:SC_FDE_TOP +pilot_noiseq hdl/data_ow.v /^ output reg [9:0] pilot_noiseq = 10'd0$/;" p module:data_ow +pilot_sumi hdl/data_ow.v /^ reg [10:0] pilot_sumi = 11'd0;$/;" r module:data_ow +pilot_sumq hdl/data_ow.v /^ reg [10:0] pilot_sumq = 11'd0;$/;" r module:data_ow +pipe adi_library/common/ad_dds_sine_cordic.v /^ pipe ($/;" i block:ad_dds_sine_cordic.rotation typeref:module:ad_dds_cordic_pipe +pl2ps_intr2 sim/TB_sys.v /^ reg pl2ps_intr2;$/;" r module:TB_sys +pmod_clk adi_library/common/up_pmod.v /^ input pmod_clk,$/;" p module:up_pmod +pmod_rst adi_library/common/up_pmod.v /^ output pmod_rst,$/;" p module:up_pmod +pmod_signal_freq adi_library/common/up_pmod.v /^ input [31:0] pmod_signal_freq,$/;" p module:up_pmod +pn adi_library/common/ad_pngen.v /^ wire [DW-1:0] pn;$/;" n module:ad_pngen +pn31 adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ function [31:0] pn31;$/;" f module:axi_xcvrlb_1 +pn_data_in adi_library/common/ad_pngen.v /^ input [DW-1:0] pn_data_in$/;" p module:ad_pngen +pn_data_in_d adi_library/common/ad_pngen.v /^ reg [PN_W-DW-1:0] pn_data_in_d = 'd0;$/;" r module:ad_pngen +pn_data_out adi_library/common/ad_pngen.v /^ output [DW-1:0] pn_data_out, \/\/ MSB has the oldest value,$/;" p module:ad_pngen +pn_full_state adi_library/common/ad_pngen.v /^ wire [DW+POL_W-1:0] pn_full_state;$/;" n module:ad_pngen +pn_init adi_library/common/ad_pngen.v /^ input pn_init,$/;" p module:ad_pngen +pn_init_data adi_library/common/ad_pngen.v /^ wire [PN_W-1:0] pn_init_data;$/;" n module:ad_pngen +pn_loop adi_library/common/ad_pngen.v /^ for (i = 0; i < DW; i = i + 1) begin: pn_loop$/;" b module:ad_pngen +pn_reset adi_library/common/ad_pngen.v /^ wire [PN_W-1:0] pn_reset;$/;" n module:ad_pngen +pn_reset_loop adi_library/common/ad_pngen.v /^ for (j = 0; j < PN_W-POL_W; j = j + 1) begin: pn_reset_loop$/;" b module:ad_pngen +pn_state adi_library/common/ad_pngen.v /^ reg [PN_W-1:0] pn_state = {PN_W{1'b1}};$/;" r module:ad_pngen +pn_state_ adi_library/common/ad_pngen.v /^ wire [PN_W-1:0] pn_state_;$/;" n module:ad_pngen +power_measure hdl/power_measure.v /^module power_measure ($/;" m +power_measure_done_pulse hdl/ad9361_mgc_pin_ctrl.v /^ wire power_measure_done_pulse;$/;" n module:ad9361_mgc_pin_ctrl +power_measure_done_pulse hdl/power_measure.v /^ output reg power_measure_done_pulse$/;" p module:power_measure +poweron_locked hdl/system_top.v /^ wire poweron_locked;$/;" n module:system_top +poweron_locked sim/TB_sys.v /^ wire poweron_locked;$/;" n module:TB_sys +poweron_locked sim/tb_tx_with_enc.v /^ wire poweron_locked;$/;" n module:tb_tx_with_enc +pps_posedge_s adi_library/common/ad_pps_receiver.v /^ wire pps_posedge_s;$/;" n module:ad_pps_receiver +pps_rcounter adi_library/common/ad_pps_receiver.v /^ reg [31:0] pps_rcounter = 32'b0;$/;" r module:ad_pps_receiver +pps_status adi_library/common/ad_pps_receiver.v /^ reg pps_status = 1'b0;$/;" r module:ad_pps_receiver +pps_toggle adi_library/common/ad_pps_receiver.v /^ reg pps_toggle = 1'b0;$/;" r module:ad_pps_receiver +preamble adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ wire preamble;$/;" n module:mdc_mdio +prefix_count adi_library/util_pack/util_pack_common/pack_ctrl.v /^ input [2**PORT_ADDRESS_WIDTH*PORT_ADDRESS_WIDTH-1:0] prefix_count,$/;" p module:pack_ctrl +prefix_count adi_library/util_pack/util_pack_common/pack_network.v /^ input [2**PORT_ADDRESS_WIDTH*PORT_ADDRESS_WIDTH-1:0] prefix_count,$/;" p module:pack_network +prefix_count adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [SAMPLE_ADDRESS_WIDTH*NUM_OF_SAMPLES-1:0] prefix_count;$/;" r module:pack_shell +prefix_count_s adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [SAMPLE_ADDRESS_WIDTH-1:0] prefix_count_s[0:NUM_OF_SAMPLES];$/;" n module:pack_shell +prev_valid adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [NUM_OF_SAMPLES-2*SAMPLES_PER_CHANNEL-1:0] prev_valid = 'h00;$/;" r block:pack_shell.gen_pack +prev_valid_d1 adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [NUM_OF_SAMPLES-2*SAMPLES_PER_CHANNEL-1:0] prev_valid_d1 = 'h00;$/;" r block:pack_shell.gen_pack.gen_output_buffer +programmed_last adi_library/axi_dmac/data_mover.v /^ wire programmed_last;$/;" n module:dmac_data_mover +prot adi_library/axi_dmac/address_generator.v /^ output [ 2:0] prot,$/;" p module:dmac_address_generator +prot adi_library/axi_dmac/tb/axi_slave.v /^ input [2:0] prot,$/;" p module:axi_slave +pulse adi_library/common/util_pulse_gen.v /^ output reg pulse,$/;" p module:util_pulse_gen +pulse_counter adi_library/common/util_pulse_gen.v /^ output [31:0] pulse_counter$/;" p module:util_pulse_gen +pulse_period adi_library/common/util_pulse_gen.v /^ input [31:0] pulse_period,$/;" p module:util_pulse_gen +pulse_period_cnt adi_library/common/util_pulse_gen.v /^ reg [31:0] pulse_period_cnt = 32'h0;$/;" r module:util_pulse_gen +pulse_period_d adi_library/common/util_pulse_gen.v /^ reg [31:0] pulse_period_d = 32'b0;$/;" r module:util_pulse_gen +pulse_period_read adi_library/common/util_pulse_gen.v /^ reg [31:0] pulse_period_read = 32'b0;$/;" r module:util_pulse_gen +pulse_width adi_library/common/util_pulse_gen.v /^ input [31:0] pulse_width,$/;" p module:util_pulse_gen +pulse_width_d adi_library/common/util_pulse_gen.v /^ reg [31:0] pulse_width_d = 32'b0;$/;" r module:util_pulse_gen +pulse_width_read adi_library/common/util_pulse_gen.v /^ reg [31:0] pulse_width_read = 32'b0;$/;" r module:util_pulse_gen +qpll1_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input qpll1_clk,$/;" p module:util_adxcvr_xch +qpll1_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ output qpll1_clk,$/;" p module:util_adxcvr_xcm +qpll1_clk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_clk_0;$/;" n module:util_adxcvr +qpll1_clk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_clk_12;$/;" n module:util_adxcvr +qpll1_clk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_clk_4;$/;" n module:util_adxcvr +qpll1_clk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_clk_8;$/;" n module:util_adxcvr +qpll1_locked adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input qpll1_locked,$/;" p module:util_adxcvr_xch +qpll1_locked adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ output qpll1_locked,$/;" p module:util_adxcvr_xcm +qpll1_locked_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_locked_0;$/;" n module:util_adxcvr +qpll1_locked_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_locked_12;$/;" n module:util_adxcvr +qpll1_locked_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_locked_4;$/;" n module:util_adxcvr +qpll1_locked_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_locked_8;$/;" n module:util_adxcvr +qpll1_ref_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input qpll1_ref_clk,$/;" p module:util_adxcvr_xch +qpll1_ref_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ output qpll1_ref_clk,$/;" p module:util_adxcvr_xcm +qpll1_ref_clk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_ref_clk_0;$/;" n module:util_adxcvr +qpll1_ref_clk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_ref_clk_12;$/;" n module:util_adxcvr +qpll1_ref_clk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_ref_clk_4;$/;" n module:util_adxcvr +qpll1_ref_clk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll1_ref_clk_8;$/;" n module:util_adxcvr +qpll2ch_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input qpll2ch_clk,$/;" p module:util_adxcvr_xch +qpll2ch_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ output qpll2ch_clk,$/;" p module:util_adxcvr_xcm +qpll2ch_clk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_clk_0;$/;" n module:util_adxcvr +qpll2ch_clk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_clk_12;$/;" n module:util_adxcvr +qpll2ch_clk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_clk_4;$/;" n module:util_adxcvr +qpll2ch_clk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_clk_8;$/;" n module:util_adxcvr +qpll2ch_locked adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input qpll2ch_locked,$/;" p module:util_adxcvr_xch +qpll2ch_locked adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ output qpll2ch_locked,$/;" p module:util_adxcvr_xcm +qpll2ch_locked_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_locked_0;$/;" n module:util_adxcvr +qpll2ch_locked_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_locked_12;$/;" n module:util_adxcvr +qpll2ch_locked_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_locked_4;$/;" n module:util_adxcvr +qpll2ch_locked_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_locked_8;$/;" n module:util_adxcvr +qpll2ch_ref_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input qpll2ch_ref_clk,$/;" p module:util_adxcvr_xch +qpll2ch_ref_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ output qpll2ch_ref_clk,$/;" p module:util_adxcvr_xcm +qpll2ch_ref_clk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_ref_clk_0;$/;" n module:util_adxcvr +qpll2ch_ref_clk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_ref_clk_12;$/;" n module:util_adxcvr +qpll2ch_ref_clk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_ref_clk_4;$/;" n module:util_adxcvr +qpll2ch_ref_clk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll2ch_ref_clk_8;$/;" n module:util_adxcvr +qpll_ref_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ input qpll_ref_clk,$/;" p module:util_adxcvr_xcm +qpll_ref_clk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input qpll_ref_clk_0,$/;" p module:util_adxcvr +qpll_ref_clk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input qpll_ref_clk_12,$/;" p module:util_adxcvr +qpll_ref_clk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input qpll_ref_clk_4,$/;" p module:util_adxcvr +qpll_ref_clk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input qpll_ref_clk_8,$/;" p module:util_adxcvr +qpll_sel adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ input qpll_sel,$/;" p module:util_adxcvr_xcm +qpll_sel_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll_sel_0;$/;" n module:util_adxcvr +qpll_sel_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll_sel_12;$/;" n module:util_adxcvr +qpll_sel_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll_sel_4;$/;" n module:util_adxcvr +qpll_sel_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire qpll_sel_8;$/;" n module:util_adxcvr +quadrant adi_library/common/ad_dds_sine_cordic.v /^ wire [ 1:0] quadrant;$/;" n module:ad_dds_sine_cordic +raddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ reg [ADDRESS_WIDTH-1:0] raddr;$/;" r module:axi_dacfifo_address_buffer +ram adi_library/util_axis_fifo/util_axis_fifo.v /^ reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1];$/;" r module:util_axis_fifo +ram_pilota hdl/freqestm.v /^ ram_pilot ram_pilota ($/;" i module:freqestm typeref:module:ram_pilot +ram_pilotb hdl/freqestm.v /^ ram_pilot ram_pilotb ($/;" i module:freqestm typeref:module:ram_pilot +rcnt adi_library/common/ad_axis_inf_rx.v /^ reg [ 2:0] rcnt = 'd0;$/;" r module:ad_axis_inf_rx +rd_en hdl/DAGC_v2.v /^ reg rd_en = 1'b0;$/;" r module:DAGC_v2 +rd_en hdl/freqestm.v /^ reg rd_en;$/;" r module:freqestm +rd_en_data1 hdl/SC_FDE_TOP.v /^ wire rd_en_data1;$/;" n module:SC_FDE_TOP +rd_en_data1 hdl/data_equalizer.v /^ output reg rd_en_data1 = 1'd0,$/;" p module:data_equalizer +rd_en_data2 hdl/SC_FDE_TOP.v /^ wire rd_en_data2;$/;" n module:SC_FDE_TOP +rd_en_data2 hdl/data_equalizer.v /^ output reg rd_en_data2 = 1'd0,$/;" p module:data_equalizer +rd_en_pilot hdl/data_ow.v /^ reg rd_en_pilot = 1'd0;$/;" r module:data_ow +rdata adi_library/axi_dmac/tb/axi_read_slave.v /^ output [DATA_WIDTH-1:0] rdata,$/;" p module:axi_read_slave +rdata adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [31:0] rdata;$/;" n module:dmac_dma_read_shutdown_tb +rdata adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [WIDTH_SRC-1:0] rdata;$/;" n module:dmac_dma_read_tb +rdy hdl/IQmerge.v /^ output reg rdy = 1'b0,$/;" p module:IQmerge +rdy hdl/TimeSync_top.v /^ output reg rdy = 1'd0,$/;" p module:TimeSync_top +rdy hdl/phase_adjust.v /^ output reg rdy,$/;" p module:phase_adjust +rdy_16 hdl/TimeSync_top.v /^ wire rdy_16;$/;" n module:TimeSync_top +rdy_4 hdl/TimeSync_top.v /^ wire rdy_4;$/;" n module:TimeSync_top +rdy_scramble hdl/FrameMerge.v /^ output rdy_scramble,$/;" p module:FrameMerge +rdy_scramble hdl/RecvTop.v /^ wire rdy_scramble;$/;" n module:RecvTop +rea adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ input rea,$/;" p module:axi_dacfifo_address_buffer +read adi_library/util_axis_fifo/address_sync.v /^wire read = m_axis_ready & m_axis_valid;$/;" n module:fifo_address_sync +read_match adi_library/axi_dmac/tb/regmap_tb.v /^ reg read_match = 1'b1;$/;" r module:dmac_regmap_tb +read_reg adi_library/axi_dmac/tb/regmap_tb.v /^ task read_reg;$/;" t module:dmac_regmap_tb +read_reg_check adi_library/axi_dmac/tb/regmap_tb.v /^ task read_reg_check;$/;" t module:dmac_regmap_tb +readvalid hdl/IQmerge.v /^ reg readvalid = 1'b0;$/;" r module:IQmerge +ready adi_library/axi_dmac/src_fifo_inf.v /^wire ready;$/;" n module:dmac_src_fifo_inf +ready adi_library/axi_dmac/tb/axi_slave.v /^ output ready,$/;" p module:axi_slave +ready adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ wire ready;$/;" n module:util_cpack2_impl +ready adi_library/util_pack/util_pack_common/pack_shell.v /^ output reg ready = 1'b0,$/;" p module:pack_shell +ready adi_library/util_pack/util_upack2/util_upack2_impl.v /^ wire ready;$/;" n module:util_upack2_impl +ready hdl/add_prefix.v /^ output reg ready,$/;" p module:add_prefix +ready sim/tb_add_prefix.v /^ wire ready;$/;" n module:tb_add_prefix +ready_counter adi_library/util_fir_int/util_fir_int.v /^ reg [2:0] ready_counter;$/;" r module:util_fir_int +reb adi_library/common/ad_mem.v /^ input reb,$/;" p module:ad_mem +reb adi_library/common/ad_mem_asym.v /^ input reb,$/;" p module:ad_mem_asym +recvNetData hdl/FrameMerge.v /^ output reg [63:0] recvNetData,$/;" p module:FrameMerge +recvNetData hdl/RecvTop.v /^ output [63:0] recvNetData,$/;" p module:RecvTop +recvNetDataNd hdl/FrameMerge.v /^ output reg recvNetDataNd$/;" p module:FrameMerge +recvNetDataNd hdl/RecvTop.v /^ output recvNetDataNd,$/;" p module:RecvTop +recv_addr_new_0 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_0,$/;" p module:FrameMerge +recv_addr_new_1 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_1,$/;" p module:FrameMerge +recv_addr_new_2 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_2,$/;" p module:FrameMerge +recv_addr_new_3 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_3,$/;" p module:FrameMerge +recv_data_new_0 hdl/FrameMerge.v /^ output [7:0] recv_data_new_0,$/;" p module:FrameMerge +recv_data_new_1 hdl/FrameMerge.v /^ output [7:0] recv_data_new_1,$/;" p module:FrameMerge +recv_data_new_2 hdl/FrameMerge.v /^ output [7:0] recv_data_new_2,$/;" p module:FrameMerge +recv_data_new_3 hdl/FrameMerge.v /^ output [7:0] recv_data_new_3,$/;" p module:FrameMerge +ref_clk adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input ref_clk,$/;" p module:axi_xcvrlb +ref_clk adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ input ref_clk,$/;" p module:axi_xcvrlb_1 +reg_add11 hdl/SCFDE_recv_FrameSync.v /^ wire [19:0] reg_add11;$/;" n module:SCFDE_recv_FrameSync +reg_save1024 hdl/SCFDE_recv_FrameSync.v /^ reg [19:0] reg_save1024 = 20'd0;$/;" r module:SCFDE_recv_FrameSync +reg_save1024_d1 hdl/SCFDE_recv_FrameSync.v /^ reg [19:0] reg_save1024_d1 = 20'd0;$/;" r module:SCFDE_recv_FrameSync +reg_save1024_d2 hdl/SCFDE_recv_FrameSync.v /^ reg [19:0] reg_save1024_d2 = 20'd0;$/;" r module:SCFDE_recv_FrameSync +reg_save1024_d2_x2 hdl/SCFDE_recv_FrameSync.v /^ reg [19:0] reg_save1024_d2_x2 = 20'd0;$/;" r module:SCFDE_recv_FrameSync +reg_save_pilot hdl/SCFDE_recv_FrameSync.v /^ reg [19:0] reg_save_pilot;$/;" r module:SCFDE_recv_FrameSync +register_pipe adi_library/common/util_delay.v /^ for (i = 1; i < DELAY_CYCLES; i=i+1) begin:register_pipe$/;" b module:util_delay +req sim/TB_sys.v /^ reg req;$/;" r module:TB_sys +req_aclk adi_library/axi_dmac/2d_transfer.v /^ input req_aclk,$/;" p module:dmac_2d_transfer +req_address adi_library/axi_dmac/address_generator.v /^ input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address,$/;" p module:dmac_address_generator +req_address adi_library/axi_dmac/dest_axi_mm.v /^ input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address,$/;" p module:dmac_dest_mm_axi +req_address adi_library/axi_dmac/src_axi_mm.v /^ input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address,$/;" p module:dmac_src_mm_axi +req_aresetn adi_library/axi_dmac/2d_transfer.v /^ input req_aresetn,$/;" p module:dmac_2d_transfer +req_burst_count adi_library/axi_dmac/request_generator.v /^ input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,$/;" p module:dmac_request_generator +req_clk adi_library/axi_dmac/axi_dmac_response_manager.v /^ input req_clk,$/;" p module:axi_dmac_response_manager +req_clk adi_library/axi_dmac/axi_dmac_transfer.v /^wire req_clk = ctrl_clk;$/;" n module:axi_dmac_transfer +req_clk adi_library/axi_dmac/request_arb.v /^ input req_clk,$/;" p module:dmac_request_arb +req_dest_address adi_library/axi_dmac/2d_transfer.v /^ input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,$/;" p module:dmac_2d_transfer +req_dest_address adi_library/axi_dmac/axi_dmac_transfer.v /^ input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,$/;" p module:axi_dmac_transfer +req_dest_address adi_library/axi_dmac/request_arb.v /^ input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,$/;" p module:dmac_request_arb +req_dest_stride adi_library/axi_dmac/2d_transfer.v /^ input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,$/;" p module:dmac_2d_transfer +req_dest_stride adi_library/axi_dmac/axi_dmac_transfer.v /^ input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,$/;" p module:axi_dmac_transfer +req_enable adi_library/axi_dmac/axi_dmac_reset_manager.v /^ output req_enable,$/;" p module:axi_dmac_reset_manager +req_enable adi_library/axi_dmac/axi_dmac_transfer.v /^wire req_enable;$/;" n module:axi_dmac_transfer +req_enable adi_library/axi_dmac/request_arb.v /^ input req_enable,$/;" p module:dmac_request_arb +req_enable adi_library/axi_dmac/tb/reset_manager_tb.v /^ wire req_enable;$/;" n module:dmac_reset_manager_tb +req_enabled adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input req_enabled,$/;" p module:axi_dmac_reset_manager +req_enabled adi_library/axi_dmac/tb/reset_manager_tb.v /^ wire req_enabled = req_enabled_shift[15];$/;" n module:dmac_reset_manager_tb +req_enabled_shift adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg [15:0] req_enabled_shift;$/;" r module:dmac_reset_manager_tb +req_eot adi_library/axi_dmac/2d_transfer.v /^ output reg req_eot,$/;" p module:dmac_2d_transfer +req_eot adi_library/axi_dmac/axi_dmac_response_manager.v /^reg req_eot = 1'b0;$/;" r module:axi_dmac_response_manager +req_eot adi_library/axi_dmac/axi_dmac_transfer.v /^ output req_eot,$/;" p module:axi_dmac_transfer +req_fifo adi_library/axi_dmac/tb/axi_slave.v /^reg [32+32+8-1:0] req_fifo[0:15];$/;" r module:axi_slave +req_fifo_level adi_library/axi_dmac/tb/axi_slave.v /^wire [3:0] req_fifo_level = req_fifo_wr - req_fifo_rd;$/;" n module:axi_slave +req_fifo_rd adi_library/axi_dmac/tb/axi_slave.v /^reg [3:0] req_fifo_rd = 'h00;$/;" r module:axi_slave +req_fifo_wr adi_library/axi_dmac/tb/axi_slave.v /^reg [3:0] req_fifo_wr = 'h00;$/;" r module:axi_slave +req_gen_ready adi_library/axi_dmac/request_arb.v /^wire req_gen_ready;$/;" n module:dmac_request_arb +req_gen_valid adi_library/axi_dmac/request_arb.v /^wire req_gen_valid;$/;" n module:dmac_request_arb +req_id adi_library/axi_dmac/2d_transfer.v /^reg [1:0] req_id = 'h00;$/;" r module:dmac_2d_transfer +req_last adi_library/axi_dmac/2d_transfer.v /^ input req_last,$/;" p module:dmac_2d_transfer +req_last adi_library/axi_dmac/axi_dmac_transfer.v /^ input req_last,$/;" p module:axi_dmac_transfer +req_last_beat_bytes adi_library/axi_dmac/src_axi_mm.v /^ input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes,$/;" p module:dmac_src_mm_axi +req_last_burst_length adi_library/axi_dmac/data_mover.v /^ input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,$/;" p module:dmac_data_mover +req_last_burst_length adi_library/axi_dmac/src_axi_mm.v /^ input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,$/;" p module:dmac_src_mm_axi +req_last_burst_length adi_library/axi_dmac/src_axi_stream.v /^ input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,$/;" p module:dmac_src_axi_stream +req_last_burst_length adi_library/axi_dmac/src_fifo_inf.v /^ input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,$/;" p module:dmac_src_fifo_inf +req_length adi_library/axi_dmac/request_arb.v /^ input [DMA_LENGTH_WIDTH-1:0] req_length,$/;" p module:dmac_request_arb +req_length adi_library/axi_dmac/tb/dma_read_tb.v /^ reg [23:0] req_length = REQ_LEN_INIT - 1;$/;" r module:dmac_dma_read_tb +req_length adi_library/axi_dmac/tb/dma_write_tb.v /^ reg [23:0] req_length = REQ_LEN_INIT - 1;$/;" r module:dmac_dma_write_tb +req_measured_burst_length adi_library/axi_dmac/2d_transfer.v /^ output reg [BYTES_PER_BURST_WIDTH-1:0] req_measured_burst_length,$/;" p module:dmac_2d_transfer +req_measured_burst_length adi_library/axi_dmac/axi_dmac_transfer.v /^ output [BYTES_PER_BURST_WIDTH-1:0] req_measured_burst_length,$/;" p module:axi_dmac_transfer +req_ready adi_library/axi_dmac/2d_transfer.v /^ output reg req_ready,$/;" p module:dmac_2d_transfer +req_ready adi_library/axi_dmac/address_generator.v /^ output reg req_ready,$/;" p module:dmac_address_generator +req_ready adi_library/axi_dmac/axi_dmac_transfer.v /^ output req_ready,$/;" p module:axi_dmac_transfer +req_ready adi_library/axi_dmac/data_mover.v /^ output req_ready,$/;" p module:dmac_data_mover +req_ready adi_library/axi_dmac/dest_axi_mm.v /^ output req_ready,$/;" p module:dmac_dest_mm_axi +req_ready adi_library/axi_dmac/dest_axi_stream.v /^ output req_ready,$/;" p module:dmac_dest_axi_stream +req_ready adi_library/axi_dmac/dest_fifo_inf.v /^ output req_ready,$/;" p module:dmac_dest_fifo_inf +req_ready adi_library/axi_dmac/request_arb.v /^ output req_ready,$/;" p module:dmac_request_arb +req_ready adi_library/axi_dmac/request_generator.v /^ output reg req_ready,$/;" p module:dmac_request_generator +req_ready adi_library/axi_dmac/src_axi_mm.v /^ output req_ready,$/;" p module:dmac_src_mm_axi +req_ready adi_library/axi_dmac/src_axi_stream.v /^ output req_ready,$/;" p module:dmac_src_axi_stream +req_ready adi_library/axi_dmac/src_fifo_inf.v /^ output req_ready,$/;" p module:dmac_src_fifo_inf +req_ready adi_library/axi_dmac/tb/dma_read_tb.v /^ wire req_ready;$/;" n module:dmac_dma_read_tb +req_ready adi_library/axi_dmac/tb/dma_write_tb.v /^ wire req_ready;$/;" n module:dmac_dma_write_tb +req_ready_ag adi_library/axi_dmac/src_axi_mm.v /^wire req_ready_ag;$/;" n module:dmac_src_mm_axi +req_ready_gated adi_library/axi_dmac/axi_dmac_transfer.v /^wire req_ready_gated;$/;" n module:axi_dmac_transfer +req_resetn adi_library/axi_dmac/axi_dmac_reset_manager.v /^ output req_resetn,$/;" p module:axi_dmac_reset_manager +req_resetn adi_library/axi_dmac/axi_dmac_response_manager.v /^ input req_resetn,$/;" p module:axi_dmac_response_manager +req_resetn adi_library/axi_dmac/axi_dmac_transfer.v /^wire req_resetn;$/;" n module:axi_dmac_transfer +req_resetn adi_library/axi_dmac/request_arb.v /^ input req_resetn,$/;" p module:dmac_request_arb +req_response_dest_data_burst_length adi_library/axi_dmac/axi_dmac_response_manager.v /^reg [BYTES_PER_BURST_WIDTH-1:0] req_response_dest_data_burst_length = 'h0;$/;" r module:axi_dmac_response_manager +req_response_partial adi_library/axi_dmac/2d_transfer.v /^ output reg req_response_partial,$/;" p module:dmac_2d_transfer +req_response_partial adi_library/axi_dmac/axi_dmac_response_manager.v /^reg req_response_partial = 1'b0;$/;" r module:axi_dmac_response_manager +req_response_partial adi_library/axi_dmac/axi_dmac_transfer.v /^ output req_response_partial,$/;" p module:axi_dmac_transfer +req_response_ready adi_library/axi_dmac/2d_transfer.v /^ input req_response_ready,$/;" p module:dmac_2d_transfer +req_response_ready adi_library/axi_dmac/axi_dmac_transfer.v /^ input req_response_ready,$/;" p module:axi_dmac_transfer +req_response_valid adi_library/axi_dmac/2d_transfer.v /^ output reg req_response_valid,$/;" p module:dmac_2d_transfer +req_response_valid adi_library/axi_dmac/axi_dmac_transfer.v /^ output req_response_valid,$/;" p module:axi_dmac_transfer +req_rewind_req_data adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH+3-1:0] req_rewind_req_data;$/;" n module:dmac_request_arb +req_rewind_req_ready adi_library/axi_dmac/request_arb.v /^wire req_rewind_req_ready;$/;" n module:dmac_request_arb +req_rewind_req_valid adi_library/axi_dmac/request_arb.v /^wire req_rewind_req_valid;$/;" n module:dmac_request_arb +req_src_address adi_library/axi_dmac/2d_transfer.v /^ input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,$/;" p module:dmac_2d_transfer +req_src_address adi_library/axi_dmac/axi_dmac_transfer.v /^ input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,$/;" p module:axi_dmac_transfer +req_src_address adi_library/axi_dmac/request_arb.v /^ input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,$/;" p module:dmac_request_arb +req_src_ready adi_library/axi_dmac/request_arb.v /^wire req_src_ready;$/;" n module:dmac_request_arb +req_src_stride adi_library/axi_dmac/2d_transfer.v /^ input [DMA_LENGTH_WIDTH-1:0] req_src_stride,$/;" p module:dmac_2d_transfer +req_src_stride adi_library/axi_dmac/axi_dmac_transfer.v /^ input [DMA_LENGTH_WIDTH-1:0] req_src_stride,$/;" p module:axi_dmac_transfer +req_src_valid adi_library/axi_dmac/request_arb.v /^wire req_src_valid;$/;" n module:dmac_request_arb +req_sync_transfer_start adi_library/axi_dmac/2d_transfer.v /^ input req_sync_transfer_start,$/;" p module:dmac_2d_transfer +req_sync_transfer_start adi_library/axi_dmac/axi_dmac_transfer.v /^ input req_sync_transfer_start,$/;" p module:axi_dmac_transfer +req_sync_transfer_start adi_library/axi_dmac/data_mover.v /^ input req_sync_transfer_start,$/;" p module:dmac_data_mover +req_sync_transfer_start adi_library/axi_dmac/request_arb.v /^ input req_sync_transfer_start,$/;" p module:dmac_request_arb +req_sync_transfer_start adi_library/axi_dmac/src_axi_stream.v /^ input req_sync_transfer_start,$/;" p module:dmac_src_axi_stream +req_sync_transfer_start adi_library/axi_dmac/src_fifo_inf.v /^ input req_sync_transfer_start$/;" p module:dmac_src_fifo_inf +req_valid adi_library/axi_dmac/2d_transfer.v /^ input req_valid,$/;" p module:dmac_2d_transfer +req_valid adi_library/axi_dmac/address_generator.v /^ input req_valid,$/;" p module:dmac_address_generator +req_valid adi_library/axi_dmac/axi_dmac_transfer.v /^ input req_valid,$/;" p module:axi_dmac_transfer +req_valid adi_library/axi_dmac/data_mover.v /^ input req_valid,$/;" p module:dmac_data_mover +req_valid adi_library/axi_dmac/dest_axi_mm.v /^ input req_valid,$/;" p module:dmac_dest_mm_axi +req_valid adi_library/axi_dmac/dest_axi_stream.v /^ input req_valid,$/;" p module:dmac_dest_axi_stream +req_valid adi_library/axi_dmac/dest_fifo_inf.v /^ input req_valid,$/;" p module:dmac_dest_fifo_inf +req_valid adi_library/axi_dmac/request_arb.v /^ input req_valid,$/;" p module:dmac_request_arb +req_valid adi_library/axi_dmac/request_generator.v /^ input req_valid,$/;" p module:dmac_request_generator +req_valid adi_library/axi_dmac/src_axi_mm.v /^ input req_valid,$/;" p module:dmac_src_mm_axi +req_valid adi_library/axi_dmac/src_axi_stream.v /^ input req_valid,$/;" p module:dmac_src_axi_stream +req_valid adi_library/axi_dmac/src_fifo_inf.v /^ input req_valid,$/;" p module:dmac_src_fifo_inf +req_valid adi_library/axi_dmac/tb/dma_read_tb.v /^ reg req_valid = 1'b1;$/;" r module:dmac_dma_read_tb +req_valid adi_library/axi_dmac/tb/dma_write_tb.v /^ reg req_valid = 1'b1;$/;" r module:dmac_dma_write_tb +req_valid_ag adi_library/axi_dmac/src_axi_mm.v /^wire req_valid_ag;$/;" n module:dmac_src_mm_axi +req_valid_gated adi_library/axi_dmac/axi_dmac_transfer.v /^wire req_valid_gated;$/;" n module:axi_dmac_transfer +req_x_length adi_library/axi_dmac/2d_transfer.v /^ input [DMA_LENGTH_WIDTH-1:0] req_x_length,$/;" p module:dmac_2d_transfer +req_x_length adi_library/axi_dmac/axi_dmac_transfer.v /^ input [DMA_LENGTH_WIDTH-1:0] req_x_length,$/;" p module:axi_dmac_transfer +req_xlast adi_library/axi_dmac/data_mover.v /^ input req_xlast$/;" p module:dmac_data_mover +req_xlast adi_library/axi_dmac/dest_axi_stream.v /^ input req_xlast,$/;" p module:dmac_dest_axi_stream +req_xlast adi_library/axi_dmac/request_arb.v /^ input req_xlast,$/;" p module:dmac_request_arb +req_xlast adi_library/axi_dmac/request_generator.v /^ input req_xlast,$/;" p module:dmac_request_generator +req_xlast adi_library/axi_dmac/src_axi_stream.v /^ input req_xlast$/;" p module:dmac_src_axi_stream +req_xlast_d adi_library/axi_dmac/data_mover.v /^ reg req_xlast_d = 1'b0;$/;" r module:dmac_data_mover +req_xlast_d adi_library/axi_dmac/dest_axi_stream.v /^reg req_xlast_d = 1'b0;$/;" r module:dmac_dest_axi_stream +req_y_length adi_library/axi_dmac/2d_transfer.v /^ input [DMA_LENGTH_WIDTH-1:0] req_y_length,$/;" p module:dmac_2d_transfer +req_y_length adi_library/axi_dmac/axi_dmac_transfer.v /^ input [DMA_LENGTH_WIDTH-1:0] req_y_length,$/;" p module:axi_dmac_transfer +request_dest_address adi_library/axi_dmac/axi_dmac_regmap.v /^ output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] request_dest_address,$/;" p module:axi_dmac_regmap +request_dest_address adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] request_dest_address,$/;" p module:axi_dmac_regmap_request +request_dest_address adi_library/axi_dmac/tb/regmap_tb.v /^ wire [31:BYTES_PER_BEAT] request_dest_address;$/;" n module:dmac_regmap_tb +request_dest_stride adi_library/axi_dmac/axi_dmac_regmap.v /^ output [DMA_LENGTH_WIDTH-1:0] request_dest_stride,$/;" p module:axi_dmac_regmap +request_dest_stride adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output [DMA_LENGTH_WIDTH-1:0] request_dest_stride,$/;" p module:axi_dmac_regmap_request +request_dest_stride adi_library/axi_dmac/tb/regmap_tb.v /^ wire [DMA_LENGTH_WIDTH-1:0] request_dest_stride;$/;" n module:dmac_regmap_tb +request_eot adi_library/axi_dmac/request_arb.v /^wire request_eot;$/;" n module:dmac_request_arb +request_id adi_library/axi_dmac/address_generator.v /^ input [ID_WIDTH-1:0] request_id,$/;" p module:dmac_address_generator +request_id adi_library/axi_dmac/data_mover.v /^ input [ID_WIDTH-1:0] request_id,$/;" p module:dmac_data_mover +request_id adi_library/axi_dmac/dest_axi_mm.v /^ input [ID_WIDTH-1:0] request_id,$/;" p module:dmac_dest_mm_axi +request_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] request_id;$/;" n module:dmac_request_arb +request_id adi_library/axi_dmac/request_generator.v /^ output [ID_WIDTH-1:0] request_id,$/;" p module:dmac_request_generator +request_id adi_library/axi_dmac/response_generator.v /^ input [ID_WIDTH-1:0] request_id,$/;" p module:dmac_response_generator +request_id adi_library/axi_dmac/response_handler.v /^ input [ID_WIDTH-1:0] request_id,$/;" p module:dmac_response_handler +request_id adi_library/axi_dmac/src_axi_mm.v /^ input [ID_WIDTH-1:0] request_id,$/;" p module:dmac_src_mm_axi +request_id adi_library/axi_dmac/src_axi_stream.v /^ input [ID_WIDTH-1:0] request_id,$/;" p module:dmac_src_axi_stream +request_id adi_library/axi_dmac/src_fifo_inf.v /^ input [ID_WIDTH-1:0] request_id,$/;" p module:dmac_src_fifo_inf +request_last adi_library/axi_dmac/axi_dmac_regmap.v /^ output request_last,$/;" p module:axi_dmac_regmap +request_last adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output request_last,$/;" p module:axi_dmac_regmap_request +request_last adi_library/axi_dmac/tb/regmap_tb.v /^ wire request_last;$/;" n module:dmac_regmap_tb +request_ready adi_library/axi_dmac/axi_dmac_regmap.v /^ input request_ready,$/;" p module:axi_dmac_regmap +request_ready adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input request_ready,$/;" p module:axi_dmac_regmap_request +request_ready adi_library/axi_dmac/tb/regmap_tb.v /^ reg request_ready = 1'b0;$/;" r module:dmac_regmap_tb +request_src_address adi_library/axi_dmac/axi_dmac_regmap.v /^ output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] request_src_address,$/;" p module:axi_dmac_regmap +request_src_address adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] request_src_address,$/;" p module:axi_dmac_regmap_request +request_src_address adi_library/axi_dmac/tb/regmap_tb.v /^ wire [31:BYTES_PER_BEAT] request_src_address;$/;" n module:dmac_regmap_tb +request_src_stride adi_library/axi_dmac/axi_dmac_regmap.v /^ output [DMA_LENGTH_WIDTH-1:0] request_src_stride,$/;" p module:axi_dmac_regmap +request_src_stride adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output [DMA_LENGTH_WIDTH-1:0] request_src_stride,$/;" p module:axi_dmac_regmap_request +request_src_stride adi_library/axi_dmac/tb/regmap_tb.v /^ wire [DMA_LENGTH_WIDTH-1:0] request_src_stride;$/;" n module:dmac_regmap_tb +request_sync_transfer_start adi_library/axi_dmac/axi_dmac_regmap.v /^ output request_sync_transfer_start,$/;" p module:axi_dmac_regmap +request_sync_transfer_start adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output request_sync_transfer_start,$/;" p module:axi_dmac_regmap_request +request_valid adi_library/axi_dmac/axi_dmac_regmap.v /^ output request_valid,$/;" p module:axi_dmac_regmap +request_valid adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output request_valid,$/;" p module:axi_dmac_regmap_request +request_x_length adi_library/axi_dmac/axi_dmac_regmap.v /^ output [DMA_LENGTH_WIDTH-1:0] request_x_length,$/;" p module:axi_dmac_regmap +request_x_length adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output [DMA_LENGTH_WIDTH-1:0] request_x_length,$/;" p module:axi_dmac_regmap_request +request_x_length adi_library/axi_dmac/tb/regmap_tb.v /^ wire [DMA_LENGTH_WIDTH-1:0] request_x_length;$/;" n module:dmac_regmap_tb +request_y_length adi_library/axi_dmac/axi_dmac_regmap.v /^ output [DMA_LENGTH_WIDTH-1:0] request_y_length,$/;" p module:axi_dmac_regmap +request_y_length adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output [DMA_LENGTH_WIDTH-1:0] request_y_length,$/;" p module:axi_dmac_regmap_request +request_y_length adi_library/axi_dmac/tb/regmap_tb.v /^ wire [DMA_LENGTH_WIDTH-1:0] request_y_length;$/;" n module:dmac_regmap_tb +reset adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input reset,$/;" p module:axi_dmac_regmap_request +reset adi_library/axi_dmac/axi_dmac_resize_dest.v /^ input reset,$/;" p module:axi_dmac_resize_dest +reset adi_library/axi_dmac/axi_dmac_resize_src.v /^ input reset,$/;" p module:axi_dmac_resize_src +reset adi_library/axi_dmac/tb/axi_read_slave.v /^ input reset,$/;" p module:axi_read_slave +reset adi_library/axi_dmac/tb/axi_slave.v /^ input reset,$/;" p module:axi_slave +reset adi_library/axi_dmac/tb/axi_write_slave.v /^ input reset,$/;" p module:axi_write_slave +reset adi_library/axi_dmac/tb/tb_base.v /^ wire reset;$/;" n +reset adi_library/common/ad_pngen.v /^ input reset,$/;" p module:ad_pngen +reset adi_library/common/util_dec256sinc24b.v /^ input reset, \/* used to reset filter *\/$/;" p module:util_dec256sinc24b +reset adi_library/common/util_delay.v /^ input reset,$/;" p module:util_delay +reset adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input reset,$/;" p module:util_gmii_to_rgmii +reset adi_library/util_pack/tb/tb_base.v /^ wire reset;$/;" n +reset adi_library/util_pack/util_cpack2/util_cpack2.v /^ input reset,$/;" p module:util_cpack2 +reset adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ input reset,$/;" p module:util_cpack2_impl +reset adi_library/util_pack/util_pack_common/pack_shell.v /^ input reset,$/;" p module:pack_shell +reset adi_library/util_pack/util_upack2/util_upack2.v /^ input reset,$/;" p module:util_upack2 +reset adi_library/util_pack/util_upack2/util_upack2_impl.v /^ input reset,$/;" p module:util_upack2_impl +reset adi_library/util_var_fifo/util_var_fifo.v /^ wire reset;$/;" n module:util_var_fifo +reset_async adi_library/axi_dmac/axi_dmac_reset_manager.v /^ reg [3:0] reset_async = 4'b1111;$/;" r block:axi_dmac_reset_manager.reset_gen +reset_async_chain adi_library/axi_dmac/axi_dmac_reset_manager.v /^wire [3:0] reset_async_chain;$/;" n module:axi_dmac_reset_manager +reset_chain_clks adi_library/axi_dmac/axi_dmac_reset_manager.v /^wire [2:0] reset_chain_clks = {clk, src_clk, dest_clk};$/;" n module:axi_dmac_reset_manager +reset_counter adi_library/util_pack/tb/cpack_tb.v /^ integer reset_counter = 'h00;$/;" r module:cpack_tb +reset_ctrl adi_library/util_pack/util_pack_common/pack_shell.v /^ reg reset_ctrl = 1'b1;$/;" r module:pack_shell +reset_data adi_library/util_pack/tb/cpack_tb.v /^ reg reset_data = 1'b0;$/;" r module:cpack_tb +reset_data adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ wire reset_data;$/;" n module:util_cpack2_impl +reset_data adi_library/util_pack/util_pack_common/pack_shell.v /^ output reg reset_data = 1'b0,$/;" p module:pack_shell +reset_data adi_library/util_pack/util_upack2/util_upack2_impl.v /^ wire reset_data;$/;" n module:util_upack2_impl +reset_gen adi_library/axi_dmac/axi_dmac_reset_manager.v /^for (i = 0; i < 3; i = i + 1) begin: reset_gen$/;" b module:axi_dmac_reset_manager +reset_shift adi_library/axi_dmac/tb/tb_base.v /^ reg [3:0] reset_shift = 4'b1111;$/;" r +reset_shift adi_library/util_pack/tb/tb_base.v /^ reg [3:0] reset_shift = 4'b1111;$/;" r +reset_sync adi_library/axi_dmac/axi_dmac_reset_manager.v /^ reg [1:0] reset_sync = 2'b11;$/;" r block:axi_dmac_reset_manager.reset_gen +reset_sync_chain adi_library/axi_dmac/axi_dmac_reset_manager.v /^wire [3:0] reset_sync_chain;$/;" n module:axi_dmac_reset_manager +reset_sync_in adi_library/axi_dmac/axi_dmac_reset_manager.v /^ reg reset_sync_in = 1'b1;$/;" r block:axi_dmac_reset_manager.reset_gen +resetn adi_library/axi_dmac/address_generator.v /^ input resetn,$/;" p module:dmac_address_generator +resetn adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input resetn,$/;" p module:axi_dmac_reset_manager +resetn adi_library/axi_dmac/axi_register_slice.v /^ input resetn,$/;" p module:axi_register_slice +resetn adi_library/axi_dmac/data_mover.v /^ input resetn,$/;" p module:dmac_data_mover +resetn adi_library/axi_dmac/dest_fifo_inf.v /^ input resetn,$/;" p module:dmac_dest_fifo_inf +resetn adi_library/axi_dmac/request_generator.v /^ input resetn,$/;" p module:dmac_request_generator +resetn adi_library/axi_dmac/response_generator.v /^ input resetn,$/;" p module:dmac_response_generator +resetn adi_library/axi_dmac/response_handler.v /^ input resetn,$/;" p module:dmac_response_handler +resetn adi_library/axi_dmac/splitter.v /^ input resetn,$/;" p module:splitter +resetn adi_library/axi_dmac/src_fifo_inf.v /^ input resetn,$/;" p module:dmac_src_fifo_inf +resetn adi_library/axi_dmac/tb/tb_base.v /^ wire resetn = ~reset;$/;" n +resetn adi_library/common/util_axis_upscale.v /^ input resetn,$/;" p module:util_axis_upscale +resetn adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input resetn,$/;" p module:spi_engine_execution +resetn adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input resetn,$/;" p module:spi_engine_interconnect +resetn adi_library/util_axis_fifo/address_sync.v /^ input resetn,$/;" p module:fifo_address_sync +resetn adi_library/util_axis_resize/util_axis_resize.v /^ input resetn,$/;" p module:util_axis_resize +resetn adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ input resetn,$/;" p module:util_sigma_delta_spi +resetn_shift adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg [5:0] resetn_shift = 'h0;$/;" r module:dmac_reset_manager_tb +resp_count adi_library/axi_dmac/tb/axi_write_slave.v /^reg [4:0] resp_count = 'h00;$/;" r module:axi_write_slave +resp_count_dec adi_library/axi_dmac/tb/axi_write_slave.v /^wire resp_count_dec = bvalid & bready;$/;" n module:axi_write_slave +resp_count_inc adi_library/axi_dmac/tb/axi_write_slave.v /^wire resp_count_inc = wvalid & wready & beat_last;$/;" n module:axi_write_slave +resp_count_next adi_library/axi_dmac/tb/axi_write_slave.v /^wire [4:0] resp_count_next;$/;" n module:axi_write_slave +resp_eot adi_library/axi_dmac/response_generator.v /^ output resp_eot,$/;" p module:dmac_response_generator +resp_eot adi_library/axi_dmac/response_handler.v /^ output resp_eot,$/;" p module:dmac_response_handler +resp_ready adi_library/axi_dmac/response_generator.v /^ input resp_ready,$/;" p module:dmac_response_generator +resp_ready adi_library/axi_dmac/response_handler.v /^ input resp_ready,$/;" p module:dmac_response_handler +resp_resp adi_library/axi_dmac/response_generator.v /^ output [1:0] resp_resp$/;" p module:dmac_response_generator +resp_resp adi_library/axi_dmac/response_handler.v /^ output [1:0] resp_resp$/;" p module:dmac_response_handler +resp_valid adi_library/axi_dmac/response_generator.v /^ output resp_valid,$/;" p module:dmac_response_generator +resp_valid adi_library/axi_dmac/response_handler.v /^ output resp_valid,$/;" p module:dmac_response_handler +response_data_burst_length adi_library/axi_dmac/dest_axi_mm.v /^ output [BYTES_PER_BURST_WIDTH-1:0] response_data_burst_length,$/;" p module:dmac_dest_mm_axi +response_dest_data_burst_length adi_library/axi_dmac/axi_dmac_response_manager.v /^wire [BYTES_PER_BURST_WIDTH-1:0] response_dest_data_burst_length;$/;" n module:axi_dmac_response_manager +response_dest_ready adi_library/axi_dmac/axi_dmac_response_manager.v /^reg response_dest_ready = 1'b1;$/;" r module:axi_dmac_response_manager +response_dest_resp adi_library/axi_dmac/axi_dmac_response_manager.v /^wire [1:0] response_dest_resp;$/;" n module:axi_dmac_response_manager +response_dest_resp_eot adi_library/axi_dmac/axi_dmac_response_manager.v /^wire response_dest_resp_eot;$/;" n module:axi_dmac_response_manager +response_dest_valid adi_library/axi_dmac/axi_dmac_response_manager.v /^wire response_dest_valid;$/;" n module:axi_dmac_response_manager +response_eot adi_library/axi_dmac/axi_dmac_regmap.v /^ input response_eot,$/;" p module:axi_dmac_regmap +response_eot adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input response_eot,$/;" p module:axi_dmac_regmap_request +response_eot adi_library/axi_dmac/axi_dmac_response_manager.v /^ output response_eot,$/;" p module:axi_dmac_response_manager +response_eot adi_library/axi_dmac/dest_axi_mm.v /^ input response_eot,$/;" p module:dmac_dest_mm_axi +response_eot adi_library/axi_dmac/dest_axi_stream.v /^ input response_eot,$/;" p module:dmac_dest_axi_stream +response_eot adi_library/axi_dmac/dest_fifo_inf.v /^ input response_eot,$/;" p module:dmac_dest_fifo_inf +response_eot adi_library/axi_dmac/request_arb.v /^wire response_eot = eot_mem_dest[dest_response_id];$/;" n module:dmac_request_arb +response_eot adi_library/axi_dmac/tb/regmap_tb.v /^ reg response_eot = 1'b0;$/;" r module:dmac_regmap_tb +response_id adi_library/axi_dmac/data_mover.v /^ output [ID_WIDTH-1:0] response_id,$/;" p module:dmac_data_mover +response_id adi_library/axi_dmac/dest_axi_mm.v /^ output [ID_WIDTH-1:0] response_id,$/;" p module:dmac_dest_mm_axi +response_id adi_library/axi_dmac/dest_axi_stream.v /^ output [ID_WIDTH-1:0] response_id,$/;" p module:dmac_dest_axi_stream +response_id adi_library/axi_dmac/dest_fifo_inf.v /^ output [ID_WIDTH-1:0] response_id,$/;" p module:dmac_dest_fifo_inf +response_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] response_id;$/;" n module:dmac_request_arb +response_id adi_library/axi_dmac/request_generator.v /^ input [ID_WIDTH-1:0] response_id,$/;" p module:dmac_request_generator +response_id adi_library/axi_dmac/response_generator.v /^ output reg [ID_WIDTH-1:0] response_id,$/;" p module:dmac_response_generator +response_id adi_library/axi_dmac/src_axi_mm.v /^ output [ID_WIDTH-1:0] response_id,$/;" p module:dmac_src_mm_axi +response_id adi_library/axi_dmac/src_axi_stream.v /^ output [ID_WIDTH-1:0] response_id,$/;" p module:dmac_src_axi_stream +response_id adi_library/axi_dmac/src_fifo_inf.v /^ output [ID_WIDTH-1:0] response_id,$/;" p module:dmac_src_fifo_inf +response_measured_burst_length adi_library/axi_dmac/axi_dmac_regmap.v /^ input [BYTES_PER_BURST_WIDTH-1:0] response_measured_burst_length,$/;" p module:axi_dmac_regmap +response_measured_burst_length adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input [BYTES_PER_BURST_WIDTH-1:0] response_measured_burst_length,$/;" p module:axi_dmac_regmap_request +response_partial adi_library/axi_dmac/axi_dmac_regmap.v /^ input response_partial,$/;" p module:axi_dmac_regmap +response_partial adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input response_partial,$/;" p module:axi_dmac_regmap_request +response_partial adi_library/axi_dmac/axi_dmac_response_manager.v /^ output response_partial,$/;" p module:axi_dmac_response_manager +response_partial adi_library/axi_dmac/request_arb.v /^ output response_partial,$/;" p module:dmac_request_arb +response_ready adi_library/axi_dmac/axi_dmac_regmap.v /^ output response_ready,$/;" p module:axi_dmac_regmap +response_ready adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output reg response_ready = 1'b1$/;" p module:axi_dmac_regmap_request +response_ready adi_library/axi_dmac/axi_dmac_response_manager.v /^ input response_ready,$/;" p module:axi_dmac_response_manager +response_ready adi_library/axi_dmac/dest_axi_mm.v /^ input response_ready,$/;" p module:dmac_dest_mm_axi +response_ready adi_library/axi_dmac/dest_axi_stream.v /^ input response_ready,$/;" p module:dmac_dest_axi_stream +response_ready adi_library/axi_dmac/dest_fifo_inf.v /^ input response_ready,$/;" p module:dmac_dest_fifo_inf +response_ready adi_library/axi_dmac/request_arb.v /^ input response_ready,$/;" p module:dmac_request_arb +response_resp adi_library/axi_dmac/dest_axi_mm.v /^ output [1:0] response_resp,$/;" p module:dmac_dest_mm_axi +response_resp adi_library/axi_dmac/dest_axi_stream.v /^ output [1:0] response_resp$/;" p module:dmac_dest_axi_stream +response_resp adi_library/axi_dmac/dest_fifo_inf.v /^ output [1:0] response_resp$/;" p module:dmac_dest_fifo_inf +response_resp_eot adi_library/axi_dmac/dest_axi_mm.v /^ output response_resp_eot,$/;" p module:dmac_dest_mm_axi +response_resp_eot adi_library/axi_dmac/dest_axi_stream.v /^ output response_resp_eot,$/;" p module:dmac_dest_axi_stream +response_resp_eot adi_library/axi_dmac/dest_fifo_inf.v /^ output response_resp_eot,$/;" p module:dmac_dest_fifo_inf +response_resp_partial adi_library/axi_dmac/dest_axi_mm.v /^ output response_resp_partial,$/;" p module:dmac_dest_mm_axi +response_valid adi_library/axi_dmac/axi_dmac_regmap.v /^ input response_valid,$/;" p module:axi_dmac_regmap +response_valid adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input response_valid,$/;" p module:axi_dmac_regmap_request +response_valid adi_library/axi_dmac/axi_dmac_response_manager.v /^ output reg response_valid = 1'b0,$/;" p module:axi_dmac_response_manager +response_valid adi_library/axi_dmac/dest_axi_mm.v /^ output response_valid,$/;" p module:dmac_dest_mm_axi +response_valid adi_library/axi_dmac/dest_axi_stream.v /^ output response_valid,$/;" p module:dmac_dest_axi_stream +response_valid adi_library/axi_dmac/dest_fifo_inf.v /^ output response_valid,$/;" p module:dmac_dest_fifo_inf +response_valid adi_library/axi_dmac/request_arb.v /^ output response_valid,$/;" p module:dmac_request_arb +result_x adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) output reg [ D_DW-1:0] result_x,$/;" p module:ad_dds_cordic_pipe +result_y adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) output reg [ D_DW-1:0] result_y,$/;" p module:ad_dds_cordic_pipe +result_z adi_library/common/ad_dds_cordic_pipe.v /^ (* keep = "TRUE" *) output reg [ P_DW-1:0] result_z,$/;" p module:ad_dds_cordic_pipe +rew_id adi_library/axi_dmac/request_generator.v /^reg [ID_WIDTH-1:0] rew_id = 'h0;$/;" r module:dmac_request_generator +rew_req_xlast adi_library/axi_dmac/request_generator.v /^reg rew_req_xlast;$/;" r module:dmac_request_generator +rew_transfer_id adi_library/axi_dmac/request_generator.v /^reg [1:0] rew_transfer_id = 1'b0;$/;" r module:dmac_request_generator +rewind_req_data adi_library/axi_dmac/data_mover.v /^ output [ID_WIDTH+3-1:0] rewind_req_data,$/;" p module:dmac_data_mover +rewind_req_data adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH+3-1:0] rewind_req_data;$/;" n module:dmac_request_arb +rewind_req_data adi_library/axi_dmac/request_generator.v /^ input [ID_WIDTH+3-1:0] rewind_req_data,$/;" p module:dmac_request_generator +rewind_req_data adi_library/axi_dmac/src_axi_stream.v /^ output [ID_WIDTH+3-1:0] rewind_req_data,$/;" p module:dmac_src_axi_stream +rewind_req_ready adi_library/axi_dmac/data_mover.v /^ input rewind_req_ready,$/;" p module:dmac_data_mover +rewind_req_ready adi_library/axi_dmac/request_arb.v /^wire rewind_req_ready;$/;" n module:dmac_request_arb +rewind_req_ready adi_library/axi_dmac/request_generator.v /^ output rewind_req_ready,$/;" p module:dmac_request_generator +rewind_req_ready adi_library/axi_dmac/src_axi_stream.v /^ input rewind_req_ready,$/;" p module:dmac_src_axi_stream +rewind_req_valid adi_library/axi_dmac/data_mover.v /^ output rewind_req_valid,$/;" p module:dmac_data_mover +rewind_req_valid adi_library/axi_dmac/request_arb.v /^wire rewind_req_valid;$/;" n module:dmac_request_arb +rewind_req_valid adi_library/axi_dmac/request_generator.v /^ input rewind_req_valid,$/;" p module:dmac_request_generator +rewind_req_valid adi_library/axi_dmac/src_axi_stream.v /^ output rewind_req_valid,$/;" p module:dmac_src_axi_stream +rewind_state adi_library/axi_dmac/request_arb.v /^wire rewind_state;$/;" n module:dmac_request_arb +rewind_state adi_library/axi_dmac/request_generator.v /^ output rewind_state,$/;" p module:dmac_request_generator +rf_gpio hdl/system_top.v /^ output wire [ 5:0] rf_gpio,$/;" p module:system_top +rf_peak_det_enb_d adi_library/common/ad_adl5904_rst.v /^ reg rf_peak_det_enb_d = 'd0;$/;" r module:ad_adl5904_rst +rf_peak_det_enb_s adi_library/common/ad_adl5904_rst.v /^ wire rf_peak_det_enb_s;$/;" n module:ad_adl5904_rst +rf_peak_det_n adi_library/common/ad_adl5904_rst.v /^ input rf_peak_det_n,$/;" p module:ad_adl5904_rst +rf_peak_det_n_d adi_library/common/ad_adl5904_rst.v /^ reg rf_peak_det_n_d = 'd0;$/;" r module:ad_adl5904_rst +rf_peak_rst adi_library/common/ad_adl5904_rst.v /^ output rf_peak_rst);$/;" p module:ad_adl5904_rst +rf_peak_rst_0_s adi_library/common/ad_adl5904_rst.v /^ wire rf_peak_rst_0_s;$/;" n module:ad_adl5904_rst +rf_peak_rst_1_s adi_library/common/ad_adl5904_rst.v /^ wire rf_peak_rst_1_s;$/;" n module:ad_adl5904_rst +rf_peak_rst_enb adi_library/common/ad_adl5904_rst.v /^ reg rf_peak_rst_enb = 'd0;$/;" r module:ad_adl5904_rst +rf_peak_rst_int adi_library/common/ad_adl5904_rst.v /^ reg rf_peak_rst_int = 'd0;$/;" r module:ad_adl5904_rst +rgmii_rd adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input [ 3:0] rgmii_rd,$/;" p module:util_gmii_to_rgmii +rgmii_rd_delay adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ wire [ 3:0] rgmii_rd_delay;$/;" n module:util_gmii_to_rgmii +rgmii_rx_ctl adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input rgmii_rx_ctl,$/;" p module:util_gmii_to_rgmii +rgmii_rx_ctl_delay adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ wire rgmii_rx_ctl_delay;$/;" n module:util_gmii_to_rgmii +rgmii_rx_ctl_iddr adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) rgmii_rx_ctl_iddr ($/;" i module:util_gmii_to_rgmii typeref:module:IDDR +rgmii_rx_ctl_s adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ wire rgmii_rx_ctl_s;$/;" n module:util_gmii_to_rgmii +rgmii_rx_iddr adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) rgmii_rx_iddr ($/;" i module:util_gmii_to_rgmii typeref:module:IDDR +rgmii_rxc adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ input rgmii_rxc,$/;" p module:util_gmii_to_rgmii +rgmii_td adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ output [ 3:0] rgmii_td,$/;" p module:util_gmii_to_rgmii +rgmii_td_out adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) rgmii_td_out ($/;" i block:util_gmii_to_rgmii.gen_tx_data typeref:module:ODDR +rgmii_tx_ctl adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ output rgmii_tx_ctl,$/;" p module:util_gmii_to_rgmii +rgmii_tx_ctl_out adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) rgmii_tx_ctl_out ($/;" i module:util_gmii_to_rgmii typeref:module:ODDR +rgmii_tx_ctl_r adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ reg rgmii_tx_ctl_r;$/;" r module:util_gmii_to_rgmii +rgmii_txc adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ output rgmii_txc,$/;" p module:util_gmii_to_rgmii +rgmii_txc_out adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ ) rgmii_txc_out ($/;" i module:util_gmii_to_rgmii typeref:module:ODDR +rlast adi_library/axi_dmac/tb/axi_read_slave.v /^ output rlast$/;" p module:axi_read_slave +rlast adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire rlast;$/;" n module:dmac_dma_read_shutdown_tb +rlast adi_library/axi_dmac/tb/dma_read_tb.v /^ wire rlast;$/;" n module:dmac_dma_read_tb +room adi_library/util_axis_fifo/address_sync.v /^reg [ADDRESS_WIDTH:0] room = MAX_ROOM;$/;" r module:fifo_address_sync +rotate adi_library/util_pack/util_pack_common/pack_ctrl.v /^ input [PORT_ADDRESS_WIDTH-1:0] rotate,$/;" p module:pack_ctrl +rotate adi_library/util_pack/util_pack_common/pack_network.v /^ input [PORT_ADDRESS_WIDTH-1:0] rotate,$/;" p module:pack_network +rotate adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [SAMPLE_ADDRESS_WIDTH-1:0] rotate = 'h00;$/;" r module:pack_shell +rotate_headi hdl/phase_adjust.v /^ wire [5:0] rotate_headi;$/;" n module:phase_adjust +rotate_headq hdl/phase_adjust.v /^ wire [5:0] rotate_headq;$/;" n module:phase_adjust +rotate_msb adi_library/util_pack/util_pack_common/pack_shell.v /^ reg rotate_msb = 1'b0;$/;" r block:pack_shell.gen_input_buffer +rotate_nd hdl/phase_adjust.v /^ reg rotate_nd;$/;" r module:phase_adjust +rotate_next adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [SAMPLE_ADDRESS_WIDTH:0] rotate_next;$/;" r block:pack_shell.gen_input_buffer +rotate_next_next adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [SAMPLE_ADDRESS_WIDTH:0] rotate_next_next;$/;" n block:pack_shell.gen_input_buffer +rotate_rdy hdl/phase_adjust.v /^ wire rotate_rdy;$/;" n module:phase_adjust +rotation adi_library/common/ad_dds_sine_cordic.v /^ for (i=0; i < PHASE_DW-1; i=i+1) begin: rotation$/;" b module:ad_dds_sine_cordic +rready adi_library/axi_dmac/tb/axi_read_slave.v /^ input rready,$/;" p module:axi_read_slave +rready adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire rready;$/;" n module:dmac_dma_read_shutdown_tb +rready adi_library/axi_dmac/tb/dma_read_tb.v /^ wire rready;$/;" n module:dmac_dma_read_tb +rresp adi_library/axi_dmac/tb/axi_read_slave.v /^ output [1:0] rresp,$/;" p module:axi_read_slave +rresp adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire [1:0] rresp;$/;" n module:dmac_dma_read_shutdown_tb +rresp adi_library/axi_dmac/tb/dma_read_tb.v /^ wire [1:0] rresp;$/;" n module:dmac_dma_read_tb +rs232_send hdl/FrameMerge.v /^ reg rs232_send;$/;" r module:FrameMerge +rs_idx hdl/DDS_compensate.v /^ wire [2:0] rs_idx; $/;" n module:DDS_compensate +rs_idx_nd hdl/DDS_compensate.v /^ wire rs_idx_nd =1'b0;$/;" n module:DDS_compensate +rst adi_library/common/ad_axis_inf_rx.v /^ input rst,$/;" p module:ad_axis_inf_rx +rst adi_library/common/ad_edge_detect.v /^ input rst,$/;" p module:ad_edge_detect +rst adi_library/common/ad_pps_receiver.v /^ input rst,$/;" p module:ad_pps_receiver +rst adi_library/common/ad_rst.v /^ output reg rst);$/;" p module:ad_rst +rst adi_library/common/ad_tdd_control.v /^ input rst,$/;" p module:ad_tdd_control +rst adi_library/common/up_tdd_cntrl.v /^ input rst,$/;" p module:up_tdd_cntrl +rst adi_library/util_var_fifo/util_var_fifo.v /^ input rst,$/;" p module:util_var_fifo +rst adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ input rst,$/;" p module:axi_dacfifo_address_buffer +rst adi_library/xilinx/common/ad_data_clk.v /^ input rst,$/;" p module:ad_data_clk +rst adi_library/xilinx/common/ad_serdes_clk.v /^ input rst,$/;" p module:ad_serdes_clk +rst adi_library/xilinx/common/ad_serdes_in.v /^ input rst,$/;" p module:ad_serdes_in +rst adi_library/xilinx/common/ad_serdes_out.v /^ input rst,$/;" p module:ad_serdes_out +rst hdl/CCSDS_LDPC_ENC_R12.v /^ input rst,$/;" p module:CCSDS_LDPC_ENC_R12 +rst hdl/Chn_Estimate.v /^ input rst,$/;" p module:Chn_Estimate +rst hdl/DAGC_v2.v /^ input rst,$/;" p module:DAGC_v2 +rst hdl/DDS_compensate.v /^ input rst;$/;" p module:DDS_compensate +rst hdl/FrameMerge.v /^ input rst,$/;" p module:FrameMerge +rst hdl/IQmerge.v /^ input rst,$/;" p module:IQmerge +rst hdl/MF_Top.v /^ input rst,$/;" p module:MF_Top +rst hdl/MagnitudeEstimator.v /^ input rst,$/;" p module:MagnitudeEstimator +rst hdl/Noise_Estimate.v /^ input rst,$/;" p module:Noise_Estimate +rst hdl/Out_Process_R12.v /^ input rst,$/;" p module:Out_Process_R12 +rst hdl/PAPR.v /^ input rst,$/;" p module:PAPR +rst hdl/Receiver.v /^ input rst,$/;" p module:Receiver +rst hdl/RecvTop.v /^ input rst,$/;" p module:RecvTop +rst hdl/SCFDE_recv_FrameSync.v /^ input rst,$/;" p module:SCFDE_recv_FrameSync +rst hdl/SC_FDE_TOP.v /^ input rst,$/;" p module:SC_FDE_TOP +rst hdl/TSync_Abs_new16.v /^ input rst,$/;" p module:TSync_Abs_new16 +rst hdl/TSync_Abs_new4.v /^ input rst,$/;" p module:TSync_Abs_new4 +rst hdl/TimeSync_top.v /^ input rst,$/;" p module:TimeSync_top +rst hdl/Transmitter.v /^ input wire rst,$/;" p module:Transmitter +rst hdl/ad9361_mgc_pin_ctrl.v /^ input rst,$/;" p module:ad9361_mgc_pin_ctrl +rst hdl/data_equalizer.v /^ input rst,$/;" p module:data_equalizer +rst hdl/data_ow.v /^ input rst,$/;" p module:data_ow +rst hdl/enc_control.v /^ input rst,$/;" p module:enc_control +rst hdl/frame_sync.v /^ input rst,$/;" p module:frame_sync +rst hdl/freqestm.v /^ input rst,$/;" p module:freqestm +rst hdl/phase_adjust.v /^ input rst,$/;" p module:phase_adjust +rst hdl/power_measure.v /^ input rst,$/;" p module:power_measure +rst hdl/shift_reg.v /^ (* max_fanout = 256 *) input rst,$/;" p module:shift_reg +rst hdl/tdma.v /^ input rst,$/;" p module:tdma +rst hdl/width_convert.v /^ input rst,$/;" p module:width_convert +rst sim/tb_Receiver.v /^ reg rst;$/;" r module:tb_Receiver +rst sim/tb_Transmitter.v /^ reg rst = 1;$/;" r module:tb_Transmitter +rst sim/tb_add_prefix.v /^ reg rst = 0;$/;" r module:tb_add_prefix +rst sim/tb_enc_control.v /^ reg rst = 1;$/;" r module:tb_enc_control +rst sim/tb_tdma.v /^ reg rst = 1;$/;" r module:tb_tdma +rst sim/tb_width_convert.v /^ reg rst = 1;$/;" r module:tb_width_convert +rst2 hdl/FrameMerge.v /^ input rst2,$/;" p module:FrameMerge +rst2 hdl/RecvTop.v /^ input rst2,$/;" p module:RecvTop +rst_1 hdl/SCFDE_recv_FrameSync.v /^ reg rst_1 = 1'b0;$/;" r module:SCFDE_recv_FrameSync +rst_1_cnt hdl/SCFDE_recv_FrameSync.v /^ reg [7:0] rst_1_cnt = 8'b0;$/;" r module:SCFDE_recv_FrameSync +rst_TimeSync hdl/RecvTop.v /^ output rst_TimeSync,$/;" p module:RecvTop +rst_async adi_library/common/ad_rst.v /^ input rst_async,$/;" p module:ad_rst +rst_async_d1 adi_library/common/ad_rst.v /^ reg rst_async_d1 = 1'd1;$/;" r module:ad_rst +rst_async_d2 adi_library/common/ad_rst.v /^ reg rst_async_d2 = 1'd1;$/;" r module:ad_rst +rst_dagc hdl/DAGC_v2.v /^ output reg rst_dagc$/;" p module:DAGC_v2 +rst_dagc hdl/RecvTop.v /^ wire rst_dagc;$/;" n module:RecvTop +rst_freq hdl/RecvTop.v /^ output rst_freq,$/;" p module:RecvTop +rst_freq hdl/freqestm.v /^ output reg rst_freq$/;" p module:freqestm +rst_ready hdl/SCFDE_recv_FrameSync.v /^ input rst_ready,$/;" p module:SCFDE_recv_FrameSync +rst_sync adi_library/common/ad_rst.v /^ reg rst_sync = 1'd1;$/;" r module:ad_rst +rst_sync_d adi_library/common/ad_rst.v /^ reg rst_sync_d = 1'd1;$/;" r module:ad_rst +rst_sys hdl/system_top.v /^ wire rst_sys;$/;" n module:system_top +rst_sys sim/TB_sys.v /^ wire rst_sys;$/;" n module:TB_sys +rst_sys sim/tb_tx_with_enc.v /^ wire rst_sys;$/;" n module:tb_tx_with_enc +rstn adi_library/common/ad_rst.v /^ output rstn,$/;" p module:ad_rst +rstn adi_library/common/util_pulse_gen.v /^ input rstn,$/;" p module:util_pulse_gen +rstn adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire rstn;$/;" n module:axi_spi_engine +rstn adi_library/util_tdd_sync/util_tdd_sync.v /^ input rstn,$/;" p module:util_tdd_sync +rstn hdl/phy_control.v /^ input rstn, \/\/ can be floating if ASYNC_CLK == 0$/;" p module:phy_control +rtz hdl/Transmitter.v /^ reg [ 3:0] rtz; \/\/ return to zero$/;" r module:Transmitter +rvalid adi_library/axi_dmac/tb/axi_read_slave.v /^ output rvalid,$/;" p module:axi_read_slave +rvalid adi_library/axi_dmac/tb/dma_read_shutdown_tb.v /^ wire rvalid;$/;" n module:dmac_dma_read_shutdown_tb +rvalid adi_library/axi_dmac/tb/dma_read_tb.v /^ wire rvalid;$/;" n module:dmac_dma_read_tb +rx_0_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_0_n,$/;" p module:util_adxcvr +rx_0_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_0_p,$/;" p module:util_adxcvr +rx_10_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_10_n,$/;" p module:util_adxcvr +rx_10_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_10_p,$/;" p module:util_adxcvr +rx_11_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_11_n,$/;" p module:util_adxcvr +rx_11_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_11_p,$/;" p module:util_adxcvr +rx_12_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_12_n,$/;" p module:util_adxcvr +rx_12_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_12_p,$/;" p module:util_adxcvr +rx_13_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_13_n,$/;" p module:util_adxcvr +rx_13_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_13_p,$/;" p module:util_adxcvr +rx_14_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_14_n,$/;" p module:util_adxcvr +rx_14_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_14_p,$/;" p module:util_adxcvr +rx_15_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_15_n,$/;" p module:util_adxcvr +rx_15_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_15_p,$/;" p module:util_adxcvr +rx_1_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_1_n,$/;" p module:util_adxcvr +rx_1_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_1_p,$/;" p module:util_adxcvr +rx_2_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_2_n,$/;" p module:util_adxcvr +rx_2_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_2_p,$/;" p module:util_adxcvr +rx_3_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_3_n,$/;" p module:util_adxcvr +rx_3_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_3_p,$/;" p module:util_adxcvr +rx_4_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_4_n,$/;" p module:util_adxcvr +rx_4_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_4_p,$/;" p module:util_adxcvr +rx_5_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_5_n,$/;" p module:util_adxcvr +rx_5_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_5_p,$/;" p module:util_adxcvr +rx_6_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_6_n,$/;" p module:util_adxcvr +rx_6_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_6_p,$/;" p module:util_adxcvr +rx_7_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_7_n,$/;" p module:util_adxcvr +rx_7_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_7_p,$/;" p module:util_adxcvr +rx_8_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_8_n,$/;" p module:util_adxcvr +rx_8_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_8_p,$/;" p module:util_adxcvr +rx_9_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_9_n,$/;" p module:util_adxcvr +rx_9_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_9_p,$/;" p module:util_adxcvr +rx_calign adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg rx_calign = 'd0;$/;" r module:axi_xcvrlb_1 +rx_calign adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input rx_calign,$/;" p module:util_adxcvr_xch +rx_calign_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_0,$/;" p module:util_adxcvr +rx_calign_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_1,$/;" p module:util_adxcvr +rx_calign_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_10,$/;" p module:util_adxcvr +rx_calign_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_11,$/;" p module:util_adxcvr +rx_calign_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_12,$/;" p module:util_adxcvr +rx_calign_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_13,$/;" p module:util_adxcvr +rx_calign_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_14,$/;" p module:util_adxcvr +rx_calign_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_15,$/;" p module:util_adxcvr +rx_calign_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_2,$/;" p module:util_adxcvr +rx_calign_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_3,$/;" p module:util_adxcvr +rx_calign_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_4,$/;" p module:util_adxcvr +rx_calign_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_5,$/;" p module:util_adxcvr +rx_calign_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_6,$/;" p module:util_adxcvr +rx_calign_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_7,$/;" p module:util_adxcvr +rx_calign_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_8,$/;" p module:util_adxcvr +rx_calign_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_calign_9,$/;" p module:util_adxcvr +rx_charisk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output [ 3:0] rx_charisk,$/;" p module:util_adxcvr_xch +rx_charisk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_0,$/;" p module:util_adxcvr +rx_charisk_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_1,$/;" p module:util_adxcvr +rx_charisk_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_10,$/;" p module:util_adxcvr +rx_charisk_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_11,$/;" p module:util_adxcvr +rx_charisk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_12,$/;" p module:util_adxcvr +rx_charisk_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_13,$/;" p module:util_adxcvr +rx_charisk_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_14,$/;" p module:util_adxcvr +rx_charisk_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_15,$/;" p module:util_adxcvr +rx_charisk_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_2,$/;" p module:util_adxcvr +rx_charisk_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_3,$/;" p module:util_adxcvr +rx_charisk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_4,$/;" p module:util_adxcvr +rx_charisk_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_5,$/;" p module:util_adxcvr +rx_charisk_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_6,$/;" p module:util_adxcvr +rx_charisk_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_7,$/;" p module:util_adxcvr +rx_charisk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_8,$/;" p module:util_adxcvr +rx_charisk_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_charisk_9,$/;" p module:util_adxcvr +rx_charisk_open_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [11:0] rx_charisk_open_s;$/;" n module:util_adxcvr_xch +rx_charisk_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire [ 3:0] rx_charisk_s;$/;" n module:axi_xcvrlb_1 +rx_clk adi_library/common/ad_xcvr_rx_if.v /^ input rx_clk,$/;" p module:ad_xcvr_rx_if +rx_clk adi_library/xilinx/common/ad_data_in.v /^ input rx_clk,$/;" p module:ad_data_in +rx_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input rx_clk,$/;" p module:util_adxcvr_xch +rx_clk hdl/ad9361_dp_fdd_1r1t.v /^ input rx_clk,$/;" p module:ad9361_dp_fdd_1r1t +rx_clk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_0,$/;" p module:util_adxcvr +rx_clk_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_1,$/;" p module:util_adxcvr +rx_clk_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_10,$/;" p module:util_adxcvr +rx_clk_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_11,$/;" p module:util_adxcvr +rx_clk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_12,$/;" p module:util_adxcvr +rx_clk_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_13,$/;" p module:util_adxcvr +rx_clk_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_14,$/;" p module:util_adxcvr +rx_clk_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_15,$/;" p module:util_adxcvr +rx_clk_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_2,$/;" p module:util_adxcvr +rx_clk_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_3,$/;" p module:util_adxcvr +rx_clk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_4,$/;" p module:util_adxcvr +rx_clk_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_5,$/;" p module:util_adxcvr +rx_clk_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_6,$/;" p module:util_adxcvr +rx_clk_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_7,$/;" p module:util_adxcvr +rx_clk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_8,$/;" p module:util_adxcvr +rx_clk_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input rx_clk_9,$/;" p module:util_adxcvr +rx_data adi_library/common/ad_xcvr_rx_if.v /^ output reg [DW-1:0] rx_data);$/;" p module:ad_xcvr_rx_if +rx_data adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg [31:0] rx_data = 'd0;$/;" r module:axi_xcvrlb_1 +rx_data adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output [31:0] rx_data,$/;" p module:util_adxcvr_xch +rx_data hdl/ad9361_dp_fdd_1r1t.v /^ input [11:0] rx_data,$/;" p module:ad9361_dp_fdd_1r1t +rx_data_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_0,$/;" p module:util_adxcvr +rx_data_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_1,$/;" p module:util_adxcvr +rx_data_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_10,$/;" p module:util_adxcvr +rx_data_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_11,$/;" p module:util_adxcvr +rx_data_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_12,$/;" p module:util_adxcvr +rx_data_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_13,$/;" p module:util_adxcvr +rx_data_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_14,$/;" p module:util_adxcvr +rx_data_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_15,$/;" p module:util_adxcvr +rx_data_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_2,$/;" p module:util_adxcvr +rx_data_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_3,$/;" p module:util_adxcvr +rx_data_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_4,$/;" p module:util_adxcvr +rx_data_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_5,$/;" p module:util_adxcvr +rx_data_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_6,$/;" p module:util_adxcvr +rx_data_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_7,$/;" p module:util_adxcvr +rx_data_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_8,$/;" p module:util_adxcvr +rx_data_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [31:0] rx_data_9,$/;" p module:util_adxcvr +rx_data_i hdl/ad9361_dp_fdd_1r1t.v /^ output [11:0] rx_data_i,$/;" p module:ad9361_dp_fdd_1r1t +rx_data_i hdl/ad9361_mgc_pin_ctrl.v /^ input [11:0] rx_data_i,$/;" p module:ad9361_mgc_pin_ctrl +rx_data_ibuf_s adi_library/xilinx/common/ad_data_in.v /^ wire rx_data_ibuf_s;$/;" n module:ad_data_in +rx_data_iddr hdl/ad9361_dp_fdd_1r1t.v /^ for (i = 0; i < 12; i = i + 1) begin : rx_data_iddr$/;" b module:ad9361_dp_fdd_1r1t +rx_data_iddr_inst hdl/ad9361_dp_fdd_1r1t.v /^ ) rx_data_iddr_inst ($/;" i block:ad9361_dp_fdd_1r1t.rx_data_iddr typeref:module:IDDR +rx_data_idelay_s adi_library/xilinx/common/ad_data_in.v /^ wire rx_data_idelay_s;$/;" n module:ad_data_in +rx_data_in_n adi_library/xilinx/common/ad_data_in.v /^ input rx_data_in_n,$/;" p module:ad_data_in +rx_data_in_p adi_library/xilinx/common/ad_data_in.v /^ input rx_data_in_p,$/;" p module:ad_data_in +rx_data_n adi_library/xilinx/common/ad_data_in.v /^ output rx_data_n,$/;" p module:ad_data_in +rx_data_open_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [95:0] rx_data_open_s;$/;" n module:util_adxcvr_xch +rx_data_p adi_library/xilinx/common/ad_data_in.v /^ output rx_data_p,$/;" p module:ad_data_in +rx_data_q hdl/ad9361_dp_fdd_1r1t.v /^ output [11:0] rx_data_q,$/;" p module:ad9361_dp_fdd_1r1t +rx_data_q hdl/ad9361_mgc_pin_ctrl.v /^ input [11:0] rx_data_q,$/;" p module:ad9361_mgc_pin_ctrl +rx_data_s adi_library/common/ad_xcvr_rx_if.v /^ wire [OCTETS_PER_BEAT*DW-1:0] rx_data_s;$/;" n module:ad_xcvr_rx_if +rx_data_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire [31:0] rx_data_s;$/;" n module:axi_xcvrlb_1 +rx_disperr adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output [ 3:0] rx_disperr,$/;" p module:util_adxcvr_xch +rx_disperr_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_0,$/;" p module:util_adxcvr +rx_disperr_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_1,$/;" p module:util_adxcvr +rx_disperr_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_10,$/;" p module:util_adxcvr +rx_disperr_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_11,$/;" p module:util_adxcvr +rx_disperr_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_12,$/;" p module:util_adxcvr +rx_disperr_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_13,$/;" p module:util_adxcvr +rx_disperr_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_14,$/;" p module:util_adxcvr +rx_disperr_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_15,$/;" p module:util_adxcvr +rx_disperr_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_2,$/;" p module:util_adxcvr +rx_disperr_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_3,$/;" p module:util_adxcvr +rx_disperr_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_4,$/;" p module:util_adxcvr +rx_disperr_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_5,$/;" p module:util_adxcvr +rx_disperr_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_6,$/;" p module:util_adxcvr +rx_disperr_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_7,$/;" p module:util_adxcvr +rx_disperr_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_8,$/;" p module:util_adxcvr +rx_disperr_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_9,$/;" p module:util_adxcvr +rx_disperr_open_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [11:0] rx_disperr_open_s;$/;" n module:util_adxcvr_xch +rx_error_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire [ 7:0] rx_error_s;$/;" n module:axi_xcvrlb_1 +rx_frame hdl/ad9361_dp_fdd_1r1t.v /^ input rx_frame,$/;" p module:ad9361_dp_fdd_1r1t +rx_frame_i hdl/ad9361_dp_fdd_1r1t.v /^ output rx_frame_i,$/;" p module:ad9361_dp_fdd_1r1t +rx_frame_q hdl/ad9361_dp_fdd_1r1t.v /^ output rx_frame_q,$/;" p module:ad9361_dp_fdd_1r1t +rx_ip_data adi_library/common/ad_xcvr_rx_if.v /^ input [DW-1:0] rx_ip_data,$/;" p module:ad_xcvr_rx_if +rx_ip_data_d adi_library/common/ad_xcvr_rx_if.v /^ reg [DW-1:0] rx_ip_data_d = 'd0;$/;" r module:ad_xcvr_rx_if +rx_ip_sof adi_library/common/ad_xcvr_rx_if.v /^ input [OCTETS_PER_BEAT-1:0] rx_ip_sof,$/;" p module:ad_xcvr_rx_if +rx_ip_sof_d adi_library/common/ad_xcvr_rx_if.v /^ reg [OCTETS_PER_BEAT-1:0] rx_ip_sof_d = 'd0;$/;" r module:ad_xcvr_rx_if +rx_ip_sof_hold adi_library/common/ad_xcvr_rx_if.v /^ reg [OCTETS_PER_BEAT-1:0] rx_ip_sof_hold = 'd0;$/;" r module:ad_xcvr_rx_if +rx_kcount adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg [ 3:0] rx_kcount = 'd0;$/;" r module:axi_xcvrlb_1 +rx_n adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input [(NUM_OF_LANES-1):0] rx_n,$/;" p module:axi_xcvrlb +rx_n adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ input rx_n,$/;" p module:axi_xcvrlb_1 +rx_n adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input rx_n,$/;" p module:util_adxcvr_xch +rx_notintable adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output [ 3:0] rx_notintable,$/;" p module:util_adxcvr_xch +rx_notintable_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_0,$/;" p module:util_adxcvr +rx_notintable_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_1,$/;" p module:util_adxcvr +rx_notintable_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_10,$/;" p module:util_adxcvr +rx_notintable_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_11,$/;" p module:util_adxcvr +rx_notintable_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_12,$/;" p module:util_adxcvr +rx_notintable_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_13,$/;" p module:util_adxcvr +rx_notintable_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_14,$/;" p module:util_adxcvr +rx_notintable_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_15,$/;" p module:util_adxcvr +rx_notintable_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_2,$/;" p module:util_adxcvr +rx_notintable_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_3,$/;" p module:util_adxcvr +rx_notintable_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_4,$/;" p module:util_adxcvr +rx_notintable_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_5,$/;" p module:util_adxcvr +rx_notintable_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_6,$/;" p module:util_adxcvr +rx_notintable_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_7,$/;" p module:util_adxcvr +rx_notintable_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_8,$/;" p module:util_adxcvr +rx_notintable_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_notintable_9,$/;" p module:util_adxcvr +rx_notintable_open_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [ 3:0] rx_notintable_open_s;$/;" n module:util_adxcvr_xch +rx_out_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output rx_out_clk,$/;" p module:util_adxcvr_xch +rx_out_clk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_0,$/;" p module:util_adxcvr +rx_out_clk_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_1,$/;" p module:util_adxcvr +rx_out_clk_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_10,$/;" p module:util_adxcvr +rx_out_clk_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_11,$/;" p module:util_adxcvr +rx_out_clk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_12,$/;" p module:util_adxcvr +rx_out_clk_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_13,$/;" p module:util_adxcvr +rx_out_clk_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_14,$/;" p module:util_adxcvr +rx_out_clk_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_15,$/;" p module:util_adxcvr +rx_out_clk_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_2,$/;" p module:util_adxcvr +rx_out_clk_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_3,$/;" p module:util_adxcvr +rx_out_clk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_4,$/;" p module:util_adxcvr +rx_out_clk_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_5,$/;" p module:util_adxcvr +rx_out_clk_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_6,$/;" p module:util_adxcvr +rx_out_clk_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_7,$/;" p module:util_adxcvr +rx_out_clk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_8,$/;" p module:util_adxcvr +rx_out_clk_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output rx_out_clk_9,$/;" p module:util_adxcvr +rx_out_clk_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire rx_out_clk_s;$/;" n module:util_adxcvr_xch +rx_p adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input [(NUM_OF_LANES-1):0] rx_p,$/;" p module:axi_xcvrlb +rx_p adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ input rx_p,$/;" p module:axi_xcvrlb_1 +rx_p adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input rx_p,$/;" p module:util_adxcvr_xch +rx_pll_clk_sel_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [ 1:0] rx_pll_clk_sel_s;$/;" n module:util_adxcvr_xch +rx_pn_data adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg [31:0] rx_pn_data = 'd0;$/;" r module:axi_xcvrlb_1 +rx_pn_data_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire [31:0] rx_pn_data_s;$/;" n module:axi_xcvrlb_1 +rx_pn_err_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire rx_pn_err_s;$/;" n module:axi_xcvrlb_1 +rx_pn_oos_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire rx_pn_oos_s;$/;" n module:axi_xcvrlb_1 +rx_rate_m1 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [ 2:0] rx_rate_m1 = 'd0;$/;" r module:util_adxcvr_xch +rx_rate_m2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [ 2:0] rx_rate_m2 = 'd0;$/;" r module:util_adxcvr_xch +rx_reset_d1 adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ reg rx_reset_d1;$/;" r module:util_gmii_to_rgmii +rx_rst_done_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire rx_rst_done_s;$/;" n module:util_adxcvr_xch +rx_sof adi_library/common/ad_xcvr_rx_if.v /^ output reg rx_sof,$/;" p module:ad_xcvr_rx_if +rx_status_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire rx_status_s;$/;" n module:axi_xcvrlb_1 +rx_sys_clk_sel_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [ 1:0] rx_sys_clk_sel_s;$/;" n module:util_adxcvr_xch +s adi_library/util_pack/util_pack_common/pack_ctrl.v /^ localparam s = (i*NUM_OF_PORTS+j)*MUX_ORDER;$/;" c block:pack_ctrl.ctrl_gen_outer.ctrl_gen_inner +s0_cmd_data adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input [15:0] s0_cmd_data,$/;" p module:spi_engine_interconnect +s0_cmd_ready adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output s0_cmd_ready,$/;" p module:spi_engine_interconnect +s0_cmd_valid adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input s0_cmd_valid,$/;" p module:spi_engine_interconnect +s0_sdi_data adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,$/;" p module:spi_engine_interconnect +s0_sdi_ready adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input s0_sdi_ready,$/;" p module:spi_engine_interconnect +s0_sdi_valid adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output s0_sdi_valid,$/;" p module:spi_engine_interconnect +s0_sdo_data adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input [(DATA_WIDTH-1):0] s0_sdo_data,$/;" p module:spi_engine_interconnect +s0_sdo_ready adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output s0_sdo_ready,$/;" p module:spi_engine_interconnect +s0_sdo_valid adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input s0_sdo_valid,$/;" p module:spi_engine_interconnect +s0_sync adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output [7:0] s0_sync,$/;" p module:spi_engine_interconnect +s0_sync_ready adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input s0_sync_ready,$/;" p module:spi_engine_interconnect +s0_sync_valid adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output s0_sync_valid,$/;" p module:spi_engine_interconnect +s1_angle adi_library/common/ad_dds_sine.v /^ reg [15:0] s1_angle = 'd0;$/;" r module:ad_dds_sine +s1_angle_s adi_library/common/ad_dds_sine.v /^ wire [15:0] s1_angle_s;$/;" n module:ad_dds_sine +s1_cmd_data adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input [15:0] s1_cmd_data,$/;" p module:spi_engine_interconnect +s1_cmd_ready adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output s1_cmd_ready,$/;" p module:spi_engine_interconnect +s1_cmd_valid adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input s1_cmd_valid,$/;" p module:spi_engine_interconnect +s1_data_n adi_library/common/ad_dds_sine.v /^ reg [33:0] s1_data_n = 'd0;$/;" r module:ad_dds_sine +s1_data_p adi_library/common/ad_dds_sine.v /^ reg [33:0] s1_data_p = 'd0;$/;" r module:ad_dds_sine +s1_data_s adi_library/common/ad_dds_1.v /^ wire [DDS_D_DW+17:0] s1_data_s;$/;" n module:ad_dds_1 +s1_data_s adi_library/common/ad_dds_sine.v /^ wire [33:0] s1_data_s;$/;" n module:ad_dds_sine +s1_ddata adi_library/common/ad_dds_sine.v /^ reg [(DELAY_DATA_WIDTH-1):0] s1_ddata = 'd0;$/;" r module:ad_dds_sine +s1_ddata_s adi_library/common/ad_dds_sine.v /^ wire [(DELAY_DATA_WIDTH-1):0] s1_ddata_s;$/;" n module:ad_dds_sine +s1_sdi_data adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,$/;" p module:spi_engine_interconnect +s1_sdi_ready adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input s1_sdi_ready,$/;" p module:spi_engine_interconnect +s1_sdi_valid adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output s1_sdi_valid,$/;" p module:spi_engine_interconnect +s1_sdo_data adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input [(DATA_WIDTH-1):0] s1_sdo_data,$/;" p module:spi_engine_interconnect +s1_sdo_ready adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output s1_sdo_ready,$/;" p module:spi_engine_interconnect +s1_sdo_valid adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input s1_sdo_valid,$/;" p module:spi_engine_interconnect +s1_sync adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output [7:0] s1_sync$/;" p module:spi_engine_interconnect +s1_sync_ready adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ input s1_sync_ready,$/;" p module:spi_engine_interconnect +s1_sync_valid adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^ output s1_sync_valid,$/;" p module:spi_engine_interconnect +s2_data_0 adi_library/common/ad_dds_sine.v /^ reg [18:0] s2_data_0 = 'd0;$/;" r module:ad_dds_sine +s2_data_1 adi_library/common/ad_dds_sine.v /^ reg [18:0] s2_data_1 = 'd0;$/;" r module:ad_dds_sine +s2_ddata adi_library/common/ad_dds_sine.v /^ reg [(DELAY_DATA_WIDTH-1):0] s2_ddata = 'd0;$/;" r module:ad_dds_sine +s3_data adi_library/common/ad_dds_sine.v /^ reg [18:0] s3_data = 'd0;$/;" r module:ad_dds_sine +s3_ddata adi_library/common/ad_dds_sine.v /^ reg [(DELAY_DATA_WIDTH-1):0] s3_ddata = 'd0;$/;" r module:ad_dds_sine +s422_CbCr adi_library/common/ad_ss_422to444.v /^ wire [ 7:0] s422_CbCr;$/;" n module:ad_ss_422to444 +s422_CbCr_2d adi_library/common/ad_ss_422to444.v /^ reg [7:0] s422_CbCr_2d;$/;" r module:ad_ss_422to444 +s422_CbCr_avg adi_library/common/ad_ss_422to444.v /^ reg [ 8:0] s422_CbCr_avg;$/;" r module:ad_ss_422to444 +s422_CbCr_d adi_library/common/ad_ss_422to444.v /^ reg [7:0] s422_CbCr_d;$/;" r module:ad_ss_422to444 +s422_Y adi_library/common/ad_ss_422to444.v /^ wire [ 7:0] s422_Y;$/;" n module:ad_ss_422to444 +s422_Y_d adi_library/common/ad_ss_422to444.v /^ reg [7:0] s422_Y_d;$/;" r module:ad_ss_422to444 +s422_data adi_library/common/ad_ss_422to444.v /^ input [ 15:0] s422_data,$/;" p module:ad_ss_422to444 +s422_data adi_library/common/ad_ss_444to422.v /^ output reg [15:0] s422_data);$/;" p module:ad_ss_444to422 +s422_de adi_library/common/ad_ss_422to444.v /^ input s422_de,$/;" p module:ad_ss_422to444 +s422_de_2d adi_library/common/ad_ss_422to444.v /^ reg s422_de_2d = 'd0;$/;" r module:ad_ss_422to444 +s422_de_d adi_library/common/ad_ss_422to444.v /^ reg s422_de_d = 'd0;$/;" r module:ad_ss_422to444 +s422_sync adi_library/common/ad_ss_422to444.v /^ input [DELAY_DATA_WIDTH-1:0] s422_sync,$/;" p module:ad_ss_422to444 +s422_sync adi_library/common/ad_ss_444to422.v /^ output reg [DELAY_DATA_WIDTH-1:0] s422_sync,$/;" p module:ad_ss_444to422 +s422_sync_d adi_library/common/ad_ss_422to444.v /^ reg [DW:0] s422_sync_d = 'd0;$/;" r module:ad_ss_422to444 +s444_data adi_library/common/ad_ss_422to444.v /^ output reg [ 23:0] s444_data);$/;" p module:ad_ss_422to444 +s444_data adi_library/common/ad_ss_444to422.v /^ input [23:0] s444_data,$/;" p module:ad_ss_444to422 +s444_data_2d adi_library/common/ad_ss_444to422.v /^ reg [23:0] s444_data_2d = 'd0;$/;" r module:ad_ss_444to422 +s444_data_3d adi_library/common/ad_ss_444to422.v /^ reg [23:0] s444_data_3d = 'd0;$/;" r module:ad_ss_444to422 +s444_data_d adi_library/common/ad_ss_444to422.v /^ reg [23:0] s444_data_d = 'd0;$/;" r module:ad_ss_444to422 +s444_de adi_library/common/ad_ss_444to422.v /^ input s444_de,$/;" p module:ad_ss_444to422 +s444_de_2d adi_library/common/ad_ss_444to422.v /^ reg s444_de_2d = 'd0;$/;" r module:ad_ss_444to422 +s444_de_3d adi_library/common/ad_ss_444to422.v /^ reg s444_de_3d = 'd0;$/;" r module:ad_ss_444to422 +s444_de_d adi_library/common/ad_ss_444to422.v /^ reg s444_de_d = 'd0;$/;" r module:ad_ss_444to422 +s444_sync adi_library/common/ad_ss_422to444.v /^ output reg [DELAY_DATA_WIDTH-1:0] s444_sync,$/;" p module:ad_ss_422to444 +s444_sync adi_library/common/ad_ss_444to422.v /^ input [DELAY_DATA_WIDTH-1:0] s444_sync,$/;" p module:ad_ss_444to422 +s444_sync_2d adi_library/common/ad_ss_444to422.v /^ reg [DW:0] s444_sync_2d = 'd0;$/;" r module:ad_ss_444to422 +s444_sync_3d adi_library/common/ad_ss_444to422.v /^ reg [DW:0] s444_sync_3d = 'd0;$/;" r module:ad_ss_444to422 +s444_sync_d adi_library/common/ad_ss_444to422.v /^ reg [DW:0] s444_sync_d = 'd0;$/;" r module:ad_ss_444to422 +s4_data1_n adi_library/common/ad_dds_sine.v /^ reg [16:0] s4_data1_n = 'd0;$/;" r module:ad_dds_sine +s4_data1_p adi_library/common/ad_dds_sine.v /^ reg [16:0] s4_data1_p = 'd0;$/;" r module:ad_dds_sine +s4_data1_s adi_library/common/ad_dds_sine.v /^ wire [16:0] s4_data1_s;$/;" n module:ad_dds_sine +s4_data2_n adi_library/common/ad_dds_sine.v /^ reg [33:0] s4_data2_n = 'd0;$/;" r module:ad_dds_sine +s4_data2_p adi_library/common/ad_dds_sine.v /^ reg [33:0] s4_data2_p = 'd0;$/;" r module:ad_dds_sine +s4_data2_s adi_library/common/ad_dds_sine.v /^ wire [33:0] s4_data2_s;$/;" n module:ad_dds_sine +s4_ddata adi_library/common/ad_dds_sine.v /^ reg [(DELAY_DATA_WIDTH-1):0] s4_ddata = 'd0;$/;" r module:ad_dds_sine +s4_ddata_s adi_library/common/ad_dds_sine.v /^ wire [(DELAY_DATA_WIDTH-1):0] s4_ddata_s;$/;" n module:ad_dds_sine +s5_data1 adi_library/common/ad_dds_sine.v /^ reg [16:0] s5_data1 = 'd0;$/;" r module:ad_dds_sine +s5_data2_0 adi_library/common/ad_dds_sine.v /^ reg [16:0] s5_data2_0 = 'd0;$/;" r module:ad_dds_sine +s5_data2_1 adi_library/common/ad_dds_sine.v /^ reg [16:0] s5_data2_1 = 'd0;$/;" r module:ad_dds_sine +s5_ddata adi_library/common/ad_dds_sine.v /^ reg [(DELAY_DATA_WIDTH-1):0] s5_ddata = 'd0;$/;" r module:ad_dds_sine +s6_data1 adi_library/common/ad_dds_sine.v /^ reg [16:0] s6_data1 = 'd0;$/;" r module:ad_dds_sine +s6_data2 adi_library/common/ad_dds_sine.v /^ reg [16:0] s6_data2 = 'd0;$/;" r module:ad_dds_sine +s6_ddata adi_library/common/ad_dds_sine.v /^ reg [(DELAY_DATA_WIDTH-1):0] s6_ddata = 'd0;$/;" r module:ad_dds_sine +s7_data adi_library/common/ad_dds_sine.v /^ reg [33:0] s7_data = 'd0;$/;" r module:ad_dds_sine +s7_data1_s adi_library/common/ad_dds_sine.v /^ wire [33:0] s7_data1_s;$/;" n module:ad_dds_sine +s7_data2_s adi_library/common/ad_dds_sine.v /^ wire [33:0] s7_data2_s;$/;" n module:ad_dds_sine +s7_ddata adi_library/common/ad_dds_sine.v /^ reg [(DELAY_DATA_WIDTH-1):0] s7_ddata = 'd0;$/;" r module:ad_dds_sine +s7_ddata_s adi_library/common/ad_dds_sine.v /^ wire [(DELAY_DATA_WIDTH-1):0] s7_ddata_s;$/;" n module:ad_dds_sine +s_active adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^reg s_active = 1'b0;$/;" r module:spi_engine_interconnect +s_axi_aclk adi_library/axi_dmac/axi_dmac.v /^ input s_axi_aclk,$/;" p module:axi_dmac +s_axi_aclk adi_library/axi_dmac/axi_dmac_regmap.v /^ input s_axi_aclk,$/;" p module:axi_dmac_regmap +s_axi_aclk adi_library/axi_dmac/tb/regmap_tb.v /^ wire s_axi_aclk = clk;$/;" n module:dmac_regmap_tb +s_axi_aclk adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input s_axi_aclk,$/;" p module:axi_spi_engine +s_axi_aclk adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input s_axi_aclk,$/;" p module:axi_adxcvr +s_axi_aclk adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input s_axi_aclk,$/;" p module:axi_xcvrlb +s_axi_aclk hdl/phy_control.v /^ input s_axi_aclk, (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ARE/;" p module:phy_control +s_axi_araddr adi_library/axi_dmac/axi_dmac.v /^ input [10:0] s_axi_araddr,$/;" p module:axi_dmac +s_axi_araddr adi_library/axi_dmac/axi_dmac_regmap.v /^ input [10:0] s_axi_araddr,$/;" p module:axi_dmac_regmap +s_axi_araddr adi_library/axi_dmac/tb/regmap_tb.v /^ reg [AW-1:0] s_axi_araddr = 'h0;$/;" r module:dmac_regmap_tb +s_axi_araddr adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [15:0] s_axi_araddr,$/;" p module:axi_spi_engine +s_axi_araddr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] s_axi_araddr,$/;" p module:axi_adxcvr +s_axi_araddr adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input [15:0] s_axi_araddr,$/;" p module:axi_xcvrlb +s_axi_araddr hdl/phy_control.v /^ input [AXI_ADDRESS_WIDTH-1:0] s_axi_araddr, (* X_INTERFACE_INFO = "xilinx.com:interface:axi/;" p module:phy_control +s_axi_aresetn adi_library/axi_dmac/axi_dmac.v /^ input s_axi_aresetn,$/;" p module:axi_dmac +s_axi_aresetn adi_library/axi_dmac/axi_dmac_regmap.v /^ input s_axi_aresetn,$/;" p module:axi_dmac_regmap +s_axi_aresetn adi_library/axi_dmac/tb/regmap_tb.v /^ wire s_axi_aresetn = ~reset;$/;" n module:dmac_regmap_tb +s_axi_aresetn adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input s_axi_aresetn,$/;" p module:axi_spi_engine +s_axi_aresetn adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input s_axi_aresetn,$/;" p module:axi_adxcvr +s_axi_aresetn adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input s_axi_aresetn,$/;" p module:axi_xcvrlb +s_axi_aresetn hdl/phy_control.v /^ input s_axi_aresetn, (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME /;" p module:phy_control +s_axi_arprot adi_library/axi_dmac/axi_dmac.v /^ input [2:0] s_axi_arprot,$/;" p module:axi_dmac +s_axi_arprot adi_library/axi_dmac/axi_dmac_regmap.v /^ input [2:0] s_axi_arprot,$/;" p module:axi_dmac_regmap +s_axi_arprot adi_library/axi_dmac/tb/regmap_tb.v /^ wire [2:0] s_axi_arprot = 3'b000;$/;" n module:dmac_regmap_tb +s_axi_arprot adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [2:0] s_axi_arprot,$/;" p module:axi_spi_engine +s_axi_arprot adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [ 2:0] s_axi_arprot,$/;" p module:axi_adxcvr +s_axi_arprot adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input [ 2:0] s_axi_arprot,$/;" p module:axi_xcvrlb +s_axi_arprot hdl/phy_control.v /^ input [ 2:0] s_axi_arprot, (* X_INTERFACE_INFO = "xilinx.com:interface:axi/;" p module:phy_control +s_axi_arready adi_library/axi_dmac/axi_dmac.v /^ output s_axi_arready,$/;" p module:axi_dmac +s_axi_arready adi_library/axi_dmac/axi_dmac_regmap.v /^ output s_axi_arready,$/;" p module:axi_dmac_regmap +s_axi_arready adi_library/axi_dmac/tb/regmap_tb.v /^ wire s_axi_arready;$/;" n module:dmac_regmap_tb +s_axi_arready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output s_axi_arready,$/;" p module:axi_spi_engine +s_axi_arready adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output s_axi_arready,$/;" p module:axi_adxcvr +s_axi_arready adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output s_axi_arready,$/;" p module:axi_xcvrlb +s_axi_arready hdl/phy_control.v /^ output s_axi_arready, (* X_INTERFACE_INFO = "xilinx.com:interface:ax/;" p module:phy_control +s_axi_arvalid adi_library/axi_dmac/axi_dmac.v /^ input s_axi_arvalid,$/;" p module:axi_dmac +s_axi_arvalid adi_library/axi_dmac/axi_dmac_regmap.v /^ input s_axi_arvalid,$/;" p module:axi_dmac_regmap +s_axi_arvalid adi_library/axi_dmac/tb/regmap_tb.v /^ reg s_axi_arvalid = 'h0;$/;" r module:dmac_regmap_tb +s_axi_arvalid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input s_axi_arvalid,$/;" p module:axi_spi_engine +s_axi_arvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input s_axi_arvalid,$/;" p module:axi_adxcvr +s_axi_arvalid adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input s_axi_arvalid,$/;" p module:axi_xcvrlb +s_axi_arvalid hdl/phy_control.v /^ input s_axi_arvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:ax/;" p module:phy_control +s_axi_awaddr adi_library/axi_dmac/axi_dmac.v /^ input [10:0] s_axi_awaddr,$/;" p module:axi_dmac +s_axi_awaddr adi_library/axi_dmac/axi_dmac_regmap.v /^ input [10:0] s_axi_awaddr,$/;" p module:axi_dmac_regmap +s_axi_awaddr adi_library/axi_dmac/tb/regmap_tb.v /^ reg [AW-1:0] s_axi_awaddr = 'h00;$/;" r module:dmac_regmap_tb +s_axi_awaddr adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [15:0] s_axi_awaddr,$/;" p module:axi_spi_engine +s_axi_awaddr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] s_axi_awaddr,$/;" p module:axi_adxcvr +s_axi_awaddr adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input [15:0] s_axi_awaddr,$/;" p module:axi_xcvrlb +s_axi_awaddr hdl/phy_control.v /^ input [AXI_ADDRESS_WIDTH-1:0] s_axi_awaddr, (* X_INTERFACE_INFO = "xilinx.com:interface:axi/;" p module:phy_control +s_axi_awprot adi_library/axi_dmac/axi_dmac.v /^ input [2:0] s_axi_awprot,$/;" p module:axi_dmac +s_axi_awprot adi_library/axi_dmac/axi_dmac_regmap.v /^ input [2:0] s_axi_awprot,$/;" p module:axi_dmac_regmap +s_axi_awprot adi_library/axi_dmac/tb/regmap_tb.v /^ wire [2:0] s_axi_awprot = 3'b000;$/;" n module:dmac_regmap_tb +s_axi_awprot adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [2:0] s_axi_awprot,$/;" p module:axi_spi_engine +s_axi_awprot adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [ 2:0] s_axi_awprot,$/;" p module:axi_adxcvr +s_axi_awprot adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input [ 2:0] s_axi_awprot,$/;" p module:axi_xcvrlb +s_axi_awprot hdl/phy_control.v /^ input [ 2:0] s_axi_awprot, (* X_INTERFACE_INFO = "xilinx.com:interface:axi/;" p module:phy_control +s_axi_awready adi_library/axi_dmac/axi_dmac.v /^ output s_axi_awready,$/;" p module:axi_dmac +s_axi_awready adi_library/axi_dmac/axi_dmac_regmap.v /^ output s_axi_awready,$/;" p module:axi_dmac_regmap +s_axi_awready adi_library/axi_dmac/tb/regmap_tb.v /^ wire s_axi_awready;$/;" n module:dmac_regmap_tb +s_axi_awready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output s_axi_awready,$/;" p module:axi_spi_engine +s_axi_awready adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output s_axi_awready,$/;" p module:axi_adxcvr +s_axi_awready adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output s_axi_awready,$/;" p module:axi_xcvrlb +s_axi_awready hdl/phy_control.v /^ output s_axi_awready, (* X_INTERFACE_INFO = "xilinx.com:interface:ax/;" p module:phy_control +s_axi_awvalid adi_library/axi_dmac/axi_dmac.v /^ input s_axi_awvalid,$/;" p module:axi_dmac +s_axi_awvalid adi_library/axi_dmac/axi_dmac_regmap.v /^ input s_axi_awvalid,$/;" p module:axi_dmac_regmap +s_axi_awvalid adi_library/axi_dmac/tb/regmap_tb.v /^ reg s_axi_awvalid = 1'b0;$/;" r module:dmac_regmap_tb +s_axi_awvalid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input s_axi_awvalid,$/;" p module:axi_spi_engine +s_axi_awvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input s_axi_awvalid,$/;" p module:axi_adxcvr +s_axi_awvalid adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input s_axi_awvalid,$/;" p module:axi_xcvrlb +s_axi_awvalid hdl/phy_control.v /^ input s_axi_awvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:ax/;" p module:phy_control +s_axi_bready adi_library/axi_dmac/axi_dmac.v /^ input s_axi_bready,$/;" p module:axi_dmac +s_axi_bready adi_library/axi_dmac/axi_dmac_regmap.v /^ input s_axi_bready,$/;" p module:axi_dmac_regmap +s_axi_bready adi_library/axi_dmac/tb/regmap_tb.v /^ wire s_axi_bready = 1'b1;$/;" n module:dmac_regmap_tb +s_axi_bready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input s_axi_bready,$/;" p module:axi_spi_engine +s_axi_bready adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input s_axi_bready,$/;" p module:axi_adxcvr +s_axi_bready adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input s_axi_bready,$/;" p module:axi_xcvrlb +s_axi_bready hdl/phy_control.v /^ input s_axi_bready, (* X_INTERFACE_INFO = "xilinx.com:interface:axi/;" p module:phy_control +s_axi_bresp adi_library/axi_dmac/axi_dmac.v /^ output [ 1:0] s_axi_bresp,$/;" p module:axi_dmac +s_axi_bresp adi_library/axi_dmac/axi_dmac_regmap.v /^ output [1:0] s_axi_bresp,$/;" p module:axi_dmac_regmap +s_axi_bresp adi_library/axi_dmac/tb/regmap_tb.v /^ wire [1:0] s_axi_bresp;$/;" n module:dmac_regmap_tb +s_axi_bresp adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output [ 1:0] s_axi_bresp,$/;" p module:axi_spi_engine +s_axi_bresp adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] s_axi_bresp,$/;" p module:axi_adxcvr +s_axi_bresp adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output [ 1:0] s_axi_bresp,$/;" p module:axi_xcvrlb +s_axi_bresp hdl/phy_control.v /^ output [ 1:0] s_axi_bresp, (* X_INTERFACE_INFO = "xilinx.com:interface:axim/;" p module:phy_control +s_axi_bvalid adi_library/axi_dmac/axi_dmac.v /^ output s_axi_bvalid,$/;" p module:axi_dmac +s_axi_bvalid adi_library/axi_dmac/axi_dmac_regmap.v /^ output s_axi_bvalid,$/;" p module:axi_dmac_regmap +s_axi_bvalid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output s_axi_bvalid,$/;" p module:axi_spi_engine +s_axi_bvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output s_axi_bvalid,$/;" p module:axi_adxcvr +s_axi_bvalid adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output s_axi_bvalid,$/;" p module:axi_xcvrlb +s_axi_bvalid hdl/phy_control.v /^ output s_axi_bvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:axi/;" p module:phy_control +s_axi_data adi_library/axi_dmac/axi_register_slice.v /^ input [DATA_WIDTH-1:0] s_axi_data,$/;" p module:axi_register_slice +s_axi_data adi_library/axi_dmac/data_mover.v /^ input [DATA_WIDTH-1:0] s_axi_data,$/;" p module:dmac_data_mover +s_axi_last adi_library/axi_dmac/data_mover.v /^ input s_axi_last,$/;" p module:dmac_data_mover +s_axi_rdata adi_library/axi_dmac/axi_dmac.v /^ output [31:0] s_axi_rdata,$/;" p module:axi_dmac +s_axi_rdata adi_library/axi_dmac/axi_dmac_regmap.v /^ output [31:0] s_axi_rdata,$/;" p module:axi_dmac_regmap +s_axi_rdata adi_library/axi_dmac/tb/regmap_tb.v /^ wire [31:0] s_axi_rdata;$/;" n module:dmac_regmap_tb +s_axi_rdata adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output [31:0] s_axi_rdata,$/;" p module:axi_spi_engine +s_axi_rdata adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [31:0] s_axi_rdata,$/;" p module:axi_adxcvr +s_axi_rdata adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output [31:0] s_axi_rdata,$/;" p module:axi_xcvrlb +s_axi_rdata hdl/phy_control.v /^ output [ 31:0] s_axi_rdata,$/;" p module:phy_control +s_axi_ready adi_library/axi_dmac/axi_register_slice.v /^ output s_axi_ready,$/;" p module:axi_register_slice +s_axi_ready adi_library/axi_dmac/data_mover.v /^ output s_axi_ready,$/;" p module:dmac_data_mover +s_axi_rready adi_library/axi_dmac/axi_dmac.v /^ input s_axi_rready,$/;" p module:axi_dmac +s_axi_rready adi_library/axi_dmac/axi_dmac_regmap.v /^ input s_axi_rready,$/;" p module:axi_dmac_regmap +s_axi_rready adi_library/axi_dmac/tb/regmap_tb.v /^ reg s_axi_rready = 'h0;$/;" r module:dmac_regmap_tb +s_axi_rready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input s_axi_rready,$/;" p module:axi_spi_engine +s_axi_rready adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input s_axi_rready,$/;" p module:axi_adxcvr +s_axi_rready adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input s_axi_rready);$/;" p module:axi_xcvrlb +s_axi_rready hdl/phy_control.v /^ input s_axi_rready, (* X_INTERFACE_INFO = "xilinx.com:interface:axi/;" p module:phy_control +s_axi_rresp adi_library/axi_dmac/axi_dmac.v /^ output [ 1:0] s_axi_rresp,$/;" p module:axi_dmac +s_axi_rresp adi_library/axi_dmac/axi_dmac_regmap.v /^ output [1:0] s_axi_rresp,$/;" p module:axi_dmac_regmap +s_axi_rresp adi_library/axi_dmac/tb/regmap_tb.v /^ wire [1:0] s_axi_rresp;$/;" n module:dmac_regmap_tb +s_axi_rresp adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output [ 1:0] s_axi_rresp,$/;" p module:axi_spi_engine +s_axi_rresp adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] s_axi_rresp,$/;" p module:axi_adxcvr +s_axi_rresp adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output [ 1:0] s_axi_rresp,$/;" p module:axi_xcvrlb +s_axi_rresp hdl/phy_control.v /^ output [ 1:0] s_axi_rresp, (* X_INTERFACE_INFO = "xilinx.com:interface:axim/;" p module:phy_control +s_axi_rvalid adi_library/axi_dmac/axi_dmac.v /^ output s_axi_rvalid,$/;" p module:axi_dmac +s_axi_rvalid adi_library/axi_dmac/axi_dmac_regmap.v /^ output s_axi_rvalid,$/;" p module:axi_dmac_regmap +s_axi_rvalid adi_library/axi_dmac/tb/regmap_tb.v /^ wire s_axi_rvalid;$/;" n module:dmac_regmap_tb +s_axi_rvalid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output s_axi_rvalid,$/;" p module:axi_spi_engine +s_axi_rvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output s_axi_rvalid,$/;" p module:axi_adxcvr +s_axi_rvalid adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output s_axi_rvalid,$/;" p module:axi_xcvrlb +s_axi_rvalid hdl/phy_control.v /^ output s_axi_rvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:axi/;" p module:phy_control +s_axi_sync adi_library/axi_dmac/data_mover.v /^ input s_axi_sync,$/;" p module:dmac_data_mover +s_axi_sync_valid adi_library/axi_dmac/data_mover.v /^wire s_axi_sync_valid = has_sync & s_axi_valid;$/;" n module:dmac_data_mover +s_axi_valid adi_library/axi_dmac/axi_register_slice.v /^ input s_axi_valid,$/;" p module:axi_register_slice +s_axi_valid adi_library/axi_dmac/data_mover.v /^ input s_axi_valid,$/;" p module:dmac_data_mover +s_axi_wdata adi_library/axi_dmac/axi_dmac.v /^ input [31:0] s_axi_wdata,$/;" p module:axi_dmac +s_axi_wdata adi_library/axi_dmac/axi_dmac_regmap.v /^ input [31:0] s_axi_wdata,$/;" p module:axi_dmac_regmap +s_axi_wdata adi_library/axi_dmac/tb/regmap_tb.v /^ reg [31:0] s_axi_wdata = 'h00;$/;" r module:dmac_regmap_tb +s_axi_wdata adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [31:0] s_axi_wdata,$/;" p module:axi_spi_engine +s_axi_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [31:0] s_axi_wdata,$/;" p module:axi_adxcvr +s_axi_wdata adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input [31:0] s_axi_wdata,$/;" p module:axi_xcvrlb +s_axi_wdata hdl/phy_control.v /^ input [ 31:0] s_axi_wdata, (* X_INTERFACE_INFO = "xilinx.com:interface:axim/;" p module:phy_control +s_axi_wready adi_library/axi_dmac/axi_dmac.v /^ output s_axi_wready,$/;" p module:axi_dmac +s_axi_wready adi_library/axi_dmac/axi_dmac_regmap.v /^ output s_axi_wready,$/;" p module:axi_dmac_regmap +s_axi_wready adi_library/axi_dmac/tb/regmap_tb.v /^ wire s_axi_wready;$/;" n module:dmac_regmap_tb +s_axi_wready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output s_axi_wready,$/;" p module:axi_spi_engine +s_axi_wready adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output s_axi_wready,$/;" p module:axi_adxcvr +s_axi_wready adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output s_axi_wready,$/;" p module:axi_xcvrlb +s_axi_wready hdl/phy_control.v /^ output s_axi_wready, (* X_INTERFACE_INFO = "xilinx.com:interface:axi/;" p module:phy_control +s_axi_wstrb adi_library/axi_dmac/axi_dmac.v /^ input [ 3:0] s_axi_wstrb,$/;" p module:axi_dmac +s_axi_wstrb adi_library/axi_dmac/axi_dmac_regmap.v /^ input [3:0] s_axi_wstrb,$/;" p module:axi_dmac_regmap +s_axi_wstrb adi_library/axi_dmac/tb/regmap_tb.v /^ wire [3:0] s_axi_wstrb = 4'b1111;$/;" n module:dmac_regmap_tb +s_axi_wstrb adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [ 3:0] s_axi_wstrb,$/;" p module:axi_spi_engine +s_axi_wstrb adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [ 3:0] s_axi_wstrb,$/;" p module:axi_adxcvr +s_axi_wstrb adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input [ 3:0] s_axi_wstrb,$/;" p module:axi_xcvrlb +s_axi_wstrb hdl/phy_control.v /^ input [ 3:0] s_axi_wstrb, (* X_INTERFACE_INFO = "xilinx.com:interface:axim/;" p module:phy_control +s_axi_wvalid adi_library/axi_dmac/axi_dmac.v /^ input s_axi_wvalid,$/;" p module:axi_dmac +s_axi_wvalid adi_library/axi_dmac/axi_dmac_regmap.v /^ input s_axi_wvalid,$/;" p module:axi_dmac_regmap +s_axi_wvalid adi_library/axi_dmac/tb/regmap_tb.v /^ reg s_axi_wvalid = 1'b0;$/;" r module:dmac_regmap_tb +s_axi_wvalid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input s_axi_wvalid,$/;" p module:axi_spi_engine +s_axi_wvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input s_axi_wvalid,$/;" p module:axi_adxcvr +s_axi_wvalid adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ input s_axi_wvalid,$/;" p module:axi_xcvrlb +s_axi_wvalid hdl/phy_control.v /^ input s_axi_wvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:axi/;" p module:phy_control +s_axis_aclk adi_library/axi_dmac/axi_dmac.v /^ input s_axis_aclk,$/;" p module:axi_dmac +s_axis_aclk adi_library/axi_dmac/axi_dmac_transfer.v /^ input s_axis_aclk,$/;" p module:axi_dmac_transfer +s_axis_aclk adi_library/axi_dmac/dest_axi_stream.v /^ input s_axis_aclk,$/;" p module:dmac_dest_axi_stream +s_axis_aclk adi_library/axi_dmac/request_arb.v /^ input s_axis_aclk,$/;" p module:dmac_request_arb +s_axis_aclk adi_library/axi_dmac/src_axi_stream.v /^ input s_axis_aclk,$/;" p module:dmac_src_axi_stream +s_axis_aclk adi_library/util_axis_fifo/address_gray.v /^ input s_axis_aclk,$/;" p module:fifo_address_gray +s_axis_aclk adi_library/util_axis_fifo/address_gray_pipelined.v /^ input s_axis_aclk,$/;" p module:fifo_address_gray_pipelined +s_axis_aclk adi_library/util_axis_fifo/util_axis_fifo.v /^ input s_axis_aclk,$/;" p module:util_axis_fifo +s_axis_aresetn adi_library/axi_dmac/dest_axi_stream.v /^ input s_axis_aresetn,$/;" p module:dmac_dest_axi_stream +s_axis_aresetn adi_library/axi_dmac/src_axi_stream.v /^ input s_axis_aresetn,$/;" p module:dmac_src_axi_stream +s_axis_aresetn adi_library/util_axis_fifo/address_gray.v /^ input s_axis_aresetn,$/;" p module:fifo_address_gray +s_axis_aresetn adi_library/util_axis_fifo/address_gray_pipelined.v /^ input s_axis_aresetn,$/;" p module:fifo_address_gray_pipelined +s_axis_aresetn adi_library/util_axis_fifo/util_axis_fifo.v /^ input s_axis_aresetn,$/;" p module:util_axis_fifo +s_axis_data adi_library/axi_dmac/axi_dmac.v /^ input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,$/;" p module:axi_dmac +s_axis_data adi_library/axi_dmac/axi_dmac_transfer.v /^ input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,$/;" p module:axi_dmac_transfer +s_axis_data adi_library/axi_dmac/request_arb.v /^ input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,$/;" p module:dmac_request_arb +s_axis_data adi_library/axi_dmac/src_axi_stream.v /^ input [S_AXIS_DATA_WIDTH-1:0] s_axis_data,$/;" p module:dmac_src_axi_stream +s_axis_data adi_library/common/util_axis_upscale.v /^ input [(NUM_OF_CHANNELS*DATA_WIDTH)-1:0] s_axis_data,$/;" p module:util_axis_upscale +s_axis_data adi_library/util_axis_fifo/util_axis_fifo.v /^ input [DATA_WIDTH-1:0] s_axis_data,$/;" p module:util_axis_fifo +s_axis_data adi_library/util_pack/tb/underflow_tb.v /^ reg [NUM_OF_PORTS*8-1:0] s_axis_data = {NUM_OF_PORTS*8{1'b1}};$/;" r module:upack2_underflow_tb +s_axis_data adi_library/util_pack/tb/upack_tb.v /^ reg [NUM_OF_PORTS*8-1:0] s_axis_data = 'h00;$/;" r module:upack_tb +s_axis_data adi_library/util_pack/util_upack2/util_upack2.v /^ input [2**$clog2(NUM_OF_CHANNELS)*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] s_axis_data$/;" p module:util_upack2 +s_axis_data adi_library/util_pack/util_upack2/util_upack2_impl.v /^ input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] s_axis_data$/;" p module:util_upack2_impl +s_axis_data_tdata adi_library/util_fir_dec/util_fir_dec.v /^ wire [31:0] s_axis_data_tdata;$/;" n module:util_fir_dec +s_axis_data_tdata adi_library/util_fir_int/util_fir_int.v /^ input [31:0] s_axis_data_tdata,$/;" p module:util_fir_int +s_axis_data_tready adi_library/util_fir_dec/util_fir_dec.v /^ output s_axis_data_tready,$/;" p module:util_fir_dec +s_axis_data_tready adi_library/util_fir_int/util_fir_int.v /^ output s_axis_data_tready,$/;" p module:util_fir_int +s_axis_data_tready_i hdl/MF_Top.v /^ wire s_axis_data_tready_i;$/;" n module:MF_Top +s_axis_data_tready_q hdl/MF_Top.v /^ wire s_axis_data_tready_q;$/;" n module:MF_Top +s_axis_data_tready_r adi_library/util_fir_int/util_fir_int.v /^ reg s_axis_data_tready_r;$/;" r module:util_fir_int +s_axis_data_tvalid adi_library/util_fir_dec/util_fir_dec.v /^ input s_axis_data_tvalid,$/;" p module:util_fir_dec +s_axis_data_tvalid adi_library/util_fir_int/util_fir_int.v /^ input s_axis_data_tvalid,$/;" p module:util_fir_int +s_axis_data_tvalid_i hdl/MF_Top.v /^ wire s_axis_data_tvalid_i;$/;" n module:MF_Top +s_axis_data_tvalid_q hdl/MF_Top.v /^ wire s_axis_data_tvalid_q;$/;" n module:MF_Top +s_axis_data_tvalid_r adi_library/util_fir_int/util_fir_int.v /^ reg s_axis_data_tvalid_r;$/;" r module:util_fir_int +s_axis_data_tvalid_s adi_library/util_fir_int/util_fir_int.v /^ wire s_axis_data_tvalid_s;$/;" n module:util_fir_int +s_axis_dest adi_library/axi_dmac/axi_dmac.v /^ input [DMA_AXIS_DEST_W-1:0] s_axis_dest,$/;" p module:axi_dmac +s_axis_empty adi_library/util_axis_fifo/address_gray.v /^ output reg s_axis_empty,$/;" p module:fifo_address_gray +s_axis_empty adi_library/util_axis_fifo/address_gray_pipelined.v /^ output reg s_axis_empty,$/;" p module:fifo_address_gray_pipelined +s_axis_empty adi_library/util_axis_fifo/address_sync.v /^ output reg s_axis_empty,$/;" p module:fifo_address_sync +s_axis_empty adi_library/util_axis_fifo/util_axis_fifo.v /^ output s_axis_empty,$/;" p module:util_axis_fifo +s_axis_fifo_tdata hdl/enc_control.v /^ input [INPUT_DATA_WIDTH - 1:0] s_axis_fifo_tdata,$/;" p module:enc_control +s_axis_fifo_tdata sim/tb_enc_control.v /^ reg [31:0] s_axis_fifo_tdata;$/;" r module:tb_enc_control +s_axis_fifo_tready hdl/enc_control.v /^ output reg s_axis_fifo_tready,$/;" p module:enc_control +s_axis_fifo_tready sim/tb_enc_control.v /^ wire s_axis_fifo_tready;$/;" n module:tb_enc_control +s_axis_fifo_tvalid hdl/enc_control.v /^ input s_axis_fifo_tvalid,$/;" p module:enc_control +s_axis_fifo_tvalid sim/tb_enc_control.v /^ reg s_axis_fifo_tvalid = 1'b0;$/;" r module:tb_enc_control +s_axis_id adi_library/axi_dmac/axi_dmac.v /^ input [DMA_AXIS_ID_W-1:0] s_axis_id,$/;" p module:axi_dmac +s_axis_keep adi_library/axi_dmac/axi_dmac.v /^ input [DMA_DATA_WIDTH_SRC\/8-1:0] s_axis_keep,$/;" p module:axi_dmac +s_axis_last adi_library/axi_dmac/axi_dmac.v /^ input s_axis_last,$/;" p module:axi_dmac +s_axis_last adi_library/axi_dmac/axi_dmac_transfer.v /^ input s_axis_last,$/;" p module:axi_dmac_transfer +s_axis_last adi_library/axi_dmac/request_arb.v /^ input s_axis_last,$/;" p module:dmac_request_arb +s_axis_last adi_library/axi_dmac/src_axi_stream.v /^ input s_axis_last,$/;" p module:dmac_src_axi_stream +s_axis_raddr adi_library/util_axis_fifo/util_axis_fifo.v /^ wire s_axis_raddr;$/;" n module:util_axis_fifo +s_axis_raddr_gray adi_library/util_axis_fifo/address_gray.v /^wire [ADDRESS_WIDTH:0] s_axis_raddr_gray;$/;" n module:fifo_address_gray +s_axis_ready adi_library/axi_dmac/axi_dmac.v /^ output s_axis_ready,$/;" p module:axi_dmac +s_axis_ready adi_library/axi_dmac/axi_dmac_transfer.v /^ output s_axis_ready,$/;" p module:axi_dmac_transfer +s_axis_ready adi_library/axi_dmac/request_arb.v /^ output s_axis_ready,$/;" p module:dmac_request_arb +s_axis_ready adi_library/axi_dmac/src_axi_stream.v /^ output s_axis_ready,$/;" p module:dmac_src_axi_stream +s_axis_ready adi_library/common/util_axis_upscale.v /^ output reg s_axis_ready,$/;" p module:util_axis_upscale +s_axis_ready adi_library/util_axis_fifo/address_gray.v /^ output reg s_axis_ready,$/;" p module:fifo_address_gray +s_axis_ready adi_library/util_axis_fifo/address_gray_pipelined.v /^ output reg s_axis_ready,$/;" p module:fifo_address_gray_pipelined +s_axis_ready adi_library/util_axis_fifo/address_sync.v /^ output reg s_axis_ready,$/;" p module:fifo_address_sync +s_axis_ready adi_library/util_axis_fifo/util_axis_fifo.v /^ output s_axis_ready,$/;" p module:util_axis_fifo +s_axis_ready adi_library/util_pack/tb/underflow_tb.v /^ wire s_axis_ready;$/;" n module:upack2_underflow_tb +s_axis_ready adi_library/util_pack/tb/upack_tb.v /^ wire s_axis_ready;$/;" n module:upack_tb +s_axis_ready adi_library/util_pack/util_upack2/util_upack2.v /^ output s_axis_ready,$/;" p module:util_upack2 +s_axis_ready adi_library/util_pack/util_upack2/util_upack2_impl.v /^ output s_axis_ready,$/;" p module:util_upack2_impl +s_axis_room adi_library/util_axis_fifo/address_gray.v /^ output reg [ADDRESS_WIDTH:0] s_axis_room$/;" p module:fifo_address_gray +s_axis_room adi_library/util_axis_fifo/address_gray_pipelined.v /^ output reg [ADDRESS_WIDTH:0] s_axis_room$/;" p module:fifo_address_gray_pipelined +s_axis_room adi_library/util_axis_fifo/address_sync.v /^ output [ADDRESS_WIDTH:0] s_axis_room$/;" p module:fifo_address_sync +s_axis_room adi_library/util_axis_fifo/util_axis_fifo.v /^ output [ADDRESS_WIDTH:0] s_axis_room$/;" p module:util_axis_fifo +s_axis_strb adi_library/axi_dmac/axi_dmac.v /^ input [DMA_DATA_WIDTH_SRC\/8-1:0] s_axis_strb,$/;" p module:axi_dmac +s_axis_user adi_library/axi_dmac/axi_dmac.v /^ input [0:0] s_axis_user,$/;" p module:axi_dmac +s_axis_user adi_library/axi_dmac/axi_dmac_transfer.v /^ input [0:0] s_axis_user,$/;" p module:axi_dmac_transfer +s_axis_user adi_library/axi_dmac/request_arb.v /^ input [0:0] s_axis_user,$/;" p module:dmac_request_arb +s_axis_user adi_library/axi_dmac/src_axi_stream.v /^ input [0:0] s_axis_user,$/;" p module:dmac_src_axi_stream +s_axis_valid adi_library/axi_dmac/axi_dmac.v /^ input s_axis_valid,$/;" p module:axi_dmac +s_axis_valid adi_library/axi_dmac/axi_dmac_transfer.v /^ input s_axis_valid,$/;" p module:axi_dmac_transfer +s_axis_valid adi_library/axi_dmac/request_arb.v /^ input s_axis_valid,$/;" p module:dmac_request_arb +s_axis_valid adi_library/axi_dmac/src_axi_stream.v /^ input s_axis_valid,$/;" p module:dmac_src_axi_stream +s_axis_valid adi_library/common/util_axis_upscale.v /^ input s_axis_valid,$/;" p module:util_axis_upscale +s_axis_valid adi_library/util_axis_fifo/address_gray.v /^ input s_axis_valid,$/;" p module:fifo_address_gray +s_axis_valid adi_library/util_axis_fifo/address_gray_pipelined.v /^ input s_axis_valid,$/;" p module:fifo_address_gray_pipelined +s_axis_valid adi_library/util_axis_fifo/address_sync.v /^ input s_axis_valid,$/;" p module:fifo_address_sync +s_axis_valid adi_library/util_axis_fifo/util_axis_fifo.v /^ input s_axis_valid,$/;" p module:util_axis_fifo +s_axis_valid adi_library/util_pack/tb/underflow_tb.v /^ reg s_axis_valid = 1'b1;$/;" r module:upack2_underflow_tb +s_axis_valid adi_library/util_pack/tb/upack_tb.v /^ reg s_axis_valid = 1'b1;$/;" r module:upack_tb +s_axis_valid adi_library/util_pack/util_upack2/util_upack2.v /^ input s_axis_valid,$/;" p module:util_upack2 +s_axis_valid adi_library/util_pack/util_upack2/util_upack2_impl.v /^ input s_axis_valid,$/;" p module:util_upack2_impl +s_axis_waddr adi_library/util_axis_fifo/address_gray.v /^ output [ADDRESS_WIDTH-1:0] s_axis_waddr,$/;" p module:fifo_address_gray +s_axis_waddr adi_library/util_axis_fifo/address_gray_pipelined.v /^ output [ADDRESS_WIDTH-1:0] s_axis_waddr,$/;" p module:fifo_address_gray_pipelined +s_axis_waddr adi_library/util_axis_fifo/address_sync.v /^ output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,$/;" p module:fifo_address_sync +s_axis_waddr adi_library/util_axis_fifo/util_axis_fifo.v /^ reg s_axis_waddr = 1'b0;$/;" r module:util_axis_fifo +s_axis_waddr adi_library/util_axis_fifo/util_axis_fifo.v /^ wire [ADDRESS_WIDTH-1:0] s_axis_waddr;$/;" n module:util_axis_fifo +s_axis_waddr_gray adi_library/util_axis_fifo/address_gray.v /^reg [ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00;$/;" r module:fifo_address_gray +s_axis_waddr_gray_next adi_library/util_axis_fifo/address_gray.v /^wire [ADDRESS_WIDTH:0] s_axis_waddr_gray_next;$/;" n module:fifo_address_gray +s_axis_xfer_req adi_library/axi_dmac/axi_dmac.v /^ output s_axis_xfer_req,$/;" p module:axi_dmac +s_axis_xfer_req adi_library/axi_dmac/axi_dmac_transfer.v /^ output s_axis_xfer_req,$/;" p module:axi_dmac_transfer +s_axis_xfer_req adi_library/axi_dmac/request_arb.v /^ output s_axis_xfer_req,$/;" p module:dmac_request_arb +s_axis_xfer_req adi_library/axi_dmac/src_axi_stream.v /^ output s_axis_xfer_req,$/;" p module:dmac_src_axi_stream +s_cs adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ input [NUM_OF_CS-1:0] s_cs,$/;" p module:util_sigma_delta_spi +s_data adi_library/util_axis_resize/util_axis_resize.v /^ input [SLAVE_DATA_WIDTH-1:0] s_data,$/;" p module:util_axis_resize +s_data_1 adi_library/common/ad_csc.v /^ reg signed [ MUL_DW:0] s_data_1;$/;" r module:ad_csc +s_data_2 adi_library/common/ad_csc.v /^ reg signed [ MUL_DW:0] s_data_2;$/;" r module:ad_csc +s_data_3 adi_library/common/ad_csc.v /^ reg signed [ MUL_DW:0] s_data_3;$/;" r module:ad_csc +s_mem_write adi_library/util_axis_fifo/util_axis_fifo.v /^ wire s_mem_write;$/;" n module:util_axis_fifo +s_ready adi_library/axi_dmac/splitter.v /^ output s_ready,$/;" p module:splitter +s_ready adi_library/util_axis_resize/util_axis_resize.v /^ output s_ready,$/;" p module:util_axis_resize +s_sclk adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ input s_sclk,$/;" p module:util_sigma_delta_spi +s_sdi adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ output s_sdi,$/;" p module:util_sigma_delta_spi +s_sdo adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ input s_sdo,$/;" p module:util_sigma_delta_spi +s_sdo_t adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ input s_sdo_t,$/;" p module:util_sigma_delta_spi +s_valid adi_library/axi_dmac/splitter.v /^ input s_valid,$/;" p module:splitter +s_valid adi_library/util_axis_resize/util_axis_resize.v /^ input s_valid,$/;" p module:util_axis_resize +samples_enable adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [NUM_OF_SAMPLES-1:0] samples_enable;$/;" n module:pack_shell +scale adi_library/common/ad_dds_1.v /^ input [ 15:0] scale,$/;" p module:ad_dds_1 +sclk adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg sclk,$/;" p module:spi_engine_execution +sclk_int adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg sclk_int = 1'b0;$/;" r module:spi_engine_execution +scramblestart hdl/FrameMerge.v /^ wire scramblestart;$/;" n module:FrameMerge +sdi adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input [NUM_OF_SDI-1:0] sdi,$/;" p module:spi_engine_execution +sdi_counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [7:0] sdi_counter = 8'b0;$/;" r module:spi_engine_execution +sdi_d adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^reg [2:0] sdi_d = 'h00;$/;" r module:util_sigma_delta_spi +sdi_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,$/;" p module:axi_spi_engine +sdi_data adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,$/;" p module:spi_engine_execution +sdi_data adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,$/;" p module:spi_engine_offload +sdi_data_ready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output sdi_data_ready,$/;" p module:axi_spi_engine +sdi_data_ready adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input sdi_data_ready,$/;" p module:spi_engine_execution +sdi_data_ready adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output sdi_data_ready,$/;" p module:spi_engine_offload +sdi_data_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input sdi_data_valid,$/;" p module:axi_spi_engine +sdi_data_valid adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg sdi_data_valid,$/;" p module:spi_engine_execution +sdi_data_valid adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input sdi_data_valid,$/;" p module:spi_engine_offload +sdi_enabled adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg sdi_enabled = 1'b0;$/;" r module:spi_engine_execution +sdi_fifo_almost_full adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire sdi_fifo_almost_full;$/;" n module:axi_spi_engine +sdi_fifo_level adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;$/;" n module:axi_spi_engine +sdi_fifo_out_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;$/;" n module:axi_spi_engine +sdi_fifo_out_data_msb_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire sdi_fifo_out_data_msb_s;$/;" n module:axi_spi_engine +sdi_fifo_out_ready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire sdi_fifo_out_ready;$/;" n module:axi_spi_engine +sdi_fifo_out_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire sdi_fifo_out_valid;$/;" n module:axi_spi_engine +sdo adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg sdo,$/;" p module:spi_engine_execution +sdo_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output [(DATA_WIDTH-1):0] sdo_data,$/;" p module:axi_spi_engine +sdo_data adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input [(DATA_WIDTH-1):0] sdo_data,$/;" p module:spi_engine_execution +sdo_data adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output [(DATA_WIDTH-1):0] sdo_data,$/;" p module:spi_engine_offload +sdo_data_ready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input sdo_data_ready,$/;" p module:axi_spi_engine +sdo_data_ready adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg sdo_data_ready,$/;" p module:spi_engine_execution +sdo_data_ready adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input sdo_data_ready,$/;" p module:spi_engine_offload +sdo_data_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output sdo_data_valid,$/;" p module:axi_spi_engine +sdo_data_valid adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input sdo_data_valid,$/;" p module:spi_engine_execution +sdo_data_valid adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output sdo_data_valid,$/;" p module:spi_engine_offload +sdo_enabled adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg sdo_enabled = 1'b0;$/;" r module:spi_engine_execution +sdo_fifo_almost_empty adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire sdo_fifo_almost_empty;$/;" n module:axi_spi_engine +sdo_fifo_in_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;$/;" n module:axi_spi_engine +sdo_fifo_in_ready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire sdo_fifo_in_ready;$/;" n module:axi_spi_engine +sdo_fifo_in_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire sdo_fifo_in_valid;$/;" n module:axi_spi_engine +sdo_fifo_room adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room;$/;" n module:axi_spi_engine +sdo_int_s adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire sdo_int_s;$/;" n module:spi_engine_execution +sdo_mem adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];$/;" r module:spi_engine_offload +sdo_t adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg sdo_t,$/;" p module:spi_engine_execution +sdo_t_int adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg sdo_t_int = 1'b0;$/;" r module:spi_engine_execution +sel adi_library/util_pack/util_pack_common/pack_interconnect.v /^ wire [MUX_ORDER-1:0] sel = ctrl[ctrl_base+:MUX_ORDER];\/\/ + j % z;$/;" n block:pack_interconnect.gen_stages.gen_ports +sel_base adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam sel_base = j & ~(z-1); \/* base increments in 2**MUX_ORDER steps *\/$/;" c block:pack_interconnect.gen_stages.gen_ports +select_path adi_library/common/ad_bus_mux.v /^ input select_path,$/;" p module:ad_bus_mux +send_data_ready hdl/Transmitter.v /^ input wire send_data_ready,$/;" p module:Transmitter +send_over hdl/Transmitter.v /^ output reg send_over,$/;" p module:Transmitter +send_start hdl/Transmitter.v /^ input wire send_start,$/;" p module:Transmitter +serdes_shift1_s adi_library/xilinx/common/ad_serdes_out.v /^ wire [(DATA_WIDTH-1):0] serdes_shift1_s;$/;" n module:ad_serdes_out +serdes_shift2_s adi_library/xilinx/common/ad_serdes_out.v /^ wire [(DATA_WIDTH-1):0] serdes_shift2_s;$/;" n module:ad_serdes_out +set_reset_reg_value adi_library/axi_dmac/tb/regmap_tb.v /^ task set_reset_reg_value;$/;" t module:dmac_regmap_tb +sgn_shift_x adi_library/common/ad_dds_cordic_pipe.v /^ wire [ D_DW-1:0] sgn_shift_x;$/;" n module:ad_dds_cordic_pipe +sgn_shift_y adi_library/common/ad_dds_cordic_pipe.v /^ wire [ D_DW-1:0] sgn_shift_y;$/;" n module:ad_dds_cordic_pipe +shift_each_reg hdl/shift_reg.v /^ for (shift_reg_cnt = 0; shift_reg_cnt < DEPTH; shift_reg_cnt = shift_reg_cnt + 1) be/;" b module:shift_reg +shift_out hdl/add_prefix.v /^ wire [ WIDTH-1:0] shift_out;$/;" n module:add_prefix +shift_r adi_library/util_cic/cic_comb.v /^ for (i = L; i <= H; i = i + 1) begin: shift_r$/;" b module:cic_comb +shift_reg hdl/shift_reg.v /^module shift_reg #($/;" m +shift_reg_cnt hdl/shift_reg.v /^ genvar shift_reg_cnt;$/;" r module:shift_reg +shift_register hdl/shift_reg.v /^ reg [DATA_WIDTH-1:0] shift_register;$/;" r module:shift_reg +shift_register hdl/shift_reg.v /^ reg [DATA_WIDTH-1:0] shift_register[DEPTH-1:0];$/;" r module:shift_reg +shiftram_freq_01 hdl/freqestm.v /^ shiftram_freq shiftram_freq_01 ($/;" i module:freqestm typeref:module:shiftram_freq +shiftram_freq_02 hdl/freqestm.v /^ shiftram_freq shiftram_freq_02 ($/;" i module:freqestm typeref:module:shiftram_freq +shuffle_in adi_library/util_pack/util_pack_common/pack_interconnect.v /^ wire [TOTAL_DATA_WIDTH-1:0] shuffle_in;$/;" n block:pack_interconnect.gen_stages +shuffle_inner adi_library/common/ad_perfect_shuffle.v /^ for (j = 0; j < WORDS_PER_GROUP; j = j + 1) begin: shuffle_inner$/;" b block:ad_perfect_shuffle.shuffle_outer +shuffle_out adi_library/util_pack/util_pack_common/pack_interconnect.v /^ wire [TOTAL_DATA_WIDTH-1:0] shuffle_out;$/;" n block:pack_interconnect.gen_stages +shuffle_outer adi_library/common/ad_perfect_shuffle.v /^ for (i = 0; i < NUM_GROUPS; i = i + 1) begin: shuffle_outer$/;" b module:ad_perfect_shuffle +sign_bit hdl/trunc_25to12_2dly.v /^ reg sign_bit = 0;$/;" r module:trunc_25to12_2dly +sign_bit_num_i hdl/power_measure.v /^ reg [ 3:0] sign_bit_num_i;$/;" r module:power_measure +sign_bit_num_min_i hdl/power_measure.v /^ reg [ 3:0] sign_bit_num_min_i;$/;" r module:power_measure +sign_bit_num_min_q hdl/power_measure.v /^ reg [ 3:0] sign_bit_num_min_q;$/;" r module:power_measure +sign_bit_num_q hdl/power_measure.v /^ reg [ 3:0] sign_bit_num_q;$/;" r module:power_measure +sign_s adi_library/common/ad_datafmt.v /^ wire sign_s;$/;" n module:ad_datafmt +sign_s adi_library/common/util_axis_upscale.v /^ wire sign_s;$/;" n block:util_axis_upscale.signext_data +signal_in adi_library/common/ad_edge_detect.v /^ input signal_in,$/;" p module:ad_edge_detect +signal_out adi_library/common/ad_edge_detect.v /^ output reg signal_out);$/;" p module:ad_edge_detect +signbit3 hdl/trunc_25to12_2dly.v /^ reg signbit3 = 0;$/;" r module:trunc_25to12_2dly +signext_data adi_library/common/util_axis_upscale.v /^ for (i=1; i <= NUM_OF_CHANNELS; i=i+1) begin : signext_data$/;" b module:util_axis_upscale +signext_s adi_library/common/ad_datafmt.v /^ wire signext_s;$/;" n module:ad_datafmt +signext_s adi_library/common/util_axis_upscale.v /^ wire signext_s;$/;" n module:util_axis_upscale +sin_addr hdl/DDS_compensate.v /^ reg [12:0] cos_addr = 0,sin_addr = -13'd2048;$/;" r module:DDS_compensate +sin_dout hdl/DDS_compensate.v /^ wire [11:0] cos_dout,sin_dout;$/;" n module:DDS_compensate +sine adi_library/common/ad_dds_sine.v /^ output [15:0] sine,$/;" p module:ad_dds_sine +sine adi_library/common/ad_dds_sine_cordic.v /^ output reg [CORDIC_DW-1:0] sine,$/;" p module:ad_dds_sine_cordic +sine_int adi_library/common/ad_dds_sine.v /^ reg [15:0] sine_int = 'd0;$/;" r module:ad_dds_sine +sine_s adi_library/common/ad_dds_1.v /^ wire [ DDS_D_DW-1:0] sine_s;$/;" n module:ad_dds_1 +size adi_library/axi_dmac/address_generator.v /^ output [ 2:0] size,$/;" p module:dmac_address_generator +size adi_library/axi_dmac/tb/axi_slave.v /^ input [2:0] size,$/;" p module:axi_slave +sleep_counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];$/;" n module:spi_engine_execution +sleep_counter_compare adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire sleep_counter_compare;$/;" n module:spi_engine_execution +sm2tc adi_library/common/up_adc_channel.v /^ function [15:0] sm2tc;$/;" f module:up_adc_channel +sm2tc adi_library/common/up_dac_channel.v /^ function [15:0] sm2tc;$/;" f module:up_dac_channel +source_eot adi_library/axi_dmac/data_mover.v /^ output source_eot,$/;" p module:dmac_data_mover +source_eot adi_library/axi_dmac/request_arb.v /^wire source_eot;$/;" n module:dmac_request_arb +source_eot adi_library/axi_dmac/src_axi_stream.v /^ output source_eot,$/;" p module:dmac_src_axi_stream +source_id adi_library/axi_dmac/data_mover.v /^ output [ID_WIDTH-1:0] source_id,$/;" p module:dmac_data_mover +source_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] source_id;$/;" n module:dmac_request_arb +source_id adi_library/axi_dmac/src_axi_stream.v /^ output [ID_WIDTH-1:0] source_id,$/;" p module:dmac_src_axi_stream +speed_mode hdl/Receiver.v /^ input [ 2:0] speed_mode,$/;" p module:Receiver +speed_mode hdl/Transmitter.v /^ input wire [ 2:0] speed_mode,$/;" p module:Transmitter +speed_mode hdl/system_top.v /^ wire [ 2:0] speed_mode;$/;" n module:system_top +speed_select adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ output reg [ 1:0] speed_select,$/;" p module:mdc_mdio +speed_selection adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ wire [ 1:0] speed_selection; \/\/ 1x gigabit, 01 100Mbps, 00 10mbps$/;" n module:util_gmii_to_rgmii +spi_active adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg spi_active = 1'b0;$/;" r module:spi_engine_offload +spi_active adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^ input spi_active,$/;" p module:util_sigma_delta_spi +spi_active hdl/ad9361_spi_interface.v /^ input spi_active$/;" p module:ad9361_spi_interface +spi_clk adi_library/common/ad_3w_spi.v /^ input spi_clk,$/;" p module:ad_3w_spi +spi_clk adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input spi_clk,$/;" p module:axi_spi_engine +spi_clk adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input spi_clk,$/;" p module:spi_engine_offload +spi_cmd_rd_addr adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'h00;$/;" r module:spi_engine_offload +spi_cmd_rd_addr_next adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;$/;" n module:spi_engine_offload +spi_count adi_library/common/ad_3w_spi.v /^ reg [ 5:0] spi_count = 'd0;$/;" r module:ad_3w_spi +spi_cs hdl/ad9361_spi_interface.v /^ input [1:0] spi_cs,$/;" p module:ad9361_spi_interface +spi_csn adi_library/common/ad_3w_spi.v /^ input [NUM_OF_SLAVES-1:0] spi_csn,$/;" p module:ad_3w_spi +spi_csn_s adi_library/common/ad_3w_spi.v /^ wire spi_csn_s;$/;" n module:ad_3w_spi +spi_dir adi_library/common/ad_3w_spi.v /^ output spi_dir);$/;" p module:ad_3w_spi +spi_enable adi_library/common/ad_3w_spi.v /^ reg spi_enable = 'd0;$/;" r module:ad_3w_spi +spi_enable adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^wire spi_enable;$/;" n module:spi_engine_offload +spi_enable_s adi_library/common/ad_3w_spi.v /^ wire spi_enable_s;$/;" n module:ad_3w_spi +spi_enabled adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg spi_enabled = 1'b0;$/;" r module:spi_engine_offload +spi_engine_execution adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^module spi_engine_execution #($/;" m +spi_engine_interconnect adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^module spi_engine_interconnect #($/;" m +spi_engine_interconnect_mux adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v /^`define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1))$/;" d module:spi_engine_interconnect +spi_engine_offload adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^module spi_engine_offload #($/;" m +spi_miso adi_library/common/ad_3w_spi.v /^ output spi_miso,$/;" p module:ad_3w_spi +spi_mosi adi_library/common/ad_3w_spi.v /^ input spi_mosi,$/;" p module:ad_3w_spi +spi_rd_wr_n adi_library/common/ad_3w_spi.v /^ reg spi_rd_wr_n = 'd0;$/;" r module:ad_3w_spi +spi_reset adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire spi_reset;$/;" n module:axi_spi_engine +spi_resetn adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output spi_resetn,$/;" p module:axi_spi_engine +spi_resetn adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input spi_resetn,$/;" p module:spi_engine_offload +spi_sclk hdl/ad9361_spi_interface.v /^ input spi_sclk,$/;" p module:ad9361_spi_interface +spi_sdi hdl/ad9361_spi_interface.v /^ output reg spi_sdi,$/;" p module:ad9361_spi_interface +spi_sdio adi_library/common/ad_3w_spi.v /^ inout spi_sdio,$/;" p module:ad_3w_spi +spi_sdo hdl/ad9361_spi_interface.v /^ input spi_sdo,$/;" p module:ad9361_spi_interface +spi_sdo_rd_addr adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00;$/;" r module:spi_engine_offload +spi_sdo_t hdl/ad9361_spi_interface.v /^ input spi_sdo_t,$/;" p module:ad9361_spi_interface +spi_sync_id_counter adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^reg [ 7:0] spi_sync_id_counter = 8'b0;$/;" r module:spi_engine_offload +spi_sync_id_init_s adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^wire [ 7:0] spi_sync_id_init_s;$/;" n module:spi_engine_offload +spi_sync_id_load_s adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^wire spi_sync_id_load_s;$/;" n module:spi_engine_offload +spi_three_wire hdl/ad9361_spi_interface.v /^ input spi_three_wire,$/;" p module:ad9361_spi_interface +split_data_0 adi_library/util_bsplit/util_bsplit.v /^ output [(CHANNEL_DATA_WIDTH-1):0] split_data_0,$/;" p module:util_bsplit +split_data_1 adi_library/util_bsplit/util_bsplit.v /^ output [(CHANNEL_DATA_WIDTH-1):0] split_data_1,$/;" p module:util_bsplit +split_data_2 adi_library/util_bsplit/util_bsplit.v /^ output [(CHANNEL_DATA_WIDTH-1):0] split_data_2,$/;" p module:util_bsplit +split_data_3 adi_library/util_bsplit/util_bsplit.v /^ output [(CHANNEL_DATA_WIDTH-1):0] split_data_3,$/;" p module:util_bsplit +split_data_4 adi_library/util_bsplit/util_bsplit.v /^ output [(CHANNEL_DATA_WIDTH-1):0] split_data_4,$/;" p module:util_bsplit +split_data_5 adi_library/util_bsplit/util_bsplit.v /^ output [(CHANNEL_DATA_WIDTH-1):0] split_data_5,$/;" p module:util_bsplit +split_data_6 adi_library/util_bsplit/util_bsplit.v /^ output [(CHANNEL_DATA_WIDTH-1):0] split_data_6,$/;" p module:util_bsplit +split_data_7 adi_library/util_bsplit/util_bsplit.v /^ output [(CHANNEL_DATA_WIDTH-1):0] split_data_7);$/;" p module:util_bsplit +splitter adi_library/axi_dmac/splitter.v /^module splitter #($/;" m +squ_abs_ZF hdl/Chn_Estimate.v /^wire [29:0] squ_abs_ZF;$/;" n module:Chn_Estimate +squ_abs_ZF1 hdl/Chn_Estimate.v /^squ_abs_ZF squ_abs_ZF1 ($/;" i module:Chn_Estimate typeref:module:squ_abs_ZF +squ_abs_ZF_nd hdl/Chn_Estimate.v /^reg squ_abs_ZF_nd = 1'd0;$/;" r module:Chn_Estimate +square2i hdl/phase_adjust.v /^ wire [11:0] square2i;$/;" n module:phase_adjust +square2q hdl/phase_adjust.v /^ wire [11:0] square2q;$/;" n module:phase_adjust +squarei hdl/phase_adjust.v /^ wire [10:0] squarei;$/;" n module:phase_adjust +squareq hdl/phase_adjust.v /^ wire [10:0] squareq;$/;" n module:phase_adjust +src_address adi_library/axi_dmac/2d_transfer.v /^reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_address = 'h00;$/;" r module:dmac_2d_transfer +src_address_eot adi_library/axi_dmac/request_arb.v /^wire src_address_eot = eot_mem_src[src_address_id];$/;" n module:dmac_request_arb +src_address_id adi_library/axi_dmac/axi_dmac.v /^wire [ID_WIDTH-1:0] src_address_id;$/;" n module:axi_dmac +src_address_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] src_address_id;$/;" n module:dmac_request_arb +src_beat adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire src_beat;$/;" n module:axi_dmac_burst_memory +src_beat_counter adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg [BURST_LEN_WIDTH_SRC-1:0] src_beat_counter = 'h00;$/;" r module:axi_dmac_burst_memory +src_bl_ready adi_library/axi_dmac/request_arb.v /^wire src_bl_ready;$/;" n module:dmac_request_arb +src_bl_valid adi_library/axi_dmac/request_arb.v /^wire src_bl_valid;$/;" n module:dmac_request_arb +src_burst_len_data adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [BYTES_PER_BURST_WIDTH+1-1:0] src_burst_len_data;$/;" n module:axi_dmac_burst_memory +src_burst_length adi_library/axi_dmac/request_arb.v /^wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_burst_length;$/;" n module:dmac_request_arb +src_clk adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input src_clk,$/;" p module:axi_dmac_burst_memory +src_clk adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input src_clk,$/;" p module:axi_dmac_reset_manager +src_clk adi_library/axi_dmac/axi_dmac_transfer.v /^wire src_clk;$/;" n module:axi_dmac_transfer +src_clk adi_library/axi_dmac/request_arb.v /^ output src_clk,$/;" p module:dmac_request_arb +src_data adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input [DATA_WIDTH_SRC-1:0] src_data,$/;" p module:axi_dmac_burst_memory +src_data adi_library/axi_dmac/axi_dmac_resize_src.v /^ input [DATA_WIDTH_SRC-1:0] src_data,$/;" p module:axi_dmac_resize_src +src_data adi_library/axi_dmac/request_arb.v /^wire [DMA_DATA_WIDTH_SRC-1:0] src_data;$/;" n module:dmac_request_arb +src_data_id adi_library/axi_dmac/axi_dmac.v /^wire [ID_WIDTH-1:0] src_data_id;$/;" n module:axi_dmac +src_data_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] src_data_id;$/;" n module:dmac_request_arb +src_data_last adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input src_data_last,$/;" p module:axi_dmac_burst_memory +src_data_last adi_library/axi_dmac/axi_dmac_resize_src.v /^ input src_data_last,$/;" p module:axi_dmac_resize_src +src_data_partial_burst adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input src_data_partial_burst,$/;" p module:axi_dmac_burst_memory +src_data_partial_burst adi_library/axi_dmac/axi_dmac_resize_src.v /^ input src_data_partial_burst,$/;" p module:axi_dmac_resize_src +src_data_request_id adi_library/axi_dmac/axi_dmac_burst_memory.v /^ output [ID_WIDTH-1:0] src_data_request_id,$/;" p module:axi_dmac_burst_memory +src_data_request_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] src_data_request_id;$/;" n module:dmac_request_arb +src_data_valid adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input src_data_valid,$/;" p module:axi_dmac_burst_memory +src_data_valid adi_library/axi_dmac/axi_dmac_resize_src.v /^ input src_data_valid,$/;" p module:axi_dmac_resize_src +src_data_valid_bytes adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_data_valid_bytes,$/;" p module:axi_dmac_burst_memory +src_data_valid_bytes adi_library/axi_dmac/axi_dmac_resize_src.v /^ input [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_data_valid_bytes,$/;" p module:axi_dmac_resize_src +src_dest_id adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [ID_WIDTH-1:0] src_dest_id;$/;" n module:axi_dmac_burst_memory +src_dest_ready adi_library/axi_dmac/request_arb.v /^wire src_dest_ready;$/;" n module:dmac_request_arb +src_dest_ready_hs adi_library/axi_dmac/request_arb.v /^wire src_dest_ready_hs;$/;" n module:dmac_request_arb +src_dest_valid adi_library/axi_dmac/request_arb.v /^wire src_dest_valid;$/;" n module:dmac_request_arb +src_dest_valid_hs adi_library/axi_dmac/request_arb.v /^reg src_dest_valid_hs = 1'b0;$/;" r module:dmac_request_arb +src_dest_valid_hs_masked adi_library/axi_dmac/request_arb.v /^wire src_dest_valid_hs_masked;$/;" n module:dmac_request_arb +src_enable adi_library/axi_dmac/axi_dmac_reset_manager.v /^ output src_enable,$/;" p module:axi_dmac_reset_manager +src_enable adi_library/axi_dmac/axi_dmac_transfer.v /^wire src_enable;$/;" n module:axi_dmac_transfer +src_enable adi_library/axi_dmac/request_arb.v /^ input src_enable,$/;" p module:dmac_request_arb +src_enable adi_library/axi_dmac/tb/reset_manager_tb.v /^ wire src_enable;$/;" n module:dmac_reset_manager_tb +src_enabled adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input src_enabled,$/;" p module:axi_dmac_reset_manager +src_enabled adi_library/axi_dmac/axi_dmac_transfer.v /^wire src_enabled;$/;" n module:axi_dmac_transfer +src_enabled adi_library/axi_dmac/request_arb.v /^ output src_enabled,$/;" p module:dmac_request_arb +src_enabled adi_library/axi_dmac/tb/reset_manager_tb.v /^ wire src_enabled = src_enabled_shift[15];$/;" n module:dmac_reset_manager_tb +src_enabled_shift adi_library/axi_dmac/tb/reset_manager_tb.v /^ reg [15:0] src_enabled_shift;$/;" r module:dmac_reset_manager_tb +src_eot adi_library/axi_dmac/request_arb.v /^wire src_eot = eot_mem_src[src_response_id];$/;" n module:dmac_request_arb +src_ext_resetn adi_library/axi_dmac/axi_dmac_reset_manager.v /^ input src_ext_resetn,$/;" p module:axi_dmac_reset_manager +src_ext_resetn adi_library/axi_dmac/axi_dmac_transfer.v /^wire src_ext_resetn;$/;" n module:axi_dmac_transfer +src_ext_resetn adi_library/axi_dmac/request_arb.v /^ output src_ext_resetn,$/;" p module:dmac_request_arb +src_fifo_data adi_library/axi_dmac/request_arb.v /^wire [DMA_DATA_WIDTH_SRC-1:0] src_fifo_data;$/;" n module:dmac_request_arb +src_fifo_last adi_library/axi_dmac/request_arb.v /^wire src_fifo_last;$/;" n module:dmac_request_arb +src_fifo_partial_burst adi_library/axi_dmac/request_arb.v /^wire src_fifo_partial_burst;$/;" n module:dmac_request_arb +src_fifo_valid adi_library/axi_dmac/request_arb.v /^wire src_fifo_valid;$/;" n module:dmac_request_arb +src_fifo_valid_bytes adi_library/axi_dmac/request_arb.v /^wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_fifo_valid_bytes;$/;" n module:dmac_request_arb +src_id adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg [ID_WIDTH-1:0] src_id = 'h0;$/;" r module:axi_dmac_burst_memory +src_id_next adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg [ID_WIDTH-1:0] src_id_next;$/;" r module:axi_dmac_burst_memory +src_id_reduced adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [ID_WIDTH-2:0] src_id_reduced;$/;" n module:axi_dmac_burst_memory +src_id_reduced_msb adi_library/axi_dmac/axi_dmac_burst_memory.v /^reg src_id_reduced_msb = 1'b0;$/;" r module:axi_dmac_burst_memory +src_last adi_library/axi_dmac/request_arb.v /^wire src_last;$/;" n module:dmac_request_arb +src_last_beat adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire src_last_beat;$/;" n module:axi_dmac_burst_memory +src_lsb adi_library/common/ad_perfect_shuffle.v /^ localparam src_lsb = (j + i * WORDS_PER_GROUP) * WORD_WIDTH;$/;" c block:ad_perfect_shuffle.shuffle_outer.shuffle_inner +src_mem_data adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [DATA_WIDTH_MEM_SRC-1:0] src_mem_data;$/;" n module:axi_dmac_burst_memory +src_mem_data_last adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire src_mem_data_last;$/;" n module:axi_dmac_burst_memory +src_mem_data_partial_burst adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire src_mem_data_partial_burst;$/;" n module:axi_dmac_burst_memory +src_mem_data_valid adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire src_mem_data_valid;$/;" n module:axi_dmac_burst_memory +src_mem_data_valid_bytes adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [BYTES_PER_BEAT_WIDTH_MEM_SRC-1:0] src_mem_data_valid_bytes;$/;" n module:axi_dmac_burst_memory +src_partial_burst adi_library/axi_dmac/request_arb.v /^wire src_partial_burst;$/;" n module:dmac_request_arb +src_req_dest_address adi_library/axi_dmac/request_arb.v /^wire [DMA_ADDRESS_WIDTH_DEST-1:0] src_req_dest_address;$/;" n module:dmac_request_arb +src_req_dest_address_cur adi_library/axi_dmac/request_arb.v /^reg [DMA_ADDRESS_WIDTH_DEST-1:0] src_req_dest_address_cur = 'h0;$/;" r module:dmac_request_arb +src_req_last_beat_bytes adi_library/axi_dmac/request_arb.v /^wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_req_last_beat_bytes;$/;" n module:dmac_request_arb +src_req_last_burst_length adi_library/axi_dmac/request_arb.v /^wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length;$/;" n module:dmac_request_arb +src_req_ready adi_library/axi_dmac/request_arb.v /^wire src_req_ready;$/;" n module:dmac_request_arb +src_req_src_address adi_library/axi_dmac/request_arb.v /^wire [DMA_ADDRESS_WIDTH_SRC-1:0] src_req_src_address;$/;" n module:dmac_request_arb +src_req_sync_transfer_start adi_library/axi_dmac/request_arb.v /^wire src_req_sync_transfer_start;$/;" n module:dmac_request_arb +src_req_valid adi_library/axi_dmac/request_arb.v /^wire src_req_valid;$/;" n module:dmac_request_arb +src_req_xlast adi_library/axi_dmac/request_arb.v /^wire src_req_xlast;$/;" n module:dmac_request_arb +src_req_xlast_cur adi_library/axi_dmac/request_arb.v /^reg src_req_xlast_cur = 1'b0;$/;" r module:dmac_request_arb +src_request_id adi_library/axi_dmac/axi_dmac.v /^wire [ID_WIDTH-1:0] src_request_id;$/;" n module:axi_dmac +src_request_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] src_request_id;$/;" n module:dmac_request_arb +src_reset adi_library/axi_dmac/axi_dmac_burst_memory.v /^ input src_reset,$/;" p module:axi_dmac_burst_memory +src_resetn adi_library/axi_dmac/axi_dmac_reset_manager.v /^ output src_resetn,$/;" p module:axi_dmac_reset_manager +src_resetn adi_library/axi_dmac/axi_dmac_transfer.v /^wire src_resetn;$/;" n module:axi_dmac_transfer +src_resetn adi_library/axi_dmac/request_arb.v /^ input src_resetn,$/;" p module:dmac_request_arb +src_response_id adi_library/axi_dmac/axi_dmac.v /^wire [ID_WIDTH-1:0] src_response_id;$/;" n module:axi_dmac +src_response_id adi_library/axi_dmac/request_arb.v /^wire [ID_WIDTH-1:0] src_response_id;$/;" n module:dmac_request_arb +src_stride adi_library/axi_dmac/2d_transfer.v /^reg [DMA_LENGTH_WIDTH-1:0] src_stride = 'h00;$/;" r module:dmac_2d_transfer +src_throttled_request_id adi_library/axi_dmac/request_arb.v /^reg [ID_WIDTH-1:0] src_throttled_request_id;$/;" r module:dmac_request_arb +src_throttler_enable adi_library/axi_dmac/request_arb.v /^wire src_throttler_enable;$/;" n module:dmac_request_arb +src_throttler_enabled adi_library/axi_dmac/request_arb.v /^reg src_throttler_enabled = 1'b1;$/;" r module:dmac_request_arb +src_valid adi_library/axi_dmac/request_arb.v /^wire src_valid;$/;" n module:dmac_request_arb +src_valid_bytes adi_library/axi_dmac/request_arb.v /^wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_valid_bytes;$/;" n module:dmac_request_arb +src_waddr adi_library/axi_dmac/axi_dmac_burst_memory.v /^wire [ADDRESS_WIDTH_SRC-1:0] src_waddr;$/;" n module:axi_dmac_burst_memory +start hdl/MF_Top.v /^ input start,$/;" p module:MF_Top +start hdl/ad9361_mgc_pin_ctrl.v /^ input start,$/;" p module:ad9361_mgc_pin_ctrl +start hdl/ad9361_mgc_pin_ctrl.v /^ wire start;$/;" n module:ad9361_mgc_pin_ctrl +start hdl/add_prefix.v /^ input start,$/;" p module:add_prefix +start hdl/power_measure.v /^ input start,$/;" p module:power_measure +start sim/tb_add_prefix.v /^ reg start;$/;" r module:tb_add_prefix +start_d1 hdl/ad9361_mgc_pin_ctrl.v /^ reg start_d1;$/;" r module:ad9361_mgc_pin_ctrl +start_posedge hdl/ad9361_mgc_pin_ctrl.v /^ wire start_posedge;$/;" n module:ad9361_mgc_pin_ctrl +startup hdl/Receiver.v /^ wire startup;$/;" n module:Receiver +startup_4x hdl/Receiver.v /^ wire startup_4x;$/;" n module:Receiver +startup_ctrl adi_library/util_pack/util_pack_common/pack_shell.v /^ reg startup_ctrl = 1'b0;$/;" r module:pack_shell +startup_ctrl2 adi_library/util_pack/util_pack_common/pack_shell.v /^ reg startup_ctrl2 = 1'b0;$/;" r module:pack_shell +state adi_library/axi_dmac/axi_dmac_reset_manager.v /^reg [2:0] state = 3'b000;$/;" r module:axi_dmac_reset_manager +state adi_library/axi_dmac/axi_dmac_response_manager.v /^reg [2:0] state = STATE_IDLE;$/;" r module:axi_dmac_response_manager +state adi_library/axi_dmac/request_generator.v /^reg [2:0] state = STATE_IDLE;$/;" r module:dmac_request_generator +state adi_library/util_cic/cic_comb.v /^reg [DATA_WIDTH-1:0] state = 'h00;$/;" r module:cic_comb +state adi_library/util_cic/cic_int.v /^reg [DATA_WIDTH-1:0] state = 'h00;$/;" r module:cic_int +state_8 hdl/FrameMerge.v /^ output reg state_8 = 1'd0,$/;" p module:FrameMerge +state_8 hdl/RecvTop.v /^ wire state_8;$/;" n module:RecvTop +state_agc hdl/DAGC_v2.v /^ reg [ 3:0] state_agc = 4'd0;$/;" r module:DAGC_v2 +state_fft hdl/SC_FDE_TOP.v /^ reg [1:0] state_fft = 2'd0;$/;" r module:SC_FDE_TOP +state_fftin hdl/data_equalizer.v /^ reg [3:0] state_fftin = 4'd0;$/;" r module:data_equalizer +state_fftout hdl/data_equalizer.v /^ reg [1:0] state_fftout = 2'd0;$/;" r module:data_equalizer +state_fifo hdl/freqestm.v /^ reg [ 2:0] state_fifo;$/;" r module:freqestm +state_flag_overflow1 hdl/Chn_Estimate.v /^reg [1:0] state_flag_overflow1 = 2'd0;$/;" r module:Chn_Estimate +state_framesync hdl/SCFDE_recv_FrameSync.v /^ reg [ 3:0] state_framesync;$/;" r module:SCFDE_recv_FrameSync +state_freq hdl/freqestm.v /^ reg [ 4:0] state_freq;$/;" r module:freqestm +state_ifft hdl/SC_FDE_TOP.v /^ reg [1:0] state_ifft = 2'd0;$/;" r module:SC_FDE_TOP +state_mgc hdl/RecvTop.v /^ output [ 4:0] state_mgc,$/;" p module:RecvTop +state_noise hdl/Noise_Estimate.v /^ reg state_noise = 1'd0;$/;" r module:Noise_Estimate +state_ow hdl/data_ow.v /^ reg [4:0] state_ow = 5'd0;$/;" r module:data_ow +state_phase hdl/phase_adjust.v /^ reg [3:0] state_phase;$/;" r module:phase_adjust +state_pilot hdl/data_ow.v /^ reg [2:0] state_pilot = 3'd0;$/;" r module:data_ow +state_pilot_div hdl/Chn_Estimate.v /^reg [4:0] state_pilot_div = 5'd0;$/;" r module:Chn_Estimate +state_pilot_fft hdl/Chn_Estimate.v /^reg [4:0] state_pilot_fft = 5'd0;$/;" r module:Chn_Estimate +state_pilot_ifft hdl/Chn_Estimate.v /^reg [1:0] state_pilot_ifft = 2'd0;$/;" r module:Chn_Estimate +state_ram hdl/FrameMerge.v /^ output reg [1:0] state_ram = 2'd0,$/;" p module:FrameMerge +state_ram hdl/RecvTop.v /^ wire [ 1:0] state_ram;$/;" n module:RecvTop +state_recv hdl/FrameMerge.v /^ reg [1:0] state_recv;$/;" r module:FrameMerge +state_rst hdl/RecvTop.v /^ output [ 2:0] state_rst,$/;" p module:RecvTop +state_storage hdl/DAGC_v2.v /^ reg [ 2:0] state_storage = 3'd0;$/;" r module:DAGC_v2 +state_tsync4 hdl/TSync_Abs_new16.v /^ reg [2:0] state_tsync4 = 3'd0;$/;" r module:TSync_Abs_new16 +state_tsync4 hdl/TSync_Abs_new4.v /^ reg [2:0] state_tsync4 = 3'd0;$/;" r module:TSync_Abs_new4 +status_sync_data adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output [7:0] status_sync_data,$/;" p module:spi_engine_offload +status_sync_ready adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input status_sync_ready,$/;" p module:spi_engine_offload +status_sync_valid adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output status_sync_valid,$/;" p module:spi_engine_offload +stop_temp_new hdl/FrameMerge.v /^ output reg [63:0] stop_temp_new = 64'd0,$/;" p module:FrameMerge +stop_temp_new hdl/RecvTop.v /^ wire [63:0] stop_temp_new;$/;" n module:RecvTop +storage adi_library/util_cic/cic_comb.v /^reg [SEQ-1:0] storage[0:DATA_WIDTH-1];$/;" r module:cic_comb +storage_out adi_library/util_cic/cic_comb.v /^wire [DATA_WIDTH-1:0] storage_out;$/;" n module:cic_comb +strb adi_library/axi_dmac/axi_dmac_resize_dest.v /^ reg [DATA_WIDTH_MEM\/8-1:0] strb = {DATA_WIDTH_MEM\/8{1'b1}};$/;" r module:axi_dmac_resize_dest +sum adi_library/util_cic/cic_int.v /^wire [DATA_WIDTH-1:0] sum;$/;" n module:cic_int +sum256i hdl/phase_adjust.v /^ reg [19:0] sum256i = 20'd0;$/;" r module:phase_adjust +sum256q hdl/phase_adjust.v /^ reg [19:0] sum256q = 20'd0; $/;" r module:phase_adjust +sum_i hdl/frame_sync.v /^ wire [17:0] sum_i [511:0];$/;" n module:frame_sync +sum_rdy hdl/phase_adjust.v /^ reg sum_rdy;$/;" r module:phase_adjust +sumquarter1 hdl/Interp_half.v /^ reg [14:0] sumquarter1 = 15'd0;$/;" r module:Interp_half +sumquarter1 hdl/Interp_quarter.v /^ reg [16:0] sumquarter1 = 17'd0;$/;" r module:Interp_quarter +sumquarter2 hdl/Interp_half.v /^ reg [14:0] sumquarter2 = 15'd0;$/;" r module:Interp_half +sumquarter2 hdl/Interp_quarter.v /^ reg [17:0] sumquarter2 = 18'd0;$/;" r module:Interp_quarter +sumquarter3 hdl/Interp_half.v /^ reg [15:0] sumquarter3 = 16'd0;$/;" r module:Interp_half +sumquarter3 hdl/Interp_quarter.v /^ reg [18:0] sumquarter3 = 19'd0;$/;" r module:Interp_quarter +sync adi_library/axi_dmac/src_fifo_inf.v /^ input sync,$/;" p module:dmac_src_fifo_inf +sync adi_library/common/ad_csc.v /^ input [ DELAY_DW-1:0] sync,$/;" p module:ad_csc +sync adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output [7:0] sync,$/;" p module:spi_engine_execution +sync adi_library/util_pack/util_pack_common/pack_shell.v /^ reg sync = 1'b1;$/;" r block:pack_shell.gen_pack.gen_output_buffer +sync hdl/FrameMerge.v /^ input sync,$/;" p module:FrameMerge +sync_1_m adi_library/common/ad_csc.v /^ reg [DELAY_DW-1:0] sync_1_m;$/;" r module:ad_csc +sync_2_m adi_library/common/ad_csc.v /^ reg [DELAY_DW-1:0] sync_2_m;$/;" r module:ad_csc +sync_3_m adi_library/common/ad_csc.v /^ reg [DELAY_DW-1:0] sync_3_m;$/;" r module:ad_csc +sync_4_m adi_library/common/ad_csc.v /^ reg [DELAY_DW-1:0] sync_4_m;$/;" r module:ad_csc +sync_5_m adi_library/common/ad_csc.v /^ reg [DELAY_DW-1:0] sync_5_m;$/;" r module:ad_csc +sync_bits adi_library/util_cdc/sync_bits.v /^module sync_bits #($/;" m +sync_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [7:0] sync_data,$/;" p module:axi_spi_engine +sync_data adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input [7:0] sync_data,$/;" p module:spi_engine_offload +sync_data adi_library/util_cdc/sync_data.v /^module sync_data #($/;" m +sync_delay adi_library/common/ad_dds.v /^ for (i=1; i < CLK_RATIO; i=i+1) begin: sync_delay$/;" b module:ad_dds +sync_event adi_library/util_cdc/sync_event.v /^module sync_event #($/;" m +sync_external adi_library/util_tdd_sync/util_tdd_sync.v /^ wire sync_external;$/;" n module:util_tdd_sync +sync_fifo_data adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [7:0] sync_fifo_data;$/;" n module:axi_spi_engine +sync_fifo_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire sync_fifo_valid;$/;" n module:axi_spi_engine +sync_gray adi_library/util_cdc/sync_gray.v /^module sync_gray #($/;" m +sync_id adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg [7:0] sync_id = 'h00;$/;" r module:axi_spi_engine +sync_id_pending adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg sync_id_pending = 1'b0;$/;" r module:axi_spi_engine +sync_in adi_library/util_tdd_sync/util_tdd_sync.v /^ input sync_in,$/;" p module:util_tdd_sync +sync_internal adi_library/util_tdd_sync/util_tdd_sync.v /^ wire sync_internal;$/;" n module:util_tdd_sync +sync_load adi_library/xilinx/common/ad_serdes_in.v /^ sync_event sync_load($/;" i block:ad_serdes_in.g_data typeref:module:sync_event +sync_min_pulse_m adi_library/common/ad_dds.v /^ reg sync_min_pulse_m[1:CLK_RATIO];$/;" r module:ad_dds +sync_mode adi_library/util_tdd_sync/util_tdd_sync.v /^ input sync_mode,$/;" p module:util_tdd_sync +sync_mode_d1 adi_library/util_tdd_sync/util_tdd_sync.v /^ reg sync_mode_d1 = 1'b0;$/;" r module:util_tdd_sync +sync_mode_d2 adi_library/util_tdd_sync/util_tdd_sync.v /^ reg sync_mode_d2 = 1'b0;$/;" r module:util_tdd_sync +sync_out adi_library/util_tdd_sync/util_tdd_sync.v /^ output reg sync_out);$/;" p module:util_tdd_sync +sync_ready adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output sync_ready,$/;" p module:axi_spi_engine +sync_ready adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input sync_ready,$/;" p module:spi_engine_execution +sync_ready adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output sync_ready,$/;" p module:spi_engine_offload +sync_rewind adi_library/axi_dmac/request_arb.v /^sync_event #(.ASYNC_CLK(ASYNC_CLK_REQ_SRC)) sync_rewind ($/;" i module:dmac_request_arb typeref:module:sync_event +sync_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input sync_valid,$/;" p module:axi_spi_engine +sync_valid adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg sync_valid,$/;" p module:spi_engine_execution +sync_valid adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input sync_valid,$/;" p module:spi_engine_offload +sys_clk_sel_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire [ 1:0] sys_clk_sel_0;$/;" n module:util_adxcvr +sys_clk_sel_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire [ 1:0] sys_clk_sel_12;$/;" n module:util_adxcvr +sys_clk_sel_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire [ 1:0] sys_clk_sel_4;$/;" n module:util_adxcvr +sys_clk_sel_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ wire [ 1:0] sys_clk_sel_8;$/;" n module:util_adxcvr +sys_cpu_clk adi_library/common/ad_adl5904_rst.v /^ input sys_cpu_clk,$/;" p module:ad_adl5904_rst +sysref_en adi_library/common/ad_sysref_gen.v /^ input sysref_en,$/;" p module:ad_sysref_gen +sysref_en_int adi_library/common/ad_sysref_gen.v /^ reg sysref_en_int;$/;" r module:ad_sysref_gen +sysref_en_m1 adi_library/common/ad_sysref_gen.v /^ reg sysref_en_m1;$/;" r module:ad_sysref_gen +sysref_en_m2 adi_library/common/ad_sysref_gen.v /^ reg sysref_en_m2;$/;" r module:ad_sysref_gen +sysref_out adi_library/common/ad_sysref_gen.v /^ output reg sysref_out$/;" p module:ad_sysref_gen +system_top hdl/system_top.v /^module system_top ($/;" m +tb_Receiver sim/tb_Receiver.v /^module tb_Receiver ();$/;" m +tb_Transmitter sim/tb_Transmitter.v /^module tb_Transmitter ();$/;" m +tb_add_prefix sim/tb_add_prefix.v /^module tb_add_prefix ();$/;" m +tb_enc_control sim/tb_enc_control.v /^module tb_enc_control ();$/;" m +tb_led sim/tb_led.v /^module tb_led($/;" m +tb_tdma sim/tb_tdma.v /^module tb_tdma ();$/;" m +tb_tx_with_enc sim/tb_tx_with_enc.v /^module tb_tx_with_enc ();$/;" m +tb_width_convert sim/tb_width_convert.v /^module tb_width_convert ();$/;" m +tdd_burst_count adi_library/common/ad_tdd_control.v /^ input [ 7:0] tdd_burst_count,$/;" p module:ad_tdd_control +tdd_burst_count adi_library/common/up_tdd_cntrl.v /^ output [ 7:0] tdd_burst_count,$/;" p module:up_tdd_cntrl +tdd_burst_counter adi_library/common/ad_tdd_control.v /^ reg [ 5:0] tdd_burst_counter = 6'h0;$/;" r module:ad_tdd_control +tdd_counter adi_library/common/ad_tdd_control.v /^ reg [23:0] tdd_counter = 24'h0;$/;" r module:ad_tdd_control +tdd_counter_init adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_counter_init,$/;" p module:ad_tdd_control +tdd_counter_init adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_counter_init,$/;" p module:up_tdd_cntrl +tdd_counter_status adi_library/common/ad_tdd_control.v /^ output [23:0] tdd_counter_status);$/;" p module:ad_tdd_control +tdd_cstate adi_library/common/ad_tdd_control.v /^ reg tdd_cstate = OFF;$/;" r module:ad_tdd_control +tdd_cstate_next adi_library/common/ad_tdd_control.v /^ reg tdd_cstate_next = OFF;$/;" r module:ad_tdd_control +tdd_enable adi_library/common/ad_tdd_control.v /^ input tdd_enable,$/;" p module:ad_tdd_control +tdd_enable adi_library/common/up_tdd_cntrl.v /^ output tdd_enable,$/;" p module:up_tdd_cntrl +tdd_endof_burst adi_library/common/ad_tdd_control.v /^ wire tdd_endof_burst;$/;" n module:ad_tdd_control +tdd_endof_frame adi_library/common/ad_tdd_control.v /^ reg tdd_endof_frame = 1'b0;$/;" r module:ad_tdd_control +tdd_frame_length adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_frame_length,$/;" p module:ad_tdd_control +tdd_frame_length adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_frame_length,$/;" p module:up_tdd_cntrl +tdd_gated_rx_dmapath adi_library/common/up_tdd_cntrl.v /^ output tdd_gated_rx_dmapath,$/;" p module:up_tdd_cntrl +tdd_gated_tx_dmapath adi_library/common/up_tdd_cntrl.v /^ output tdd_gated_tx_dmapath,$/;" p module:up_tdd_cntrl +tdd_last_burst adi_library/common/ad_tdd_control.v /^ reg tdd_last_burst = 1'b0;$/;" r module:ad_tdd_control +tdd_rx_dp_en adi_library/common/ad_tdd_control.v /^ output reg tdd_rx_dp_en,$/;" p module:ad_tdd_control +tdd_rx_dp_off_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_rx_dp_off_1,$/;" p module:ad_tdd_control +tdd_rx_dp_off_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_rx_dp_off_1,$/;" p module:up_tdd_cntrl +tdd_rx_dp_off_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_rx_dp_off_2,$/;" p module:ad_tdd_control +tdd_rx_dp_off_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_rx_dp_off_2,$/;" p module:up_tdd_cntrl +tdd_rx_dp_on_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_rx_dp_on_1,$/;" p module:ad_tdd_control +tdd_rx_dp_on_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_rx_dp_on_1,$/;" p module:up_tdd_cntrl +tdd_rx_dp_on_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_rx_dp_on_2,$/;" p module:ad_tdd_control +tdd_rx_dp_on_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_rx_dp_on_2,$/;" p module:up_tdd_cntrl +tdd_rx_off_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_rx_off_1,$/;" p module:ad_tdd_control +tdd_rx_off_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_rx_off_1,$/;" p module:up_tdd_cntrl +tdd_rx_off_1_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_rx_off_1_s;$/;" n module:ad_tdd_control +tdd_rx_off_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_rx_off_2,$/;" p module:ad_tdd_control +tdd_rx_off_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_rx_off_2,$/;" p module:up_tdd_cntrl +tdd_rx_off_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_rx_off_2_s;$/;" n module:ad_tdd_control +tdd_rx_on_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_rx_on_1,$/;" p module:ad_tdd_control +tdd_rx_on_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_rx_on_1,$/;" p module:up_tdd_cntrl +tdd_rx_on_1_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_rx_on_1_s;$/;" n module:ad_tdd_control +tdd_rx_on_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_rx_on_2,$/;" p module:ad_tdd_control +tdd_rx_on_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_rx_on_2,$/;" p module:up_tdd_cntrl +tdd_rx_on_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_rx_on_2_s;$/;" n module:ad_tdd_control +tdd_rx_only adi_library/common/ad_tdd_control.v /^ input tdd_rx_only,$/;" p module:ad_tdd_control +tdd_rx_only adi_library/common/up_tdd_cntrl.v /^ output tdd_rx_only,$/;" p module:up_tdd_cntrl +tdd_rx_rf_en adi_library/common/ad_tdd_control.v /^ output reg tdd_rx_rf_en,$/;" p module:ad_tdd_control +tdd_rx_vco_en adi_library/common/ad_tdd_control.v /^ output reg tdd_rx_vco_en,$/;" p module:ad_tdd_control +tdd_secondary adi_library/common/ad_tdd_control.v /^ input tdd_secondary,$/;" p module:ad_tdd_control +tdd_secondary adi_library/common/up_tdd_cntrl.v /^ output tdd_secondary,$/;" p module:up_tdd_cntrl +tdd_status adi_library/common/up_tdd_cntrl.v /^ input [ 7:0] tdd_status,$/;" p module:up_tdd_cntrl +tdd_sync adi_library/common/ad_tdd_control.v /^ input tdd_sync,$/;" p module:ad_tdd_control +tdd_sync_d1 adi_library/common/ad_tdd_control.v /^ reg tdd_sync_d1 = 1'b0;$/;" r module:ad_tdd_control +tdd_sync_d2 adi_library/common/ad_tdd_control.v /^ reg tdd_sync_d2 = 1'b0;$/;" r module:ad_tdd_control +tdd_sync_d3 adi_library/common/ad_tdd_control.v /^ reg tdd_sync_d3 = 1'b0;$/;" r module:ad_tdd_control +tdd_terminal_type adi_library/common/up_tdd_cntrl.v /^ output tdd_terminal_type,$/;" p module:up_tdd_cntrl +tdd_tx_dp_en adi_library/common/ad_tdd_control.v /^ output reg tdd_tx_dp_en,$/;" p module:ad_tdd_control +tdd_tx_dp_off_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_tx_dp_off_1,$/;" p module:ad_tdd_control +tdd_tx_dp_off_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_tx_dp_off_1,$/;" p module:up_tdd_cntrl +tdd_tx_dp_off_1_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_tx_dp_off_1_s;$/;" n module:ad_tdd_control +tdd_tx_dp_off_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_tx_dp_off_2,$/;" p module:ad_tdd_control +tdd_tx_dp_off_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_tx_dp_off_2,$/;" p module:up_tdd_cntrl +tdd_tx_dp_off_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_tx_dp_off_2_s;$/;" n module:ad_tdd_control +tdd_tx_dp_on_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_tx_dp_on_1,$/;" p module:ad_tdd_control +tdd_tx_dp_on_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_tx_dp_on_1,$/;" p module:up_tdd_cntrl +tdd_tx_dp_on_1_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_tx_dp_on_1_s;$/;" n module:ad_tdd_control +tdd_tx_dp_on_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_tx_dp_on_2,$/;" p module:ad_tdd_control +tdd_tx_dp_on_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_tx_dp_on_2,$/;" p module:up_tdd_cntrl +tdd_tx_dp_on_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_tx_dp_on_2_s;$/;" n module:ad_tdd_control +tdd_tx_off_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_tx_off_1,$/;" p module:ad_tdd_control +tdd_tx_off_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_tx_off_1,$/;" p module:up_tdd_cntrl +tdd_tx_off_1_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_tx_off_1_s;$/;" n module:ad_tdd_control +tdd_tx_off_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_tx_off_2,$/;" p module:ad_tdd_control +tdd_tx_off_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_tx_off_2,$/;" p module:up_tdd_cntrl +tdd_tx_off_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_tx_off_2_s;$/;" n module:ad_tdd_control +tdd_tx_on_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_tx_on_1,$/;" p module:ad_tdd_control +tdd_tx_on_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_tx_on_1,$/;" p module:up_tdd_cntrl +tdd_tx_on_1_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_tx_on_1_s;$/;" n module:ad_tdd_control +tdd_tx_on_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_tx_on_2,$/;" p module:ad_tdd_control +tdd_tx_on_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_tx_on_2,$/;" p module:up_tdd_cntrl +tdd_tx_on_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_tx_on_2_s;$/;" n module:ad_tdd_control +tdd_tx_only adi_library/common/ad_tdd_control.v /^ input tdd_tx_only,$/;" p module:ad_tdd_control +tdd_tx_only adi_library/common/up_tdd_cntrl.v /^ output tdd_tx_only,$/;" p module:up_tdd_cntrl +tdd_tx_rf_en adi_library/common/ad_tdd_control.v /^ output reg tdd_tx_rf_en,$/;" p module:ad_tdd_control +tdd_tx_vco_en adi_library/common/ad_tdd_control.v /^ output reg tdd_tx_vco_en,$/;" p module:ad_tdd_control +tdd_txrx_only_en_s adi_library/common/ad_tdd_control.v /^ wire tdd_txrx_only_en_s;$/;" n module:ad_tdd_control +tdd_vco_rx_off_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_vco_rx_off_1,$/;" p module:ad_tdd_control +tdd_vco_rx_off_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_vco_rx_off_1,$/;" p module:up_tdd_cntrl +tdd_vco_rx_off_1_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_vco_rx_off_1_s;$/;" n module:ad_tdd_control +tdd_vco_rx_off_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_vco_rx_off_2,$/;" p module:ad_tdd_control +tdd_vco_rx_off_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_vco_rx_off_2,$/;" p module:up_tdd_cntrl +tdd_vco_rx_off_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_vco_rx_off_2_s;$/;" n module:ad_tdd_control +tdd_vco_rx_on_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_vco_rx_on_1,$/;" p module:ad_tdd_control +tdd_vco_rx_on_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_vco_rx_on_1,$/;" p module:up_tdd_cntrl +tdd_vco_rx_on_1_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_vco_rx_on_1_s;$/;" n module:ad_tdd_control +tdd_vco_rx_on_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_vco_rx_on_2,$/;" p module:ad_tdd_control +tdd_vco_rx_on_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_vco_rx_on_2,$/;" p module:up_tdd_cntrl +tdd_vco_rx_on_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_vco_rx_on_2_s;$/;" n module:ad_tdd_control +tdd_vco_tx_off_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_vco_tx_off_1,$/;" p module:ad_tdd_control +tdd_vco_tx_off_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_vco_tx_off_1,$/;" p module:up_tdd_cntrl +tdd_vco_tx_off_1_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_vco_tx_off_1_s;$/;" n module:ad_tdd_control +tdd_vco_tx_off_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_vco_tx_off_2,$/;" p module:ad_tdd_control +tdd_vco_tx_off_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_vco_tx_off_2,$/;" p module:up_tdd_cntrl +tdd_vco_tx_off_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_vco_tx_off_2_s;$/;" n module:ad_tdd_control +tdd_vco_tx_on_1 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_vco_tx_on_1,$/;" p module:ad_tdd_control +tdd_vco_tx_on_1 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_vco_tx_on_1,$/;" p module:up_tdd_cntrl +tdd_vco_tx_on_1_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_vco_tx_on_1_s;$/;" n module:ad_tdd_control +tdd_vco_tx_on_2 adi_library/common/ad_tdd_control.v /^ input [23:0] tdd_vco_tx_on_2,$/;" p module:ad_tdd_control +tdd_vco_tx_on_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_vco_tx_on_2,$/;" p module:up_tdd_cntrl +tdd_vco_tx_on_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_vco_tx_on_2_s;$/;" n module:ad_tdd_control +tdma hdl/tdma.v /^module tdma #($/;" m +temp_1_01 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_1_01 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_1_01 hdl/TSync_Abs_new4.v /^ reg [19:0] temp_1_01 = 20'd0;$/;" r module:TSync_Abs_new4 +temp_1_02 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_1_02 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_1_02 hdl/TSync_Abs_new4.v /^ reg [19:0] temp_1_02 = 20'd0;$/;" r module:TSync_Abs_new4 +temp_1_03 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_1_03 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_1_04 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_1_04 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_1_05 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_1_05 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_1_06 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_1_06 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_1_07 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_1_07 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_1_08 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_1_08 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_2_01 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_2_01 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_2_02 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_2_02 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_2_03 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_2_03 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_2_04 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_2_04 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_3_1 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_3_1 = 20'd0;$/;" r module:TSync_Abs_new16 +temp_3_2 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_3_2 = 20'd0;$/;" r module:TSync_Abs_new16 +test hdl/Transmitter.v /^ input wire test,$/;" p module:Transmitter +test sim/tb_Transmitter.v /^ reg test=0;$/;" r module:tb_Transmitter +th_control hdl/SCFDE_recv_FrameSync.v /^ reg [ 3:0] th_control = 4'd8;$/;" r module:SCFDE_recv_FrameSync +three_wire adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg three_wire$/;" p module:spi_engine_execution +tic_hop_m sim/tb_tdma.v /^ wire tic_hop_m;$/;" n module:tb_tdma +tic_hop_s sim/tb_tdma.v /^ wire tic_hop_s;$/;" n module:tb_tdma +timestamp adi_library/axi_dmac/tb/axi_slave.v /^reg [31:0] timestamp = 'h00;$/;" r module:axi_slave +to_complete_count adi_library/axi_dmac/axi_dmac_response_manager.v /^reg [1:0] to_complete_count = 'h0;$/;" r module:axi_dmac_response_manager +tone_1_freq_word adi_library/common/ad_dds.v /^ input [ PHASE_DW-1:0] tone_1_freq_word,$/;" p module:ad_dds +tone_1_init_offset adi_library/common/ad_dds.v /^ input [ 15:0] tone_1_init_offset,$/;" p module:ad_dds +tone_1_scale adi_library/common/ad_dds.v /^ input [ 15:0] tone_1_scale,$/;" p module:ad_dds +tone_2_freq_word adi_library/common/ad_dds.v /^ input [ PHASE_DW-1:0] tone_2_freq_word,$/;" p module:ad_dds +tone_2_init_offset adi_library/common/ad_dds.v /^ input [ 15:0] tone_2_init_offset,$/;" p module:ad_dds +tone_2_scale adi_library/common/ad_dds.v /^ input [ 15:0] tone_2_scale,$/;" p module:ad_dds +total_frames hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ output [8:0] total_frames \/\/译码总帧数计数 $/;" p module:CCSDS_LDPC_DEC_K1024_R12_TOPP +total_frames hdl/RecvTop.v /^ wire [8:0] total_frames;$/;" n module:RecvTop +total_frames_A hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [8:0] total_frames_A; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +total_frames_B hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v /^ wire [8:0] total_frames_B; $/;" n module:CCSDS_LDPC_DEC_K1024_R12_TOPP +transfer adi_library/axi_dmac/tb/dma_read_tb.v /^ ) transfer ($/;" i module:dmac_dma_read_tb typeref:module:axi_dmac_transfer +transfer_abort adi_library/axi_dmac/data_mover.v /^ reg transfer_abort = 1'b0;$/;" r module:dmac_data_mover +transfer_abort_s adi_library/axi_dmac/data_mover.v /^wire transfer_abort_s;$/;" n module:dmac_data_mover +transfer_active adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg transfer_active = 1'b0;$/;" r module:spi_engine_execution +transfer_counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];$/;" n module:spi_engine_execution +transfer_id adi_library/axi_dmac/axi_dmac_response_manager.v /^reg [1:0] transfer_id = 'h0;$/;" r module:axi_dmac_response_manager +transfer_id adi_library/axi_dmac/data_mover.v /^ reg [1:0] transfer_id = 2'b0;$/;" r module:dmac_data_mover +transfer_id_match adi_library/axi_dmac/request_generator.v /^wire transfer_id_match;$/;" n module:dmac_request_generator +trigger adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg trigger = 1'b0;$/;" r module:spi_engine_execution +trigger adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ input trigger,$/;" p module:spi_engine_offload +trigger adi_library/util_extract/util_extract.v /^ wire [15:0] trigger; \/\/ 16 maximum channels$/;" n module:util_extract +trigger_d1 adi_library/util_extract/util_extract.v /^ reg trigger_d1;$/;" r module:util_extract +trigger_next adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg trigger_next = 1'b0;$/;" r module:spi_engine_execution +trigger_out adi_library/util_extract/util_extract.v /^ output reg trigger_out$/;" p module:util_extract +trigger_reset adi_library/axi_dmac/tb/tb_base.v /^ reg trigger_reset = 1'b0;$/;" r +trigger_reset adi_library/util_pack/tb/tb_base.v /^ reg trigger_reset = 1'b0;$/;" r +trigger_rx adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire trigger_rx;$/;" n module:spi_engine_execution +trigger_rx_d adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};$/;" r module:spi_engine_execution +trigger_rx_s adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire trigger_rx_s;$/;" n module:spi_engine_execution +trigger_s adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^wire trigger_s;$/;" n module:spi_engine_offload +trigger_tx adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire trigger_tx;$/;" n module:spi_engine_execution +trunc_25to12_2dly hdl/trunc_25to12_2dly.v /^module trunc_25to12_2dly($/;" m +tx_0_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_0_n,$/;" p module:util_adxcvr +tx_0_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_0_p,$/;" p module:util_adxcvr +tx_10_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_10_n,$/;" p module:util_adxcvr +tx_10_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_10_p,$/;" p module:util_adxcvr +tx_11_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_11_n,$/;" p module:util_adxcvr +tx_11_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_11_p,$/;" p module:util_adxcvr +tx_12_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_12_n,$/;" p module:util_adxcvr +tx_12_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_12_p,$/;" p module:util_adxcvr +tx_13_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_13_n,$/;" p module:util_adxcvr +tx_13_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_13_p,$/;" p module:util_adxcvr +tx_14_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_14_n,$/;" p module:util_adxcvr +tx_14_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_14_p,$/;" p module:util_adxcvr +tx_15_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_15_n,$/;" p module:util_adxcvr +tx_15_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_15_p,$/;" p module:util_adxcvr +tx_1_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_1_n,$/;" p module:util_adxcvr +tx_1_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_1_p,$/;" p module:util_adxcvr +tx_2_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_2_n,$/;" p module:util_adxcvr +tx_2_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_2_p,$/;" p module:util_adxcvr +tx_3_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_3_n,$/;" p module:util_adxcvr +tx_3_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_3_p,$/;" p module:util_adxcvr +tx_4_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_4_n,$/;" p module:util_adxcvr +tx_4_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_4_p,$/;" p module:util_adxcvr +tx_5_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_5_n,$/;" p module:util_adxcvr +tx_5_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_5_p,$/;" p module:util_adxcvr +tx_6_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_6_n,$/;" p module:util_adxcvr +tx_6_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_6_p,$/;" p module:util_adxcvr +tx_7_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_7_n,$/;" p module:util_adxcvr +tx_7_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_7_p,$/;" p module:util_adxcvr +tx_8_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_8_n,$/;" p module:util_adxcvr +tx_8_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_8_p,$/;" p module:util_adxcvr +tx_9_n adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_9_n,$/;" p module:util_adxcvr +tx_9_p adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_9_p,$/;" p module:util_adxcvr +tx_charisk adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg tx_charisk = 'd0;$/;" r module:axi_xcvrlb_1 +tx_charisk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [ 3:0] tx_charisk,$/;" p module:util_adxcvr_xch +tx_charisk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_0,$/;" p module:util_adxcvr +tx_charisk_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_1,$/;" p module:util_adxcvr +tx_charisk_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_10,$/;" p module:util_adxcvr +tx_charisk_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_11,$/;" p module:util_adxcvr +tx_charisk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_12,$/;" p module:util_adxcvr +tx_charisk_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_13,$/;" p module:util_adxcvr +tx_charisk_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_14,$/;" p module:util_adxcvr +tx_charisk_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_15,$/;" p module:util_adxcvr +tx_charisk_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_2,$/;" p module:util_adxcvr +tx_charisk_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_3,$/;" p module:util_adxcvr +tx_charisk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_4,$/;" p module:util_adxcvr +tx_charisk_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_5,$/;" p module:util_adxcvr +tx_charisk_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_6,$/;" p module:util_adxcvr +tx_charisk_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_7,$/;" p module:util_adxcvr +tx_charisk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_8,$/;" p module:util_adxcvr +tx_charisk_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 3:0] tx_charisk_9,$/;" p module:util_adxcvr +tx_clk adi_library/xilinx/common/ad_data_out.v /^ input tx_clk,$/;" p module:ad_data_out +tx_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input tx_clk,$/;" p module:util_adxcvr_xch +tx_clk hdl/ad9361_dp_fdd_1r1t.v /^ input tx_clk,$/;" p module:ad9361_dp_fdd_1r1t +tx_clk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_0,$/;" p module:util_adxcvr +tx_clk_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_1,$/;" p module:util_adxcvr +tx_clk_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_10,$/;" p module:util_adxcvr +tx_clk_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_11,$/;" p module:util_adxcvr +tx_clk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_12,$/;" p module:util_adxcvr +tx_clk_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_13,$/;" p module:util_adxcvr +tx_clk_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_14,$/;" p module:util_adxcvr +tx_clk_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_15,$/;" p module:util_adxcvr +tx_clk_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_2,$/;" p module:util_adxcvr +tx_clk_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_3,$/;" p module:util_adxcvr +tx_clk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_4,$/;" p module:util_adxcvr +tx_clk_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_5,$/;" p module:util_adxcvr +tx_clk_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_6,$/;" p module:util_adxcvr +tx_clk_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_7,$/;" p module:util_adxcvr +tx_clk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_8,$/;" p module:util_adxcvr +tx_clk_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input tx_clk_9,$/;" p module:util_adxcvr +tx_data adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg [31:0] tx_data = 'd0;$/;" r module:axi_xcvrlb_1 +tx_data adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [31:0] tx_data,$/;" p module:util_adxcvr_xch +tx_data hdl/ad9361_dp_fdd_1r1t.v /^ output [11:0] tx_data,$/;" p module:ad9361_dp_fdd_1r1t +tx_data_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_0,$/;" p module:util_adxcvr +tx_data_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_1,$/;" p module:util_adxcvr +tx_data_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_10,$/;" p module:util_adxcvr +tx_data_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_11,$/;" p module:util_adxcvr +tx_data_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_12,$/;" p module:util_adxcvr +tx_data_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_13,$/;" p module:util_adxcvr +tx_data_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_14,$/;" p module:util_adxcvr +tx_data_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_15,$/;" p module:util_adxcvr +tx_data_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_2,$/;" p module:util_adxcvr +tx_data_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_3,$/;" p module:util_adxcvr +tx_data_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_4,$/;" p module:util_adxcvr +tx_data_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_5,$/;" p module:util_adxcvr +tx_data_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_6,$/;" p module:util_adxcvr +tx_data_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_7,$/;" p module:util_adxcvr +tx_data_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_8,$/;" p module:util_adxcvr +tx_data_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [31:0] tx_data_9,$/;" p module:util_adxcvr +tx_data_i hdl/ad9361_dp_fdd_1r1t.v /^ input [11:0] tx_data_i,$/;" p module:ad9361_dp_fdd_1r1t +tx_data_n adi_library/xilinx/common/ad_data_out.v /^ input tx_data_n,$/;" p module:ad_data_out +tx_data_oddr hdl/ad9361_dp_fdd_1r1t.v /^ for (i = 0; i < 12; i = i + 1) begin : tx_data_oddr$/;" b module:ad9361_dp_fdd_1r1t +tx_data_oddr_inst hdl/ad9361_dp_fdd_1r1t.v /^ ) tx_data_oddr_inst ($/;" i block:ad9361_dp_fdd_1r1t.tx_data_oddr typeref:module:ODDR +tx_data_oddr_s adi_library/xilinx/common/ad_data_out.v /^ wire tx_data_oddr_s;$/;" n module:ad_data_out +tx_data_odelay_s adi_library/xilinx/common/ad_data_out.v /^ wire tx_data_odelay_s;$/;" n module:ad_data_out +tx_data_out_n adi_library/xilinx/common/ad_data_out.v /^ output tx_data_out_n,$/;" p module:ad_data_out +tx_data_out_p adi_library/xilinx/common/ad_data_out.v /^ output tx_data_out_p,$/;" p module:ad_data_out +tx_data_p adi_library/xilinx/common/ad_data_out.v /^ input tx_data_p,$/;" p module:ad_data_out +tx_data_q hdl/ad9361_dp_fdd_1r1t.v /^ input [11:0] tx_data_q,$/;" p module:ad9361_dp_fdd_1r1t +tx_data_src_count hdl/system_top.v /^ wire [31:0] tx_data_src_count;$/;" n module:system_top +tx_data_src_count sim/TB_sys.v /^ wire [31:0] tx_data_src_count;$/;" n module:TB_sys +tx_data_src_count sim/tb_tx_with_enc.v /^ wire [31:0] tx_data_src_count;$/;" n module:tb_tx_with_enc +tx_data_src_tdata hdl/Transmitter.v /^ input wire [31:0] tx_data_src_tdata,$/;" p module:Transmitter +tx_data_src_tdata hdl/system_top.v /^ wire [31:0] tx_data_src_tdata;$/;" n module:system_top +tx_data_src_tdata sim/TB_sys.v /^ wire [15:0] tx_data_src_tdata;$/;" n module:TB_sys +tx_data_src_tdata sim/tb_tx_with_enc.v /^ wire [31:0] tx_data_src_tdata;$/;" n module:tb_tx_with_enc +tx_data_src_tready hdl/Transmitter.v /^ output reg tx_data_src_tready,$/;" p module:Transmitter +tx_data_src_tready hdl/system_top.v /^ wire tx_data_src_tready;$/;" n module:system_top +tx_data_src_tready sim/TB_sys.v /^ wire tx_data_src_tready;$/;" n module:TB_sys +tx_data_src_tready sim/tb_tx_with_enc.v /^ wire tx_data_src_tready;$/;" n module:tb_tx_with_enc +tx_data_src_tvalid hdl/Transmitter.v /^ input wire tx_data_src_tvalid,$/;" p module:Transmitter +tx_data_src_tvalid hdl/system_top.v /^ wire tx_data_src_tvalid;$/;" n module:system_top +tx_data_src_tvalid sim/TB_sys.v /^ wire tx_data_src_tvalid;$/;" n module:TB_sys +tx_data_src_tvalid sim/tb_tx_with_enc.v /^ wire tx_data_src_tvalid;$/;" n module:tb_tx_with_enc +tx_frame hdl/ad9361_dp_fdd_1r1t.v /^ output tx_frame$/;" p module:ad9361_dp_fdd_1r1t +tx_n adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output [(NUM_OF_LANES-1):0] tx_n,$/;" p module:axi_xcvrlb +tx_n adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ output tx_n,$/;" p module:axi_xcvrlb_1 +tx_n adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output tx_n,$/;" p module:util_adxcvr_xch +tx_out_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output tx_out_clk,$/;" p module:util_adxcvr_xch +tx_out_clk_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_0,$/;" p module:util_adxcvr +tx_out_clk_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_1,$/;" p module:util_adxcvr +tx_out_clk_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_10,$/;" p module:util_adxcvr +tx_out_clk_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_11,$/;" p module:util_adxcvr +tx_out_clk_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_12,$/;" p module:util_adxcvr +tx_out_clk_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_13,$/;" p module:util_adxcvr +tx_out_clk_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_14,$/;" p module:util_adxcvr +tx_out_clk_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_15,$/;" p module:util_adxcvr +tx_out_clk_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_2,$/;" p module:util_adxcvr +tx_out_clk_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_3,$/;" p module:util_adxcvr +tx_out_clk_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_4,$/;" p module:util_adxcvr +tx_out_clk_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_5,$/;" p module:util_adxcvr +tx_out_clk_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_6,$/;" p module:util_adxcvr +tx_out_clk_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_7,$/;" p module:util_adxcvr +tx_out_clk_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_8,$/;" p module:util_adxcvr +tx_out_clk_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output tx_out_clk_9,$/;" p module:util_adxcvr +tx_out_clk_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire tx_out_clk_s;$/;" n module:util_adxcvr_xch +tx_p adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ output [(NUM_OF_LANES-1):0] tx_p,$/;" p module:axi_xcvrlb +tx_p adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ output tx_p,$/;" p module:axi_xcvrlb_1 +tx_p adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output tx_p,$/;" p module:util_adxcvr_xch +tx_pll_clk_sel_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [ 1:0] tx_pll_clk_sel_s;$/;" n module:util_adxcvr_xch +tx_pn_data adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg [31:0] tx_pn_data = 'd0;$/;" r module:axi_xcvrlb_1 +tx_rate_m1 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [ 2:0] tx_rate_m1 = 'd0;$/;" r module:util_adxcvr_xch +tx_rate_m2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [ 2:0] tx_rate_m2 = 'd0;$/;" r module:util_adxcvr_xch +tx_reset_d1 adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ reg tx_reset_d1;$/;" r module:util_gmii_to_rgmii +tx_reset_sync adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ reg tx_reset_sync;$/;" r module:util_gmii_to_rgmii +tx_rst_done_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire tx_rst_done_s;$/;" n module:util_adxcvr_xch +tx_start hdl/tdma.v /^ output tx_start$/;" p module:tdma +tx_start_m sim/tb_tdma.v /^ wire tx_start_m;$/;" n module:tb_tdma +tx_start_s sim/tb_tdma.v /^ wire tx_start_s;$/;" n module:tb_tdma +tx_sys_clk_sel_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [ 1:0] tx_sys_clk_sel_s;$/;" n module:util_adxcvr_xch +tx_test_flag hdl/system_top.v /^ wire tx_test_flag;$/;" n module:system_top +tx_test_flag sim/tb_tx_with_enc.v /^ wire tx_test_flag;$/;" n module:tb_tx_with_enc +tx_test_flag_ps sim/tb_tx_with_enc.v /^ wire tx_test_flag_ps;$/;" n module:tb_tx_with_enc +type_s adi_library/common/ad_datafmt.v /^ wire type_s;$/;" n module:ad_datafmt +type_s adi_library/common/util_axis_upscale.v /^ wire type_s;$/;" n module:util_axis_upscale +u_CCSDS_LDPC_ENC_R12 hdl/enc_control.v /^ CCSDS_LDPC_ENC_R12 u_CCSDS_LDPC_ENC_R12 ($/;" i module:enc_control typeref:module:CCSDS_LDPC_ENC_R12 +u_MM7020_BD_wrapper hdl/system_top.v /^ MM7020_BD_wrapper u_MM7020_BD_wrapper ($/;" i module:system_top typeref:module:MM7020_BD_wrapper +u_MM7020_BD_wrapper sim/TB_sys.v /^ MM7020_BD_wrapper u_MM7020_BD_wrapper ($/;" i module:TB_sys typeref:module:MM7020_BD_wrapper +u_MM7020_BD_wrapper sim/tb_tx_with_enc.v /^ MM7020_BD_wrapper u_MM7020_BD_wrapper ($/;" i module:tb_tx_with_enc typeref:module:MM7020_BD_wrapper +u_MagnitudeEstimator hdl/Receiver.v /^ ) u_MagnitudeEstimator ($/;" i module:Receiver typeref:module:MagnitudeEstimator +u_PAPR hdl/Receiver.v /^ ) u_PAPR ($/;" i module:Receiver typeref:module:PAPR +u_Receiver sim/tb_Receiver.v /^ Receiver u_Receiver ($/;" i module:tb_Receiver typeref:module:Receiver +u_Transmitter sim/tb_Transmitter.v /^ ) u_Transmitter ($/;" i module:tb_Transmitter typeref:module:Transmitter +u_Transmitter sim/tb_tx_with_enc.v /^ Transmitter u_Transmitter ($/;" i module:tb_tx_with_enc typeref:module:Transmitter +u_ad9361_mgc_pin_ctrl hdl/RecvTop.v /^ ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ($/;" i module:RecvTop typeref:module:ad9361_mgc_pin_ctrl +u_ad9361_mgc_pin_ctrl hdl/system_top.v /^ ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ($/;" i module:system_top typeref:module:ad9361_mgc_pin_ctrl +u_add_prefix hdl/enc_control.v /^ ) u_add_prefix ($/;" i module:enc_control typeref:module:add_prefix +u_add_prefix sim/tb_add_prefix.v /^ ) u_add_prefix ($/;" i module:tb_add_prefix typeref:module:add_prefix +u_adder_i hdl/frame_sync.v /^ adder_iq u_adder_i ($/;" i block:frame_sync.adder_gen_block typeref:module:adder_iq +u_bram_chu_seq hdl/Transmitter.v /^ bram_chu_seq u_bram_chu_seq ($/;" i module:Transmitter typeref:module:bram_chu_seq +u_bram_m_seqs_512 hdl/Transmitter.v /^ bram_m_seqs_512 u_bram_m_seqs_512 ($/;" i module:Transmitter typeref:module:bram_m_seqs_512 +u_bram_tx_test hdl/Transmitter.v /^ bram_tx_test u_bram_tx_test ($/;" i module:Transmitter typeref:module:bram_tx_test +u_clk_wiz_baseband hdl/system_top.v /^ clk_wiz_baseband u_clk_wiz_baseband ($/;" i module:system_top typeref:module:clk_wiz_baseband +u_clk_wiz_baseband sim/TB_sys.v /^ clk_wiz_baseband u_clk_wiz_baseband ($/;" i module:TB_sys typeref:module:clk_wiz_baseband +u_clk_wiz_baseband sim/tb_tx_with_enc.v /^ clk_wiz_baseband u_clk_wiz_baseband ($/;" i module:tb_tx_with_enc typeref:module:clk_wiz_baseband +u_clk_wiz_poweron hdl/system_top.v /^ clk_wiz_poweron u_clk_wiz_poweron ($/;" i module:system_top typeref:module:clk_wiz_poweron +u_clk_wiz_poweron sim/TB_sys.v /^ clk_wiz_poweron u_clk_wiz_poweron ($/;" i module:TB_sys typeref:module:clk_wiz_poweron +u_clk_wiz_poweron sim/tb_tx_with_enc.v /^ clk_wiz_poweron u_clk_wiz_poweron ($/;" i module:tb_tx_with_enc typeref:module:clk_wiz_poweron +u_enc_control sim/tb_enc_control.v /^ enc_control u_enc_control ($/;" i module:tb_enc_control typeref:module:enc_control +u_enc_control sim/tb_tx_with_enc.v /^ enc_control u_enc_control ($/;" i module:tb_tx_with_enc typeref:module:enc_control +u_fifo_enc_out hdl/enc_control.v /^ fifo_enc_out u_fifo_enc_out ($/;" i module:enc_control typeref:module:fifo_enc_out +u_fifo_shift hdl/Receiver.v /^ fifo_shift u_fifo_shift ($/;" i module:Receiver typeref:module:fifo_shift +u_fifo_width_convert_1_2 hdl/enc_control.v /^ fifo_width_convert_1_2 u_fifo_width_convert_1_2 ($/;" i module:enc_control typeref:module:fifo_width_convert_1_2 +u_fir_dmf_interp4_i hdl/Receiver.v /^ fir_dmf_interp4 u_fir_dmf_interp4_i ($/;" i module:Receiver typeref:module:fir_dmf_interp4 +u_fir_dmf_interp4_q hdl/Receiver.v /^ fir_dmf_interp4 u_fir_dmf_interp4_q ($/;" i module:Receiver typeref:module:fir_dmf_interp4 +u_fir_match_filter_interp4_i hdl/Receiver.v /^ fir_match_interp4 u_fir_match_filter_interp4_i ($/;" i module:Receiver typeref:module:fir_match_interp4 +u_fir_match_filter_interp4_q hdl/Receiver.v /^ fir_match_interp4 u_fir_match_filter_interp4_q ($/;" i module:Receiver typeref:module:fir_match_interp4 +u_fir_shape_interp16_i hdl/Transmitter.v /^ fir_shape_interp16 u_fir_shape_interp16_i ($/;" i module:Transmitter typeref:module:fir_shape_interp16 +u_fir_shape_interp16_q hdl/Transmitter.v /^ fir_shape_interp16 u_fir_shape_interp16_q ($/;" i module:Transmitter typeref:module:fir_shape_interp16 +u_fir_shape_interp4_i hdl/Transmitter.v /^ fir_shape_interp4 u_fir_shape_interp4_i ($/;" i module:Transmitter typeref:module:fir_shape_interp4 +u_fir_shape_interp4_q hdl/Transmitter.v /^ fir_shape_interp4 u_fir_shape_interp4_q ($/;" i module:Transmitter typeref:module:fir_shape_interp4 +u_fir_shape_interp8_i hdl/Transmitter.v /^ fir_shape_interp8 u_fir_shape_interp8_i ($/;" i module:Transmitter typeref:module:fir_shape_interp8 +u_fir_shape_interp8_q hdl/Transmitter.v /^ fir_shape_interp8 u_fir_shape_interp8_q ($/;" i module:Transmitter typeref:module:fir_shape_interp8 +u_ila_ad9361_mgc hdl/ad9361_mgc_pin_ctrl.v /^ ila_ad9361_mgc u_ila_ad9361_mgc ($/;" i module:ad9361_mgc_pin_ctrl typeref:module:ila_ad9361_mgc +u_ila_ad9361_rx hdl/system_top.v /^ ila_ad9361_rx u_ila_ad9361_rx ($/;" i module:system_top typeref:module:ila_ad9361_rx +u_ila_ad9361_tx hdl/system_top.v /^ ila_ad9361_tx u_ila_ad9361_tx ($/;" i module:system_top typeref:module:ila_ad9361_tx +u_ila_frame_sync hdl/PAPR.v /^ ila_frame_sync u_ila_frame_sync ($/;" i module:PAPR typeref:module:ila_frame_sync +u_ila_transmitter hdl/Transmitter.v /^ ila_transmitter u_ila_transmitter ($/;" i module:Transmitter typeref:module:ila_transmitter +u_power_measure hdl/ad9361_mgc_pin_ctrl.v /^ power_measure u_power_measure ($/;" i module:ad9361_mgc_pin_ctrl typeref:module:power_measure +u_shift256_8 hdl/add_prefix.v /^ shift256_8 u_shift256_8 ($/;" i module:add_prefix typeref:module:shift256_8 +u_shift_reg hdl/PAPR.v /^ ) u_shift_reg ($/;" i module:PAPR typeref:module:shift_reg +u_tdma sim/tb_tx_with_enc.v /^ ) u_tdma ($/;" i module:tb_tx_with_enc typeref:module:tdma +u_tdma_master sim/tb_tdma.v /^ ) u_tdma_master ($/;" i module:tb_tdma typeref:module:tdma +u_tdma_slave sim/tb_tdma.v /^ ) u_tdma_slave ($/;" i module:tb_tdma typeref:module:tdma +u_vio_gpio hdl/system_top.v /^ vio_gpio u_vio_gpio ($/;" i module:system_top typeref:module:vio_gpio +u_vio_phy_control hdl/system_top.v /^ vio_phy_control u_vio_phy_control ($/;" i module:system_top typeref:module:vio_phy_control +u_vio_tx_speed_mode hdl/system_top.v /^ vio_tx_speed_mode u_vio_tx_speed_mode ($/;" i module:system_top typeref:module:vio_tx_speed_mode +u_width_convert hdl/enc_control.v /^ ) u_width_convert ($/;" i module:enc_control typeref:module:width_convert +u_width_convert sim/tb_width_convert.v /^ ) u_width_convert ($/;" i module:tb_width_convert typeref:module:width_convert +uart_rx hdl/system_top.v /^ input uart_rx,$/;" p module:system_top +uart_tx hdl/system_top.v /^ output uart_tx,$/;" p module:system_top +underflow adi_library/axi_dmac/dest_fifo_inf.v /^ output reg underflow,$/;" p module:dmac_dest_fifo_inf +up_ack adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg up_ack = 'd0;$/;" r module:axi_adxcvr_es +up_adc_ce adi_library/common/up_adc_common.v /^ output up_adc_ce,$/;" p module:up_adc_common +up_adc_channel adi_library/common/up_adc_channel.v /^module up_adc_channel #($/;" m +up_adc_clk_count_s adi_library/common/up_adc_common.v /^ wire [31:0] up_adc_clk_count_s;$/;" n module:up_adc_common +up_adc_clk_enb adi_library/common/up_adc_common.v /^ reg up_adc_clk_enb = 'd0;$/;" r module:up_adc_common +up_adc_clk_enb_int adi_library/common/up_adc_common.v /^ reg up_adc_clk_enb_int = 'd1;$/;" r module:up_adc_common +up_adc_common adi_library/common/up_adc_common.v /^module up_adc_common #($/;" m +up_adc_data_sel adi_library/common/up_adc_channel.v /^ reg [ 3:0] up_adc_data_sel = 'd0;$/;" r module:up_adc_channel +up_adc_data_sel_m adi_library/common/up_adc_channel.v /^ reg [ 3:0] up_adc_data_sel_m = 'd0;$/;" r module:up_adc_channel +up_adc_dcfilt_coeff adi_library/common/up_adc_channel.v /^ reg [15:0] up_adc_dcfilt_coeff = 'd0;$/;" r module:up_adc_channel +up_adc_dcfilt_enb adi_library/common/up_adc_channel.v /^ reg up_adc_dcfilt_enb = 'd0;$/;" r module:up_adc_channel +up_adc_dcfilt_offset adi_library/common/up_adc_channel.v /^ reg [15:0] up_adc_dcfilt_offset = 'd0;$/;" r module:up_adc_channel +up_adc_ddr_edgesel adi_library/common/up_adc_common.v /^ reg up_adc_ddr_edgesel = 'd0;$/;" r module:up_adc_common +up_adc_dfmt_enable adi_library/common/up_adc_channel.v /^ reg up_adc_dfmt_enable = 'd0;$/;" r module:up_adc_channel +up_adc_dfmt_se adi_library/common/up_adc_channel.v /^ reg up_adc_dfmt_se = 'd0;$/;" r module:up_adc_channel +up_adc_dfmt_type adi_library/common/up_adc_channel.v /^ reg up_adc_dfmt_type = 'd0;$/;" r module:up_adc_channel +up_adc_enable adi_library/common/up_adc_channel.v /^ reg up_adc_enable = 'd0;$/;" r module:up_adc_channel +up_adc_gpio_in adi_library/common/up_adc_common.v /^ input [31:0] up_adc_gpio_in,$/;" p module:up_adc_common +up_adc_gpio_out adi_library/common/up_adc_common.v /^ output [31:0] up_adc_gpio_out,$/;" p module:up_adc_common +up_adc_gpio_out_int adi_library/common/up_adc_common.v /^ reg [31:0] up_adc_gpio_out_int = 'd0;$/;" r module:up_adc_common +up_adc_iqcor_coeff_1 adi_library/common/up_adc_channel.v /^ reg [15:0] up_adc_iqcor_coeff_1 = 'd0;$/;" r module:up_adc_channel +up_adc_iqcor_coeff_2 adi_library/common/up_adc_channel.v /^ reg [15:0] up_adc_iqcor_coeff_2 = 'd0;$/;" r module:up_adc_channel +up_adc_iqcor_coeff_tc_1 adi_library/common/up_adc_channel.v /^ reg [15:0] up_adc_iqcor_coeff_tc_1 = 'd0;$/;" r module:up_adc_channel +up_adc_iqcor_coeff_tc_2 adi_library/common/up_adc_channel.v /^ reg [15:0] up_adc_iqcor_coeff_tc_2 = 'd0;$/;" r module:up_adc_channel +up_adc_iqcor_enb adi_library/common/up_adc_channel.v /^ reg up_adc_iqcor_enb = 'd0;$/;" r module:up_adc_channel +up_adc_lb_enb adi_library/common/up_adc_channel.v /^ reg up_adc_lb_enb = 'd0;$/;" r module:up_adc_channel +up_adc_num_lanes adi_library/common/up_adc_common.v /^ reg [4:0] up_adc_num_lanes = 'd0;$/;" r module:up_adc_common +up_adc_or adi_library/common/up_adc_channel.v /^ output up_adc_or,$/;" p module:up_adc_channel +up_adc_or_int adi_library/common/up_adc_channel.v /^ reg up_adc_or_int = 'd0;$/;" r module:up_adc_channel +up_adc_or_s adi_library/common/up_adc_channel.v /^ wire up_adc_or_s;$/;" n module:up_adc_channel +up_adc_pin_mode adi_library/common/up_adc_common.v /^ reg up_adc_pin_mode = 'd0;$/;" r module:up_adc_common +up_adc_pn_err adi_library/common/up_adc_channel.v /^ output up_adc_pn_err,$/;" p module:up_adc_channel +up_adc_pn_err_int adi_library/common/up_adc_channel.v /^ reg up_adc_pn_err_int = 'd0;$/;" r module:up_adc_channel +up_adc_pn_err_s adi_library/common/up_adc_channel.v /^ wire up_adc_pn_err_s;$/;" n module:up_adc_channel +up_adc_pn_oos adi_library/common/up_adc_channel.v /^ output up_adc_pn_oos,$/;" p module:up_adc_channel +up_adc_pn_oos_int adi_library/common/up_adc_channel.v /^ reg up_adc_pn_oos_int = 'd0;$/;" r module:up_adc_channel +up_adc_pn_oos_s adi_library/common/up_adc_channel.v /^ wire up_adc_pn_oos_s;$/;" n module:up_adc_channel +up_adc_pn_sel adi_library/common/up_adc_channel.v /^ reg up_adc_pn_sel = 'd0;$/;" r module:up_adc_channel +up_adc_pn_type adi_library/common/up_adc_channel.v /^ reg up_adc_pn_type = 'd0;$/;" r module:up_adc_channel +up_adc_pnseq_sel adi_library/common/up_adc_channel.v /^ reg [ 3:0] up_adc_pnseq_sel = 'd0;$/;" r module:up_adc_channel +up_adc_pnseq_sel_m adi_library/common/up_adc_channel.v /^ reg [ 3:0] up_adc_pnseq_sel_m = 'd0;$/;" r module:up_adc_channel +up_adc_r1_mode adi_library/common/up_adc_common.v /^ output reg up_adc_r1_mode = 'd0,$/;" p module:up_adc_common +up_adc_sdr_ddr_n adi_library/common/up_adc_common.v /^ reg up_adc_sdr_ddr_n = 'd0;$/;" r module:up_adc_common +up_adc_sref_sync adi_library/common/up_adc_common.v /^ reg up_adc_sref_sync = 'd0;$/;" r module:up_adc_common +up_adc_start_code adi_library/common/up_adc_common.v /^ reg [31:0] up_adc_start_code = 'd0;$/;" r module:up_adc_common +up_adc_sync adi_library/common/up_adc_common.v /^ reg up_adc_sync = 'd0;$/;" r module:up_adc_common +up_addr adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [11:0] up_addr = 'd0;$/;" r module:axi_adxcvr_es +up_addr_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [11:0] up_addr_int = 'd0;$/;" r module:util_adxcvr_xch +up_addr_int adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ reg [11:0] up_addr_int = 'd0;$/;" r module:util_adxcvr_xcm +up_awaddr adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [31:0] up_awaddr = 'd0;$/;" r module:axi_adxcvr_es +up_awvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg up_awvalid = 'd0;$/;" r module:axi_adxcvr_es +up_axi adi_library/common/up_axi.v /^module up_axi #($/;" m +up_axi hdl/up_axi.v /^module up_axi #($/;" m +up_axi_araddr adi_library/common/up_axi.v /^ input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr,$/;" p module:up_axi +up_axi_araddr adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output [31:0] up_axi_araddr,$/;" p module:axi_adxcvr_es +up_axi_araddr hdl/up_axi.v /^ input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr,$/;" p module:up_axi +up_axi_arprot adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output [ 2:0] up_axi_arprot,$/;" p module:axi_adxcvr_es +up_axi_arready adi_library/common/up_axi.v /^ output up_axi_arready,$/;" p module:up_axi +up_axi_arready adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input up_axi_arready,$/;" p module:axi_adxcvr_es +up_axi_arready hdl/up_axi.v /^ output up_axi_arready,$/;" p module:up_axi +up_axi_arready_int adi_library/common/up_axi.v /^ reg up_axi_arready_int = 'd0;$/;" r module:up_axi +up_axi_arready_int hdl/up_axi.v /^ reg up_axi_arready_int = 'd0;$/;" r module:up_axi +up_axi_arvalid adi_library/common/up_axi.v /^ input up_axi_arvalid,$/;" p module:up_axi +up_axi_arvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output up_axi_arvalid,$/;" p module:axi_adxcvr_es +up_axi_arvalid hdl/up_axi.v /^ input up_axi_arvalid,$/;" p module:up_axi +up_axi_awaddr adi_library/common/up_axi.v /^ input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr,$/;" p module:up_axi +up_axi_awaddr adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output [31:0] up_axi_awaddr,$/;" p module:axi_adxcvr_es +up_axi_awaddr hdl/up_axi.v /^ input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr,$/;" p module:up_axi +up_axi_awprot adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output [ 2:0] up_axi_awprot,$/;" p module:axi_adxcvr_es +up_axi_awready adi_library/common/up_axi.v /^ output up_axi_awready,$/;" p module:up_axi +up_axi_awready adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input up_axi_awready,$/;" p module:axi_adxcvr_es +up_axi_awready hdl/up_axi.v /^ output up_axi_awready,$/;" p module:up_axi +up_axi_awready_int adi_library/common/up_axi.v /^ reg up_axi_awready_int = 'd0;$/;" r module:up_axi +up_axi_awready_int hdl/up_axi.v /^ reg up_axi_awready_int = 'd0;$/;" r module:up_axi +up_axi_awvalid adi_library/common/up_axi.v /^ input up_axi_awvalid,$/;" p module:up_axi +up_axi_awvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output up_axi_awvalid,$/;" p module:axi_adxcvr_es +up_axi_awvalid hdl/up_axi.v /^ input up_axi_awvalid,$/;" p module:up_axi +up_axi_bready adi_library/common/up_axi.v /^ input up_axi_bready,$/;" p module:up_axi +up_axi_bready adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output up_axi_bready,$/;" p module:axi_adxcvr_es +up_axi_bready hdl/up_axi.v /^ input up_axi_bready,$/;" p module:up_axi +up_axi_bresp adi_library/common/up_axi.v /^ output [ 1:0] up_axi_bresp,$/;" p module:up_axi +up_axi_bresp adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [ 1:0] up_axi_bresp,$/;" p module:axi_adxcvr_es +up_axi_bresp hdl/up_axi.v /^ output [ 1:0] up_axi_bresp,$/;" p module:up_axi +up_axi_bresp_int hdl/up_axi.v /^ reg [ 1:0] up_axi_bresp_int = 'd0;$/;" r module:up_axi +up_axi_bvalid adi_library/common/up_axi.v /^ output up_axi_bvalid,$/;" p module:up_axi +up_axi_bvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input up_axi_bvalid,$/;" p module:axi_adxcvr_es +up_axi_bvalid hdl/up_axi.v /^ output up_axi_bvalid,$/;" p module:up_axi +up_axi_bvalid_int adi_library/common/up_axi.v /^ reg up_axi_bvalid_int = 'd0;$/;" r module:up_axi +up_axi_bvalid_int hdl/up_axi.v /^ reg up_axi_bvalid_int = 'd0;$/;" r module:up_axi +up_axi_rdata adi_library/common/up_axi.v /^ output [31:0] up_axi_rdata,$/;" p module:up_axi +up_axi_rdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [31:0] up_axi_rdata,$/;" p module:axi_adxcvr_es +up_axi_rdata hdl/up_axi.v /^ output [ 31:0] up_axi_rdata,$/;" p module:up_axi +up_axi_rdata_int adi_library/common/up_axi.v /^ reg [31:0] up_axi_rdata_int = 'd0;$/;" r module:up_axi +up_axi_rdata_int hdl/up_axi.v /^ reg [ 31:0] up_axi_rdata_int = 'd0;$/;" r module:up_axi +up_axi_rready adi_library/common/up_axi.v /^ input up_axi_rready,$/;" p module:up_axi +up_axi_rready adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output up_axi_rready);$/;" p module:axi_adxcvr_es +up_axi_rready hdl/up_axi.v /^ input up_axi_rready,$/;" p module:up_axi +up_axi_rresp adi_library/common/up_axi.v /^ output [ 1:0] up_axi_rresp,$/;" p module:up_axi +up_axi_rresp adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [ 1:0] up_axi_rresp,$/;" p module:axi_adxcvr_es +up_axi_rresp hdl/up_axi.v /^ output [ 1:0] up_axi_rresp,$/;" p module:up_axi +up_axi_rresp_int hdl/up_axi.v /^ reg [ 1:0] up_axi_rresp_int = 'd0;$/;" r module:up_axi +up_axi_rvalid adi_library/common/up_axi.v /^ output up_axi_rvalid,$/;" p module:up_axi +up_axi_rvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input up_axi_rvalid,$/;" p module:axi_adxcvr_es +up_axi_rvalid hdl/up_axi.v /^ output up_axi_rvalid,$/;" p module:up_axi +up_axi_rvalid_int adi_library/common/up_axi.v /^ reg up_axi_rvalid_int = 'd0;$/;" r module:up_axi +up_axi_rvalid_int hdl/up_axi.v /^ reg up_axi_rvalid_int = 'd0;$/;" r module:up_axi +up_axi_wdata adi_library/common/up_axi.v /^ input [31:0] up_axi_wdata,$/;" p module:up_axi +up_axi_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output [31:0] up_axi_wdata,$/;" p module:axi_adxcvr_es +up_axi_wdata hdl/up_axi.v /^ input [ 31:0] up_axi_wdata,$/;" p module:up_axi +up_axi_wready adi_library/common/up_axi.v /^ output up_axi_wready,$/;" p module:up_axi +up_axi_wready adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input up_axi_wready,$/;" p module:axi_adxcvr_es +up_axi_wready hdl/up_axi.v /^ output up_axi_wready,$/;" p module:up_axi +up_axi_wready_int adi_library/common/up_axi.v /^ reg up_axi_wready_int = 'd0;$/;" r module:up_axi +up_axi_wready_int hdl/up_axi.v /^ reg up_axi_wready_int = 'd0;$/;" r module:up_axi +up_axi_wstrb adi_library/common/up_axi.v /^ input [ 3:0] up_axi_wstrb,$/;" p module:up_axi +up_axi_wstrb adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output [ 3:0] up_axi_wstrb,$/;" p module:axi_adxcvr_es +up_axi_wstrb hdl/up_axi.v /^ input [ 3:0] up_axi_wstrb,$/;" p module:up_axi +up_axi_wvalid adi_library/common/up_axi.v /^ input up_axi_wvalid,$/;" p module:up_axi +up_axi_wvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output up_axi_wvalid,$/;" p module:axi_adxcvr_es +up_axi_wvalid hdl/up_axi.v /^ input up_axi_wvalid,$/;" p module:up_axi +up_bgr adi_library/common/up_hdmi_rx.v /^ reg up_bgr = 'd0;$/;" r module:up_hdmi_rx +up_bl_partial adi_library/axi_dmac/axi_dmac_regmap_request.v /^wire up_bl_partial;$/;" n module:axi_dmac_regmap_request +up_bresp_d hdl/up_axi.v /^ reg [ 1:0] up_bresp_d;$/;" r module:up_axi +up_bresp_s hdl/up_axi.v /^ wire [ 1:0] up_bresp_s;$/;" n module:up_axi +up_cdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [15:0] up_cdata = 'd0;$/;" r module:axi_adxcvr_es +up_ch_addr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [11:0] up_ch_addr;$/;" n module:axi_adxcvr +up_ch_addr adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [11:0] up_ch_addr,$/;" p module:axi_adxcvr_up +up_ch_addr_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_0,$/;" p module:axi_adxcvr +up_ch_addr_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_1,$/;" p module:axi_adxcvr +up_ch_addr_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_10,$/;" p module:axi_adxcvr +up_ch_addr_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_11,$/;" p module:axi_adxcvr +up_ch_addr_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_12,$/;" p module:axi_adxcvr +up_ch_addr_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_13,$/;" p module:axi_adxcvr +up_ch_addr_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_14,$/;" p module:axi_adxcvr +up_ch_addr_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_15,$/;" p module:axi_adxcvr +up_ch_addr_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_2,$/;" p module:axi_adxcvr +up_ch_addr_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_3,$/;" p module:axi_adxcvr +up_ch_addr_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_4,$/;" p module:axi_adxcvr +up_ch_addr_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_5,$/;" p module:axi_adxcvr +up_ch_addr_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_6,$/;" p module:axi_adxcvr +up_ch_addr_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_7,$/;" p module:axi_adxcvr +up_ch_addr_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_8,$/;" p module:axi_adxcvr +up_ch_addr_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_ch_addr_9,$/;" p module:axi_adxcvr +up_ch_enb adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_enb;$/;" n module:axi_adxcvr +up_ch_enb adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_ch_enb,$/;" p module:axi_adxcvr_up +up_ch_enb_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_0,$/;" p module:axi_adxcvr +up_ch_enb_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_1,$/;" p module:axi_adxcvr +up_ch_enb_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_10,$/;" p module:axi_adxcvr +up_ch_enb_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_11,$/;" p module:axi_adxcvr +up_ch_enb_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_12,$/;" p module:axi_adxcvr +up_ch_enb_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_13,$/;" p module:axi_adxcvr +up_ch_enb_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_14,$/;" p module:axi_adxcvr +up_ch_enb_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_15,$/;" p module:axi_adxcvr +up_ch_enb_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_2,$/;" p module:axi_adxcvr +up_ch_enb_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_3,$/;" p module:axi_adxcvr +up_ch_enb_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_4,$/;" p module:axi_adxcvr +up_ch_enb_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_5,$/;" p module:axi_adxcvr +up_ch_enb_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_6,$/;" p module:axi_adxcvr +up_ch_enb_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_7,$/;" p module:axi_adxcvr +up_ch_enb_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_8,$/;" p module:axi_adxcvr +up_ch_enb_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_enb_9,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_lpm_dfe_n;$/;" n module:axi_adxcvr +up_ch_lpm_dfe_n adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input up_ch_lpm_dfe_n,$/;" p module:axi_adxcvr_es +up_ch_lpm_dfe_n adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_ch_lpm_dfe_n,$/;" p module:axi_adxcvr_up +up_ch_lpm_dfe_n_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_0,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_1,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_10,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_11,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_12,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_13,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_14,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_15,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_2,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_3,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_4,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_5,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_6,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_7,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_8,$/;" p module:axi_adxcvr +up_ch_lpm_dfe_n_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_lpm_dfe_n_9,$/;" p module:axi_adxcvr +up_ch_out_clk_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 2:0] up_ch_out_clk_sel;$/;" n module:axi_adxcvr +up_ch_out_clk_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 2:0] up_ch_out_clk_sel,$/;" p module:axi_adxcvr_up +up_ch_out_clk_sel_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_0,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_1,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_10,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_11,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_12,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_13,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_14,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_15,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_2,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_3,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_4,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_5,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_6,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_7,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_8,$/;" p module:axi_adxcvr +up_ch_out_clk_sel_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_out_clk_sel_9,$/;" p module:axi_adxcvr +up_ch_pll_locked adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input up_ch_pll_locked,$/;" p module:axi_adxcvr_up +up_ch_pll_locked_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_0,$/;" p module:axi_adxcvr +up_ch_pll_locked_0_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_0_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_1,$/;" p module:axi_adxcvr +up_ch_pll_locked_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_10,$/;" p module:axi_adxcvr +up_ch_pll_locked_10_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_10_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_11,$/;" p module:axi_adxcvr +up_ch_pll_locked_11_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_11_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_12,$/;" p module:axi_adxcvr +up_ch_pll_locked_12_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_12_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_13,$/;" p module:axi_adxcvr +up_ch_pll_locked_13_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_13_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_14,$/;" p module:axi_adxcvr +up_ch_pll_locked_14_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_14_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_15,$/;" p module:axi_adxcvr +up_ch_pll_locked_15_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_15_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_1_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_1_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_2,$/;" p module:axi_adxcvr +up_ch_pll_locked_2_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_2_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_3,$/;" p module:axi_adxcvr +up_ch_pll_locked_3_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_3_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_4,$/;" p module:axi_adxcvr +up_ch_pll_locked_4_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_4_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_5,$/;" p module:axi_adxcvr +up_ch_pll_locked_5_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_5_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_6,$/;" p module:axi_adxcvr +up_ch_pll_locked_6_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_6_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_7,$/;" p module:axi_adxcvr +up_ch_pll_locked_7_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_7_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_8,$/;" p module:axi_adxcvr +up_ch_pll_locked_8_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_8_s;$/;" n module:axi_adxcvr +up_ch_pll_locked_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_pll_locked_9,$/;" p module:axi_adxcvr +up_ch_pll_locked_9_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_pll_locked_9_s;$/;" n module:axi_adxcvr +up_ch_rate adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 2:0] up_ch_rate;$/;" n module:axi_adxcvr +up_ch_rate adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 2:0] up_ch_rate,$/;" p module:axi_adxcvr_up +up_ch_rate_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_0,$/;" p module:axi_adxcvr +up_ch_rate_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_1,$/;" p module:axi_adxcvr +up_ch_rate_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_10,$/;" p module:axi_adxcvr +up_ch_rate_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_11,$/;" p module:axi_adxcvr +up_ch_rate_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_12,$/;" p module:axi_adxcvr +up_ch_rate_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_13,$/;" p module:axi_adxcvr +up_ch_rate_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_14,$/;" p module:axi_adxcvr +up_ch_rate_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_15,$/;" p module:axi_adxcvr +up_ch_rate_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_2,$/;" p module:axi_adxcvr +up_ch_rate_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_3,$/;" p module:axi_adxcvr +up_ch_rate_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_4,$/;" p module:axi_adxcvr +up_ch_rate_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_5,$/;" p module:axi_adxcvr +up_ch_rate_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_6,$/;" p module:axi_adxcvr +up_ch_rate_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_7,$/;" p module:axi_adxcvr +up_ch_rate_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_8,$/;" p module:axi_adxcvr +up_ch_rate_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 2:0] up_ch_rate_9,$/;" p module:axi_adxcvr +up_ch_rdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input [15:0] up_ch_rdata,$/;" p module:axi_adxcvr_up +up_ch_rdata_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_0,$/;" p module:axi_adxcvr +up_ch_rdata_0_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_0_s;$/;" n module:axi_adxcvr +up_ch_rdata_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_1,$/;" p module:axi_adxcvr +up_ch_rdata_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_10,$/;" p module:axi_adxcvr +up_ch_rdata_10_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_10_s;$/;" n module:axi_adxcvr +up_ch_rdata_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_11,$/;" p module:axi_adxcvr +up_ch_rdata_11_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_11_s;$/;" n module:axi_adxcvr +up_ch_rdata_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_12,$/;" p module:axi_adxcvr +up_ch_rdata_12_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_12_s;$/;" n module:axi_adxcvr +up_ch_rdata_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_13,$/;" p module:axi_adxcvr +up_ch_rdata_13_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_13_s;$/;" n module:axi_adxcvr +up_ch_rdata_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_14,$/;" p module:axi_adxcvr +up_ch_rdata_14_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_14_s;$/;" n module:axi_adxcvr +up_ch_rdata_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_15,$/;" p module:axi_adxcvr +up_ch_rdata_15_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_15_s;$/;" n module:axi_adxcvr +up_ch_rdata_1_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_1_s;$/;" n module:axi_adxcvr +up_ch_rdata_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_2,$/;" p module:axi_adxcvr +up_ch_rdata_2_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_2_s;$/;" n module:axi_adxcvr +up_ch_rdata_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_3,$/;" p module:axi_adxcvr +up_ch_rdata_3_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_3_s;$/;" n module:axi_adxcvr +up_ch_rdata_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_4,$/;" p module:axi_adxcvr +up_ch_rdata_4_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_4_s;$/;" n module:axi_adxcvr +up_ch_rdata_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_5,$/;" p module:axi_adxcvr +up_ch_rdata_5_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_5_s;$/;" n module:axi_adxcvr +up_ch_rdata_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_6,$/;" p module:axi_adxcvr +up_ch_rdata_6_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_6_s;$/;" n module:axi_adxcvr +up_ch_rdata_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_7,$/;" p module:axi_adxcvr +up_ch_rdata_7_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_7_s;$/;" n module:axi_adxcvr +up_ch_rdata_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_8,$/;" p module:axi_adxcvr +up_ch_rdata_8_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_8_s;$/;" n module:axi_adxcvr +up_ch_rdata_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_ch_rdata_9,$/;" p module:axi_adxcvr +up_ch_rdata_9_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_rdata_9_s;$/;" n module:axi_adxcvr +up_ch_ready adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input up_ch_ready,$/;" p module:axi_adxcvr_up +up_ch_ready_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_0,$/;" p module:axi_adxcvr +up_ch_ready_0_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_0_s;$/;" n module:axi_adxcvr +up_ch_ready_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_1,$/;" p module:axi_adxcvr +up_ch_ready_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_10,$/;" p module:axi_adxcvr +up_ch_ready_10_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_10_s;$/;" n module:axi_adxcvr +up_ch_ready_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_11,$/;" p module:axi_adxcvr +up_ch_ready_11_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_11_s;$/;" n module:axi_adxcvr +up_ch_ready_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_12,$/;" p module:axi_adxcvr +up_ch_ready_12_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_12_s;$/;" n module:axi_adxcvr +up_ch_ready_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_13,$/;" p module:axi_adxcvr +up_ch_ready_13_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_13_s;$/;" n module:axi_adxcvr +up_ch_ready_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_14,$/;" p module:axi_adxcvr +up_ch_ready_14_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_14_s;$/;" n module:axi_adxcvr +up_ch_ready_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_15,$/;" p module:axi_adxcvr +up_ch_ready_15_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_15_s;$/;" n module:axi_adxcvr +up_ch_ready_1_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_1_s;$/;" n module:axi_adxcvr +up_ch_ready_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_2,$/;" p module:axi_adxcvr +up_ch_ready_2_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_2_s;$/;" n module:axi_adxcvr +up_ch_ready_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_3,$/;" p module:axi_adxcvr +up_ch_ready_3_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_3_s;$/;" n module:axi_adxcvr +up_ch_ready_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_4,$/;" p module:axi_adxcvr +up_ch_ready_4_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_4_s;$/;" n module:axi_adxcvr +up_ch_ready_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_5,$/;" p module:axi_adxcvr +up_ch_ready_5_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_5_s;$/;" n module:axi_adxcvr +up_ch_ready_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_6,$/;" p module:axi_adxcvr +up_ch_ready_6_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_6_s;$/;" n module:axi_adxcvr +up_ch_ready_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_7,$/;" p module:axi_adxcvr +up_ch_ready_7_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_7_s;$/;" n module:axi_adxcvr +up_ch_ready_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_8,$/;" p module:axi_adxcvr +up_ch_ready_8_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_8_s;$/;" n module:axi_adxcvr +up_ch_ready_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_ready_9,$/;" p module:axi_adxcvr +up_ch_ready_9_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_ready_9_s;$/;" n module:axi_adxcvr +up_ch_rst adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst;$/;" n module:axi_adxcvr +up_ch_rst adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_ch_rst,$/;" p module:axi_adxcvr_up +up_ch_rst_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_0,$/;" p module:axi_adxcvr +up_ch_rst_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_1,$/;" p module:axi_adxcvr +up_ch_rst_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_10,$/;" p module:axi_adxcvr +up_ch_rst_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_11,$/;" p module:axi_adxcvr +up_ch_rst_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_12,$/;" p module:axi_adxcvr +up_ch_rst_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_13,$/;" p module:axi_adxcvr +up_ch_rst_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_14,$/;" p module:axi_adxcvr +up_ch_rst_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_15,$/;" p module:axi_adxcvr +up_ch_rst_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_2,$/;" p module:axi_adxcvr +up_ch_rst_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_3,$/;" p module:axi_adxcvr +up_ch_rst_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_4,$/;" p module:axi_adxcvr +up_ch_rst_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_5,$/;" p module:axi_adxcvr +up_ch_rst_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_6,$/;" p module:axi_adxcvr +up_ch_rst_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_7,$/;" p module:axi_adxcvr +up_ch_rst_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_8,$/;" p module:axi_adxcvr +up_ch_rst_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_rst_9,$/;" p module:axi_adxcvr +up_ch_rst_done adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input up_ch_rst_done,$/;" p module:axi_adxcvr_up +up_ch_rst_done_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_0,$/;" p module:axi_adxcvr +up_ch_rst_done_0_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_0_s;$/;" n module:axi_adxcvr +up_ch_rst_done_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_1,$/;" p module:axi_adxcvr +up_ch_rst_done_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_10,$/;" p module:axi_adxcvr +up_ch_rst_done_10_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_10_s;$/;" n module:axi_adxcvr +up_ch_rst_done_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_11,$/;" p module:axi_adxcvr +up_ch_rst_done_11_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_11_s;$/;" n module:axi_adxcvr +up_ch_rst_done_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_12,$/;" p module:axi_adxcvr +up_ch_rst_done_12_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_12_s;$/;" n module:axi_adxcvr +up_ch_rst_done_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_13,$/;" p module:axi_adxcvr +up_ch_rst_done_13_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_13_s;$/;" n module:axi_adxcvr +up_ch_rst_done_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_14,$/;" p module:axi_adxcvr +up_ch_rst_done_14_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_14_s;$/;" n module:axi_adxcvr +up_ch_rst_done_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_15,$/;" p module:axi_adxcvr +up_ch_rst_done_15_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_15_s;$/;" n module:axi_adxcvr +up_ch_rst_done_1_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_1_s;$/;" n module:axi_adxcvr +up_ch_rst_done_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_2,$/;" p module:axi_adxcvr +up_ch_rst_done_2_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_2_s;$/;" n module:axi_adxcvr +up_ch_rst_done_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_3,$/;" p module:axi_adxcvr +up_ch_rst_done_3_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_3_s;$/;" n module:axi_adxcvr +up_ch_rst_done_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_4,$/;" p module:axi_adxcvr +up_ch_rst_done_4_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_4_s;$/;" n module:axi_adxcvr +up_ch_rst_done_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_5,$/;" p module:axi_adxcvr +up_ch_rst_done_5_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_5_s;$/;" n module:axi_adxcvr +up_ch_rst_done_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_6,$/;" p module:axi_adxcvr +up_ch_rst_done_6_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_6_s;$/;" n module:axi_adxcvr +up_ch_rst_done_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_7,$/;" p module:axi_adxcvr +up_ch_rst_done_7_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_7_s;$/;" n module:axi_adxcvr +up_ch_rst_done_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_8,$/;" p module:axi_adxcvr +up_ch_rst_done_8_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_8_s;$/;" n module:axi_adxcvr +up_ch_rst_done_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_ch_rst_done_9,$/;" p module:axi_adxcvr +up_ch_rst_done_9_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_rst_done_9_s;$/;" n module:axi_adxcvr +up_ch_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 7:0] up_ch_sel;$/;" n module:axi_adxcvr +up_ch_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 7:0] up_ch_sel,$/;" p module:axi_adxcvr_up +up_ch_sys_clk_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 1:0] up_ch_sys_clk_sel;$/;" n module:axi_adxcvr +up_ch_sys_clk_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 1:0] up_ch_sys_clk_sel,$/;" p module:axi_adxcvr_up +up_ch_sys_clk_sel_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_0,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_1,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_10,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_11,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_12,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_13,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_14,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_15,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_2,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_3,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_4,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_5,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_6,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_7,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_8,$/;" p module:axi_adxcvr +up_ch_sys_clk_sel_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 1:0] up_ch_sys_clk_sel_9,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 4:0] up_ch_tx_diffctrl;$/;" n module:axi_adxcvr +up_ch_tx_diffctrl adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 4:0] up_ch_tx_diffctrl,$/;" p module:axi_adxcvr_up +up_ch_tx_diffctrl_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_0,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_1,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_10,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_11,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_12,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_13,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_14,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_15,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_2,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_3,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_4,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_5,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_6,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_7,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_8,$/;" p module:axi_adxcvr +up_ch_tx_diffctrl_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_diffctrl_9,$/;" p module:axi_adxcvr +up_ch_tx_postcursor adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 4:0] up_ch_tx_postcursor;$/;" n module:axi_adxcvr +up_ch_tx_postcursor adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 4:0] up_ch_tx_postcursor,$/;" p module:axi_adxcvr_up +up_ch_tx_postcursor_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_0,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_1,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_10,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_11,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_12,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_13,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_14,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_15,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_2,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_3,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_4,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_5,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_6,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_7,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_8,$/;" p module:axi_adxcvr +up_ch_tx_postcursor_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_postcursor_9,$/;" p module:axi_adxcvr +up_ch_tx_precursor adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 4:0] up_ch_tx_precursor;$/;" n module:axi_adxcvr +up_ch_tx_precursor adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 4:0] up_ch_tx_precursor,$/;" p module:axi_adxcvr_up +up_ch_tx_precursor_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_0,$/;" p module:axi_adxcvr +up_ch_tx_precursor_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_1,$/;" p module:axi_adxcvr +up_ch_tx_precursor_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_10,$/;" p module:axi_adxcvr +up_ch_tx_precursor_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_11,$/;" p module:axi_adxcvr +up_ch_tx_precursor_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_12,$/;" p module:axi_adxcvr +up_ch_tx_precursor_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_13,$/;" p module:axi_adxcvr +up_ch_tx_precursor_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_14,$/;" p module:axi_adxcvr +up_ch_tx_precursor_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_15,$/;" p module:axi_adxcvr +up_ch_tx_precursor_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_2,$/;" p module:axi_adxcvr +up_ch_tx_precursor_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_3,$/;" p module:axi_adxcvr +up_ch_tx_precursor_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_4,$/;" p module:axi_adxcvr +up_ch_tx_precursor_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_5,$/;" p module:axi_adxcvr +up_ch_tx_precursor_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_6,$/;" p module:axi_adxcvr +up_ch_tx_precursor_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_7,$/;" p module:axi_adxcvr +up_ch_tx_precursor_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_8,$/;" p module:axi_adxcvr +up_ch_tx_precursor_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [ 4:0] up_ch_tx_precursor_9,$/;" p module:axi_adxcvr +up_ch_user_ready adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_user_ready;$/;" n module:axi_adxcvr +up_ch_user_ready adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_ch_user_ready,$/;" p module:axi_adxcvr_up +up_ch_user_ready_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_0,$/;" p module:axi_adxcvr +up_ch_user_ready_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_1,$/;" p module:axi_adxcvr +up_ch_user_ready_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_10,$/;" p module:axi_adxcvr +up_ch_user_ready_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_11,$/;" p module:axi_adxcvr +up_ch_user_ready_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_12,$/;" p module:axi_adxcvr +up_ch_user_ready_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_13,$/;" p module:axi_adxcvr +up_ch_user_ready_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_14,$/;" p module:axi_adxcvr +up_ch_user_ready_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_15,$/;" p module:axi_adxcvr +up_ch_user_ready_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_2,$/;" p module:axi_adxcvr +up_ch_user_ready_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_3,$/;" p module:axi_adxcvr +up_ch_user_ready_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_4,$/;" p module:axi_adxcvr +up_ch_user_ready_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_5,$/;" p module:axi_adxcvr +up_ch_user_ready_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_6,$/;" p module:axi_adxcvr +up_ch_user_ready_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_7,$/;" p module:axi_adxcvr +up_ch_user_ready_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_8,$/;" p module:axi_adxcvr +up_ch_user_ready_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_user_ready_9,$/;" p module:axi_adxcvr +up_ch_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_ch_wdata;$/;" n module:axi_adxcvr +up_ch_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [15:0] up_ch_wdata,$/;" p module:axi_adxcvr_up +up_ch_wdata_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_0,$/;" p module:axi_adxcvr +up_ch_wdata_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_1,$/;" p module:axi_adxcvr +up_ch_wdata_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_10,$/;" p module:axi_adxcvr +up_ch_wdata_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_11,$/;" p module:axi_adxcvr +up_ch_wdata_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_12,$/;" p module:axi_adxcvr +up_ch_wdata_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_13,$/;" p module:axi_adxcvr +up_ch_wdata_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_14,$/;" p module:axi_adxcvr +up_ch_wdata_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_15,$/;" p module:axi_adxcvr +up_ch_wdata_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_2,$/;" p module:axi_adxcvr +up_ch_wdata_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_3,$/;" p module:axi_adxcvr +up_ch_wdata_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_4,$/;" p module:axi_adxcvr +up_ch_wdata_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_5,$/;" p module:axi_adxcvr +up_ch_wdata_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_6,$/;" p module:axi_adxcvr +up_ch_wdata_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_7,$/;" p module:axi_adxcvr +up_ch_wdata_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_8,$/;" p module:axi_adxcvr +up_ch_wdata_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_ch_wdata_9,$/;" p module:axi_adxcvr +up_ch_wr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_ch_wr;$/;" n module:axi_adxcvr +up_ch_wr adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_ch_wr,$/;" p module:axi_adxcvr_up +up_ch_wr_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_0,$/;" p module:axi_adxcvr +up_ch_wr_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_1,$/;" p module:axi_adxcvr +up_ch_wr_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_10,$/;" p module:axi_adxcvr +up_ch_wr_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_11,$/;" p module:axi_adxcvr +up_ch_wr_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_12,$/;" p module:axi_adxcvr +up_ch_wr_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_13,$/;" p module:axi_adxcvr +up_ch_wr_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_14,$/;" p module:axi_adxcvr +up_ch_wr_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_15,$/;" p module:axi_adxcvr +up_ch_wr_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_2,$/;" p module:axi_adxcvr +up_ch_wr_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_3,$/;" p module:axi_adxcvr +up_ch_wr_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_4,$/;" p module:axi_adxcvr +up_ch_wr_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_5,$/;" p module:axi_adxcvr +up_ch_wr_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_6,$/;" p module:axi_adxcvr +up_ch_wr_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_7,$/;" p module:axi_adxcvr +up_ch_wr_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_8,$/;" p module:axi_adxcvr +up_ch_wr_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_ch_wr_9,$/;" p module:axi_adxcvr +up_clear_tl adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg up_clear_tl = 1'b0;$/;" r module:axi_dmac_regmap_request +up_clip_max adi_library/common/up_hdmi_tx.v /^ reg [23:0] up_clip_max;$/;" r module:up_hdmi_tx +up_clip_min adi_library/common/up_hdmi_tx.v /^ reg [23:0] up_clip_min;$/;" r module:up_hdmi_tx +up_clk adi_library/common/ad_pps_receiver.v /^ input up_clk,$/;" p module:ad_pps_receiver +up_clk adi_library/common/up_adc_channel.v /^ input up_clk,$/;" p module:up_adc_channel +up_clk adi_library/common/up_adc_common.v /^ input up_clk,$/;" p module:up_adc_common +up_clk adi_library/common/up_axi.v /^ input up_clk,$/;" p module:up_axi +up_clk adi_library/common/up_clkgen.v /^ input up_clk,$/;" p module:up_clkgen +up_clk adi_library/common/up_clock_mon.v /^ input up_clk,$/;" p module:up_clock_mon +up_clk adi_library/common/up_dac_channel.v /^ input up_clk,$/;" p module:up_dac_channel +up_clk adi_library/common/up_dac_common.v /^ input up_clk,$/;" p module:up_dac_common +up_clk adi_library/common/up_delay_cntrl.v /^ input up_clk,$/;" p module:up_delay_cntrl +up_clk adi_library/common/up_hdmi_rx.v /^ input up_clk,$/;" p module:up_hdmi_rx +up_clk adi_library/common/up_hdmi_tx.v /^ input up_clk,$/;" p module:up_hdmi_tx +up_clk adi_library/common/up_pmod.v /^ input up_clk,$/;" p module:up_pmod +up_clk adi_library/common/up_tdd_cntrl.v /^ input up_clk,$/;" p module:up_tdd_cntrl +up_clk adi_library/common/up_xfer_cntrl.v /^ input up_clk,$/;" p module:up_xfer_cntrl +up_clk adi_library/common/up_xfer_status.v /^ input up_clk,$/;" p module:up_xfer_status +up_clk adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input up_clk,$/;" p module:axi_spi_engine +up_clk adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_clk;$/;" n module:axi_adxcvr +up_clk adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input up_clk,$/;" p module:axi_adxcvr_es +up_clk adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ input up_clk,$/;" p module:axi_adxcvr_mdrp +up_clk adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ input up_clk,$/;" p module:axi_adxcvr_mstatus +up_clk adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input up_clk,$/;" p module:axi_adxcvr_up +up_clk adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ wire up_clk;$/;" n module:axi_xcvrlb +up_clk adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ input up_clk,$/;" p module:axi_xcvrlb_1 +up_clk adi_library/xilinx/common/ad_data_in.v /^ input up_clk,$/;" p module:ad_data_in +up_clk adi_library/xilinx/common/ad_data_out.v /^ input up_clk,$/;" p module:ad_data_out +up_clk adi_library/xilinx/common/ad_mmcm_drp.v /^ input up_clk,$/;" p module:ad_mmcm_drp +up_clk adi_library/xilinx/common/ad_serdes_clk.v /^ input up_clk,$/;" p module:ad_serdes_clk +up_clk adi_library/xilinx/common/ad_serdes_in.v /^ input up_clk,$/;" p module:ad_serdes_in +up_clk adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_clk,$/;" p module:util_adxcvr +up_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_clk,$/;" p module:util_adxcvr_xch +up_clk adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ input up_clk,$/;" p module:util_adxcvr_xcm +up_clk hdl/up_axi.v /^ input up_clk,$/;" p module:up_axi +up_clk_count_s adi_library/common/up_hdmi_rx.v /^ wire [31:0] up_clk_count_s;$/;" n module:up_hdmi_rx +up_clk_sel adi_library/common/up_clkgen.v /^ reg up_clk_sel = 'd0;$/;" r module:up_clkgen +up_clkgen adi_library/common/up_clkgen.v /^module up_clkgen #($/;" m +up_clock_mon adi_library/common/up_clock_mon.v /^module up_clock_mon #($/;" m +up_cm_addr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [11:0] up_cm_addr;$/;" n module:axi_adxcvr +up_cm_addr adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [11:0] up_cm_addr,$/;" p module:axi_adxcvr_up +up_cm_addr adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ input [11:0] up_cm_addr,$/;" p module:util_adxcvr_xcm +up_cm_addr_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_cm_addr_0,$/;" p module:axi_adxcvr +up_cm_addr_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_cm_addr_0,$/;" p module:util_adxcvr +up_cm_addr_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_cm_addr_12,$/;" p module:axi_adxcvr +up_cm_addr_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_cm_addr_12,$/;" p module:util_adxcvr +up_cm_addr_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_cm_addr_4,$/;" p module:axi_adxcvr +up_cm_addr_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_cm_addr_4,$/;" p module:util_adxcvr +up_cm_addr_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_cm_addr_8,$/;" p module:axi_adxcvr +up_cm_addr_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_cm_addr_8,$/;" p module:util_adxcvr +up_cm_enb adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_cm_enb;$/;" n module:axi_adxcvr +up_cm_enb adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_cm_enb,$/;" p module:axi_adxcvr_up +up_cm_enb adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ input up_cm_enb,$/;" p module:util_adxcvr_xcm +up_cm_enb_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_cm_enb_0,$/;" p module:axi_adxcvr +up_cm_enb_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cm_enb_0,$/;" p module:util_adxcvr +up_cm_enb_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_cm_enb_12,$/;" p module:axi_adxcvr +up_cm_enb_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cm_enb_12,$/;" p module:util_adxcvr +up_cm_enb_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_cm_enb_4,$/;" p module:axi_adxcvr +up_cm_enb_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cm_enb_4,$/;" p module:util_adxcvr +up_cm_enb_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_cm_enb_8,$/;" p module:axi_adxcvr +up_cm_enb_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cm_enb_8,$/;" p module:util_adxcvr +up_cm_rdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input [15:0] up_cm_rdata,$/;" p module:axi_adxcvr_up +up_cm_rdata adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ output [15:0] up_cm_rdata,$/;" p module:util_adxcvr_xcm +up_cm_rdata_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_cm_rdata_0,$/;" p module:axi_adxcvr +up_cm_rdata_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_cm_rdata_0,$/;" p module:util_adxcvr +up_cm_rdata_0_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_cm_rdata_0_s;$/;" n module:axi_adxcvr +up_cm_rdata_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_cm_rdata_12,$/;" p module:axi_adxcvr +up_cm_rdata_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_cm_rdata_12,$/;" p module:util_adxcvr +up_cm_rdata_12_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_cm_rdata_12_s;$/;" n module:axi_adxcvr +up_cm_rdata_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_cm_rdata_4,$/;" p module:axi_adxcvr +up_cm_rdata_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_cm_rdata_4,$/;" p module:util_adxcvr +up_cm_rdata_4_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_cm_rdata_4_s;$/;" n module:axi_adxcvr +up_cm_rdata_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_cm_rdata_8,$/;" p module:axi_adxcvr +up_cm_rdata_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_cm_rdata_8,$/;" p module:util_adxcvr +up_cm_rdata_8_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_cm_rdata_8_s;$/;" n module:axi_adxcvr +up_cm_ready adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input up_cm_ready,$/;" p module:axi_adxcvr_up +up_cm_ready adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ output up_cm_ready);$/;" p module:util_adxcvr_xcm +up_cm_ready_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_cm_ready_0,$/;" p module:axi_adxcvr +up_cm_ready_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_cm_ready_0,$/;" p module:util_adxcvr +up_cm_ready_0_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_cm_ready_0_s;$/;" n module:axi_adxcvr +up_cm_ready_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_cm_ready_12,$/;" p module:axi_adxcvr +up_cm_ready_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_cm_ready_12,$/;" p module:util_adxcvr +up_cm_ready_12_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_cm_ready_12_s;$/;" n module:axi_adxcvr +up_cm_ready_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_cm_ready_4,$/;" p module:axi_adxcvr +up_cm_ready_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_cm_ready_4,$/;" p module:util_adxcvr +up_cm_ready_4_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_cm_ready_4_s;$/;" n module:axi_adxcvr +up_cm_ready_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_cm_ready_8,$/;" p module:axi_adxcvr +up_cm_ready_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_cm_ready_8,$/;" p module:util_adxcvr +up_cm_ready_8_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_cm_ready_8_s;$/;" n module:axi_adxcvr +up_cm_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 7:0] up_cm_sel;$/;" n module:axi_adxcvr +up_cm_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 7:0] up_cm_sel,$/;" p module:axi_adxcvr_up +up_cm_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_cm_wdata;$/;" n module:axi_adxcvr +up_cm_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [15:0] up_cm_wdata,$/;" p module:axi_adxcvr_up +up_cm_wdata adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ input [15:0] up_cm_wdata,$/;" p module:util_adxcvr_xcm +up_cm_wdata_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_cm_wdata_0,$/;" p module:axi_adxcvr +up_cm_wdata_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_cm_wdata_0,$/;" p module:util_adxcvr +up_cm_wdata_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_cm_wdata_12,$/;" p module:axi_adxcvr +up_cm_wdata_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_cm_wdata_12,$/;" p module:util_adxcvr +up_cm_wdata_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_cm_wdata_4,$/;" p module:axi_adxcvr +up_cm_wdata_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_cm_wdata_4,$/;" p module:util_adxcvr +up_cm_wdata_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_cm_wdata_8,$/;" p module:axi_adxcvr +up_cm_wdata_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_cm_wdata_8,$/;" p module:util_adxcvr +up_cm_wr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_cm_wr;$/;" n module:axi_adxcvr +up_cm_wr adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_cm_wr,$/;" p module:axi_adxcvr_up +up_cm_wr adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ input up_cm_wr,$/;" p module:util_adxcvr_xcm +up_cm_wr_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_cm_wr_0,$/;" p module:axi_adxcvr +up_cm_wr_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cm_wr_0,$/;" p module:util_adxcvr +up_cm_wr_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_cm_wr_12,$/;" p module:axi_adxcvr +up_cm_wr_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cm_wr_12,$/;" p module:util_adxcvr +up_cm_wr_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_cm_wr_4,$/;" p module:axi_adxcvr +up_cm_wr_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cm_wr_4,$/;" p module:util_adxcvr +up_cm_wr_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_cm_wr_8,$/;" p module:axi_adxcvr +up_cm_wr_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cm_wr_8,$/;" p module:util_adxcvr +up_cntrl_xfer_done_s adi_library/common/up_adc_common.v /^ wire up_cntrl_xfer_done_s;$/;" n module:up_adc_common +up_const_rgb adi_library/common/up_hdmi_tx.v /^ reg [23:0] up_const_rgb = 'd0;$/;" r module:up_hdmi_tx +up_core_preset adi_library/common/up_adc_common.v /^ reg up_core_preset = 'd1;$/;" r module:up_adc_common +up_core_preset adi_library/common/up_dac_common.v /^ reg up_core_preset = 'd1;$/;" r module:up_dac_common +up_core_preset adi_library/common/up_hdmi_rx.v /^ reg up_core_preset = 'd0;$/;" r module:up_hdmi_rx +up_core_preset adi_library/common/up_hdmi_tx.v /^ reg up_core_preset;$/;" r module:up_hdmi_tx +up_count adi_library/common/up_clock_mon.v /^ reg [15:0] up_count = 'd1;$/;" r module:up_clock_mon +up_count_capture_s adi_library/common/up_clock_mon.v /^ wire up_count_capture_s;$/;" n module:up_clock_mon +up_count_run adi_library/common/up_clock_mon.v /^ reg up_count_run = 'd0;$/;" r module:up_clock_mon +up_count_running_m1 adi_library/common/up_clock_mon.v /^ reg up_count_running_m1 = 'd0;$/;" r module:up_clock_mon +up_count_running_m2 adi_library/common/up_clock_mon.v /^ reg up_count_running_m2 = 'd0;$/;" r module:up_clock_mon +up_count_running_m3 adi_library/common/up_clock_mon.v /^ reg up_count_running_m3 = 'd0;$/;" r module:up_clock_mon +up_cpll_rst adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_cpll_rst,$/;" p module:util_adxcvr_xch +up_cpll_rst_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_0,$/;" p module:util_adxcvr +up_cpll_rst_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_1,$/;" p module:util_adxcvr +up_cpll_rst_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_10,$/;" p module:util_adxcvr +up_cpll_rst_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_11,$/;" p module:util_adxcvr +up_cpll_rst_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_12,$/;" p module:util_adxcvr +up_cpll_rst_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_13,$/;" p module:util_adxcvr +up_cpll_rst_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_14,$/;" p module:util_adxcvr +up_cpll_rst_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_15,$/;" p module:util_adxcvr +up_cpll_rst_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_2,$/;" p module:util_adxcvr +up_cpll_rst_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_3,$/;" p module:util_adxcvr +up_cpll_rst_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_4,$/;" p module:util_adxcvr +up_cpll_rst_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_5,$/;" p module:util_adxcvr +up_cpll_rst_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_6,$/;" p module:util_adxcvr +up_cpll_rst_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_7,$/;" p module:util_adxcvr +up_cpll_rst_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_8,$/;" p module:util_adxcvr +up_cpll_rst_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_cpll_rst_9,$/;" p module:util_adxcvr +up_csc_bypass adi_library/common/up_hdmi_rx.v /^ reg up_csc_bypass = 'd0;$/;" r module:up_hdmi_rx +up_csc_bypass adi_library/common/up_hdmi_tx.v /^ reg up_csc_bypass = 'd0;$/;" r module:up_hdmi_tx +up_d_count adi_library/common/up_clock_mon.v /^ output reg [TOTAL_WIDTH-1:0] up_d_count,$/;" p module:up_clock_mon +up_dac_ce adi_library/common/up_dac_common.v /^ output up_dac_ce,$/;" p module:up_dac_common +up_dac_channel adi_library/common/up_dac_channel.v /^module up_dac_channel #($/;" m +up_dac_clk_count_s adi_library/common/up_dac_common.v /^ wire [31:0] up_dac_clk_count_s;$/;" n module:up_dac_common +up_dac_clk_enb adi_library/common/up_dac_common.v /^ reg up_dac_clk_enb = 'd0;$/;" r module:up_dac_common +up_dac_clk_enb_int adi_library/common/up_dac_common.v /^ reg up_dac_clk_enb_int = 'd0;$/;" r module:up_dac_common +up_dac_clksel adi_library/common/up_dac_common.v /^ reg up_dac_clksel = CLK_EDGE_SEL;$/;" r module:up_dac_common +up_dac_common adi_library/common/up_dac_common.v /^module up_dac_common #($/;" m +up_dac_data_sel adi_library/common/up_dac_channel.v /^ reg [ 3:0] up_dac_data_sel = 'd0;$/;" r module:up_dac_channel +up_dac_data_sel_m adi_library/common/up_dac_channel.v /^ reg [ 3:0] up_dac_data_sel_m = 'd0;$/;" r module:up_dac_channel +up_dac_datafmt adi_library/common/up_dac_common.v /^ reg up_dac_datafmt = 'd0;$/;" r module:up_dac_common +up_dac_datarate adi_library/common/up_dac_common.v /^ reg [15:0] up_dac_datarate = 'd0;$/;" r module:up_dac_common +up_dac_dds_incr_1 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_dds_incr_1 = 'd0;$/;" r module:up_dac_channel +up_dac_dds_incr_2 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_dds_incr_2 = 'd0;$/;" r module:up_dac_channel +up_dac_dds_init_1 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_dds_init_1 = 'd0;$/;" r module:up_dac_channel +up_dac_dds_init_2 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_dds_init_2 = 'd0;$/;" r module:up_dac_channel +up_dac_dds_scale_1 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_dds_scale_1 = 'd0;$/;" r module:up_dac_channel +up_dac_dds_scale_2 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_dds_scale_2 = 'd0;$/;" r module:up_dac_channel +up_dac_dds_scale_tc_1 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_dds_scale_tc_1 = 'd0;$/;" r module:up_dac_channel +up_dac_dds_scale_tc_2 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_dds_scale_tc_2 = 'd0;$/;" r module:up_dac_channel +up_dac_frame adi_library/common/up_dac_common.v /^ reg up_dac_frame = 'd0;$/;" r module:up_dac_common +up_dac_gpio_in adi_library/common/up_dac_common.v /^ input [31:0] up_dac_gpio_in,$/;" p module:up_dac_common +up_dac_gpio_out adi_library/common/up_dac_common.v /^ output [31:0] up_dac_gpio_out,$/;" p module:up_dac_common +up_dac_gpio_out_int adi_library/common/up_dac_common.v /^ reg [31:0] up_dac_gpio_out_int = 'd0;$/;" r module:up_dac_common +up_dac_iq_mode adi_library/common/up_dac_channel.v /^ reg [ 1:0] up_dac_iq_mode = 'd0;$/;" r module:up_dac_channel +up_dac_iqcor_coeff_1 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_iqcor_coeff_1 = 'd0;$/;" r module:up_dac_channel +up_dac_iqcor_coeff_2 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_iqcor_coeff_2 = 'd0;$/;" r module:up_dac_channel +up_dac_iqcor_coeff_tc_1 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_iqcor_coeff_tc_1 = 'd0;$/;" r module:up_dac_channel +up_dac_iqcor_coeff_tc_2 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_iqcor_coeff_tc_2 = 'd0;$/;" r module:up_dac_channel +up_dac_iqcor_enb adi_library/common/up_dac_channel.v /^ reg up_dac_iqcor_enb = 'd0;$/;" r module:up_dac_channel +up_dac_lb_enb adi_library/common/up_dac_channel.v /^ reg up_dac_lb_enb = 'd0;$/;" r module:up_dac_channel +up_dac_num_lanes adi_library/common/up_dac_common.v /^ reg [4:0] up_dac_num_lanes = 'd0;$/;" r module:up_dac_common +up_dac_par_enb adi_library/common/up_dac_common.v /^ reg up_dac_par_enb = 'd0;$/;" r module:up_dac_common +up_dac_par_type adi_library/common/up_dac_common.v /^ reg up_dac_par_type = 'd0;$/;" r module:up_dac_common +up_dac_pat_data_1 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_pat_data_1 = 'd0;$/;" r module:up_dac_channel +up_dac_pat_data_2 adi_library/common/up_dac_channel.v /^ reg [15:0] up_dac_pat_data_2 = 'd0;$/;" r module:up_dac_channel +up_dac_pn_enb adi_library/common/up_dac_channel.v /^ reg up_dac_pn_enb = 'd0;$/;" r module:up_dac_channel +up_dac_r1_mode adi_library/common/up_dac_common.v /^ output reg up_dac_r1_mode = 'd0,$/;" p module:up_dac_common +up_dac_sdr_ddr_n adi_library/common/up_dac_common.v /^ reg up_dac_sdr_ddr_n = 'd0;$/;" r module:up_dac_common +up_dac_sync adi_library/common/up_dac_common.v /^ reg up_dac_sync = 'd0;$/;" r module:up_dac_common +up_daddr adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [31:0] up_daddr = 'd0;$/;" r module:axi_adxcvr_es +up_data adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [15:0] up_data = 'd0;$/;" r module:axi_adxcvr_es +up_data_cntrl adi_library/common/up_xfer_cntrl.v /^ input [(DATA_WIDTH-1):0] up_data_cntrl,$/;" p module:up_xfer_cntrl +up_data_status adi_library/common/up_xfer_status.v /^ output [(DATA_WIDTH-1):0] up_data_status,$/;" p module:up_xfer_status +up_data_status_int adi_library/common/up_xfer_status.v /^ reg [(DATA_WIDTH-1):0] up_data_status_int = 'd0;$/;" r module:up_xfer_status +up_delay_cntrl adi_library/common/up_delay_cntrl.v /^module up_delay_cntrl #($/;" m +up_dinit_s adi_library/common/up_delay_cntrl.v /^ wire [(DATA_WIDTH-1):0] up_dinit_s;$/;" n module:up_delay_cntrl +up_dinitdata_s adi_library/common/up_delay_cntrl.v /^ wire [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dinitdata_s;$/;" n module:up_delay_cntrl +up_dld adi_library/common/up_delay_cntrl.v /^ output [(DATA_WIDTH-1):0] up_dld,$/;" p module:up_delay_cntrl +up_dld adi_library/xilinx/common/ad_data_in.v /^ input up_dld,$/;" p module:ad_data_in +up_dld adi_library/xilinx/common/ad_data_out.v /^ input up_dld,$/;" p module:ad_data_out +up_dld adi_library/xilinx/common/ad_serdes_in.v /^ input [(DATA_WIDTH-1):0] up_dld,$/;" p module:ad_serdes_in +up_dld_int adi_library/common/up_delay_cntrl.v /^ reg [(DATA_WIDTH-1):0] up_dld_int = 'd0;$/;" r module:up_delay_cntrl +up_dld_s adi_library/common/up_delay_cntrl.v /^ wire [(DATA_WIDTH-1):0] up_dld_s;$/;" n module:up_delay_cntrl +up_dlocked adi_library/common/up_delay_cntrl.v /^ reg up_dlocked = 'd0;$/;" r module:up_delay_cntrl +up_dlocked_m1 adi_library/common/up_delay_cntrl.v /^ reg up_dlocked_m1 = 'd0;$/;" r module:up_delay_cntrl +up_dlocked_m2 adi_library/common/up_delay_cntrl.v /^ reg up_dlocked_m2 = 'd0;$/;" r module:up_delay_cntrl +up_dlocked_m3 adi_library/common/up_delay_cntrl.v /^ reg up_dlocked_m3 = 'd0;$/;" r module:up_delay_cntrl +up_dma_cyclic adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg up_dma_cyclic = DMA_CYCLIC ? 1'b1 : 1'b0;$/;" r module:axi_dmac_regmap_request +up_dma_dest_address adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00;$/;" r module:axi_dmac_regmap_request +up_dma_dest_stride adi_library/axi_dmac/axi_dmac_regmap_request.v /^ reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;$/;" r module:axi_dmac_regmap_request +up_dma_enable_tlen_reporting adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg up_dma_enable_tlen_reporting = 1'b0;$/;" r module:axi_dmac_regmap_request +up_dma_last adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg up_dma_last = 1'b1;$/;" r module:axi_dmac_regmap_request +up_dma_ovf adi_library/common/up_hdmi_rx.v /^ reg up_dma_ovf = 'd0;$/;" r module:up_hdmi_rx +up_dma_ovf_s adi_library/common/up_hdmi_rx.v /^ wire up_dma_ovf_s;$/;" n module:up_hdmi_rx +up_dma_req_dest_address adi_library/axi_dmac/axi_dmac.v /^wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_req_dest_address;$/;" n module:axi_dmac +up_dma_req_dest_stride adi_library/axi_dmac/axi_dmac.v /^wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_dest_stride;$/;" n module:axi_dmac +up_dma_req_last adi_library/axi_dmac/axi_dmac.v /^wire up_dma_req_last;$/;" n module:axi_dmac +up_dma_req_ready adi_library/axi_dmac/axi_dmac.v /^wire up_dma_req_ready;$/;" n module:axi_dmac +up_dma_req_ready adi_library/axi_dmac/axi_dmac_regmap_request.v /^wire up_dma_req_ready;$/;" n module:axi_dmac_regmap_request +up_dma_req_src_address adi_library/axi_dmac/axi_dmac.v /^wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_req_src_address;$/;" n module:axi_dmac +up_dma_req_src_stride adi_library/axi_dmac/axi_dmac.v /^wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_src_stride;$/;" n module:axi_dmac +up_dma_req_sync_transfer_start adi_library/axi_dmac/axi_dmac.v /^wire up_dma_req_sync_transfer_start;$/;" n module:axi_dmac +up_dma_req_valid adi_library/axi_dmac/axi_dmac.v /^wire up_dma_req_valid;$/;" n module:axi_dmac +up_dma_req_valid adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg up_dma_req_valid = 1'b0;$/;" r module:axi_dmac_regmap_request +up_dma_req_x_length adi_library/axi_dmac/axi_dmac.v /^wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_x_length;$/;" n module:axi_dmac +up_dma_req_y_length adi_library/axi_dmac/axi_dmac.v /^wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_y_length;$/;" n module:axi_dmac +up_dma_src_address adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00;$/;" r module:axi_dmac_regmap_request +up_dma_src_stride adi_library/axi_dmac/axi_dmac_regmap_request.v /^ reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;$/;" r module:axi_dmac_regmap_request +up_dma_unf adi_library/common/up_hdmi_rx.v /^ reg up_dma_unf = 'd0;$/;" r module:up_hdmi_rx +up_dma_unf_s adi_library/common/up_hdmi_rx.v /^ wire up_dma_unf_s;$/;" n module:up_hdmi_rx +up_dma_x_length adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = {DMA_LENGTH_ALIGN{1'b1}};$/;" r module:axi_dmac_regmap_request +up_dma_y_length adi_library/axi_dmac/axi_dmac_regmap_request.v /^ reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;$/;" r module:axi_dmac_regmap_request +up_drdata adi_library/common/up_delay_cntrl.v /^ input [((DATA_WIDTH*DRP_WIDTH)-1):0] up_drdata,$/;" p module:up_delay_cntrl +up_drdata adi_library/xilinx/common/ad_data_in.v /^ output [ 4:0] up_drdata,$/;" p module:ad_data_in +up_drdata adi_library/xilinx/common/ad_data_out.v /^ output [ 4:0] up_drdata,$/;" p module:ad_data_out +up_drdata adi_library/xilinx/common/ad_serdes_in.v /^ output [((DATA_WIDTH*DRP_WIDTH)-1):0] up_drdata,$/;" p module:ad_serdes_in +up_drdata0_s adi_library/common/up_delay_cntrl.v /^ wire [(DATA_WIDTH-1):0] up_drdata0_s;$/;" n module:up_delay_cntrl +up_drdata1_s adi_library/common/up_delay_cntrl.v /^ wire [(DATA_WIDTH-1):0] up_drdata1_s;$/;" n module:up_delay_cntrl +up_drdata2_s adi_library/common/up_delay_cntrl.v /^ wire [(DATA_WIDTH-1):0] up_drdata2_s;$/;" n module:up_delay_cntrl +up_drdata3_s adi_library/common/up_delay_cntrl.v /^ wire [(DATA_WIDTH-1):0] up_drdata3_s;$/;" n module:up_delay_cntrl +up_drdata4_s adi_library/common/up_delay_cntrl.v /^ wire [(DATA_WIDTH-1):0] up_drdata4_s;$/;" n module:up_delay_cntrl +up_drdata_s adi_library/xilinx/common/ad_data_in.v /^ wire [ 8:0] up_drdata_s;$/;" n module:ad_data_in +up_drp_addr adi_library/common/up_adc_common.v /^ output [11:0] up_drp_addr,$/;" p module:up_adc_common +up_drp_addr adi_library/common/up_clkgen.v /^ output reg [11:0] up_drp_addr,$/;" p module:up_clkgen +up_drp_addr adi_library/common/up_dac_common.v /^ output [11:0] up_drp_addr,$/;" p module:up_dac_common +up_drp_addr adi_library/xilinx/common/ad_mmcm_drp.v /^ input [11:0] up_drp_addr,$/;" p module:ad_mmcm_drp +up_drp_addr adi_library/xilinx/common/ad_serdes_clk.v /^ input [11:0] up_drp_addr,$/;" p module:ad_serdes_clk +up_drp_addr_int adi_library/common/up_adc_common.v /^ reg [11:0] up_drp_addr_int = 'd0;$/;" r module:up_adc_common +up_drp_addr_int adi_library/common/up_dac_common.v /^ reg [11:0] up_drp_addr_int = 'd0;$/;" r module:up_dac_common +up_drp_locked adi_library/common/up_adc_common.v /^ input up_drp_locked,$/;" p module:up_adc_common +up_drp_locked adi_library/common/up_clkgen.v /^ input up_drp_locked,$/;" p module:up_clkgen +up_drp_locked adi_library/common/up_dac_common.v /^ input up_drp_locked,$/;" p module:up_dac_common +up_drp_locked adi_library/xilinx/common/ad_mmcm_drp.v /^ output reg up_drp_locked);$/;" p module:ad_mmcm_drp +up_drp_locked adi_library/xilinx/common/ad_serdes_clk.v /^ output up_drp_locked);$/;" p module:ad_serdes_clk +up_drp_locked_m1 adi_library/xilinx/common/ad_mmcm_drp.v /^ reg up_drp_locked_m1 = 'd0;$/;" r module:ad_mmcm_drp +up_drp_rdata adi_library/common/up_adc_common.v /^ input [31:0] up_drp_rdata,$/;" p module:up_adc_common +up_drp_rdata adi_library/common/up_clkgen.v /^ input [15:0] up_drp_rdata,$/;" p module:up_clkgen +up_drp_rdata adi_library/common/up_dac_common.v /^ input [31:0] up_drp_rdata,$/;" p module:up_dac_common +up_drp_rdata adi_library/xilinx/common/ad_mmcm_drp.v /^ output reg [15:0] up_drp_rdata,$/;" p module:ad_mmcm_drp +up_drp_rdata adi_library/xilinx/common/ad_serdes_clk.v /^ output [31:0] up_drp_rdata,$/;" p module:ad_serdes_clk +up_drp_rdata_hold adi_library/common/up_clkgen.v /^ reg [15:0] up_drp_rdata_hold = 'd0;$/;" r module:up_clkgen +up_drp_rdata_hold_int adi_library/common/up_adc_common.v /^ reg [31:0] up_drp_rdata_hold_int = 'd0;$/;" r module:up_adc_common +up_drp_rdata_hold_int adi_library/common/up_dac_common.v /^ reg [31:0] up_drp_rdata_hold_int = 'd0;$/;" r module:up_dac_common +up_drp_rdata_hold_s adi_library/common/up_adc_common.v /^ wire [31:0] up_drp_rdata_hold_s;$/;" n module:up_adc_common +up_drp_rdata_hold_s adi_library/common/up_dac_common.v /^ wire [31:0] up_drp_rdata_hold_s;$/;" n module:up_dac_common +up_drp_rdata_s adi_library/xilinx/common/ad_mmcm_drp.v /^ wire [15:0] up_drp_rdata_s;$/;" n module:ad_mmcm_drp +up_drp_ready adi_library/common/up_adc_common.v /^ input up_drp_ready,$/;" p module:up_adc_common +up_drp_ready adi_library/common/up_clkgen.v /^ input up_drp_ready,$/;" p module:up_clkgen +up_drp_ready adi_library/common/up_dac_common.v /^ input up_drp_ready,$/;" p module:up_dac_common +up_drp_ready adi_library/xilinx/common/ad_mmcm_drp.v /^ output reg up_drp_ready,$/;" p module:ad_mmcm_drp +up_drp_ready adi_library/xilinx/common/ad_serdes_clk.v /^ output up_drp_ready,$/;" p module:ad_serdes_clk +up_drp_ready_s adi_library/xilinx/common/ad_mmcm_drp.v /^ wire up_drp_ready_s;$/;" n module:ad_mmcm_drp +up_drp_rwn adi_library/common/up_clkgen.v /^ reg up_drp_rwn = 'd0;$/;" r module:up_clkgen +up_drp_rwn_int adi_library/common/up_adc_common.v /^ reg up_drp_rwn_int = 'd0;$/;" r module:up_adc_common +up_drp_rwn_int adi_library/common/up_dac_common.v /^ reg up_drp_rwn_int = 'd0;$/;" r module:up_dac_common +up_drp_rwn_s adi_library/common/up_adc_common.v /^ wire up_drp_rwn_s;$/;" n module:up_adc_common +up_drp_rwn_s adi_library/common/up_dac_common.v /^ wire up_drp_rwn_s;$/;" n module:up_dac_common +up_drp_sel adi_library/common/up_adc_common.v /^ output up_drp_sel,$/;" p module:up_adc_common +up_drp_sel adi_library/common/up_clkgen.v /^ output reg up_drp_sel,$/;" p module:up_clkgen +up_drp_sel adi_library/common/up_dac_common.v /^ output up_drp_sel,$/;" p module:up_dac_common +up_drp_sel adi_library/xilinx/common/ad_mmcm_drp.v /^ input up_drp_sel,$/;" p module:ad_mmcm_drp +up_drp_sel adi_library/xilinx/common/ad_serdes_clk.v /^ input up_drp_sel,$/;" p module:ad_serdes_clk +up_drp_sel_int adi_library/common/up_adc_common.v /^ reg up_drp_sel_int = 'd0;$/;" r module:up_adc_common +up_drp_sel_int adi_library/common/up_dac_common.v /^ reg up_drp_sel_int = 'd0;$/;" r module:up_dac_common +up_drp_status adi_library/common/up_clkgen.v /^ reg up_drp_status = 'd0;$/;" r module:up_clkgen +up_drp_status_int adi_library/common/up_adc_common.v /^ reg up_drp_status_int = 'd0;$/;" r module:up_adc_common +up_drp_status_int adi_library/common/up_dac_common.v /^ reg up_drp_status_int = 'd0;$/;" r module:up_dac_common +up_drp_status_s adi_library/common/up_adc_common.v /^ wire up_drp_status_s;$/;" n module:up_adc_common +up_drp_status_s adi_library/common/up_dac_common.v /^ wire up_drp_status_s;$/;" n module:up_dac_common +up_drp_wdata adi_library/common/up_adc_common.v /^ output [31:0] up_drp_wdata,$/;" p module:up_adc_common +up_drp_wdata adi_library/common/up_clkgen.v /^ output reg [15:0] up_drp_wdata,$/;" p module:up_clkgen +up_drp_wdata adi_library/common/up_dac_common.v /^ output [31:0] up_drp_wdata,$/;" p module:up_dac_common +up_drp_wdata adi_library/xilinx/common/ad_mmcm_drp.v /^ input [15:0] up_drp_wdata,$/;" p module:ad_mmcm_drp +up_drp_wdata adi_library/xilinx/common/ad_serdes_clk.v /^ input [31:0] up_drp_wdata,$/;" p module:ad_serdes_clk +up_drp_wdata_int adi_library/common/up_adc_common.v /^ reg [31:0] up_drp_wdata_int = 'd0;$/;" r module:up_adc_common +up_drp_wdata_int adi_library/common/up_dac_common.v /^ reg [31:0] up_drp_wdata_int = 'd0;$/;" r module:up_dac_common +up_drp_wr adi_library/common/up_adc_common.v /^ output up_drp_wr,$/;" p module:up_adc_common +up_drp_wr adi_library/common/up_clkgen.v /^ output reg up_drp_wr,$/;" p module:up_clkgen +up_drp_wr adi_library/common/up_dac_common.v /^ output up_drp_wr,$/;" p module:up_dac_common +up_drp_wr adi_library/xilinx/common/ad_mmcm_drp.v /^ input up_drp_wr,$/;" p module:ad_mmcm_drp +up_drp_wr adi_library/xilinx/common/ad_serdes_clk.v /^ input up_drp_wr,$/;" p module:ad_serdes_clk +up_drp_wr_int adi_library/common/up_adc_common.v /^ reg up_drp_wr_int = 'd0;$/;" r module:up_adc_common +up_drp_wr_int adi_library/common/up_dac_common.v /^ reg up_drp_wr_int = 'd0;$/;" r module:up_dac_common +up_dwdata adi_library/common/up_delay_cntrl.v /^ output [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata,$/;" p module:up_delay_cntrl +up_dwdata adi_library/xilinx/common/ad_data_in.v /^ input [ 4:0] up_dwdata,$/;" p module:ad_data_in +up_dwdata adi_library/xilinx/common/ad_data_out.v /^ input [ 4:0] up_dwdata,$/;" p module:ad_data_out +up_dwdata adi_library/xilinx/common/ad_serdes_in.v /^ input [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata,$/;" p module:ad_serdes_in +up_dwdata_int adi_library/common/up_delay_cntrl.v /^ reg [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata_int = 'd0;$/;" r module:up_delay_cntrl +up_dwdata_s adi_library/common/up_delay_cntrl.v /^ wire [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata_s;$/;" n module:up_delay_cntrl +up_edata adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [15:0] up_edata = 'd0;$/;" r module:axi_adxcvr_es +up_edge_sel adi_library/common/up_hdmi_rx.v /^ reg up_edge_sel = 'd0;$/;" r module:up_hdmi_rx +up_enb adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg up_enb = 'd0;$/;" r module:axi_adxcvr_es +up_enb adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ input up_enb,$/;" p module:axi_adxcvr_mdrp +up_enb_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg up_enb_int = 'd0;$/;" r module:util_adxcvr_xch +up_enb_int adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ reg up_enb_int = 'd0;$/;" r module:util_adxcvr_xcm +up_enb_out adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ output up_enb_out,$/;" p module:axi_adxcvr_mdrp +up_eos_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ wire up_eos_s;$/;" n module:axi_adxcvr_es +up_eot adi_library/axi_dmac/axi_dmac_regmap.v /^wire up_eot; \/\/ Asserted for one cycle when a transfer has been completed$/;" n module:axi_dmac_regmap +up_eot adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output up_eot,$/;" p module:axi_dmac_regmap_request +up_es_ack adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ack;$/;" n module:axi_adxcvr +up_es_ack adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output up_es_ack,$/;" p module:axi_adxcvr_es +up_es_ack adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input up_es_ack,$/;" p module:axi_adxcvr_up +up_es_addr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [11:0] up_es_addr;$/;" n module:axi_adxcvr +up_es_addr adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output [11:0] up_es_addr,$/;" p module:axi_adxcvr_es +up_es_addr adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [11:0] up_es_addr,$/;" p module:util_adxcvr_xch +up_es_addr_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_0,$/;" p module:axi_adxcvr +up_es_addr_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_0,$/;" p module:util_adxcvr +up_es_addr_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_1,$/;" p module:axi_adxcvr +up_es_addr_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_1,$/;" p module:util_adxcvr +up_es_addr_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_10,$/;" p module:axi_adxcvr +up_es_addr_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_10,$/;" p module:util_adxcvr +up_es_addr_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_11,$/;" p module:axi_adxcvr +up_es_addr_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_11,$/;" p module:util_adxcvr +up_es_addr_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_12,$/;" p module:axi_adxcvr +up_es_addr_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_12,$/;" p module:util_adxcvr +up_es_addr_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_13,$/;" p module:axi_adxcvr +up_es_addr_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_13,$/;" p module:util_adxcvr +up_es_addr_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_14,$/;" p module:axi_adxcvr +up_es_addr_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_14,$/;" p module:util_adxcvr +up_es_addr_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_15,$/;" p module:axi_adxcvr +up_es_addr_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_15,$/;" p module:util_adxcvr +up_es_addr_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_2,$/;" p module:axi_adxcvr +up_es_addr_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_2,$/;" p module:util_adxcvr +up_es_addr_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_3,$/;" p module:axi_adxcvr +up_es_addr_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_3,$/;" p module:util_adxcvr +up_es_addr_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_4,$/;" p module:axi_adxcvr +up_es_addr_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_4,$/;" p module:util_adxcvr +up_es_addr_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_5,$/;" p module:axi_adxcvr +up_es_addr_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_5,$/;" p module:util_adxcvr +up_es_addr_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_6,$/;" p module:axi_adxcvr +up_es_addr_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_6,$/;" p module:util_adxcvr +up_es_addr_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_7,$/;" p module:axi_adxcvr +up_es_addr_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_7,$/;" p module:util_adxcvr +up_es_addr_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_8,$/;" p module:axi_adxcvr +up_es_addr_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_8,$/;" p module:util_adxcvr +up_es_addr_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [11:0] up_es_addr_9,$/;" p module:axi_adxcvr +up_es_addr_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_es_addr_9,$/;" p module:util_adxcvr +up_es_enb adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_enb;$/;" n module:axi_adxcvr +up_es_enb adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output up_es_enb,$/;" p module:axi_adxcvr_es +up_es_enb adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_es_enb,$/;" p module:util_adxcvr_xch +up_es_enb_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_0,$/;" p module:axi_adxcvr +up_es_enb_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_0,$/;" p module:util_adxcvr +up_es_enb_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_1,$/;" p module:axi_adxcvr +up_es_enb_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_1,$/;" p module:util_adxcvr +up_es_enb_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_10,$/;" p module:axi_adxcvr +up_es_enb_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_10,$/;" p module:util_adxcvr +up_es_enb_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_11,$/;" p module:axi_adxcvr +up_es_enb_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_11,$/;" p module:util_adxcvr +up_es_enb_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_12,$/;" p module:axi_adxcvr +up_es_enb_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_12,$/;" p module:util_adxcvr +up_es_enb_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_13,$/;" p module:axi_adxcvr +up_es_enb_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_13,$/;" p module:util_adxcvr +up_es_enb_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_14,$/;" p module:axi_adxcvr +up_es_enb_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_14,$/;" p module:util_adxcvr +up_es_enb_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_15,$/;" p module:axi_adxcvr +up_es_enb_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_15,$/;" p module:util_adxcvr +up_es_enb_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_2,$/;" p module:axi_adxcvr +up_es_enb_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_2,$/;" p module:util_adxcvr +up_es_enb_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_3,$/;" p module:axi_adxcvr +up_es_enb_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_3,$/;" p module:util_adxcvr +up_es_enb_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_4,$/;" p module:axi_adxcvr +up_es_enb_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_4,$/;" p module:util_adxcvr +up_es_enb_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_5,$/;" p module:axi_adxcvr +up_es_enb_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_5,$/;" p module:util_adxcvr +up_es_enb_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_6,$/;" p module:axi_adxcvr +up_es_enb_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_6,$/;" p module:util_adxcvr +up_es_enb_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_7,$/;" p module:axi_adxcvr +up_es_enb_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_7,$/;" p module:util_adxcvr +up_es_enb_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_8,$/;" p module:axi_adxcvr +up_es_enb_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_8,$/;" p module:util_adxcvr +up_es_enb_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_enb_9,$/;" p module:axi_adxcvr +up_es_enb_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_enb_9,$/;" p module:util_adxcvr +up_es_hmax adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [11:0] up_es_hmax;$/;" n module:axi_adxcvr +up_es_hmax adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [11:0] up_es_hmax,$/;" p module:axi_adxcvr_es +up_es_hmax adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [11:0] up_es_hmax,$/;" p module:axi_adxcvr_up +up_es_hmin adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [11:0] up_es_hmin;$/;" n module:axi_adxcvr +up_es_hmin adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [11:0] up_es_hmin,$/;" p module:axi_adxcvr_es +up_es_hmin adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [11:0] up_es_hmin,$/;" p module:axi_adxcvr_up +up_es_hstep adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [11:0] up_es_hstep;$/;" n module:axi_adxcvr +up_es_hstep adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [11:0] up_es_hstep,$/;" p module:axi_adxcvr_es +up_es_hstep adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [11:0] up_es_hstep,$/;" p module:axi_adxcvr_up +up_es_pscale adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 4:0] up_es_pscale;$/;" n module:axi_adxcvr +up_es_pscale adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [ 4:0] up_es_pscale,$/;" p module:axi_adxcvr_es +up_es_pscale adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 4:0] up_es_pscale,$/;" p module:axi_adxcvr_up +up_es_rdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [15:0] up_es_rdata,$/;" p module:axi_adxcvr_es +up_es_rdata adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output [15:0] up_es_rdata,$/;" p module:util_adxcvr_xch +up_es_rdata_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_0,$/;" p module:axi_adxcvr +up_es_rdata_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_0,$/;" p module:util_adxcvr +up_es_rdata_0_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_0_s;$/;" n module:axi_adxcvr +up_es_rdata_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_1,$/;" p module:axi_adxcvr +up_es_rdata_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_1,$/;" p module:util_adxcvr +up_es_rdata_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_10,$/;" p module:axi_adxcvr +up_es_rdata_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_10,$/;" p module:util_adxcvr +up_es_rdata_10_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_10_s;$/;" n module:axi_adxcvr +up_es_rdata_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_11,$/;" p module:axi_adxcvr +up_es_rdata_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_11,$/;" p module:util_adxcvr +up_es_rdata_11_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_11_s;$/;" n module:axi_adxcvr +up_es_rdata_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_12,$/;" p module:axi_adxcvr +up_es_rdata_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_12,$/;" p module:util_adxcvr +up_es_rdata_12_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_12_s;$/;" n module:axi_adxcvr +up_es_rdata_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_13,$/;" p module:axi_adxcvr +up_es_rdata_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_13,$/;" p module:util_adxcvr +up_es_rdata_13_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_13_s;$/;" n module:axi_adxcvr +up_es_rdata_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_14,$/;" p module:axi_adxcvr +up_es_rdata_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_14,$/;" p module:util_adxcvr +up_es_rdata_14_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_14_s;$/;" n module:axi_adxcvr +up_es_rdata_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_15,$/;" p module:axi_adxcvr +up_es_rdata_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_15,$/;" p module:util_adxcvr +up_es_rdata_15_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_15_s;$/;" n module:axi_adxcvr +up_es_rdata_1_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_1_s;$/;" n module:axi_adxcvr +up_es_rdata_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_2,$/;" p module:axi_adxcvr +up_es_rdata_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_2,$/;" p module:util_adxcvr +up_es_rdata_2_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_2_s;$/;" n module:axi_adxcvr +up_es_rdata_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_3,$/;" p module:axi_adxcvr +up_es_rdata_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_3,$/;" p module:util_adxcvr +up_es_rdata_3_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_3_s;$/;" n module:axi_adxcvr +up_es_rdata_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_4,$/;" p module:axi_adxcvr +up_es_rdata_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_4,$/;" p module:util_adxcvr +up_es_rdata_4_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_4_s;$/;" n module:axi_adxcvr +up_es_rdata_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_5,$/;" p module:axi_adxcvr +up_es_rdata_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_5,$/;" p module:util_adxcvr +up_es_rdata_5_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_5_s;$/;" n module:axi_adxcvr +up_es_rdata_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_6,$/;" p module:axi_adxcvr +up_es_rdata_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_6,$/;" p module:util_adxcvr +up_es_rdata_6_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_6_s;$/;" n module:axi_adxcvr +up_es_rdata_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_7,$/;" p module:axi_adxcvr +up_es_rdata_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_7,$/;" p module:util_adxcvr +up_es_rdata_7_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_7_s;$/;" n module:axi_adxcvr +up_es_rdata_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_8,$/;" p module:axi_adxcvr +up_es_rdata_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_8,$/;" p module:util_adxcvr +up_es_rdata_8_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_8_s;$/;" n module:axi_adxcvr +up_es_rdata_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input [15:0] up_es_rdata_9,$/;" p module:axi_adxcvr +up_es_rdata_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_es_rdata_9,$/;" p module:util_adxcvr +up_es_rdata_9_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_rdata_9_s;$/;" n module:axi_adxcvr +up_es_rdata_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [15:0] up_es_rdata_int = 'd0;$/;" r module:util_adxcvr_xch +up_es_ready adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input up_es_ready,$/;" p module:axi_adxcvr_es +up_es_ready adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output up_es_ready,$/;" p module:util_adxcvr_xch +up_es_ready_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_0,$/;" p module:axi_adxcvr +up_es_ready_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_0,$/;" p module:util_adxcvr +up_es_ready_0_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_0_s;$/;" n module:axi_adxcvr +up_es_ready_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_1,$/;" p module:axi_adxcvr +up_es_ready_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_1,$/;" p module:util_adxcvr +up_es_ready_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_10,$/;" p module:axi_adxcvr +up_es_ready_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_10,$/;" p module:util_adxcvr +up_es_ready_10_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_10_s;$/;" n module:axi_adxcvr +up_es_ready_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_11,$/;" p module:axi_adxcvr +up_es_ready_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_11,$/;" p module:util_adxcvr +up_es_ready_11_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_11_s;$/;" n module:axi_adxcvr +up_es_ready_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_12,$/;" p module:axi_adxcvr +up_es_ready_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_12,$/;" p module:util_adxcvr +up_es_ready_12_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_12_s;$/;" n module:axi_adxcvr +up_es_ready_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_13,$/;" p module:axi_adxcvr +up_es_ready_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_13,$/;" p module:util_adxcvr +up_es_ready_13_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_13_s;$/;" n module:axi_adxcvr +up_es_ready_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_14,$/;" p module:axi_adxcvr +up_es_ready_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_14,$/;" p module:util_adxcvr +up_es_ready_14_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_14_s;$/;" n module:axi_adxcvr +up_es_ready_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_15,$/;" p module:axi_adxcvr +up_es_ready_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_15,$/;" p module:util_adxcvr +up_es_ready_15_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_15_s;$/;" n module:axi_adxcvr +up_es_ready_1_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_1_s;$/;" n module:axi_adxcvr +up_es_ready_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_2,$/;" p module:axi_adxcvr +up_es_ready_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_2,$/;" p module:util_adxcvr +up_es_ready_2_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_2_s;$/;" n module:axi_adxcvr +up_es_ready_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_3,$/;" p module:axi_adxcvr +up_es_ready_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_3,$/;" p module:util_adxcvr +up_es_ready_3_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_3_s;$/;" n module:axi_adxcvr +up_es_ready_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_4,$/;" p module:axi_adxcvr +up_es_ready_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_4,$/;" p module:util_adxcvr +up_es_ready_4_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_4_s;$/;" n module:axi_adxcvr +up_es_ready_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_5,$/;" p module:axi_adxcvr +up_es_ready_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_5,$/;" p module:util_adxcvr +up_es_ready_5_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_5_s;$/;" n module:axi_adxcvr +up_es_ready_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_6,$/;" p module:axi_adxcvr +up_es_ready_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_6,$/;" p module:util_adxcvr +up_es_ready_6_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_6_s;$/;" n module:axi_adxcvr +up_es_ready_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_7,$/;" p module:axi_adxcvr +up_es_ready_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_7,$/;" p module:util_adxcvr +up_es_ready_7_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_7_s;$/;" n module:axi_adxcvr +up_es_ready_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_8,$/;" p module:axi_adxcvr +up_es_ready_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_8,$/;" p module:util_adxcvr +up_es_ready_8_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_8_s;$/;" n module:axi_adxcvr +up_es_ready_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ input up_es_ready_9,$/;" p module:axi_adxcvr +up_es_ready_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_es_ready_9,$/;" p module:util_adxcvr +up_es_ready_9_s adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_ready_9_s;$/;" n module:axi_adxcvr +up_es_ready_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg up_es_ready_int = 'd0;$/;" r module:util_adxcvr_xch +up_es_req adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_req;$/;" n module:axi_adxcvr +up_es_req adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input up_es_req,$/;" p module:axi_adxcvr_es +up_es_req adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_es_req,$/;" p module:axi_adxcvr_up +up_es_reset adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_reset;$/;" n module:axi_adxcvr +up_es_reset adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output reg [15:0] up_es_reset = 'h0,$/;" p module:axi_adxcvr_up +up_es_reset adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_es_reset,$/;" p module:util_adxcvr_xch +up_es_reset_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_0,$/;" p module:axi_adxcvr +up_es_reset_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_0,$/;" p module:util_adxcvr +up_es_reset_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_1,$/;" p module:axi_adxcvr +up_es_reset_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_1,$/;" p module:util_adxcvr +up_es_reset_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_10,$/;" p module:axi_adxcvr +up_es_reset_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_10,$/;" p module:util_adxcvr +up_es_reset_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_11,$/;" p module:axi_adxcvr +up_es_reset_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_11,$/;" p module:util_adxcvr +up_es_reset_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_12,$/;" p module:axi_adxcvr +up_es_reset_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_12,$/;" p module:util_adxcvr +up_es_reset_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_13,$/;" p module:axi_adxcvr +up_es_reset_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_13,$/;" p module:util_adxcvr +up_es_reset_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_14,$/;" p module:axi_adxcvr +up_es_reset_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_14,$/;" p module:util_adxcvr +up_es_reset_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_15,$/;" p module:axi_adxcvr +up_es_reset_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_15,$/;" p module:util_adxcvr +up_es_reset_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_2,$/;" p module:axi_adxcvr +up_es_reset_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_2,$/;" p module:util_adxcvr +up_es_reset_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_3,$/;" p module:axi_adxcvr +up_es_reset_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_3,$/;" p module:util_adxcvr +up_es_reset_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_4,$/;" p module:axi_adxcvr +up_es_reset_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_4,$/;" p module:util_adxcvr +up_es_reset_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_5,$/;" p module:axi_adxcvr +up_es_reset_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_5,$/;" p module:util_adxcvr +up_es_reset_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_6,$/;" p module:axi_adxcvr +up_es_reset_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_6,$/;" p module:util_adxcvr +up_es_reset_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_7,$/;" p module:axi_adxcvr +up_es_reset_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_7,$/;" p module:util_adxcvr +up_es_reset_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_8,$/;" p module:axi_adxcvr +up_es_reset_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_8,$/;" p module:util_adxcvr +up_es_reset_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_reset_9,$/;" p module:axi_adxcvr +up_es_reset_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_reset_9,$/;" p module:util_adxcvr +up_es_saddr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [31:0] up_es_saddr;$/;" n module:axi_adxcvr +up_es_saddr adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [31:0] up_es_saddr,$/;" p module:axi_adxcvr_es +up_es_saddr adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [31:0] up_es_saddr,$/;" p module:axi_adxcvr_up +up_es_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 7:0] up_es_sel;$/;" n module:axi_adxcvr +up_es_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 7:0] up_es_sel,$/;" p module:axi_adxcvr_up +up_es_status adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_status;$/;" n module:axi_adxcvr +up_es_status adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output up_es_status,$/;" p module:axi_adxcvr_es +up_es_status adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input up_es_status,$/;" p module:axi_adxcvr_up +up_es_vmax adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 7:0] up_es_vmax;$/;" n module:axi_adxcvr +up_es_vmax adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [ 7:0] up_es_vmax,$/;" p module:axi_adxcvr_es +up_es_vmax adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 7:0] up_es_vmax,$/;" p module:axi_adxcvr_up +up_es_vmin adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 7:0] up_es_vmin;$/;" n module:axi_adxcvr +up_es_vmin adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [ 7:0] up_es_vmin,$/;" p module:axi_adxcvr_es +up_es_vmin adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 7:0] up_es_vmin,$/;" p module:axi_adxcvr_up +up_es_vrange adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 1:0] up_es_vrange;$/;" n module:axi_adxcvr +up_es_vrange adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [ 1:0] up_es_vrange,$/;" p module:axi_adxcvr_es +up_es_vrange adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 1:0] up_es_vrange,$/;" p module:axi_adxcvr_up +up_es_vstep adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 7:0] up_es_vstep;$/;" n module:axi_adxcvr +up_es_vstep adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input [ 7:0] up_es_vstep,$/;" p module:axi_adxcvr_es +up_es_vstep adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [ 7:0] up_es_vstep,$/;" p module:axi_adxcvr_up +up_es_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [15:0] up_es_wdata;$/;" n module:axi_adxcvr +up_es_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output [15:0] up_es_wdata,$/;" p module:axi_adxcvr_es +up_es_wdata adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [15:0] up_es_wdata,$/;" p module:util_adxcvr_xch +up_es_wdata_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_0,$/;" p module:axi_adxcvr +up_es_wdata_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_0,$/;" p module:util_adxcvr +up_es_wdata_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_1,$/;" p module:axi_adxcvr +up_es_wdata_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_1,$/;" p module:util_adxcvr +up_es_wdata_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_10,$/;" p module:axi_adxcvr +up_es_wdata_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_10,$/;" p module:util_adxcvr +up_es_wdata_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_11,$/;" p module:axi_adxcvr +up_es_wdata_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_11,$/;" p module:util_adxcvr +up_es_wdata_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_12,$/;" p module:axi_adxcvr +up_es_wdata_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_12,$/;" p module:util_adxcvr +up_es_wdata_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_13,$/;" p module:axi_adxcvr +up_es_wdata_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_13,$/;" p module:util_adxcvr +up_es_wdata_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_14,$/;" p module:axi_adxcvr +up_es_wdata_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_14,$/;" p module:util_adxcvr +up_es_wdata_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_15,$/;" p module:axi_adxcvr +up_es_wdata_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_15,$/;" p module:util_adxcvr +up_es_wdata_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_2,$/;" p module:axi_adxcvr +up_es_wdata_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_2,$/;" p module:util_adxcvr +up_es_wdata_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_3,$/;" p module:axi_adxcvr +up_es_wdata_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_3,$/;" p module:util_adxcvr +up_es_wdata_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_4,$/;" p module:axi_adxcvr +up_es_wdata_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_4,$/;" p module:util_adxcvr +up_es_wdata_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_5,$/;" p module:axi_adxcvr +up_es_wdata_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_5,$/;" p module:util_adxcvr +up_es_wdata_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_6,$/;" p module:axi_adxcvr +up_es_wdata_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_6,$/;" p module:util_adxcvr +up_es_wdata_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_7,$/;" p module:axi_adxcvr +up_es_wdata_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_7,$/;" p module:util_adxcvr +up_es_wdata_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_8,$/;" p module:axi_adxcvr +up_es_wdata_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_8,$/;" p module:util_adxcvr +up_es_wdata_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output [15:0] up_es_wdata_9,$/;" p module:axi_adxcvr +up_es_wdata_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_es_wdata_9,$/;" p module:util_adxcvr +up_es_wr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_es_wr;$/;" n module:axi_adxcvr +up_es_wr adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ output up_es_wr,$/;" p module:axi_adxcvr_es +up_es_wr adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_es_wr,$/;" p module:util_adxcvr_xch +up_es_wr_0 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_0,$/;" p module:axi_adxcvr +up_es_wr_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_0,$/;" p module:util_adxcvr +up_es_wr_1 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_1,$/;" p module:axi_adxcvr +up_es_wr_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_1,$/;" p module:util_adxcvr +up_es_wr_10 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_10,$/;" p module:axi_adxcvr +up_es_wr_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_10,$/;" p module:util_adxcvr +up_es_wr_11 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_11,$/;" p module:axi_adxcvr +up_es_wr_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_11,$/;" p module:util_adxcvr +up_es_wr_12 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_12,$/;" p module:axi_adxcvr +up_es_wr_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_12,$/;" p module:util_adxcvr +up_es_wr_13 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_13,$/;" p module:axi_adxcvr +up_es_wr_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_13,$/;" p module:util_adxcvr +up_es_wr_14 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_14,$/;" p module:axi_adxcvr +up_es_wr_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_14,$/;" p module:util_adxcvr +up_es_wr_15 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_15,$/;" p module:axi_adxcvr +up_es_wr_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_15,$/;" p module:util_adxcvr +up_es_wr_2 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_2,$/;" p module:axi_adxcvr +up_es_wr_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_2,$/;" p module:util_adxcvr +up_es_wr_3 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_3,$/;" p module:axi_adxcvr +up_es_wr_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_3,$/;" p module:util_adxcvr +up_es_wr_4 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_4,$/;" p module:axi_adxcvr +up_es_wr_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_4,$/;" p module:util_adxcvr +up_es_wr_5 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_5,$/;" p module:axi_adxcvr +up_es_wr_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_5,$/;" p module:util_adxcvr +up_es_wr_6 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_6,$/;" p module:axi_adxcvr +up_es_wr_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_6,$/;" p module:util_adxcvr +up_es_wr_7 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_7,$/;" p module:axi_adxcvr +up_es_wr_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_7,$/;" p module:util_adxcvr +up_es_wr_8 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_8,$/;" p module:axi_adxcvr +up_es_wr_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_8,$/;" p module:util_adxcvr +up_es_wr_9 adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_es_wr_9,$/;" p module:axi_adxcvr +up_es_wr_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_es_wr_9,$/;" p module:util_adxcvr +up_fsm adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [ 4:0] up_fsm = 'd0;$/;" r module:axi_adxcvr_es +up_hdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [15:0] up_hdata = 'd0;$/;" r module:axi_adxcvr_es +up_hdmi_clk_count_s adi_library/common/up_hdmi_tx.v /^ wire [31:0] up_hdmi_clk_count_s;$/;" n module:up_hdmi_tx +up_hdmi_rx adi_library/common/up_hdmi_rx.v /^module up_hdmi_rx #($/;" m +up_hdmi_status_s adi_library/common/up_hdmi_tx.v /^ wire up_hdmi_status_s;$/;" n module:up_hdmi_tx +up_hdmi_tpm_oos adi_library/common/up_hdmi_tx.v /^ reg up_hdmi_tpm_oos = 'd0;$/;" r module:up_hdmi_tx +up_hdmi_tpm_oos_s adi_library/common/up_hdmi_tx.v /^ wire up_hdmi_tpm_oos_s;$/;" n module:up_hdmi_tx +up_hdmi_tx adi_library/common/up_hdmi_tx.v /^module up_hdmi_tx #($/;" m +up_he_max adi_library/common/up_hdmi_tx.v /^ reg [15:0] up_he_max = 'd0;$/;" r module:up_hdmi_tx +up_he_min adi_library/common/up_hdmi_tx.v /^ reg [15:0] up_he_min = 'd0;$/;" r module:up_hdmi_tx +up_heos_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ wire up_heos_s;$/;" n module:axi_adxcvr_es +up_hindex adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [11:0] up_hindex = 'd0;$/;" r module:axi_adxcvr_es +up_hl_active adi_library/common/up_hdmi_tx.v /^ reg [15:0] up_hl_active = 'd0;$/;" r module:up_hdmi_tx +up_hl_width adi_library/common/up_hdmi_tx.v /^ reg [15:0] up_hl_width = 'd0;$/;" r module:up_hdmi_tx +up_hs_count adi_library/common/up_hdmi_rx.v /^ reg [15:0] up_hs_count = 'd0;$/;" r module:up_hdmi_rx +up_hs_mismatch adi_library/common/up_hdmi_rx.v /^ reg up_hs_mismatch = 'd0;$/;" r module:up_hdmi_rx +up_hs_mismatch_s adi_library/common/up_hdmi_rx.v /^ wire up_hs_mismatch_s;$/;" n module:up_hdmi_rx +up_hs_oos adi_library/common/up_hdmi_rx.v /^ reg up_hs_oos = 'd0;$/;" r module:up_hdmi_rx +up_hs_oos_s adi_library/common/up_hdmi_rx.v /^ wire up_hs_oos_s;$/;" n module:up_hdmi_rx +up_hs_s adi_library/common/up_hdmi_rx.v /^ wire [15:0] up_hs_s;$/;" n module:up_hdmi_rx +up_hs_width adi_library/common/up_hdmi_tx.v /^ reg [15:0] up_hs_width = 'd0;$/;" r module:up_hdmi_tx +up_ich_busy adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_ich_busy = 'd0;$/;" r module:axi_adxcvr_up +up_ich_data adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [28:0] up_ich_data = 'd0;$/;" r module:axi_adxcvr_up +up_ich_enb adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_ich_enb = 'd0;$/;" r module:axi_adxcvr_up +up_ich_rdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [15:0] up_ich_rdata = 'd0;$/;" r module:axi_adxcvr_up +up_ich_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 7:0] up_ich_sel = 'd0;$/;" r module:axi_adxcvr_up +up_ich_wr adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_ich_wr = 'd0;$/;" r module:axi_adxcvr_up +up_icm_busy adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_icm_busy = 'd0;$/;" r module:axi_adxcvr_up +up_icm_data adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [28:0] up_icm_data = 'd0;$/;" r module:axi_adxcvr_up +up_icm_enb adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_icm_enb = 'd0;$/;" r module:axi_adxcvr_up +up_icm_rdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [15:0] up_icm_rdata = 'd0;$/;" r module:axi_adxcvr_up +up_icm_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 7:0] up_icm_sel = 'd0;$/;" r module:axi_adxcvr_up +up_icm_wr adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_icm_wr = 'd0;$/;" r module:axi_adxcvr_up +up_ies_hoffset_max adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [11:0] up_ies_hoffset_max = 'd0;$/;" r module:axi_adxcvr_up +up_ies_hoffset_min adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [11:0] up_ies_hoffset_min = 'd0;$/;" r module:axi_adxcvr_up +up_ies_hoffset_step adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [11:0] up_ies_hoffset_step = 'd0;$/;" r module:axi_adxcvr_up +up_ies_prescale adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 4:0] up_ies_prescale = 'd0;$/;" r module:axi_adxcvr_up +up_ies_req adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_ies_req = 'd0;$/;" r module:axi_adxcvr_up +up_ies_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 7:0] up_ies_sel = 'd0;$/;" r module:axi_adxcvr_up +up_ies_start_addr adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [31:0] up_ies_start_addr = 'd0;$/;" r module:axi_adxcvr_up +up_ies_status adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_ies_status = 'd0;$/;" r module:axi_adxcvr_up +up_ies_voffset_max adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 7:0] up_ies_voffset_max = 'd0;$/;" r module:axi_adxcvr_up +up_ies_voffset_min adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 7:0] up_ies_voffset_min = 'd0;$/;" r module:axi_adxcvr_up +up_ies_voffset_range adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 1:0] up_ies_voffset_range = 'd0;$/;" r module:axi_adxcvr_up +up_ies_voffset_step adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 7:0] up_ies_voffset_step = 'd0;$/;" r module:axi_adxcvr_up +up_irq adi_library/common/ad_pps_receiver.v /^ output reg up_irq);$/;" p module:ad_pps_receiver +up_irq_mask adi_library/axi_dmac/axi_dmac_regmap.v /^reg [1:0] up_irq_mask = 2'h3;$/;" r module:axi_dmac_regmap +up_irq_mask adi_library/common/ad_pps_receiver.v /^ input up_irq_mask,$/;" p module:ad_pps_receiver +up_irq_mask adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg [3:0] up_irq_mask = 'h0;$/;" r module:axi_spi_engine +up_irq_pending adi_library/axi_dmac/axi_dmac_regmap.v /^wire [1:0] up_irq_pending;$/;" n module:axi_dmac_regmap +up_irq_pending adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [3:0] up_irq_pending;$/;" n module:axi_spi_engine +up_irq_source adi_library/axi_dmac/axi_dmac_regmap.v /^reg [1:0] up_irq_source = 2'h0;$/;" r module:axi_dmac_regmap +up_irq_source adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [3:0] up_irq_source;$/;" n module:axi_spi_engine +up_irq_source_clear adi_library/axi_dmac/axi_dmac_regmap.v /^wire [1:0] up_irq_source_clear;$/;" n module:axi_dmac_regmap +up_irq_trigger adi_library/axi_dmac/axi_dmac_regmap.v /^wire [1:0] up_irq_trigger;$/;" n module:axi_dmac_regmap +up_lpm_dfe_n adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_lpm_dfe_n = LPM_OR_DFE_N;$/;" r module:axi_adxcvr_up +up_measured_transfer_length adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg [MEASURED_LENGTH_WIDTH-1:0] up_measured_transfer_length = 'h0;$/;" r module:axi_dmac_regmap_request +up_mmcm_preset adi_library/common/up_adc_common.v /^ reg up_mmcm_preset = 'd1;$/;" r module:up_adc_common +up_mmcm_preset adi_library/common/up_clkgen.v /^ reg up_mmcm_preset = 'd0;$/;" r module:up_clkgen +up_mmcm_preset adi_library/common/up_dac_common.v /^ reg up_mmcm_preset = 'd1;$/;" r module:up_dac_common +up_mmcm_resetn adi_library/common/up_adc_common.v /^ reg up_mmcm_resetn = 'd0;$/;" r module:up_adc_common +up_mmcm_resetn adi_library/common/up_clkgen.v /^ reg up_mmcm_resetn = 'd0;$/;" r module:up_clkgen +up_mmcm_resetn adi_library/common/up_dac_common.v /^ reg up_mmcm_resetn = 'd0;$/;" r module:up_dac_common +up_offload0_cmd_wr_data_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [15:0] up_offload0_cmd_wr_data_s;$/;" n module:axi_spi_engine +up_offload0_cmd_wr_en_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire up_offload0_cmd_wr_en_s;$/;" n module:axi_spi_engine +up_offload0_sdo_wr_data_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s;$/;" n module:axi_spi_engine +up_offload0_sdo_wr_en_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire up_offload0_sdo_wr_en_s;$/;" n module:axi_spi_engine +up_out_clk_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 2:0] up_out_clk_sel = OUT_CLK_SEL;$/;" r module:axi_adxcvr_up +up_packed adi_library/common/up_hdmi_rx.v /^ reg up_packed = 'd0;$/;" r module:up_hdmi_rx +up_partial_length_valid adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg up_partial_length_valid = 1'b0;$/;" r module:axi_dmac_regmap_request +up_pll_locked adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ input up_pll_locked,$/;" p module:axi_adxcvr_mstatus +up_pll_locked adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ reg [31:0] up_pll_locked = 'd0;$/;" r module:axi_xcvrlb +up_pll_locked adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ output up_pll_locked);$/;" p module:axi_xcvrlb_1 +up_pll_locked_in adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ input up_pll_locked_in,$/;" p module:axi_adxcvr_mstatus +up_pll_locked_int adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ reg up_pll_locked_int = 'd0;$/;" r module:axi_adxcvr_mstatus +up_pll_locked_out adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ output up_pll_locked_out,$/;" p module:axi_adxcvr_mstatus +up_pll_locked_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ wire up_pll_locked_s;$/;" n module:axi_adxcvr_mstatus +up_pll_locked_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ wire [31:0] up_pll_locked_s;$/;" n module:axi_xcvrlb +up_pll_locked_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_pll_locked_s;$/;" n module:axi_xcvrlb_1 +up_pll_rst adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_pll_rst,$/;" p module:axi_adxcvr +up_pll_rst adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_pll_rst,$/;" p module:axi_adxcvr_up +up_pll_rst_cnt adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 3:0] up_pll_rst_cnt = 'd0;$/;" r module:axi_adxcvr_up +up_pll_rst_cnt adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg [ 3:0] up_pll_rst_cnt = 'd0;$/;" r module:axi_xcvrlb_1 +up_pll_rst_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_pll_rst_s;$/;" n module:axi_xcvrlb_1 +up_pmod adi_library/common/up_pmod.v /^module up_pmod #($/;" m +up_pmod_signal_freq_s adi_library/common/up_pmod.v /^ wire [31:0] up_pmod_signal_freq_s;$/;" n module:up_pmod +up_pn_err_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_pn_err_s;$/;" n module:axi_xcvrlb_1 +up_pn_oos_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_pn_oos_s;$/;" n module:axi_xcvrlb_1 +up_pps_irq_mask adi_library/common/up_adc_common.v /^ output reg up_pps_irq_mask,$/;" p module:up_adc_common +up_pps_irq_mask adi_library/common/up_dac_common.v /^ output reg up_pps_irq_mask,$/;" p module:up_dac_common +up_pps_m adi_library/common/ad_pps_receiver.v /^ reg [ 2:0] up_pps_m = 3'b0;$/;" r module:ad_pps_receiver +up_pps_posedge_s adi_library/common/ad_pps_receiver.v /^ wire up_pps_posedge_s;$/;" n module:ad_pps_receiver +up_pps_rcounter adi_library/common/ad_pps_receiver.v /^ output reg [31:0] up_pps_rcounter,$/;" p module:ad_pps_receiver +up_pps_rcounter adi_library/common/up_adc_common.v /^ input [31:0] up_pps_rcounter,$/;" p module:up_adc_common +up_pps_rcounter adi_library/common/up_dac_common.v /^ input [31:0] up_pps_rcounter,$/;" p module:up_dac_common +up_pps_status adi_library/common/ad_pps_receiver.v /^ output reg up_pps_status,$/;" p module:ad_pps_receiver +up_pps_status adi_library/common/up_adc_common.v /^ input up_pps_status,$/;" p module:up_adc_common +up_pps_status adi_library/common/up_dac_common.v /^ input up_pps_status,$/;" p module:up_dac_common +up_pps_status_m adi_library/common/ad_pps_receiver.v /^ reg up_pps_status_m = 1'b0;$/;" r module:ad_pps_receiver +up_preset adi_library/common/up_delay_cntrl.v /^ reg up_preset = 'd0;$/;" r module:up_delay_cntrl +up_qpll_rst adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ input up_qpll_rst,$/;" p module:util_adxcvr_xcm +up_qpll_rst_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_qpll_rst_0,$/;" p module:util_adxcvr +up_qpll_rst_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_qpll_rst_12,$/;" p module:util_adxcvr +up_qpll_rst_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_qpll_rst_4,$/;" p module:util_adxcvr +up_qpll_rst_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_qpll_rst_8,$/;" p module:util_adxcvr +up_rack adi_library/axi_dmac/axi_dmac_regmap.v /^reg up_rack = 1'b0;$/;" r module:axi_dmac_regmap +up_rack adi_library/common/up_adc_channel.v /^ output up_rack);$/;" p module:up_adc_channel +up_rack adi_library/common/up_adc_common.v /^ output up_rack);$/;" p module:up_adc_common +up_rack adi_library/common/up_axi.v /^ input up_rack);$/;" p module:up_axi +up_rack adi_library/common/up_clkgen.v /^ output reg up_rack);$/;" p module:up_clkgen +up_rack adi_library/common/up_dac_channel.v /^ output up_rack);$/;" p module:up_dac_channel +up_rack adi_library/common/up_dac_common.v /^ output up_rack);$/;" p module:up_dac_common +up_rack adi_library/common/up_delay_cntrl.v /^ output up_rack);$/;" p module:up_delay_cntrl +up_rack adi_library/common/up_hdmi_rx.v /^ output reg up_rack);$/;" p module:up_hdmi_rx +up_rack adi_library/common/up_hdmi_tx.v /^ output reg up_rack);$/;" p module:up_hdmi_tx +up_rack adi_library/common/up_pmod.v /^ output reg up_rack);$/;" p module:up_pmod +up_rack adi_library/common/up_tdd_cntrl.v /^ output reg up_rack);$/;" p module:up_tdd_cntrl +up_rack adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output up_rack,$/;" p module:axi_spi_engine +up_rack adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_rack;$/;" n module:axi_adxcvr +up_rack adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_rack);$/;" p module:axi_adxcvr_up +up_rack adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ reg up_rack = 'd0;$/;" r module:axi_xcvrlb +up_rack hdl/phy_control.v /^ wire up_rack;$/;" n module:phy_control +up_rack hdl/up_axi.v /^ input up_rack$/;" p module:up_axi +up_rack_d adi_library/common/up_axi.v /^ reg up_rack_d = 'd0;$/;" r module:up_axi +up_rack_d hdl/up_axi.v /^ reg up_rack_d = 'd0;$/;" r module:up_axi +up_rack_ff adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg up_rack_ff = 1'b0;$/;" r module:axi_spi_engine +up_rack_ff hdl/phy_control.v /^ reg up_rack_ff = 1'b0;$/;" r module:phy_control +up_rack_int adi_library/common/up_adc_channel.v /^ reg up_rack_int = 'd0;$/;" r module:up_adc_channel +up_rack_int adi_library/common/up_adc_common.v /^ reg up_rack_int = 'd0;$/;" r module:up_adc_common +up_rack_int adi_library/common/up_dac_channel.v /^ reg up_rack_int = 'd0;$/;" r module:up_dac_channel +up_rack_int adi_library/common/up_dac_common.v /^ reg up_rack_int = 'd0;$/;" r module:up_dac_common +up_rack_int adi_library/common/up_delay_cntrl.v /^ reg up_rack_int = 'd0;$/;" r module:up_delay_cntrl +up_rack_rcv hdl/phy_control.v /^ wire up_rack_rcv;$/;" n module:phy_control +up_rack_s adi_library/common/up_axi.v /^ wire up_rack_s;$/;" n module:up_axi +up_rack_s hdl/up_axi.v /^ wire up_rack_s;$/;" n module:up_axi +up_rack_send hdl/phy_control.v /^ reg up_rack_send = 1'b0;$/;" r module:phy_control +up_raddr adi_library/axi_dmac/axi_dmac_regmap.v /^wire [8:0] up_raddr;$/;" n module:axi_dmac_regmap +up_raddr adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input [8:0] up_raddr,$/;" p module:axi_dmac_regmap_request +up_raddr adi_library/common/up_adc_channel.v /^ input [13:0] up_raddr,$/;" p module:up_adc_channel +up_raddr adi_library/common/up_adc_common.v /^ input [13:0] up_raddr,$/;" p module:up_adc_common +up_raddr adi_library/common/up_axi.v /^ output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,$/;" p module:up_axi +up_raddr adi_library/common/up_clkgen.v /^ input [13:0] up_raddr,$/;" p module:up_clkgen +up_raddr adi_library/common/up_dac_channel.v /^ input [13:0] up_raddr,$/;" p module:up_dac_channel +up_raddr adi_library/common/up_dac_common.v /^ input [13:0] up_raddr,$/;" p module:up_dac_common +up_raddr adi_library/common/up_delay_cntrl.v /^ input [13:0] up_raddr,$/;" p module:up_delay_cntrl +up_raddr adi_library/common/up_hdmi_rx.v /^ input [13:0] up_raddr,$/;" p module:up_hdmi_rx +up_raddr adi_library/common/up_hdmi_tx.v /^ input [13:0] up_raddr,$/;" p module:up_hdmi_tx +up_raddr adi_library/common/up_pmod.v /^ input [13:0] up_raddr,$/;" p module:up_pmod +up_raddr adi_library/common/up_tdd_cntrl.v /^ input [13:0] up_raddr,$/;" p module:up_tdd_cntrl +up_raddr adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [13:0] up_raddr,$/;" p module:axi_spi_engine +up_raddr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 9:0] up_raddr;$/;" n module:axi_adxcvr +up_raddr adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input [ 9:0] up_raddr,$/;" p module:axi_adxcvr_up +up_raddr hdl/phy_control.v /^ wire [(AXI_ADDRESS_WIDTH-3):0] up_raddr;$/;" n module:phy_control +up_raddr hdl/up_axi.v /^ output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,$/;" p module:up_axi +up_raddr_int adi_library/common/up_axi.v /^ reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;$/;" r module:up_axi +up_raddr_int hdl/up_axi.v /^ reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;$/;" r module:up_axi +up_raddr_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [13:0] up_raddr_s;$/;" n module:axi_spi_engine +up_raddr_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ wire [ 7:0] up_raddr_s;$/;" n module:axi_xcvrlb +up_raddr_s hdl/phy_control.v /^ wire [(AXI_ADDRESS_WIDTH-3):0] up_raddr_s;$/;" n module:phy_control +up_rate adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 2:0] up_rate = RATE;$/;" r module:axi_adxcvr_up +up_rcount adi_library/common/up_axi.v /^ reg [ 4:0] up_rcount = 'd0;$/;" r module:up_axi +up_rcount hdl/up_axi.v /^ reg [ 5:0] up_rcount = 'd0;$/;" r module:up_axi +up_rdata adi_library/axi_dmac/axi_dmac_regmap.v /^reg [31:0] up_rdata = 32'h00;$/;" r module:axi_dmac_regmap +up_rdata adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output reg [31:0] up_rdata,$/;" p module:axi_dmac_regmap_request +up_rdata adi_library/common/up_adc_channel.v /^ output [31:0] up_rdata,$/;" p module:up_adc_channel +up_rdata adi_library/common/up_adc_common.v /^ output [31:0] up_rdata,$/;" p module:up_adc_common +up_rdata adi_library/common/up_axi.v /^ input [31:0] up_rdata,$/;" p module:up_axi +up_rdata adi_library/common/up_clkgen.v /^ output reg [31:0] up_rdata,$/;" p module:up_clkgen +up_rdata adi_library/common/up_dac_channel.v /^ output [31:0] up_rdata,$/;" p module:up_dac_channel +up_rdata adi_library/common/up_dac_common.v /^ output [31:0] up_rdata,$/;" p module:up_dac_common +up_rdata adi_library/common/up_delay_cntrl.v /^ output [31:0] up_rdata,$/;" p module:up_delay_cntrl +up_rdata adi_library/common/up_hdmi_rx.v /^ output reg [31:0] up_rdata,$/;" p module:up_hdmi_rx +up_rdata adi_library/common/up_hdmi_tx.v /^ output reg [31:0] up_rdata,$/;" p module:up_hdmi_tx +up_rdata adi_library/common/up_pmod.v /^ output reg [31:0] up_rdata,$/;" p module:up_pmod +up_rdata adi_library/common/up_tdd_cntrl.v /^ output reg [31:0] up_rdata,$/;" p module:up_tdd_cntrl +up_rdata adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output [31:0] up_rdata,$/;" p module:axi_spi_engine +up_rdata adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [31:0] up_rdata;$/;" n module:axi_adxcvr +up_rdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ input [15:0] up_rdata,$/;" p module:axi_adxcvr_mdrp +up_rdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output [31:0] up_rdata,$/;" p module:axi_adxcvr_up +up_rdata adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ reg [31:0] up_rdata = 'd0;$/;" r module:axi_xcvrlb +up_rdata hdl/phy_control.v /^ wire [ 31:0] up_rdata;$/;" n module:phy_control +up_rdata hdl/up_axi.v /^ input [ 31:0] up_rdata,$/;" p module:up_axi +up_rdata_d adi_library/common/up_axi.v /^ reg [31:0] up_rdata_d = 'd0;$/;" r module:up_axi +up_rdata_d adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [31:0] up_rdata_d = 'd0;$/;" r module:axi_adxcvr_up +up_rdata_d hdl/up_axi.v /^ reg [ 31:0] up_rdata_d = 'd0;$/;" r module:up_axi +up_rdata_ff adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg [31:0] up_rdata_ff = 'd0;$/;" r module:axi_spi_engine +up_rdata_ff hdl/phy_control.v /^ reg [ 31:0] up_rdata_ff = 'd0;$/;" r module:phy_control +up_rdata_i adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ reg [15:0] up_rdata_i = 'd0;$/;" r module:axi_adxcvr_mdrp +up_rdata_in adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ input [15:0] up_rdata_in,$/;" p module:axi_adxcvr_mdrp +up_rdata_int adi_library/common/up_adc_channel.v /^ reg [31:0] up_rdata_int = 'd0;$/;" r module:up_adc_channel +up_rdata_int adi_library/common/up_adc_common.v /^ reg [31:0] up_rdata_int = 'd0;$/;" r module:up_adc_common +up_rdata_int adi_library/common/up_dac_channel.v /^ reg [31:0] up_rdata_int = 'd0;$/;" r module:up_dac_channel +up_rdata_int adi_library/common/up_dac_common.v /^ reg [31:0] up_rdata_int = 'd0;$/;" r module:up_dac_common +up_rdata_int adi_library/common/up_delay_cntrl.v /^ reg [31:0] up_rdata_int = 'd0;$/;" r module:up_delay_cntrl +up_rdata_int adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ reg [15:0] up_rdata_int = 'd0;$/;" r module:axi_adxcvr_mdrp +up_rdata_int adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ reg [15:0] up_rdata_int = 'd0;$/;" r module:util_adxcvr_xcm +up_rdata_m adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ reg [15:0] up_rdata_m = 'd0;$/;" r module:axi_adxcvr_mdrp +up_rdata_mi_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ wire [15:0] up_rdata_mi_s;$/;" n module:axi_adxcvr_mdrp +up_rdata_out adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ output [15:0] up_rdata_out,$/;" p module:axi_adxcvr_mdrp +up_rdata_request adi_library/axi_dmac/axi_dmac_regmap.v /^wire [31:0] up_rdata_request;$/;" n module:axi_dmac_regmap +up_rdata_s adi_library/common/up_axi.v /^ wire [31:0] up_rdata_s;$/;" n module:up_axi +up_rdata_s adi_library/common/up_delay_cntrl.v /^ wire [ DRP_WIDTH-1:0] up_rdata_s;$/;" n module:up_delay_cntrl +up_rdata_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [15:0] up_rdata_s;$/;" n module:util_adxcvr_xch +up_rdata_s adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ wire [15:0] up_rdata_s;$/;" n module:util_adxcvr_xcm +up_rdata_s hdl/up_axi.v /^ wire [ 31:0] up_rdata_s;$/;" n module:up_axi +up_ready adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ input up_ready,$/;" p module:axi_adxcvr_mdrp +up_ready_i adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ reg up_ready_i = 'd0;$/;" r module:axi_adxcvr_mdrp +up_ready_in adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ input up_ready_in,$/;" p module:axi_adxcvr_mdrp +up_ready_int adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ reg up_ready_int = 'd0;$/;" r module:axi_adxcvr_mdrp +up_ready_int adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ reg up_ready_int = 'd0;$/;" r module:util_adxcvr_xcm +up_ready_m adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ reg up_ready_m = 'd0;$/;" r module:axi_adxcvr_mdrp +up_ready_mi adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ reg up_ready_mi = 'd0;$/;" r module:axi_adxcvr_mdrp +up_ready_mi_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ wire up_ready_mi_s;$/;" n module:axi_adxcvr_mdrp +up_ready_out adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ output up_ready_out);$/;" p module:axi_adxcvr_mdrp +up_ready_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ wire up_ready_s;$/;" n module:axi_adxcvr_mdrp +up_ready_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire up_ready_s;$/;" n module:util_adxcvr_xch +up_ready_s adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ wire up_ready_s;$/;" n module:util_adxcvr_xcm +up_req_d adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg up_req_d = 'd0;$/;" r module:axi_adxcvr_es +up_req_eot adi_library/axi_dmac/axi_dmac.v /^wire up_req_eot;$/;" n module:axi_dmac +up_req_measured_burst_length adi_library/axi_dmac/axi_dmac.v /^wire [BYTES_PER_BURST_WIDTH-1:0] up_req_measured_burst_length;$/;" n module:axi_dmac +up_resetn adi_library/common/up_adc_common.v /^ reg up_resetn = 'd0;$/;" r module:up_adc_common +up_resetn adi_library/common/up_clkgen.v /^ reg up_resetn = 'd0;$/;" r module:up_clkgen +up_resetn adi_library/common/up_dac_common.v /^ reg up_resetn = 'd0;$/;" r module:up_dac_common +up_resetn adi_library/common/up_hdmi_rx.v /^ reg up_resetn = 'd0;$/;" r module:up_hdmi_rx +up_resetn adi_library/common/up_hdmi_tx.v /^ reg up_resetn = 'd0;$/;" r module:up_hdmi_tx +up_resetn adi_library/common/up_pmod.v /^ reg up_resetn = 'd0;$/;" r module:up_pmod +up_resetn adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_resetn = 'd0;$/;" r module:axi_adxcvr_up +up_resetn adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ reg up_resetn = 'd0;$/;" r module:axi_xcvrlb +up_resetn adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ input up_resetn,$/;" p module:axi_xcvrlb_1 +up_response_partial adi_library/axi_dmac/axi_dmac.v /^wire up_response_partial;$/;" n module:axi_dmac +up_response_ready adi_library/axi_dmac/axi_dmac.v /^wire up_response_ready;$/;" n module:axi_dmac +up_response_valid adi_library/axi_dmac/axi_dmac.v /^wire up_response_valid;$/;" n module:axi_dmac +up_rparam_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ wire [31:0] up_rparam_s;$/;" n module:axi_adxcvr_up +up_rreq adi_library/axi_dmac/axi_dmac_regmap.v /^wire up_rreq;$/;" n module:axi_dmac_regmap +up_rreq adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input up_rreq,$/;" p module:axi_dmac_regmap_request +up_rreq adi_library/common/up_adc_channel.v /^ input up_rreq,$/;" p module:up_adc_channel +up_rreq adi_library/common/up_adc_common.v /^ input up_rreq,$/;" p module:up_adc_common +up_rreq adi_library/common/up_axi.v /^ output up_rreq,$/;" p module:up_axi +up_rreq adi_library/common/up_clkgen.v /^ input up_rreq,$/;" p module:up_clkgen +up_rreq adi_library/common/up_dac_channel.v /^ input up_rreq,$/;" p module:up_dac_channel +up_rreq adi_library/common/up_dac_common.v /^ input up_rreq,$/;" p module:up_dac_common +up_rreq adi_library/common/up_delay_cntrl.v /^ input up_rreq,$/;" p module:up_delay_cntrl +up_rreq adi_library/common/up_hdmi_rx.v /^ input up_rreq,$/;" p module:up_hdmi_rx +up_rreq adi_library/common/up_hdmi_tx.v /^ input up_rreq,$/;" p module:up_hdmi_tx +up_rreq adi_library/common/up_pmod.v /^ input up_rreq,$/;" p module:up_pmod +up_rreq adi_library/common/up_tdd_cntrl.v /^ input up_rreq,$/;" p module:up_tdd_cntrl +up_rreq adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input up_rreq,$/;" p module:axi_spi_engine +up_rreq adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_rreq;$/;" n module:axi_adxcvr +up_rreq adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input up_rreq,$/;" p module:axi_adxcvr_up +up_rreq hdl/phy_control.v /^ wire up_rreq;$/;" n module:phy_control +up_rreq hdl/up_axi.v /^ output up_rreq,$/;" p module:up_axi +up_rreq_d adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_rreq_d = 'd0;$/;" r module:axi_adxcvr_up +up_rreq_int adi_library/common/up_axi.v /^ reg up_rreq_int = 'd0;$/;" r module:up_axi +up_rreq_int hdl/up_axi.v /^ reg up_rreq_int = 'd0;$/;" r module:up_axi +up_rreq_rcv hdl/phy_control.v /^ wire up_rreq_rcv;$/;" n module:phy_control +up_rreq_s adi_library/common/up_adc_channel.v /^ wire up_rreq_s;$/;" n module:up_adc_channel +up_rreq_s adi_library/common/up_adc_common.v /^ wire up_rreq_s;$/;" n module:up_adc_common +up_rreq_s adi_library/common/up_clkgen.v /^ wire up_rreq_s;$/;" n module:up_clkgen +up_rreq_s adi_library/common/up_dac_channel.v /^ wire up_rreq_s;$/;" n module:up_dac_channel +up_rreq_s adi_library/common/up_dac_common.v /^ wire up_rreq_s;$/;" n module:up_dac_common +up_rreq_s adi_library/common/up_delay_cntrl.v /^ wire up_rreq_s;$/;" n module:up_delay_cntrl +up_rreq_s adi_library/common/up_hdmi_rx.v /^ wire up_rreq_s;$/;" n module:up_hdmi_rx +up_rreq_s adi_library/common/up_hdmi_tx.v /^ wire up_rreq_s;$/;" n module:up_hdmi_tx +up_rreq_s adi_library/common/up_pmod.v /^ wire up_rreq_s;$/;" n module:up_pmod +up_rreq_s adi_library/common/up_tdd_cntrl.v /^ wire up_rreq_s;$/;" n module:up_tdd_cntrl +up_rreq_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire up_rreq_s;$/;" n module:axi_spi_engine +up_rreq_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ wire up_rreq_s;$/;" n module:axi_xcvrlb +up_rreq_s hdl/phy_control.v /^ wire up_rreq_s;$/;" n module:phy_control +up_rreq_send hdl/phy_control.v /^ reg up_rreq_send = 1'b0;$/;" r module:phy_control +up_rresp_d hdl/up_axi.v /^ reg [ 1:0] up_rresp_d = 'd0;$/;" r module:up_axi +up_rresp_s hdl/up_axi.v /^ wire [ 1:0] up_rresp_s;$/;" n module:up_axi +up_rsel adi_library/common/up_axi.v /^ reg up_rsel = 'd0;$/;" r module:up_axi +up_rsel hdl/up_axi.v /^ reg up_rsel = 'd0;$/;" r module:up_axi +up_rst_cnt adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 3:0] up_rst_cnt = 'd0;$/;" r module:axi_adxcvr_up +up_rst_cnt adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg [ 3:0] up_rst_cnt = 'd0;$/;" r module:axi_xcvrlb_1 +up_rst_done adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ input up_rst_done,$/;" p module:axi_adxcvr_mstatus +up_rst_done_in adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ input up_rst_done_in,$/;" p module:axi_adxcvr_mstatus +up_rst_done_int adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ reg up_rst_done_int = 'd0;$/;" r module:axi_adxcvr_mstatus +up_rst_done_out adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ output up_rst_done_out);$/;" p module:axi_adxcvr_mstatus +up_rst_done_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ wire up_rst_done_s;$/;" n module:axi_adxcvr_mstatus +up_rst_done_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_rst_done_s;$/;" n module:axi_xcvrlb_1 +up_rst_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_rst_s;$/;" n module:axi_xcvrlb_1 +up_rstn adi_library/common/ad_pps_receiver.v /^ input up_rstn,$/;" p module:ad_pps_receiver +up_rstn adi_library/common/up_adc_channel.v /^ input up_rstn,$/;" p module:up_adc_channel +up_rstn adi_library/common/up_adc_common.v /^ input up_rstn,$/;" p module:up_adc_common +up_rstn adi_library/common/up_axi.v /^ input up_rstn,$/;" p module:up_axi +up_rstn adi_library/common/up_clkgen.v /^ input up_rstn,$/;" p module:up_clkgen +up_rstn adi_library/common/up_clock_mon.v /^ input up_rstn,$/;" p module:up_clock_mon +up_rstn adi_library/common/up_dac_channel.v /^ input up_rstn,$/;" p module:up_dac_channel +up_rstn adi_library/common/up_dac_common.v /^ input up_rstn,$/;" p module:up_dac_common +up_rstn adi_library/common/up_delay_cntrl.v /^ input up_rstn,$/;" p module:up_delay_cntrl +up_rstn adi_library/common/up_hdmi_rx.v /^ input up_rstn,$/;" p module:up_hdmi_rx +up_rstn adi_library/common/up_hdmi_tx.v /^ input up_rstn,$/;" p module:up_hdmi_tx +up_rstn adi_library/common/up_pmod.v /^ input up_rstn,$/;" p module:up_pmod +up_rstn adi_library/common/up_tdd_cntrl.v /^ input up_rstn,$/;" p module:up_tdd_cntrl +up_rstn adi_library/common/up_xfer_cntrl.v /^ input up_rstn,$/;" p module:up_xfer_cntrl +up_rstn adi_library/common/up_xfer_status.v /^ input up_rstn,$/;" p module:up_xfer_status +up_rstn adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input up_rstn,$/;" p module:axi_spi_engine +up_rstn adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_rstn;$/;" n module:axi_adxcvr +up_rstn adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ input up_rstn,$/;" p module:axi_adxcvr_es +up_rstn adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ input up_rstn,$/;" p module:axi_adxcvr_mdrp +up_rstn adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v /^ input up_rstn,$/;" p module:axi_adxcvr_mstatus +up_rstn adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input up_rstn,$/;" p module:axi_adxcvr_up +up_rstn adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ wire up_rstn;$/;" n module:axi_xcvrlb +up_rstn adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ input up_rstn,$/;" p module:axi_xcvrlb_1 +up_rstn adi_library/xilinx/common/ad_mmcm_drp.v /^ input up_rstn,$/;" p module:ad_mmcm_drp +up_rstn adi_library/xilinx/common/ad_serdes_clk.v /^ input up_rstn,$/;" p module:ad_serdes_clk +up_rstn adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rstn,$/;" p module:util_adxcvr +up_rstn adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_rstn,$/;" p module:util_adxcvr_xch +up_rstn adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ input up_rstn,$/;" p module:util_adxcvr_xcm +up_rstn hdl/up_axi.v /^ input up_rstn,$/;" p module:up_axi +up_rx_addr adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [11:0] up_rx_addr,$/;" p module:util_adxcvr_xch +up_rx_addr_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_0,$/;" p module:util_adxcvr +up_rx_addr_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_1,$/;" p module:util_adxcvr +up_rx_addr_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_10,$/;" p module:util_adxcvr +up_rx_addr_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_11,$/;" p module:util_adxcvr +up_rx_addr_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_12,$/;" p module:util_adxcvr +up_rx_addr_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_13,$/;" p module:util_adxcvr +up_rx_addr_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_14,$/;" p module:util_adxcvr +up_rx_addr_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_15,$/;" p module:util_adxcvr +up_rx_addr_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_2,$/;" p module:util_adxcvr +up_rx_addr_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_3,$/;" p module:util_adxcvr +up_rx_addr_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_4,$/;" p module:util_adxcvr +up_rx_addr_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_5,$/;" p module:util_adxcvr +up_rx_addr_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_6,$/;" p module:util_adxcvr +up_rx_addr_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_7,$/;" p module:util_adxcvr +up_rx_addr_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_8,$/;" p module:util_adxcvr +up_rx_addr_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_rx_addr_9,$/;" p module:util_adxcvr +up_rx_enb adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_rx_enb,$/;" p module:util_adxcvr_xch +up_rx_enb_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_0,$/;" p module:util_adxcvr +up_rx_enb_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_1,$/;" p module:util_adxcvr +up_rx_enb_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_10,$/;" p module:util_adxcvr +up_rx_enb_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_11,$/;" p module:util_adxcvr +up_rx_enb_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_12,$/;" p module:util_adxcvr +up_rx_enb_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_13,$/;" p module:util_adxcvr +up_rx_enb_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_14,$/;" p module:util_adxcvr +up_rx_enb_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_15,$/;" p module:util_adxcvr +up_rx_enb_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_2,$/;" p module:util_adxcvr +up_rx_enb_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_3,$/;" p module:util_adxcvr +up_rx_enb_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_4,$/;" p module:util_adxcvr +up_rx_enb_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_5,$/;" p module:util_adxcvr +up_rx_enb_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_6,$/;" p module:util_adxcvr +up_rx_enb_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_7,$/;" p module:util_adxcvr +up_rx_enb_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_8,$/;" p module:util_adxcvr +up_rx_enb_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_enb_9,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_rx_lpm_dfe_n,$/;" p module:util_adxcvr_xch +up_rx_lpm_dfe_n_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_0,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_1,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_10,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_11,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_12,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_13,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_14,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_15,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_2,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_3,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_4,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_5,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_6,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_7,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_8,$/;" p module:util_adxcvr +up_rx_lpm_dfe_n_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_lpm_dfe_n_9,$/;" p module:util_adxcvr +up_rx_out_clk_sel adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [ 2:0] up_rx_out_clk_sel,$/;" p module:util_adxcvr_xch +up_rx_out_clk_sel_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_0,$/;" p module:util_adxcvr +up_rx_out_clk_sel_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_1,$/;" p module:util_adxcvr +up_rx_out_clk_sel_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_10,$/;" p module:util_adxcvr +up_rx_out_clk_sel_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_11,$/;" p module:util_adxcvr +up_rx_out_clk_sel_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_12,$/;" p module:util_adxcvr +up_rx_out_clk_sel_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_13,$/;" p module:util_adxcvr +up_rx_out_clk_sel_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_14,$/;" p module:util_adxcvr +up_rx_out_clk_sel_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_15,$/;" p module:util_adxcvr +up_rx_out_clk_sel_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_2,$/;" p module:util_adxcvr +up_rx_out_clk_sel_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_3,$/;" p module:util_adxcvr +up_rx_out_clk_sel_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_4,$/;" p module:util_adxcvr +up_rx_out_clk_sel_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_5,$/;" p module:util_adxcvr +up_rx_out_clk_sel_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_6,$/;" p module:util_adxcvr +up_rx_out_clk_sel_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_7,$/;" p module:util_adxcvr +up_rx_out_clk_sel_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_8,$/;" p module:util_adxcvr +up_rx_out_clk_sel_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_out_clk_sel_9,$/;" p module:util_adxcvr +up_rx_pll_locked adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output up_rx_pll_locked,$/;" p module:util_adxcvr_xch +up_rx_pll_locked_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_0,$/;" p module:util_adxcvr +up_rx_pll_locked_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_1,$/;" p module:util_adxcvr +up_rx_pll_locked_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_10,$/;" p module:util_adxcvr +up_rx_pll_locked_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_11,$/;" p module:util_adxcvr +up_rx_pll_locked_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_12,$/;" p module:util_adxcvr +up_rx_pll_locked_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_13,$/;" p module:util_adxcvr +up_rx_pll_locked_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_14,$/;" p module:util_adxcvr +up_rx_pll_locked_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_15,$/;" p module:util_adxcvr +up_rx_pll_locked_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_2,$/;" p module:util_adxcvr +up_rx_pll_locked_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_3,$/;" p module:util_adxcvr +up_rx_pll_locked_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_4,$/;" p module:util_adxcvr +up_rx_pll_locked_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_5,$/;" p module:util_adxcvr +up_rx_pll_locked_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_6,$/;" p module:util_adxcvr +up_rx_pll_locked_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_7,$/;" p module:util_adxcvr +up_rx_pll_locked_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_8,$/;" p module:util_adxcvr +up_rx_pll_locked_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_pll_locked_9,$/;" p module:util_adxcvr +up_rx_pll_locked_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_rx_pll_locked_s;$/;" n module:axi_xcvrlb_1 +up_rx_rate adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [ 2:0] up_rx_rate,$/;" p module:util_adxcvr_xch +up_rx_rate_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_0,$/;" p module:util_adxcvr +up_rx_rate_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_1,$/;" p module:util_adxcvr +up_rx_rate_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_10,$/;" p module:util_adxcvr +up_rx_rate_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_11,$/;" p module:util_adxcvr +up_rx_rate_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_12,$/;" p module:util_adxcvr +up_rx_rate_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_13,$/;" p module:util_adxcvr +up_rx_rate_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_14,$/;" p module:util_adxcvr +up_rx_rate_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_15,$/;" p module:util_adxcvr +up_rx_rate_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_2,$/;" p module:util_adxcvr +up_rx_rate_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_3,$/;" p module:util_adxcvr +up_rx_rate_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_4,$/;" p module:util_adxcvr +up_rx_rate_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_5,$/;" p module:util_adxcvr +up_rx_rate_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_6,$/;" p module:util_adxcvr +up_rx_rate_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_7,$/;" p module:util_adxcvr +up_rx_rate_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_8,$/;" p module:util_adxcvr +up_rx_rate_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_rx_rate_9,$/;" p module:util_adxcvr +up_rx_rdata adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output [15:0] up_rx_rdata,$/;" p module:util_adxcvr_xch +up_rx_rdata_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_0,$/;" p module:util_adxcvr +up_rx_rdata_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_1,$/;" p module:util_adxcvr +up_rx_rdata_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_10,$/;" p module:util_adxcvr +up_rx_rdata_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_11,$/;" p module:util_adxcvr +up_rx_rdata_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_12,$/;" p module:util_adxcvr +up_rx_rdata_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_13,$/;" p module:util_adxcvr +up_rx_rdata_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_14,$/;" p module:util_adxcvr +up_rx_rdata_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_15,$/;" p module:util_adxcvr +up_rx_rdata_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_2,$/;" p module:util_adxcvr +up_rx_rdata_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_3,$/;" p module:util_adxcvr +up_rx_rdata_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_4,$/;" p module:util_adxcvr +up_rx_rdata_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_5,$/;" p module:util_adxcvr +up_rx_rdata_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_6,$/;" p module:util_adxcvr +up_rx_rdata_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_7,$/;" p module:util_adxcvr +up_rx_rdata_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_8,$/;" p module:util_adxcvr +up_rx_rdata_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_rx_rdata_9,$/;" p module:util_adxcvr +up_rx_rdata_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [15:0] up_rx_rdata_int = 'd0;$/;" r module:util_adxcvr_xch +up_rx_ready adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output up_rx_ready,$/;" p module:util_adxcvr_xch +up_rx_ready_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_0,$/;" p module:util_adxcvr +up_rx_ready_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_1,$/;" p module:util_adxcvr +up_rx_ready_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_10,$/;" p module:util_adxcvr +up_rx_ready_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_11,$/;" p module:util_adxcvr +up_rx_ready_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_12,$/;" p module:util_adxcvr +up_rx_ready_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_13,$/;" p module:util_adxcvr +up_rx_ready_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_14,$/;" p module:util_adxcvr +up_rx_ready_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_15,$/;" p module:util_adxcvr +up_rx_ready_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_2,$/;" p module:util_adxcvr +up_rx_ready_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_3,$/;" p module:util_adxcvr +up_rx_ready_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_4,$/;" p module:util_adxcvr +up_rx_ready_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_5,$/;" p module:util_adxcvr +up_rx_ready_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_6,$/;" p module:util_adxcvr +up_rx_ready_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_7,$/;" p module:util_adxcvr +up_rx_ready_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_8,$/;" p module:util_adxcvr +up_rx_ready_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_ready_9,$/;" p module:util_adxcvr +up_rx_ready_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg up_rx_ready_int = 'd0;$/;" r module:util_adxcvr_xch +up_rx_rst adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_rx_rst,$/;" p module:util_adxcvr_xch +up_rx_rst_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_0,$/;" p module:util_adxcvr +up_rx_rst_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_1,$/;" p module:util_adxcvr +up_rx_rst_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_10,$/;" p module:util_adxcvr +up_rx_rst_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_11,$/;" p module:util_adxcvr +up_rx_rst_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_12,$/;" p module:util_adxcvr +up_rx_rst_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_13,$/;" p module:util_adxcvr +up_rx_rst_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_14,$/;" p module:util_adxcvr +up_rx_rst_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_15,$/;" p module:util_adxcvr +up_rx_rst_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_2,$/;" p module:util_adxcvr +up_rx_rst_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_3,$/;" p module:util_adxcvr +up_rx_rst_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_4,$/;" p module:util_adxcvr +up_rx_rst_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_5,$/;" p module:util_adxcvr +up_rx_rst_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_6,$/;" p module:util_adxcvr +up_rx_rst_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_7,$/;" p module:util_adxcvr +up_rx_rst_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_8,$/;" p module:util_adxcvr +up_rx_rst_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_rst_9,$/;" p module:util_adxcvr +up_rx_rst_done adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output up_rx_rst_done,$/;" p module:util_adxcvr_xch +up_rx_rst_done_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_0,$/;" p module:util_adxcvr +up_rx_rst_done_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_1,$/;" p module:util_adxcvr +up_rx_rst_done_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_10,$/;" p module:util_adxcvr +up_rx_rst_done_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_11,$/;" p module:util_adxcvr +up_rx_rst_done_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_12,$/;" p module:util_adxcvr +up_rx_rst_done_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_13,$/;" p module:util_adxcvr +up_rx_rst_done_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_14,$/;" p module:util_adxcvr +up_rx_rst_done_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_15,$/;" p module:util_adxcvr +up_rx_rst_done_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_2,$/;" p module:util_adxcvr +up_rx_rst_done_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_3,$/;" p module:util_adxcvr +up_rx_rst_done_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_4,$/;" p module:util_adxcvr +up_rx_rst_done_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_5,$/;" p module:util_adxcvr +up_rx_rst_done_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_6,$/;" p module:util_adxcvr +up_rx_rst_done_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_7,$/;" p module:util_adxcvr +up_rx_rst_done_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_8,$/;" p module:util_adxcvr +up_rx_rst_done_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_rx_rst_done_9,$/;" p module:util_adxcvr +up_rx_rst_done_m1 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg up_rx_rst_done_m1 = 'd0;$/;" r module:util_adxcvr_xch +up_rx_rst_done_m2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg up_rx_rst_done_m2 = 'd0;$/;" r module:util_adxcvr_xch +up_rx_rst_done_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_rx_rst_done_s;$/;" n module:axi_xcvrlb_1 +up_rx_sys_clk_sel adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [ 1:0] up_rx_sys_clk_sel,$/;" p module:util_adxcvr_xch +up_rx_sys_clk_sel_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_0,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_1,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_10,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_11,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_12,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_13,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_14,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_15,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_2,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_3,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_4,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_5,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_6,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_7,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_8,$/;" p module:util_adxcvr +up_rx_sys_clk_sel_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_rx_sys_clk_sel_9,$/;" p module:util_adxcvr +up_rx_user_ready adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_rx_user_ready,$/;" p module:util_adxcvr_xch +up_rx_user_ready_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_0,$/;" p module:util_adxcvr +up_rx_user_ready_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_1,$/;" p module:util_adxcvr +up_rx_user_ready_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_10,$/;" p module:util_adxcvr +up_rx_user_ready_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_11,$/;" p module:util_adxcvr +up_rx_user_ready_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_12,$/;" p module:util_adxcvr +up_rx_user_ready_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_13,$/;" p module:util_adxcvr +up_rx_user_ready_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_14,$/;" p module:util_adxcvr +up_rx_user_ready_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_15,$/;" p module:util_adxcvr +up_rx_user_ready_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_2,$/;" p module:util_adxcvr +up_rx_user_ready_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_3,$/;" p module:util_adxcvr +up_rx_user_ready_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_4,$/;" p module:util_adxcvr +up_rx_user_ready_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_5,$/;" p module:util_adxcvr +up_rx_user_ready_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_6,$/;" p module:util_adxcvr +up_rx_user_ready_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_7,$/;" p module:util_adxcvr +up_rx_user_ready_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_8,$/;" p module:util_adxcvr +up_rx_user_ready_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_user_ready_9,$/;" p module:util_adxcvr +up_rx_wdata adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [15:0] up_rx_wdata,$/;" p module:util_adxcvr_xch +up_rx_wdata_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_0,$/;" p module:util_adxcvr +up_rx_wdata_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_1,$/;" p module:util_adxcvr +up_rx_wdata_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_10,$/;" p module:util_adxcvr +up_rx_wdata_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_11,$/;" p module:util_adxcvr +up_rx_wdata_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_12,$/;" p module:util_adxcvr +up_rx_wdata_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_13,$/;" p module:util_adxcvr +up_rx_wdata_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_14,$/;" p module:util_adxcvr +up_rx_wdata_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_15,$/;" p module:util_adxcvr +up_rx_wdata_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_2,$/;" p module:util_adxcvr +up_rx_wdata_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_3,$/;" p module:util_adxcvr +up_rx_wdata_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_4,$/;" p module:util_adxcvr +up_rx_wdata_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_5,$/;" p module:util_adxcvr +up_rx_wdata_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_6,$/;" p module:util_adxcvr +up_rx_wdata_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_7,$/;" p module:util_adxcvr +up_rx_wdata_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_8,$/;" p module:util_adxcvr +up_rx_wdata_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_rx_wdata_9,$/;" p module:util_adxcvr +up_rx_wr adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_rx_wr,$/;" p module:util_adxcvr_xch +up_rx_wr_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_0,$/;" p module:util_adxcvr +up_rx_wr_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_1,$/;" p module:util_adxcvr +up_rx_wr_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_10,$/;" p module:util_adxcvr +up_rx_wr_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_11,$/;" p module:util_adxcvr +up_rx_wr_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_12,$/;" p module:util_adxcvr +up_rx_wr_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_13,$/;" p module:util_adxcvr +up_rx_wr_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_14,$/;" p module:util_adxcvr +up_rx_wr_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_15,$/;" p module:util_adxcvr +up_rx_wr_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_2,$/;" p module:util_adxcvr +up_rx_wr_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_3,$/;" p module:util_adxcvr +up_rx_wr_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_4,$/;" p module:util_adxcvr +up_rx_wr_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_5,$/;" p module:util_adxcvr +up_rx_wr_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_6,$/;" p module:util_adxcvr +up_rx_wr_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_7,$/;" p module:util_adxcvr +up_rx_wr_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_8,$/;" p module:util_adxcvr +up_rx_wr_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_rx_wr_9,$/;" p module:util_adxcvr +up_scratch adi_library/axi_dmac/axi_dmac_regmap.v /^reg [31:0] up_scratch = 32'h00;$/;" r module:axi_dmac_regmap +up_scratch adi_library/common/up_adc_common.v /^ reg [31:0] up_scratch = 'd0;$/;" r module:up_adc_common +up_scratch adi_library/common/up_clkgen.v /^ reg [31:0] up_scratch = 'd0;$/;" r module:up_clkgen +up_scratch adi_library/common/up_dac_common.v /^ reg [31:0] up_scratch = 'd0;$/;" r module:up_dac_common +up_scratch adi_library/common/up_hdmi_rx.v /^ reg [31:0] up_scratch = 'd0;$/;" r module:up_hdmi_rx +up_scratch adi_library/common/up_hdmi_tx.v /^ reg [31:0] up_scratch = 'd0;$/;" r module:up_hdmi_tx +up_scratch adi_library/common/up_pmod.v /^ reg [31:0] up_scratch = 'd0;$/;" r module:up_pmod +up_scratch adi_library/common/up_tdd_cntrl.v /^ reg [31:0] up_scratch = 32'h0;$/;" r module:up_tdd_cntrl +up_scratch adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg [31:0] up_scratch = 'h00;$/;" r module:axi_spi_engine +up_scratch adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [31:0] up_scratch = 'd0;$/;" r module:axi_adxcvr_up +up_scratch adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ reg [31:0] up_scratch = 'd0;$/;" r module:axi_xcvrlb +up_sdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [15:0] up_sdata = 'd0;$/;" r module:axi_adxcvr_es +up_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v /^ input [ 7:0] up_sel,$/;" p module:axi_adxcvr_mdrp +up_sel_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [ 2:0] up_sel_int = 'd0;$/;" r module:util_adxcvr_xch +up_sel_int adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ reg up_sel_int = 'd0;$/;" r module:util_adxcvr_xcm +up_sot adi_library/axi_dmac/axi_dmac_regmap.v /^wire up_sot; \/\/ Asserted for one cycle when a transfer has been queued$/;" n module:axi_dmac_regmap +up_sot adi_library/axi_dmac/axi_dmac_regmap_request.v /^ output up_sot,$/;" p module:axi_dmac_regmap_request +up_srcsel adi_library/common/up_hdmi_tx.v /^ reg [ 1:0] up_srcsel = 'd1;$/;" r module:up_hdmi_tx +up_ss_bypass adi_library/common/up_hdmi_tx.v /^ reg up_ss_bypass = 'd0;$/;" r module:up_hdmi_tx +up_start_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ wire up_start_s;$/;" n module:axi_adxcvr_es +up_status adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ output up_status,$/;" p module:axi_adxcvr +up_status adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg up_status = 'd0;$/;" r module:axi_adxcvr_es +up_status adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_status,$/;" p module:axi_adxcvr_up +up_status adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ reg [31:0] up_status = 'd0;$/;" r module:axi_xcvrlb +up_status adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ output up_status,$/;" p module:axi_xcvrlb_1 +up_status_int adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_status_int = 'd0;$/;" r module:axi_adxcvr_up +up_status_int adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg up_status_int = 'd1;$/;" r module:axi_xcvrlb_1 +up_status_or adi_library/common/up_adc_common.v /^ input up_status_or,$/;" p module:up_adc_common +up_status_ovf adi_library/common/up_adc_common.v /^ reg up_status_ovf = 'd0;$/;" r module:up_adc_common +up_status_ovf_s adi_library/common/up_adc_common.v /^ wire up_status_ovf_s;$/;" n module:up_adc_common +up_status_pn_err adi_library/common/up_adc_common.v /^ input up_status_pn_err,$/;" p module:up_adc_common +up_status_pn_oos adi_library/common/up_adc_common.v /^ input up_status_pn_oos,$/;" p module:up_adc_common +up_status_s adi_library/common/up_adc_common.v /^ wire up_status_s;$/;" n module:up_adc_common +up_status_s adi_library/common/up_dac_common.v /^ wire up_status_s;$/;" n module:up_dac_common +up_status_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ wire [31:0] up_status_s;$/;" n module:axi_xcvrlb +up_status_unf adi_library/common/up_dac_common.v /^ reg up_status_unf = 'd0;$/;" r module:up_dac_common +up_status_unf_s adi_library/common/up_dac_common.v /^ wire up_status_unf_s;$/;" n module:up_dac_common +up_sw_reset adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg up_sw_reset = 1'b1;$/;" r module:axi_spi_engine +up_sw_resetn adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire up_sw_resetn = ~up_sw_reset;$/;" n module:axi_spi_engine +up_sync_in_status adi_library/common/up_dac_common.v /^ wire up_sync_in_status;$/;" n module:up_dac_common +up_sync_status_s adi_library/common/up_adc_common.v /^ wire up_sync_status_s;$/;" n module:up_adc_common +up_sys_clk_sel adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 1:0] up_sys_clk_sel = SYS_CLK_SEL;$/;" r module:axi_adxcvr_up +up_tdd_burst_count adi_library/common/up_tdd_cntrl.v /^ reg [ 7:0] up_tdd_burst_count = 8'h0;$/;" r module:up_tdd_cntrl +up_tdd_cntrl adi_library/common/up_tdd_cntrl.v /^module up_tdd_cntrl #($/;" m +up_tdd_counter_init adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_counter_init = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_enable adi_library/common/up_tdd_cntrl.v /^ reg up_tdd_enable = 1'h0;$/;" r module:up_tdd_cntrl +up_tdd_frame_length adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_frame_length = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_gated_rx_dmapath adi_library/common/up_tdd_cntrl.v /^ reg up_tdd_gated_rx_dmapath = 1'h0;$/;" r module:up_tdd_cntrl +up_tdd_gated_tx_dmapath adi_library/common/up_tdd_cntrl.v /^ reg up_tdd_gated_tx_dmapath = 1'h0;$/;" r module:up_tdd_cntrl +up_tdd_rx_dp_off_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_rx_dp_off_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_rx_dp_off_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_rx_dp_off_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_rx_dp_on_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_rx_dp_on_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_rx_dp_on_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_rx_dp_on_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_rx_off_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_rx_off_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_rx_off_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_rx_off_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_rx_on_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_rx_on_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_rx_on_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_rx_on_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_rx_only adi_library/common/up_tdd_cntrl.v /^ reg up_tdd_rx_only = 1'h0;$/;" r module:up_tdd_cntrl +up_tdd_secondary adi_library/common/up_tdd_cntrl.v /^ reg up_tdd_secondary = 1'h0;$/;" r module:up_tdd_cntrl +up_tdd_status_s adi_library/common/up_tdd_cntrl.v /^ wire [ 7:0] up_tdd_status_s;$/;" n module:up_tdd_cntrl +up_tdd_terminal_type adi_library/common/up_tdd_cntrl.v /^ reg up_tdd_terminal_type = 1'h0;$/;" r module:up_tdd_cntrl +up_tdd_tx_dp_off_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_tx_dp_off_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_tx_dp_off_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_tx_dp_off_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_tx_dp_on_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_tx_dp_on_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_tx_dp_on_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_tx_dp_on_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_tx_off_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_tx_off_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_tx_off_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_tx_off_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_tx_on_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_tx_on_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_tx_on_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_tx_on_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_tx_only adi_library/common/up_tdd_cntrl.v /^ reg up_tdd_tx_only = 1'h0;$/;" r module:up_tdd_cntrl +up_tdd_vco_rx_off_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_vco_rx_off_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_vco_rx_off_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_vco_rx_off_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_vco_rx_on_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_vco_rx_on_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_vco_rx_on_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_vco_rx_on_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_vco_tx_off_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_vco_tx_off_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_vco_tx_off_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_vco_tx_off_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_vco_tx_on_1 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_vco_tx_on_1 = 24'h0;$/;" r module:up_tdd_cntrl +up_tdd_vco_tx_on_2 adi_library/common/up_tdd_cntrl.v /^ reg [23:0] up_tdd_vco_tx_on_2 = 24'h0;$/;" r module:up_tdd_cntrl +up_timer adi_library/common/up_adc_common.v /^ reg [31:0] up_timer = 'd0;$/;" r module:up_adc_common +up_timer adi_library/common/up_dac_common.v /^ reg [31:0] up_timer = 'd0;$/;" r module:up_dac_common +up_tlf_data adi_library/axi_dmac/axi_dmac_regmap_request.v /^wire [MEASURED_LENGTH_WIDTH+2-1:0] up_tlf_data;$/;" n module:axi_dmac_regmap_request +up_tlf_rd adi_library/axi_dmac/axi_dmac_regmap_request.v /^wire up_tlf_rd;$/;" n module:axi_dmac_regmap_request +up_tlf_s_ready adi_library/axi_dmac/axi_dmac_regmap_request.v /^wire up_tlf_s_ready;$/;" n module:axi_dmac_regmap_request +up_tlf_s_valid adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg up_tlf_s_valid = 1'b0;$/;" r module:axi_dmac_regmap_request +up_tlf_valid adi_library/axi_dmac/axi_dmac_regmap_request.v /^wire up_tlf_valid;$/;" n module:axi_dmac_regmap_request +up_tpm_oos adi_library/common/up_hdmi_rx.v /^ reg up_tpm_oos = 'd0;$/;" r module:up_hdmi_rx +up_transfer_done_bitmap adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg [3:0] up_transfer_done_bitmap = 4'b0;$/;" r module:axi_dmac_regmap_request +up_transfer_id adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg [1:0] up_transfer_id = 2'b0;$/;" r module:axi_dmac_regmap_request +up_transfer_id_eot adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg [1:0] up_transfer_id_eot = 2'b0;$/;" r module:axi_dmac_regmap_request +up_transfer_id_eot_d adi_library/axi_dmac/axi_dmac_regmap_request.v /^reg [1:0] up_transfer_id_eot_d = 'h0;$/;" r module:axi_dmac_regmap_request +up_tx_addr adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [11:0] up_tx_addr,$/;" p module:util_adxcvr_xch +up_tx_addr_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_0,$/;" p module:util_adxcvr +up_tx_addr_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_1,$/;" p module:util_adxcvr +up_tx_addr_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_10,$/;" p module:util_adxcvr +up_tx_addr_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_11,$/;" p module:util_adxcvr +up_tx_addr_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_12,$/;" p module:util_adxcvr +up_tx_addr_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_13,$/;" p module:util_adxcvr +up_tx_addr_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_14,$/;" p module:util_adxcvr +up_tx_addr_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_15,$/;" p module:util_adxcvr +up_tx_addr_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_2,$/;" p module:util_adxcvr +up_tx_addr_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_3,$/;" p module:util_adxcvr +up_tx_addr_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_4,$/;" p module:util_adxcvr +up_tx_addr_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_5,$/;" p module:util_adxcvr +up_tx_addr_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_6,$/;" p module:util_adxcvr +up_tx_addr_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_7,$/;" p module:util_adxcvr +up_tx_addr_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_8,$/;" p module:util_adxcvr +up_tx_addr_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [11:0] up_tx_addr_9,$/;" p module:util_adxcvr +up_tx_diffctrl adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 4:0] up_tx_diffctrl = TX_DIFFCTRL;$/;" r module:axi_adxcvr_up +up_tx_diffctrl adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [ 4:0] up_tx_diffctrl,$/;" p module:util_adxcvr_xch +up_tx_diffctrl_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_0,$/;" p module:util_adxcvr +up_tx_diffctrl_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_1,$/;" p module:util_adxcvr +up_tx_diffctrl_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_10,$/;" p module:util_adxcvr +up_tx_diffctrl_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_11,$/;" p module:util_adxcvr +up_tx_diffctrl_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_12,$/;" p module:util_adxcvr +up_tx_diffctrl_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_13,$/;" p module:util_adxcvr +up_tx_diffctrl_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_14,$/;" p module:util_adxcvr +up_tx_diffctrl_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_15,$/;" p module:util_adxcvr +up_tx_diffctrl_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_2,$/;" p module:util_adxcvr +up_tx_diffctrl_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_3,$/;" p module:util_adxcvr +up_tx_diffctrl_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_4,$/;" p module:util_adxcvr +up_tx_diffctrl_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_5,$/;" p module:util_adxcvr +up_tx_diffctrl_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_6,$/;" p module:util_adxcvr +up_tx_diffctrl_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_7,$/;" p module:util_adxcvr +up_tx_diffctrl_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_8,$/;" p module:util_adxcvr +up_tx_diffctrl_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_diffctrl_9,$/;" p module:util_adxcvr +up_tx_enb adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_tx_enb,$/;" p module:util_adxcvr_xch +up_tx_enb_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_0,$/;" p module:util_adxcvr +up_tx_enb_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_1,$/;" p module:util_adxcvr +up_tx_enb_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_10,$/;" p module:util_adxcvr +up_tx_enb_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_11,$/;" p module:util_adxcvr +up_tx_enb_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_12,$/;" p module:util_adxcvr +up_tx_enb_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_13,$/;" p module:util_adxcvr +up_tx_enb_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_14,$/;" p module:util_adxcvr +up_tx_enb_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_15,$/;" p module:util_adxcvr +up_tx_enb_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_2,$/;" p module:util_adxcvr +up_tx_enb_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_3,$/;" p module:util_adxcvr +up_tx_enb_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_4,$/;" p module:util_adxcvr +up_tx_enb_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_5,$/;" p module:util_adxcvr +up_tx_enb_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_6,$/;" p module:util_adxcvr +up_tx_enb_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_7,$/;" p module:util_adxcvr +up_tx_enb_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_8,$/;" p module:util_adxcvr +up_tx_enb_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_enb_9,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_tx_lpm_dfe_n,$/;" p module:util_adxcvr_xch +up_tx_lpm_dfe_n_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_0,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_1,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_10,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_11,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_12,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_13,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_14,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_15,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_2,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_3,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_4,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_5,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_6,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_7,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_8,$/;" p module:util_adxcvr +up_tx_lpm_dfe_n_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_lpm_dfe_n_9,$/;" p module:util_adxcvr +up_tx_out_clk_sel adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [ 2:0] up_tx_out_clk_sel,$/;" p module:util_adxcvr_xch +up_tx_out_clk_sel_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_0,$/;" p module:util_adxcvr +up_tx_out_clk_sel_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_1,$/;" p module:util_adxcvr +up_tx_out_clk_sel_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_10,$/;" p module:util_adxcvr +up_tx_out_clk_sel_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_11,$/;" p module:util_adxcvr +up_tx_out_clk_sel_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_12,$/;" p module:util_adxcvr +up_tx_out_clk_sel_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_13,$/;" p module:util_adxcvr +up_tx_out_clk_sel_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_14,$/;" p module:util_adxcvr +up_tx_out_clk_sel_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_15,$/;" p module:util_adxcvr +up_tx_out_clk_sel_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_2,$/;" p module:util_adxcvr +up_tx_out_clk_sel_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_3,$/;" p module:util_adxcvr +up_tx_out_clk_sel_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_4,$/;" p module:util_adxcvr +up_tx_out_clk_sel_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_5,$/;" p module:util_adxcvr +up_tx_out_clk_sel_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_6,$/;" p module:util_adxcvr +up_tx_out_clk_sel_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_7,$/;" p module:util_adxcvr +up_tx_out_clk_sel_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_8,$/;" p module:util_adxcvr +up_tx_out_clk_sel_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_out_clk_sel_9,$/;" p module:util_adxcvr +up_tx_pll_locked adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output up_tx_pll_locked,$/;" p module:util_adxcvr_xch +up_tx_pll_locked_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_0,$/;" p module:util_adxcvr +up_tx_pll_locked_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_1,$/;" p module:util_adxcvr +up_tx_pll_locked_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_10,$/;" p module:util_adxcvr +up_tx_pll_locked_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_11,$/;" p module:util_adxcvr +up_tx_pll_locked_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_12,$/;" p module:util_adxcvr +up_tx_pll_locked_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_13,$/;" p module:util_adxcvr +up_tx_pll_locked_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_14,$/;" p module:util_adxcvr +up_tx_pll_locked_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_15,$/;" p module:util_adxcvr +up_tx_pll_locked_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_2,$/;" p module:util_adxcvr +up_tx_pll_locked_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_3,$/;" p module:util_adxcvr +up_tx_pll_locked_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_4,$/;" p module:util_adxcvr +up_tx_pll_locked_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_5,$/;" p module:util_adxcvr +up_tx_pll_locked_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_6,$/;" p module:util_adxcvr +up_tx_pll_locked_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_7,$/;" p module:util_adxcvr +up_tx_pll_locked_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_8,$/;" p module:util_adxcvr +up_tx_pll_locked_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_pll_locked_9,$/;" p module:util_adxcvr +up_tx_pll_locked_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_tx_pll_locked_s;$/;" n module:axi_xcvrlb_1 +up_tx_postcursor adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 4:0] up_tx_postcursor = TX_POSTCURSOR;$/;" r module:axi_adxcvr_up +up_tx_postcursor adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [ 4:0] up_tx_postcursor,$/;" p module:util_adxcvr_xch +up_tx_postcursor_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_0,$/;" p module:util_adxcvr +up_tx_postcursor_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_1,$/;" p module:util_adxcvr +up_tx_postcursor_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_10,$/;" p module:util_adxcvr +up_tx_postcursor_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_11,$/;" p module:util_adxcvr +up_tx_postcursor_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_12,$/;" p module:util_adxcvr +up_tx_postcursor_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_13,$/;" p module:util_adxcvr +up_tx_postcursor_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_14,$/;" p module:util_adxcvr +up_tx_postcursor_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_15,$/;" p module:util_adxcvr +up_tx_postcursor_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_2,$/;" p module:util_adxcvr +up_tx_postcursor_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_3,$/;" p module:util_adxcvr +up_tx_postcursor_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_4,$/;" p module:util_adxcvr +up_tx_postcursor_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_5,$/;" p module:util_adxcvr +up_tx_postcursor_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_6,$/;" p module:util_adxcvr +up_tx_postcursor_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_7,$/;" p module:util_adxcvr +up_tx_postcursor_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_8,$/;" p module:util_adxcvr +up_tx_postcursor_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_postcursor_9,$/;" p module:util_adxcvr +up_tx_precursor adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 4:0] up_tx_precursor = TX_PRECURSOR;$/;" r module:axi_adxcvr_up +up_tx_precursor adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [ 4:0] up_tx_precursor,$/;" p module:util_adxcvr_xch +up_tx_precursor_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_0,$/;" p module:util_adxcvr +up_tx_precursor_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_1,$/;" p module:util_adxcvr +up_tx_precursor_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_10,$/;" p module:util_adxcvr +up_tx_precursor_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_11,$/;" p module:util_adxcvr +up_tx_precursor_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_12,$/;" p module:util_adxcvr +up_tx_precursor_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_13,$/;" p module:util_adxcvr +up_tx_precursor_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_14,$/;" p module:util_adxcvr +up_tx_precursor_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_15,$/;" p module:util_adxcvr +up_tx_precursor_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_2,$/;" p module:util_adxcvr +up_tx_precursor_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_3,$/;" p module:util_adxcvr +up_tx_precursor_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_4,$/;" p module:util_adxcvr +up_tx_precursor_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_5,$/;" p module:util_adxcvr +up_tx_precursor_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_6,$/;" p module:util_adxcvr +up_tx_precursor_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_7,$/;" p module:util_adxcvr +up_tx_precursor_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_8,$/;" p module:util_adxcvr +up_tx_precursor_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 4:0] up_tx_precursor_9,$/;" p module:util_adxcvr +up_tx_rate adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [ 2:0] up_tx_rate,$/;" p module:util_adxcvr_xch +up_tx_rate_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_0,$/;" p module:util_adxcvr +up_tx_rate_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_1,$/;" p module:util_adxcvr +up_tx_rate_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_10,$/;" p module:util_adxcvr +up_tx_rate_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_11,$/;" p module:util_adxcvr +up_tx_rate_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_12,$/;" p module:util_adxcvr +up_tx_rate_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_13,$/;" p module:util_adxcvr +up_tx_rate_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_14,$/;" p module:util_adxcvr +up_tx_rate_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_15,$/;" p module:util_adxcvr +up_tx_rate_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_2,$/;" p module:util_adxcvr +up_tx_rate_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_3,$/;" p module:util_adxcvr +up_tx_rate_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_4,$/;" p module:util_adxcvr +up_tx_rate_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_5,$/;" p module:util_adxcvr +up_tx_rate_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_6,$/;" p module:util_adxcvr +up_tx_rate_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_7,$/;" p module:util_adxcvr +up_tx_rate_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_8,$/;" p module:util_adxcvr +up_tx_rate_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 2:0] up_tx_rate_9,$/;" p module:util_adxcvr +up_tx_rdata adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output [15:0] up_tx_rdata,$/;" p module:util_adxcvr_xch +up_tx_rdata_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_0,$/;" p module:util_adxcvr +up_tx_rdata_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_1,$/;" p module:util_adxcvr +up_tx_rdata_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_10,$/;" p module:util_adxcvr +up_tx_rdata_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_11,$/;" p module:util_adxcvr +up_tx_rdata_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_12,$/;" p module:util_adxcvr +up_tx_rdata_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_13,$/;" p module:util_adxcvr +up_tx_rdata_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_14,$/;" p module:util_adxcvr +up_tx_rdata_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_15,$/;" p module:util_adxcvr +up_tx_rdata_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_2,$/;" p module:util_adxcvr +up_tx_rdata_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_3,$/;" p module:util_adxcvr +up_tx_rdata_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_4,$/;" p module:util_adxcvr +up_tx_rdata_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_5,$/;" p module:util_adxcvr +up_tx_rdata_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_6,$/;" p module:util_adxcvr +up_tx_rdata_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_7,$/;" p module:util_adxcvr +up_tx_rdata_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_8,$/;" p module:util_adxcvr +up_tx_rdata_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [15:0] up_tx_rdata_9,$/;" p module:util_adxcvr +up_tx_rdata_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [15:0] up_tx_rdata_int = 'd0;$/;" r module:util_adxcvr_xch +up_tx_ready adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output up_tx_ready);$/;" p module:util_adxcvr_xch +up_tx_ready_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_0,$/;" p module:util_adxcvr +up_tx_ready_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_1,$/;" p module:util_adxcvr +up_tx_ready_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_10,$/;" p module:util_adxcvr +up_tx_ready_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_11,$/;" p module:util_adxcvr +up_tx_ready_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_12,$/;" p module:util_adxcvr +up_tx_ready_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_13,$/;" p module:util_adxcvr +up_tx_ready_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_14,$/;" p module:util_adxcvr +up_tx_ready_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_15);$/;" p module:util_adxcvr +up_tx_ready_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_2,$/;" p module:util_adxcvr +up_tx_ready_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_3,$/;" p module:util_adxcvr +up_tx_ready_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_4,$/;" p module:util_adxcvr +up_tx_ready_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_5,$/;" p module:util_adxcvr +up_tx_ready_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_6,$/;" p module:util_adxcvr +up_tx_ready_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_7,$/;" p module:util_adxcvr +up_tx_ready_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_8,$/;" p module:util_adxcvr +up_tx_ready_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_ready_9,$/;" p module:util_adxcvr +up_tx_ready_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg up_tx_ready_int = 'd0;$/;" r module:util_adxcvr_xch +up_tx_rst adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_tx_rst,$/;" p module:util_adxcvr_xch +up_tx_rst_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_0,$/;" p module:util_adxcvr +up_tx_rst_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_1,$/;" p module:util_adxcvr +up_tx_rst_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_10,$/;" p module:util_adxcvr +up_tx_rst_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_11,$/;" p module:util_adxcvr +up_tx_rst_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_12,$/;" p module:util_adxcvr +up_tx_rst_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_13,$/;" p module:util_adxcvr +up_tx_rst_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_14,$/;" p module:util_adxcvr +up_tx_rst_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_15,$/;" p module:util_adxcvr +up_tx_rst_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_2,$/;" p module:util_adxcvr +up_tx_rst_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_3,$/;" p module:util_adxcvr +up_tx_rst_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_4,$/;" p module:util_adxcvr +up_tx_rst_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_5,$/;" p module:util_adxcvr +up_tx_rst_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_6,$/;" p module:util_adxcvr +up_tx_rst_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_7,$/;" p module:util_adxcvr +up_tx_rst_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_8,$/;" p module:util_adxcvr +up_tx_rst_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_rst_9,$/;" p module:util_adxcvr +up_tx_rst_done adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output up_tx_rst_done,$/;" p module:util_adxcvr_xch +up_tx_rst_done_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_0,$/;" p module:util_adxcvr +up_tx_rst_done_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_1,$/;" p module:util_adxcvr +up_tx_rst_done_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_10,$/;" p module:util_adxcvr +up_tx_rst_done_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_11,$/;" p module:util_adxcvr +up_tx_rst_done_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_12,$/;" p module:util_adxcvr +up_tx_rst_done_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_13,$/;" p module:util_adxcvr +up_tx_rst_done_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_14,$/;" p module:util_adxcvr +up_tx_rst_done_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_15,$/;" p module:util_adxcvr +up_tx_rst_done_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_2,$/;" p module:util_adxcvr +up_tx_rst_done_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_3,$/;" p module:util_adxcvr +up_tx_rst_done_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_4,$/;" p module:util_adxcvr +up_tx_rst_done_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_5,$/;" p module:util_adxcvr +up_tx_rst_done_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_6,$/;" p module:util_adxcvr +up_tx_rst_done_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_7,$/;" p module:util_adxcvr +up_tx_rst_done_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_8,$/;" p module:util_adxcvr +up_tx_rst_done_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output up_tx_rst_done_9,$/;" p module:util_adxcvr +up_tx_rst_done_m1 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg up_tx_rst_done_m1 = 'd0;$/;" r module:util_adxcvr_xch +up_tx_rst_done_m2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg up_tx_rst_done_m2 = 'd0;$/;" r module:util_adxcvr_xch +up_tx_rst_done_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_tx_rst_done_s;$/;" n module:axi_xcvrlb_1 +up_tx_sys_clk_sel adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [ 1:0] up_tx_sys_clk_sel,$/;" p module:util_adxcvr_xch +up_tx_sys_clk_sel_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_0,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_1,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_10,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_11,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_12,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_13,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_14,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_15,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_2,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_3,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_4,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_5,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_6,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_7,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_8,$/;" p module:util_adxcvr +up_tx_sys_clk_sel_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [ 1:0] up_tx_sys_clk_sel_9,$/;" p module:util_adxcvr +up_tx_user_ready adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_tx_user_ready,$/;" p module:util_adxcvr_xch +up_tx_user_ready_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_0,$/;" p module:util_adxcvr +up_tx_user_ready_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_1,$/;" p module:util_adxcvr +up_tx_user_ready_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_10,$/;" p module:util_adxcvr +up_tx_user_ready_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_11,$/;" p module:util_adxcvr +up_tx_user_ready_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_12,$/;" p module:util_adxcvr +up_tx_user_ready_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_13,$/;" p module:util_adxcvr +up_tx_user_ready_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_14,$/;" p module:util_adxcvr +up_tx_user_ready_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_15,$/;" p module:util_adxcvr +up_tx_user_ready_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_2,$/;" p module:util_adxcvr +up_tx_user_ready_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_3,$/;" p module:util_adxcvr +up_tx_user_ready_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_4,$/;" p module:util_adxcvr +up_tx_user_ready_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_5,$/;" p module:util_adxcvr +up_tx_user_ready_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_6,$/;" p module:util_adxcvr +up_tx_user_ready_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_7,$/;" p module:util_adxcvr +up_tx_user_ready_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_8,$/;" p module:util_adxcvr +up_tx_user_ready_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_user_ready_9,$/;" p module:util_adxcvr +up_tx_wdata adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input [15:0] up_tx_wdata,$/;" p module:util_adxcvr_xch +up_tx_wdata_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_0,$/;" p module:util_adxcvr +up_tx_wdata_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_1,$/;" p module:util_adxcvr +up_tx_wdata_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_10,$/;" p module:util_adxcvr +up_tx_wdata_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_11,$/;" p module:util_adxcvr +up_tx_wdata_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_12,$/;" p module:util_adxcvr +up_tx_wdata_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_13,$/;" p module:util_adxcvr +up_tx_wdata_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_14,$/;" p module:util_adxcvr +up_tx_wdata_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_15,$/;" p module:util_adxcvr +up_tx_wdata_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_2,$/;" p module:util_adxcvr +up_tx_wdata_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_3,$/;" p module:util_adxcvr +up_tx_wdata_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_4,$/;" p module:util_adxcvr +up_tx_wdata_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_5,$/;" p module:util_adxcvr +up_tx_wdata_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_6,$/;" p module:util_adxcvr +up_tx_wdata_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_7,$/;" p module:util_adxcvr +up_tx_wdata_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_8,$/;" p module:util_adxcvr +up_tx_wdata_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input [15:0] up_tx_wdata_9,$/;" p module:util_adxcvr +up_tx_wr adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ input up_tx_wr,$/;" p module:util_adxcvr_xch +up_tx_wr_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_0,$/;" p module:util_adxcvr +up_tx_wr_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_1,$/;" p module:util_adxcvr +up_tx_wr_10 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_10,$/;" p module:util_adxcvr +up_tx_wr_11 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_11,$/;" p module:util_adxcvr +up_tx_wr_12 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_12,$/;" p module:util_adxcvr +up_tx_wr_13 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_13,$/;" p module:util_adxcvr +up_tx_wr_14 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_14,$/;" p module:util_adxcvr +up_tx_wr_15 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_15,$/;" p module:util_adxcvr +up_tx_wr_2 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_2,$/;" p module:util_adxcvr +up_tx_wr_3 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_3,$/;" p module:util_adxcvr +up_tx_wr_4 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_4,$/;" p module:util_adxcvr +up_tx_wr_5 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_5,$/;" p module:util_adxcvr +up_tx_wr_6 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_6,$/;" p module:util_adxcvr +up_tx_wr_7 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_7,$/;" p module:util_adxcvr +up_tx_wr_8 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_8,$/;" p module:util_adxcvr +up_tx_wr_9 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ input up_tx_wr_9,$/;" p module:util_adxcvr +up_user_ready_cnt adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg [ 6:0] up_user_ready_cnt = 'd0;$/;" r module:axi_adxcvr_up +up_user_ready_cnt adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ reg [ 6:0] up_user_ready_cnt = 'd0;$/;" r module:axi_xcvrlb_1 +up_user_ready_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire up_user_ready_s;$/;" n module:axi_xcvrlb_1 +up_usr_chanmax adi_library/common/up_dac_common.v /^ output [ 7:0] up_usr_chanmax,$/;" p module:up_dac_common +up_usr_chanmax_in adi_library/common/up_adc_common.v /^ input [ 7:0] up_usr_chanmax_in,$/;" p module:up_adc_common +up_usr_chanmax_int adi_library/common/up_adc_common.v /^ reg [ 7:0] up_usr_chanmax_int = 'd0;$/;" r module:up_adc_common +up_usr_chanmax_int adi_library/common/up_dac_common.v /^ reg [ 7:0] up_usr_chanmax_int = 'd0;$/;" r module:up_dac_common +up_usr_chanmax_out adi_library/common/up_adc_common.v /^ output [ 7:0] up_usr_chanmax_out,$/;" p module:up_adc_common +up_usr_datatype_be adi_library/common/up_adc_channel.v /^ output up_usr_datatype_be,$/;" p module:up_adc_channel +up_usr_datatype_be adi_library/common/up_dac_channel.v /^ output up_usr_datatype_be,$/;" p module:up_dac_channel +up_usr_datatype_be_int adi_library/common/up_adc_channel.v /^ reg up_usr_datatype_be_int = 'd0;$/;" r module:up_adc_channel +up_usr_datatype_be_int adi_library/common/up_dac_channel.v /^ reg up_usr_datatype_be_int = 'd0;$/;" r module:up_dac_channel +up_usr_datatype_bits adi_library/common/up_adc_channel.v /^ output [ 7:0] up_usr_datatype_bits,$/;" p module:up_adc_channel +up_usr_datatype_bits adi_library/common/up_dac_channel.v /^ output [ 7:0] up_usr_datatype_bits,$/;" p module:up_dac_channel +up_usr_datatype_bits_int adi_library/common/up_adc_channel.v /^ reg [ 7:0] up_usr_datatype_bits_int = 'd0;$/;" r module:up_adc_channel +up_usr_datatype_bits_int adi_library/common/up_dac_channel.v /^ reg [ 7:0] up_usr_datatype_bits_int = 'd0;$/;" r module:up_dac_channel +up_usr_datatype_shift adi_library/common/up_adc_channel.v /^ output [ 7:0] up_usr_datatype_shift,$/;" p module:up_adc_channel +up_usr_datatype_shift adi_library/common/up_dac_channel.v /^ output [ 7:0] up_usr_datatype_shift,$/;" p module:up_dac_channel +up_usr_datatype_shift_int adi_library/common/up_adc_channel.v /^ reg [ 7:0] up_usr_datatype_shift_int = 'd0;$/;" r module:up_adc_channel +up_usr_datatype_shift_int adi_library/common/up_dac_channel.v /^ reg [ 7:0] up_usr_datatype_shift_int = 'd0;$/;" r module:up_dac_channel +up_usr_datatype_signed adi_library/common/up_adc_channel.v /^ output up_usr_datatype_signed,$/;" p module:up_adc_channel +up_usr_datatype_signed adi_library/common/up_dac_channel.v /^ output up_usr_datatype_signed,$/;" p module:up_dac_channel +up_usr_datatype_signed_int adi_library/common/up_adc_channel.v /^ reg up_usr_datatype_signed_int = 'd0;$/;" r module:up_adc_channel +up_usr_datatype_signed_int adi_library/common/up_dac_channel.v /^ reg up_usr_datatype_signed_int = 'd0;$/;" r module:up_dac_channel +up_usr_datatype_total_bits adi_library/common/up_adc_channel.v /^ output [ 7:0] up_usr_datatype_total_bits,$/;" p module:up_adc_channel +up_usr_datatype_total_bits adi_library/common/up_dac_channel.v /^ output [ 7:0] up_usr_datatype_total_bits,$/;" p module:up_dac_channel +up_usr_datatype_total_bits_int adi_library/common/up_adc_channel.v /^ reg [ 7:0] up_usr_datatype_total_bits_int = 'd0;$/;" r module:up_adc_channel +up_usr_datatype_total_bits_int adi_library/common/up_dac_channel.v /^ reg [ 7:0] up_usr_datatype_total_bits_int = 'd0;$/;" r module:up_dac_channel +up_usr_decimation_m adi_library/common/up_adc_channel.v /^ output [15:0] up_usr_decimation_m,$/;" p module:up_adc_channel +up_usr_decimation_m_int adi_library/common/up_adc_channel.v /^ reg [15:0] up_usr_decimation_m_int = 'd0;$/;" r module:up_adc_channel +up_usr_decimation_n adi_library/common/up_adc_channel.v /^ output [15:0] up_usr_decimation_n,$/;" p module:up_adc_channel +up_usr_decimation_n_int adi_library/common/up_adc_channel.v /^ reg [15:0] up_usr_decimation_n_int = 'd0;$/;" r module:up_adc_channel +up_usr_interpolation_m adi_library/common/up_dac_channel.v /^ output [15:0] up_usr_interpolation_m,$/;" p module:up_dac_channel +up_usr_interpolation_m_int adi_library/common/up_dac_channel.v /^ reg [15:0] up_usr_interpolation_m_int = 'd0;$/;" r module:up_dac_channel +up_usr_interpolation_n adi_library/common/up_dac_channel.v /^ output [15:0] up_usr_interpolation_n,$/;" p module:up_dac_channel +up_usr_interpolation_n_int adi_library/common/up_dac_channel.v /^ reg [15:0] up_usr_interpolation_n_int = 'd0;$/;" r module:up_dac_channel +up_ut adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg up_ut = 'd0;$/;" r module:axi_adxcvr_es +up_ut_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ wire up_ut_s;$/;" n module:axi_adxcvr_es +up_vdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [15:0] up_vdata = 'd0;$/;" r module:axi_adxcvr_es +up_vdma_ovf adi_library/common/up_hdmi_tx.v /^ reg up_vdma_ovf = 'd0;$/;" r module:up_hdmi_tx +up_vdma_ovf_s adi_library/common/up_hdmi_tx.v /^ wire up_vdma_ovf_s;$/;" n module:up_hdmi_tx +up_vdma_tpm_oos adi_library/common/up_hdmi_tx.v /^ reg up_vdma_tpm_oos = 'd0;$/;" r module:up_hdmi_tx +up_vdma_tpm_oos_s adi_library/common/up_hdmi_tx.v /^ wire up_vdma_tpm_oos_s;$/;" n module:up_hdmi_tx +up_vdma_unf adi_library/common/up_hdmi_tx.v /^ reg up_vdma_unf = 'd0;$/;" r module:up_hdmi_tx +up_vdma_unf_s adi_library/common/up_hdmi_tx.v /^ wire up_vdma_unf_s;$/;" n module:up_hdmi_tx +up_ve_max adi_library/common/up_hdmi_tx.v /^ reg [15:0] up_ve_max = 'd0;$/;" r module:up_hdmi_tx +up_ve_min adi_library/common/up_hdmi_tx.v /^ reg [15:0] up_ve_min = 'd0;$/;" r module:up_hdmi_tx +up_vf_active adi_library/common/up_hdmi_tx.v /^ reg [15:0] up_vf_active = 'd0;$/;" r module:up_hdmi_tx +up_vf_width adi_library/common/up_hdmi_tx.v /^ reg [15:0] up_vf_width = 'd0;$/;" r module:up_hdmi_tx +up_vindex adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [ 7:0] up_vindex = 'd0;$/;" r module:axi_adxcvr_es +up_vindex_m_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ wire [ 7:0] up_vindex_m_s;$/;" n module:axi_adxcvr_es +up_vindex_n_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ wire [ 7:0] up_vindex_n_s;$/;" n module:axi_adxcvr_es +up_vindex_s adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ wire [ 7:0] up_vindex_s;$/;" n module:axi_adxcvr_es +up_vs_count adi_library/common/up_hdmi_rx.v /^ reg [15:0] up_vs_count = 'd0;$/;" r module:up_hdmi_rx +up_vs_mismatch adi_library/common/up_hdmi_rx.v /^ reg up_vs_mismatch = 'd0;$/;" r module:up_hdmi_rx +up_vs_mismatch_s adi_library/common/up_hdmi_rx.v /^ wire up_vs_mismatch_s;$/;" n module:up_hdmi_rx +up_vs_oos adi_library/common/up_hdmi_rx.v /^ reg up_vs_oos = 'd0;$/;" r module:up_hdmi_rx +up_vs_oos_s adi_library/common/up_hdmi_rx.v /^ wire up_vs_oos_s;$/;" n module:up_hdmi_rx +up_vs_s adi_library/common/up_hdmi_rx.v /^ wire [15:0] up_vs_s;$/;" n module:up_hdmi_rx +up_vs_width adi_library/common/up_hdmi_tx.v /^ reg [15:0] up_vs_width = 'd0;$/;" r module:up_hdmi_tx +up_wack adi_library/axi_dmac/axi_dmac_regmap.v /^reg up_wack = 1'b0;$/;" r module:axi_dmac_regmap +up_wack adi_library/common/up_adc_channel.v /^ output up_wack,$/;" p module:up_adc_channel +up_wack adi_library/common/up_adc_common.v /^ output up_wack,$/;" p module:up_adc_common +up_wack adi_library/common/up_axi.v /^ input up_wack,$/;" p module:up_axi +up_wack adi_library/common/up_clkgen.v /^ output reg up_wack,$/;" p module:up_clkgen +up_wack adi_library/common/up_dac_channel.v /^ output up_wack,$/;" p module:up_dac_channel +up_wack adi_library/common/up_dac_common.v /^ output up_wack,$/;" p module:up_dac_common +up_wack adi_library/common/up_delay_cntrl.v /^ output up_wack,$/;" p module:up_delay_cntrl +up_wack adi_library/common/up_hdmi_rx.v /^ output reg up_wack,$/;" p module:up_hdmi_rx +up_wack adi_library/common/up_hdmi_tx.v /^ output reg up_wack,$/;" p module:up_hdmi_tx +up_wack adi_library/common/up_pmod.v /^ output reg up_wack,$/;" p module:up_pmod +up_wack adi_library/common/up_tdd_cntrl.v /^ output reg up_wack,$/;" p module:up_tdd_cntrl +up_wack adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output up_wack,$/;" p module:axi_spi_engine +up_wack adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_wack;$/;" n module:axi_adxcvr +up_wack adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ output up_wack,$/;" p module:axi_adxcvr_up +up_wack adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ reg up_wack = 'd0;$/;" r module:axi_xcvrlb +up_wack hdl/phy_control.v /^ wire up_wack;$/;" n module:phy_control +up_wack hdl/up_axi.v /^ input up_wack,$/;" p module:up_axi +up_wack_d adi_library/common/up_axi.v /^ reg up_wack_d = 'd0;$/;" r module:up_axi +up_wack_d hdl/up_axi.v /^ reg up_wack_d = 'd0;$/;" r module:up_axi +up_wack_ff adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ reg up_wack_ff = 1'b0;$/;" r module:axi_spi_engine +up_wack_ff hdl/phy_control.v /^ reg up_wack_ff = 1'b0;$/;" r module:phy_control +up_wack_int adi_library/common/up_adc_channel.v /^ reg up_wack_int = 'd0;$/;" r module:up_adc_channel +up_wack_int adi_library/common/up_adc_common.v /^ reg up_wack_int = 'd0;$/;" r module:up_adc_common +up_wack_int adi_library/common/up_dac_channel.v /^ reg up_wack_int = 'd0;$/;" r module:up_dac_channel +up_wack_int adi_library/common/up_dac_common.v /^ reg up_wack_int = 'd0;$/;" r module:up_dac_common +up_wack_int adi_library/common/up_delay_cntrl.v /^ reg up_wack_int = 'd0;$/;" r module:up_delay_cntrl +up_wack_rcv hdl/phy_control.v /^ wire up_wack_rcv;$/;" n module:phy_control +up_wack_s adi_library/common/up_axi.v /^ wire up_wack_s;$/;" n module:up_axi +up_wack_s hdl/up_axi.v /^ wire up_wack_s;$/;" n module:up_axi +up_wack_send hdl/phy_control.v /^ reg up_wack_send = 1'b0;$/;" r module:phy_control +up_waddr adi_library/axi_dmac/axi_dmac_regmap.v /^wire [8:0] up_waddr;$/;" n module:axi_dmac_regmap +up_waddr adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input [8:0] up_waddr,$/;" p module:axi_dmac_regmap_request +up_waddr adi_library/common/up_adc_channel.v /^ input [13:0] up_waddr,$/;" p module:up_adc_channel +up_waddr adi_library/common/up_adc_common.v /^ input [13:0] up_waddr,$/;" p module:up_adc_common +up_waddr adi_library/common/up_axi.v /^ output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,$/;" p module:up_axi +up_waddr adi_library/common/up_clkgen.v /^ input [13:0] up_waddr,$/;" p module:up_clkgen +up_waddr adi_library/common/up_dac_channel.v /^ input [13:0] up_waddr,$/;" p module:up_dac_channel +up_waddr adi_library/common/up_dac_common.v /^ input [13:0] up_waddr,$/;" p module:up_dac_common +up_waddr adi_library/common/up_delay_cntrl.v /^ input [13:0] up_waddr,$/;" p module:up_delay_cntrl +up_waddr adi_library/common/up_hdmi_rx.v /^ input [13:0] up_waddr,$/;" p module:up_hdmi_rx +up_waddr adi_library/common/up_hdmi_tx.v /^ input [13:0] up_waddr,$/;" p module:up_hdmi_tx +up_waddr adi_library/common/up_pmod.v /^ input [13:0] up_waddr,$/;" p module:up_pmod +up_waddr adi_library/common/up_tdd_cntrl.v /^ input [13:0] up_waddr,$/;" p module:up_tdd_cntrl +up_waddr adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [13:0] up_waddr,$/;" p module:axi_spi_engine +up_waddr adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [ 9:0] up_waddr;$/;" n module:axi_adxcvr +up_waddr adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input [ 9:0] up_waddr,$/;" p module:axi_adxcvr_up +up_waddr hdl/phy_control.v /^ wire [(AXI_ADDRESS_WIDTH-3):0] up_waddr;$/;" n module:phy_control +up_waddr hdl/up_axi.v /^ output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,$/;" p module:up_axi +up_waddr_int adi_library/common/up_axi.v /^ reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;$/;" r module:up_axi +up_waddr_int hdl/up_axi.v /^ reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;$/;" r module:up_axi +up_waddr_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [13:0] up_waddr_s;$/;" n module:axi_spi_engine +up_waddr_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ wire [ 7:0] up_waddr_s;$/;" n module:axi_xcvrlb +up_waddr_s hdl/phy_control.v /^ wire [(AXI_ADDRESS_WIDTH-3):0] up_waddr_s;$/;" n module:phy_control +up_wcount adi_library/common/up_axi.v /^ reg [ 4:0] up_wcount = 'd0;$/;" r module:up_axi +up_wcount hdl/up_axi.v /^ reg [ 5:0] up_wcount = 'd0;$/;" r module:up_axi +up_wdata adi_library/axi_dmac/axi_dmac_regmap.v /^wire [31:0] up_wdata;$/;" n module:axi_dmac_regmap +up_wdata adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input [31:0] up_wdata,$/;" p module:axi_dmac_regmap_request +up_wdata adi_library/common/up_adc_channel.v /^ input [31:0] up_wdata,$/;" p module:up_adc_channel +up_wdata adi_library/common/up_adc_common.v /^ input [31:0] up_wdata,$/;" p module:up_adc_common +up_wdata adi_library/common/up_axi.v /^ output [31:0] up_wdata,$/;" p module:up_axi +up_wdata adi_library/common/up_clkgen.v /^ input [31:0] up_wdata,$/;" p module:up_clkgen +up_wdata adi_library/common/up_dac_channel.v /^ input [31:0] up_wdata,$/;" p module:up_dac_channel +up_wdata adi_library/common/up_dac_common.v /^ input [31:0] up_wdata,$/;" p module:up_dac_common +up_wdata adi_library/common/up_delay_cntrl.v /^ input [31:0] up_wdata,$/;" p module:up_delay_cntrl +up_wdata adi_library/common/up_hdmi_rx.v /^ input [31:0] up_wdata,$/;" p module:up_hdmi_rx +up_wdata adi_library/common/up_hdmi_tx.v /^ input [31:0] up_wdata,$/;" p module:up_hdmi_tx +up_wdata adi_library/common/up_pmod.v /^ input [31:0] up_wdata,$/;" p module:up_pmod +up_wdata adi_library/common/up_tdd_cntrl.v /^ input [31:0] up_wdata,$/;" p module:up_tdd_cntrl +up_wdata adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input [31:0] up_wdata,$/;" p module:axi_spi_engine +up_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire [31:0] up_wdata;$/;" n module:axi_adxcvr +up_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg [31:0] up_wdata = 'd0;$/;" r module:axi_adxcvr_es +up_wdata adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input [31:0] up_wdata,$/;" p module:axi_adxcvr_up +up_wdata hdl/phy_control.v /^ wire [ 31:0] up_wdata;$/;" n module:phy_control +up_wdata hdl/up_axi.v /^ output [ 31:0] up_wdata,$/;" p module:up_axi +up_wdata_int adi_library/common/up_axi.v /^ reg [31:0] up_wdata_int = 'd0;$/;" r module:up_axi +up_wdata_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [15:0] up_wdata_int = 'd0;$/;" r module:util_adxcvr_xch +up_wdata_int adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ reg [15:0] up_wdata_int = 'd0;$/;" r module:util_adxcvr_xcm +up_wdata_int hdl/up_axi.v /^ reg [ 31:0] up_wdata_int = 'd0;$/;" r module:up_axi +up_wdata_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire [31:0] up_wdata_s;$/;" n module:axi_spi_engine +up_wdata_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ wire [31:0] up_wdata_s;$/;" n module:axi_xcvrlb +up_wdata_s hdl/phy_control.v /^ wire [ 31:0] up_wdata_s;$/;" n module:phy_control +up_wr adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg up_wr = 'd0;$/;" r module:axi_adxcvr_es +up_wr_int adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg up_wr_int = 'd0;$/;" r module:util_adxcvr_xch +up_wr_int adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^ reg up_wr_int = 'd0;$/;" r module:util_adxcvr_xcm +up_wreq adi_library/axi_dmac/axi_dmac_regmap.v /^wire up_wreq;$/;" n module:axi_dmac_regmap +up_wreq adi_library/axi_dmac/axi_dmac_regmap_request.v /^ input up_wreq,$/;" p module:axi_dmac_regmap_request +up_wreq adi_library/common/up_adc_channel.v /^ input up_wreq,$/;" p module:up_adc_channel +up_wreq adi_library/common/up_adc_common.v /^ input up_wreq,$/;" p module:up_adc_common +up_wreq adi_library/common/up_axi.v /^ output up_wreq,$/;" p module:up_axi +up_wreq adi_library/common/up_clkgen.v /^ input up_wreq,$/;" p module:up_clkgen +up_wreq adi_library/common/up_dac_channel.v /^ input up_wreq,$/;" p module:up_dac_channel +up_wreq adi_library/common/up_dac_common.v /^ input up_wreq,$/;" p module:up_dac_common +up_wreq adi_library/common/up_delay_cntrl.v /^ input up_wreq,$/;" p module:up_delay_cntrl +up_wreq adi_library/common/up_hdmi_rx.v /^ input up_wreq,$/;" p module:up_hdmi_rx +up_wreq adi_library/common/up_hdmi_tx.v /^ input up_wreq,$/;" p module:up_hdmi_tx +up_wreq adi_library/common/up_pmod.v /^ input up_wreq,$/;" p module:up_pmod +up_wreq adi_library/common/up_tdd_cntrl.v /^ input up_wreq,$/;" p module:up_tdd_cntrl +up_wreq adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ input up_wreq,$/;" p module:axi_spi_engine +up_wreq adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ wire up_wreq;$/;" n module:axi_adxcvr +up_wreq adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ input up_wreq,$/;" p module:axi_adxcvr_up +up_wreq hdl/phy_control.v /^ wire up_wreq;$/;" n module:phy_control +up_wreq hdl/up_axi.v /^ output up_wreq,$/;" p module:up_axi +up_wreq_d adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ reg up_wreq_d = 'd0;$/;" r module:axi_adxcvr_up +up_wreq_int adi_library/common/up_axi.v /^ reg up_wreq_int = 'd0;$/;" r module:up_axi +up_wreq_int hdl/up_axi.v /^ reg up_wreq_int = 'd0;$/;" r module:up_axi +up_wreq_rcv hdl/phy_control.v /^ wire up_wreq_rcv;$/;" n module:phy_control +up_wreq_s adi_library/common/up_adc_channel.v /^ wire up_wreq_s;$/;" n module:up_adc_channel +up_wreq_s adi_library/common/up_adc_common.v /^ wire up_wreq_s;$/;" n module:up_adc_common +up_wreq_s adi_library/common/up_clkgen.v /^ wire up_wreq_s;$/;" n module:up_clkgen +up_wreq_s adi_library/common/up_dac_channel.v /^ wire up_wreq_s;$/;" n module:up_dac_channel +up_wreq_s adi_library/common/up_dac_common.v /^ wire up_wreq_s;$/;" n module:up_dac_common +up_wreq_s adi_library/common/up_delay_cntrl.v /^ wire up_wreq_s;$/;" n module:up_delay_cntrl +up_wreq_s adi_library/common/up_hdmi_rx.v /^ wire up_wreq_s;$/;" n module:up_hdmi_rx +up_wreq_s adi_library/common/up_hdmi_tx.v /^ wire up_wreq_s;$/;" n module:up_hdmi_tx +up_wreq_s adi_library/common/up_pmod.v /^ wire up_wreq_s;$/;" n module:up_pmod +up_wreq_s adi_library/common/up_tdd_cntrl.v /^ wire up_wreq_s;$/;" n module:up_tdd_cntrl +up_wreq_s adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ wire up_wreq_s;$/;" n module:axi_spi_engine +up_wreq_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v /^ wire up_wreq_s;$/;" n module:axi_xcvrlb +up_wreq_s hdl/phy_control.v /^ wire up_wreq_s;$/;" n module:phy_control +up_wreq_send hdl/phy_control.v /^ reg up_wreq_send = 1'b0;$/;" r module:phy_control +up_wsel adi_library/common/up_axi.v /^ reg up_wsel = 'd0;$/;" r module:up_axi +up_wsel hdl/up_axi.v /^ reg up_wsel = 'd0;$/;" r module:up_axi +up_wvalid adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v /^ reg up_wvalid = 'd0;$/;" r module:axi_adxcvr_es +up_xfer_cntrl adi_library/common/up_xfer_cntrl.v /^module up_xfer_cntrl #($/;" m +up_xfer_count adi_library/common/up_xfer_cntrl.v /^ reg [ 5:0] up_xfer_count = 'd0;$/;" r module:up_xfer_cntrl +up_xfer_data adi_library/common/up_xfer_cntrl.v /^ reg [(DATA_WIDTH-1):0] up_xfer_data = 'd0;$/;" r module:up_xfer_cntrl +up_xfer_done adi_library/common/up_xfer_cntrl.v /^ output up_xfer_done,$/;" p module:up_xfer_cntrl +up_xfer_done_int adi_library/common/up_xfer_cntrl.v /^ reg up_xfer_done_int = 'd0;$/;" r module:up_xfer_cntrl +up_xfer_done_s adi_library/common/up_dac_common.v /^ wire up_xfer_done_s;$/;" n module:up_dac_common +up_xfer_enable_s adi_library/common/up_xfer_cntrl.v /^ wire up_xfer_enable_s;$/;" n module:up_xfer_cntrl +up_xfer_state adi_library/common/up_xfer_cntrl.v /^ reg up_xfer_state = 'd0;$/;" r module:up_xfer_cntrl +up_xfer_state_m1 adi_library/common/up_xfer_cntrl.v /^ reg up_xfer_state_m1 = 'd0;$/;" r module:up_xfer_cntrl +up_xfer_state_m2 adi_library/common/up_xfer_cntrl.v /^ reg up_xfer_state_m2 = 'd0;$/;" r module:up_xfer_cntrl +up_xfer_status adi_library/common/up_xfer_status.v /^module up_xfer_status #($/;" m +up_xfer_toggle adi_library/common/up_xfer_cntrl.v /^ reg up_xfer_toggle = 'd0;$/;" r module:up_xfer_cntrl +up_xfer_toggle adi_library/common/up_xfer_status.v /^ reg up_xfer_toggle = 'd0;$/;" r module:up_xfer_status +up_xfer_toggle_m1 adi_library/common/up_xfer_status.v /^ reg up_xfer_toggle_m1 = 'd0;$/;" r module:up_xfer_status +up_xfer_toggle_m2 adi_library/common/up_xfer_status.v /^ reg up_xfer_toggle_m2 = 'd0;$/;" r module:up_xfer_status +up_xfer_toggle_m3 adi_library/common/up_xfer_status.v /^ reg up_xfer_toggle_m3 = 'd0;$/;" r module:up_xfer_status +up_xfer_toggle_s adi_library/common/up_xfer_status.v /^ wire up_xfer_toggle_s;$/;" n module:up_xfer_status +upack2_underflow_tb adi_library/util_pack/tb/underflow_tb.v /^module upack2_underflow_tb;$/;" m +upack_tb adi_library/util_pack/tb/upack_tb.v /^module upack_tb;$/;" m +updata_s hdl/DDS_compensate.v /^ wire [DDS_width:0] updata_s;$/;" n module:DDS_compensate +util_adcfifo adi_library/util_adcfifo/util_adcfifo.v /^module util_adcfifo #($/;" m +util_adxcvr adi_library/xilinx/util_adxcvr/util_adxcvr.v /^module util_adxcvr #($/;" m +util_adxcvr_xch adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^module util_adxcvr_xch #($/;" m +util_adxcvr_xcm adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v /^module util_adxcvr_xcm #($/;" m +util_axis_fifo adi_library/util_axis_fifo/util_axis_fifo.v /^module util_axis_fifo #($/;" m +util_axis_resize adi_library/util_axis_resize/util_axis_resize.v /^module util_axis_resize # ($/;" m +util_axis_upscale adi_library/common/util_axis_upscale.v /^module util_axis_upscale # ($/;" m +util_bsplit adi_library/util_bsplit/util_bsplit.v /^module util_bsplit #($/;" m +util_clkdiv adi_library/xilinx/util_clkdiv/util_clkdiv.v /^module util_clkdiv ($/;" m +util_cpack2 adi_library/util_pack/util_cpack2/util_cpack2.v /^module util_cpack2 #($/;" m +util_cpack2_impl adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^module util_cpack2_impl #($/;" m +util_dacfifo adi_library/util_dacfifo/util_dacfifo.v /^module util_dacfifo #($/;" m +util_dacfifo_bypass adi_library/util_dacfifo/util_dacfifo_bypass.v /^module util_dacfifo_bypass #($/;" m +util_dec256sinc24b adi_library/common/util_dec256sinc24b.v /^module util_dec256sinc24b ($/;" m +util_delay adi_library/common/util_delay.v /^module util_delay #($/;" m +util_extract adi_library/util_extract/util_extract.v /^module util_extract #($/;" m +util_fir_dec adi_library/util_fir_dec/util_fir_dec.v /^module util_fir_dec ($/;" m +util_fir_int adi_library/util_fir_int/util_fir_int.v /^module util_fir_int ($/;" m +util_gmii_to_rgmii adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^module util_gmii_to_rgmii #($/;" m +util_mfifo adi_library/util_mfifo/util_mfifo.v /^module util_mfifo #($/;" m +util_pulse_gen adi_library/common/util_pulse_gen.v /^module util_pulse_gen #($/;" m +util_rfifo adi_library/util_rfifo/util_rfifo.v /^module util_rfifo #($/;" m +util_sigma_delta_spi adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v /^module util_sigma_delta_spi #($/;" m +util_tdd_sync adi_library/util_tdd_sync/util_tdd_sync.v /^module util_tdd_sync #($/;" m +util_upack2 adi_library/util_pack/util_upack2/util_upack2.v /^module util_upack2 #($/;" m +util_upack2_impl adi_library/util_pack/util_upack2/util_upack2_impl.v /^module util_upack2_impl #($/;" m +util_var_fifo adi_library/util_var_fifo/util_var_fifo.v /^module util_var_fifo #($/;" m +util_wfifo adi_library/util_wfifo/util_wfifo.v /^module util_wfifo #($/;" m +valid adi_library/axi_dmac/axi_dmac_resize_dest.v /^ reg valid = 1'b0;$/;" r module:axi_dmac_resize_dest +valid adi_library/axi_dmac/axi_dmac_resize_src.v /^ reg valid = 1'b0;$/;" r module:axi_dmac_resize_src +valid adi_library/axi_dmac/dest_fifo_inf.v /^ output reg valid,$/;" p module:dmac_dest_fifo_inf +valid adi_library/axi_dmac/src_fifo_inf.v /^wire valid;$/;" n module:dmac_src_fifo_inf +valid adi_library/axi_dmac/tb/axi_slave.v /^ input valid,$/;" p module:axi_slave +valid adi_library/common/ad_axis_inf_rx.v /^ input valid,$/;" p module:ad_axis_inf_rx +valid adi_library/common/ad_datafmt.v /^ input valid,$/;" p module:ad_datafmt +valid adi_library/common/ad_iqcor.v /^ input valid,$/;" p module:ad_iqcor +valid adi_library/util_axis_fifo/util_axis_fifo.v /^ reg valid;$/;" r module:util_axis_fifo +valid adi_library/util_axis_resize/util_axis_resize.v /^reg valid;$/;" r module:util_axis_resize +valid adi_library/util_pack/util_pack_common/pack_shell.v /^ reg [NUM_OF_SAMPLES-1:0] valid = 'h00;$/;" r block:pack_shell.gen_pack +valid adi_library/xilinx/common/ad_dcfilter.v /^ input valid,$/;" p module:ad_dcfilter +valid_2d adi_library/xilinx/common/ad_dcfilter.v /^ reg valid_2d = 'd0;$/;" r module:ad_dcfilter +valid_bytes adi_library/axi_dmac/axi_dmac_resize_src.v /^ reg [BYTES_PER_BEAT_WIDTH_SRC-1:0] valid_bytes = 'h00;$/;" r module:axi_dmac_resize_src +valid_d adi_library/xilinx/common/ad_dcfilter.v /^ reg valid_d = 'd0;$/;" r module:ad_dcfilter +valid_in_0 adi_library/common/ad_bus_mux.v /^ input valid_in_0,$/;" p module:ad_bus_mux +valid_in_1 adi_library/common/ad_bus_mux.v /^ input valid_in_1,$/;" p module:ad_bus_mux +valid_int adi_library/common/ad_datafmt.v /^ reg valid_int = 'd0;$/;" r module:ad_datafmt +valid_int adi_library/common/ad_iqcor.v /^ reg valid_int = 'd0;$/;" r block:ad_iqcor.g_loop +valid_int adi_library/xilinx/common/ad_dcfilter.v /^ reg valid_int = 'd0;$/;" r module:ad_dcfilter +valid_int_loc adi_library/common/ad_iqcor.v /^ wire [DPW-1:0] valid_int_loc;$/;" n module:ad_iqcor +valid_out adi_library/common/ad_bus_mux.v /^ output valid_out,$/;" p module:ad_bus_mux +valid_out adi_library/common/ad_datafmt.v /^ output valid_out,$/;" p module:ad_datafmt +valid_out adi_library/common/ad_iqcor.v /^ output valid_out,$/;" p module:ad_iqcor +valid_out adi_library/util_extract/util_extract.v /^ output reg valid_out,$/;" p module:util_extract +valid_out adi_library/xilinx/common/ad_dcfilter.v /^ output valid_out,$/;" p module:ad_dcfilter +validlength hdl/FrameMerge.v /^ reg [9:0] validlength = 10'd0;$/;" r module:FrameMerge +validnd_new hdl/FrameMerge.v /^ reg validnd_new = 1'b0;$/;" r module:FrameMerge +validnd_new_1d hdl/FrameMerge.v /^ reg validnd_new_1d = 1'b0;$/;" r module:FrameMerge +validnd_new_delay hdl/FrameMerge.v /^ wire validnd_new_delay;$/;" n module:FrameMerge +validnd_new_delay_d1 hdl/FrameMerge.v /^ reg validnd_new_delay_d1;$/;" r module:FrameMerge +validnd_new_new hdl/FrameMerge.v /^ output reg validnd_new_new = 1'b0,$/;" p module:FrameMerge +validnd_new_new hdl/RecvTop.v /^ wire validnd_new_new;$/;" n module:RecvTop +value adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] value;$/;" p task:dmac_regmap_tb.set_reset_reg_value +value adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] value;$/;" p task:dmac_regmap_tb.write_reg +value adi_library/axi_dmac/tb/regmap_tb.v /^ input [31:0] value;$/;" p task:dmac_regmap_tb.write_reg_and_update +value adi_library/axi_dmac/tb/regmap_tb.v /^ output [31:0] value;$/;" p task:dmac_regmap_tb.read_reg +value adi_library/axi_dmac/tb/regmap_tb.v /^ reg [31:0] value;$/;" r task:dmac_regmap_tb.invert_register +value adi_library/axi_dmac/tb/regmap_tb.v /^ reg [31:0] value;$/;" r task:dmac_regmap_tb.read_reg_check +value adi_library/common/ad_mem_asym.v /^ input integer value;$/;" p function:ad_mem_asym.clog2 +value adi_library/util_axis_resize/util_axis_resize.v /^ input integer value;$/;" p function:util_axis_resize.clog2 +vdma_clk adi_library/common/up_hdmi_tx.v /^ input vdma_clk,$/;" p module:up_hdmi_tx +vdma_ovf adi_library/common/up_hdmi_tx.v /^ input vdma_ovf,$/;" p module:up_hdmi_tx +vdma_rst adi_library/common/up_hdmi_tx.v /^ output vdma_rst,$/;" p module:up_hdmi_tx +vdma_tpm_oos adi_library/common/up_hdmi_tx.v /^ input vdma_tpm_oos,$/;" p module:up_hdmi_tx +vdma_unf adi_library/common/up_hdmi_tx.v /^ input vdma_unf,$/;" p module:up_hdmi_tx +vec_mag hdl/PAPR.v /^ input [MAG_WIDTH-1:0] vec_mag,$/;" p module:PAPR +vec_mag_1024 hdl/PAPR.v /^ wire [MAG_WIDTH-1:0] vec_mag_1024;$/;" n module:PAPR +vec_mag_d1 hdl/PAPR.v /^ reg [MAG_WIDTH-1:0] vec_mag_d1;$/;" r module:PAPR +vec_mag_d2 hdl/PAPR.v /^ reg [MAG_WIDTH-1:0] vec_mag_d2;$/;" r module:PAPR +vec_mag_d3 hdl/PAPR.v /^ reg [MAG_WIDTH-1:0] vec_mag_d3;$/;" r module:PAPR +vec_valid hdl/MagnitudeEstimator.v /^ input vec_valid,$/;" p module:MagnitudeEstimator +vec_valid_d1 hdl/MagnitudeEstimator.v /^ reg vec_valid_d1;$/;" r module:MagnitudeEstimator +vec_valid_d2 hdl/MagnitudeEstimator.v /^ reg vec_valid_d2;$/;" r module:MagnitudeEstimator +vio_powertest_h hdl/DAGC_v2.v /^ input [1:0] vio_powertest_h,$/;" p module:DAGC_v2 +vio_powertest_l hdl/DAGC_v2.v /^ input [1:0] vio_powertest_l,$/;" p module:DAGC_v2 +vio_stopbit hdl/FrameMerge.v /^ input [6:0] vio_stopbit,$/;" p module:FrameMerge +vio_stopbit hdl/RecvTop.v /^ input [6:0] vio_stopbit, \/\/寻找停止位，默认值为7'd60$/;" p module:RecvTop +vio_tsync_inter16 hdl/TimeSync_top.v /^ input vio_tsync_inter16,\/\/12.5$/;" p module:TimeSync_top +vtc_cnt adi_library/xilinx/common/ad_serdes_in.v /^ reg [4:0] vtc_cnt = {5{1'b1}};$/;" r block:ad_serdes_in.g_data +w adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam w = PORT_DATA_WIDTH;$/;" c module:pack_interconnect +w adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam w = SAMPLE_DATA_WIDTH;$/;" c block:pack_shell.gen_pack.gen_output_buffer.gen_out_data +waddr adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ reg [ADDRESS_WIDTH-1:0] waddr;$/;" r module:axi_dacfifo_address_buffer +wait_for_io adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg wait_for_io = 1'b0;$/;" r module:spi_engine_execution +wc_data_in hdl/enc_control.v /^ wire [ 31:0] wc_data_in;$/;" n module:enc_control +wc_data_in_ready hdl/enc_control.v /^ wire wc_data_in_ready;$/;" n module:enc_control +wc_data_in_valid hdl/enc_control.v /^ reg wc_data_in_valid;$/;" r module:enc_control +wc_data_out hdl/enc_control.v /^ wire wc_data_out;$/;" n module:enc_control +wc_data_out_valid hdl/enc_control.v /^ wire wc_data_out_valid;$/;" n module:enc_control +wcnt adi_library/common/ad_axis_inf_rx.v /^ reg [ 2:0] wcnt = 'd0;$/;" r module:ad_axis_inf_rx +wdata adi_library/axi_dmac/tb/axi_write_slave.v /^ input [DATA_WIDTH-1:0] wdata,$/;" p module:axi_write_slave +wdata adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire [31:0] wdata;$/;" n module:dmac_dma_write_shutdown_tb +wdata adi_library/axi_dmac/tb/dma_write_tb.v /^ wire [WIDTH_DEST-1:0] wdata;$/;" n module:dmac_dma_write_tb +wdata_0 adi_library/common/ad_axis_inf_rx.v /^ reg [(DATA_WIDTH-1):0] wdata_0 = 'd0;$/;" r module:ad_axis_inf_rx +wdata_1 adi_library/common/ad_axis_inf_rx.v /^ reg [(DATA_WIDTH-1):0] wdata_1 = 'd0;$/;" r module:ad_axis_inf_rx +wdata_2 adi_library/common/ad_axis_inf_rx.v /^ reg [(DATA_WIDTH-1):0] wdata_2 = 'd0;$/;" r module:ad_axis_inf_rx +wdata_3 adi_library/common/ad_axis_inf_rx.v /^ reg [(DATA_WIDTH-1):0] wdata_3 = 'd0;$/;" r module:ad_axis_inf_rx +wdata_4 adi_library/common/ad_axis_inf_rx.v /^ reg [(DATA_WIDTH-1):0] wdata_4 = 'd0;$/;" r module:ad_axis_inf_rx +wdata_5 adi_library/common/ad_axis_inf_rx.v /^ reg [(DATA_WIDTH-1):0] wdata_5 = 'd0;$/;" r module:ad_axis_inf_rx +wdata_6 adi_library/common/ad_axis_inf_rx.v /^ reg [(DATA_WIDTH-1):0] wdata_6 = 'd0;$/;" r module:ad_axis_inf_rx +wdata_7 adi_library/common/ad_axis_inf_rx.v /^ reg [(DATA_WIDTH-1):0] wdata_7 = 'd0;$/;" r module:ad_axis_inf_rx +we hdl/shift_reg.v /^ input we,$/;" p module:shift_reg +wea adi_library/common/ad_mem.v /^ input wea,$/;" p module:ad_mem +wea adi_library/common/ad_mem_asym.v /^ input wea,$/;" p module:ad_mem_asym +wea adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v /^ input wea,$/;" p module:axi_dacfifo_address_buffer +wea_01 hdl/freqestm.v /^ reg wea_01;$/;" r module:freqestm +wea_02 hdl/freqestm.v /^ reg wea_02;$/;" r module:freqestm +wea_1 hdl/DAGC_v2.v /^ reg wea_1 = 1'd0;$/;" r module:DAGC_v2 +wea_w adi_library/util_var_fifo/util_var_fifo.v /^ output wea_w,$/;" p module:util_var_fifo +width_convert hdl/width_convert.v /^module width_convert #($/;" m +wlast adi_library/axi_dmac/tb/axi_write_slave.v /^ input wlast,$/;" p module:axi_write_slave +wlast adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire wlast;$/;" n module:dmac_dma_write_shutdown_tb +wlast adi_library/axi_dmac/tb/dma_write_tb.v /^ wire wlast;$/;" n module:dmac_dma_write_tb +wlast_0 adi_library/common/ad_axis_inf_rx.v /^ reg wlast_0 = 'd0;$/;" r module:ad_axis_inf_rx +wlast_1 adi_library/common/ad_axis_inf_rx.v /^ reg wlast_1 = 'd0;$/;" r module:ad_axis_inf_rx +wlast_2 adi_library/common/ad_axis_inf_rx.v /^ reg wlast_2 = 'd0;$/;" r module:ad_axis_inf_rx +wlast_3 adi_library/common/ad_axis_inf_rx.v /^ reg wlast_3 = 'd0;$/;" r module:ad_axis_inf_rx +wlast_4 adi_library/common/ad_axis_inf_rx.v /^ reg wlast_4 = 'd0;$/;" r module:ad_axis_inf_rx +wlast_5 adi_library/common/ad_axis_inf_rx.v /^ reg wlast_5 = 'd0;$/;" r module:ad_axis_inf_rx +wlast_6 adi_library/common/ad_axis_inf_rx.v /^ reg wlast_6 = 'd0;$/;" r module:ad_axis_inf_rx +wlast_7 adi_library/common/ad_axis_inf_rx.v /^ reg wlast_7 = 'd0;$/;" r module:ad_axis_inf_rx +word_count adi_library/common/util_dec256sinc24b.v /^ reg [15:0] word_count = 16'h0;$/;" r module:util_dec256sinc24b +word_en adi_library/common/util_dec256sinc24b.v /^ reg word_en = 1'b0;$/;" r module:util_dec256sinc24b +word_length adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [7:0] word_length = DATA_WIDTH;$/;" r module:spi_engine_execution +wr_en hdl/freqestm.v /^ reg wr_en;$/;" r module:freqestm +wr_en_232 hdl/FrameMerge.v /^ reg wr_en_232;$/;" r module:FrameMerge +wr_en_data1 hdl/SC_FDE_TOP.v /^ wire wr_en_data1;$/;" n module:SC_FDE_TOP +wr_en_data1 hdl/data_ow.v /^ output reg wr_en_data1 = 1'd0,$/;" p module:data_ow +wr_en_data2 hdl/SC_FDE_TOP.v /^ wire wr_en_data2;$/;" n module:SC_FDE_TOP +wr_en_data2 hdl/data_ow.v /^ output reg wr_en_data2 = 1'd0,$/;" p module:data_ow +wr_en_pilot1 hdl/data_ow.v /^ reg wr_en_pilot1 = 1'd0;$/;" r module:data_ow +wr_en_pilot2 hdl/data_ow.v /^ reg wr_en_pilot2 = 1'd0;$/;" r module:data_ow +wready adi_library/axi_dmac/tb/axi_write_slave.v /^ output wready,$/;" p module:axi_write_slave +wready adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire wready;$/;" n module:dmac_dma_write_shutdown_tb +wready adi_library/axi_dmac/tb/dma_write_tb.v /^ wire wready;$/;" n module:dmac_dma_write_tb +write adi_library/util_axis_fifo/address_sync.v /^wire write = s_axis_ready & s_axis_valid;$/;" n module:fifo_address_sync +write_MMSE_wea hdl/Chn_Estimate.v /^ output reg write_MMSE_wea = 1'd0,$/;" p module:Chn_Estimate +write_MMSE_wea hdl/SC_FDE_TOP.v /^ wire write_MMSE_wea;$/;" n module:SC_FDE_TOP +write_reg adi_library/axi_dmac/tb/regmap_tb.v /^ task write_reg;$/;" t module:dmac_regmap_tb +write_reg_and_update adi_library/axi_dmac/tb/regmap_tb.v /^ task write_reg_and_update;$/;" t module:dmac_regmap_tb +writevalid hdl/IQmerge.v /^ reg [1:0] writevalid = 2'd0;$/;" r module:IQmerge +wstrb adi_library/axi_dmac/tb/axi_write_slave.v /^ input [DATA_WIDTH\/8-1:0] wstrb,$/;" p module:axi_write_slave +wstrb adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire [3:0] wstrb;$/;" n module:dmac_dma_write_shutdown_tb +wstrb adi_library/axi_dmac/tb/dma_write_tb.v /^ wire [WIDTH_DEST\/8-1:0] wstrb;$/;" n module:dmac_dma_write_tb +wvalid adi_library/axi_dmac/tb/axi_write_slave.v /^ input wvalid,$/;" p module:axi_write_slave +wvalid adi_library/axi_dmac/tb/dma_write_shutdown_tb.v /^ wire wvalid;$/;" n module:dmac_dma_write_shutdown_tb +wvalid adi_library/axi_dmac/tb/dma_write_tb.v /^ wire wvalid;$/;" n module:dmac_dma_write_tb +x adi_library/util_cic/cic_comb.v /^integer x;$/;" r module:cic_comb +x0 adi_library/common/ad_dds_sine_cordic.v /^ reg [CORDIC_DW-1:0] x0 = 'd0;$/;" r module:ad_dds_sine_cordic +x_length adi_library/axi_dmac/2d_transfer.v /^reg [DMA_LENGTH_WIDTH-1:0] x_length = 'h00;$/;" r module:dmac_2d_transfer +x_s adi_library/common/ad_dds_sine_cordic.v /^ wire [CORDIC_DW-1:0] x_s [0:CORDIC_DW-1];$/;" n module:ad_dds_sine_cordic +xfer_req adi_library/axi_dmac/data_mover.v /^ output xfer_req,$/;" p module:dmac_data_mover +xfer_req adi_library/axi_dmac/dest_axi_stream.v /^ output xfer_req,$/;" p module:dmac_dest_axi_stream +xfer_req adi_library/axi_dmac/dest_fifo_inf.v /^ output xfer_req,$/;" p module:dmac_dest_fifo_inf +xfer_req adi_library/axi_dmac/src_fifo_inf.v /^ output xfer_req,$/;" p module:dmac_src_fifo_inf +xpm_cdc_frame_sync_pulse_inst hdl/Receiver.v /^ ) xpm_cdc_frame_sync_pulse_inst ($/;" i module:Receiver typeref:module:xpm_cdc_pulse +xpm_cdc_single_inst hdl/enc_control.v /^ ) xpm_cdc_single_inst ($/;" i module:enc_control typeref:module:xpm_cdc_single +xpm_cdc_single_tx_test_flag_ps_inst hdl/system_top.v /^ ) xpm_cdc_single_tx_test_flag_ps_inst ($/;" i module:system_top typeref:module:xpm_cdc_single +xpm_cdc_startup_inst hdl/Receiver.v /^ ) xpm_cdc_startup_inst ($/;" i module:Receiver typeref:module:xpm_cdc_single +xpm_cdc_sync_rst_inst hdl/Receiver.v /^ ) xpm_cdc_sync_rst_inst ($/;" i module:Receiver typeref:module:xpm_cdc_sync_rst +xpm_cdc_sync_rst_phy_rst_inst hdl/system_top.v /^ ) xpm_cdc_sync_rst_phy_rst_inst ($/;" i module:system_top typeref:module:xpm_cdc_sync_rst +y0 adi_library/common/ad_dds_sine_cordic.v /^ reg [CORDIC_DW-1:0] y0 = 'd0;$/;" r module:ad_dds_sine_cordic +y_length adi_library/axi_dmac/2d_transfer.v /^reg [DMA_LENGTH_WIDTH-1:0] y_length = 'h00;$/;" r module:dmac_2d_transfer +y_s adi_library/common/ad_dds_sine_cordic.v /^ wire [CORDIC_DW-1:0] y_s [0:CORDIC_DW-1];$/;" n module:ad_dds_sine_cordic +z adi_library/util_pack/util_pack_common/pack_ctrl.v /^ localparam z = 2**MUX_ORDER;$/;" c module:pack_ctrl +z adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam z = 2**MUX_ORDER;$/;" c module:pack_interconnect +z0 adi_library/common/ad_dds_sine_cordic.v /^ reg [ PHASE_DW-1:0] z0 = 'd0;$/;" r module:ad_dds_sine_cordic +z_s adi_library/common/ad_dds_sine_cordic.v /^ wire [ PHASE_DW-1:0] z_s [0:CORDIC_DW-1];$/;" n module:ad_dds_sine_cordic diff --git a/hdl/RecvTop.v b/hdl/RecvTop.v index ac72c0b..8738364 100644 --- a/hdl/RecvTop.v +++ b/hdl/RecvTop.v @@ -258,11 +258,11 @@ module RecvTop ( .framesync_d0 (framesync), .vio_powertest_h (2'b00), .vio_powertest_l (2'b00), - .matchfilterout_i(FrameSync_douti), - .matchfilterout_q(FrameSync_doutq), + .matchfilterout_i(FrameSync_douti), // input, + .matchfilterout_q(FrameSync_doutq), // input - .DAGC_out_i(DAGC_out_i), - .DAGC_out_q(DAGC_out_q), + .DAGC_out_i(DAGC_out_i), // output + .DAGC_out_q(DAGC_out_q), // output .flag_agch (flag_agch), .flag_agcl (flag_agcl),