diff --git a/.gitignore b/.gitignore index 4772138..fe36af2 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,4 @@ adi_library c/** -ip \ No newline at end of file +ip +.tags \ No newline at end of file diff --git a/coe/DAGC_LUT.coe b/coe/DAGC_LUT.coe new file mode 100644 index 0000000..493fb80 --- /dev/null +++ b/coe/DAGC_LUT.coe @@ -0,0 +1,2029 @@ +memory_initialization_radix=10; +memory_initialization_vector= +15825, +14507, +13391, +12434, +11605, +10880, +10240, +9671, +9162, +8704, +8290, +7913, +7569, +7253, +6963, +6695, +6447, +6217, +6003, +5803, +5615, +5440, +5275, +5120, +4974, +4836, +4705, +4581, +4464, +4352, +4246, +4145, +4048, +3956, +3868, +3784, +3704, +3627, +3553, +3482, +3413, +3348, +3285, +3224, +3165, +3109, +3054, +3001, +2951, +2901, +2854, +2808, +2763, +2720, +2678, +2638, +2598, +2560, +2523, +2487, +2452, +2418, +2385, +2352, +2321, +2291, +2261, +2232, +2204, +2176, +2149, +2123, +2097, +2072, +2048, +2024, +2001, +1978, +1956, +1934, +1913, +1892, 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+2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, +2046, diff --git a/coe/fft_pilot_i.coe b/coe/fft_pilot_i.coe new file mode 100644 index 0000000..11a3229 --- /dev/null +++ b/coe/fft_pilot_i.coe @@ -0,0 +1,258 @@ +memory_initialization_radix=10; +memory_initialization_vector= +80, +96, +79, +88, +97, +95, +103, +113, +112, +101, +103, +80, +58, +34, +-1, +-45, +-80, +-104, +-112, +-94, +-58, +-17, +56, +97, +112, +90, +32, +-36, +-97, +-111, +-79, +-3, +80, +109, +79, +-7, +-97, +-103, +-32, +61, +112, +56, +-56, +-112, +-58, +59, +112, +45, +-80, +-101, +1, +109, +58, +-75, +-103, +22, +112, +21, +-103, +-52, +97, +72, +-79, +-78, +80, +78, +-79, +-72, +97, +52, +-103, +-21, +112, +-22, +-103, +75, +58, +-109, +1, +101, +-80, +-45, +112, +-59, +-58, +112, +-56, +-56, +112, +-61, +-32, +103, +-97, +7, +79, +-109, +80, +3, +-79, +111, +-97, +36, +32, +-90, +112, +-97, +56, +17, +-58, +94, +-112, +104, +-80, +45, +-1, +-34, +58, +-80, +103, +-101, +112, +-113, +103, +-95, +97, +-88, +79, +-96, +80, +-96, +79, +-88, +97, +-95, +103, +-113, +112, +-101, +103, +-80, +58, +-34, +-1, +45, +-80, +104, +-112, +94, +-58, +17, +56, +-97, +112, +-90, +32, +36, +-97, +111, +-79, +3, +80, +-109, +79, +7, +-97, +103, +-32, +-61, +112, +-56, +-56, +112, +-58, +-59, +112, +-45, +-80, +101, +1, +-109, +58, +75, +-103, +-22, +112, +-21, +-103, +52, +97, +-72, +-79, +78, +80, +-78, +-79, +72, +97, +-52, +-103, +21, +112, +22, +-103, +-75, +58, +109, +1, +-101, +-80, +45, +112, +59, +-58, +-112, +-56, +56, +112, +61, +-32, +-103, +-97, +-7, +79, +109, +80, +-3, +-79, +-111, +-97, +-36, +32, +90, +112, +97, +56, +-17, +-58, +-94, +-112, +-104, +-80, +-45, +-1, +34, +58, +80, +103, +101, +112, +113, +103, +95, +97, +88, +79, +96; diff --git a/coe/fft_pilot_q.coe b/coe/fft_pilot_q.coe new file mode 100644 index 0000000..7e6ea78 --- /dev/null +++ b/coe/fft_pilot_q.coe @@ -0,0 +1,258 @@ +memory_initialization_radix=10; +memory_initialization_vector= +80, +78, +79, +72, +58, +52, +32, +21, +0, +-22, +-56, +-75, +-97, +-109, +-112, +-101, +-80, +-45, +1, +59, +97, +112, +103, +56, +0, +-61, +-103, +-103, +-58, +7, +79, +109, +80, +3, +-79, +-111, +-58, +36, +103, +90, +0, +-97, +-103, +-17, +97, +94, +-1, +-104, +-80, +45, +112, +34, +-97, +-80, +56, +101, +0, +-113, +-32, +95, +58, +-88, +-79, +96, +80, +-96, +-79, +88, +58, +-95, +-32, +113, +0, +-101, +56, +80, +-97, +-34, +112, +-45, +-80, +104, +-1, +-94, +97, +17, +-103, +97, +0, +-90, +103, +-36, +-58, +111, +-79, +-3, +80, +-109, +79, +-7, +-58, +103, +-103, +61, +0, +-56, +103, +-112, +97, +-59, +1, +45, +-80, +101, +-112, +109, +-97, +75, +-56, +22, +0, +-21, +32, +-52, +58, +-72, +79, +-78, +80, +-78, +79, +-72, +58, +-52, +32, +-21, +0, +22, +-56, +75, +-97, +109, +-112, +101, +-80, +45, +1, +-59, +97, +-112, +103, +-56, +0, +61, +-103, +103, +-58, +-7, +79, +-109, +80, +-3, +-79, +111, +-58, +-36, +103, +-90, +0, +97, +-103, +17, +97, +-94, +-1, +104, +-80, +-45, +112, +-34, +-97, +80, +56, +-101, +0, +113, +-32, +-95, +58, +88, +-79, +-96, +80, +96, +-79, +-88, +58, +95, +-32, +-113, +0, +101, +56, +-80, +-97, +34, +112, +45, +-80, +-104, +-1, +94, +97, +-17, +-103, +-97, +0, +90, +103, +36, +-58, +-111, +-79, +3, +80, +109, +79, +7, +-58, +-103, +-103, +-61, +0, +56, +103, +112, +97, +59, +1, +-45, +-80, +-101, +-112, +-109, +-97, +-75, +-56, +-22, +0, +21, +32, +52, +58, +72, +79, +78; diff --git a/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v b/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v new file mode 100644 index 0000000..26bb2ec --- /dev/null +++ b/hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v @@ -0,0 +1,149 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/14 17:44:48 +// Design Name: +// Module Name: CCSDS_LDPC_DEC_K1024_R12_TOPP +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module CCSDS_LDPC_DEC_K1024_R12_TOPP + #( + parameter MAX_ITER_NUM = 6'd14, //最大迭代次数常量 + parameter WIDTH = 4'd8, //量化比特 + parameter OUT_ONLY_INFORMATION = 1'b0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字 + ) + ( + input clk, //工作时钟,100MHz + input Rst, //同步复位信号,高有效 + input FrameSync, //帧同步标志,高脉冲 + input Nd, //译码输入数据有效标志,高有效 + input [WIDTH-1:0] Din, //译码输入数据,软信息 + + + output LDPC_SyncOut, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点 + output Rdy, //译码输出信号有效标志,高有效 + output [0:0] LDPC_Dout, //译码输出信号,MSB输出 + + output [8:0] good_frames, //译码好帧计数 + output [8:0] bad_frames, //译码坏帧计数 + output [8:0] total_frames //译码总帧数计数 + ); + + wire FrameSync_A_TM; + wire Nd_A_TM; + wire [WIDTH-1:0] Din_A_TM; + + wire FrameSync_B_TM; + wire Nd_B_TM; + wire [WIDTH-1:0] Din_B_TM; + + wire LDPC_SyncOut_A; + wire Rdy_A; + wire [0:0] LDPC_Dout_A; + wire [8:0] good_frames_A; + wire [8:0] bad_frames_A; + wire [8:0] total_frames_A; + + wire LDPC_SyncOut_B; + wire Rdy_B; + wire [0:0] LDPC_Dout_B; + wire [8:0] good_frames_B; + wire [8:0] bad_frames_B; + wire [8:0] total_frames_B; + + + LDPC_TopManage_2 + #( + .WIDTH(WIDTH) + ) + TM ( + .clk(clk), + .Rst(Rst), + .FrameSync_TM(FrameSync), + .Nd_TM(Nd), + .Din_TM(Din), + .FrameSync_A_TM(FrameSync_A_TM), + .Nd_A_TM(Nd_A_TM), + .Din_A_TM(Din_A_TM), + .FrameSync_B_TM(FrameSync_B_TM), + .Nd_B_TM(Nd_B_TM), + .Din_B_TM(Din_B_TM), + .LDPC_SyncOut_A_TM(LDPC_SyncOut_A), + .Rdy_A_TM(Rdy_A), + .LDPC_Dout_A_TM(LDPC_Dout_A), + .good_frames_A_TM(good_frames_A), + .bad_frames_A_TM(bad_frames_A), + .total_frames_A_TM(total_frames_A), + .LDPC_SyncOut_B_TM(LDPC_SyncOut_B), + .Rdy_B_TM(Rdy_B), + .LDPC_Dout_B_TM(LDPC_Dout_B), + .good_frames_B_TM(good_frames_B), + .bad_frames_B_TM(bad_frames_B), + .total_frames_B_TM(total_frames_B), + .LDPC_SyncOut_TM(LDPC_SyncOut), + .Rdy_TM(Rdy), + .LDPC_Dout_TM(LDPC_Dout), + .good_frames_TM(good_frames), + .bad_frames_TM(bad_frames), + .total_frames_TM(total_frames) + ); + + CCSDS_LDPC_DEC_K1024_R12 + #( + .MAX_ITER_NUM(MAX_ITER_NUM), + .WIDTH(WIDTH), + .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION) + ) + inst_DEC_A ( + .clk(clk), + .Rst(Rst), + .FrameSync(FrameSync_A_TM), + .Nd(Nd_A_TM), + .Din(Din_A_TM), + .LDPC_SyncOut(LDPC_SyncOut_A), + .Rdy(Rdy_A), + .LDPC_Dout(LDPC_Dout_A), + .good_frames(good_frames_A), + .bad_frames(bad_frames_A), + .total_frames(total_frames_A) + ); + + CCSDS_LDPC_DEC_K1024_R12 + #( + .MAX_ITER_NUM(MAX_ITER_NUM), + .WIDTH(WIDTH), + .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION) + ) + inst_DEC_B ( + .clk(clk), + .Rst(Rst), + .FrameSync(FrameSync_B_TM), + .Nd(Nd_B_TM), + .Din(Din_B_TM), + .LDPC_SyncOut(LDPC_SyncOut_B), + .Rdy(Rdy_B), + .LDPC_Dout(LDPC_Dout_B), + .good_frames(good_frames_B), + .bad_frames(bad_frames_B), + .total_frames(total_frames_B) + ); + + + + +endmodule + diff --git a/hdl/FrameMerge.v b/hdl/FrameMerge.v new file mode 100644 index 0000000..180ccde --- /dev/null +++ b/hdl/FrameMerge.v @@ -0,0 +1,973 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/14 17:44:48 +// Design Name: +// Module Name: FrameMerge +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FrameMerge( + input clk, + input rst, + input rst2, + input sync, + input nd, + input din, + + input [6:0] vio_stopbit, + + input frameIDnd, + input clk2, + output reg framerdy = 1'b0, + // output reg flag_recvram = 1'b0, + // input [12:0] recv_addr1, + // input [12:0] recv_addr2, + // output [7:0] recv_data1, + // output [7:0] recv_data2, + input [13:0] recv_addr_new_0, + input [13:0] recv_addr_new_1, + input [13:0] recv_addr_new_2, + input [13:0] recv_addr_new_3, + output [7:0] recv_data_new_0, + output [7:0] recv_data_new_1, + output [7:0] recv_data_new_2, + output [7:0] recv_data_new_3, + output reg [16:0] RAMaddra_write_0 = 17'd0, + output reg [16:0] RAMaddra_write_1 = 17'd0, + output reg [16:0] RAMaddra_write_2 = 17'd0, + output reg [16:0] RAMaddra_write_3 = 17'd0, + output reg [16:0] RAMaddra_new_0 = 17'd0, + output reg [16:0] RAMaddra_new_1 = 17'd0, + output reg [16:0] RAMaddra_new_2 = 17'd0, + output reg [16:0] RAMaddra_new_3 = 17'd0, + output reg flag_notbyte = 1'd0, + output reg [1:0] state_ram = 2'd0, + + output reg flag_stop = 1'd0, //给shx，拉高一个clk表示当前时帧有效数据接收完毕 + output reg [16:0] addr_stop = 17'd0, //给shx，拉高一个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 + + //debug + output reg berstart_1d = 1'b0, + output reg bercompare = 1'b0, + output reg [16:0] bercount = 17'd0, + output reg [16:0] bercount_max = 17'd0, + output reg [16:0] ROMaddra_d2 = 17'd0, + output reg RAMdout_d1 = 1'd0, + + // output reg validnd_1_1d = 1'b0, + // output reg validnd_2_1d = 1'b0, + output reg validnd_new_new = 1'b0, + // output reg [63:0] stop_temp_1 = 64'd0, + // output reg [63:0] stop_temp_2 = 64'd0, + output reg [63:0] stop_temp_new = 64'd0, + + output flag_stop_0, //给shx，拉高1个clk表示当前时帧有效数据接收完毕 + output [16:0] addr_stop_0, + output reg [2:0] cnt_8 = 3'b0, + output reg state_8 = 1'd0, + + output rdy_scramble, + output dout_scramble, + + output reg [16:0] RAMaddra = 17'd0, //比较误码率 + output reg [16:0] ROMaddra = 17'd0, //比较误码率 + output reg [0:0] nd_ber = 1'd0, //比较误码率 + output reg [63:0] recvNetData, + output reg recvNetDataNd + // input [7:0] video_id01, + // input [7:0] video_id02, + // input [7:0] video_id03, + // input [7:0] MAC_idNum + ); + + reg frameIDnd_d1 = 1'd0; + reg frameIDnd_d2 = 1'd0; + always @(posedge clk)begin + frameIDnd_d1 <= frameIDnd; + frameIDnd_d2 <= frameIDnd_d1; + end + + // always @(posedge clk)begin + // if(frameIDnd && !frameIDnd_d1) flag_recvram <= ~flag_recvram; + // else flag_recvram <= flag_recvram; + // end + + //-------------------------------------------------------------------------------------------------------------// + + // reg validnd_1 = 1'b0; + // reg validnd_2 = 1'b0; + reg validnd_new = 1'b0; + reg [9:0] validlength = 10'd0; + reg [6:0] cnt_net; + reg [1:0] state_recv; + reg nd_recvnet_dout; + always @(posedge clk)begin + if(rst)begin + // validnd_1 <= 1'b0; + // validnd_2 <= 1'b0; + state_recv <= 2'd0; + validnd_new <= 1'b0; + validlength <= 10'd0; + cnt_net <= 6'd0; + nd_recvnet_dout <= 1'd0; + end + else begin + case(state_recv) + 2'd0:begin + if(!validnd_new)begin + if(sync)begin + validnd_new <= 1'b1; + nd_recvnet_dout <= 1'b1; + end + else begin + validnd_new <= 1'b0; + end + end + else begin + if(cnt_net == 6'd63) begin + validlength <= validlength + 10'd1; + if(validlength == 10'd1023)begin + validnd_new <= 1'b0; + state_recv <= 2'd1; + end else begin + validnd_new <= 1'b1; + state_recv <= state_recv; + end + nd_recvnet_dout <= 1'b0; + cnt_net <= 6'd63; + end + else begin + state_recv <= state_recv; + nd_recvnet_dout <= 1'b1; + cnt_net <= cnt_net +6'd1; + validlength <= validlength + 10'd1; + if(validlength == 10'd1023)begin + validnd_new <= 1'b0; + end else begin + validnd_new <= 1'b1; + end + end + + end + end + 2'd1:begin + if(!validnd_new)begin + if(sync)begin + validnd_new <= 1'b1; + end + else begin + validnd_new <= 1'b0; + end + state_recv <= state_recv; + end + else begin + state_recv <= state_recv; + nd_recvnet_dout <= 1'b0; + cnt_net <= 6'd0; + validlength <= validlength + 10'd1; + if(validlength == 10'd1023)begin + validnd_new <= 1'b0; + end else begin + validnd_new <= 1'b1; + end + end + end + default:begin + + if(!validnd_new)begin + if(sync)begin + + validnd_new <= 1'b1; + + nd_recvnet_dout <= 1'b1; + end + else begin + validnd_new <= 1'b0; + end + end + else begin + if(cnt_net == 6'd63) begin + validlength <= validlength + 10'd1; + if(validlength == 10'd1023)begin + validnd_new <= 1'b0; + state_recv <= 2'd1; + end else begin + validnd_new <= 1'b1; + state_recv <= state_recv; + end + nd_recvnet_dout <= 1'b0; + cnt_net <= 6'd63; + end + else begin + state_recv <= state_recv; + nd_recvnet_dout <= 1'b1; + cnt_net <= cnt_net +6'd1; + validlength <= validlength + 10'd1; + if(validlength == 10'd1023)begin + validnd_new <= 1'b0; + end else begin + validnd_new <= 1'b1; + end + end + + end + end + endcase + end + end + + // reg [15:0] RAMaddra_1 = 16'd0; + // reg [15:0] RAMaddra_2 = 16'd0; + // reg [16:0] RAMaddra_new = 17'd0; + // reg [15:0] RAMaddra = 16'd0; //比较误码率 + reg [0:0] dout_scramble_d1 = 1'd0; //比较误码率 + // reg [0:0] nd_ber = 1'd0; //比较误码率 + // reg validnd_1_1d = 1'b0; + // reg validnd_2_1d = 1'b0; + reg validnd_new_1d = 1'b0; + always @(posedge clk)begin + if(rst)begin + // RAMaddra_1 <= 16'd0; + // RAMaddra_2 <= 16'd0; + // RAMaddra_new <= RAMaddra_new; + RAMaddra <= 17'd0; //比较误码率 + ROMaddra <= 17'd0; //比较误码率 + dout_scramble_d1 <= 1'd0; //比较误码率 + nd_ber <= 1'd0; //比较误码率 + // validnd_1_1d <= 1'b0; + // validnd_2_1d <= 1'b0; + validnd_new_1d <= 1'b0; + end else begin + // validnd_1_1d <= validnd_1; + // if(validnd_1_1d) begin + // RAMaddra_1 <= RAMaddra_1 + 16'd1; + // end else begin + // RAMaddra_1 <= RAMaddra_1; + // end + + // validnd_2_1d <= validnd_2; + // if(validnd_2_1d) begin + // RAMaddra_2 <= RAMaddra_2 + 16'd1; + // end else begin + // RAMaddra_2 <= RAMaddra_2; + // end + + validnd_new_1d <= validnd_new; + // if(validnd_new_1d) begin + // RAMaddra_new <= RAMaddra_new + 16'd1; + // end else begin + // RAMaddra_new <= RAMaddra_new; + // end + + //比较误码率 + // if(validnd_1_1d||validnd_2_1d) begin + if(validnd_new_1d) begin + RAMaddra <= RAMaddra + 17'd1; + ROMaddra <= ROMaddra + 17'd1; + dout_scramble_d1 <= dout_scramble; + nd_ber <= 1'd1; + end + else begin + RAMaddra <= RAMaddra; + ROMaddra <= ROMaddra; + dout_scramble_d1 <= dout_scramble_d1; + nd_ber <= 1'd0; + end + //比较误码率 + end + end + + reg nd_recvnet_dout_d1; + reg nd_recvnet_dout_d2; + reg nd_recvnet_dout_d3; + reg nd_recvnet_dout_d4; + + reg wr_en_232; + reg rs232_send; + reg [4:0] cnt_422_wait; + wire validnd_new_delay; + reg validnd_new_delay_d1; + wire framedata; + reg framedata_d1; + reg [7:0] data_net_byte [87:0]; + reg [7:0] clk_net_byte; + reg [9:0] clk_net_bit; + //shiftram_scramble shiftram_scramble(.CLK(clk),.D({dout_scramble,validnd_new}),.Q({framedata,validnd_new_delay})); + reg [7:0] cnt_422_net; + always @(posedge clk)begin + if(rst2)begin + state_ram <= 2'd0; + RAMaddra_new_0 <= 17'd0; + RAMaddra_new_1 <= 17'd0; + RAMaddra_new_2 <= 17'd0; + RAMaddra_new_3 <= 17'd0; + flag_notbyte <= 1'd0; + nd_recvnet_dout_d1 <= 1'd0; + nd_recvnet_dout_d2 <= 1'd0; + nd_recvnet_dout_d3 <= 1'd0; + nd_recvnet_dout_d4 <= 1'd0; + recvNetDataNd <= 1'd0; + recvNetData <= 64'd0; + wr_en_232 <= 1'b0; + rs232_send <= 1'b0; + cnt_422_wait <= 5'd0; + cnt_422_net <= 8'd0; + clk_net_bit <= 10'd0; + clk_net_byte <= 8'd0; + validnd_new_delay_d1 <= 1'b0; + framedata_d1 <= 1'b0; + end + else begin + framedata_d1 <= framedata; + validnd_new_delay_d1 <= validnd_new_delay; + nd_recvnet_dout_d1 <= nd_recvnet_dout; + nd_recvnet_dout_d2 <= nd_recvnet_dout_d1; + nd_recvnet_dout_d3 <= nd_recvnet_dout_d2; + nd_recvnet_dout_d4 <= nd_recvnet_dout_d3; + if(!nd_recvnet_dout_d1 && nd_recvnet_dout_d2) begin//检测到网络层数据传输完毕拉高2个clk recvNetDataNd + recvNetDataNd <= 1'b1; + end + else begin + if(!nd_recvnet_dout_d3 && nd_recvnet_dout_d4) begin//延迟2个clk确保50MHz采到recvNetDataNd再拉低 + recvNetDataNd <= 1'b0; + end + else begin + recvNetDataNd <= recvNetDataNd; + end + end + case(state_ram) + //有了新的一帧，准备开始存储 + 2'd0:begin + if(frameIDnd_d2) begin + state_ram <= 2'd1; + RAMaddra_new_0<= RAMaddra_new_0; + RAMaddra_new_1<= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3; + end + else begin + state_ram <= state_ram; + RAMaddra_new_0<= RAMaddra_new_0; + RAMaddra_new_1<= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3; + end + validnd_new_new <= 1'd0; + flag_notbyte <= 1'd0; + end + 2'd1:begin + if(flag_stop_0) begin + if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_0 <= addr_stop_0 +17'd1; + end + else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_1 <= addr_stop_0 +17'd1; + end + else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_2 <= addr_stop_0 +17'd1; + end + else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_3 <= addr_stop_0 +17'd1; + end + else begin + RAMaddra_new_0 <= RAMaddra_new_0; + RAMaddra_new_1 <= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3; + end + validnd_new_new <= 1'd0; + state_ram <= 2'd2; + end + else begin + state_ram <= state_ram; + validnd_new_new <= validnd_new; + if(validnd_new_new) begin + if(nd_recvnet_dout_d1) begin + recvNetData[63:0] <= {dout_scramble,recvNetData[63:1]}; + end + else begin + if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_0 <= RAMaddra_new_0 + 17'd1; + RAMaddra_new_1 <= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3; + end + else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_0 <= RAMaddra_new_0; + RAMaddra_new_1 <= RAMaddra_new_1 + 17'd1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3; + end + else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_0 <= RAMaddra_new_0; + RAMaddra_new_1 <= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2 + 17'd1; + RAMaddra_new_3 <= RAMaddra_new_3; + end + else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_0 <= RAMaddra_new_0; + RAMaddra_new_1 <= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3 + 17'd1; + end + else begin + RAMaddra_new_0 <= RAMaddra_new_0; + RAMaddra_new_1 <= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3; + end + end + end + else begin + RAMaddra_new_0 <= RAMaddra_new_0; + RAMaddra_new_1 <= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3; + end + end + flag_notbyte <= 1'd0; + end + 2'd2:begin + // rs232_send <= 1'b0; + state_ram <= 2'd0; + if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin + case(RAMaddra_new_0[2:0]) + 3'b000:begin + flag_notbyte <= 1'd0; + RAMaddra_new_0 <= RAMaddra_new_0; + end + 3'b001:begin + flag_notbyte <= 1'd1; + RAMaddra_new_0 <= RAMaddra_new_0+17'd7; + end + 3'b010:begin + flag_notbyte <= 1'd1; + RAMaddra_new_0 <= RAMaddra_new_0+17'd6; + end + 3'b011:begin + flag_notbyte <= 1'd1; + RAMaddra_new_0 <= RAMaddra_new_0+17'd5; + end + 3'b100:begin + flag_notbyte <= 1'd1; + RAMaddra_new_0 <= RAMaddra_new_0+17'd4; + end + 3'b101:begin + flag_notbyte <= 1'd1; + RAMaddra_new_0 <= RAMaddra_new_0+17'd3; + end + 3'b110:begin + flag_notbyte <= 1'd1; + RAMaddra_new_0 <= RAMaddra_new_0+17'd2; + end + 3'b111:begin + flag_notbyte <= 1'd1; + RAMaddra_new_0 <= RAMaddra_new_0+17'd1; + end + endcase + end + else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin + case(RAMaddra_new_1[2:0]) + 3'b000:begin + flag_notbyte <= 1'd0; + RAMaddra_new_1 <= RAMaddra_new_1; + end + 3'b001:begin + flag_notbyte <= 1'd1; + RAMaddra_new_1 <= RAMaddra_new_1+17'd7; + end + 3'b010:begin + flag_notbyte <= 1'd1; + RAMaddra_new_1 <= RAMaddra_new_1+17'd6; + end + 3'b011:begin + flag_notbyte <= 1'd1; + RAMaddra_new_1 <= RAMaddra_new_1+17'd5; + end + 3'b100:begin + flag_notbyte <= 1'd1; + RAMaddra_new_1 <= RAMaddra_new_1+17'd4; + end + 3'b101:begin + flag_notbyte <= 1'd1; + RAMaddra_new_1 <= RAMaddra_new_1+17'd3; + end + 3'b110:begin + flag_notbyte <= 1'd1; + RAMaddra_new_1 <= RAMaddra_new_1+17'd2; + end + 3'b111:begin + flag_notbyte <= 1'd1; + RAMaddra_new_1 <= RAMaddra_new_1+17'd1; + end + endcase + end + else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin + case(RAMaddra_new_2[2:0]) + 3'b000:begin + flag_notbyte <= 1'd0; + RAMaddra_new_2 <= RAMaddra_new_2; + end + 3'b001:begin + flag_notbyte <= 1'd1; + RAMaddra_new_2 <= RAMaddra_new_2+17'd7; + end + 3'b010:begin + flag_notbyte <= 1'd1; + RAMaddra_new_2 <= RAMaddra_new_2+17'd6; + end + 3'b011:begin + flag_notbyte <= 1'd1; + RAMaddra_new_2 <= RAMaddra_new_2+17'd5; + end + 3'b100:begin + flag_notbyte <= 1'd1; + RAMaddra_new_2 <= RAMaddra_new_2+17'd4; + end + 3'b101:begin + flag_notbyte <= 1'd1; + RAMaddra_new_2 <= RAMaddra_new_2+17'd3; + end + 3'b110:begin + flag_notbyte <= 1'd1; + RAMaddra_new_2 <= RAMaddra_new_2+17'd2; + end + 3'b111:begin + flag_notbyte <= 1'd1; + RAMaddra_new_2 <= RAMaddra_new_2+17'd1; + end + endcase + end + else if(recvNetData[63:56] == 8'hff&& recvNetData[23:0]==24'h7E5A33) begin + case(RAMaddra_new_3[2:0]) + 3'b000:begin + flag_notbyte <= 1'd0; + RAMaddra_new_3 <= RAMaddra_new_3; + end + 3'b001:begin + flag_notbyte <= 1'd1; + RAMaddra_new_3 <= RAMaddra_new_3+17'd7; + end + 3'b010:begin + flag_notbyte <= 1'd1; + RAMaddra_new_3 <= RAMaddra_new_3+17'd6; + end + 3'b011:begin + flag_notbyte <= 1'd1; + RAMaddra_new_3 <= RAMaddra_new_3+17'd5; + end + 3'b100:begin + flag_notbyte <= 1'd1; + RAMaddra_new_3 <= RAMaddra_new_3+17'd4; + end + 3'b101:begin + flag_notbyte <= 1'd1; + RAMaddra_new_3 <= RAMaddra_new_3+17'd3; + end + 3'b110:begin + flag_notbyte <= 1'd1; + RAMaddra_new_3 <= RAMaddra_new_3+17'd2; + end + 3'b111:begin + flag_notbyte <= 1'd1; + RAMaddra_new_3 <= RAMaddra_new_3+17'd1; + end + endcase + end + else begin + flag_notbyte <= 1'b0; + RAMaddra_new_0 <= RAMaddra_new_0; + RAMaddra_new_1 <= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3; + end + + end + default:begin + if(frameIDnd_d2) begin + state_ram <= 2'd1; + RAMaddra_new_0 <= RAMaddra_new_0; + RAMaddra_new_1 <= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3; + end + else begin + state_ram <= state_ram; + RAMaddra_new_0 <= RAMaddra_new_0; + RAMaddra_new_1 <= RAMaddra_new_1; + RAMaddra_new_2 <= RAMaddra_new_2; + RAMaddra_new_3 <= RAMaddra_new_3; + end + validnd_new_new <= 1'd0; + flag_notbyte <= 1'd0; + end + endcase + end + end + + + reg [8:0] bagcnt = 9'd0; + always @(posedge clk)begin + if(rst)begin + bagcnt <= 9'd0; + end else begin + if(sync)begin + bagcnt <= bagcnt + 9'd1; + end else begin + bagcnt <= bagcnt; + end + end + end + + wire scramblestart; + assign scramblestart = (bagcnt == 9'd0)? sync : 1'b0; + + // wire rdy_scramble; + // wire dout_scramble; + Scramble Scramble ( + .clk(clk), + .rst(rst2 || framerdy), + .start(scramblestart), + // .nd(validnd_1||validnd_2), + .nd(validnd_new), + .din(din), + .rdy(rdy_scramble), + .dout(dout_scramble) + ); + + + + //------------------------------------------比较误码率---------------------------// + reg [16:0] RAMaddrb = 17'd0; + wire RAMdout; + RAM_merge RAM_merge_0 ( + .clka(clk), // input clka + // .wea(validnd_1_1d||validnd_2_1d), // input [0 : 0] wea + .wea(validnd_new_1d), // input [0 : 0] wea + .addra(RAMaddra), // input [16 : 0] addra + .dina(dout_scramble), // input [0 : 0] dina + .clkb(clk), // input clkb + .addrb(RAMaddrb), // input [16 : 0] addrb + .doutb(RAMdout) // output [0 : 0] doutb + ); + + // reg [15:0] ROMaddra = 16'd0; + wire ROMdout; + ROM_ber ROM_ber ( + .clka(clk), // input clka + .addra(ROMaddra), // input [16 : 0] addra + .douta(ROMdout) // output [0 : 0] douta + ); + + reg berstart = 1'b0; + always @(posedge clk)begin + if(rst2)begin + RAMaddrb <= 17'd0; + berstart <= 1'b0; + end else begin + if(!berstart)begin + RAMaddrb <= 17'd0; + if(bagcnt == 9'd105 && validlength == 10'd1023)begin + berstart <= 1'b1; + end else begin + berstart <= 1'b0; + end + end else begin + if(RAMaddrb == 17'd107519)begin + berstart <= 1'b0; + RAMaddrb <= 17'd0; + end else begin + berstart <= 1'b1; + RAMaddrb <= RAMaddrb + 17'd1; + end + end + end + end + + + + + reg [16:0] ROMaddra_d1 = 17'd0; + always @(posedge clk)begin + berstart_1d <= berstart; + if(rst)begin + bercompare <= 1'b0; + bercount <= 17'd0; + ROMaddra_d1 <= 17'd0; + ROMaddra_d2 <= 17'd0; + RAMdout_d1 <= 1'd0; + bercount_max <= bercount; + end else begin + if(nd_ber) begin + bercompare <= dout_scramble_d1^ROMdout; + bercount <= bercount + bercompare; + + ROMaddra_d1 <= ROMaddra; + ROMaddra_d2 <= ROMaddra_d1; + RAMdout_d1 <= dout_scramble_d1; + bercount_max <= bercount_max; + end + else begin + bercompare <= 1'd0; + bercount <= bercount; + + ROMaddra_d1 <= ROMaddra_d1; + ROMaddra_d2 <= ROMaddra_d2; + RAMdout_d1 <= RAMdout_d1; + bercount_max <= bercount_max; + end + end + end + //------------------------------------------比较误码率---------------------------// + + + + // RAM_recv RAM_recv_1 ( + // .clka(clk), // input clka + // .wea(validnd_1_1d), // input [0 : 0] wea + // .addra(RAMaddra_1), // input [15 : 0] addra + // .dina(dout_scramble), // input [0 : 0] dina + // .clkb(clk2), // input clkb + // .addrb(recv_addr1), // input [12 : 0] addrb + // .doutb(recv_data1) // output [7 : 0] doutb + // ); + + // RAM_recv RAM_recv_2 ( + // .clka(clk), // input clka + // .wea(validnd_2_1d), // input [0 : 0] wea + // .addra(RAMaddra_2), // input [15 : 0] addra + // .dina(dout_scramble), // input [0 : 0] dina + // .clkb(clk2), // input clkb + // .addrb(recv_addr2), // input [12 : 0] addrb + // .doutb(recv_data2) // output [7 : 0] doutb + // ); + + RAM_recvnew RAM_recvnew_0 ( + .clka(clk), // input clka + .wea(validnd_new_new), // input [0 : 0] wea + .addra(RAMaddra_new_0), // input [16 : 0] addra + .dina(dout_scramble), // input [0 : 0] dina + .clkb(clk2), // input clkb + .addrb(recv_addr_new_0), // input [13 : 0] addrb + .doutb(recv_data_new_0) // output [7 : 0] doutb + ); + + RAM_recvnew RAM_recvnew_1 ( + .clka(clk), // input clka + .wea(validnd_new_new), // input [0 : 0] wea + .addra(RAMaddra_new_1), // input [16 : 0] addra + .dina(dout_scramble), // input [0 : 0] dina + .clkb(clk2), // input clkb + .addrb(recv_addr_new_1), // input [13 : 0] addrb + .doutb(recv_data_new_1) // output [7 : 0] doutb + ); + RAM_recvnew RAM_recvnew_2 ( + .clka(clk), // input clka + .wea(validnd_new_new), // input [0 : 0] wea + .addra(RAMaddra_new_2), // input [16 : 0] addra + .dina(dout_scramble), // input [0 : 0] dina + .clkb(clk2), // input clkb + .addrb(recv_addr_new_2), // input [13 : 0] addrb + .doutb(recv_data_new_2) // output [7 : 0] doutb + ); + /*RAM_recvnew RAM_recvnew_3 ( + .clka(clk), // input clka + .wea(validnd_new_new), // input [0 : 0] wea + .addra(RAMaddra_new_3), // input [16 : 0] addra + .dina(dout_scramble), // input [0 : 0] dina + .clkb(clk2), // input clkb + .addrb(recv_addr_new_3), // input [13 : 0] addrb + .doutb(recv_data_new_3) // output [7 : 0] doutb + );*/ + + //-------------------------------------------------------------------------------------------------------------// + + //-------------------------------------找停止位---------------------------// + + + // reg nd_stop_1 = 1'd0; + // reg nd_stop_2 = 1'd0; + reg nd_stop_new = 1'd0; + + // reg [15:0] RAMaddra_1_temp = 16'd0; + // reg [15:0] RAMaddra_2_temp = 16'd0; + reg [16:0] RAMaddra_new_temp = 17'd0; + find_stop find_stop ( + .clk(clk), + // .nd_stop_1(nd_stop_1), + // .nd_stop_2(nd_stop_2), + .nd_stop_new(nd_stop_new), + // .RAMaddra_1_temp(RAMaddra_1_temp), + // .RAMaddra_2_temp(RAMaddra_2_temp), + .RAMaddra_new_temp(RAMaddra_new_temp), + // .stop_temp_1(stop_temp_1), + // .stop_temp_2(stop_temp_2), + .stop_temp_new(stop_temp_new), + + .vio_stopbit(vio_stopbit), + + .flag_stop_0(flag_stop_0), + .addr_stop_0(addr_stop_0) + ); + + // reg [63:0] stop_temp_1 = 64'd0; + // reg [63:0] stop_temp_2 = 64'd0; + // reg flag_stop_0 = 1'd0; //给shx，拉高1个clk表示当前时帧有效数据接收完毕 + // reg [15:0] addr_stop_0 = 16'd0; //给shx，拉高1个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 + always @(posedge clk)begin + // nd_stop_1 <= validnd_1_1d; + // nd_stop_2 <= validnd_2_1d; + nd_stop_new <= validnd_new_1d; + // if(validnd_1_1d) begin + // stop_temp_1[0] <= dout_scramble; + // stop_temp_1[63:1] <= stop_temp_1[62:0]; + // RAMaddra_1_temp <= RAMaddra_1; + // RAMaddra_2_temp <= 16'd0; + // end + // else begin + // if(validnd_2_1d) begin + // stop_temp_2[0] <= dout_scramble; + // stop_temp_2[63:1] <= stop_temp_2[62:0]; + // RAMaddra_1_temp <= 16'd0; + // RAMaddra_2_temp <= RAMaddra_2; + // end + // else begin + // stop_temp_1 <= stop_temp_1; + // stop_temp_2 <= stop_temp_2; + + // RAMaddra_1_temp <= RAMaddra_1_temp; + // RAMaddra_2_temp <= RAMaddra_2_temp; + // end + // end + if(validnd_new_1d) begin + stop_temp_new[0] <= dout_scramble; + stop_temp_new[63:1] <= stop_temp_new[62:0]; + if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_temp <= RAMaddra_new_0; + end + else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_temp <= RAMaddra_new_1; + end + else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_temp <= RAMaddra_new_2; + end + else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin + RAMaddra_new_temp <= RAMaddra_new_3; + end + else begin + RAMaddra_new_temp <= RAMaddra_new_temp; + end + end + else begin + stop_temp_new <= stop_temp_new; + + RAMaddra_new_temp <= RAMaddra_new_temp; + end + end + + + // reg [2:0] cnt_8 = 3'b0; + // reg state_8 = 1'd0; + always @(posedge clk)begin + case(state_8) + 1'd0:begin + if(flag_stop_0)begin + cnt_8 <= 3'b0; + flag_stop <= 1'b1; + addr_stop <= addr_stop_0; + state_8 <= 1'd1; + end + else begin + cnt_8 <= 3'b0; + flag_stop <= 1'b0; + addr_stop <= addr_stop; + state_8 <= state_8; + end + end + 1'd1:begin + if(cnt_8==3'd7) begin + cnt_8 <= 3'b0; + flag_stop <= 1'b0; + addr_stop <= addr_stop; + state_8 <= 1'd0; + end + else begin + cnt_8 <= 3'b1+cnt_8; + flag_stop <= 1'b1; + addr_stop <= addr_stop; + state_8 <= state_8; + end + end + endcase + end + + + reg [16:0] RAMaddra_new_0_d1 = 17'd0; + reg [16:0] RAMaddra_new_1_d1 = 17'd0; + reg [16:0] RAMaddra_new_2_d1 = 17'd0; + reg [16:0] RAMaddra_new_3_d1 = 17'd0; + always@(posedge clk2)begin + RAMaddra_new_0_d1 <= RAMaddra_new_0; + RAMaddra_new_1_d1 <= RAMaddra_new_1; + RAMaddra_new_2_d1 <= RAMaddra_new_2; + RAMaddra_new_3_d1 <= RAMaddra_new_3; + RAMaddra_write_0 <= RAMaddra_new_0_d1; + RAMaddra_write_1 <= RAMaddra_new_1_d1; + RAMaddra_write_2 <= RAMaddra_new_2_d1; + RAMaddra_write_3 <= RAMaddra_new_3_d1; + end + + //-------------------------------------找停止位---------------------------// + + + + always @(posedge clk)begin + if(rst2)begin + framerdy <= 1'b0; + end else begin + if(bagcnt == 9'd105 && validlength == 10'd1023)begin + framerdy <= 1'b1; + end else begin + framerdy <= 1'b0; + end + end + end + + ila_ber ila_ber( + .clk(clk), + .probe0(rst), + .probe1(ROMdout), + .probe2(validnd_new_delay), + .probe3(bercount), + .probe4(flag_stop_0), + .probe5(framedata_d1), + .probe6(recvNetDataNd), + .probe7(addr_stop_0), + .probe8(nd_recvnet_dout_d1), + .probe9(recvNetData), + .probe10(dout_scramble), + .probe11(wr_en_232), + .probe12(framedata), + .probe13(data_net_byte[87]), + .probe14(RAMaddra_new_0), + .probe15(RAMaddra_new_1) + + ); + + +endmodule + diff --git a/hdl/MF_Top.v b/hdl/MF_Top.v new file mode 100644 index 0000000..6686c24 --- /dev/null +++ b/hdl/MF_Top.v @@ -0,0 +1,121 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:44 11/14/2019 +// Design Name: +// Module Name: MF_Top +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module MF_Top ( + input clk, + input rst, + + input [11:0] dini, + input [11:0] dinq, + input start, + + output reg [9:0] matchfilterout_i = 10'd0, + output reg [9:0] matchfilterout_q = 10'd0, + output reg MF_rdy, + output reg MF_rst +); + + wire s_axis_data_tvalid_i; + wire s_axis_data_tready_i; + wire m_axis_data_tvalid_i; + wire [31:0] MF_m_axis_data_tdata_i; + + assign s_axis_data_tvalid_i = start; + MF12p5_12bit MF12p5_12bit_i ( + .aclk (clk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid_i), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready_i), // output wire s_axis_data_tready + .s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid_i), // output wire m_axis_data_tvalid + .m_axis_data_tdata (MF_m_axis_data_tdata_i) // output wire [31 : 0] m_axis_data_tdata + ); + + wire s_axis_data_tvalid_q; + wire s_axis_data_tready_q; + wire m_axis_data_tvalid_q; + wire [31:0] MF_m_axis_data_tdata_q; + + assign s_axis_data_tvalid_q = start; + MF12p5_12bit MF12p5_12bit_q ( + .aclk (clk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid_q), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready_q), // output wire s_axis_data_tready + .s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid_q), // output wire m_axis_data_tvalid + .m_axis_data_tdata (MF_m_axis_data_tdata_q) // output wire [31 : 0] m_axis_data_tdata + ); + + //截位：结果为MF_m_axis_data_tdata_i/q[25:0] + //低位截位15bit，高位截位1bit，得10bit宽结果 + always @(posedge clk) begin + if (MF_m_axis_data_tdata_i[25:24] == 2'b00 || MF_m_axis_data_tdata_i[25:24] == 2'b11) begin + matchfilterout_i <= MF_m_axis_data_tdata_i[24:15]; + end + else begin + matchfilterout_i <= (MF_m_axis_data_tdata_i[25] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111; + end + + if (MF_m_axis_data_tdata_q[25:24] == 2'b00 || MF_m_axis_data_tdata_q[25:24] == 2'b11) begin + matchfilterout_q <= MF_m_axis_data_tdata_q[24:15]; + end + else begin + matchfilterout_q <= (MF_m_axis_data_tdata_q[25] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111; + end + end + + reg MF_rdy_d1; + always @(posedge clk) begin + MF_rdy_d1 <= MF_rdy; + if (rst) begin + MF_rdy <= 1'b0; + MF_rst <= 1'b0; + end + else begin + MF_rdy <= start; + if ((MF_rdy == 1'b1) && (MF_rdy_d1 == 1'b0)) begin + MF_rst <= 1'b1; + end + else begin + MF_rst <= 1'b0; + end + end + end + + //------DEBUG模块------// +`ifdef MF_debug + + //ILA + /*ila_16x8 ila_MF_inst( + .clk(clk), + .probe0(dini), + .probe1(dinq), + .probe2(start), + .probe3(matchfilterout_i), + .probe4(matchfilterout_q), + .probe5(MF_rdy), + .probe6(8'b0), + .probe7(8'b0) + );*/ + + + +`endif + +endmodule diff --git a/hdl/Receiver.v b/hdl/Receiver.v index a320485..b92a99c 100644 --- a/hdl/Receiver.v +++ b/hdl/Receiver.v @@ -74,6 +74,7 @@ module Receiver ( dmf_s_valid <= 1'd0; end else if (startup_4x && fifo_out_valid && cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin + // fifo_out_valid may be not trustable at the rst state dmf_s_valid <= 1'd1; end else begin diff --git a/hdl/RecvTop.v b/hdl/RecvTop.v index 8738364..3bc78da 100644 --- a/hdl/RecvTop.v +++ b/hdl/RecvTop.v @@ -28,44 +28,12 @@ module RecvTop ( input [11:0] dini, input [11:0] dinq, - //视频数据存储，shx - input [13:0] recv_addr_new_0, - input [13:0] recv_addr_new_1, - input [13:0] recv_addr_new_2, - input [13:0] recv_addr_new_3, - output [ 7:0] recv_data_new_0, - output [ 7:0] recv_data_new_1, - output [ 7:0] recv_data_new_2, - output [ 7:0] recv_data_new_3, - output [16:0] RAMaddra_write_0, - output [16:0] RAMaddra_write_1, - output [16:0] RAMaddra_write_2, - output [16:0] RAMaddra_write_3, - output [16:0] RAMaddra_new_0, - output [16:0] RAMaddra_new_1, - output [16:0] RAMaddra_new_2, - output [16:0] RAMaddra_new_3, - output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 - output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 + output [3:0] ad9361_ctrl_in, - //vio - // input DC_move_able, //为1的时候启用去直流，为0的时候不启用 - // input [1:0] vio_powertest_h, //DAGC - // input [1:0] vio_powertest_l, //DAGC - // input DAGC_enab, //为1的时候启用DAGC，为0的时候不启用DAGC - // input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路 - // input EQUenable_vio, //为1时启用均衡 - // input [7:0] Zerozone_vio, //零域估计，默认值为8'd29 - input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60 + output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 + output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 - //9361、射频增益控制 - output [7:0] data_9361, - output [9:0] addr_9361, - output enab_9361, - output D1_12dB, - output D2_6dB, - output D3_18dB, - output D4_12dB, + input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60 //debug //trigger @@ -139,74 +107,212 @@ module RecvTop ( output reg flagoverflow = 1'd0, //总溢出标志 output Pilot_rdy_hide1_d1, - - - - output [63:0] recvNetData, output recvNetDataNd, input debug_loss - // input [ 7:0] MAC_idNum - // input [ 7:0] video_id01, - // input [ 7:0] video_id02, - // input [ 7:0] video_id03 - ); + reg [7:0] cnt_mgc_delay; + wire mgc_start; + wire flag_mgc_done; // level flag + wire flag_mgc_done_4x; // level flag + always @(posedge clk) begin + if (rst) begin + cnt_mgc_delay <= 0; + end + else if (cnt_mgc_delay < 8'hff) begin + cnt_mgc_delay <= cnt_mgc_delay + 1; + end + else begin + cnt_mgc_delay <= cnt_mgc_delay; + end + end + assign mgc_start = (nt_mgc_delay == 8'hff); - MGC_adaptation MGC_adaptation ( - .clk (clk), - .rst (rst), - .dini(dini), - .dinq(dinq), - - .data_9361(data_9361), - .addr_9361(addr_9361), - .enab_9361(enab_9361), - .D1_12dB (D1_12dB), - .D2_6dB (D2_6dB), - .D3_18dB (D3_18dB), - .D4_12dB (D4_12dB), - - .mgc1_rdy(mgc1_rdy) + ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ( + .clk (clk), + .rst (rst), + .start (mgc_start), + .rx_data_i (dini), + .rx_data_q (dinq), + .ad9361_ctrl_in(ad9361_ctrl_in), + .flag_mgc_done (flag_mgc_done) ); + wire MF_rdy; // flag_mgc_done_d1 + wire MF_rst; // flag_mgc_done_pulse_d2 - wire MF_rdy; - wire MF_rst; + wire fifo_out_valid; + reg [ 2:0] cnt_fifo_out_valid; + reg [ 2:0] cnt_fifo_out_valid_sel = 1; // 根据speed mode对应的计数器边界值 + + wire [31:0] fifo_out; + reg dmf_s_valid; + wire dmf_tvalid_interp4_i; + wire dmf_tvalid_interp4_q; + wire [31:0] mf_data_interp4_i; + wire [31:0] mf_data_interp4_q; + wire [23:0] dmf_tdata_interp4_i; + wire [23:0] dmf_tdata_interp4_q; + + // valid signal for dmf + always @(posedge clk_4x) begin + if (rst) begin + dmf_s_valid <= 1'd0; + end + else if (flag_mgc_done_4x && fifo_out_valid && cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin + // fifo_out_valid may be not trustable at the rst state + dmf_s_valid <= 1'd1; + end + else begin + dmf_s_valid <= 1'd0; + end + end + + always @(posedge clk_4x) begin + if (rst) begin + cnt_fifo_out_valid <= 3'd0; + end + else if (fifo_out_valid) begin + if (cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin // refer to Receiver.v + cnt_fifo_out_valid <= 3'd0; + end + else begin + cnt_fifo_out_valid <= cnt_fifo_out_valid + 3'd1; + end + end + else begin + cnt_fifo_out_valid <= cnt_fifo_out_valid; + end + end - MF_Top MF_Top ( - .clk(clk), - .rst(rst), - // .rst (rst), - .dini (dini), - .dinq (dinq), - .start(mgc1_rdy), - - .matchfilterout_i(matchfilterout_i), - .matchfilterout_q(matchfilterout_q), - .MF_rdy (MF_rdy), - .MF_rst (MF_rst) + // Match filter + fir_match_interp4 u_fir_match_filter_interp4_i ( + .aclk (clk), // input wire aclk + .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid + .s_axis_data_tready(), // output wire s_axis_data_tready + .s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid(), // output wire m_axis_data_tvalid + .m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata + ); + fir_match_interp4 u_fir_match_filter_interp4_q ( + .aclk (clk), // input wire aclk + .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid + .s_axis_data_tready(), // output wire s_axis_data_tready + .s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid(), // output wire m_axis_data_tvalid + .m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata ); + // CDC into clk_4x + fifo_shift u_fifo_shift ( + // input + .s_aclk (clk), // input wire s_aclk + .s_aresetn (flag_mgc_done), // input wire s_aresetn + .s_axis_tvalid(flag_mgc_done), // input wire s_axis_tvalid + .s_axis_tready(), // output wire s_axis_tready + .s_axis_tdata ({8'd0, mf_data_interp4_q[29-:12], mf_data_interp4_i[29-:12]}), // input wire [31 : 0] s_axis_tdata + // output + .m_aclk (clk_4x), // input wire m_aclk + .m_axis_tvalid(fifo_out_valid), // output wire m_axis_tvalid + .m_axis_tready(1'b1), // input wire m_axis_tready + .m_axis_tdata (fifo_out), // output wire [31 : 0] m_axis_tdata + .wr_rst_busy (), + .rd_rst_busy () + ); + fir_dmf_interp4 u_fir_dmf_interp4_i ( + .aclk (clk_4x), + .s_axis_data_tvalid(dmf_s_valid), + .s_axis_data_tready(), + .s_axis_data_tdata ({4'd0, fifo_out[11:0]}), + .m_axis_data_tvalid(dmf_tvalid_interp4_i), + .m_axis_data_tdata (dmf_tdata_interp4_i) + ); + + fir_dmf_interp4 u_fir_dmf_interp4_q ( + .aclk (clk_4x), + .s_axis_data_tvalid(dmf_s_valid), + .s_axis_data_tready(), + .s_axis_data_tdata ({4'd0, fifo_out[23:12]}), + .m_axis_data_tvalid(dmf_tvalid_interp4_q), + .m_axis_data_tdata (dmf_tdata_interp4_q) + ); + + wire [21:0] mag; + wire mag_valid; + wire frame_sync_4x; + wire frame_sync_pulse; // in domain clk + MagnitudeEstimator #( + .VEC_WIDTH(21) + ) u_MagnitudeEstimator ( + .clk (clk_4x), + .rst (rst), + .vec_valid(dmf_tvalid_interp4_i), + .I (dmf_tdata_interp4_i), + .Q (dmf_tdata_interp4_q), + .mag (mag), + .mag_valid(mag_valid) + ); + + PAPR #( + .MAG_WIDTH (22), + .WINDOW_DEPTH(1023) + ) u_PAPR ( + .clk (clk_4x), + .rst (rst), + .vec_mag (mag), + .mag_valid (mag_valid), + .frame_sync (frame_sync_4x), + .frame_sync_pulse() + ); + + // wire [9:0] DAGC_out_i; + // wire [9:0] DAGC_out_q; + + wire [9:0] FrameSync_douti; + wire [9:0] FrameSync_doutq; + wire dagc_rdy; + wire mgc_rdy; + wire rst_dagc; + + DAGC_v2 DAGC_v2 ( + .clk (clk), + .rst (~mgc1_rdy), + .mgc1_rdy (MF_rdy), + .framesync_d0 (framesync), + .vio_powertest_h (2'b00), + .vio_powertest_l (2'b00), + .matchfilterout_i(FrameSync_douti), + .matchfilterout_q(FrameSync_doutq), + // output + .DAGC_out_i (DAGC_out_i), + .DAGC_out_q (DAGC_out_q), + //flag + .flag_agch (flag_agch), + .flag_agcl (flag_agcl), + .flag_agc_power (flag_agc_power), + .agc_ref (agc_ref), + .agc_check (agc_check), + .dagc_rdy (dagc_rdy), + .mgc_rdy (mgc_rdy), + .rst_dagc (rst_dagc) + ); //帧同步模块 - assign FrameSync_dini = (DAGC_enab) ? DAGC_out_i : matchfilterout_i; - assign FrameSync_dinq = (DAGC_enab) ? DAGC_out_q : matchfilterout_q; + assign FrameSync_dini = DAGC_out_i; + assign FrameSync_dinq = DAGC_out_q; // wire framesync; - wire Sync_rdy; - wire Pilot_rdy; + wire Sync_rdy; + wire Pilot_rdy; - wire [9:0] FrameSync_douti; - wire [9:0] FrameSync_doutq; SCFDE_recv_FrameSync SCFDE_recv_FrameSync_inst ( @@ -217,10 +323,10 @@ module RecvTop ( .datain_q (matchfilterout_q), .Sync_i (FrameSync_douti), .Sync_q (FrameSync_doutq), - .Sync_rdy (Sync_rdy), // 帧同步找到了过门限峰值 - .Pilot_rdy (Pilot_rdy),// 开始取导频的标志位 not used - .flag_sync (framesync), // high level flag - .Pilot_rdy_hide1_d1(Pilot_rdy_hide1_d1) // not used + .Sync_rdy (Sync_rdy), // 帧同步找到了过门限峰值 + .Pilot_rdy (Pilot_rdy), // 开始取导频的标志位 not used + .flag_sync (framesync), // high level flag not used + .Pilot_rdy_hide1_d1(Pilot_rdy_hide1_d1) // not used ); // @@ -230,12 +336,13 @@ module RecvTop ( if (Pilot_rdy_hide1_d1) begin cnt_lost <= 21'd0; framelost <= 1'b0; - end else begin + end + else begin if (cnt_lost >= 21'd750000) begin - ; cnt_lost <= 21'd0; framelost <= 1'b1; - end else begin + end + else begin cnt_lost <= 21'd1 + cnt_lost; framelost <= 1'b0; end @@ -490,61 +597,47 @@ module RecvTop ( .nd_ber (nd_ber), .recvNetData (recvNetData), .recvNetDataNd(recvNetDataNd) - // .MAC_idNum (MAC_idNum) - // .video_id01 (8'd0), - // .video_id02 (8'd0), - // .video_id03 (8'd0) ); - - - /*ila_recvtop ila_recvtop( - .clk(clk), - .probe0(framesync), - .probe1(framesync_delay), - .probe2(phase_adjust_rdy), - .probe3(nd_SC_FDE_dout), - .probe4(IQmergerdy), - .probe5(IQmergedout), - .probe6(LDPC_Rdy), - .probe7(LDPC_Dout), - .probe8(SC_FDE_douti), - .probe9(SC_FDE_doutq), - .probe10(total_frames), - .probe11(good_frames), - .probe12(dini), - .probe13(dinq), - .probe14(phase_adjust_douti), - .probe15(phase_adjust_doutq), - .probe16(D1_12dB), - .probe17(D2_6dB), - .probe18(D3_18dB), - .probe19(D4_12dB) - -);*/ - ila_recvtest ila_recvtest ( - .clk (clk), - .probe0(framesync), - .probe1(framesync_delay), - .probe2(D1_12dB), - .probe3(D2_6dB), - .probe4(D3_18dB), - .probe5(D4_12dB), - .probe6(mgc1_rdy), - .probe7(rst), - .probe8(dini), - .probe9(dinq) + // **** cdc **** + xpm_cdc_single #( + .DEST_SYNC_FF (2), // DECIMAL; range: 2-10 + .INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .SIM_ASSERT_CHK(1), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + .SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input + ) xpm_cdc_startup_inst ( + .dest_out(flag_mgc_done_4x), // 1-bit output: src_in synchronized to the destination clock domain. This output is + // registered. + .dest_clk(clk_4x), // 1-bit input: Clock signal for the destination clock domain. + .src_clk (clk), // 1-bit input: optional; required when SRC_INPUT_REG = 1 + .src_in (flag_mgc_done) // 1-bit input: Input signal to be synchronized to dest_clk domain. ); - /*ila_decode ila_decode( - .clk(clk2), - .probe0(IQmergerdy), - .probe1(IQmergedout), - .probe2(LDPC_Dout), - .probe3(LDPC_Rdy), - .probe4(framerdy), - .probe5(total_frames), - .probe6(good_frames) -);*/ + + xpm_cdc_pulse #( + .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 + .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output + .RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset + .SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + ) xpm_cdc_frame_sync_pulse_inst ( + .dest_pulse(frame_sync_pulse), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse + // transfer is correctly initiated on src_pulse input. This output is + // combinatorial unless REG_OUTPUT is set to 1. + .dest_clk (clk), // 1-bit input: Destination clock. + .dest_rst (), // 1-bit input: optional; required when RST_USED = 1 + .src_clk (clk_4x), // 1-bit input: Source clock. + .src_pulse (frame_sync_4x), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the + // destination clock domain. The minimum gap between each pulse transfer must be + // at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured + // between the falling edge of a src_pulse to the rising edge of the next + // src_pulse. This minimum gap will guarantee that each rising edge of src_pulse + // will generate a pulse the size of one dest_clk period in the destination + // clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while + // src_rst and/or dest_rst are asserted. + .src_rst () // 1-bit input: optional; required when RST_USED = 1 + ); + + endmodule diff --git a/hdl/SCFDE_recv_FrameSync.v b/hdl/SCFDE_recv_FrameSync.v new file mode 100644 index 0000000..d2cc648 --- /dev/null +++ b/hdl/SCFDE_recv_FrameSync.v @@ -0,0 +1,409 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/12/20 21:52:37 +// Design Name: +// Module Name: SCFDE_recv_FrameSync +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module SCFDE_recv_FrameSync ( + + input clk, + input rst, + input rst_ready, + input [9:0] datain_i, + input [9:0] datain_q, + input debug_loss, + output reg [9:0] Sync_i = 10'd0, + output reg [9:0] Sync_q = 10'd0, + output reg Sync_rdy = 1'b0, //判断出峰的标志位，出峰后拉高1clk + output reg Pilot_rdy = 1'b0, //出峰后88个clk后拉高1clk，对齐导频头 + output reg flag_sync = 1'b0, + output reg Pilot_rdy_hide1_d1 = 1'b0 + + //debug + +); + + //----------卷积与流水累加替代模块----------// + + //wire [19:0] add_regi_2048; + //wire [19:0] add_regq_2048; + wire [18:0] add_regi_19bit; + wire [18:0] add_regq_19bit; + /*conv_add conv_add( + .clk(clk), + .rst(rst), + .data_i(datain_i), + .data_q(datain_q), + .add_regi_2048(add_regi_2048), + .add_regq_2048(add_regq_2048) + );*/ + wire [ 9:0] dataout_i; + wire dout_valid_i; + DMF DMF_i ( + .clk (clk), + .rst (rst), + .din_data (datain_i), + .din_valid (1'b1), + .dout_dmf (add_regi_19bit), + .dout_data (dataout_i), + .dout_valid(dout_valid_i) + ); + + wire [9:0] dataout_q; + wire dout_valid_q; + DMF DMF_q ( + .clk (clk), + .rst (rst), + .din_data (datain_q), + .din_valid (1'b1), + .dout_dmf (add_regq_19bit), + .dout_data (dataout_q), + .dout_valid(dout_valid_q) + ); + + + + //----------将实部和虚部的相关结果求近似模值----------// + //----------6 delay----------// + wire [19:0] reg_add11; + wire [18:0] add_regi; + wire [18:0] add_regq; + wire ApproxAbs_rdy; + + assign add_regi = (add_regi_19bit[18] == 1'd1) ? -add_regi_19bit : add_regi_19bit; + assign add_regq = (add_regq_19bit[18] == 1'd1) ? -add_regq_19bit : add_regq_19bit; + + ApproxAbs_v2_20bit ApproxAbs_v2_tsync4 ( + .clk (clk), + .ND (dout_valid_i), + .Din_I(add_regi), + .Din_Q(add_regq), + .Dout (reg_add11), + .Rdy (ApproxAbs_rdy) + ); + + + //----------将1024个相关结果流水累加----------// + reg rst_1 = 1'b0; + reg [7:0] rst_1_cnt = 8'b0; + always @(posedge clk) begin + if (!ApproxAbs_rdy) begin + rst_1_cnt = 8'b0; + end + else begin + rst_1_cnt <= rst_1_cnt > 8'd128 ? 8'd129 : rst_1_cnt + 8'd1; + end + rst_1 <= (rst_1_cnt < 8'd128); + end + wire [19:0] average_add10; + + average_1024 average_1024 ( + .clk (clk), + .rst (rst_1), + .nd (ApproxAbs_rdy), + .din (reg_add11), + .average(average_add10) + ); + + + //----------将和求平均值，从而得到门限----------// + reg [19:0] reg_save1024 = 20'd0; + reg [19:0] reg_save1024_d1 = 20'd0; + reg [19:0] reg_save1024_d2 = 20'd0; + reg [19:0] reg_save1024_d2_x2 = 20'd0; + reg [19:0] reg_save_pilot; + reg [19:0] Threshold; + reg [ 3:0] th_control = 4'd8; + + always @(posedge clk) begin + if (rst) begin + reg_save1024 <= 20'd0; + reg_save1024_d1 <= 20'd0; + reg_save1024_d2 <= 20'd0; + reg_save1024_d2_x2 <= 20'd0; + Threshold <= 20'd0; + end + else begin + reg_save1024 <= reg_add11; + reg_save1024_d1 <= reg_save1024; + reg_save1024_d2 <= reg_save1024_d1; + case (th_control) + 4'd1: begin + Threshold <= average_add10; + reg_save1024_d2_x2 <= reg_save1024_d1; + end + 4'd2: begin + Threshold <= {average_add10[18:0], 1'b0}; + reg_save1024_d2_x2 <= reg_save1024_d1; + end + 4'd3: begin + Threshold <= average_add10 + {average_add10[18:0], 1'b0}; + reg_save1024_d2_x2 <= reg_save1024_d1; + end + 4'd4: begin + Threshold <= {average_add10[17:0], 2'b00}; + reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0}; + end + 4'd5: begin + Threshold <= average_add10 + {average_add10[17:0], 2'b00}; + reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0}; + end + 4'd6: begin + Threshold <= {average_add10[18:0], 1'b0} + {average_add10[17:0], 2'b00}; + reg_save1024_d2_x2 <= reg_save1024_d1 + {reg_save1024_d1[18:0], 1'b0}; + end + 4'd7: begin + Threshold <= average_add10 + {average_add10[18:0], 1'b0} + {average_add10[17:0], 2'b0}; + reg_save1024_d2_x2 <= reg_save1024_d1 + {reg_save1024_d1[18:0], 1'b0}; + end + 4'd8: begin + Threshold <= {average_add10[16:0], 3'b000}; + reg_save1024_d2_x2 <= {reg_save1024_d1[17:0], 2'b00}; + end + 4'd9: begin + Threshold <= average_add10 + {average_add10[16:0], 3'b000}; + reg_save1024_d2_x2 <= {reg_save1024_d1[17:0], 2'b00}; + end + default: begin + Threshold <= {average_add10[17:0], 2'b00}; + reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0}; + end + endcase + end + end + + //----------将相关求和后的近似模值与门限比较；若高于门限，再与相邻近似模值比较----------// + + reg [ 6:0] counter88 = 7'd0; + //rst之后500个clk之内不允许拉高Pilot_rdy_hide1 + reg [11:0] count_rst500 = 12'd0; + reg [ 3:0] state_framesync; + always @(posedge clk) begin + if (rst) begin + count_rst500 <= 15'd0; + state_framesync <= 4'd0; + counter88 <= 7'd0; + reg_save_pilot <= 20'd0; + Pilot_rdy_hide1_d1 <= 1'b0; + flag_sync <= 1'b0; + Sync_rdy <= 1'b0; + end + else begin + case (state_framesync) + 4'd0: begin + if (count_rst500 == 12'd32) begin //等待32个clk的rst + count_rst500 <= 12'd0; + state_framesync <= 4'd1; + end + else begin + count_rst500 <= count_rst500 + 12'd1; + state_framesync <= state_framesync; + end + end + 4'd1: begin + if (Threshold != 20'd0) begin + state_framesync <= 4'd2; + end + else begin + state_framesync <= state_framesync; + end + end + 4'd2: begin + if (count_rst500 == 12'd2048) begin //等待计数过2048个clk + count_rst500 <= 12'd0; + state_framesync <= 4'd3; + end + else begin + count_rst500 <= count_rst500 + 12'd1; + state_framesync <= state_framesync; + end + end + 4'd3: begin + if ((reg_save1024_d1 > Threshold)) begin //检测到过门限值 + if ((reg_save1024_d1 >= reg_save1024) && (reg_save1024_d1 >= reg_save1024_d2)) begin + if (reg_save1024_d1 >= 20'd128) begin + Sync_rdy <= 1'b1; + state_framesync <= 4'd4; + reg_save_pilot <= reg_save1024_d1; + end + else begin + Sync_rdy <= 1'b0; + state_framesync <= state_framesync; + end + end + + else begin + Sync_rdy <= 1'b0; + end + end + + else begin + Sync_rdy <= 1'b0; + end + end + 4'd4: begin + if (counter88 == 7'd86) begin + Sync_rdy <= 1'b0; + flag_sync <= 1'b1; + Pilot_rdy_hide1_d1 <= 1'b1; + state_framesync <= 4'd5; + end + else if (counter88 >= 7'd32) begin + if (reg_save_pilot >= reg_save1024_d2_x2) begin // ? reg_save_pilot是DMF滤波器输出峰值 + counter88 <= counter88 + 7'd1; + end + else begin + counter88 <= 7'd0; + state_framesync <= 4'd3; + Sync_rdy <= 1'b0; + end + flag_sync <= 1'b0; + end + else begin + counter88 <= counter88 + 7'd1; + flag_sync <= 1'b0; + end + end + 4'd5: begin + flag_sync <= 1'b1; + Pilot_rdy_hide1_d1 <= 1'b0; + state_framesync <= state_framesync; + end + default: begin + if (count_rst500 == 12'd32) begin + count_rst500 <= 12'd0; + state_framesync <= 4'd1; + end + else begin + count_rst500 <= count_rst500 + 12'd1; + state_framesync <= state_framesync; + end + end + endcase + end + end + + //----------将输入数据打延迟，与Sync_rdy拉高的时刻同步输出----------// + reg [9:0] datain_i_d1; + reg [9:0] datain_q_d1; + reg [9:0] datain_i_d2; + reg [9:0] datain_q_d2; + reg [9:0] datain_i_d3; + reg [9:0] datain_q_d3; + reg [9:0] datain_i_d4; + reg [9:0] datain_q_d4; + reg [9:0] datain_i_d5; + reg [9:0] datain_q_d5; + reg [9:0] datain_i_d6; + reg [9:0] datain_q_d6; + reg [9:0] datain_i_d7; + reg [9:0] datain_q_d7; + reg [9:0] datain_i_d8; + reg [9:0] datain_q_d8; + reg [9:0] datain_i_d9; + reg [9:0] datain_q_d9; + /*shift_ram_x shift_ram_i1 ( + .D(datain_i), + .CLK(clk), + .Q(datain_i_d3) + ); + wire [9:0] datain_q_d3; + shift_ram_x shift_ram_q1 ( + .D(datain_q), + .CLK(clk), + .Q(datain_q_d3) + );*/ + always @(posedge clk) begin + if (rst) begin + Sync_i <= 10'd0; + Sync_q <= 10'd0; + datain_i_d1 <= 10'd0; + datain_q_d1 <= 10'd0; + datain_i_d2 <= 10'd0; + datain_q_d2 <= 10'd0; + datain_i_d3 <= 10'd0; + datain_q_d3 <= 10'd0; + datain_i_d4 <= 10'd0; + datain_q_d4 <= 10'd0; + datain_i_d5 <= 10'd0; + datain_q_d5 <= 10'd0; + datain_i_d6 <= 10'd0; + datain_q_d6 <= 10'd0; + datain_i_d7 <= 10'd0; + datain_q_d7 <= 10'd0; + datain_i_d8 <= 10'd0; + datain_q_d8 <= 10'd0; + datain_i_d9 <= 10'd0; + datain_q_d9 <= 10'd0; + end + else begin + datain_i_d1 <= datain_i; + datain_q_d1 <= datain_q; + datain_i_d2 <= datain_i_d1; + datain_q_d2 <= datain_q_d1; + datain_i_d3 <= datain_i_d2; + datain_q_d3 <= datain_q_d2; + datain_i_d4 <= datain_i_d3; + datain_q_d4 <= datain_q_d3; + datain_i_d5 <= datain_i_d4; + datain_q_d5 <= datain_q_d4; + datain_i_d6 <= datain_i_d5; + datain_q_d6 <= datain_q_d5; + datain_i_d7 <= datain_i_d6; + datain_q_d7 <= datain_q_d6; + datain_i_d8 <= datain_i_d7; + datain_q_d8 <= datain_q_d7; + datain_i_d9 <= datain_i_d8; + datain_q_d9 <= datain_q_d8; + Sync_i <= datain_i_d9; + Sync_q <= datain_q_d9; + end + end + + // `ifdef FrameSync_debug + + /* ila_FS_inst ila_FS_inst( + .clk(clk), + .probe0(datain_i),//10 + .probe1(datain_q),//10 + .probe2(rst),//1 + .probe3(Pilot_rdy_hide1_d1),//1 + .probe4(reg_save1024_d2_x2),//20 + .probe5(average_add10),//20 + .probe6(Threshold),//20 + .probe7(reg_save1024_d1),//20 + .probe8(debug_loss),//1 + .probe9(flag_sync),//1 + .probe10(state_framesync),//4 + .probe11(counter88),//7 + .probe12(Sync_rdy),//1 + .probe13(th_control)//4 + + );*/ + + // ILA LARGE + /*ila_large ila_MF_large_inst( + .clk(clk), + .probe0(datain_i[9:0]), + .probe1({rst_ready,rst,Pilot_rdy_hide1}) + );*/ + + // `endif + +endmodule diff --git a/hdl/ad9361_mgc_pin_ctrl.v b/hdl/ad9361_mgc_pin_ctrl.v index a5aba34..eb0355a 100644 --- a/hdl/ad9361_mgc_pin_ctrl.v +++ b/hdl/ad9361_mgc_pin_ctrl.v @@ -14,13 +14,14 @@ module ad9361_mgc_pin_ctrl ( - input clk, + input clk, input rst, - // input start, + input start, input [11:0] rx_data_i, input [11:0] rx_data_q, // this port is from zynq to ad9361 - output wire [ 3:0] ad9361_ctrl_in + output wire [ 3:0] ad9361_ctrl_in, + output reg flag_mgc_done ); @@ -41,6 +42,9 @@ module ad9361_mgc_pin_ctrl ( wire flag_too_low; // low amplitude wire flag_adjust; reg [3:0] cnt_pulse_width; + // indicating the mgc done ready + wire power_measure_done_pulse; + // adjust fsm localparam S_IDLE = 0; @@ -76,6 +80,15 @@ module ad9361_mgc_pin_ctrl ( start_d1 <= start; end + // single pulse to level signal + always @(posedge clk) begin + if (rst) begin + flag_mgc_done <= 0; + end + else if (power_measure_done_pulse) begin + flag_mgc_done <= 1; + end + end // FSM always @(posedge clk) begin @@ -122,21 +135,22 @@ module ad9361_mgc_pin_ctrl ( // measuring the signal power // two cases, amplitute too high or amplitude too low power_measure u_power_measure ( - .clk (clk), - .rst (rst), - .start (start_posedge), - .data_i (rx_data_i), - .data_q (rx_data_q), - .flag_too_high(flag_too_high), - .flag_too_low (flag_too_low) + .clk (clk), + .rst (rst), + .start (start_posedge), + .data_i (rx_data_i), + .data_q (rx_data_q), + .flag_too_high (flag_too_high), + .flag_too_low (flag_too_low), + .power_measure_done_pulse(power_measure_done_pulse) ); // ******** Debug ******** - vio_mgc_control_in u_vio_mgc_control_in ( - .clk (clk), // input wire clk - .probe_out0(start) // output wire [0 : 0] probe_out0 - ); + // vio_mgc_control_in u_vio_mgc_control_in ( + // .clk (clk), // input wire clk + // .probe_out0(start) // output wire [0 : 0] probe_out0 + // ); ila_ad9361_mgc u_ila_ad9361_mgc ( .clk (clk), // input wire clk @@ -148,7 +162,7 @@ module ad9361_mgc_pin_ctrl ( .probe5(flag_too_high), // input wire [0:0] probe5 .probe6(flag_too_low), // input wire [0:0] probe6 .probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6 - .probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6 + .probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6 ); diff --git a/hdl/power_measure.v b/hdl/power_measure.v index 5a4e286..ebdf975 100644 --- a/hdl/power_measure.v +++ b/hdl/power_measure.v @@ -25,7 +25,8 @@ module power_measure ( input wire [11:0] data_i, input wire [11:0] data_q, output reg flag_too_high, - output reg flag_too_low + output reg flag_too_low, + output reg power_measure_done_pulse ); localparam CNT_WAIT_9361_MAX = 80; //* 等待周期数 @@ -56,11 +57,11 @@ module power_measure ( reg [ 3:0] sign_bit_num_min_i; reg [ 3:0] sign_bit_num_q; reg [ 3:0] sign_bit_num_min_q; - + // startup reg [ 7:0] cnt_startup; // set rx gain to max each time start posedge comes reg [ 3:0] cnt_amp_too_high; // for short cuirt - + // abs reg [11:0] data_i_abs; reg [11:0] data_q_abs; @@ -200,6 +201,15 @@ module power_measure ( end end + always @(posedge clk) begin + if (cs == S_MEASURE_ADJ && ns == S_MEASURE_IDLE) begin + power_measure_done_pulse <= 1; + end + else begin + power_measure_done_pulse <= 0; + end + end + // get the abs value always @(posedge clk) begin