`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/01/18 15:02:10
// Design Name: 
// Module Name: Out_Process_R12
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Out_Process_R12(
	input clk,
	input rst,
	
	input encode_din,	//将输入信息比特输出
	input encode_valid,	//下降沿表示完成码字计算
	input [10:0] check_clk_num,		//校验比特个数
	
	input [63:0] en_row_01,
	input [63:0] en_row_02,
	input [63:0] en_row_03,
	input [63:0] en_row_04,
	input [63:0] en_row_05,
	input [63:0] en_row_06,
	input [63:0] en_row_07,
	input [63:0] en_row_08,
	input [63:0] en_row_09,
	input [63:0] en_row_10,
	input [63:0] en_row_11,
	input [63:0] en_row_12,
	input [63:0] en_row_13,
	input [63:0] en_row_14,
	input [63:0] en_row_15,
	input [63:0] en_row_16,
	
	output reg encode_out = 1'd0,
	output reg encode_sync_out = 1'd0,
	output reg encode_rdy = 1'd0
);
	reg encode_valid_d1 = 1'd0; reg encode_valid_d2 = 1'd0;
	always@(posedge clk)begin
		if(rst)begin
			encode_valid_d1 <= 1'd0;
			encode_valid_d2 <= 1'd0;
		end
		else begin
			encode_valid_d1 <= encode_valid;
			encode_valid_d2 <= encode_valid_d1;
		end
	end
	
	reg [10:0] cycle_out_cnt = 11'd0;
	always@(posedge clk)begin
		if(rst)
			cycle_out_cnt[10:0] <= 11'd0;
		else begin
			if(encode_valid_d1 && !encode_valid)
				cycle_out_cnt[10:0] <= 11'd1;
			else begin
				if(cycle_out_cnt[10:0] >= 11'd1)
					cycle_out_cnt[10:0] <= (cycle_out_cnt[10:0] == check_clk_num[10:0]) ? 11'd0 : cycle_out_cnt[10:0] + 11'd1;
				else
					cycle_out_cnt[10:0] <= 11'd0;
			end
		end
	end
	
	reg cycle_out_en = 1'd0;
	always@(posedge clk)begin
		if(rst)
			cycle_out_en <= 1'd0;
		else begin
			if(cycle_out_cnt[10:0] >= 11'd1)
				cycle_out_en <= 1'd1;
			else
				cycle_out_en <= 1'd0;
		end
	end
	
	reg [63:0] en_row_01_tem = 64'd0;  
	reg [63:0] en_row_02_tem = 64'd0;  
	reg [63:0] en_row_03_tem = 64'd0;  
	reg [63:0] en_row_04_tem = 64'd0;  
	reg [63:0] en_row_05_tem = 64'd0;  
	reg [63:0] en_row_06_tem = 64'd0;  
	reg [63:0] en_row_07_tem = 64'd0;  
	reg [63:0] en_row_08_tem = 64'd0;  
	reg [63:0] en_row_09_tem = 64'd0;  
	reg [63:0] en_row_10_tem = 64'd0;  
	reg [63:0] en_row_11_tem = 64'd0;  
	reg [63:0] en_row_12_tem = 64'd0; 
	reg [63:0] en_row_13_tem = 64'd0;  
	reg [63:0] en_row_14_tem = 64'd0;  
	reg [63:0] en_row_15_tem = 64'd0;  
	reg [63:0] en_row_16_tem = 64'd0; 
	always@(posedge clk)begin
		if(rst)begin
			en_row_01_tem[63:0] <= 64'd0;  
			en_row_02_tem[63:0] <= 64'd0;  
			en_row_03_tem[63:0] <= 64'd0;  
			en_row_04_tem[63:0] <= 64'd0;  
			en_row_05_tem[63:0] <= 64'd0;  
			en_row_06_tem[63:0] <= 64'd0;  
			en_row_07_tem[63:0] <= 64'd0;  
			en_row_08_tem[63:0] <= 64'd0;  
			en_row_09_tem[63:0] <= 64'd0;  
			en_row_10_tem[63:0] <= 64'd0;  
			en_row_11_tem[63:0] <= 64'd0;  
			en_row_12_tem[63:0] <= 64'd0; 
			en_row_13_tem[63:0] <= 64'd0;  
			en_row_14_tem[63:0] <= 64'd0;  
			en_row_15_tem[63:0] <= 64'd0;  
			en_row_16_tem[63:0] <= 64'd0; 
		end
		else begin
			if(cycle_out_cnt[10:0] == 11'd1)begin
				en_row_01_tem[63:0] <= en_row_01[63:0];  
				en_row_02_tem[63:0] <= en_row_02[63:0];  
				en_row_03_tem[63:0] <= en_row_03[63:0];  
				en_row_04_tem[63:0] <= en_row_04[63:0];  
				en_row_05_tem[63:0] <= en_row_05[63:0];  
				en_row_06_tem[63:0] <= en_row_06[63:0];  
				en_row_07_tem[63:0] <= en_row_07[63:0];  
				en_row_08_tem[63:0] <= en_row_08[63:0];  
				en_row_09_tem[63:0] <= en_row_09[63:0];  
				en_row_10_tem[63:0] <= en_row_10[63:0];  
				en_row_11_tem[63:0] <= en_row_11[63:0];  
				en_row_12_tem[63:0] <= en_row_12[63:0]; 
				en_row_13_tem[63:0] <= en_row_13[63:0];  
				en_row_14_tem[63:0] <= en_row_14[63:0];  
				en_row_15_tem[63:0] <= en_row_15[63:0];  
				en_row_16_tem[63:0] <= en_row_16[63:0];
			end
			else if(cycle_out_en)begin
				en_row_16_tem[63:0] <= {en_row_16_tem[62:0],en_row_15_tem[63]}; 
				en_row_15_tem[63:0] <= {en_row_15_tem[62:0],en_row_14_tem[63]}; 
				en_row_14_tem[63:0] <= {en_row_14_tem[62:0],en_row_13_tem[63]}; 
				en_row_13_tem[63:0] <= {en_row_13_tem[62:0],en_row_12_tem[63]}; 
				en_row_12_tem[63:0] <= {en_row_12_tem[62:0],en_row_11_tem[63]}; 
				en_row_11_tem[63:0] <= {en_row_11_tem[62:0],en_row_10_tem[63]}; 
				en_row_10_tem[63:0] <= {en_row_10_tem[62:0],en_row_09_tem[63]}; 
				en_row_09_tem[63:0] <= {en_row_09_tem[62:0],en_row_08_tem[63]}; 
				en_row_08_tem[63:0] <= {en_row_08_tem[62:0],en_row_07_tem[63]}; 
				en_row_07_tem[63:0] <= {en_row_07_tem[62:0],en_row_06_tem[63]}; 
				en_row_06_tem[63:0] <= {en_row_06_tem[62:0],en_row_05_tem[63]}; 
				en_row_05_tem[63:0] <= {en_row_05_tem[62:0],en_row_04_tem[63]}; 
				en_row_04_tem[63:0] <= {en_row_04_tem[62:0],en_row_03_tem[63]}; 
				en_row_03_tem[63:0] <= {en_row_03_tem[62:0],en_row_02_tem[63]}; 
				en_row_02_tem[63:0] <= {en_row_02_tem[62:0],en_row_01_tem[63]}; 
				en_row_01_tem[63:0] <= {en_row_01_tem[62:0],1'd0}; 
			end
			else begin
				en_row_01_tem[63:0] <= 64'd0;  
				en_row_02_tem[63:0] <= 64'd0;  
				en_row_03_tem[63:0] <= 64'd0;  
				en_row_04_tem[63:0] <= 64'd0;  
				en_row_05_tem[63:0] <= 64'd0;  
				en_row_06_tem[63:0] <= 64'd0;  
				en_row_07_tem[63:0] <= 64'd0;  
				en_row_08_tem[63:0] <= 64'd0;  
				en_row_09_tem[63:0] <= 64'd0;  
				en_row_10_tem[63:0] <= 64'd0;  
				en_row_11_tem[63:0] <= 64'd0;  
				en_row_12_tem[63:0] <= 64'd0; 
				en_row_13_tem[63:0] <= 64'd0;  
				en_row_14_tem[63:0] <= 64'd0;  
				en_row_15_tem[63:0] <= 64'd0;  
				en_row_16_tem[63:0] <= 64'd0; 
			end
		end
	end
	
	always@(posedge clk)begin
		if(rst)
			encode_out <= 1'd0;
		else begin
			if(cycle_out_en)begin
				encode_out <= en_row_16_tem[63];
			end
			else
				encode_out <= encode_din;
		end
	end
	always@(posedge clk)begin
		if(rst)begin
			encode_rdy <= 1'd0;
			encode_sync_out <= 1'd0;
		end
		else begin
			if(encode_valid_d1 && !encode_valid_d2)
				encode_sync_out <= 1'd1;
			else
				encode_sync_out <= 1'd0; 
				
			encode_rdy <= encode_valid_d2 || cycle_out_en;
		end
	end
	
	
endmodule