module extract_mac_frame (
    input              clk,
    input              rst,
    // ldpc out
    input              ldpc_dec_out_start,
    input              ldpc_dec_out_valid,
    input              ldpc_dec_out_data,
    // axis
    output wire        m_axis_mac_frame_tvalid,
    output wire [31:0] m_axis_mac_frame_tdata,
    input              m_axis_mac_frame_tready,
    output reg         m_axis_mac_frame_tlast

);
    // NOTE: module 1bit --> 32bit
    // transfer 1bit serial to 32bit and sent to axis fifo
    // 

    localparam MAC_FRAME_LEN_BIT = 107520;
    localparam MAC_FRAME_LEN_BYTE = 13440;
    localparam MAC_FRAME_LEN_QUAD_BYTE = 3360;


    // ******** Wire & Reg  ********

    reg  [15:0] cnt_axis_out;
    wire        flag_handshake;
    // serial input 
    wire        ser;
    wire        ser_valid;
    wire [31:0] par;
    wire        par_valid;


    // ******** Assingment  ********

    assign ser                     = ldpc_dec_out_data;
    assign ser_valid               = ldpc_dec_out_valid;
    assign m_axis_mac_frame_tvalid = par_valid;
    assign m_axis_mac_frame_tdata  = par;

    assign flag_handshake          = m_axis_mac_frame_tvalid & m_axis_mac_frame_tready;

    // ******** Logic Block ********

    always @(posedge clk) begin
        if (rst) begin
            cnt_axis_out <= 0;
        end
        else if (flag_handshake) begin
            cnt_axis_out <= cnt_axis_out + 1;
        end
    end

    always @(*) begin
        if (cnt_axis_out == MAC_FRAME_LEN_QUAD_BYTE - 1 && flag_handshake) begin
            m_axis_mac_frame_tlast = 1;
        end
        else begin
            m_axis_mac_frame_tlast = 0;
        end
    end

    // ********    Inst     ********

    // serial 1bit --> 32bit
    ser2par u_ser2par (
        .clk      (clk),
        .rst      (rst),
        .ser      (ser),
        .ser_valid(ser_valid),
        .par      (par),
        .par_valid(par_valid)
    );



    // ********    Debug    ********



endmodule