`timescale 1ns / 1ps

module net_city (
    // basic
    input              clk,
    input              rst_initial,
    input              rst_manual,              //manual
    // tx signal
    output reg         tx_start = 1'b0,         // pulse
    output reg  [63:0] trans_net_data = 64'd0,
    output reg         flag_video_send = 1'b0,
    output reg  [07:0] recv_id = 8'd0,
    // rx signal
    input              frame_sync,
    // input              recv_net_data_nd,
    // input       [63:0] recv_net_data,
    // net parameter
    input       [31:0] frame_sync_time,
    input       [07:0] id_num,
    input       [07:0] max_slot_num,
    input       [07:0] video_id01,
    input       [07:0] video_id02,
    input       [07:0] video_id03,
    // net state
    output reg         is_net = 1'b0,
    output reg         flag_to_uc = 1'b0,
    // intr 2 ps
    output wire        intr_ps,
    output reg         rx_rst,
    input  wire        tx_done
);
    //----------parameter----------
    localparam SLOT_TIME = 750000;  // 15ms

    //----------rst----------
    wire rst;
    assign rst = rst_initial || rst_manual;

    //----------counter_1s----------
    reg [31:0] cnt_1s = 32'd0;
    always @(posedge clk) begin
        if (rst) begin
            cnt_1s <= 32'd0;
        end
        else begin
            if (cnt_1s == 32'd49999999) begin
                cnt_1s <= 32'd0;
            end
            else begin
                cnt_1s <= cnt_1s + 32'd1;
            end
        end
    end

    //----------flag_tx----------


    //----------state_net----------
    reg [07:0] state_net = 8'd0;
    reg [31:0] cnt_trans_slot = 32'd0;
    reg [31:0] cnt_inter_slot = 32'd0;
    reg [07:0] cur_slot = 8'd0;
    reg [07:0] cnt_video_slot = 8'd0;
    reg [31:0] cnt_other = 32'd0;

    reg [07:0] connect_node = 8'd0;
    reg [63:0] trans_net_data_reg = 64'd0;
    reg [07:0] recv_connect_node = 8'd0;
    reg [07:0] recv_video_id01 = 8'd0;
    reg [07:0] recv_video_id02 = 8'd0;
    reg [07:0] recv_video_id03 = 8'd0;

    // if u dont understand this code blew, plz contact NanzZ 😊
    assign intr_ps = (cnt_trans_slot == SLOT_TIME - 50000) && ((id_num == 1 && (cur_slot == max_slot_num - 1)) || (id_num != 1 && (cur_slot == id_num - 8'd2)));

    always @(posedge clk) begin
        if (rst) begin
            rx_rst <= 0;
        end
        else if (tx_start) begin
            rx_rst <= 1;
        end
        else if (tx_done) begin
            rx_rst <= 0;
        end
    end



    always @(posedge clk) begin
        if (rst) begin
            state_net         <= 8'd0;
            cnt_trans_slot    <= 32'd0;
            cnt_inter_slot    <= 32'd0;
            cnt_other         <= 32'd0;
            recv_id           <= 8'd0;
            recv_connect_node <= 8'd0;
            recv_video_id01   <= 8'd0;
            recv_video_id02   <= 8'd0;
            recv_video_id03   <= 8'd0;
            tx_start          <= 1'b0;
            trans_net_data    <= 64'd0;
            is_net            <= 1'b0;
            flag_video_send   <= 1'b0;
        end
        else begin
            case (state_net)
                8'd0: begin
                    state_net         <= 8'd1;
                    cnt_trans_slot    <= 32'd0;
                    cnt_inter_slot    <= 32'd0;
                    cnt_other         <= 32'd0;
                    recv_id           <= recv_id;
                    recv_connect_node <= 8'd0;
                    recv_video_id01   <= recv_video_id01;
                    recv_video_id02   <= recv_video_id02;
                    recv_video_id03   <= recv_video_id03;
                    tx_start          <= 1'b0;
                    trans_net_data    <= 64'd0;
                    is_net            <= 1'b0;
                    flag_video_send   <= 1'b0;
                end
                8'd1: begin
                    state_net <= 8'd2;
                end
                8'd2: begin
                    if (frame_sync) begin
                        state_net      <= 8'd50;
                        cnt_other      <= 32'd0;
                        cnt_trans_slot <= frame_sync_time;
                        cnt_inter_slot <= cnt_trans_slot + 32'd1;
                    end
                    else if (cnt_other == 32'd49999999) begin
                        cnt_other <= 32'd0;
                        state_net <= 8'd100;
                        is_net    <= 1'b1;
                    end
                    else begin
                        cnt_other <= cnt_other + 32'd1;
                    end
                end

                8'd100: begin  // _tx
                    state_net      <= 8'd101;
                    tx_start       <= 1'b1;
                    trans_net_data <= trans_net_data_reg;
                    cnt_trans_slot <= 32'd0;
                    cnt_inter_slot <= 32'd0;
                end
                8'd101: begin
                    state_net      <= 8'd200;
                    tx_start       <= 1'b0;
                    cnt_trans_slot <= cnt_trans_slot + 32'd1;
                end

                8'd200: begin  // wait
                    if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num == 1 && (cur_slot == max_slot_num - 1))) begin
                        state_net      <= 8'd100;
                        cnt_trans_slot <= cnt_trans_slot + 32'd1;
                        cnt_inter_slot <= 32'd0;
                    end
                    else if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num != 1 && (cur_slot == id_num - 8'd2))) begin
                        state_net      <= 8'd100;
                        cnt_trans_slot <= cnt_trans_slot + 32'd1;
                        cnt_inter_slot <= 32'd0;
                    end
                    else if (frame_sync) begin
                        state_net      <= 8'd50;
                        cnt_trans_slot <= frame_sync_time;
                        cnt_inter_slot <= cnt_trans_slot + 32'd1;
                    end
                    else begin
                        if (cnt_trans_slot == SLOT_TIME - 1) begin
                            cnt_trans_slot <= 32'd0;
                        end
                        else begin
                            cnt_trans_slot <= cnt_trans_slot + 32'd1;
                        end
                        cnt_inter_slot <= 32'd0;
                    end

                    case (id_num)
                        recv_video_id01: begin
                            if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd0) begin
                                flag_video_send <= 1'b1;
                            end
                            else begin
                                flag_video_send <= 1'b0;
                            end
                        end
                        recv_video_id02: begin
                            if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd1) begin
                                flag_video_send <= 1'b1;
                            end
                            else begin
                                flag_video_send <= 1'b0;
                            end
                        end
                        recv_video_id03: begin
                            if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd2) begin
                                flag_video_send <= 1'b1;
                            end
                            else begin
                                flag_video_send <= 1'b0;
                            end
                        end
                        default: begin
                            flag_video_send <= 1'b0;
                        end
                    endcase
                end

                8'd50: begin
                    // if (recv_net_data_nd) begin
                    //     if (recv_net_data[23:00] == 24'h7e5a33) begin
                    state_net         <= 8'd51;
                    is_net            <= 1'b1;
                    // cnt_trans_slot    <= cnt_trans_slot + 32'd1;
                    // cnt_inter_slot    <= cnt_inter_slot + 32'd1;
                    // recv_id           <= recv_net_data[63:56];
                    // recv_video_id01   <= recv_net_data[55:48];
                    // recv_video_id02   <= recv_net_data[47:40];
                    // recv_video_id03   <= recv_net_data[39:32];
                    // recv_connect_node <= recv_net_data[31:24];
                    //     end
                    //     else begin
                    //         state_net      <= 8'd200;
                    //         is_net         <= 1'b0;

                    //         cnt_trans_slot <= cnt_inter_slot + 32'd1;
                    //     end
                    // end
                    // else begin
                    //     cnt_trans_slot <= cnt_trans_slot + 32'd1;
                    //     cnt_inter_slot <= cnt_inter_slot + 32'd1;
                    // end
                end
                8'd51: begin
                    state_net      <= 8'd200;
                    cnt_trans_slot <= cnt_trans_slot + 32'd1;
                end

                default: begin
                    state_net         <= 8'd0;
                    cnt_trans_slot    <= 32'd0;
                    cnt_inter_slot    <= 32'd0;
                    cnt_other         <= 32'd0;
                    recv_id           <= recv_id;
                    recv_connect_node <= 8'd0;
                    recv_video_id01   <= recv_video_id01;
                    recv_video_id02   <= recv_video_id02;
                    recv_video_id03   <= recv_video_id03;
                    tx_start          <= 1'b0;
                    trans_net_data    <= 64'd0;
                    is_net            <= 1'b0;
                    flag_video_send   <= 1'b0;
                end
            endcase
        end
    end

    //----------connect_node----------
    // always @(posedge clk) begin
    //     if (rst) begin
    //         connect_node <= 8'd0;
    //     end else begin
    //         if (state_net == 8'd51) begin
    //             case (recv_id)
    //                 8'd1: begin
    //                     connect_node[07:06] <= 2'b11;
    //                 end
    //                 8'd2: begin
    //                     connect_node[05:04] <= 2'b11;
    //                 end
    //                 8'd3: begin
    //                     connect_node[03:02] <= 2'b11;
    //                 end
    //                 8'd4: begin
    //                     connect_node[01:00] <= 2'b11;
    //                 end
    //                 default: begin
    //                     connect_node <= 8'd0;
    //                 end
    //             endcase
    //         end else if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num) begin
    //             connect_node <= 8'd0;
    //         end else begin
    //             connect_node <= connect_node;
    //         end
    //     end
    // end

    //----------trans_net_data_reg----------
    reg [07:0] trans_video_id01;
    reg [07:0] trans_video_id02;
    reg [07:0] trans_video_id03;
    always @(posedge clk) begin
        if (rst) begin
            trans_video_id01 <= 8'd0;
            trans_video_id02 <= 8'd0;
            trans_video_id03 <= 8'd0;
        end
        else begin
            if (id_num == 8'd1) begin  //主节点
                trans_video_id01 <= video_id01;
                trans_video_id02 <= video_id02;
                trans_video_id03 <= video_id03;
            end
            else if (recv_id == 8'd1) begin  //从节点只听从主节点命令
                trans_video_id01 <= recv_video_id01;
                trans_video_id02 <= recv_video_id02;
                trans_video_id03 <= recv_video_id03;
            end
            else begin
                trans_video_id01 <= trans_video_id01;
                trans_video_id02 <= trans_video_id02;
                trans_video_id03 <= trans_video_id03;
            end
        end
    end
    always @(posedge clk) begin
        if (rst) begin
            trans_net_data_reg <= 64'd0;
        end
        else begin
            if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num - 8'd1) begin
                trans_net_data_reg[63:56] <= id_num;
                trans_net_data_reg[55:48] <= trans_video_id01;
                trans_net_data_reg[47:40] <= trans_video_id02;
                trans_net_data_reg[39:32] <= trans_video_id03;
                trans_net_data_reg[31:24] <= connect_node;
                trans_net_data_reg[23:00] <= 24'h7e5a33;
            end
            else begin
                trans_net_data_reg <= trans_net_data_reg;
            end
        end
    end

    //----------cur_slot----------
    always @(posedge clk) begin
        if (rst) begin
            cur_slot <= 8'd0;
        end
        else begin
            if (state_net == 8'd51) begin
                if (recv_id <= max_slot_num) begin
                    cur_slot <= recv_id - 8'd1;
                end
                else begin
                    cur_slot <= cur_slot;
                end
            end
            else if (cnt_trans_slot == SLOT_TIME - 1) begin
                if (cur_slot == max_slot_num - 8'd1) begin
                    cur_slot <= 8'd0;
                end
                else begin
                    cur_slot <= cur_slot + 8'd1;
                end
            end
            else begin
                cur_slot <= cur_slot;
            end
        end
    end

    //----------cnt_video_slot----------
    always @(posedge clk) begin
        if (rst) begin
            cnt_video_slot <= 8'd0;
        end
        else begin
            if (cnt_trans_slot == SLOT_TIME - 1) begin
                if (cnt_video_slot == 8'd2) begin
                    cnt_video_slot <= 8'd0;
                end
                else begin
                    cnt_video_slot <= cnt_video_slot + 8'd1;
                end
            end
            else begin
                cnt_video_slot <= cnt_video_slot;
            end
        end
    end

    always @(posedge clk) begin
        if (rst) begin
            flag_to_uc <= 1'b0;
        end
        else begin
            if (cnt_trans_slot == SLOT_TIME / 2 - 1) begin
                flag_to_uc <= 1'b1;
            end
            else begin
                flag_to_uc <= 1'b0;
            end
        end
    end

    ila_MAC ila_MAC (
        .clk    (clk),
        .probe0 (tx_start),
        .probe1 (connect_node),
        .probe2 (cnt_trans_slot),
        .probe3 (recv_net_data),
        .probe4 (state_net),
        .probe5 (recv_id),
        .probe6 (cur_slot),
        .probe7 (id_num),
        .probe8 (frame_sync),
        .probe9 (max_slot_num),
        .probe10(recv_net_data_nd),
        .probe11(trans_net_data)
    );
endmodule