`timescale 1ns / 1ns

module tb_Transmitter ();



    reg clk = 1;
    reg clk_tx = 1;

    reg rst = 1;

    always #1 clk <= ~clk;
    always #2 clk_tx <= ~clk_tx;
    reg intr = 0;
    reg test=0;

    initial begin
        #100 rst <= 0;
        #1000 test <=1;
        #1000 test <=0;
        #1000 test <=1;
        #1000 test <=1;
    end

    Transmitter #(
        .AGC_HEADER_LEN(200),
        .FRAME_HEADER_LEN(512),
        .BLOCK_NUM(3),
        .PHASE1_LEN(2112),
        .PREFIX_LEN(8),
        .CHU_SEQ_LEN(128),
        .GAP_LEN(128)
    ) u_Transmitter (
        .clk               (clk_tx),
        .rst               (rst),
        .speed_mode        (0),
        .send_data_ready   (),
        .send_start        (),
        .send_over         (),
        .clk_data_src      (),
        .tx_data_src_tdata (),
        .tx_data_src_tready(),
        .tx_data_src_tvalid(),
        .hopping_freq      (),
        .ad9361_tx_data_i  (),
        .ad9361_tx_data_q  (),
        .test              (test),
        .hop_wait          (2000)
    );



endmodule