`timescale 1ns / 100ps
module tb_sys_tx_rx_e_d ();

    reg ad9361_rx_clk = 0;  // 50MHz 20ns
    reg clk_crystal = 0;  // 40MHz 25ns

    always #(10) ad9361_rx_clk = ~ad9361_rx_clk;
    always #(12.5) clk_crystal = ~clk_crystal;

    // ******** Wire & Reg  ********

    // power on clock domain
    wire        clk_poweron;
    (*max_fanout = 256 *)
    wire        rst_sys;
    wire        poweron_locked;

    // ad9361 clock domain
    wire        locked;
    wire        clk_1x;
    wire        clk_2x;
    wire        clk_4x;

    // enc signal
    wire        enc_fifo_rd_en;
    wire [31:0] enc_fifo_dout_map;
    wire        enc_fifo_empty;

    // tx bus
    wire        clk_tx_data_src;
    reg  [31:0] tx_data_src_count;
    reg  [31:0] tx_data_src_tdata;
    wire        tx_data_src_tready;
    reg         tx_data_src_tvalid;
    // tx signal 
    wire        tx_test_flag;

    // baseband signal
    wire [11:0] ad9361_rx_data_i;
    wire [11:0] ad9361_rx_data_q;
    wire        ad9361_rx_frame_i;
    wire        ad9361_rx_frame_q;
    wire [11:0] ad9361_tx_data_i;
    wire [11:0] ad9361_tx_data_q;
    wire [ 2:0] speed_mode;

    // phy control signal
    wire        phy_rst_vio;
    wire        phy_rst_ps;
    wire        phy_rst;
    wire        phy_tx_test_flag_vio;
    wire        phy_tx_test_flag;


    // ***** simulation *****
    reg  [ 3:0] cnt_delay = 0;
    reg  [31:0] idx = 0;
    reg         send_start = 0;
    reg  [31:0] mem                  [0:31];  // 1024 bit
    initial begin
        $readmemh("C:/Users/ZoroGH/dev/vivadoPrj/MM7020/source/sim/sim_data/enc_src.txt", mem);
    end
    always @(posedge clk_1x) send_start <= (cnt_delay >= 4'hA) && (cnt_delay <= 4'hE);

    // ******** Assingment  ********
    assign ad9361_tx_clk = clk_1x;
    assign rst_sys       = ~poweron_locked;
    // ******** Logic Block ********

    // ************************             ************************
    // ************************ simulation  ************************
    // ************************             ************************




    always @(posedge clk_poweron) begin
        if (rst_sys) begin
            cnt_delay <= 0;
        end
        else if (cnt_delay < 4'hF) begin
            cnt_delay <= cnt_delay + 1;
        end
    end

    always @(posedge clk_poweron) begin
        if (rst_sys) begin
            idx                <= 0;
            tx_data_src_tvalid <= 0;
            tx_data_src_tdata  <= 0;
            tx_data_src_count  <= 32;
        end
        else if (cnt_delay == 4'hF) begin
            tx_data_src_tvalid <= 1;
            tx_data_src_tdata  <= mem[idx];
            if (tx_data_src_tready) begin
                if (idx < 31) begin
                    idx               <= idx + 1;
                    tx_data_src_count <= tx_data_src_count - 1;
                end
                else begin
                    idx               <= 0;
                    tx_data_src_count <= 32;
                end
            end

        end
    end


    // ************************************************************
    // ************************ simulation ************************
    // ************************************************************


    // ********    Inst     ********

    clk_wiz_poweron u_clk_wiz_poweron (
        // Clock out ports
        .clk_poweron(clk_poweron),     // output clk_poweron
        // Status and control signals
        .locked     (poweron_locked),  // output locked
        // Clock in ports
        .clk_crystal(clk_crystal)      // input clk_crystal
    );

    // clock domain - ad9361 rx & tx 
    clk_wiz_baseband u_clk_wiz_baseband (
        // Clock out ports
        .clk_1x (clk_1x),        // output clk_1x
        .clk_2x (clk_2x),        // output clk_2x
        .clk_4x (clk_4x),        // output clk_4x
        // Status and control signals
        .locked (locked),        // output locked
        // Clock in ports
        .clk_src(ad9361_rx_clk)  // input clk_src
    );

    // ************************************************************
    // *************************** TX *****************************
    // ************************************************************


    enc_control u_enc_control (
        .clk                  (clk_poweron),
        .rst                  (rst_sys),
        .s_axis_fifo_tvalid   (tx_data_src_tvalid),
        .s_axis_fifo_tready   (tx_data_src_tready),
        .s_axis_fifo_tdata    (tx_data_src_tdata),
        .data_src_count       (tx_data_src_count),
        .fifo_enc_out_rd_clk  (clk_1x),
        .fifo_enc_out_rd_en   (enc_fifo_rd_en),
        .fifo_enc_out_dout_map(enc_fifo_dout_map),
        .fifo_enc_out_empty   (enc_fifo_empty)
    );

    Transmitter #(
        .AGC_HEADER_LEN(2500)
    ) u_Transmitter (
        .clk               (clk_1x),
        .rst               (rst_sys),
        .speed_mode        (2),
        .send_data_ready   (send_data_ready),
        .send_start        (send_start),
        .send_over         (send_over),
        .clk_data_src      (clk_data_src),
        .tx_data_src_tdata (enc_fifo_dout_map),
        .tx_data_src_tready(enc_fifo_rd_en),
        .tx_data_src_tvalid(~enc_fifo_empty),
        .hopping_freq      (),
        .ad9361_tx_data_i  (ad9361_tx_data_i),
        .ad9361_tx_data_q  (ad9361_tx_data_q),
        .test              (0),
        .hop_wait          (100)
    );


    // ************************************************************
    // *************************** RX *****************************
    // ************************************************************


    RecvTop u_RecvTop (
        .clk              (clk_1x),
        .clk_2x           (clk_2x),
        .clk_4x           (clk_4x),
        .rst              (rst_sys),
        .rst2             (rst_sys),
        .dini             (ad9361_tx_data_i),
        .dinq             (ad9361_tx_data_q),
        .ad9361_ctrl_in   (),
        .vio_tsync_inter16(1),
        .EQUenable_vio    (1),
        .Zerozone_vio     (8'd29),
        .vio_stopbit      (7'd60),
        .flag_stop        (flag_stop),
        .addr_stop        (addr_stop),
        .recvNetData      (recvNetData),
        .recvNetDataNd    (recvNetDataNd)
    );














endmodule