`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/26 17:05:11
// Design Name: 
// Module Name: tb_tdma
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_tdma ();

    reg clk = 1;
    reg rst = 1;
    always #1 clk <= ~clk;
    initial begin
        #10 rst <= 1'b0;
    end

    reg [7:0] local_id = 0;

    initial begin
        #20 local_id <= 1;
    end


    reg       flag_frame_sync = 0;
    reg       recevied_cur_slot_id_valid = 0;
    reg [7:0] recevied_cur_slot_id = 0;

    tdma u_tdma_master (
        .clk                       (clk),
        .rst                       (rst),
        .flag_frame_sync           (flag_frame_sync),
        .tdma_slot_len             (24'd7500),
        .tdma_tic_2_ps             (24'd6000),
        .tdma_slot_num             (8'd4),
        .local_id                  (local_id),
        .recevied_cur_slot_id_valid(recevied_cur_slot_id_valid),
        .recevied_cur_slot_id      (recevied_cur_slot_id),
        .intr_2ps                  (),
        .tx_start                  (),
        .rx_rst                    ()
    );


    reg       flag_frame_sync_slave = 0;
    reg       recevied_cur_slot_id_valid_slave = 0;
    reg [7:0] recevied_cur_slot_id_slave = 7;
    reg [7:0] local_id_slave = 10;
    reg [7:0] cnt = 0;
    always @(posedge clk) begin
        if (cnt < 8'hFF) begin
            cnt <= cnt + 1;
        end
    end

    always @(posedge clk) begin
        if (cnt == 8'hF3) begin
            flag_frame_sync_slave <= 1;
        end
        else begin
            flag_frame_sync_slave <= 0;
        end
        if (cnt == 8'hFE) begin
            recevied_cur_slot_id_valid_slave <= 1;
        end
        else begin
            recevied_cur_slot_id_valid_slave <= 0;
        end
    end

    tdma u_tdma_slave (
        .clk                       (clk),
        .rst                       (rst),
        .flag_frame_sync           (flag_frame_sync_slave),
        .tdma_slot_len             (24'd7500),
        .tdma_tic_2_ps             (24'd6000),
        .tdma_slot_num             (8'd10),
        .local_id                  (local_id_slave),
        .recevied_cur_slot_id_valid(recevied_cur_slot_id_valid_slave),
        .recevied_cur_slot_id      (recevied_cur_slot_id_slave),
        .intr_2ps                  (),
        .tx_start                  (),
        .rx_rst                    ()
    );


endmodule