`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/18 23:18:07
// Design Name: 
// Module Name: CK_PRO
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module CK_PRO
    #(
        parameter Index_p1_row_01_dec_01_01=0, Index_p1_row_01_dec_02_01=0,
        parameter Index_p1_row_02_dec_02_01=0, Index_p1_row_02_dec_03_01=0,
        parameter Index_p1_row_03_dec_03_01=0, Index_p1_row_03_dec_04_01=0,
        parameter Index_p1_row_04_dec_04_01=0, Index_p1_row_04_dec_01_01=112,
        
        parameter Index_p2_row_01_dec_05_01=0, Index_p2_row_01_dec_05_02=25, Index_p2_row_01_dec_08_01=31,Index_p2_row_01_dec_07_01=39,
        parameter Index_p2_row_02_dec_06_01=0, Index_p2_row_02_dec_06_02=75, Index_p2_row_02_dec_05_01=23,Index_p2_row_02_dec_08_01=16,
        parameter Index_p2_row_03_dec_07_01=0, Index_p2_row_03_dec_07_02=120,Index_p2_row_03_dec_06_01=54,Index_p2_row_03_dec_05_01=0,
        parameter Index_p2_row_04_dec_08_01=0, Index_p2_row_04_dec_08_02=93, Index_p2_row_04_dec_07_01=9, Index_p2_row_04_dec_06_01=83,
        
        parameter Index_p3_row_01_dec_09_01=0, Index_p3_row_01_dec_09_02=13, Index_p3_row_01_dec_11_01=97, Index_p3_row_01_dec_10_01=0,  Index_p3_row_01_dec_12_01=34,
        parameter Index_p3_row_02_dec_10_01=0, Index_p3_row_02_dec_10_02=69, Index_p3_row_02_dec_12_01=64, Index_p3_row_02_dec_11_01=6,  Index_p3_row_02_dec_09_01=98,
        parameter Index_p3_row_03_dec_11_01=0, Index_p3_row_03_dec_11_02=127,Index_p3_row_03_dec_09_01=78, Index_p3_row_03_dec_12_01=35, Index_p3_row_03_dec_10_01=26,
        parameter Index_p3_row_04_dec_12_01=0, Index_p3_row_04_dec_12_02=29, Index_p3_row_04_dec_10_01=81, Index_p3_row_04_dec_09_01=99, Index_p3_row_04_dec_11_01=59
     )
    (
    input clk,
    input rst_OUTCK,
    input start_OUTCK,
    input nd_OUTCK,
    input [0:0] DR_din_01,
    input [0:0] DR_din_02,
    input [0:0] DR_din_03,
    input [0:0] DR_din_04,
    input [0:0] DR_din_05,
    
    output reg [8:0] gd_frames=9'd0,//译码好帧计数
    output reg [8:0] bd_frames=9'd0,//译码坏帧计数
    output reg [8:0] tl_frames=9'd0 //译码总帧数计数
    );

    reg [127:0] dec_01 = 128'd0, dec_02 = 128'd0, dec_03 = 128'd0, dec_04 = 128'd0;
    reg [127:0] dec_05 = 128'd0, dec_06 = 128'd0, dec_07 = 128'd0, dec_08 = 128'd0;
    reg [127:0] dec_09 = 128'd0, dec_10 = 128'd0, dec_11 = 128'd0, dec_12 = 128'd0;
    reg [127:0] dec_01_d1 = 128'd0, dec_02_d1 = 128'd0, dec_03_d1 = 128'd0, dec_04_d1 = 128'd0;
    reg [127:0] dec_05_d1 = 128'd0, dec_06_d1 = 128'd0, dec_07_d1 = 128'd0, dec_08_d1 = 128'd0;
    reg [127:0] dec_09_d1 = 128'd0, dec_10_d1 = 128'd0, dec_11_d1 = 128'd0, dec_12_d1 = 128'd0;
    
    reg [10:0] cnt_CK=11'd0;
    reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_end_d5=1'd0,dec_proc=1'd0;
    // 产生本模块的计数器
    always @ (posedge clk) begin
        if (rst_OUTCK) begin
            dec_proc <= 1'd0;
            cnt_CK <= 11'd0;
        end else begin
            if (start_OUTCK) begin
                dec_proc <= 1'd1;
                cnt_CK <= 11'd0;
            end else begin
                if (dec_proc) begin
                    if (cnt_CK < 11'd560) begin
                        cnt_CK <= cnt_CK + 11'd1;
						dec_proc <= dec_proc;
                    end else begin
                        cnt_CK <= cnt_CK;
                        dec_proc <= 1'd0;
                    end
                end else begin
                    cnt_CK <= cnt_CK;
                end                
            end
        end
    end
	
    parameter DELAY_DIN = 11'd0;
    always @ (posedge clk) begin
        if (rst_OUTCK || start_OUTCK) begin
            dec_01 <= 128'd0; dec_01_d1 <= 128'd0;
            dec_02 <= 128'd0; dec_02_d1 <= 128'd0;    
            dec_03 <= 128'd0; dec_03_d1 <= 128'd0;    
            dec_04 <= 128'd0; dec_04_d1 <= 128'd0; 
               
            dec_05 <= 128'd0; dec_05_d1 <= 128'd0;    
            dec_06 <= 128'd0; dec_06_d1 <= 128'd0;    
            dec_07 <= 128'd0; dec_07_d1 <= 128'd0;    
            dec_08 <= 128'd0; dec_08_d1 <= 128'd0; 
               
            dec_09 <= 128'd0; dec_09_d1 <= 128'd0;    
            dec_10 <= 128'd0; dec_10_d1 <= 128'd0;    
            dec_11 <= 128'd0; dec_11_d1 <= 128'd0;    
            dec_12 <= 128'd0; dec_12_d1 <= 128'd0;
           
		   deal_end <= 1'd0;  
        end else begin
		//  本来3行5列的H矩阵转置后变成5行3列
            // 第1列（4*128=512）个校验子求解过程
            if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
                dec_01[Index_p1_row_01_dec_01_01] <= DR_din_03 ^ DR_din_05;
                dec_02[Index_p1_row_01_dec_02_01] <= DR_din_05;
            end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
				dec_01[Index_p1_row_01_dec_01_01] <= 1'd0;
                dec_02[Index_p1_row_02_dec_02_01] <= DR_din_03 ^ DR_din_05;
                dec_03[Index_p1_row_02_dec_03_01] <= DR_din_05;                
            end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin
                dec_03[Index_p1_row_03_dec_03_01] <= DR_din_03 ^ DR_din_05;
                dec_04[Index_p1_row_03_dec_04_01] <= DR_din_05;
            end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin
                dec_04[Index_p1_row_04_dec_04_01] <= DR_din_03 ^ DR_din_05;
                dec_01[Index_p1_row_04_dec_01_01] <= DR_din_05;               
            end else begin
                dec_01 <= dec_01;
                dec_02 <= dec_02;
                dec_03 <= dec_03;
                dec_04 <= dec_04;
            end     
              
            if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
                dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]} ^ dec_01;
                dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]} ^ dec_02;  
            end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
                dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]} ^ dec_02; 
                dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]} ^ dec_03;            
            end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin
                dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]} ^ dec_03;
                dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]} ^ dec_04;                
            end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin
                dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]} ^ dec_04;
                dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]} ^ dec_01;
            end else if (cnt_CK == 11'd514 + DELAY_DIN) begin                
                dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]};
                dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]};
                dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]};
                dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]};
            end else begin
                dec_01_d1 <= dec_01_d1;
                dec_02_d1 <= dec_02_d1;
                dec_03_d1 <= dec_03_d1;
                dec_04_d1 <= dec_04_d1;
                deal_end  <= 1'd0;
            end 
            

               
            // 第2列（4*128=512）个校验子求解过程
            if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
                    dec_05[Index_p2_row_01_dec_05_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
                    dec_05[Index_p2_row_01_dec_05_02] <= DR_din_05;
                    dec_08[Index_p2_row_01_dec_08_01] <= DR_din_05;
                    dec_07[Index_p2_row_01_dec_07_01] <= DR_din_05;
            end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
                    dec_06[Index_p2_row_02_dec_06_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
                    dec_06[Index_p2_row_02_dec_06_02] <= DR_din_05;
                    dec_05[Index_p2_row_02_dec_05_01] <= DR_din_05;
                    dec_05[Index_p2_row_01_dec_05_01] <= 1'd0;
                    dec_05[Index_p2_row_01_dec_05_02] <= 1'd0;                    
                    dec_08[Index_p2_row_02_dec_08_01] <= DR_din_05;
                    dec_08[Index_p2_row_01_dec_08_01] <= 1'd0;
					dec_07[Index_p2_row_01_dec_07_01] <= 1'd0;   //xhx
            end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin 
                    dec_07[Index_p2_row_03_dec_07_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
                    dec_07[Index_p2_row_03_dec_07_02] <= DR_din_05;
                    dec_06[Index_p2_row_03_dec_06_01] <= DR_din_05;
                    dec_06[Index_p2_row_02_dec_06_01] <= 1'd0;
                    dec_06[Index_p2_row_02_dec_06_02] <= 1'd0;                    
                    dec_05[Index_p2_row_03_dec_05_01] <= DR_din_05;
                    dec_05[Index_p2_row_02_dec_05_01] <= 1'd0;
					dec_08[Index_p2_row_02_dec_08_01] <= 1'd0;   //xhx
            end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin  
                    dec_08[Index_p2_row_04_dec_08_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
                    dec_08[Index_p2_row_04_dec_08_02] <= DR_din_05;
                    dec_07[Index_p2_row_04_dec_07_01] <= DR_din_05;
                    dec_07[Index_p2_row_03_dec_07_01] <= 1'd0;
                    dec_07[Index_p2_row_03_dec_07_02] <= 1'd0;
                    dec_06[Index_p2_row_04_dec_06_01] <= DR_din_05;
                    dec_06[Index_p2_row_03_dec_06_01] <= 1'd0;
					dec_05[Index_p2_row_03_dec_05_01] <= 1'd0;   //xhx
            end else begin
                dec_05 <= dec_05;
                dec_06 <= dec_06;
                dec_07 <= dec_07;                
                dec_08 <= dec_08;
            end 
                       
            if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
                    dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
                    dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
                    dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
            end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
                    dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
                    dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
                    dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
            end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin 
                    dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
                    dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
                    dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
            end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin  
                    dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
                    dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
                    dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
            end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
                dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]};
                dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]};
                dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]};
                dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]};
            end else begin
                dec_05_d1 <= dec_05_d1;
                dec_06_d1 <= dec_06_d1;
                dec_07_d1 <= dec_07_d1;
                dec_08_d1 <= dec_08_d1;
            end
            
            
           // 第3列（4*128=512）个校验子求解过程 
            if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
                    dec_09[Index_p3_row_01_dec_09_01] <= DR_din_01 ^ DR_din_05;
                    dec_09[Index_p3_row_01_dec_09_02] <= DR_din_04;
                    dec_11[Index_p3_row_01_dec_11_01] <= DR_din_02;
                    dec_10[Index_p3_row_01_dec_10_01] <= DR_din_02;
                    dec_12[Index_p3_row_01_dec_12_01] <= DR_din_04;
            end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
                    dec_10[Index_p3_row_02_dec_10_01] <= DR_din_01 ^ DR_din_05;
                    dec_10[Index_p3_row_02_dec_10_02] <= DR_din_04;
                    dec_12[Index_p3_row_02_dec_12_01] <= DR_din_02;
                    dec_12[Index_p3_row_01_dec_12_01] <= 1'd0;
                    dec_11[Index_p3_row_02_dec_11_01] <= DR_din_02;
                    dec_11[Index_p3_row_01_dec_11_01] <= 1'd0;
                    dec_09[Index_p3_row_02_dec_09_01] <= DR_din_04;
                    dec_09[Index_p3_row_01_dec_09_01] <= 1'd0;
                    dec_09[Index_p3_row_01_dec_09_02] <= 1'd0;
            end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin 
                    dec_11[Index_p3_row_03_dec_11_01] <= DR_din_01 ^ DR_din_05;
                    dec_11[Index_p3_row_03_dec_11_02] <= DR_din_04;
                    dec_11[Index_p3_row_02_dec_11_01] <= 1'd0;
                    dec_09[Index_p3_row_03_dec_09_01] <= DR_din_02;
                    dec_09[Index_p3_row_02_dec_09_01] <= 1'd0;
                    dec_12[Index_p3_row_03_dec_12_01] <= DR_din_02;
                    dec_12[Index_p3_row_02_dec_12_01] <= 1'd0;
                    dec_10[Index_p3_row_03_dec_10_01] <= DR_din_04;
                    dec_10[Index_p3_row_02_dec_10_01] <= 1'd0;
                    dec_10[Index_p3_row_02_dec_10_02] <= 1'd0;
            end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin  
                    dec_12[Index_p3_row_04_dec_12_01] <= DR_din_01 ^ DR_din_05;
                    dec_12[Index_p3_row_04_dec_12_02] <= DR_din_04;
                    dec_12[Index_p3_row_03_dec_12_01] <= 1'd0;
                    dec_10[Index_p3_row_04_dec_10_01] <= DR_din_02;
                    dec_10[Index_p3_row_03_dec_10_01] <= 1'd0;
                    dec_09[Index_p3_row_04_dec_09_01] <= DR_din_02;
                    dec_09[Index_p3_row_03_dec_09_01] <= 1'd0;
                    dec_11[Index_p3_row_04_dec_11_01] <= DR_din_04;
                    dec_11[Index_p3_row_03_dec_11_01] <= 1'd0;
                    dec_11[Index_p3_row_03_dec_11_02] <= 1'd0;
            end else begin
                dec_09 <= dec_09;
                dec_10 <= dec_10;
                dec_11 <= dec_11;                
                dec_12 <= dec_12;
            end 
                       
            if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
                    dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
                    dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
                    dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
                    dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
            end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
                    dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
                    dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
                    dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
                    dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
            end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin 
                    dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
                    dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
                    dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
                    dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
            end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin  
                    dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
                    dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
                    dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
                    dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
            end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
                dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]};
                dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]};
                dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]};
                dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]};
            end else begin
                dec_09_d1 <= dec_09_d1;
                dec_10_d1 <= dec_10_d1;
                dec_11_d1 <= dec_11_d1;
                dec_12_d1 <= dec_12_d1;
            end
            
            // 产生标志位
            if (cnt_CK == 11'd514 + DELAY_DIN) 
                deal_end  <= 1'd1;
            else
                deal_end  <= 1'd0;
        end
    end
	
	//2019.02.28添加：打一拍，尝试避免时序问题
	reg	deal_end_d6 = 1'd0;
	reg	flag_judge1 = 1'd0;
	reg	flag_judge2 = 1'd0;
	reg	flag_judge3 = 1'd0;
	always@(posedge clk) begin
        if(rst_OUTCK) begin
			flag_judge1	<= 1'd0;
			flag_judge2	<= 1'd0;
			flag_judge3	<= 1'd0;
		end
		else begin
			if(deal_end_d5) begin
                if(dec_01_d1 == 128'd0 && dec_02_d1 == 128'd0 && dec_03_d1 == 128'd0 && dec_04_d1 == 128'd0 )	flag_judge1	<= 1'd0;
				else																							flag_judge1	<= 1'd1;
                if(dec_05_d1 == 128'd0 && dec_06_d1 == 128'd0 && dec_07_d1 == 128'd0 && dec_08_d1 == 128'd0 )	flag_judge2	<= 1'd0;
                else																							flag_judge2	<= 1'd1;
                if(dec_09_d1 == 128'd0 && dec_10_d1 == 128'd0 && dec_11_d1 == 128'd0 && dec_12_d1 == 128'd0 )	flag_judge3	<= 1'd0;
				else																							flag_judge3	<= 1'd1;
			end
			else begin
				flag_judge1	<= flag_judge1;
				flag_judge2	<= flag_judge2;
				flag_judge3	<= flag_judge3;
			end
		end
	end
	
 
	always@(posedge clk) begin
        if(rst_OUTCK) begin
            gd_frames   <= 9'd0;
            bd_frames   <= 9'd0;
            tl_frames   <= 9'd0;
            deal_end_d1 <= 1'd0;
            deal_end_d2 <= 1'd0;
            deal_end_d3 <= 1'd0;
			deal_end_d4 <= 1'd0;
			deal_end_d5 <= 1'd0;
			deal_end_d6 <= 1'd0;	//2019.02.28添加
        end else begin
        	deal_end_d1 <= deal_end;
        	deal_end_d2 <= deal_end_d1;
        	deal_end_d3 <= deal_end_d2;
			deal_end_d4 <= deal_end_d3;
			deal_end_d5 <= deal_end_d4;
			deal_end_d6 <= deal_end_d5;	//2019.02.28添加
            if(deal_end_d6) begin
                if(flag_judge1 == 1'd0 && flag_judge2 == 1'd0 && flag_judge3 == 1'd0 ) begin
				// if(dec_01_d1 == 128'd0 && dec_02_d1 == 128'd0 && dec_03_d1 == 128'd0 && dec_04_d1 == 128'd0 &&
                   // dec_05_d1 == 128'd0 && dec_06_d1 == 128'd0 && dec_07_d1 == 128'd0 && dec_08_d1 == 128'd0 &&
                   // dec_09_d1 == 128'd0 && dec_10_d1 == 128'd0 && dec_11_d1 == 128'd0 && dec_12_d1 == 128'd0  ) begin
                    gd_frames <= gd_frames + 9'd1;
                    bd_frames <= bd_frames;
                    tl_frames <= tl_frames + 9'd1;
                end else begin
                    gd_frames <= gd_frames;
                    bd_frames <= bd_frames + 9'd1;
                    tl_frames <= tl_frames + 9'd1;
                end
            end else begin
                gd_frames <= gd_frames;
                bd_frames <= bd_frames;
                tl_frames <= tl_frames;
            end
        end
    end   

	
endmodule