`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/18 23:18:07
// Design Name: 
// Module Name: CN_PRO
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module CN_PRO
    #(
        parameter WIDTH = 4'd8
     )
    (
    input clk,
    input rst_CN,
    input start_CN,                //模块启动信号，高脉冲
    
    //VN数据输出，H阵第１行             
    input  [WIDTH-1:0] VN1_dout_01_00, 
    input  [WIDTH-1:0] VN1_dout_02_00, //后面的00代表H阵原模图的IM
    input  [WIDTH-1:0] VN1_dout_02_01, //后面的01代表H阵原模图的II1
    //VN数据输出，H阵第２行            
    input  [WIDTH-1:0] VN2_dout_01_00,
    input  [WIDTH-1:0] VN2_dout_02_00,
    input  [WIDTH-1:0] VN2_dout_03_00,
    input  [WIDTH-1:0] VN2_dout_04_02, //后面的02代表H阵原模图的II2
    input  [WIDTH-1:0] VN2_dout_04_03, //后面的03代表H阵原模图的II3
    input  [WIDTH-1:0] VN2_dout_04_04, //后面的04代表H阵原模图的II4
    //VN数据输出，H阵第３行            
    input  [WIDTH-1:0] VN3_dout_01_00,
    input  [WIDTH-1:0] VN3_dout_02_05, //后面的05代表H阵原模图的II5
    input  [WIDTH-1:0] VN3_dout_02_06, //后面的06代表H阵原模图的II6
    input  [WIDTH-1:0] VN3_dout_03_07, //后面的07代表H阵原模图的II7
    input  [WIDTH-1:0] VN3_dout_03_08, //后面的08代表H阵原模图的II8
    input  [WIDTH-1:0] VN3_dout_04_00,
    
    //VN读地址，H阵第１行
    output reg [8:0] VN1_addr_rd_01_00=9'd511,
    output reg [9:0] VN1_addr_rd_02_00=10'd1023,
    output reg [9:0] VN1_addr_rd_02_01=10'd511,
    //VN读地址，H阵第２行
    output reg [8:0] VN2_addr_rd_01_00=9'd511,
    output reg [8:0] VN2_addr_rd_02_00=9'd511,
    output reg [8:0] VN2_addr_rd_03_00=9'd511,
    output reg [9:0] VN2_addr_rd_04_02=10'd1023,
    output reg [9:0] VN2_addr_rd_04_03=10'd511,
    output reg [8:0] VN2_addr_rd_04_04=9'd511,
	//VN读地址，H阵第３行 
    output reg [8:0] VN3_addr_rd_01_00=9'd511,
    output reg [9:0] VN3_addr_rd_02_05=10'd1023,
    output reg [9:0] VN3_addr_rd_02_06=10'd511,
    output reg [9:0] VN3_addr_rd_03_07=10'd1023,
    output reg [9:0] VN3_addr_rd_03_08=10'd511,
    output reg [8:0] VN3_addr_rd_04_00=9'd511,

    //CN写使能
    output reg [0:0] CN_wea=1'd0,
    
    //CN写地址，H阵第１行
    output reg [8:0] CN1_addr_wr_01_00=9'd511,
    output reg [9:0] CN1_addr_wr_02_00=10'd1023,
    output reg [9:0] CN1_addr_wr_02_01=10'd511,
    
    //CN写地址，H阵第２行
    output reg [8:0] CN2_addr_wr_01_00=9'd511,
    output reg [8:0] CN2_addr_wr_02_00=9'd511,
    output reg [8:0] CN2_addr_wr_03_00=9'd511,
    output reg [9:0] CN2_addr_wr_04_02=10'd1023,
    output reg [9:0] CN2_addr_wr_04_03=10'd511,
    output reg [8:0] CN2_addr_wr_04_04=9'd511,

    //CN写地址，H阵第３行
    output reg [8:0] CN3_addr_wr_01_00=9'd511,
    output reg [9:0] CN3_addr_wr_02_05=10'd1023,
    output reg [9:0] CN3_addr_wr_02_06=10'd511,
    output reg [9:0] CN3_addr_wr_03_07=10'd1023,
    output reg [9:0] CN3_addr_wr_03_08=10'd511,
    output reg [8:0] CN3_addr_wr_04_00=9'd511,


    //CN写数据，H阵第１行
    output reg  [WIDTH-1:0] CN1_din_01_00=8'd0,
    output reg  [WIDTH-1:0] CN1_din_02_00=8'd0,
    output reg  [WIDTH-1:0] CN1_din_02_01=8'd0,
    
    //CN写数据，H阵第２行
    output reg  [WIDTH-1:0] CN2_din_01_00=8'd0,
    output reg  [WIDTH-1:0] CN2_din_02_00=8'd0,
    output reg  [WIDTH-1:0] CN2_din_03_00=8'd0,
    output reg  [WIDTH-1:0] CN2_din_04_02=8'd0,
    output reg  [WIDTH-1:0] CN2_din_04_03=8'd0,
    output reg  [WIDTH-1:0] CN2_din_04_04=8'd0,

    //CN写数据，H阵第３行
    output reg  [WIDTH-1:0] CN3_din_01_00=8'd0,
    output reg  [WIDTH-1:0] CN3_din_02_05=8'd0,
    output reg  [WIDTH-1:0] CN3_din_02_06=8'd0,
    output reg  [WIDTH-1:0] CN3_din_03_07=8'd0,
    output reg  [WIDTH-1:0] CN3_din_03_08=8'd0,
    output reg  [WIDTH-1:0] CN3_din_04_00=8'd0,
 
    output end_CN               //模块结束标志，高脉冲    
    );
   
    reg [10:0] cnt_CN=11'd0;
    reg flag_CN=1'd0;    
    // 产生该模块的计数基准
    always @ (posedge clk) begin
        if(rst_CN) begin
            cnt_CN  <= 11'd0;
            flag_CN <= 1'b0;
        end else begin
            if(start_CN) begin
                flag_CN <= 1'b1;
                cnt_CN  <= 11'd0;           
            end else begin
                if(flag_CN) begin
                    if(cnt_CN<11'd560)begin
						flag_CN <= flag_CN;
                        cnt_CN <= cnt_CN + 11'd1;
                    end else begin 
                        cnt_CN <= cnt_CN; 
                        flag_CN<= 1'b0;
                    end           
                end else begin
                    cnt_CN <= cnt_CN;
                end
            end         
        end 
    end  
      
    // 对VN地址操作
    always @ (posedge clk) begin
        if (rst_CN) begin
            VN1_addr_rd_01_00 <= 9'd511;
            VN1_addr_rd_02_00 <= 10'd1023;
            VN2_addr_rd_01_00 <= 9'd511;
            VN2_addr_rd_02_00 <= 9'd511;
            VN2_addr_rd_03_00 <= 9'd511;
            VN3_addr_rd_01_00 <= 9'd511;
            VN3_addr_rd_04_00 <= 9'd511;
            
            VN1_addr_rd_02_01 <= 10'd511;
            VN2_addr_rd_04_02 <= 10'd1023;
            VN2_addr_rd_04_03 <= 10'd511;
            VN2_addr_rd_04_04 <= 9'd511;            
            VN3_addr_rd_02_05 <= 10'd1023;
            VN3_addr_rd_02_06 <= 10'd511;
            VN3_addr_rd_03_07 <= 10'd1023;
            VN3_addr_rd_03_08 <= 10'd511;
            
        end else begin
            if (cnt_CN >= 11'd1 && cnt_CN <= 11'd512) begin
                VN1_addr_rd_01_00 <= VN1_addr_rd_01_00 + 9'd1; 
                VN1_addr_rd_02_00 <= VN1_addr_rd_02_00 + 9'd1; 
                VN2_addr_rd_01_00 <= VN2_addr_rd_01_00 + 9'd1; 
                VN2_addr_rd_02_00 <= VN2_addr_rd_02_00 + 9'd1; 
                VN2_addr_rd_03_00 <= VN2_addr_rd_03_00 + 9'd1; 
                VN3_addr_rd_01_00 <= VN3_addr_rd_01_00 + 9'd1; 
                VN3_addr_rd_04_00 <= VN3_addr_rd_04_00 + 9'd1; 
                VN1_addr_rd_02_01 <= VN1_addr_rd_02_01 + 10'd1;
                VN2_addr_rd_04_02 <= VN2_addr_rd_04_02 + 10'd1;
                VN2_addr_rd_04_03 <= VN2_addr_rd_04_03 + 10'd1;
                VN2_addr_rd_04_04 <= VN2_addr_rd_04_04 + 9'd1;          
                VN3_addr_rd_02_05 <= VN3_addr_rd_02_05 + 10'd1;
                VN3_addr_rd_02_06 <= VN3_addr_rd_02_06 + 10'd1;
                VN3_addr_rd_03_07 <= VN3_addr_rd_03_07 + 10'd1;
                VN3_addr_rd_03_08 <= VN3_addr_rd_03_08 + 10'd1;
           end else begin
                VN1_addr_rd_01_00 <= 9'd511;
                VN1_addr_rd_02_00 <= 10'd1023;
                VN2_addr_rd_01_00 <= 9'd511;
                VN2_addr_rd_02_00 <= 9'd511;
                VN2_addr_rd_03_00 <= 9'd511;
                VN3_addr_rd_01_00 <= 9'd511;
                VN3_addr_rd_04_00 <= 9'd511;
                VN1_addr_rd_02_01 <= 10'd511;
                VN2_addr_rd_04_02 <= 10'd1023;
                VN2_addr_rd_04_03 <= 10'd511;
                VN2_addr_rd_04_04 <= 9'd511;            
                VN3_addr_rd_02_05 <= 10'd1023;
                VN3_addr_rd_02_06 <= 10'd511;
                VN3_addr_rd_03_07 <= 10'd1023;
                VN3_addr_rd_03_08 <= 10'd511;
            end
        end   
    end
    
    wire [WIDTH-1:0] din01_VN_RU01;
    wire [WIDTH-1:0] din02_VN_RU01;
    wire [WIDTH-1:0] din03_VN_RU01;
    wire [WIDTH-1:0] dout01_RU01  ;
    wire [WIDTH-1:0] dout02_RU01  ;
    wire [WIDTH-1:0] dout03_RU01  ;
    wire [WIDTH-1:0] din01_VN_RU02;
    wire [WIDTH-1:0] din02_VN_RU02;
    wire [WIDTH-1:0] din03_VN_RU02;
    wire [WIDTH-1:0] din04_VN_RU02;
    wire [WIDTH-1:0] din05_VN_RU02;
    wire [WIDTH-1:0] din06_VN_RU02;
    wire [WIDTH-1:0] dout01_RU02  ;
    wire [WIDTH-1:0] dout02_RU02  ;
    wire [WIDTH-1:0] dout03_RU02  ;
    wire [WIDTH-1:0] dout04_RU02  ;
    wire [WIDTH-1:0] dout05_RU02  ;
    wire [WIDTH-1:0] dout06_RU02  ;
    wire [WIDTH-1:0] din01_VN_RU03;
    wire [WIDTH-1:0] din02_VN_RU03;
    wire [WIDTH-1:0] din03_VN_RU03;
    wire [WIDTH-1:0] din04_VN_RU03;
    wire [WIDTH-1:0] din05_VN_RU03;
    wire [WIDTH-1:0] din06_VN_RU03;
    wire [WIDTH-1:0] dout01_RU03  ;
    wire [WIDTH-1:0] dout02_RU03  ;
    wire [WIDTH-1:0] dout03_RU03  ;
    wire [WIDTH-1:0] dout04_RU03  ;
    wire [WIDTH-1:0] dout05_RU03  ;
    wire [WIDTH-1:0] dout06_RU03  ;
    

    
    CNU_3din #(.WIDTH(WIDTH)) RU_01 (
    .clk(clk), 
    .din01_VN_RU(din01_VN_RU01), 
    .din02_VN_RU(din02_VN_RU01), 
    .din03_VN_RU(din03_VN_RU01), 
    .dout01_RU(dout01_RU01), 
    .dout02_RU(dout02_RU01), 
    .dout03_RU(dout03_RU01)
    );  
      
    CNU_6din #(.WIDTH(WIDTH)) RU_02 (
    .clk(clk), 
    .din01_VN_RU(din01_VN_RU02), 
    .din02_VN_RU(din02_VN_RU02), 
    .din03_VN_RU(din03_VN_RU02), 
    .din04_VN_RU(din04_VN_RU02), 
    .din05_VN_RU(din05_VN_RU02), 
    .din06_VN_RU(din06_VN_RU02), 
    .dout01_RU(dout01_RU02), 
    .dout02_RU(dout02_RU02), 
    .dout03_RU(dout03_RU02), 
    .dout04_RU(dout04_RU02), 
    .dout05_RU(dout05_RU02), 
    .dout06_RU(dout06_RU02)
    );

    CNU_6din #(.WIDTH(WIDTH)) RU_03 (
    .clk(clk), 
    .din01_VN_RU(din01_VN_RU03), 
    .din02_VN_RU(din02_VN_RU03), 
    .din03_VN_RU(din03_VN_RU03), 
    .din04_VN_RU(din04_VN_RU03), 
    .din05_VN_RU(din05_VN_RU03), 
    .din06_VN_RU(din06_VN_RU03), 
    .dout01_RU(dout01_RU03), 
    .dout02_RU(dout02_RU03), 
    .dout03_RU(dout03_RU03), 
    .dout04_RU(dout04_RU03), 
    .dout05_RU(dout05_RU03), 
    .dout06_RU(dout06_RU03)
    );
    // 设置读操作的时延  
    parameter DELAY_RD = 11'd6;     
    // RU模块的输入    
    assign din01_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_01_00 : 8'd0;
    assign din02_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_02_00 : 8'd0;
    assign din03_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_02_01 : 8'd0;
    assign din01_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_01_00 : 8'd0;
    assign din02_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_02_00 : 8'd0;
    assign din03_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_03_00 : 8'd0;
    assign din04_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_02 : 8'd0;
    assign din05_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_03 : 8'd0;
    assign din06_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_04 : 8'd0;
    assign din01_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_01_00 : 8'd0;
    assign din02_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_02_05 : 8'd0;
    assign din03_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_02_06 : 8'd0;
    assign din04_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_03_07 : 8'd0;
    assign din05_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_03_08 : 8'd0;
    assign din06_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_04_00 : 8'd0;
    
    // 设置写操作的时延
    parameter DELAY_WR = 11'd15;
    
    // 控制CN的写使能
    always @ (posedge clk) begin
        if(rst_CN) begin 
            CN_wea <= 1'd0;
        end else begin
            if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR)
                CN_wea <= 1'd1;
            else
                CN_wea <= 1'd0;
        end
    end
    
    // 控制CN存储的写地址
    always @ (posedge clk) begin
        if (rst_CN) begin
            CN1_addr_wr_01_00 <= 9'd511;
            CN1_addr_wr_02_00 <= 10'd1023;
            CN2_addr_wr_01_00 <= 9'd511;
            CN2_addr_wr_02_00 <= 9'd511;
            CN2_addr_wr_03_00 <= 9'd511;
            CN3_addr_wr_01_00 <= 9'd511;
            CN3_addr_wr_04_00 <= 9'd511;
            
            CN1_addr_wr_02_01 <= 10'd511;
            CN2_addr_wr_04_02 <= 10'd1023;
            CN2_addr_wr_04_03 <= 10'd511;
            CN2_addr_wr_04_04 <= 9'd511;            
            CN3_addr_wr_02_05 <= 10'd1023;
            CN3_addr_wr_02_06 <= 10'd511;
            CN3_addr_wr_03_07 <= 10'd1023;
            CN3_addr_wr_03_08 <= 10'd511;
            
        end else begin
            if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR) begin
                CN1_addr_wr_01_00 <= CN1_addr_wr_01_00 + 9'd1; 
                CN1_addr_wr_02_00 <= CN1_addr_wr_02_00 + 9'd1; 
                CN2_addr_wr_01_00 <= CN2_addr_wr_01_00 + 9'd1; 
                CN2_addr_wr_02_00 <= CN2_addr_wr_02_00 + 9'd1; 
                CN2_addr_wr_03_00 <= CN2_addr_wr_03_00 + 9'd1; 
                CN3_addr_wr_01_00 <= CN3_addr_wr_01_00 + 9'd1; 
                CN3_addr_wr_04_00 <= CN3_addr_wr_04_00 + 9'd1; 
                CN1_addr_wr_02_01 <= CN1_addr_wr_02_01 + 10'd1;
                CN2_addr_wr_04_02 <= CN2_addr_wr_04_02 + 10'd1;
                CN2_addr_wr_04_03 <= CN2_addr_wr_04_03 + 10'd1;
                CN2_addr_wr_04_04 <= CN2_addr_wr_04_04 + 9'd1;          
                CN3_addr_wr_02_05 <= CN3_addr_wr_02_05 + 10'd1;
                CN3_addr_wr_02_06 <= CN3_addr_wr_02_06 + 10'd1;
                CN3_addr_wr_03_07 <= CN3_addr_wr_03_07 + 10'd1;
                CN3_addr_wr_03_08 <= CN3_addr_wr_03_08 + 10'd1;
           end else begin
                CN1_addr_wr_01_00 <= 9'd511;
                CN1_addr_wr_02_00 <= 10'd1023;
                CN2_addr_wr_01_00 <= 9'd511;
                CN2_addr_wr_02_00 <= 9'd511;
                CN2_addr_wr_03_00 <= 9'd511;
                CN3_addr_wr_01_00 <= 9'd511;
                CN3_addr_wr_04_00 <= 9'd511;
                CN1_addr_wr_02_01 <= 10'd511;
                CN2_addr_wr_04_02 <= 10'd1023;
                CN2_addr_wr_04_03 <= 10'd511;
                CN2_addr_wr_04_04 <= 9'd511;            
                CN3_addr_wr_02_05 <= 10'd1023;
                CN3_addr_wr_02_06 <= 10'd511;
                CN3_addr_wr_03_07 <= 10'd1023;
                CN3_addr_wr_03_08 <= 10'd511;
            end
        end   
    end  
    
    // 控制CN的写数据
    always @ (posedge clk) begin
        if (rst_CN) begin
            CN1_din_01_00 <= 8'd0;
            CN1_din_02_00 <= 8'd0;
            CN2_din_01_00 <= 8'd0;
            CN2_din_02_00 <= 8'd0;
            CN2_din_03_00 <= 8'd0;
            CN3_din_01_00 <= 8'd0;
            CN3_din_04_00 <= 8'd0;
            CN1_din_02_01 <= 8'd0; 
            CN2_din_04_02 <= 8'd0; 
            CN2_din_04_03 <= 8'd0; 
            CN2_din_04_04 <= 8'd0;            
            CN3_din_02_05 <= 8'd0; 
            CN3_din_02_06 <= 8'd0; 
            CN3_din_03_07 <= 8'd0; 
            CN3_din_03_08 <= 8'd0;
        end else begin 
            if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR) begin
                CN1_din_01_00 <= dout01_RU01; 
                CN1_din_02_00 <= dout02_RU01;
                CN2_din_01_00 <= dout01_RU02;
                CN2_din_02_00 <= dout02_RU02;
                CN2_din_03_00 <= dout03_RU02;
                CN3_din_01_00 <= dout01_RU03;
                CN3_din_04_00 <= dout06_RU03;
                CN1_din_02_01 <= dout03_RU01;
                CN2_din_04_02 <= dout04_RU02;
                CN2_din_04_03 <= dout05_RU02;
                CN2_din_04_04 <= dout06_RU02;          
                CN3_din_02_05 <= dout02_RU03;
                CN3_din_02_06 <= dout03_RU03;
                CN3_din_03_07 <= dout04_RU03;
                CN3_din_03_08 <= dout05_RU03;
            end else begin
                CN1_din_01_00 <= 8'd0;
                CN1_din_02_00 <= 8'd0;
                CN2_din_01_00 <= 8'd0;
                CN2_din_02_00 <= 8'd0;
                CN2_din_03_00 <= 8'd0;
                CN3_din_01_00 <= 8'd0;
                CN3_din_04_00 <= 8'd0;
                CN1_din_02_01 <= 8'd0; 
                CN2_din_04_02 <= 8'd0; 
                CN2_din_04_03 <= 8'd0; 
                CN2_din_04_04 <= 8'd0;            
                CN3_din_02_05 <= 8'd0; 
                CN3_din_02_06 <= 8'd0; 
                CN3_din_03_07 <= 8'd0; 
                CN3_din_03_08 <= 8'd0; 
            end
        end
    end
    
    //状态指示
    assign end_CN = (cnt_CN == 11'd512 + DELAY_WR + 11'd2) ? 1'd1 : 1'd0;
endmodule