`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/12/20 15:37:19
// Design Name: 
// Module Name: Noise_Estimate
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Noise_Estimate(
	input 				clk,
	input 				rst,

	input				nd_pilot2,
	input		[9:0]	pilot_noisei,
	input		[9:0]	pilot_noiseq,
	
	output	reg			nd_EstNoise = 1'd0,
	output	reg	[27:0]	EstNoise_i = 28'd0,
	output	reg	[27:0]	EstNoise_q = 28'd0	//应当为0
	
    );
	
	//----------------------------------------共轭相乘，延时为6clk-----------------------------------//
	reg	[9:0]	noisei = 10'd0;
	reg	[9:0]	noiseq = 10'd0;
	reg	[9:0]	noiseqh = 10'd0;
	reg			nd_noise_d0 = 1'd0;
	reg			nd_noise_d1 = 1'd0;
	reg			nd_noise_d2 = 1'd0;
	reg			nd_noise_d3 = 1'd0;
	reg			nd_noise_d4 = 1'd0;
	reg			nd_noise_d5 = 1'd0;
	reg			nd_noise_d6 = 1'd0;
	always @(posedge clk)begin
		if(rst)begin
			noisei		<= 10'd0;
			noiseq		<= 10'd0;
			noiseqh		<= 10'd0;
			nd_noise_d0	<= 1'd0;
			nd_noise_d1	<= 1'd0;
			nd_noise_d2	<= 1'd0;
			nd_noise_d3	<= 1'd0;
			nd_noise_d4	<= 1'd0;
			nd_noise_d5	<= 1'd0;
			nd_noise_d6	<= 1'd0;
		end
		else begin
			noisei		<= pilot_noisei;
			noiseq		<= pilot_noiseq;
			if(pilot_noiseq==10'd512)	noiseqh <= 10'd511;
			else						noiseqh <= -pilot_noiseq;
			nd_noise_d0	<= nd_pilot2;
			nd_noise_d1	<= nd_noise_d0;
			nd_noise_d2	<= nd_noise_d1;
			nd_noise_d3	<= nd_noise_d2;
			nd_noise_d4	<= nd_noise_d3;
			nd_noise_d5	<= nd_noise_d4;
			nd_noise_d6	<= nd_noise_d5;
		end
	end
	
	
	wire		m_axis_dout_tvalid;
	wire [47:0] m_axis_dout_tdata;
	ComMul_EstNoise ComMul_EstNoise (
	  .aclk					(clk),                              // input wire aclk
	  .s_axis_a_tvalid		(1'd1),        						// input wire s_axis_a_tvalid
	  .s_axis_a_tdata		({6'd0,noiseq,6'd0,noisei}),          // input wire [31 : 0] s_axis_a_tdata
	  .s_axis_b_tvalid		(1'd1),        						// input wire s_axis_b_tvalid
	  .s_axis_b_tdata		({6'd0,noiseqh,6'd0,noisei}),          // input wire [31 : 0] s_axis_b_tdata
	  .m_axis_dout_tvalid	(m_axis_dout_tvalid),  // output wire m_axis_dout_tvalid
	  .m_axis_dout_tdata	(m_axis_dout_tdata)    // output wire [47 : 0] m_axis_dout_tdata
	);

	wire	[19:0]	ComMul_Noisei;
	wire	[19:0]	ComMul_Noiseq;

	assign ComMul_Noiseq = m_axis_dout_tdata[43:24];
	assign ComMul_Noisei = m_axis_dout_tdata[19:0];
	
	
	//--------------------------------------------累加求和，状态机控制----------------------------------------//
	reg 		state_noise = 1'd0;
	reg [27:0]	add_Noisei = 28'd0;
	reg [27:0]	add_Noiseq = 28'd0;
	
	always @(posedge clk)begin
		if(rst)begin
			add_Noisei	<= 28'd0;
			add_Noiseq	<= 28'd0;
			nd_EstNoise	<= 1'd0;
			EstNoise_i	<= 28'd0;
			EstNoise_q	<= 28'd0;			
			state_noise	<= 1'd0;		
		end
		else begin
			case(state_noise)
			//帧间复位结束后，等待nd_noise_d6拉高，拉高持续256clk，期间数据全部累加
			//nd_noise_d6拉低说明256clk的累加结束，给一次噪声估计结果，伴随nd
			1'd0:begin
				if(nd_noise_d6) begin
					add_Noisei	<= {{8{ComMul_Noisei[19]}},ComMul_Noisei};
					add_Noiseq	<= {{8{ComMul_Noiseq[19]}},ComMul_Noiseq};
					nd_EstNoise	<= 1'd0;
					EstNoise_i	<= EstNoise_i;
					EstNoise_q	<= EstNoise_q;			
					state_noise	<= state_noise + 1'd1;		
				end
				else begin
					add_Noisei	<= 28'd0;
					add_Noiseq	<= 28'd0;
					nd_EstNoise	<= 1'd0;
					EstNoise_i	<= EstNoise_i;
					EstNoise_q	<= EstNoise_q;			
					state_noise	<= state_noise;
				end
			end
			1'd1:begin
				if(nd_noise_d6==1'd0) begin
					add_Noisei	<= add_Noisei;
					add_Noiseq	<= add_Noiseq;
					nd_EstNoise	<= 1'd1;
					EstNoise_i	<= add_Noisei;
					EstNoise_q	<= add_Noiseq;			
					state_noise	<= 1'd0;		
				end
				else begin
					add_Noisei	<= add_Noisei + {{8{ComMul_Noisei[19]}},ComMul_Noisei};
					add_Noiseq	<= add_Noiseq + {{8{ComMul_Noiseq[19]}},ComMul_Noiseq};
					nd_EstNoise	<= 1'd0;
					EstNoise_i	<= EstNoise_i;
					EstNoise_q	<= EstNoise_q;			
					state_noise	<= state_noise;
				end
				
			end
			endcase
		end
	end
	
	
	//----------------------------------------除data_length=256，再乘2-----------------------------------//
	//----------------------------------------除49，再除2-----------------------------------//
	//根据量化方案，此处不再做除法，相当于噪声估计结果放大了256*49倍
	//FullSystem_v5.m
	
	// integer	handle01;
	// integer	handle02;
	// integer	handle03;
	// integer	handle04;

	// reg enable1 = 0;
	// initial begin
		// handle01=$fopen("ComMul_Noisei.txt","w"); $fclose(handle01);
		// handle02=$fopen("ComMul_Noiseq.txt","w"); $fclose(handle02);
	
	
   
		// #10;
		// enable1 = 1;
	// end

	// always@(posedge clk)begin
		// if(enable1)begin		
			// if(nd_noise_d6)begin		
				// handle01=$fopen("ComMul_Noisei.txt","a+");$fwrite(handle01,"%d\n",$signed(ComMul_Noisei));$fclose(handle01);
				// handle02=$fopen("ComMul_Noiseq.txt","a+");$fwrite(handle02,"%d\n",$signed(ComMul_Noiseq));$fclose(handle02);
			// end
		// end
	// end
	
	
endmodule